[PATCH 0/5] ARM: DT: tegra114: Add DT entry for different controller

[PATCH 0/5] ARM: DT: tegra114: Add DT entry for different controller

[Laxman Dewangan]

This patch series add DT entry for APB DMA, I2C, UART, KBC and SPI.

This patch series is generated on top of CCF work for T114 done by Peter
and hence it should be applied on top of T114 CCF patches.

Laxman Dewangan (5):
  ARM: DT: tegra114: add APB DMA controller DT entry
  ARM: DT: tegra114: Add i2c controller DT entry
  ARM: DT: tegra114:add aliases and DMA requestor for serial controller
  ARM: DT: tegra114: add KBC controller DT entry
  ARM: DT: tegra114: Add spi controller DT entry

 arch/arm/boot/dts/tegra114.dtsi |  202 ++++++++++++++++++++++++++++++++++++++-
 1 files changed, 197 insertions(+), 5 deletions(-)

[PATCH 1/5] ARM: DT: tegra114: add APB DMA controller DT entry

[Laxman Dewangan]

NVIDIA's Tegra114 has 32 channels APB DMA controller. Add DT entry for
APB DMA controllers and make it compatible with "nvidia,tegra114-apbdma".

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
 arch/arm/boot/dts/tegra114.dtsi |   38 ++++++++++++++++++++++++++++++++++++++
 1 files changed, 38 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 0eec49f..b73b8a6 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -38,6 +38,44 @@
 		reg = <0x6000c004 0x14c>;
 	};
 
+	apbdma: dma {
+		compatible = "nvidia,tegra114-apbdma";
+		reg = <0x6000a000 0x1400>;
+		interrupts = <0 104 0x04
+			      0 105 0x04
+			      0 106 0x04
+			      0 107 0x04
+			      0 108 0x04
+			      0 109 0x04
+			      0 110 0x04
+			      0 111 0x04
+			      0 112 0x04
+			      0 113 0x04
+			      0 114 0x04
+			      0 115 0x04
+			      0 116 0x04
+			      0 117 0x04
+			      0 118 0x04
+			      0 119 0x04
+			      0 128 0x04
+			      0 129 0x04
+			      0 130 0x04
+			      0 131 0x04
+			      0 132 0x04
+			      0 133 0x04
+			      0 134 0x04
+			      0 135 0x04
+			      0 136 0x04
+			      0 137 0x04
+			      0 138 0x04
+			      0 139 0x04
+			      0 140 0x04
+			      0 141 0x04
+			      0 142 0x04
+			      0 143 0x04>;
+		clocks = <&tegra_car 34>;
+	};
+
 	gpio: gpio {
 		compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
 		reg = <0x6000d000 0x1000>;
-- 
1.7.1.1

[PATCH 2/5] ARM: DT: tegra114: Add i2c controller DT entry

[Laxman Dewangan]

NVIDIA's Tegra114 has 5 i2c controllers. These controllers have
additional feature/configurations to make it functional over
Tegra30's i2c controller driver.

Add DT entry for i2c controllers and make it compatible with
"nvidia,tegra114-i2c".

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
 arch/arm/boot/dts/tegra114.dtsi |   55 +++++++++++++++++++++++++++++++++++++++
 1 files changed, 55 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index b73b8a6..14afbc8 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -135,6 +135,61 @@
 		clocks = <&tegra_car 65>;
 	};
 
+	i2c@7000c000 {
+		compatible = "nvidia,tegra114-i2c";
+		reg = <0x7000c000 0x100>;
+		interrupts = <0 38 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		clocks = <&tegra_car 12>;
+		clock-names = "div-clk";
+	};
+
+	i2c@7000c400 {
+		compatible = "nvidia,tegra114-i2c";
+		reg = <0x7000c400 0x100>;
+		interrupts = <0 84 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		clocks = <&tegra_car 54>;
+		clock-names = "div-clk";
+	};
+
+	i2c@7000c500 {
+		compatible = "nvidia,tegra114-i2c";
+		reg = <0x7000c500 0x100>;
+		interrupts = <0 92 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		clocks = <&tegra_car 67>;
+		clock-names = "div-clk";
+	};
+
+	i2c@7000c700 {
+		compatible = "nvidia,tegra114-i2c";
+		reg = <0x7000c700 0x100>;
+		interrupts = <0 120 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		clocks = <&tegra_car 103>;
+		clock-names = "div-clk";
+	};
+
+	i2c@7000d000 {
+		compatible = "nvidia,tegra114-i2c";
+		reg = <0x7000d000 0x100>;
+		interrupts = <0 53 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		clocks = <&tegra_car 47>;
+		clock-names = "div-clk";
+	};
+
 	sdhci@78000000 {
 		compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 		reg = <0x78000000 0x200>;
-- 
1.7.1.1

[PATCH 3/5] ARM: DT: tegra114:add aliases and DMA requestor for serial controller

[Laxman Dewangan]

Add APB DMA requestor and serial aliases for serial controller.
There will be two serial driver i.e. 8250 based simple serial driver
and APB DMA based serial driver for higher baudrate and performace.

The simple serial driver get enabled with compatible nvidia,tegra20-uart
and APB DMA based driver will get enabled with compatible
nvidia,tegra30-hsuart.

Also Fix the clock id for the UARTB.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
 arch/arm/boot/dts/tegra114.dtsi |   29 ++++++++++++++++++++++++-----
 1 files changed, 24 insertions(+), 5 deletions(-)

diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 14afbc8..686e33f 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -4,6 +4,13 @@
 	compatible = "nvidia,tegra114";
 	interrupt-parent = <&gic>;
 
+	aliases {
+		serial0 = &uarta;
+		serial1 = &uartb;
+		serial2 = &uartc;
+		serial3 = &uartd;
+	};
+
 	gic: interrupt-controller {
 		compatible = "arm,cortex-a15-gic";
 		#interrupt-cells = <3>;
@@ -99,38 +106,50 @@
 		       0x70003000 0x40c>;	/* Mux registers */
 	};
 
-	serial@70006000 {
+	/*
+	 * There are two serial driver i.e. 8250 based simple serial
+	 * driver and APB DMA based serial driver for higher baudrate
+	 * and performace. To enable the 8250 based driver, the compatible
+	 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
+	 * the APB DMA based serial driver, the comptible is
+	 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
+	 */
+	uarta: serial@70006000 {
 		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 		reg = <0x70006000 0x40>;
 		reg-shift = <2>;
 		interrupts = <0 36 0x04>;
+		nvidia,dma-request-selector = <&apbdma 8>;
 		status = "disabled";
 		clocks = <&tegra_car 6>;
 	};
 
-	serial@70006040 {
+	uartb: serial@70006040 {
 		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 		reg = <0x70006040 0x40>;
 		reg-shift = <2>;
 		interrupts = <0 37 0x04>;
+		nvidia,dma-request-selector = <&apbdma 9>;
 		status = "disabled";
-		clocks = <&tegra_car 192>;
+		clocks = <&tegra_car 7>;
 	};
 
-	serial@70006200 {
+	uartc: serial@70006200 {
 		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 		reg = <0x70006200 0x100>;
 		reg-shift = <2>;
 		interrupts = <0 46 0x04>;
+		nvidia,dma-request-selector = <&apbdma 10>;
 		status = "disabled";
 		clocks = <&tegra_car 55>;
 	};
 
-	serial@70006300 {
+	uartd: serial@70006300 {
 		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 		reg = <0x70006300 0x100>;
 		reg-shift = <2>;
 		interrupts = <0 90 0x04>;
+		nvidia,dma-request-selector = <&apbdma 19>;
 		status = "disabled";
 		clocks = <&tegra_car 65>;
 	};
-- 
1.7.1.1

[PATCH 4/5] ARM: DT: tegra114: add KBC controller DT entry

[Laxman Dewangan]

NVIDIA's Tegra114 SoCs have the matrix keyboard controller which
supports 11x8 type of matrix. The number of rows and columns
are configurable.

Add DT entry for KBC controller.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
 arch/arm/boot/dts/tegra114.dtsi |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 686e33f..18fbd49 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -248,6 +248,14 @@
 		clocks = <&tegra_car 4>;
 	};
 
+	kbc {
+		compatible = "nvidia,tegra20-kbc";
+		reg = <0x7000e200 0x100>;
+		interrupts = <0 85 0x04>;
+		clocks = <&tegra_car 36>;
+		status = "disabled";
+	};
+
 	pmc {
 		compatible = "nvidia,tegra114-pmc";
 		reg = <0x7000e400 0x400>;
-- 
1.7.1.1

[PATCH 5/5] ARM: DT: tegra114: Add spi controller DT entry

[Laxman Dewangan]

NVIDIA's Tegra114 has 6 spi controllers. These controllers are
redesign on T114 with different register interface.

Add DT entry for spi controllers and make it compatible with
"nvidia,tegra114-spi".

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
 arch/arm/boot/dts/tegra114.dtsi |   72 +++++++++++++++++++++++++++++++++++++++
 1 files changed, 72 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 18fbd49..5f5c403 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -209,6 +209,78 @@
 		clock-names = "div-clk";
 	};
 
+	spi@7000d400 {
+		compatible = "nvidia,tegra114-spi";
+		reg = <0x7000d400 0x200>;
+		interrupts = <0 59 0x04>;
+		nvidia,dma-request-selector = <&apbdma 15>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 41>;
+		clock-names = "spi";
+		status = "disabled";
+	};
+
+	spi@7000d600 {
+		compatible = "nvidia,tegra114-spi";
+		reg = <0x7000d600 0x200>;
+		interrupts = <0 82 0x04>;
+		nvidia,dma-request-selector = <&apbdma 16>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 44>;
+		clock-names = "spi";
+		status = "disabled";
+	};
+
+	spi@7000d800 {
+		compatible = "nvidia,tegra114-spi";
+		reg = <0x7000d480 0x200>;
+		interrupts = <0 83 0x04>;
+		nvidia,dma-request-selector = <&apbdma 17>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 46>;
+		clock-names = "spi";
+		status = "disabled";
+	};
+
+	spi@7000da00 {
+		compatible = "nvidia,tegra114-spi";
+		reg = <0x7000da00 0x200>;
+		interrupts = <0 93 0x04>;
+		nvidia,dma-request-selector = <&apbdma 18>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 68>;
+		clock-names = "spi";
+		status = "disabled";
+	};
+
+	spi@7000dc00 {
+		compatible = "nvidia,tegra114-spi";
+		reg = <0x7000dc00 0x200>;
+		interrupts = <0 94 0x04>;
+		nvidia,dma-request-selector = <&apbdma 27>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 104>;
+		clock-names = "spi";
+		status = "disabled";
+	};
+
+	spi@7000de00 {
+		compatible = "nvidia,tegra114-spi";
+		reg = <0x7000de00 0x200>;
+		interrupts = <0 79 0x04>;
+		nvidia,dma-request-selector = <&apbdma 28>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 105>;
+		clock-names = "spi";
+		status = "disabled";
+	};
+
 	sdhci@78000000 {
 		compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 		reg = <0x78000000 0x200>;
-- 
1.7.1.1

Re: [PATCH 1/5] ARM: DT: tegra114: add APB DMA controller DT entry

[Stephen Warren]

On 03/08/2013 06:52 AM, Laxman Dewangan wrote:
> NVIDIA's Tegra114 has 32 channels APB DMA controller. Add DT entry for
> APB DMA controllers and make it compatible with "nvidia,tegra114-apbdma".

> diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi

> +	apbdma: dma {
> +		compatible = "nvidia,tegra114-apbdma";

So I know that the Tegra114 HW has a new channel-pause feature, which
the driver /can/ use. However, if the driver didn't know about that
feature, and continued to use the global-pause feature, would it still
work fine?

In other words, is the Tegra114 HW 100% backwards-compatible with the
Tegra30 HW, it's just that there are new features that SW could
optionally use?

If that is true, then we should also include "nvidia,tegra30-apbdma" in
the compatible value.

Re: [PATCH 3/5] ARM: DT: tegra114:add aliases and DMA requestor for serial controller

[Stephen Warren]

On 03/08/2013 06:53 AM, Laxman Dewangan wrote:
> Add APB DMA requestor and serial aliases for serial controller.
> There will be two serial driver i.e. 8250 based simple serial driver
> and APB DMA based serial driver for higher baudrate and performace.
> 
> The simple serial driver get enabled with compatible nvidia,tegra20-uart
> and APB DMA based driver will get enabled with compatible
> nvidia,tegra30-hsuart.
> 
> Also Fix the clock id for the UARTB.

If you feel like saying "also", that should probably be a separate patch!

In this case, if the UARTB clock ID actually should be changed, then the
fix should be rolled into Peter's Tegra114 clock series, since it adds
the property you're changing here, and his series hasn't yet been applied.

But, as I mentioned in my previous email, I don't believe the UARTB
clock ID change is correct.

> diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi

> +	/*
> +	 * There are two serial driver i.e. 8250 based simple serial
> +	 * driver and APB DMA based serial driver for higher baudrate
> +	 * and performace. To enable the 8250 based driver, the compatible
> +	 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
> +	 * the APB DMA based serial driver, the comptible is
> +	 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
> +	 */

Any references to Tegra30 there should be changed to Tegra114 I think.

Re: [PATCH 4/5] ARM: DT: tegra114: add KBC controller DT entry

[Stephen Warren]

On 03/08/2013 06:53 AM, Laxman Dewangan wrote:
> NVIDIA's Tegra114 SoCs have the matrix keyboard controller which
> supports 11x8 type of matrix. The number of rows and columns
> are configurable.

Earlier Tegra versions supported up to a 16x8 matrix. This feeds into
the following defines in the driver:

#define KBC_MAX_GPIO    24
#define KBC_MAX_ROW     16
#define KBC_MAX_COL     8
#define KBC_MAX_KEY     (KBC_MAX_ROW * KBC_MAX_COL)

Given Tegra114 supports /fewer/ pins and rows than earlier chips, I
think that makes the HW technically incompatible, since GPIO IDs 19..23
are invalid in this HW but valid earlier.

Now in practice I suppose that with a correct DT keyboard map for a
Tegra114 device, those extra invalid GPIOs would never be referenced, so
this is a little nit-picky, but I still feel we should fix this.

So, I'd like to see the KBC driver updated to derive the values for all
the defines I listed above from the compatible value.

Technically, tegra114.dtsi should not pretend that the Tegra114 KBC is
compatible with previous generations either.

> diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi

> +	kbc {
> +		compatible = "nvidia,tegra20-kbc";

Ignoring any of the discussion above, i.e. even if the HW was 100%
identical, we should still include a Tegra114 entry in the compatible
property (compatible = "nvidia,tegra114-kbc", "nvidia,tegra20-kbc"), so
that if Tegra114-specific bugs were found in the future, any device
trees would already indicate that they describe Tegra114 HW, so the SW
could key off that to enable the workaround.

Re-stated: The rules for compatible are: Always include the exact HW
name, then optionally include any other HW names it's compatible with.

Re: [PATCH 3/5] ARM: DT: tegra114:add aliases and DMA requestor for serial controller

[Laxman Dewangan]

On Friday 08 March 2013 11:24 PM, Stephen Warren wrote:
> On 03/08/2013 06:53 AM, Laxman Dewangan wrote:
>> Add APB DMA requestor and serial aliases for serial controller.
>> There will be two serial driver i.e. 8250 based simple serial driver
>> and APB DMA based serial driver for higher baudrate and performace.
>>
>> The simple serial driver get enabled with compatible nvidia,tegra20-uart
>> and APB DMA based driver will get enabled with compatible
>> nvidia,tegra30-hsuart.
>>
>> Also Fix the clock id for the UARTB.
> If you feel like saying "also", that should probably be a separate patch!

I will remove "also ..." as I did not see the Documetation part. I think 
it is correct as per Dcoument.

>> diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
>> +	/*
>> +	 * There are two serial driver i.e. 8250 based simple serial
>> +	 * driver and APB DMA based serial driver for higher baudrate
>> +	 * and performace. To enable the 8250 based driver, the compatible
>> +	 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
>> +	 * the APB DMA based serial driver, the comptible is
>> +	 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
>> +	 */
> Any references to Tegra30 there should be changed to Tegra114 I think.

Ok, there is not change on tegra30 and Tegra114, also we have not added 
the tegra114 compatible in driver file.

Re: [PATCH 1/5] ARM: DT: tegra114: add APB DMA controller DT entry

[Laxman Dewangan]

On Friday 08 March 2013 11:21 PM, Stephen Warren wrote:
> On 03/08/2013 06:52 AM, Laxman Dewangan wrote:
>> NVIDIA's Tegra114 has 32 channels APB DMA controller. Add DT entry for
>> APB DMA controllers and make it compatible with "nvidia,tegra114-apbdma".
>> diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
>> +	apbdma: dma {
>> +		compatible = "nvidia,tegra114-apbdma";
> So I know that the Tegra114 HW has a new channel-pause feature, which
> the driver /can/ use. However, if the driver didn't know about that
> feature, and continued to use the global-pause feature, would it still
> work fine?
>
> In other words, is the Tegra114 HW 100% backwards-compatible with the
> Tegra30 HW, it's just that there are new features that SW could
> optionally use?
>
> If that is true, then we should also include "nvidia,tegra30-apbdma" in
> the compatible value.

Tegra114 HW is not compatible with the tegra30 as with global pause, it 
is not able to write into the dma register in T114. On t114, the dma 
register is clock gated with global enable/disable.

Re: [PATCH 4/5] ARM: DT: tegra114: add KBC controller DT entry

[Laxman Dewangan]

On Friday 08 March 2013 11:34 PM, Stephen Warren wrote:
> On 03/08/2013 06:53 AM, Laxman Dewangan wrote:
>> NVIDIA's Tegra114 SoCs have the matrix keyboard controller which
>> supports 11x8 type of matrix. The number of rows and columns
>> are configurable.
> Earlier Tegra versions supported up to a 16x8 matrix. This feeds into
> the following defines in the driver:
>
> #define KBC_MAX_GPIO    24
> #define KBC_MAX_ROW     16
> #define KBC_MAX_COL     8
> #define KBC_MAX_KEY     (KBC_MAX_ROW * KBC_MAX_COL)
>
> Given Tegra114 supports /fewer/ pins and rows than earlier chips, I
> think that makes the HW technically incompatible, since GPIO IDs 19..23
> are invalid in this HW but valid earlier.
>
> Now in practice I suppose that with a correct DT keyboard map for a
> Tegra114 device, those extra invalid GPIOs would never be referenced, so
> this is a little nit-picky, but I still feel we should fix this.

Where do we fix this? In binding document?

>
> So, I'd like to see the KBC driver updated to derive the values for all
> the defines I listed above from the compatible value.

Ok, we can update the kbc driver to derive above param from compatible.

>
>
>
> Re-stated: The rules for compatible are: Always include the exact HW
> name, then optionally include any other HW names it's compatible with.

OK, will update this in next version of patch.
>

Re: [PATCH 3/5] ARM: DT: tegra114:add aliases and DMA requestor for serial controller

[Stephen Warren]

On 03/08/2013 11:04 AM, Laxman Dewangan wrote:
> On Friday 08 March 2013 11:24 PM, Stephen Warren wrote:
>> On 03/08/2013 06:53 AM, Laxman Dewangan wrote:
>>> Add APB DMA requestor and serial aliases for serial controller.
>>> There will be two serial driver i.e. 8250 based simple serial driver
>>> and APB DMA based serial driver for higher baudrate and performace.
>>>
>>> The simple serial driver get enabled with compatible nvidia,tegra20-uart
>>> and APB DMA based driver will get enabled with compatible
>>> nvidia,tegra30-hsuart.

>>> diff --git a/arch/arm/boot/dts/tegra114.dtsi
>>> b/arch/arm/boot/dts/tegra114.dtsi
>>> +    /*
>>> +     * There are two serial driver i.e. 8250 based simple serial
>>> +     * driver and APB DMA based serial driver for higher baudrate
>>> +     * and performace. To enable the 8250 based driver, the compatible
>>> +     * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
>>> +     * the APB DMA based serial driver, the comptible is
>>> +     * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
>>> +     */
>> Any references to Tegra30 there should be changed to Tegra114 I think.
> 
> Ok, there is not change on tegra30 and Tegra114, also we have not added
> the tegra114 compatible in driver file.

As I mentioned elsewhere, compatible must always include the most
specific value; nvidia,tegra114-uart in this case. If the HW is
backwards-compatible, then also include entries for the HW it's
compatible with.

Hence here, you want:

compatible = "nvidia,tegra114-uart", "nvdia,tegra20-uart";

Since the compatible value here shouldn't include any Tegra30-related
value, the comment shouldn't say that it should.

Note that when there are multiple values in the compatible property,
even if the driver doesn't know about the first value, it will still get
matched based upon the 2nd/3rd/... value, so even though the driver
doesn't explicitly know about nvidia,tegra114-uart, it will still get
instantiated, because it does support nvdia,tegra20-uart.

Re: [PATCH 1/5] ARM: DT: tegra114: add APB DMA controller DT entry

[Stephen Warren]

On 03/08/2013 11:06 AM, Laxman Dewangan wrote:
> On Friday 08 March 2013 11:21 PM, Stephen Warren wrote:
>> On 03/08/2013 06:52 AM, Laxman Dewangan wrote:
>>> NVIDIA's Tegra114 has 32 channels APB DMA controller. Add DT entry for
>>> APB DMA controllers and make it compatible with
>>> "nvidia,tegra114-apbdma".
>>> diff --git a/arch/arm/boot/dts/tegra114.dtsi
>>> b/arch/arm/boot/dts/tegra114.dtsi
>>> +    apbdma: dma {
>>> +        compatible = "nvidia,tegra114-apbdma";
>> So I know that the Tegra114 HW has a new channel-pause feature, which
>> the driver /can/ use. However, if the driver didn't know about that
>> feature, and continued to use the global-pause feature, would it still
>> work fine?
>>
>> In other words, is the Tegra114 HW 100% backwards-compatible with the
>> Tegra30 HW, it's just that there are new features that SW could
>> optionally use?
>>
>> If that is true, then we should also include "nvidia,tegra30-apbdma" in
>> the compatible value.
> 
> Tegra114 HW is not compatible with the tegra30 as with global pause, it
> is not able to write into the dma register in T114. On t114, the dma
> register is clock gated with global enable/disable.

Interesting. In that case, the compatible value above is entirely
correct. Thanks for the explanation. It might be worth mentioning this
in the commit description.

Re: [PATCH 4/5] ARM: DT: tegra114: add KBC controller DT entry

[Stephen Warren]

On 03/08/2013 11:14 AM, Laxman Dewangan wrote:
> On Friday 08 March 2013 11:34 PM, Stephen Warren wrote:
>> On 03/08/2013 06:53 AM, Laxman Dewangan wrote:
>>> NVIDIA's Tegra114 SoCs have the matrix keyboard controller which
>>> supports 11x8 type of matrix. The number of rows and columns
>>> are configurable.
>> Earlier Tegra versions supported up to a 16x8 matrix. This feeds into
>> the following defines in the driver:
>>
>> #define KBC_MAX_GPIO    24
>> #define KBC_MAX_ROW     16
>> #define KBC_MAX_COL     8
>> #define KBC_MAX_KEY     (KBC_MAX_ROW * KBC_MAX_COL)
>>
>> Given Tegra114 supports /fewer/ pins and rows than earlier chips, I
>> think that makes the HW technically incompatible, since GPIO IDs 19..23
>> are invalid in this HW but valid earlier.
>>
>> Now in practice I suppose that with a correct DT keyboard map for a
>> Tegra114 device, those extra invalid GPIOs would never be referenced, so
>> this is a little nit-picky, but I still feel we should fix this.
> 
> Where do we fix this? In binding document?

In the driver and .dtsi files; the rest of my message was describing how
to fix this.

Re: [PATCH 1/5] ARM: DT: tegra114: add APB DMA controller DT entry

[Laxman Dewangan]

On Saturday 09 March 2013 12:11 AM, Stephen Warren wrote:
> On 03/08/2013 11:06 AM, Laxman Dewangan wrote:
>> On Friday 08 March 2013 11:21 PM, Stephen Warren wrote:
>>> On 03/08/2013 06:52 AM, Laxman Dewangan wrote:
>>>> NVIDIA's Tegra114 has 32 channels APB DMA controller. Add DT entry for
>>>> APB DMA controllers and make it compatible with
>>>> "nvidia,tegra114-apbdma".
>>>> diff --git a/arch/arm/boot/dts/tegra114.dtsi
>>>> b/arch/arm/boot/dts/tegra114.dtsi
>>>> +    apbdma: dma {
>>>> +        compatible = "nvidia,tegra114-apbdma";
>>> So I know that the Tegra114 HW has a new channel-pause feature, which
>>> the driver /can/ use. However, if the driver didn't know about that
>>> feature, and continued to use the global-pause feature, would it still
>>> work fine?
>>>
>>> In other words, is the Tegra114 HW 100% backwards-compatible with the
>>> Tegra30 HW, it's just that there are new features that SW could
>>> optionally use?
>>>
>>> If that is true, then we should also include "nvidia,tegra30-apbdma" in
>>> the compatible value.
>> Tegra114 HW is not compatible with the tegra30 as with global pause, it
>> is not able to write into the dma register in T114. On t114, the dma
>> register is clock gated with global enable/disable.
> Interesting. In that case, the compatible value above is entirely
> correct. Thanks for the explanation. It might be worth mentioning this
> in the commit description.

I can describe here as I am going to respin the patches anyhow.
However, I have already explain this in the driver commit when porting 
for T114.