* [PATCH 1/6] reset: qcom: AOSS (Always on subsystem) reset controller
2018-03-05 9:53 [PATCH 0/6] Add support for remoteproc modem-pil on SDM845 SoCs sibis
@ 2018-03-05 9:53 ` sibis
2018-03-07 21:35 ` Rob Herring
2018-03-05 9:53 ` [PATCH 2/6] dt-bindings: mailbox: Add APCS global binding for SDM845 SoCs sibis
` (4 subsequent siblings)
5 siblings, 1 reply; 16+ messages in thread
From: sibis @ 2018-03-05 9:53 UTC (permalink / raw)
To: bjorn.andersson
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, p.zabel, ohad, mark.rutland, robh+dt, kyan,
sricharan, akdwived, linux-arm-msm
Add reset controller driver for Qualcomm SDM845 SoC to
control reset signals provided by AOSS for Modem, Venus
ADSP, GPU, Camera, Wireless, Display subsystem
Signed-off-by: sibis <sibis@codeaurora.org>
---
.../devicetree/bindings/reset/qcom,aoss-reset.txt | 54 ++++++++
drivers/reset/Kconfig | 10 ++
drivers/reset/Makefile | 1 +
drivers/reset/reset-qcom-aoss.c | 151 +++++++++++++++++++++
include/dt-bindings/reset/qcom,aoss-sdm845.h | 17 +++
5 files changed, 233 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
create mode 100644 drivers/reset/reset-qcom-aoss.c
create mode 100644 include/dt-bindings/reset/qcom,aoss-sdm845.h
diff --git a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
new file mode 100644
index 0000000..5318e14
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
@@ -0,0 +1,54 @@
+Qualcomm AOSS Reset Controller
+======================================
+
+This binding describes a reset-controller found on AOSS (Always on SubSysem)
+for Qualcomm SDM845 SoCs.
+
+Required properties:
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be:
+ "qcom,aoss-reset-sdm845", "syscon"
+
+- reg:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: must specify the base address and size of the
+ syscon device.
+
+
+- #reset-cells:
+ Usage: required
+ Value type: <uint>
+ Definition: must be 1; cell entry represents the reset index.
+
+example:
+
+aoss_reset: qcom,reset-controller@b2e0100 {
+ compatible = "qcom,aoss-reset-sdm845", "syscon";
+ reg = <0xc2b0000 0x20004>;
+ #reset-cells = <1>;
+};
+
+
+Specifying reset lines connected to IP modules
+==============================================
+
+Device nodes that need access to reset lines should
+specify them as a reset phandle in their corresponding node as
+specified in reset.txt.
+
+Example:
+
+ modem-pil@4080000 {
+ ...
+
+ resets = <&aoss_reset AOSS_CC_MSS_RESTART>;
+ reset-names = "mss_restart";
+
+ ...
+ };
+
+For list of all valid reset indicies see
+<dt-bindings/reset/qcom,aoss-sdm845.h>
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 7fc7769..1141733 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -81,6 +81,16 @@ config RESET_PISTACHIO
help
This enables the reset driver for ImgTec Pistachio SoCs.
+config RESET_QCOM_AOSS
+ bool "Qcom AOSS Reset Driver"
+ depends on ARCH_QCOM || COMPILE_TEST
+ select MFD_SYSCON
+ help
+ This enables the AOSS (Always On SubSystem) reset driver
+ for Qualcomm SDM845 SoCs. Say Y if you want to control
+ reset signals provided by AOSS for Modem, Venus, ADSP,
+ GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
+
config RESET_SIMPLE
bool "Simple Reset Controller Driver" if COMPILE_TEST
default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 132c24f..c30044a 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
obj-$(CONFIG_RESET_MESON) += reset-meson.o
obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
+obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
diff --git a/drivers/reset/reset-qcom-aoss.c b/drivers/reset/reset-qcom-aoss.c
new file mode 100644
index 0000000..1f3e3e8
--- /dev/null
+++ b/drivers/reset/reset-qcom-aoss.c
@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/regmap.h>
+#include <linux/of_device.h>
+#include <dt-bindings/reset/qcom,aoss-sdm845.h>
+
+struct qcom_aoss_reset_map {
+ unsigned int reg;
+ u8 bit;
+};
+
+struct qcom_aoss_desc {
+ const struct regmap_config *config;
+ const struct qcom_aoss_reset_map *resets;
+ int delay;
+ size_t num_resets;
+};
+
+struct qcom_aoss_reset_data {
+ struct reset_controller_dev rcdev;
+ struct regmap *regmap;
+ const struct qcom_aoss_desc *desc;
+};
+
+static const struct regmap_config aoss_sdm845_regmap_config = {
+ .name = "aoss-reset",
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x20000,
+ .fast_io = true,
+};
+
+static const struct qcom_aoss_reset_map aoss_sdm845_resets[] = {
+ [AOSS_CC_MSS_RESTART] = { 0x0, 0 },
+ [AOSS_CC_CAMSS_RESTART] = { 0x1000, 0 },
+ [AOSS_CC_VENUS_RESTART] = { 0x2000, 0 },
+ [AOSS_CC_GPU_RESTART] = { 0x3000, 0 },
+ [AOSS_CC_DISPSS_RESTART] = { 0x4000, 0 },
+ [AOSS_CC_WCSS_RESTART] = { 0x10000, 0 },
+ [AOSS_CC_LPASS_RESTART] = { 0x20000, 0 },
+};
+
+static const struct qcom_aoss_desc aoss_sdm845_desc = {
+ .config = &aoss_sdm845_regmap_config,
+ .resets = aoss_sdm845_resets,
+ /* Wait 6 32kHz sleep cycles for reset */
+ .delay = 200,
+ .num_resets = ARRAY_SIZE(aoss_sdm845_resets),
+};
+
+static struct qcom_aoss_reset_data *to_qcom_aoss_reset_data(
+ struct reset_controller_dev *rcdev)
+{
+ return container_of(rcdev, struct qcom_aoss_reset_data, rcdev);
+}
+
+static int qcom_aoss_control_assert(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
+ const struct qcom_aoss_reset_map *map = &data->desc->resets[idx];
+
+ return regmap_update_bits(data->regmap, map->reg,
+ BIT(map->bit), BIT(map->bit));
+}
+
+static int qcom_aoss_control_deassert(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
+ const struct qcom_aoss_reset_map *map = &data->desc->resets[idx];
+
+ return regmap_update_bits(data->regmap, map->reg, BIT(map->bit), 0);
+}
+
+static int qcom_aoss_control_reset(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
+ int ret;
+
+ ret = qcom_aoss_control_assert(rcdev, idx);
+ if (ret)
+ return ret;
+
+ udelay(data->desc->delay);
+
+ return qcom_aoss_control_deassert(rcdev, idx);
+}
+
+static const struct reset_control_ops qcom_aoss_reset_ops = {
+ .reset = qcom_aoss_control_reset,
+ .assert = qcom_aoss_control_assert,
+ .deassert = qcom_aoss_control_deassert,
+};
+
+static int qcom_aoss_reset_probe(struct platform_device *pdev)
+{
+ struct qcom_aoss_reset_data *data;
+ struct device *dev = &pdev->dev;
+ const struct qcom_aoss_desc *desc;
+
+ desc = of_device_get_match_data(dev);
+ if (!desc)
+ return -EINVAL;
+
+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ data->desc = desc;
+ data->regmap = syscon_node_to_regmap(dev->of_node);
+ if (IS_ERR(data->regmap)) {
+ dev_err(dev, "Unable to get aoss-reset regmap");
+ return PTR_ERR(data->regmap);
+ }
+ regmap_attach_dev(dev, data->regmap, desc->config);
+
+ data->rcdev.owner = THIS_MODULE;
+ data->rcdev.ops = &qcom_aoss_reset_ops;
+ data->rcdev.nr_resets = desc->num_resets;
+ data->rcdev.of_node = dev->of_node;
+
+ return devm_reset_controller_register(dev, &data->rcdev);
+}
+
+static const struct of_device_id qcom_aoss_reset_of_match[] = {
+ { .compatible = "qcom,aoss-reset-sdm845", .data = &aoss_sdm845_desc },
+ {}
+};
+
+static struct platform_driver qcom_aoss_reset_driver = {
+ .probe = qcom_aoss_reset_probe,
+ .driver = {
+ .name = "qcom_aoss_reset",
+ .of_match_table = qcom_aoss_reset_of_match,
+ },
+};
+
+builtin_platform_driver(qcom_aoss_reset_driver);
+
+MODULE_DESCRIPTION("Qualcomm AOSS Reset Driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/dt-bindings/reset/qcom,aoss-sdm845.h b/include/dt-bindings/reset/qcom,aoss-sdm845.h
new file mode 100644
index 0000000..e9b38fc
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,aoss-sdm845.h
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_RESET_AOSS_SDM_845_H
+#define _DT_BINDINGS_RESET_AOSS_SDM_845_H
+
+#define AOSS_CC_MSS_RESTART 0
+#define AOSS_CC_CAMSS_RESTART 1
+#define AOSS_CC_VENUS_RESTART 2
+#define AOSS_CC_GPU_RESTART 3
+#define AOSS_CC_DISPSS_RESTART 4
+#define AOSS_CC_WCSS_RESTART 5
+#define AOSS_CC_LPASS_RESTART 6
+
+#endif
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 1/6] reset: qcom: AOSS (Always on subsystem) reset controller
2018-03-05 9:53 ` [PATCH 1/6] reset: qcom: AOSS (Always on subsystem) reset controller sibis
@ 2018-03-07 21:35 ` Rob Herring
2018-03-09 14:55 ` Sibi S
0 siblings, 1 reply; 16+ messages in thread
From: Rob Herring @ 2018-03-07 21:35 UTC (permalink / raw)
To: sibis
Cc: bjorn.andersson, linux-remoteproc, linux-kernel, devicetree,
georgi.djakov, jassisinghbrar, p.zabel, ohad, mark.rutland, kyan,
sricharan, akdwived, linux-arm-msm
On Mon, Mar 05, 2018 at 03:23:28PM +0530, sibis wrote:
> Add reset controller driver for Qualcomm SDM845 SoC to
> control reset signals provided by AOSS for Modem, Venus
> ADSP, GPU, Camera, Wireless, Display subsystem
>
> Signed-off-by: sibis <sibis@codeaurora.org>
Need a full name here.
> ---
> .../devicetree/bindings/reset/qcom,aoss-reset.txt | 54 ++++++++
Separate patch for bindings (with the header) please.
> drivers/reset/Kconfig | 10 ++
> drivers/reset/Makefile | 1 +
> drivers/reset/reset-qcom-aoss.c | 151 +++++++++++++++++++++
> include/dt-bindings/reset/qcom,aoss-sdm845.h | 17 +++
> 5 files changed, 233 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
> create mode 100644 drivers/reset/reset-qcom-aoss.c
> create mode 100644 include/dt-bindings/reset/qcom,aoss-sdm845.h
>
> diff --git a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
> new file mode 100644
> index 0000000..5318e14
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
> @@ -0,0 +1,54 @@
> +Qualcomm AOSS Reset Controller
> +======================================
> +
> +This binding describes a reset-controller found on AOSS (Always on SubSysem)
> +for Qualcomm SDM845 SoCs.
> +
> +Required properties:
> +- compatible:
> + Usage: required
> + Value type: <string>
> + Definition: must be:
> + "qcom,aoss-reset-sdm845", "syscon"
Someone in QCom needs to go fix the order of all your downstream
compatibles or review your bindings before sending upstream. The
standard ordering is <vendor>,<soc>-<block>.
Why syscon? The description is this is just a reset controller.
> +
> +- reg:
> + Usage: required
> + Value type: <prop-encoded-array>
> + Definition: must specify the base address and size of the
> + syscon device.
> +
> +
> +- #reset-cells:
> + Usage: required
> + Value type: <uint>
> + Definition: must be 1; cell entry represents the reset index.
> +
> +example:
> +
> +aoss_reset: qcom,reset-controller@b2e0100 {
> + compatible = "qcom,aoss-reset-sdm845", "syscon";
> + reg = <0xc2b0000 0x20004>;
> + #reset-cells = <1>;
> +};
> +
> +
> +Specifying reset lines connected to IP modules
> +==============================================
> +
> +Device nodes that need access to reset lines should
> +specify them as a reset phandle in their corresponding node as
> +specified in reset.txt.
> +
> +Example:
> +
> + modem-pil@4080000 {
> + ...
> +
> + resets = <&aoss_reset AOSS_CC_MSS_RESTART>;
> + reset-names = "mss_restart";
> +
> + ...
> + };
> +
> +For list of all valid reset indicies see
> +<dt-bindings/reset/qcom,aoss-sdm845.h>
Put this before the example.
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH 1/6] reset: qcom: AOSS (Always on subsystem) reset controller
2018-03-07 21:35 ` Rob Herring
@ 2018-03-09 14:55 ` Sibi S
2018-03-09 21:29 ` Trilok Soni
0 siblings, 1 reply; 16+ messages in thread
From: Sibi S @ 2018-03-09 14:55 UTC (permalink / raw)
To: Rob Herring
Cc: bjorn.andersson, linux-remoteproc, linux-kernel, devicetree,
georgi.djakov, jassisinghbrar, p.zabel, ohad, mark.rutland, kyan,
sricharan, akdwived, linux-arm-msm
Hi Rob,
Thanks for the review, will add the changes in v3 of the patch series
On 03/08/2018 03:05 AM, Rob Herring wrote:
> On Mon, Mar 05, 2018 at 03:23:28PM +0530, sibis wrote:
>> Add reset controller driver for Qualcomm SDM845 SoC to
>> control reset signals provided by AOSS for Modem, Venus
>> ADSP, GPU, Camera, Wireless, Display subsystem
>>
>> Signed-off-by: sibis <sibis@codeaurora.org>
>
> Need a full name here.
>
Will correct it
>> ---
>> .../devicetree/bindings/reset/qcom,aoss-reset.txt | 54 ++++++++
>
> Separate patch for bindings (with the header) please.
>
Will make a separate patch
>> drivers/reset/Kconfig | 10 ++
>> drivers/reset/Makefile | 1 +
>> drivers/reset/reset-qcom-aoss.c | 151 +++++++++++++++++++++
>> include/dt-bindings/reset/qcom,aoss-sdm845.h | 17 +++
>> 5 files changed, 233 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
>> create mode 100644 drivers/reset/reset-qcom-aoss.c
>> create mode 100644 include/dt-bindings/reset/qcom,aoss-sdm845.h
>>
>> diff --git a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
>> new file mode 100644
>> index 0000000..5318e14
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
>> @@ -0,0 +1,54 @@
>> +Qualcomm AOSS Reset Controller
>> +======================================
>> +
>> +This binding describes a reset-controller found on AOSS (Always on SubSysem)
>> +for Qualcomm SDM845 SoCs.
>> +
>> +Required properties:
>> +- compatible:
>> + Usage: required
>> + Value type: <string>
>> + Definition: must be:
>> + "qcom,aoss-reset-sdm845", "syscon"
>
> Someone in QCom needs to go fix the order of all your downstream
> compatibles or review your bindings before sending upstream. The
> standard ordering is <vendor>,<soc>-<block>.
>
Will correct it.
> Why syscon? The description is this is just a reset controller.
>
syscon was needed in the compatible list due to using
syscon_node_to_regmap in the reset driver but I guess
since it is just a reset controller the correct thing to do
be ioremap the reg space and do devm_regmap_init_mmio on it.
Will remove syscon.
>> +
>> +- reg:
>> + Usage: required
>> + Value type: <prop-encoded-array>
>> + Definition: must specify the base address and size of the
>> + syscon device.
>> +
>> +
>> +- #reset-cells:
>> + Usage: required
>> + Value type: <uint>
>> + Definition: must be 1; cell entry represents the reset index.
>> +
>> +example:
>> +
>> +aoss_reset: qcom,reset-controller@b2e0100 {
>> + compatible = "qcom,aoss-reset-sdm845", "syscon";
>> + reg = <0xc2b0000 0x20004>;
>> + #reset-cells = <1>;
>> +};
>> +
>> +
>> +Specifying reset lines connected to IP modules
>> +==============================================
>> +
>> +Device nodes that need access to reset lines should
>> +specify them as a reset phandle in their corresponding node as
>> +specified in reset.txt.
>> +
>> +Example:
>> +
>> + modem-pil@4080000 {
>> + ...
>> +
>> + resets = <&aoss_reset AOSS_CC_MSS_RESTART>;
>> + reset-names = "mss_restart";
>> +
>> + ...
>> + };
>> +
>> +For list of all valid reset indicies see
>> +<dt-bindings/reset/qcom,aoss-sdm845.h>
>
> Put this before the example.
>
ok
> --
> To unsubscribe from this list: send the line "unsubscribe linux-remoteproc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
--
Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc, is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH 1/6] reset: qcom: AOSS (Always on subsystem) reset controller
2018-03-09 14:55 ` Sibi S
@ 2018-03-09 21:29 ` Trilok Soni
2018-03-12 7:01 ` Sibi S
0 siblings, 1 reply; 16+ messages in thread
From: Trilok Soni @ 2018-03-09 21:29 UTC (permalink / raw)
To: Sibi S, Rob Herring
Cc: bjorn.andersson, linux-remoteproc, linux-kernel, devicetree,
georgi.djakov, jassisinghbrar, p.zabel, ohad, mark.rutland, kyan,
sricharan, akdwived, linux-arm-msm
Sibi,
One cosmetic comment below.
On 3/9/2018 6:55 AM, Sibi S wrote:
> +
>>> +This binding describes a reset-controller found on AOSS (Always on
>>> SubSysem)
>>> +for Qualcomm SDM845 SoCs.
S/SubSysem/Subsytem
---Trilok Soni
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/6] reset: qcom: AOSS (Always on subsystem) reset controller
2018-03-09 21:29 ` Trilok Soni
@ 2018-03-12 7:01 ` Sibi S
0 siblings, 0 replies; 16+ messages in thread
From: Sibi S @ 2018-03-12 7:01 UTC (permalink / raw)
To: Trilok Soni, Rob Herring
Cc: bjorn.andersson, linux-remoteproc, linux-kernel, devicetree,
georgi.djakov, jassisinghbrar, p.zabel, ohad, mark.rutland, kyan,
sricharan, akdwived, linux-arm-msm
Hi Trilok,
Thanks for the review. I will include it in the v3 patch series.
On 03/10/2018 02:59 AM, Trilok Soni wrote:
> Sibi,
>
> One cosmetic comment below.
>
> On 3/9/2018 6:55 AM, Sibi S wrote:
>> +
>>>> +This binding describes a reset-controller found on AOSS (Always on
>>>> SubSysem)
>>>> +for Qualcomm SDM845 SoCs.
>
> S/SubSysem/Subsytem
>
Will correct it
> ---Trilok Soni
>
>
>
--
Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc, is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 2/6] dt-bindings: mailbox: Add APCS global binding for SDM845 SoCs
2018-03-05 9:53 [PATCH 0/6] Add support for remoteproc modem-pil on SDM845 SoCs sibis
2018-03-05 9:53 ` [PATCH 1/6] reset: qcom: AOSS (Always on subsystem) reset controller sibis
@ 2018-03-05 9:53 ` sibis
2018-03-07 21:55 ` Rob Herring
2018-03-05 9:53 ` [PATCH 3/6] mailbox: Add support for Qualcomm " sibis
` (3 subsequent siblings)
5 siblings, 1 reply; 16+ messages in thread
From: sibis @ 2018-03-05 9:53 UTC (permalink / raw)
To: bjorn.andersson
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, p.zabel, ohad, mark.rutland, robh+dt, kyan,
sricharan, akdwived, linux-arm-msm
Include SDM845 APCS binding to the list of possible bindings
Signed-off-by: sibis <sibis@codeaurora.org>
---
Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
index 16964f0..a60d2b2 100644
--- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
+++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
@@ -9,7 +9,8 @@ platforms.
Value type: <string>
Definition: must be one of:
"qcom,msm8916-apcs-kpss-global",
- "qcom,msm8996-apcs-hmss-global"
+ "qcom,msm8996-apcs-hmss-global",
+ "qcom,sdm845-apcs-hmss-global"
- reg:
Usage: required
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 2/6] dt-bindings: mailbox: Add APCS global binding for SDM845 SoCs
2018-03-05 9:53 ` [PATCH 2/6] dt-bindings: mailbox: Add APCS global binding for SDM845 SoCs sibis
@ 2018-03-07 21:55 ` Rob Herring
0 siblings, 0 replies; 16+ messages in thread
From: Rob Herring @ 2018-03-07 21:55 UTC (permalink / raw)
To: sibis
Cc: bjorn.andersson, linux-remoteproc, linux-kernel, devicetree,
georgi.djakov, jassisinghbrar, p.zabel, ohad, mark.rutland, kyan,
sricharan, akdwived, linux-arm-msm
On Mon, Mar 05, 2018 at 03:23:29PM +0530, sibis wrote:
> Include SDM845 APCS binding to the list of possible bindings
>
> Signed-off-by: sibis <sibis@codeaurora.org>
Need a full name.
> ---
> Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
> index 16964f0..a60d2b2 100644
> --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
> +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
> @@ -9,7 +9,8 @@ platforms.
> Value type: <string>
> Definition: must be one of:
> "qcom,msm8916-apcs-kpss-global",
> - "qcom,msm8996-apcs-hmss-global"
> + "qcom,msm8996-apcs-hmss-global",
> + "qcom,sdm845-apcs-hmss-global"
Drop the comma so we can have 1 line changes instead of 3 in the
future.
>
> - reg:
> Usage: required
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 3/6] mailbox: Add support for Qualcomm SDM845 SoCs
2018-03-05 9:53 [PATCH 0/6] Add support for remoteproc modem-pil on SDM845 SoCs sibis
2018-03-05 9:53 ` [PATCH 1/6] reset: qcom: AOSS (Always on subsystem) reset controller sibis
2018-03-05 9:53 ` [PATCH 2/6] dt-bindings: mailbox: Add APCS global binding for SDM845 SoCs sibis
@ 2018-03-05 9:53 ` sibis
2018-03-05 9:53 ` [PATCH 4/6] dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845 sibis
` (2 subsequent siblings)
5 siblings, 0 replies; 16+ messages in thread
From: sibis @ 2018-03-05 9:53 UTC (permalink / raw)
To: bjorn.andersson
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, p.zabel, ohad, mark.rutland, robh+dt, kyan,
sricharan, akdwived, linux-arm-msm
Add the corresponding APCS offset for SDM845 SoC
Signed-off-by: sibis <sibis@codeaurora.org>
---
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
index 57bde0d..62d704d 100644
--- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
+++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
@@ -125,6 +125,7 @@ static int qcom_apcs_ipc_remove(struct platform_device *pdev)
static const struct of_device_id qcom_apcs_ipc_of_match[] = {
{ .compatible = "qcom,msm8916-apcs-kpss-global", .data = (void *)8 },
{ .compatible = "qcom,msm8996-apcs-hmss-global", .data = (void *)16 },
+ { .compatible = "qcom,sdm845-apcs-hmss-global", .data = (void *)12 },
{}
};
MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 4/6] dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845
2018-03-05 9:53 [PATCH 0/6] Add support for remoteproc modem-pil on SDM845 SoCs sibis
` (2 preceding siblings ...)
2018-03-05 9:53 ` [PATCH 3/6] mailbox: Add support for Qualcomm " sibis
@ 2018-03-05 9:53 ` sibis
2018-03-07 21:56 ` Rob Herring
2018-03-05 9:53 ` [PATCH 5/6] remoteproc: qcom: Add support for mss remoteproc on SDM845 sibis
2018-03-05 9:53 ` [PATCH 6/6] remoteproc: qcom: Always assert and deassert reset signals in SDM845 sibis
5 siblings, 1 reply; 16+ messages in thread
From: sibis @ 2018-03-05 9:53 UTC (permalink / raw)
To: bjorn.andersson
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, p.zabel, ohad, mark.rutland, robh+dt, kyan,
sricharan, akdwived, linux-arm-msm
Add new compatible string for Qualcomm SDM845 SoCs
Signed-off-by: sibis <sibis@codeaurora.org>
---
Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
index 00d3d58..11907db 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
@@ -9,8 +9,9 @@ on the Qualcomm Hexagon core.
Definition: must be one of:
"qcom,q6v5-pil",
"qcom,msm8916-mss-pil",
- "qcom,msm8974-mss-pil"
- "qcom,msm8996-mss-pil"
+ "qcom,msm8974-mss-pil",
+ "qcom,msm8996-mss-pil",
+ "qcom,sdm845-mss-pil"
- reg:
Usage: required
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 4/6] dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845
2018-03-05 9:53 ` [PATCH 4/6] dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845 sibis
@ 2018-03-07 21:56 ` Rob Herring
0 siblings, 0 replies; 16+ messages in thread
From: Rob Herring @ 2018-03-07 21:56 UTC (permalink / raw)
To: sibis
Cc: bjorn.andersson, linux-remoteproc, linux-kernel, devicetree,
georgi.djakov, jassisinghbrar, p.zabel, ohad, mark.rutland, kyan,
sricharan, akdwived, linux-arm-msm
On Mon, Mar 05, 2018 at 03:23:31PM +0530, sibis wrote:
> Add new compatible string for Qualcomm SDM845 SoCs
>
> Signed-off-by: sibis <sibis@codeaurora.org>
Full name.
> ---
> Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
> index 00d3d58..11907db 100644
> --- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
> +++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
> @@ -9,8 +9,9 @@ on the Qualcomm Hexagon core.
> Definition: must be one of:
> "qcom,q6v5-pil",
> "qcom,msm8916-mss-pil",
> - "qcom,msm8974-mss-pil"
> - "qcom,msm8996-mss-pil"
> + "qcom,msm8974-mss-pil",
> + "qcom,msm8996-mss-pil",
> + "qcom,sdm845-mss-pil"
Drop the comma.
>
> - reg:
> Usage: required
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 5/6] remoteproc: qcom: Add support for mss remoteproc on SDM845
2018-03-05 9:53 [PATCH 0/6] Add support for remoteproc modem-pil on SDM845 SoCs sibis
` (3 preceding siblings ...)
2018-03-05 9:53 ` [PATCH 4/6] dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845 sibis
@ 2018-03-05 9:53 ` sibis
2018-03-05 9:53 ` [PATCH 6/6] remoteproc: qcom: Always assert and deassert reset signals in SDM845 sibis
5 siblings, 0 replies; 16+ messages in thread
From: sibis @ 2018-03-05 9:53 UTC (permalink / raw)
To: bjorn.andersson
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, p.zabel, ohad, mark.rutland, robh+dt, kyan,
sricharan, akdwived, linux-arm-msm
>From SDM845, the Q6SS reset sequence on software side has been
simplified with the introduction of boot FSM which assists in
bringing the Q6 out of reset
Add GLINK subdevice to allow definition of GLINK edge as a
child of modem-pil
Signed-off-by: sibis <sibis@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_pil.c | 65 +++++++++++++++++++++++++++++++++++++-
1 file changed, 64 insertions(+), 1 deletion(-)
diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index b4e5e72..92bf125 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -57,6 +57,8 @@
#define RMB_PMI_META_DATA_REG 0x10
#define RMB_PMI_CODE_START_REG 0x14
#define RMB_PMI_CODE_LENGTH_REG 0x18
+#define RMB_MBA_MSS_STATUS 0x40
+#define RMB_MBA_ALT_RESET 0x44
#define RMB_CMD_META_DATA_READY 0x1
#define RMB_CMD_LOAD_READY 0x2
@@ -104,6 +106,13 @@
#define QDSP6SS_XO_CBCR 0x0038
#define QDSP6SS_ACC_OVERRIDE_VAL 0x20
+/* QDSP6v65 parameters */
+#define QDSP6SS_SLEEP 0x3C
+#define QDSP6SS_BOOT_CORE_START 0x400
+#define QDSP6SS_BOOT_CMD 0x404
+#define SLEEP_CHECK_MAX_LOOPS 200
+#define BOOT_FSM_TIMEOUT 10000
+
struct reg_info {
struct regulator *reg;
int uV;
@@ -166,6 +175,7 @@ struct q6v5 {
void *mpss_region;
size_t mpss_size;
+ struct qcom_rproc_glink glink_subdev;
struct qcom_rproc_subdev smd_subdev;
struct qcom_rproc_ssr ssr_subdev;
bool need_mem_protection;
@@ -178,6 +188,7 @@ enum {
MSS_MSM8916,
MSS_MSM8974,
MSS_MSM8996,
+ MSS_SDM845,
};
static int q6v5_regulator_init(struct device *dev, struct reg_info *regs,
@@ -384,8 +395,35 @@ static int q6v5proc_reset(struct q6v5 *qproc)
int ret;
int i;
+ if (qproc->version == MSS_SDM845) {
- if (qproc->version == MSS_MSM8996) {
+ val = readl(qproc->reg_base + QDSP6SS_SLEEP);
+ val |= 0x1;
+ writel(val, qproc->reg_base + QDSP6SS_SLEEP);
+
+ ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
+ val, !(val & BIT(31)), 1,
+ SLEEP_CHECK_MAX_LOOPS);
+ if (ret) {
+ dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
+ return -ETIMEDOUT;
+ }
+
+ /* De-assert QDSP6 stop core */
+ writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
+ /* Trigger boot FSM */
+ writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
+
+ ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
+ val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
+ if (ret) {
+ dev_err(qproc->dev, "Boot FSM failed to complete.\n");
+ return ret;
+ }
+
+ goto pbl_wait;
+
+ } else if (qproc->version == MSS_MSM8996) {
/* Override the ACC value if required */
writel(QDSP6SS_ACC_OVERRIDE_VAL,
qproc->reg_base + QDSP6SS_STRAP_ACC);
@@ -493,6 +531,7 @@ static int q6v5proc_reset(struct q6v5 *qproc)
val &= ~Q6SS_STOP_CORE;
writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
+pbl_wait:
/* Wait for PBL status */
ret = q6v5_rmb_pbl_wait(qproc, 1000);
if (ret == -ETIMEDOUT) {
@@ -1213,6 +1252,7 @@ static int q6v5_probe(struct platform_device *pdev)
}
qproc->mpss_perm = BIT(QCOM_SCM_VMID_HLOS);
qproc->mba_perm = BIT(QCOM_SCM_VMID_HLOS);
+ qcom_add_glink_subdev(rproc, &qproc->glink_subdev);
qcom_add_smd_subdev(rproc, &qproc->smd_subdev);
qcom_add_ssr_subdev(rproc, &qproc->ssr_subdev, "mpss");
@@ -1234,6 +1274,7 @@ static int q6v5_remove(struct platform_device *pdev)
rproc_del(qproc->rproc);
+ qcom_remove_glink_subdev(qproc->rproc, &qproc->glink_subdev);
qcom_remove_smd_subdev(qproc->rproc, &qproc->smd_subdev);
qcom_remove_ssr_subdev(qproc->rproc, &qproc->ssr_subdev);
rproc_free(qproc->rproc);
@@ -1241,6 +1282,27 @@ static int q6v5_remove(struct platform_device *pdev)
return 0;
}
+static const struct rproc_hexagon_res sdm845_mss = {
+ .hexagon_mba_image = "mba.mbn",
+ .proxy_clk_names = (char*[]){
+ "xo",
+ "axis2",
+ "prng",
+ NULL
+ },
+ .active_clk_names = (char*[]){
+ "iface",
+ "bus",
+ "mem",
+ "gpll0_mss",
+ "snoc_axi",
+ "mnoc_axi",
+ NULL
+ },
+ .need_mem_protection = true,
+ .version = MSS_SDM845,
+};
+
static const struct rproc_hexagon_res msm8996_mss = {
.hexagon_mba_image = "mba.mbn",
.proxy_clk_names = (char*[]){
@@ -1334,6 +1396,7 @@ static int q6v5_remove(struct platform_device *pdev)
{ .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss},
{ .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss},
{ .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
+ { .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss},
{ },
};
MODULE_DEVICE_TABLE(of, q6v5_of_match);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 6/6] remoteproc: qcom: Always assert and deassert reset signals in SDM845
2018-03-05 9:53 [PATCH 0/6] Add support for remoteproc modem-pil on SDM845 SoCs sibis
` (4 preceding siblings ...)
2018-03-05 9:53 ` [PATCH 5/6] remoteproc: qcom: Add support for mss remoteproc on SDM845 sibis
@ 2018-03-05 9:53 ` sibis
5 siblings, 0 replies; 16+ messages in thread
From: sibis @ 2018-03-05 9:53 UTC (permalink / raw)
To: bjorn.andersson
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, p.zabel, ohad, mark.rutland, robh+dt, kyan,
sricharan, akdwived, linux-arm-msm
SDM845 brings a new reset signal ALT_RESET which is a part of the MSS
subsystem hence requires some of the active clks to be enabled before
assert/deassert
Reset the modem if the BOOT FSM does timeout
Reset assert/deassert sequence vary across SoCs adding reset, adding
start/stop helper functions to handle SoC specific reset sequences
Signed-off-by: sibis <sibis@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_pil.c | 100 ++++++++++++++++++++++++++++++++++---
1 file changed, 94 insertions(+), 6 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index 92bf125..bd8c397 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -130,11 +130,14 @@ struct rproc_hexagon_res {
struct qcom_mss_reg_res *proxy_supply;
struct qcom_mss_reg_res *active_supply;
char **proxy_clk_names;
+ char **reset_clk_names;
char **active_clk_names;
int version;
bool need_mem_protection;
};
+struct q6v5_reset_ops;
+
struct q6v5 {
struct device *dev;
struct rproc *rproc;
@@ -153,8 +156,10 @@ struct q6v5 {
unsigned stop_bit;
struct clk *active_clks[8];
+ struct clk *reset_clks[4];
struct clk *proxy_clks[4];
int active_clk_count;
+ int reset_clk_count;
int proxy_clk_count;
struct reg_info active_regs[1];
@@ -175,6 +180,7 @@ struct q6v5 {
void *mpss_region;
size_t mpss_size;
+ const struct q6v5_reset_ops *ops;
struct qcom_rproc_glink glink_subdev;
struct qcom_rproc_subdev smd_subdev;
struct qcom_rproc_ssr ssr_subdev;
@@ -184,6 +190,11 @@ struct q6v5 {
int version;
};
+struct q6v5_reset_ops {
+ int (*reset_start)(struct q6v5 *qproc);
+ int (*reset_stop)(struct q6v5 *qproc);
+};
+
enum {
MSS_MSM8916,
MSS_MSM8974,
@@ -343,6 +354,52 @@ static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
return 0;
}
+static void alt_reset_restart(struct q6v5 *qproc, u32 restart)
+{
+ writel(restart, qproc->rmb_base + RMB_MBA_ALT_RESET);
+}
+
+static int q6v5_msm_reset_stop(struct q6v5 *qproc)
+{
+ return reset_control_assert(qproc->mss_restart);
+}
+
+static int q6v5_msm_reset_start(struct q6v5 *qproc)
+{
+ return reset_control_deassert(qproc->mss_restart);
+}
+
+static int q6v5_sdm_reset_stop(struct q6v5 *qproc)
+{
+ return reset_control_reset(qproc->mss_restart);
+}
+
+static int q6v5_sdm_reset_start(struct q6v5 *qproc)
+{
+ int ret;
+
+ alt_reset_restart(qproc, 1);
+ /* Ensure alt reset is written before restart reg */
+ udelay(100);
+
+ ret = reset_control_reset(qproc->mss_restart);
+
+ udelay(100);
+ alt_reset_restart(qproc, 0);
+
+ return ret;
+}
+
+static const struct q6v5_reset_ops q6v5_msm_ops = {
+ .reset_stop = q6v5_msm_reset_stop,
+ .reset_start = q6v5_msm_reset_start,
+};
+
+static const struct q6v5_reset_ops q6v5_sdm_ops = {
+ .reset_stop = q6v5_sdm_reset_stop,
+ .reset_start = q6v5_sdm_reset_start,
+};
+
static int q6v5_rmb_pbl_wait(struct q6v5 *qproc, int ms)
{
unsigned long timeout;
@@ -418,6 +475,8 @@ static int q6v5proc_reset(struct q6v5 *qproc)
val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
if (ret) {
dev_err(qproc->dev, "Boot FSM failed to complete.\n");
+ /* Reset the modem so that boot FSM is in reset state */
+ qproc->ops->reset_start(qproc);
return ret;
}
@@ -785,10 +844,18 @@ static int q6v5_start(struct rproc *rproc)
dev_err(qproc->dev, "failed to enable supplies\n");
goto disable_proxy_clk;
}
- ret = reset_control_deassert(qproc->mss_restart);
+
+ ret = q6v5_clk_enable(qproc->dev, qproc->reset_clks,
+ qproc->reset_clk_count);
+ if (ret) {
+ dev_err(qproc->dev, "failed to enable reset clocks\n");
+ goto disable_vdd;
+ }
+
+ ret = qproc->ops->reset_start(qproc);
if (ret) {
dev_err(qproc->dev, "failed to deassert mss restart\n");
- goto disable_vdd;
+ goto disable_reset_clks;
}
ret = q6v5_clk_enable(qproc->dev, qproc->active_clks,
@@ -880,7 +947,10 @@ static int q6v5_start(struct rproc *rproc)
qproc->active_clk_count);
assert_reset:
- reset_control_assert(qproc->mss_restart);
+ qproc->ops->reset_stop(qproc);
+disable_reset_clks:
+ q6v5_clk_disable(qproc->dev, qproc->reset_clks,
+ qproc->reset_clk_count);
disable_vdd:
q6v5_regulator_disable(qproc, qproc->active_regs,
qproc->active_reg_count);
@@ -930,9 +1000,11 @@ static int q6v5_stop(struct rproc *rproc)
qproc->mpss_phys, qproc->mpss_size);
WARN_ON(ret);
- reset_control_assert(qproc->mss_restart);
+ qproc->ops->reset_stop(qproc);
q6v5_clk_disable(qproc->dev, qproc->active_clks,
qproc->active_clk_count);
+ q6v5_clk_disable(qproc->dev, qproc->reset_clks,
+ qproc->reset_clk_count);
q6v5_regulator_disable(qproc, qproc->active_regs,
qproc->active_reg_count);
@@ -1179,6 +1251,12 @@ static int q6v5_probe(struct platform_device *pdev)
qproc->dev = &pdev->dev;
qproc->rproc = rproc;
platform_set_drvdata(pdev, qproc);
+ qproc->version = desc->version;
+
+ if (qproc->version == MSS_SDM845)
+ qproc->ops = &q6v5_sdm_ops;
+ else
+ qproc->ops = &q6v5_msm_ops;
init_completion(&qproc->start_done);
init_completion(&qproc->stop_done);
@@ -1199,6 +1277,14 @@ static int q6v5_probe(struct platform_device *pdev)
}
qproc->proxy_clk_count = ret;
+ ret = q6v5_init_clocks(&pdev->dev, qproc->reset_clks,
+ desc->reset_clk_names);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Failed to get reset clocks.\n");
+ goto free_rproc;
+ }
+ qproc->reset_clk_count = ret;
+
ret = q6v5_init_clocks(&pdev->dev, qproc->active_clks,
desc->active_clk_names);
if (ret < 0) {
@@ -1227,7 +1313,6 @@ static int q6v5_probe(struct platform_device *pdev)
if (ret)
goto free_rproc;
- qproc->version = desc->version;
qproc->need_mem_protection = desc->need_mem_protection;
ret = q6v5_request_irq(qproc, pdev, "wdog", q6v5_wdog_interrupt);
if (ret < 0)
@@ -1290,8 +1375,11 @@ static int q6v5_remove(struct platform_device *pdev)
"prng",
NULL
},
- .active_clk_names = (char*[]){
+ .reset_clk_names = (char*[]){
"iface",
+ NULL
+ },
+ .active_clk_names = (char*[]){
"bus",
"mem",
"gpll0_mss",
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 1/6] reset: qcom: AOSS (Always on subsystem) reset controller
2018-03-02 9:23 [PATCH 0/6] Add support for remoteproc modem-pil on SDM845 SoCs sibis
@ 2018-03-02 9:23 ` sibis
2018-03-02 10:30 ` Philipp Zabel
0 siblings, 1 reply; 16+ messages in thread
From: sibis @ 2018-03-02 9:23 UTC (permalink / raw)
To: bjorn.andersson
Cc: linux-remoteproc, linux-kernel, devicetree, sibis, georgi.djakov,
jassisinghbrar, p.zabel, ohad, mark.rutland, robh+dt, kyan,
sricharan, akdwived, linux-arm-msm
Add reset controller driver for Qualcomm SDM845 SoC to
control reset signals provided by AOSS for Modem, Venus
ADSP, GPU, Camera, Wireless, Display subsystem
Signed-off-by: sibis <sibis@codeaurora.org>
---
.../devicetree/bindings/reset/qcom,aoss-reset.txt | 54 +++++++
drivers/reset/Kconfig | 10 ++
drivers/reset/Makefile | 1 +
drivers/reset/reset-qcom-aoss.c | 161 +++++++++++++++++++++
include/dt-bindings/reset/qcom,aoss-sdm845.h | 17 +++
5 files changed, 243 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
create mode 100644 drivers/reset/reset-qcom-aoss.c
create mode 100644 include/dt-bindings/reset/qcom,aoss-sdm845.h
diff --git a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
new file mode 100644
index 0000000..5318e14
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
@@ -0,0 +1,54 @@
+Qualcomm AOSS Reset Controller
+======================================
+
+This binding describes a reset-controller found on AOSS (Always on SubSysem)
+for Qualcomm SDM845 SoCs.
+
+Required properties:
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be:
+ "qcom,aoss-reset-sdm845", "syscon"
+
+- reg:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: must specify the base address and size of the
+ syscon device.
+
+
+- #reset-cells:
+ Usage: required
+ Value type: <uint>
+ Definition: must be 1; cell entry represents the reset index.
+
+example:
+
+aoss_reset: qcom,reset-controller@b2e0100 {
+ compatible = "qcom,aoss-reset-sdm845", "syscon";
+ reg = <0xc2b0000 0x20004>;
+ #reset-cells = <1>;
+};
+
+
+Specifying reset lines connected to IP modules
+==============================================
+
+Device nodes that need access to reset lines should
+specify them as a reset phandle in their corresponding node as
+specified in reset.txt.
+
+Example:
+
+ modem-pil@4080000 {
+ ...
+
+ resets = <&aoss_reset AOSS_CC_MSS_RESTART>;
+ reset-names = "mss_restart";
+
+ ...
+ };
+
+For list of all valid reset indicies see
+<dt-bindings/reset/qcom,aoss-sdm845.h>
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 7fc7769..4b1da86 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -81,6 +81,16 @@ config RESET_PISTACHIO
help
This enables the reset driver for ImgTec Pistachio SoCs.
+config RESET_QCOM_AOSS
+ bool "Qcom AOSS Reset Driver"
+ depends on ARCH_QCOM || COMPILE_TEST
+ select MFD_SYSCON
+ help
+ This enables the AOSS (Always On SubSystem) reset driver
+ for Qcom SoCs. Say Y if you want to control reset signals
+ provided by AOSS for Modem, Venus, ADSP, GPU, Camera,
+ Wireless, Display subsystem. Otherwise, say N.
+
config RESET_SIMPLE
bool "Simple Reset Controller Driver" if COMPILE_TEST
default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 132c24f..c30044a 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
obj-$(CONFIG_RESET_MESON) += reset-meson.o
obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
+obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
diff --git a/drivers/reset/reset-qcom-aoss.c b/drivers/reset/reset-qcom-aoss.c
new file mode 100644
index 0000000..eb8c69b
--- /dev/null
+++ b/drivers/reset/reset-qcom-aoss.c
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/regmap.h>
+#include <linux/of_device.h>
+#include <dt-bindings/reset/qcom,aoss-sdm845.h>
+
+struct qcom_aoss_reset_map {
+ unsigned int reg;
+ u8 bit;
+};
+
+struct qcom_aoss_desc {
+ const struct regmap_config *config;
+ const struct qcom_aoss_reset_map *resets;
+ int delay;
+ size_t num_resets;
+};
+
+struct qcom_aoss_reset_data {
+ struct reset_controller_dev rcdev;
+ struct regmap *regmap;
+ const struct qcom_aoss_desc *desc;
+};
+
+static const struct regmap_config aoss_sdm845_regmap_config = {
+ .name = "aoss-reset",
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x20000,
+ .fast_io = true,
+};
+
+static const struct qcom_aoss_reset_map aoss_sdm845_resets[] = {
+ [AOSS_CC_MSS_RESTART] = { 0x0, 0 },
+ [AOSS_CC_CAMSS_RESTART] = { 0x1000, 0 },
+ [AOSS_CC_VENUS_RESTART] = { 0x2000, 0 },
+ [AOSS_CC_GPU_RESTART] = { 0x3000, 0 },
+ [AOSS_CC_DISPSS_RESTART] = { 0x4000, 0 },
+ [AOSS_CC_WCSS_RESTART] = { 0x10000, 0 },
+ [AOSS_CC_LPASS_RESTART] = { 0x20000, 0 },
+};
+
+static const struct qcom_aoss_desc aoss_sdm845_desc = {
+ .config = &aoss_sdm845_regmap_config,
+ .resets = aoss_sdm845_resets,
+ /* Wait 6 32kHz sleep cycles for reset */
+ .delay = 200,
+ .num_resets = ARRAY_SIZE(aoss_sdm845_resets),
+};
+
+static struct qcom_aoss_reset_data *to_qcom_aoss_reset_data(
+ struct reset_controller_dev *rcdev)
+{
+ return container_of(rcdev, struct qcom_aoss_reset_data, rcdev);
+}
+
+static int qcom_aoss_control_assert(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
+ const struct qcom_aoss_reset_map *map = &data->desc->resets[idx];
+
+ if (idx >= rcdev->nr_resets)
+ return -EINVAL;
+
+ return regmap_update_bits(data->regmap, map->reg,
+ BIT(map->bit), BIT(map->bit));
+}
+
+static int qcom_aoss_control_deassert(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
+ const struct qcom_aoss_reset_map *map = &data->desc->resets[idx];
+
+ if (idx >= rcdev->nr_resets)
+ return -EINVAL;
+
+ return regmap_update_bits(data->regmap, map->reg, BIT(map->bit), 0);
+}
+
+static int qcom_aoss_control_reset(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
+ int ret;
+
+ ret = rcdev->ops->assert(rcdev, idx);
+ if (ret)
+ return ret;
+
+ udelay(data->desc->delay);
+
+ ret = rcdev->ops->deassert(rcdev, idx);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static const struct reset_control_ops qcom_aoss_reset_ops = {
+ .reset = qcom_aoss_control_reset,
+ .assert = qcom_aoss_control_assert,
+ .deassert = qcom_aoss_control_deassert,
+};
+
+static int qcom_aoss_reset_probe(struct platform_device *pdev)
+{
+ struct qcom_aoss_reset_data *data;
+ struct device *dev = &pdev->dev;
+ const struct qcom_aoss_desc *desc;
+
+ desc = of_device_get_match_data(&pdev->dev);
+ if (!desc)
+ return -EINVAL;
+
+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ data->desc = desc;
+ data->regmap = syscon_node_to_regmap(dev->of_node);
+ if (IS_ERR(data->regmap)) {
+ dev_err(dev, "Unable to get aoss-reset regmap");
+ return PTR_ERR(data->regmap);
+ }
+ regmap_attach_dev(dev, data->regmap, desc->config);
+
+ data->rcdev.owner = THIS_MODULE;
+ data->rcdev.ops = &qcom_aoss_reset_ops;
+ data->rcdev.nr_resets = desc->num_resets;
+ data->rcdev.of_node = pdev->dev.of_node;
+
+ return devm_reset_controller_register(&pdev->dev, &data->rcdev);
+}
+
+static const struct of_device_id qcom_aoss_reset_of_match[] = {
+ { .compatible = "qcom,aoss-reset-sdm845", .data = &aoss_sdm845_desc},
+ {}
+};
+
+static struct platform_driver qcom_aoss_reset_driver = {
+ .probe = qcom_aoss_reset_probe,
+ .driver = {
+ .name = "qcom_aoss_reset",
+ .of_match_table = qcom_aoss_reset_of_match,
+ },
+};
+
+builtin_platform_driver(qcom_aoss_reset_driver);
+
+MODULE_DESCRIPTION("Qualcomm AOSS Reset Driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/dt-bindings/reset/qcom,aoss-sdm845.h b/include/dt-bindings/reset/qcom,aoss-sdm845.h
new file mode 100644
index 0000000..e9b38fc
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,aoss-sdm845.h
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_RESET_AOSS_SDM_845_H
+#define _DT_BINDINGS_RESET_AOSS_SDM_845_H
+
+#define AOSS_CC_MSS_RESTART 0
+#define AOSS_CC_CAMSS_RESTART 1
+#define AOSS_CC_VENUS_RESTART 2
+#define AOSS_CC_GPU_RESTART 3
+#define AOSS_CC_DISPSS_RESTART 4
+#define AOSS_CC_WCSS_RESTART 5
+#define AOSS_CC_LPASS_RESTART 6
+
+#endif
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 1/6] reset: qcom: AOSS (Always on subsystem) reset controller
2018-03-02 9:23 ` [PATCH 1/6] reset: qcom: AOSS (Always on subsystem) reset controller sibis
@ 2018-03-02 10:30 ` Philipp Zabel
2018-03-05 6:47 ` Sibi S
0 siblings, 1 reply; 16+ messages in thread
From: Philipp Zabel @ 2018-03-02 10:30 UTC (permalink / raw)
To: sibis, bjorn.andersson
Cc: linux-remoteproc, linux-kernel, devicetree, georgi.djakov,
jassisinghbrar, ohad, mark.rutland, robh+dt, kyan, sricharan,
akdwived, linux-arm-msm
Hi sibis,
thank you for the patch. I have a few questions and comments below.
On Fri, 2018-03-02 at 14:53 +0530, sibis wrote:
> Add reset controller driver for Qualcomm SDM845 SoC to
> control reset signals provided by AOSS for Modem, Venus
> ADSP, GPU, Camera, Wireless, Display subsystem
>
> Signed-off-by: sibis <sibis@codeaurora.org>
> ---
> .../devicetree/bindings/reset/qcom,aoss-reset.txt | 54 +++++++
> drivers/reset/Kconfig | 10 ++
> drivers/reset/Makefile | 1 +
> drivers/reset/reset-qcom-aoss.c | 161 +++++++++++++++++++++
> include/dt-bindings/reset/qcom,aoss-sdm845.h | 17 +++
> 5 files changed, 243 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
> create mode 100644 drivers/reset/reset-qcom-aoss.c
> create mode 100644 include/dt-bindings/reset/qcom,aoss-sdm845.h
>
> diff --git a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
> new file mode 100644
> index 0000000..5318e14
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
> @@ -0,0 +1,54 @@
> +Qualcomm AOSS Reset Controller
> +======================================
> +
> +This binding describes a reset-controller found on AOSS (Always on SubSysem)
> +for Qualcomm SDM845 SoCs.
> +
> +Required properties:
> +- compatible:
> + Usage: required
> + Value type: <string>
> + Definition: must be:
> + "qcom,aoss-reset-sdm845", "syscon"
> +
> +- reg:
> + Usage: required
> + Value type: <prop-encoded-array>
> + Definition: must specify the base address and size of the
> + syscon device.
> +
> +
> +- #reset-cells:
> + Usage: required
> + Value type: <uint>
> + Definition: must be 1; cell entry represents the reset index.
> +
> +example:
> +
> +aoss_reset: qcom,reset-controller@b2e0100 {
> + compatible = "qcom,aoss-reset-sdm845", "syscon";
> + reg = <0xc2b0000 0x20004>;
> + #reset-cells = <1>;
> +};
> +
> +
> +Specifying reset lines connected to IP modules
> +==============================================
> +
> +Device nodes that need access to reset lines should
> +specify them as a reset phandle in their corresponding node as
> +specified in reset.txt.
> +
> +Example:
> +
> + modem-pil@4080000 {
> + ...
> +
> + resets = <&aoss_reset AOSS_CC_MSS_RESTART>;
> + reset-names = "mss_restart";
> +
> + ...
> + };
> +
> +For list of all valid reset indicies see
> +<dt-bindings/reset/qcom,aoss-sdm845.h>
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index 7fc7769..4b1da86 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -81,6 +81,16 @@ config RESET_PISTACHIO
> help
> This enables the reset driver for ImgTec Pistachio SoCs.
>
> +config RESET_QCOM_AOSS
> + bool "Qcom AOSS Reset Driver"
> + depends on ARCH_QCOM || COMPILE_TEST
Do all ARCH_QCOM have AOSS? If so, should this be enabled by default?
> + select MFD_SYSCON
> + help
> + This enables the AOSS (Always On SubSystem) reset driver
> + for Qcom SoCs. Say Y if you want to control reset signals
Is Qcom and Qualcomm interchangeable?
> + provided by AOSS for Modem, Venus, ADSP, GPU, Camera,
> + Wireless, Display subsystem. Otherwise, say N.
> +
> config RESET_SIMPLE
> bool "Simple Reset Controller Driver" if COMPILE_TEST
> default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX
> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> index 132c24f..c30044a 100644
> --- a/drivers/reset/Makefile
> +++ b/drivers/reset/Makefile
> @@ -14,6 +14,7 @@ obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
> obj-$(CONFIG_RESET_MESON) += reset-meson.o
> obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
> obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
> +obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
> obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
> obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
> obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
> diff --git a/drivers/reset/reset-qcom-aoss.c b/drivers/reset/reset-qcom-aoss.c
> new file mode 100644
> index 0000000..eb8c69b
> --- /dev/null
> +++ b/drivers/reset/reset-qcom-aoss.c
> @@ -0,0 +1,161 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2018 The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset-controller.h>
> +#include <linux/regmap.h>
> +#include <linux/of_device.h>
> +#include <dt-bindings/reset/qcom,aoss-sdm845.h>
> +
> +struct qcom_aoss_reset_map {
> + unsigned int reg;
> + u8 bit;
> +};
> +
> +struct qcom_aoss_desc {
> + const struct regmap_config *config;
> + const struct qcom_aoss_reset_map *resets;
> + int delay;
> + size_t num_resets;
> +};
> +
> +struct qcom_aoss_reset_data {
> + struct reset_controller_dev rcdev;
> + struct regmap *regmap;
> + const struct qcom_aoss_desc *desc;
> +};
> +
> +static const struct regmap_config aoss_sdm845_regmap_config = {
> + .name = "aoss-reset",
> + .reg_bits = 32,
> + .reg_stride = 4,
> + .val_bits = 32,
> + .max_register = 0x20000,
> + .fast_io = true,
> +};
> +
> +static const struct qcom_aoss_reset_map aoss_sdm845_resets[] = {
> + [AOSS_CC_MSS_RESTART] = { 0x0, 0 },
> + [AOSS_CC_CAMSS_RESTART] = { 0x1000, 0 },
> + [AOSS_CC_VENUS_RESTART] = { 0x2000, 0 },
> + [AOSS_CC_GPU_RESTART] = { 0x3000, 0 },
> + [AOSS_CC_DISPSS_RESTART] = { 0x4000, 0 },
> + [AOSS_CC_WCSS_RESTART] = { 0x10000, 0 },
> + [AOSS_CC_LPASS_RESTART] = { 0x20000, 0 },
> +};
> +
> +static const struct qcom_aoss_desc aoss_sdm845_desc = {
> + .config = &aoss_sdm845_regmap_config,
> + .resets = aoss_sdm845_resets,
> + /* Wait 6 32kHz sleep cycles for reset */
> + .delay = 200,
> + .num_resets = ARRAY_SIZE(aoss_sdm845_resets),
> +};
> +
> +static struct qcom_aoss_reset_data *to_qcom_aoss_reset_data(
> + struct reset_controller_dev *rcdev)
> +{
> + return container_of(rcdev, struct qcom_aoss_reset_data, rcdev);
> +}
> +
> +static int qcom_aoss_control_assert(struct reset_controller_dev *rcdev,
> + unsigned long idx)
> +{
> + struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
> + const struct qcom_aoss_reset_map *map = &data->desc->resets[idx];
> +
> + if (idx >= rcdev->nr_resets)
> + return -EINVAL;
This check is not necessary. For all drivers that don't set of_xlate,
the default of_reset_simple_xlate already makes sure no reset_control
is ever returned with rstc->id >= rcdev->nr_resets.
> + return regmap_update_bits(data->regmap, map->reg,
> + BIT(map->bit), BIT(map->bit));
> +}
> +
> +static int qcom_aoss_control_deassert(struct reset_controller_dev *rcdev,
> + unsigned long idx)
> +{
> + struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
> + const struct qcom_aoss_reset_map *map = &data->desc->resets[idx];
> +
> + if (idx >= rcdev->nr_resets)
> + return -EINVAL;
Same here.
> + return regmap_update_bits(data->regmap, map->reg, BIT(map->bit), 0);
> +}
> +
> +static int qcom_aoss_control_reset(struct reset_controller_dev *rcdev,
> + unsigned long idx)
> +{
> + struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
> + int ret;
> +
> + ret = rcdev->ops->assert(rcdev, idx);
Don't use the ops function pointers here, just call
qcom_aoss_control_assert directly.
> + if (ret)
> + return ret;
> +
> + udelay(data->desc->delay);
> +
> + ret = rcdev->ops->deassert(rcdev, idx);
> + if (ret)
> + return ret;
> +
> + return 0;
This can be simplified to just
return qcom_aoss_control_deassert(rcdev, idx);
> +}
> +
> +static const struct reset_control_ops qcom_aoss_reset_ops = {
> + .reset = qcom_aoss_control_reset,
> + .assert = qcom_aoss_control_assert,
> + .deassert = qcom_aoss_control_deassert,
> +};
> +
> +static int qcom_aoss_reset_probe(struct platform_device *pdev)
> +{
> + struct qcom_aoss_reset_data *data;
> + struct device *dev = &pdev->dev;
> + const struct qcom_aoss_desc *desc;
> +
> + desc = of_device_get_match_data(&pdev->dev);
You could use dev here instead of pdev->dev.
> + if (!desc)
> + return -EINVAL;
> +
> + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
> + if (!data)
> + return -ENOMEM;
> +
> + data->desc = desc;
> + data->regmap = syscon_node_to_regmap(dev->of_node);
> + if (IS_ERR(data->regmap)) {
> + dev_err(dev, "Unable to get aoss-reset regmap");
> + return PTR_ERR(data->regmap);
> + }
> + regmap_attach_dev(dev, data->regmap, desc->config);
> +
> + data->rcdev.owner = THIS_MODULE;
> + data->rcdev.ops = &qcom_aoss_reset_ops;
> + data->rcdev.nr_resets = desc->num_resets;
> + data->rcdev.of_node = pdev->dev.of_node;
And here.
> + return devm_reset_controller_register(&pdev->dev, &data->rcdev);
And here.
> +}
> +
> +static const struct of_device_id qcom_aoss_reset_of_match[] = {
> + { .compatible = "qcom,aoss-reset-sdm845", .data = &aoss_sdm845_desc},
Consider adding a space between &aoss_sdm845_desc and } ...
> + {}
> +};
> +
> +static struct platform_driver qcom_aoss_reset_driver = {
> + .probe = qcom_aoss_reset_probe,
> + .driver = {
> + .name = "qcom_aoss_reset",
... and removing the superfluous space here.
> + .of_match_table = qcom_aoss_reset_of_match,
> + },
> +};
> +
> +builtin_platform_driver(qcom_aoss_reset_driver);
> +
> +MODULE_DESCRIPTION("Qualcomm AOSS Reset Driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/include/dt-bindings/reset/qcom,aoss-sdm845.h b/include/dt-bindings/reset/qcom,aoss-sdm845.h
> new file mode 100644
> index 0000000..e9b38fc
> --- /dev/null
> +++ b/include/dt-bindings/reset/qcom,aoss-sdm845.h
> @@ -0,0 +1,17 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2018 The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_RESET_AOSS_SDM_845_H
> +#define _DT_BINDINGS_RESET_AOSS_SDM_845_H
> +
> +#define AOSS_CC_MSS_RESTART 0
> +#define AOSS_CC_CAMSS_RESTART 1
> +#define AOSS_CC_VENUS_RESTART 2
> +#define AOSS_CC_GPU_RESTART 3
> +#define AOSS_CC_DISPSS_RESTART 4
> +#define AOSS_CC_WCSS_RESTART 5
> +#define AOSS_CC_LPASS_RESTART 6
> +
> +#endif
regards
Philipp
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH 1/6] reset: qcom: AOSS (Always on subsystem) reset controller
2018-03-02 10:30 ` Philipp Zabel
@ 2018-03-05 6:47 ` Sibi S
0 siblings, 0 replies; 16+ messages in thread
From: Sibi S @ 2018-03-05 6:47 UTC (permalink / raw)
To: Philipp Zabel, bjorn.andersson
Cc: linux-remoteproc, linux-kernel, devicetree, georgi.djakov,
jassisinghbrar, ohad, mark.rutland, robh+dt, kyan, sricharan,
akdwived, linux-arm-msm
Hi Philipp,
Thanks for the review. I will post out the v2 of the patch series.
On 03/02/2018 04:00 PM, Philipp Zabel wrote:
> Hi sibis,
>
> thank you for the patch. I have a few questions and comments below.
>
> On Fri, 2018-03-02 at 14:53 +0530, sibis wrote:
>> Add reset controller driver for Qualcomm SDM845 SoC to
>> control reset signals provided by AOSS for Modem, Venus
>> ADSP, GPU, Camera, Wireless, Display subsystem
>>
>> Signed-off-by: sibis <sibis@codeaurora.org>
>> ---
>> .../devicetree/bindings/reset/qcom,aoss-reset.txt | 54 +++++++
>> drivers/reset/Kconfig | 10 ++
>> drivers/reset/Makefile | 1 +
>> drivers/reset/reset-qcom-aoss.c | 161 +++++++++++++++++++++
>> include/dt-bindings/reset/qcom,aoss-sdm845.h | 17 +++
>> 5 files changed, 243 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
>> create mode 100644 drivers/reset/reset-qcom-aoss.c
>> create mode 100644 include/dt-bindings/reset/qcom,aoss-sdm845.h
>>
>> diff --git a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
>> new file mode 100644
>> index 0000000..5318e14
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
>> @@ -0,0 +1,54 @@
>> +Qualcomm AOSS Reset Controller
>> +======================================
>> +
>> +This binding describes a reset-controller found on AOSS (Always on SubSysem)
>> +for Qualcomm SDM845 SoCs.
>> +
>> +Required properties:
>> +- compatible:
>> + Usage: required
>> + Value type: <string>
>> + Definition: must be:
>> + "qcom,aoss-reset-sdm845", "syscon"
>> +
>> +- reg:
>> + Usage: required
>> + Value type: <prop-encoded-array>
>> + Definition: must specify the base address and size of the
>> + syscon device.
>> +
>> +
>> +- #reset-cells:
>> + Usage: required
>> + Value type: <uint>
>> + Definition: must be 1; cell entry represents the reset index.
>> +
>> +example:
>> +
>> +aoss_reset: qcom,reset-controller@b2e0100 {
>> + compatible = "qcom,aoss-reset-sdm845", "syscon";
>> + reg = <0xc2b0000 0x20004>;
>> + #reset-cells = <1>;
>> +};
>> +
>> +
>> +Specifying reset lines connected to IP modules
>> +==============================================
>> +
>> +Device nodes that need access to reset lines should
>> +specify them as a reset phandle in their corresponding node as
>> +specified in reset.txt.
>> +
>> +Example:
>> +
>> + modem-pil@4080000 {
>> + ...
>> +
>> + resets = <&aoss_reset AOSS_CC_MSS_RESTART>;
>> + reset-names = "mss_restart";
>> +
>> + ...
>> + };
>> +
>> +For list of all valid reset indicies see
>> +<dt-bindings/reset/qcom,aoss-sdm845.h>
>> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
>> index 7fc7769..4b1da86 100644
>> --- a/drivers/reset/Kconfig
>> +++ b/drivers/reset/Kconfig
>> @@ -81,6 +81,16 @@ config RESET_PISTACHIO
>> help
>> This enables the reset driver for ImgTec Pistachio SoCs.
>>
>> +config RESET_QCOM_AOSS
>> + bool "Qcom AOSS Reset Driver"
>> + depends on ARCH_QCOM || COMPILE_TEST
>
> Do all ARCH_QCOM have AOSS? If so, should this be enabled by default?
>
AOSS reset is currently supported on SDM845 SoCs and not on any of other
the previously upstreamed Qualcomm SoCs. I will change description to
convey the same. I needs to explicitly enabled for SDM845 SoCs.
>> + select MFD_SYSCON
>> + help
>> + This enables the AOSS (Always On SubSystem) reset driver
>> + for Qcom SoCs. Say Y if you want to control reset signals
>
> Is Qcom and Qualcomm interchangeable?
>
Though it is used interchangeably, it will make more sense if I
change it to Qualcomm here.
>> + provided by AOSS for Modem, Venus, ADSP, GPU, Camera,
>> + Wireless, Display subsystem. Otherwise, say N.
>> +
>> config RESET_SIMPLE
>> bool "Simple Reset Controller Driver" if COMPILE_TEST
>> default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX
>> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
>> index 132c24f..c30044a 100644
>> --- a/drivers/reset/Makefile
>> +++ b/drivers/reset/Makefile
>> @@ -14,6 +14,7 @@ obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
>> obj-$(CONFIG_RESET_MESON) += reset-meson.o
>> obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
>> obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
>> +obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
>> obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
>> obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
>> obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
>> diff --git a/drivers/reset/reset-qcom-aoss.c b/drivers/reset/reset-qcom-aoss.c
>> new file mode 100644
>> index 0000000..eb8c69b
>> --- /dev/null
>> +++ b/drivers/reset/reset-qcom-aoss.c
>> @@ -0,0 +1,161 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2018 The Linux Foundation. All rights reserved.
>> + */
>> +
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/module.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/reset-controller.h>
>> +#include <linux/regmap.h>
>> +#include <linux/of_device.h>
>> +#include <dt-bindings/reset/qcom,aoss-sdm845.h>
>> +
>> +struct qcom_aoss_reset_map {
>> + unsigned int reg;
>> + u8 bit;
>> +};
>> +
>> +struct qcom_aoss_desc {
>> + const struct regmap_config *config;
>> + const struct qcom_aoss_reset_map *resets;
>> + int delay;
>> + size_t num_resets;
>> +};
>> +
>> +struct qcom_aoss_reset_data {
>> + struct reset_controller_dev rcdev;
>> + struct regmap *regmap;
>> + const struct qcom_aoss_desc *desc;
>> +};
>> +
>> +static const struct regmap_config aoss_sdm845_regmap_config = {
>> + .name = "aoss-reset",
>> + .reg_bits = 32,
>> + .reg_stride = 4,
>> + .val_bits = 32,
>> + .max_register = 0x20000,
>> + .fast_io = true,
>> +};
>> +
>> +static const struct qcom_aoss_reset_map aoss_sdm845_resets[] = {
>> + [AOSS_CC_MSS_RESTART] = { 0x0, 0 },
>> + [AOSS_CC_CAMSS_RESTART] = { 0x1000, 0 },
>> + [AOSS_CC_VENUS_RESTART] = { 0x2000, 0 },
>> + [AOSS_CC_GPU_RESTART] = { 0x3000, 0 },
>> + [AOSS_CC_DISPSS_RESTART] = { 0x4000, 0 },
>> + [AOSS_CC_WCSS_RESTART] = { 0x10000, 0 },
>> + [AOSS_CC_LPASS_RESTART] = { 0x20000, 0 },
>> +};
>> +
>> +static const struct qcom_aoss_desc aoss_sdm845_desc = {
>> + .config = &aoss_sdm845_regmap_config,
>> + .resets = aoss_sdm845_resets,
>> + /* Wait 6 32kHz sleep cycles for reset */
>> + .delay = 200,
>> + .num_resets = ARRAY_SIZE(aoss_sdm845_resets),
>> +};
>> +
>> +static struct qcom_aoss_reset_data *to_qcom_aoss_reset_data(
>> + struct reset_controller_dev *rcdev)
>> +{
>> + return container_of(rcdev, struct qcom_aoss_reset_data, rcdev);
>> +}
>> +
>> +static int qcom_aoss_control_assert(struct reset_controller_dev *rcdev,
>> + unsigned long idx)
>> +{
>> + struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
>> + const struct qcom_aoss_reset_map *map = &data->desc->resets[idx];
>> +
>> + if (idx >= rcdev->nr_resets)
>> + return -EINVAL;
>
> This check is not necessary. For all drivers that don't set of_xlate,
> the default of_reset_simple_xlate already makes sure no reset_control
> is ever returned with rstc->id >= rcdev->nr_resets.
>
Will remove it
>> + return regmap_update_bits(data->regmap, map->reg,
>> + BIT(map->bit), BIT(map->bit));
>> +}
>> +
>> +static int qcom_aoss_control_deassert(struct reset_controller_dev *rcdev,
>> + unsigned long idx)
>> +{
>> + struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
>> + const struct qcom_aoss_reset_map *map = &data->desc->resets[idx];
>> +
>> + if (idx >= rcdev->nr_resets)
>> + return -EINVAL;
>
> Same here.
>
ditto
>> + return regmap_update_bits(data->regmap, map->reg, BIT(map->bit), 0);
>> +}
>> +
>> +static int qcom_aoss_control_reset(struct reset_controller_dev *rcdev,
>> + unsigned long idx)
>> +{
>> + struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
>> + int ret;
>> +
>> + ret = rcdev->ops->assert(rcdev, idx);
>
> Don't use the ops function pointers here, just call
> qcom_aoss_control_assert directly.
sure will repace it.
>
>> + if (ret)
>> + return ret;
>> +
>> + udelay(data->desc->delay);
>> +
>> + ret = rcdev->ops->deassert(rcdev, idx);
>> + if (ret)
>> + return ret;
>> +
>> + return 0;
>
> This can be simplified to just
>
> return qcom_aoss_control_deassert(rcdev, idx);
>
ditto
>> +}
>> +
>> +static const struct reset_control_ops qcom_aoss_reset_ops = {
>> + .reset = qcom_aoss_control_reset,
>> + .assert = qcom_aoss_control_assert,
>> + .deassert = qcom_aoss_control_deassert,
>> +};
>> +
>> +static int qcom_aoss_reset_probe(struct platform_device *pdev)
>> +{
>> + struct qcom_aoss_reset_data *data;
>> + struct device *dev = &pdev->dev;
>> + const struct qcom_aoss_desc *desc;
>> +
>> + desc = of_device_get_match_data(&pdev->dev);
>
> You could use dev here instead of pdev->dev.
>
Yeah I will replace all instances of pdev->dev with dev
>> + if (!desc)
>> + return -EINVAL;
>> +
>> + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
>> + if (!data)
>> + return -ENOMEM;
>> +
>> + data->desc = desc;
>> + data->regmap = syscon_node_to_regmap(dev->of_node);
>> + if (IS_ERR(data->regmap)) {
>> + dev_err(dev, "Unable to get aoss-reset regmap");
>> + return PTR_ERR(data->regmap);
>> + }
>> + regmap_attach_dev(dev, data->regmap, desc->config);
>> +
>> + data->rcdev.owner = THIS_MODULE;
>> + data->rcdev.ops = &qcom_aoss_reset_ops;
>> + data->rcdev.nr_resets = desc->num_resets;
>> + data->rcdev.of_node = pdev->dev.of_node;
>
> And here.
>
>> + return devm_reset_controller_register(&pdev->dev, &data->rcdev);
>
> And here.
>
>> +}
>> +
>> +static const struct of_device_id qcom_aoss_reset_of_match[] = {
>> + { .compatible = "qcom,aoss-reset-sdm845", .data = &aoss_sdm845_desc},
>
> Consider adding a space between &aoss_sdm845_desc and } ...
>
sure will do
>> + {}
>> +};
>> +
>> +static struct platform_driver qcom_aoss_reset_driver = {
>> + .probe = qcom_aoss_reset_probe,
>> + .driver = {
>> + .name = "qcom_aoss_reset",
>
> ... and removing the superfluous space here.
Will remove the superfluous spacing
>
>> + .of_match_table = qcom_aoss_reset_of_match,
>> + },
>> +};
>> +
>> +builtin_platform_driver(qcom_aoss_reset_driver);
>> +
>> +MODULE_DESCRIPTION("Qualcomm AOSS Reset Driver");
>> +MODULE_LICENSE("GPL v2");
>> diff --git a/include/dt-bindings/reset/qcom,aoss-sdm845.h b/include/dt-bindings/reset/qcom,aoss-sdm845.h
>> new file mode 100644
>> index 0000000..e9b38fc
>> --- /dev/null
>> +++ b/include/dt-bindings/reset/qcom,aoss-sdm845.h
>> @@ -0,0 +1,17 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2018 The Linux Foundation. All rights reserved.
>> + */
>> +
>> +#ifndef _DT_BINDINGS_RESET_AOSS_SDM_845_H
>> +#define _DT_BINDINGS_RESET_AOSS_SDM_845_H
>> +
>> +#define AOSS_CC_MSS_RESTART 0
>> +#define AOSS_CC_CAMSS_RESTART 1
>> +#define AOSS_CC_VENUS_RESTART 2
>> +#define AOSS_CC_GPU_RESTART 3
>> +#define AOSS_CC_DISPSS_RESTART 4
>> +#define AOSS_CC_WCSS_RESTART 5
>> +#define AOSS_CC_LPASS_RESTART 6
>> +
>> +#endif
>
> regards
> Philipp
>
--
Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc, is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 16+ messages in thread