[PATCH v5 0/9] phy: Add new Exynos USB 2.0 PHY driver

[PATCH v5 0/9] phy: Add new Exynos USB 2.0 PHY driver

[Kamil Debski]

Hi,

This is the fifth version of the patchset. It adds a new Exynos USB 2.0 PHY
driver. The driver uses the Generic PHY Framework.

I would like to thank everyone who contributed with comments and took the time
to read through the patches in the previous versions of this patchset.
We had a lengthy discussion with Kishon about how the driver should look like.
This patchset contains the updated version of my original idea, where support
for Exynos 4210 and 4212 is done in separate files. Kishon's idea is to join
these two into a single file. I have prepared two alternative version which I
will send soon after this patchset.

Just like the fourth version this patch depends on:
[PATCH V11 1/3] ARM: dts: Add pmu sysreg node to exynos5250 and exynos5420 dtsi
files [1].

Best wishes,
Kamil Debski

[1] - http://www.spinics.net/lists/linux-samsung-soc/msg24528.html

----------------
Changes from v4:
1) phy: core: Add an exported of_phy_get function
- the new exported function of_phy_get was changed to take the phy's name as a
  parameter instead of the index
2) phy: core: Add devm_of_phy_get to phy-core
- fixes made in the comments to devm_of_phy_get
3) phy: Add new Exynos USB PHY driver
- move the documentation from a new to an existing file - samsung-phy.txt
- fix typos and uppercase hex addresses
- add more explanations to Kconfig (checkpatch still complains, but I find it
  hard to think what else could I add)
- add selects MFD_SYSCON as the driver needs it (Thank you, Tobias!)
- cleanup included headers in both *.c and .h files
- use BIT(x) macro instead of (1 << x)
- replaced HOST and DEV with PHY0 and PHY1 in phy-exynos4212-usb2.c, the
  registers are described as PHYx in the documentation hence the decision to
  leave the PHYx naming
- fixed typo in exynos4210_rate_to_clk reg -> *reg
- change hax_mode_switch and enabled type to bool
4) usb: ehci-s5p: Change to use phy provided by the generic phy framework
- Put the issue of phy->otg in order - since the new phy driver does not provide
  this field. With the new driver the switch between host and device is done in
  power_on of the respective host and device phys.
5) usb: s3c-hsotg: Use the new Exynos USB phy driver with the generic phy
   framework
- fixed the example in the documentation
6) phy: Add support for S5PV210 to the Exynos USB PHY driver
- include files cleanup
- use BIT(x) macro instead of (1 << x)
7) phy: Add Exynos 5250 support to the Exynos USB 2.0 PHY driver
- include files cleanup
- use BIT(x) macro instead of (1 << x)
8) dts: Add usb2phy to Exynos 4
- no changes
9) dts: Add usb2phy to Exynos 5250
- no changes

----------------
Changes from v3:
- using PMU and system registers indirectly via syscon
- change labelling
- change Kconfig name
- fixed typos/stray whitespace
- move of_phy_provider_register() to the end of probe
- add a regular error return code to the rate_to_clk functions
- cleanup code and remove unused code
- change struct names to avoid collisions
- add mechanism to support multiple phys by the ehci driver

----------------
Changes from v2:
- rebase all patches to the usb-next branch
- fixes in the documentation file
  - remove wrong entries in the phy node (ranges, and #address- & #size-cells)
  - add clocks and clock-names as required properites
  - rephrase a few sentences
- fixes in the ehci-exynos.c file
  - move phy_name variable next to phy in exynos_ehci_hcd
  - remove otg from exynos_ehci_hcd as it was no longer used
  - move devm_phy_get after the Exynos5440 skip_phy check
- fixes in the s3c-hsotg.c file
  - cosmetic fixes (remove empty line that was wrongfully added)
- fixes in the main driver
  - remove cpu_type in favour for a boolean flag matched with the compatible
    value
  - rename files, structures, variables and Kconfig entires - change from simple
    "uphy" to "usb2_phy"
  - fix multiline comments style
  - simplify #ifdefs in of_device_id
  - fix Kconfig description
  - change dev_info to dev_dbg where reasonable
  - cosmetic changes (remove wrongful blank lines)
  - remove unnecessary reference counting

----------------
Changes from v1:
- the changes include minor fixes of the hardware initialization of the PHY
  module
- some other minor fixes were introduced

----------------------
Original cover letter:

Hi,

This patch adds a new drive for USB PHYs for Samsung SoCs. The driver is
using the Generic PHY Framework created by Kishon Vijay Abrahan I. It
can be found here https://lkml.org/lkml/2013/8/21/29. This patch adds
support to Exynos4 family of SoCs. Support for Exynos3 and Exynos5 is
planned to be added in the near future.

I welcome your comments.

----------------------

[1] https://lkml.org/lkml/2013/8/21/29

Kamil Debski (8):
  phy: core: Add an exported of_phy_get function
  phy: core: Add devm_of_phy_get to phy-core
  phy: Add new Exynos USB PHY driver
  usb: ehci-s5p: Change to use phy provided by the generic phy
    framework
  usb: s3c-hsotg: Use the new Exynos USB phy driver with the generic
    phy framework
  phy: Add Exynos 5250 support to the Exynos USB 2.0 PHY driver
  dts: Add usb2phy to Exynos 4
  dts: Add usb2phy to Exynos 5250

Mateusz Krawczuk (1):
  phy: Add support for S5PV210 to the Exynos USB PHY driver

 .../devicetree/bindings/arm/samsung/pmu.txt        |    2 +
 .../devicetree/bindings/phy/samsung-phy.txt        |   57 +++
 .../devicetree/bindings/usb/samsung-hsotg.txt      |    4 +
 Documentation/devicetree/bindings/usb/usb-ehci.txt |   35 ++
 arch/arm/boot/dts/exynos4.dtsi                     |   31 ++
 arch/arm/boot/dts/exynos4210.dtsi                  |   17 +
 arch/arm/boot/dts/exynos4x12.dtsi                  |   17 +
 arch/arm/boot/dts/exynos5250.dtsi                  |   33 +-
 drivers/phy/Kconfig                                |   50 +++
 drivers/phy/Makefile                               |    5 +
 drivers/phy/phy-core.c                             |   76 +++-
 drivers/phy/phy-exynos4210-usb2.c                  |  257 +++++++++++++
 drivers/phy/phy-exynos4212-usb2.c                  |  306 +++++++++++++++
 drivers/phy/phy-exynos5250-usb2.c                  |  406 ++++++++++++++++++++
 drivers/phy/phy-s5pv210-usb2.c                     |  199 ++++++++++
 drivers/phy/phy-samsung-usb2.c                     |  238 ++++++++++++
 drivers/phy/phy-samsung-usb2.h                     |   69 ++++
 drivers/usb/gadget/s3c-hsotg.c                     |   11 +-
 drivers/usb/host/ehci-exynos.c                     |   97 +++--
 include/linux/phy/phy.h                            |    3 +
 20 files changed, 1853 insertions(+), 60 deletions(-)
 create mode 100644 drivers/phy/phy-exynos4210-usb2.c
 create mode 100644 drivers/phy/phy-exynos4212-usb2.c
 create mode 100644 drivers/phy/phy-exynos5250-usb2.c
 create mode 100644 drivers/phy/phy-s5pv210-usb2.c
 create mode 100644 drivers/phy/phy-samsung-usb2.c
 create mode 100644 drivers/phy/phy-samsung-usb2.h

-- 
1.7.9.5

[PATCH v4 1/9] phy: core: Add an exported of_phy_get function

[Kamil Debski]

Previously the of_phy_get function took a struct device * and
was declared static. It was impossible to call it from
another driver and thus it was impossible to get phy defined
for a given node. The old function was renamed to _of_phy_get
and was left for internal use. of_phy_get function was added
and it was exported. The function enables to get a phy for
a given device tree node.

Signed-off-by: Kamil Debski <k.debski@samsung.com>
---
 drivers/phy/phy-core.c  |   45 ++++++++++++++++++++++++++++++++++++---------
 include/linux/phy/phy.h |    1 +
 2 files changed, 37 insertions(+), 9 deletions(-)

diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
index 03cf8fb..d6f8c34 100644
--- a/drivers/phy/phy-core.c
+++ b/drivers/phy/phy-core.c
@@ -240,8 +240,8 @@ out:
 EXPORT_SYMBOL_GPL(phy_power_off);
 
 /**
- * of_phy_get() - lookup and obtain a reference to a phy by phandle
- * @dev: device that requests this phy
+ * _of_phy_get() - lookup and obtain a reference to a phy by phandle
+ * @np: device_node for which to get the phy
  * @index: the index of the phy
  *
  * Returns the phy associated with the given phandle value,
@@ -250,20 +250,17 @@ EXPORT_SYMBOL_GPL(phy_power_off);
  * not yet loaded. This function uses of_xlate call back function provided
  * while registering the phy_provider to find the phy instance.
  */
-static struct phy *of_phy_get(struct device *dev, int index)
+static struct phy *_of_phy_get(struct device_node *np, int index)
 {
 	int ret;
 	struct phy_provider *phy_provider;
 	struct phy *phy = NULL;
 	struct of_phandle_args args;
 
-	ret = of_parse_phandle_with_args(dev->of_node, "phys", "#phy-cells",
+	ret = of_parse_phandle_with_args(np, "phys", "#phy-cells",
 		index, &args);
-	if (ret) {
-		dev_dbg(dev, "failed to get phy in %s node\n",
-			dev->of_node->full_name);
+	if (ret)
 		return ERR_PTR(-ENODEV);
-	}
 
 	mutex_lock(&phy_provider_mutex);
 	phy_provider = of_phy_provider_lookup(args.np);
@@ -283,6 +280,36 @@ err0:
 }
 
 /**
+ * of_phy_get() - lookup and obtain a reference to a phy using a device_node.
+ * @np: device_node for which to get the phy
+ * @con_id: name of the phy from device's point of view
+ *
+ * Returns the phy driver, after getting a refcount to it; or
+ * -ENODEV if there is no such phy. The caller is responsible for
+ * calling phy_put() to release that count.
+ */
+struct phy *of_phy_get(struct device_node *np, const char *con_id)
+{
+	struct phy *phy = NULL;
+	int index = 0;
+
+	if (con_id)
+		index = of_property_match_string(np, "phy-names", con_id);
+
+	phy = _of_phy_get(np, index);
+	if (IS_ERR(phy))
+		return phy;
+
+	if (!try_module_get(phy->ops->owner))
+		return ERR_PTR(-EPROBE_DEFER);
+
+	get_device(&phy->dev);
+
+	return phy;
+}
+EXPORT_SYMBOL_GPL(of_phy_get);
+
+/**
  * phy_put() - release the PHY
  * @phy: the phy returned by phy_get()
  *
@@ -370,7 +397,7 @@ struct phy *phy_get(struct device *dev, const char *string)
 	if (dev->of_node) {
 		index = of_property_match_string(dev->of_node, "phy-names",
 			string);
-		phy = of_phy_get(dev, index);
+		phy = _of_phy_get(dev->of_node, index);
 		if (IS_ERR(phy)) {
 			dev_err(dev, "unable to find phy\n");
 			return phy;
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index 6d72269..bcb6274 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -131,6 +131,7 @@ struct phy *phy_get(struct device *dev, const char *string);
 struct phy *devm_phy_get(struct device *dev, const char *string);
 void phy_put(struct phy *phy);
 void devm_phy_put(struct device *dev, struct phy *phy);
+struct phy *of_phy_get(struct device_node *np, const char *con_id);
 struct phy *of_phy_simple_xlate(struct device *dev,
 	struct of_phandle_args *args);
 struct phy *phy_create(struct device *dev, const struct phy_ops *ops,
-- 
1.7.9.5

[PATCH v4 2/9] phy: core: Add devm_of_phy_get to phy-core

[Kamil Debski]

Adding devm_of_phy_get will allow to get phys by supplying a
pointer to the struct device_node instead of struct device.

Signed-off-by: Kamil Debski <k.debski@samsung.com>
---
 drivers/phy/phy-core.c  |   31 +++++++++++++++++++++++++++++++
 include/linux/phy/phy.h |    2 ++
 2 files changed, 33 insertions(+)

diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
index d6f8c34..0551cc3 100644
--- a/drivers/phy/phy-core.c
+++ b/drivers/phy/phy-core.c
@@ -450,6 +450,37 @@ struct phy *devm_phy_get(struct device *dev, const char *string)
 EXPORT_SYMBOL_GPL(devm_phy_get);
 
 /**
+ * devm_of_phy_get() - lookup and obtain a reference to a phy.
+ * @dev: device that requests this phy
+ * @np: node containing the phy
+ * @con_id: name of the phy from device's point of view
+ *
+ * Gets the phy using of_phy_get(), and associates a device with it using
+ * devres. On driver detach, release function is invoked on the devres data,
+ * then, devres data is freed.
+ */
+struct phy *devm_of_phy_get(struct device *dev, struct device_node *np,
+			    const char *con_id)
+{
+	struct phy **ptr, *phy;
+
+	ptr = devres_alloc(devm_phy_release, sizeof(*ptr), GFP_KERNEL);
+	if (!ptr)
+		return ERR_PTR(-ENOMEM);
+
+	phy = of_phy_get(np, con_id);
+	if (!IS_ERR(phy)) {
+		*ptr = phy;
+		devres_add(dev, ptr);
+	} else {
+		devres_free(ptr);
+	}
+
+	return phy;
+}
+EXPORT_SYMBOL_GPL(devm_of_phy_get);
+
+/**
  * phy_create() - create a new phy
  * @dev: device that is creating the new phy
  * @ops: function pointers for performing phy operations
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index bcb6274..864914c 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -129,6 +129,8 @@ int phy_power_on(struct phy *phy);
 int phy_power_off(struct phy *phy);
 struct phy *phy_get(struct device *dev, const char *string);
 struct phy *devm_phy_get(struct device *dev, const char *string);
+struct phy *devm_of_phy_get(struct device *dev, struct device_node *np,
+			    const char *con_id);
 void phy_put(struct phy *phy);
 void devm_phy_put(struct device *dev, struct phy *phy);
 struct phy *of_phy_get(struct device_node *np, const char *con_id);
-- 
1.7.9.5

[PATCH v5 3/9] phy: Add new Exynos USB 2.0 PHY driver

[Kamil Debski]

Add a new driver for the Exynos USB 2.0 PHY. The new driver uses the generic
PHY framework. The driver includes support for the Exynos 4x10 and 4x12
SoC families.

Signed-off-by: Kamil Debski <k.debski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 .../devicetree/bindings/phy/samsung-phy.txt        |   55 ++++
 drivers/phy/Kconfig                                |   29 ++
 drivers/phy/Makefile                               |    3 +
 drivers/phy/phy-exynos4210-usb2.c                  |  257 ++++++++++++++++
 drivers/phy/phy-exynos4212-usb2.c                  |  306 ++++++++++++++++++++
 drivers/phy/phy-samsung-usb2.c                     |  226 +++++++++++++++
 drivers/phy/phy-samsung-usb2.h                     |   67 +++++
 7 files changed, 943 insertions(+)
 create mode 100644 drivers/phy/phy-exynos4210-usb2.c
 create mode 100644 drivers/phy/phy-exynos4212-usb2.c
 create mode 100644 drivers/phy/phy-samsung-usb2.c
 create mode 100644 drivers/phy/phy-samsung-usb2.h

diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index c0fccaa..39d52cc 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -20,3 +20,58 @@ Required properties:
 - compatible : should be "samsung,exynos5250-dp-video-phy";
 - reg : offset and length of the Display Port PHY register set;
 - #phy-cells : from the generic PHY bindings, must be 0;
+
+Samsung S5P/EXYNOS SoC series USB PHY
+-------------------------------------------------
+
+Required properties:
+- compatible : should be one of the listed compatibles:
+	- "samsung,exynos4210-usb2-phy"
+	- "samsung,exynos4212-usb2-phy"
+- reg : a list of registers used by phy driver
+	- first and obligatory is the location of phy modules registers
+- samsung,sysreg-phandle - handle to syscon used to control the system registers
+- samsung,pmureg-phandle - handle to syscon used to control PMU registers
+- #phy-cells : from the generic phy bindings, must be 1;
+- clocks and clock-names:
+	- the "phy" clocks is required by the phy module
+	- next for each of the phys a clock has to be assigned, this clock
+	  will be used to determine clocking frequency for the phys
+	  (the labels are specified in the paragraph below)
+
+The first phandle argument in the PHY specifier identifies the PHY, its
+meaning is compatible dependent. For the currently supported SoCs (Exynos 4210
+and Exynos 4212) it is as follows:
+  0 - USB device ("device"),
+  1 - USB host ("host"),
+  2 - HSIC0 ("hsic0"),
+  3 - HSIC1 ("hsic1"),
+
+Exynos 4210 and Exynos 4212 use mode switching and require that mode switch
+register is supplied.
+
+Example:
+
+For Exynos 4412 (compatible with Exynos 4212):
+
+usbphy: phy@125b0000 {
+	compatible = "samsung,exynos4212-usb2-phy";
+	reg = <0x125b0000 0x100 0x10020704 0x0c 0x1001021c 0x4>;
+	clocks = <&clock 305>, <&clock 2>, <&clock 2>, <&clock 2>,
+							<&clock 2>;
+	clock-names = "phy", "device", "host", "hsic0", "hsic1";
+	status = "okay";
+	#phy-cells = <1>;
+	samsung,sysreg-phandle = <&sys_reg>;
+	samsung,pmureg-phandle = <&pmu_reg>;
+};
+
+Then the PHY can be used in other nodes such as:
+
+phy-consumer@12340000 {
+	phys = <&usbphy 2>;
+	phy-names = "phy";
+};
+
+Refer to DT bindings documentation of particular PHY consumer devices for more
+information about required PHYs and the way of specification.
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index a344f3d..8e5cce1 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -51,4 +51,33 @@ config PHY_EXYNOS_DP_VIDEO
 	help
 	  Support for Display Port PHY found on Samsung EXYNOS SoCs.
 
+config PHY_SAMSUNG_USB2
+	tristate "Samsung USB 2.0 PHY driver"
+	select GENERIC_PHY
+	select MFD_SYSCON
+	help
+	  Enable this to support the Samsung USB 2.0 PHY driver for Samsung
+	  SoCs. This driver provides the interface for USB 2.0 PHY. Support for
+	  particular SoCs has to be enabled in addition to this driver. Number
+	  and type of supported phys depends on the SoC.
+
+config PHY_EXYNOS4210_USB2
+	bool "Support for Exynos 4210"
+	depends on PHY_SAMSUNG_USB2
+	depends on CPU_EXYNOS4210
+	help
+	  Enable USB PHY support for Exynos 4210. This option requires that
+	  Samsung USB 2.0 PHY driver is enabled and means that support for this
+	  particular SoC is compiled in the driver. In case of Exynos 4210 four
+	  phys are available - device, host, HSCI0 and HSCI1.
+
+config PHY_EXYNOS4212_USB2
+	bool "Support for Exynos 4212"
+	depends on PHY_SAMSUNG_USB2
+	depends on (SOC_EXYNOS4212 || SOC_EXYNOS4412)
+	help
+	  Enable USB PHY support for Exynos 4212. This option requires that
+	  Samsung USB 2.0 PHY driver is enabled and means that support for this
+	  particular SoC is compiled in the driver. In case of Exynos 4212 four
+	  phys are available - device, host, HSIC0 and HSIC1.
 endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index d0caae9..9f4befd 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -7,3 +7,6 @@ obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO)	+= phy-exynos-dp-video.o
 obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)	+= phy-exynos-mipi-video.o
 obj-$(CONFIG_OMAP_USB2)			+= phy-omap-usb2.o
 obj-$(CONFIG_TWL4030_USB)		+= phy-twl4030-usb.o
+obj-$(CONFIG_PHY_SAMSUNG_USB2)		+= phy-samsung-usb2.o
+obj-$(CONFIG_PHY_EXYNOS4210_USB2)	+= phy-exynos4210-usb2.o
+obj-$(CONFIG_PHY_EXYNOS4212_USB2)	+= phy-exynos4212-usb2.o
diff --git a/drivers/phy/phy-exynos4210-usb2.c b/drivers/phy/phy-exynos4210-usb2.c
new file mode 100644
index 0000000..1c8f63f
--- /dev/null
+++ b/drivers/phy/phy-exynos4210-usb2.c
@@ -0,0 +1,257 @@
+/*
+ * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 4210 support
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Author: Kamil Debski <k.debski@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+#include "phy-samsung-usb2.h"
+
+/* Exynos USB PHY registers */
+
+/* PHY power control */
+#define EXYNOS_4210_UPHYPWR			0x0
+
+#define EXYNOS_4210_UPHYPWR_PHY0_SUSPEND	BIT(0)
+#define EXYNOS_4210_UPHYPWR_PHY0_PWR		BIT(3)
+#define EXYNOS_4210_UPHYPWR_PHY0_OTG_PWR	BIT(4)
+#define EXYNOS_4210_UPHYPWR_PHY0_SLEEP		BIT(5)
+#define EXYNOS_4210_UPHYPWR_PHY0	( \
+	EXYNOS_4210_UPHYPWR_PHY0_SUSPEND | \
+	EXYNOS_4210_UPHYPWR_PHY0_PWR | \
+	EXYNOS_4210_UPHYPWR_PHY0_OTG_PWR | \
+	EXYNOS_4210_UPHYPWR_PHY0_SLEEP)
+
+#define EXYNOS_4210_UPHYPWR_PHY1_SUSPEND	BIT(6)
+#define EXYNOS_4210_UPHYPWR_PHY1_PWR		BIT(7)
+#define EXYNOS_4210_UPHYPWR_PHY1_SLEEP		BIT(8)
+#define EXYNOS_4210_UPHYPWR_PHY1 ( \
+	EXYNOS_4210_UPHYPWR_PHY1_SUSPEND | \
+	EXYNOS_4210_UPHYPWR_PHY1_PWR | \
+	EXYNOS_4210_UPHYPWR_PHY1_SLEEP)
+
+#define EXYNOS_4210_UPHYPWR_HSCI0_SUSPEND	BIT(9)
+#define EXYNOS_4210_UPHYPWR_HSCI0_SLEEP		BIT(10)
+#define EXYNOS_4210_UPHYPWR_HSCI0 ( \
+	EXYNOS_4210_UPHYPWR_HSCI0_SUSPEND | \
+	EXYNOS_4210_UPHYPWR_HSCI0_SLEEP)
+
+#define EXYNOS_4210_UPHYPWR_HSCI1_SUSPEND	BIT(11)
+#define EXYNOS_4210_UPHYPWR_HSCI1_SLEEP		BIT(12)
+#define EXYNOS_4210_UPHYPWR_HSCI1 ( \
+	EXYNOS_4210_UPHYPWR_HSCI1_SUSPEND | \
+	EXYNOS_4210_UPHYPWR_HSCI1_SLEEP)
+
+/* PHY clock control */
+#define EXYNOS_4210_UPHYCLK			0x4
+
+#define EXYNOS_4210_UPHYCLK_PHYFSEL_MASK	(0x3 << 0)
+#define EXYNOS_4210_UPHYCLK_PHYFSEL_48MHZ	(0x0 << 0)
+#define EXYNOS_4210_UPHYCLK_PHYFSEL_24MHZ	(0x3 << 0)
+#define EXYNOS_4210_UPHYCLK_PHYFSEL_12MHZ	(0x2 << 0)
+
+#define EXYNOS_4210_UPHYCLK_PHY0_ID_PULLUP	BIT(2)
+#define EXYNOS_4210_UPHYCLK_PHY0_COMMON_ON	BIT(4)
+#define EXYNOS_4210_UPHYCLK_PHY1_COMMON_ON	BIT(7)
+
+/* PHY reset control */
+#define EXYNOS_4210_UPHYRST			0x8
+
+#define EXYNOS_4210_URSTCON_PHY0		BIT(0)
+#define EXYNOS_4210_URSTCON_OTG_HLINK		BIT(1)
+#define EXYNOS_4210_URSTCON_OTG_PHYLINK		BIT(2)
+#define EXYNOS_4210_URSTCON_PHY1_ALL		BIT(3)
+#define EXYNOS_4210_URSTCON_PHY1_P0		BIT(4)
+#define EXYNOS_4210_URSTCON_PHY1_P1P2		BIT(5)
+#define EXYNOS_4210_URSTCON_HOST_LINK_ALL	BIT(6)
+#define EXYNOS_4210_URSTCON_HOST_LINK_P0	BIT(7)
+#define EXYNOS_4210_URSTCON_HOST_LINK_P1	BIT(8)
+#define EXYNOS_4210_URSTCON_HOST_LINK_P2	BIT(9)
+
+/* Isolation, configured in the power management unit */
+#define EXYNOS_4210_USB_ISOL_DEVICE_OFFSET	0x704
+#define EXYNOS_4210_USB_ISOL_DEVICE		BIT(0)
+#define EXYNOS_4210_USB_ISOL_HOST_OFFSET	0x708
+#define EXYNOS_4210_USB_ISOL_HOST		BIT(0)
+
+/* USBYPHY1 Floating prevention */
+#define EXYNOS_4210_UPHY1CON			0x34
+#define EXYNOS_4210_UPHY1CON_FLOAT_PREVENTION	0x1
+
+/* Mode switching SUB Device <-> Host */
+#define EXYNOS_4210_MODE_SWITCH_OFFSET		0x21c
+#define EXYNOS_4210_MODE_SWITCH_MASK		1
+#define EXYNOS_4210_MODE_SWITCH_DEVICE		0
+#define EXYNOS_4210_MODE_SWITCH_HOST		1
+
+enum exynos4210_phy_id {
+	EXYNOS4210_DEVICE,
+	EXYNOS4210_HOST,
+	EXYNOS4210_HSIC0,
+	EXYNOS4210_HSIC1,
+	EXYNOS4210_NUM_PHYS,
+};
+
+/*
+ * exynos4210_rate_to_clk() converts the supplied clock rate to the value that
+ * can be written to the phy register.
+ */
+static int exynos4210_rate_to_clk(unsigned long rate, u32 *reg)
+{
+	switch (rate) {
+	case 12 * MHZ:
+		*reg = EXYNOS_4210_UPHYCLK_PHYFSEL_12MHZ;
+		break;
+	case 24 * MHZ:
+		*reg = EXYNOS_4210_UPHYCLK_PHYFSEL_24MHZ;
+		break;
+	case 48 * MHZ:
+		*reg = EXYNOS_4210_UPHYCLK_PHYFSEL_48MHZ;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static void exynos4210_isol(struct samsung_usb2_phy_instance *inst, bool on)
+{
+	struct samsung_usb2_phy_driver *drv = inst->drv;
+	u32 offset;
+	u32 mask;
+
+	switch (inst->cfg->id) {
+	case EXYNOS4210_DEVICE:
+		offset = EXYNOS_4210_USB_ISOL_DEVICE_OFFSET;
+		mask = EXYNOS_4210_USB_ISOL_DEVICE;
+		break;
+	case EXYNOS4210_HOST:
+		offset = EXYNOS_4210_USB_ISOL_HOST_OFFSET;
+		mask = EXYNOS_4210_USB_ISOL_HOST;
+		break;
+	default:
+		return;
+	};
+
+	regmap_update_bits(drv->reg_pmu, offset, mask, on ? 0 : mask);
+}
+
+static void exynos4210_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on)
+{
+	struct samsung_usb2_phy_driver *drv = inst->drv;
+	u32 rstbits = 0;
+	u32 phypwr = 0;
+	u32 rst;
+	u32 pwr;
+
+	switch (inst->cfg->id) {
+	case EXYNOS4210_DEVICE:
+		phypwr =	EXYNOS_4210_UPHYPWR_PHY0;
+		rstbits =	EXYNOS_4210_URSTCON_PHY0;
+		break;
+	case EXYNOS4210_HOST:
+		phypwr =	EXYNOS_4210_UPHYPWR_PHY1;
+		rstbits =	EXYNOS_4210_URSTCON_PHY1_ALL |
+				EXYNOS_4210_URSTCON_PHY1_P0 |
+				EXYNOS_4210_URSTCON_PHY1_P1P2 |
+				EXYNOS_4210_URSTCON_HOST_LINK_ALL |
+				EXYNOS_4210_URSTCON_HOST_LINK_P0;
+		writel(on, drv->reg_phy + EXYNOS_4210_UPHY1CON);
+		break;
+	case EXYNOS4210_HSIC0:
+		phypwr =	EXYNOS_4210_UPHYPWR_HSCI0;
+		rstbits =	EXYNOS_4210_URSTCON_PHY1_P1P2 |
+				EXYNOS_4210_URSTCON_HOST_LINK_P1;
+		break;
+	case EXYNOS4210_HSIC1:
+		phypwr =	EXYNOS_4210_UPHYPWR_HSCI1;
+		rstbits =	EXYNOS_4210_URSTCON_PHY1_P1P2 |
+				EXYNOS_4210_URSTCON_HOST_LINK_P2;
+		break;
+	};
+
+	if (on) {
+		writel(inst->clk_reg_val, drv->reg_phy + EXYNOS_4210_UPHYCLK);
+
+		pwr = readl(drv->reg_phy + EXYNOS_4210_UPHYPWR);
+		pwr &= ~phypwr;
+		writel(pwr, drv->reg_phy + EXYNOS_4210_UPHYPWR);
+
+		rst = readl(drv->reg_phy + EXYNOS_4210_UPHYRST);
+		rst |= rstbits;
+		writel(rst, drv->reg_phy + EXYNOS_4210_UPHYRST);
+		udelay(10);
+		rst &= ~rstbits;
+		writel(rst, drv->reg_phy + EXYNOS_4210_UPHYRST);
+	} else {
+		pwr = readl(drv->reg_phy + EXYNOS_4210_UPHYPWR);
+		pwr |= phypwr;
+		writel(pwr, drv->reg_phy + EXYNOS_4210_UPHYPWR);
+	}
+}
+
+static int exynos4210_power_on(struct samsung_usb2_phy_instance *inst)
+{
+	/* Order of initialisation is important - first power then isolation */
+	exynos4210_phy_pwr(inst, 1);
+	exynos4210_isol(inst, 0);
+
+	return 0;
+}
+
+static int exynos4210_power_off(struct samsung_usb2_phy_instance *inst)
+{
+	exynos4210_isol(inst, 1);
+	exynos4210_phy_pwr(inst, 0);
+
+	return 0;
+}
+
+
+static const struct samsung_usb2_common_phy exynos4210_phys[] = {
+	{
+		.label		= "device",
+		.id		= EXYNOS4210_DEVICE,
+		.rate_to_clk	= exynos4210_rate_to_clk,
+		.power_on	= exynos4210_power_on,
+		.power_off	= exynos4210_power_off,
+	},
+	{
+		.label		= "host",
+		.id		= EXYNOS4210_HOST,
+		.rate_to_clk	= exynos4210_rate_to_clk,
+		.power_on	= exynos4210_power_on,
+		.power_off	= exynos4210_power_off,
+	},
+	{
+		.label		= "hsic0",
+		.id		= EXYNOS4210_HSIC0,
+		.rate_to_clk	= exynos4210_rate_to_clk,
+		.power_on	= exynos4210_power_on,
+		.power_off	= exynos4210_power_off,
+	},
+	{
+		.label		= "hsic1",
+		.id		= EXYNOS4210_HSIC1,
+		.rate_to_clk	= exynos4210_rate_to_clk,
+		.power_on	= exynos4210_power_on,
+		.power_off	= exynos4210_power_off,
+	},
+	{},
+};
+
+const struct samsung_usb2_phy_config exynos4210_usb2_phy_config = {
+	.num_phys		= EXYNOS4210_NUM_PHYS,
+	.phys			= exynos4210_phys,
+	.has_mode_switch	= 1,
+};
+
diff --git a/drivers/phy/phy-exynos4212-usb2.c b/drivers/phy/phy-exynos4212-usb2.c
new file mode 100644
index 0000000..50f809c
--- /dev/null
+++ b/drivers/phy/phy-exynos4212-usb2.c
@@ -0,0 +1,306 @@
+/*
+ * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 4212 support
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Author: Kamil Debski <k.debski@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+#include "phy-samsung-usb2.h"
+
+/* Exynos USB PHY registers */
+
+/* PHY power control */
+#define EXYNOS_4212_UPHYPWR			0x0
+
+#define EXYNOS_4212_UPHYPWR_PHY0_SUSPEND	BIT(0)
+#define EXYNOS_4212_UPHYPWR_PHY0_PWR		BIT(3)
+#define EXYNOS_4212_UPHYPWR_PHY0_OTG_PWR	BIT(4)
+#define EXYNOS_4212_UPHYPWR_PHY0_SLEEP		BIT(5)
+#define EXYNOS_4212_UPHYPWR_PHY0 ( \
+	EXYNOS_4212_UPHYPWR_PHY0_SUSPEND | \
+	EXYNOS_4212_UPHYPWR_PHY0_PWR | \
+	EXYNOS_4212_UPHYPWR_PHY0_OTG_PWR | \
+	EXYNOS_4212_UPHYPWR_PHY0_SLEEP)
+
+#define EXYNOS_4212_UPHYPWR_PHY1_SUSPEND	BIT(6)
+#define EXYNOS_4212_UPHYPWR_PHY1_PWR		BIT(7)
+#define EXYNOS_4212_UPHYPWR_PHY1_SLEEP		BIT(8)
+#define EXYNOS_4212_UPHYPWR_PHY1 ( \
+	EXYNOS_4212_UPHYPWR_PHY1_SUSPEND | \
+	EXYNOS_4212_UPHYPWR_PHY1_PWR | \
+	EXYNOS_4212_UPHYPWR_PHY1_SLEEP)
+
+#define EXYNOS_4212_UPHYPWR_HSCI0_SUSPEND	BIT(9)
+#define EXYNOS_4212_UPHYPWR_HSCI0_PWR		BIT(10)
+#define EXYNOS_4212_UPHYPWR_HSCI0_SLEEP		BIT(11)
+#define EXYNOS_4212_UPHYPWR_HSCI0 ( \
+	EXYNOS_4212_UPHYPWR_HSCI0_SUSPEND | \
+	EXYNOS_4212_UPHYPWR_HSCI0_PWR | \
+	EXYNOS_4212_UPHYPWR_HSCI0_SLEEP)
+
+#define EXYNOS_4212_UPHYPWR_HSCI1_SUSPEND	BIT(12)
+#define EXYNOS_4212_UPHYPWR_HSCI1_PWR		BIT(13)
+#define EXYNOS_4212_UPHYPWR_HSCI1_SLEEP		BIT(14)
+#define EXYNOS_4212_UPHYPWR_HSCI1 ( \
+	EXYNOS_4212_UPHYPWR_HSCI1_SUSPEND | \
+	EXYNOS_4212_UPHYPWR_HSCI1_PWR | \
+	EXYNOS_4212_UPHYPWR_HSCI1_SLEEP)
+
+/* PHY clock control */
+#define EXYNOS_4212_UPHYCLK			0x4
+
+#define EXYNOS_4212_UPHYCLK_PHYFSEL_MASK	(0x7 << 0)
+#define EXYNOS_4212_UPHYCLK_PHYFSEL_9MHZ6	(0x0 << 0)
+#define EXYNOS_4212_UPHYCLK_PHYFSEL_10MHZ	(0x1 << 0)
+#define EXYNOS_4212_UPHYCLK_PHYFSEL_12MHZ	(0x2 << 0)
+#define EXYNOS_4212_UPHYCLK_PHYFSEL_19MHZ2	(0x3 << 0)
+#define EXYNOS_4212_UPHYCLK_PHYFSEL_20MHZ	(0x4 << 0)
+#define EXYNOS_4212_UPHYCLK_PHYFSEL_24MHZ	(0x5 << 0)
+#define EXYNOS_4212_UPHYCLK_PHYFSEL_50MHZ	(0x7 << 0)
+
+#define EXYNOS_4212_UPHYCLK_PHY0_ID_PULLUP	BIT(3)
+#define EXYNOS_4212_UPHYCLK_PHY0_COMMON_ON	BIT(4)
+#define EXYNOS_4212_UPHYCLK_PHY1_COMMON_ON	BIT(7)
+
+#define EXYNOS_4212_UPHYCLK_HSIC_REFCLK_MASK	(0x7f << 10)
+#define EXYNOS_4212_UPHYCLK_HSIC_REFCLK_12MHZ	(0x24 << 10)
+#define EXYNOS_4212_UPHYCLK_HSIC_REFCLK_15MHZ	(0x1c << 10)
+#define EXYNOS_4212_UPHYCLK_HSIC_REFCLK_16MHZ	(0x1a << 10)
+#define EXYNOS_4212_UPHYCLK_HSIC_REFCLK_19MHZ2	(0x15 << 10)
+#define EXYNOS_4212_UPHYCLK_HSIC_REFCLK_20MHZ	(0x14 << 10)
+
+/* PHY reset control */
+#define EXYNOS_4212_UPHYRST			0x8
+
+#define EXYNOS_4212_URSTCON_PHY0		BIT(0)
+#define EXYNOS_4212_URSTCON_OTG_HLINK		BIT(1)
+#define EXYNOS_4212_URSTCON_OTG_PHYLINK		BIT(2)
+#define EXYNOS_4212_URSTCON_HOST_PHY		BIT(3)
+#define EXYNOS_4212_URSTCON_PHY1		BIT(4)
+#define EXYNOS_4212_URSTCON_HSIC0		BIT(5)
+#define EXYNOS_4212_URSTCON_HSIC1		BIT(6)
+#define EXYNOS_4212_URSTCON_HOST_LINK_ALL	BIT(7)
+#define EXYNOS_4212_URSTCON_HOST_LINK_P0	BIT(8)
+#define EXYNOS_4212_URSTCON_HOST_LINK_P1	BIT(9)
+#define EXYNOS_4212_URSTCON_HOST_LINK_P2	BIT(10)
+
+/* Isolation, configured in the power management unit */
+#define EXYNOS_4212_USB_ISOL_OFFSET		0x704
+#define EXYNOS_4212_USB_ISOL_OTG		BIT(0)
+#define EXYNOS_4212_USB_ISOL_HSIC0_OFFSET	0x708
+#define EXYNOS_4212_USB_ISOL_HSIC0		BIT(0)
+#define EXYNOS_4212_USB_ISOL_HSIC1_OFFSET	0x70c
+#define EXYNOS_4212_USB_ISOL_HSIC1		BIT(0)
+
+/* Mode switching SUB Device <-> Host */
+#define EXYNOS_4212_MODE_SWITCH_OFFSET		0x21c
+#define EXYNOS_4212_MODE_SWITCH_MASK		1
+#define EXYNOS_4212_MODE_SWITCH_DEVICE		0
+#define EXYNOS_4212_MODE_SWITCH_HOST		1
+
+enum exynos4x12_phy_id {
+	EXYNOS4212_DEVICE,
+	EXYNOS4212_HOST,
+	EXYNOS4212_HSIC0,
+	EXYNOS4212_HSIC1,
+	EXYNOS4212_NUM_PHYS,
+};
+
+/*
+ * exynos4212_rate_to_clk() converts the supplied clock rate to the value that
+ * can be written to the phy register.
+ */
+static int exynos4212_rate_to_clk(unsigned long rate, u32 *reg)
+{
+	/* EXYNOS_4212_UPHYCLK_PHYFSEL_MASK */
+
+	switch (rate) {
+	case 9600 * KHZ:
+		*reg = EXYNOS_4212_UPHYCLK_PHYFSEL_9MHZ6;
+		break;
+	case 10 * MHZ:
+		*reg = EXYNOS_4212_UPHYCLK_PHYFSEL_10MHZ;
+		break;
+	case 12 * MHZ:
+		*reg = EXYNOS_4212_UPHYCLK_PHYFSEL_12MHZ;
+		break;
+	case 19200 * KHZ:
+		*reg = EXYNOS_4212_UPHYCLK_PHYFSEL_19MHZ2;
+		break;
+	case 20 * MHZ:
+		*reg = EXYNOS_4212_UPHYCLK_PHYFSEL_20MHZ;
+		break;
+	case 24 * MHZ:
+		*reg = EXYNOS_4212_UPHYCLK_PHYFSEL_24MHZ;
+		break;
+	case 50 * MHZ:
+		*reg = EXYNOS_4212_UPHYCLK_PHYFSEL_50MHZ;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static void exynos4212_isol(struct samsung_usb2_phy_instance *inst, bool on)
+{
+	struct samsung_usb2_phy_driver *drv = inst->drv;
+	u32 offset;
+	u32 mask;
+
+	switch (inst->cfg->id) {
+	case EXYNOS4212_DEVICE:
+	case EXYNOS4212_HOST:
+		offset = EXYNOS_4212_USB_ISOL_OFFSET;
+		mask = EXYNOS_4212_USB_ISOL_OTG;
+		break;
+	case EXYNOS4212_HSIC0:
+		offset = EXYNOS_4212_USB_ISOL_HSIC0_OFFSET;
+		mask = EXYNOS_4212_USB_ISOL_HSIC0;
+		break;
+	case EXYNOS4212_HSIC1:
+		offset = EXYNOS_4212_USB_ISOL_HSIC1_OFFSET;
+		mask = EXYNOS_4212_USB_ISOL_HSIC1;
+		break;
+	default:
+		return;
+	};
+
+	regmap_update_bits(drv->reg_pmu, offset, mask, on ? 0 : mask);
+}
+
+static void exynos4212_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on)
+{
+	struct samsung_usb2_phy_driver *drv = inst->drv;
+	u32 rstbits = 0;
+	u32 phypwr = 0;
+	u32 rst;
+	u32 pwr;
+
+	switch (inst->cfg->id) {
+	case EXYNOS4212_DEVICE:
+		phypwr =	EXYNOS_4212_UPHYPWR_PHY0;
+		rstbits =	EXYNOS_4212_URSTCON_PHY0;
+		break;
+	case EXYNOS4212_HOST:
+		phypwr =	EXYNOS_4212_UPHYPWR_PHY1;
+		rstbits =	EXYNOS_4212_URSTCON_HOST_PHY;
+		break;
+	case EXYNOS4212_HSIC0:
+		phypwr =	EXYNOS_4212_UPHYPWR_HSCI0;
+		rstbits =	EXYNOS_4212_URSTCON_HSIC1 |
+				EXYNOS_4212_URSTCON_HOST_LINK_P0 |
+				EXYNOS_4212_URSTCON_HOST_PHY;
+		break;
+	case EXYNOS4212_HSIC1:
+		phypwr =	EXYNOS_4212_UPHYPWR_HSCI1;
+		rstbits =	EXYNOS_4212_URSTCON_HSIC1 |
+				EXYNOS_4212_URSTCON_HOST_LINK_P1;
+		break;
+	};
+
+	if (on) {
+		writel(inst->clk_reg_val, drv->reg_phy + EXYNOS_4212_UPHYCLK);
+
+		pwr = readl(drv->reg_phy + EXYNOS_4212_UPHYPWR);
+		pwr &= ~phypwr;
+		writel(pwr, drv->reg_phy + EXYNOS_4212_UPHYPWR);
+
+		rst = readl(drv->reg_phy + EXYNOS_4212_UPHYRST);
+		rst |= rstbits;
+		writel(rst, drv->reg_phy + EXYNOS_4212_UPHYRST);
+		udelay(10);
+		rst &= ~rstbits;
+		writel(rst, drv->reg_phy + EXYNOS_4212_UPHYRST);
+	} else {
+		pwr = readl(drv->reg_phy + EXYNOS_4212_UPHYPWR);
+		pwr |= phypwr;
+		writel(pwr, drv->reg_phy + EXYNOS_4212_UPHYPWR);
+	}
+}
+
+static int exynos4212_power_on(struct samsung_usb2_phy_instance *inst)
+{
+	struct samsung_usb2_phy_driver *drv = inst->drv;
+
+	inst->enabled = 1;
+	exynos4212_phy_pwr(inst, 1);
+	exynos4212_isol(inst, 0);
+
+	/* Power on the device, as it is necessary for HSIC to work */
+	if (inst->cfg->id == EXYNOS4212_HSIC0) {
+		struct samsung_usb2_phy_instance *device =
+					&drv->instances[EXYNOS4212_DEVICE];
+		exynos4212_phy_pwr(device, 1);
+		exynos4212_isol(device, 0);
+	}
+
+	return 0;
+}
+
+static int exynos4212_power_off(struct samsung_usb2_phy_instance *inst)
+{
+	struct samsung_usb2_phy_driver *drv = inst->drv;
+	struct samsung_usb2_phy_instance *device =
+					&drv->instances[EXYNOS4212_DEVICE];
+
+	inst->enabled = 0;
+	exynos4212_isol(inst, 1);
+	exynos4212_phy_pwr(inst, 0);
+
+	if (inst->cfg->id == EXYNOS4212_HSIC0 && !device->enabled) {
+		exynos4212_isol(device, 1);
+		exynos4212_phy_pwr(device, 0);
+	}
+
+	return 0;
+}
+
+
+static const struct samsung_usb2_common_phy exynos4212_phys[] = {
+	{
+		.label		= "device",
+		.id		= EXYNOS4212_DEVICE,
+		.rate_to_clk	= exynos4212_rate_to_clk,
+		.power_on	= exynos4212_power_on,
+		.power_off	= exynos4212_power_off,
+	},
+	{
+		.label		= "host",
+		.id		= EXYNOS4212_HOST,
+		.rate_to_clk	= exynos4212_rate_to_clk,
+		.power_on	= exynos4212_power_on,
+		.power_off	= exynos4212_power_off,
+	},
+	{
+		.label		= "hsic0",
+		.id		= EXYNOS4212_HSIC0,
+		.rate_to_clk	= exynos4212_rate_to_clk,
+		.power_on	= exynos4212_power_on,
+		.power_off	= exynos4212_power_off,
+	},
+	{
+		.label		= "hsic1",
+		.id		= EXYNOS4212_HSIC1,
+		.rate_to_clk	= exynos4212_rate_to_clk,
+		.power_on	= exynos4212_power_on,
+		.power_off	= exynos4212_power_off,
+	},
+	{},
+};
+
+const struct samsung_usb2_phy_config exynos4212_usb2_phy_config = {
+	.num_phys		= EXYNOS4212_NUM_PHYS,
+	.phys			= exynos4212_phys,
+	.has_mode_switch	= 1,
+};
+
diff --git a/drivers/phy/phy-samsung-usb2.c b/drivers/phy/phy-samsung-usb2.c
new file mode 100644
index 0000000..3c09e0e
--- /dev/null
+++ b/drivers/phy/phy-samsung-usb2.c
@@ -0,0 +1,226 @@
+/*
+ * Samsung SoC USB 1.1/2.0 PHY driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Author: Kamil Debski <k.debski@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include "phy-samsung-usb2.h"
+
+static int samsung_usb2_phy_power_on(struct phy *phy)
+{
+	struct samsung_usb2_phy_instance *inst = phy_get_drvdata(phy);
+	struct samsung_usb2_phy_driver *drv = inst->drv;
+	int ret;
+
+	dev_dbg(drv->dev, "Request to power_on \"%s\" usb phy\n",
+							inst->cfg->label);
+	ret = clk_prepare_enable(drv->clk);
+	if (ret)
+		goto err_main_clk;
+	ret = clk_prepare_enable(inst->clk);
+	if (ret)
+		goto err_instance_clk;
+	inst->rate = clk_get_rate(inst->clk);
+	if (inst->cfg->rate_to_clk) {
+		ret = inst->cfg->rate_to_clk(inst->rate, &inst->clk_reg_val);
+		if (ret)
+			goto err_get_rate;
+	}
+	if (inst->cfg->power_on) {
+		spin_lock(&drv->lock);
+		ret = inst->cfg->power_on(inst);
+		spin_unlock(&drv->lock);
+	}
+
+	return 0;
+
+err_get_rate:
+	clk_disable_unprepare(inst->clk);
+err_instance_clk:
+	clk_disable_unprepare(drv->clk);
+err_main_clk:
+	return ret;
+}
+
+static int samsung_usb2_phy_power_off(struct phy *phy)
+{
+	struct samsung_usb2_phy_instance *inst = phy_get_drvdata(phy);
+	struct samsung_usb2_phy_driver *drv = inst->drv;
+	int ret = 0;
+
+	dev_dbg(drv->dev, "Request to power_off \"%s\" usb phy\n",
+							inst->cfg->label);
+	if (inst->cfg->power_off) {
+		spin_lock(&drv->lock);
+		ret = inst->cfg->power_off(inst);
+		spin_unlock(&drv->lock);
+	}
+	clk_disable_unprepare(inst->clk);
+	clk_disable_unprepare(drv->clk);
+	return ret;
+}
+
+static struct phy_ops samsung_usb2_phy_ops = {
+	.power_on	= samsung_usb2_phy_power_on,
+	.power_off	= samsung_usb2_phy_power_off,
+	.owner		= THIS_MODULE,
+};
+
+static struct phy *samsung_usb2_phy_xlate(struct device *dev,
+					struct of_phandle_args *args)
+{
+	struct samsung_usb2_phy_driver *drv;
+
+	drv = dev_get_drvdata(dev);
+	if (!drv)
+		return ERR_PTR(-EINVAL);
+
+	if (WARN_ON(args->args[0] >= drv->cfg->num_phys))
+		return ERR_PTR(-ENODEV);
+
+	return drv->instances[args->args[0]].phy;
+}
+
+static const struct of_device_id samsung_usb2_phy_of_match[] = {
+#ifdef CONFIG_PHY_EXYNOS4210_USB2
+	{
+		.compatible = "samsung,exynos4210-usb2-phy",
+		.data = &exynos4210_usb2_phy_config,
+	},
+#endif
+#ifdef CONFIG_PHY_EXYNOS4212_USB2
+	{
+		.compatible = "samsung,exynos4212-usb2-phy",
+		.data = &exynos4212_usb2_phy_config,
+	},
+#endif
+	{ },
+};
+
+static int samsung_usb2_phy_probe(struct platform_device *pdev)
+{
+	const struct of_device_id *match;
+	const struct samsung_usb2_phy_config *cfg;
+	struct clk *clk;
+	struct device *dev = &pdev->dev;
+	struct phy_provider *phy_provider;
+	struct resource *mem;
+	struct samsung_usb2_phy_driver *drv;
+	int i;
+
+	if (!pdev->dev.of_node) {
+		dev_err(dev, "This driver is required to be instantiated from device tree\n");
+		return -EINVAL;
+	}
+
+	match = of_match_node(samsung_usb2_phy_of_match, pdev->dev.of_node);
+	if (!match) {
+		dev_err(dev, "of_match_node() failed\n");
+		return -EINVAL;
+	}
+	cfg = match->data;
+
+	drv = devm_kzalloc(dev, sizeof(struct samsung_usb2_phy_driver) +
+		cfg->num_phys * sizeof(struct samsung_usb2_phy_instance),
+								GFP_KERNEL);
+	if (!drv)
+		return -ENOMEM;
+
+	dev_set_drvdata(dev, drv);
+	spin_lock_init(&drv->lock);
+
+	drv->cfg = cfg;
+	drv->dev = dev;
+
+	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	drv->reg_phy = devm_ioremap_resource(dev, mem);
+	if (IS_ERR(drv->reg_phy)) {
+		dev_err(dev, "Failed to map register memory (phy)\n");
+		return PTR_ERR(drv->reg_phy);
+	}
+
+	drv->reg_pmu = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
+		"samsung,pmureg-phandle");
+	if (IS_ERR(drv->reg_pmu)) {
+		dev_err(dev, "Failed to map PMU registers (via syscon)\n");
+		return PTR_ERR(drv->reg_pmu);
+	}
+
+	if (drv->cfg->has_mode_switch) {
+		drv->reg_sys = syscon_regmap_lookup_by_phandle(
+				pdev->dev.of_node, "samsung,sysreg-phandle");
+		if (IS_ERR(drv->reg_sys)) {
+			dev_err(dev, "Failed to map system registers (via syscon)\n");
+			return PTR_ERR(drv->reg_sys);
+		}
+	}
+
+	drv->clk = devm_clk_get(dev, "phy");
+	if (IS_ERR(drv->clk)) {
+		dev_err(dev, "Failed to get clock of phy controller\n");
+		return PTR_ERR(drv->clk);
+	}
+
+	for (i = 0; i < drv->cfg->num_phys; i++) {
+		char *label = drv->cfg->phys[i].label;
+		struct samsung_usb2_phy_instance *p = &drv->instances[i];
+
+		dev_dbg(dev, "Creating phy \"%s\"\n", label);
+		p->phy = devm_phy_create(dev, &samsung_usb2_phy_ops, NULL);
+		if (IS_ERR(p->phy)) {
+			dev_err(drv->dev, "Failed to create usb2_phy \"%s\"\n",
+						label);
+			return PTR_ERR(p->phy);
+		}
+
+		p->cfg = &drv->cfg->phys[i];
+		p->drv = drv;
+		phy_set_drvdata(p->phy, p);
+
+		clk = devm_clk_get(dev, p->cfg->label);
+		if (IS_ERR(clk)) {
+			dev_err(dev, "Failed to get clock of \"%s\" phy\n",
+								p->cfg->label);
+			return PTR_ERR(clk);
+		}
+		p->clk = clk;
+	}
+
+	phy_provider = devm_of_phy_provider_register(dev,
+							samsung_usb2_phy_xlate);
+	if (IS_ERR(phy_provider)) {
+		dev_err(drv->dev, "Failed to register phy provider\n");
+		return PTR_ERR(phy_provider);
+	}
+
+	return 0;
+}
+
+static struct platform_driver samsung_usb2_phy_driver = {
+	.probe	= samsung_usb2_phy_probe,
+	.driver = {
+		.of_match_table	= samsung_usb2_phy_of_match,
+		.name		= "samsung-usb2-phy",
+		.owner		= THIS_MODULE,
+	}
+};
+
+module_platform_driver(samsung_usb2_phy_driver);
+MODULE_DESCRIPTION("Samsung S5P/EXYNOS SoC USB PHY driver");
+MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:samsung-usb2-phy");
+
diff --git a/drivers/phy/phy-samsung-usb2.h b/drivers/phy/phy-samsung-usb2.h
new file mode 100644
index 0000000..ab89f91
--- /dev/null
+++ b/drivers/phy/phy-samsung-usb2.h
@@ -0,0 +1,67 @@
+/*
+ * Samsung SoC USB 1.1/2.0 PHY driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Author: Kamil Debski <k.debski@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _PHY_EXYNOS_USB2_H
+#define _PHY_EXYNOS_USB2_H
+
+#include <linux/clk.h>
+#include <linux/phy/phy.h>
+#include <linux/device.h>
+#include <linux/regmap.h>
+#include <linux/spinlock.h>
+
+#define KHZ 1000
+#define MHZ (KHZ * KHZ)
+
+struct samsung_usb2_phy_driver;
+struct samsung_usb2_phy_instance;
+struct samsung_usb2_phy_config;
+
+struct samsung_usb2_phy_instance {
+	const struct samsung_usb2_common_phy *cfg;
+	struct clk *clk;
+	struct phy *phy;
+	struct samsung_usb2_phy_driver *drv;
+	unsigned long rate;
+	u32 clk_reg_val;
+	bool enabled;
+};
+
+struct samsung_usb2_phy_driver {
+	const struct samsung_usb2_phy_config *cfg;
+	struct clk *clk;
+	struct device *dev;
+	void __iomem *reg_phy;
+	struct regmap *reg_pmu;
+	struct regmap *reg_sys;
+	spinlock_t lock;
+	struct samsung_usb2_phy_instance instances[0];
+};
+
+struct samsung_usb2_common_phy {
+	int (*rate_to_clk)(unsigned long, u32 *);
+	int (*power_on)(struct samsung_usb2_phy_instance *);
+	int (*power_off)(struct samsung_usb2_phy_instance *);
+	unsigned int id;
+	char *label;
+};
+
+
+struct samsung_usb2_phy_config {
+	const struct samsung_usb2_common_phy *phys;
+	unsigned int num_phys;
+	bool has_mode_switch;
+};
+
+extern const struct samsung_usb2_phy_config exynos4210_usb2_phy_config;
+extern const struct samsung_usb2_phy_config exynos4212_usb2_phy_config;
+#endif
+
-- 
1.7.9.5

[PATCH v5 4/9] usb: ehci-s5p: Change to use phy provided by the generic phy framework

[Kamil Debski]

Change the phy provider used from the old one using the USB phy
framework to a new one using the Generic phy framework.

Signed-off-by: Kamil Debski <k.debski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 Documentation/devicetree/bindings/usb/usb-ehci.txt |   35 +++++++
 drivers/usb/host/ehci-exynos.c                     |   97 +++++++++++++-------
 2 files changed, 98 insertions(+), 34 deletions(-)

diff --git a/Documentation/devicetree/bindings/usb/usb-ehci.txt b/Documentation/devicetree/bindings/usb/usb-ehci.txt
index fa18612..413f7cd 100644
--- a/Documentation/devicetree/bindings/usb/usb-ehci.txt
+++ b/Documentation/devicetree/bindings/usb/usb-ehci.txt
@@ -14,6 +14,10 @@ If controller implementation operates with big endian descriptors,
 If both big endian registers and descriptors are used by the controller
 implementation, "big-endian" property can be specified instead of having
 both "big-endian-regs" and "big-endian-desc".
+  - port: if in the SoC there are EHCI phys, they should be listed here.
+One phy per port. Each port should have its reg entry with a consecutive
+number. Also it should contain phys and phy-names entries specifying the
+phy used by the port.
 
 Example (Sequoia 440EPx):
     ehci@e0000300 {
@@ -23,3 +27,34 @@ Example (Sequoia 440EPx):
 	   reg = <0 e0000300 90 0 e0000390 70>;
 	   big-endian;
    };
+
+Example (Exynos 4212):
+    ehci@12580000 {
+        compatible = "samsung,exynos4210-ehci";
+        reg = <0x12580000 0x20000>;
+        interrupts = <0 70 0>;
+        clocks = <&clock 304>, <&clock 305>;
+        clock-names = "usbhost", "otg";
+        status = "disabled";
+        #address-cells = <1>;
+        #size-cells = <0>;
+        port@0 {
+            reg = <0>;
+            phys = <&usb2phy 1>;
+            phy-names = "host";
+            status = "disabled";
+        };
+        port@1 {
+            reg = <1>;
+            phys = <&usb2phy 2>;
+            phy-names = "hsic0";
+            status = "disabled";
+        };
+        port@2 {
+            reg = <2>;
+            phys = <&usb2phy 3>;
+            phy-names = "hsic1";
+            status = "disabled";
+        };
+    };
+
diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c
index d1d8c47..7c35501 100644
--- a/drivers/usb/host/ehci-exynos.c
+++ b/drivers/usb/host/ehci-exynos.c
@@ -19,12 +19,12 @@
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/of_gpio.h>
+#include <linux/phy/phy.h>
 #include <linux/platform_device.h>
 #include <linux/usb/phy.h>
 #include <linux/usb/samsung_usb_phy.h>
 #include <linux/usb.h>
 #include <linux/usb/hcd.h>
-#include <linux/usb/otg.h>
 
 #include "ehci.h"
 
@@ -42,10 +42,10 @@
 static const char hcd_name[] = "ehci-exynos";
 static struct hc_driver __read_mostly exynos_ehci_hc_driver;
 
+#define PHY_NUMBER 3
 struct exynos_ehci_hcd {
 	struct clk *clk;
-	struct usb_phy *phy;
-	struct usb_otg *otg;
+	struct phy *phy[PHY_NUMBER];
 };
 
 #define to_exynos_ehci(hcd) (struct exynos_ehci_hcd *)(hcd_to_ehci(hcd)->priv)
@@ -69,13 +69,43 @@ static void exynos_setup_vbus_gpio(struct platform_device *pdev)
 		dev_err(dev, "can't request ehci vbus gpio %d", gpio);
 }
 
+static int exynos_phys_on(struct phy *p[])
+{
+	int i;
+	int ret = 0;
+
+	for (i = 0; ret == 0 && i < PHY_NUMBER; i++)
+		if (p[i])
+			ret = phy_power_on(p[i]);
+	if (ret)
+		for (i--; i > 0; i--)
+			if (p[i])
+				phy_power_off(p[i]);
+
+	return ret;
+}
+
+static int exynos_phys_off(struct phy *p[])
+{
+	int i;
+	int ret = 0;
+
+	for (i = 0; ret == 0 && i < PHY_NUMBER; i++)
+		if (p[i])
+			ret = phy_power_off(p[i]);
+
+	return ret;
+}
+
 static int exynos_ehci_probe(struct platform_device *pdev)
 {
 	struct exynos_ehci_hcd *exynos_ehci;
 	struct usb_hcd *hcd;
 	struct ehci_hcd *ehci;
 	struct resource *res;
-	struct usb_phy *phy;
+	struct phy *phy;
+	struct device_node *child;
+	int phy_number;
 	int irq;
 	int err;
 
@@ -102,14 +132,26 @@ static int exynos_ehci_probe(struct platform_device *pdev)
 					"samsung,exynos5440-ehci"))
 		goto skip_phy;
 
-	phy = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2);
-	if (IS_ERR(phy)) {
-		usb_put_hcd(hcd);
-		dev_warn(&pdev->dev, "no platform data or transceiver defined\n");
-		return -EPROBE_DEFER;
-	} else {
-		exynos_ehci->phy = phy;
-		exynos_ehci->otg = phy->otg;
+	for_each_available_child_of_node(pdev->dev.of_node, child) {
+		err = of_property_read_u32(child, "reg", &phy_number);
+		if (err) {
+			dev_err(&pdev->dev, "Failed to parse device tree\n");
+			of_node_put(child);
+			return err;
+		}
+		if (phy_number >= PHY_NUMBER) {
+			dev_err(&pdev->dev, "Failed to parse device tree - number out of range\n");
+			of_node_put(child);
+			return -EINVAL;
+		}
+		phy = devm_of_phy_get(&pdev->dev, child, 0);
+		of_node_put(child);
+		if (IS_ERR(phy)) {
+			dev_err(&pdev->dev, "Failed to get phy number %d",
+								phy_number);
+			return PTR_ERR(phy);
+		}
+		exynos_ehci->phy[phy_number] = phy;
 	}
 
 skip_phy:
@@ -149,11 +191,11 @@ skip_phy:
 		goto fail_io;
 	}
 
-	if (exynos_ehci->otg)
-		exynos_ehci->otg->set_host(exynos_ehci->otg, &hcd->self);
-
-	if (exynos_ehci->phy)
-		usb_phy_init(exynos_ehci->phy);
+	err = exynos_phys_on(exynos_ehci->phy);
+	if (err) {
+		dev_err(&pdev->dev, "Failed to enabled phys\n");
+		goto fail_io;
+	}
 
 	ehci = hcd_to_ehci(hcd);
 	ehci->caps = hcd->regs;
@@ -173,8 +215,7 @@ skip_phy:
 	return 0;
 
 fail_add_hcd:
-	if (exynos_ehci->phy)
-		usb_phy_shutdown(exynos_ehci->phy);
+	exynos_phys_off(exynos_ehci->phy);
 fail_io:
 	clk_disable_unprepare(exynos_ehci->clk);
 fail_clk:
@@ -189,11 +230,7 @@ static int exynos_ehci_remove(struct platform_device *pdev)
 
 	usb_remove_hcd(hcd);
 
-	if (exynos_ehci->otg)
-		exynos_ehci->otg->set_host(exynos_ehci->otg, &hcd->self);
-
-	if (exynos_ehci->phy)
-		usb_phy_shutdown(exynos_ehci->phy);
+	exynos_phys_off(exynos_ehci->phy);
 
 	clk_disable_unprepare(exynos_ehci->clk);
 
@@ -213,11 +250,7 @@ static int exynos_ehci_suspend(struct device *dev)
 
 	rc = ehci_suspend(hcd, do_wakeup);
 
-	if (exynos_ehci->otg)
-		exynos_ehci->otg->set_host(exynos_ehci->otg, &hcd->self);
-
-	if (exynos_ehci->phy)
-		usb_phy_shutdown(exynos_ehci->phy);
+	exynos_phys_off(exynos_ehci->phy);
 
 	clk_disable_unprepare(exynos_ehci->clk);
 
@@ -231,11 +264,7 @@ static int exynos_ehci_resume(struct device *dev)
 
 	clk_prepare_enable(exynos_ehci->clk);
 
-	if (exynos_ehci->otg)
-		exynos_ehci->otg->set_host(exynos_ehci->otg, &hcd->self);
-
-	if (exynos_ehci->phy)
-		usb_phy_init(exynos_ehci->phy);
+	exynos_phys_on(exynos_ehci->phy);
 
 	/* DMA burst Enable */
 	writel(EHCI_INSNREG00_ENABLE_DMA_BURST, EHCI_INSNREG00(hcd->regs));
-- 
1.7.9.5

[PATCH v5 5/9] usb: s3c-hsotg: Use the new Exynos USB phy driver with the generic phy framework

[Kamil Debski]

Change the used phy driver to the new Exynos USB phy driver that uses the
generic phy framework.

Signed-off-by: Kamil Debski <k.debski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 .../devicetree/bindings/usb/samsung-hsotg.txt      |    4 ++++
 drivers/usb/gadget/s3c-hsotg.c                     |   11 ++++++-----
 2 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/usb/samsung-hsotg.txt b/Documentation/devicetree/bindings/usb/samsung-hsotg.txt
index b83d428..75edb9d 100644
--- a/Documentation/devicetree/bindings/usb/samsung-hsotg.txt
+++ b/Documentation/devicetree/bindings/usb/samsung-hsotg.txt
@@ -24,6 +24,8 @@ Required properties:
     - first entry: must be "otg"
 - vusb_d-supply: phandle to voltage regulator of digital section,
 - vusb_a-supply: phandle to voltage regulator of analog section.
+- phys: from general PHY binding: phandle to the PHY device
+- phy-names: from general PHY binding: should be "usb2-phy"
 
 Example
 -----
@@ -36,5 +38,7 @@ Example
 		clock-names = "otg";
 		vusb_d-supply = <&vusb_reg>;
 		vusb_a-supply = <&vusbdac_reg>;
+		phys = <&usb2phy 0>;
+		phy-names = "usb2-phy";
 	};
 
diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
index 7aedaaf..a05c2f9 100644
--- a/drivers/usb/gadget/s3c-hsotg.c
+++ b/drivers/usb/gadget/s3c-hsotg.c
@@ -31,6 +31,7 @@
 #include <linux/regulator/consumer.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
+#include <linux/phy/phy.h>
 
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
@@ -162,7 +163,7 @@ struct s3c_hsotg_ep {
 struct s3c_hsotg {
 	struct device		 *dev;
 	struct usb_gadget_driver *driver;
-	struct usb_phy		*phy;
+	struct phy		 *phy;
 	struct s3c_hsotg_plat	 *plat;
 
 	spinlock_t              lock;
@@ -2910,7 +2911,7 @@ static void s3c_hsotg_phy_enable(struct s3c_hsotg *hsotg)
 	dev_dbg(hsotg->dev, "pdev 0x%p\n", pdev);
 
 	if (hsotg->phy)
-		usb_phy_init(hsotg->phy);
+		phy_power_on(hsotg->phy);
 	else if (hsotg->plat->phy_init)
 		hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
 }
@@ -2927,7 +2928,7 @@ static void s3c_hsotg_phy_disable(struct s3c_hsotg *hsotg)
 	struct platform_device *pdev = to_platform_device(hsotg->dev);
 
 	if (hsotg->phy)
-		usb_phy_shutdown(hsotg->phy);
+		phy_power_off(hsotg->phy);
 	else if (hsotg->plat->phy_exit)
 		hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
 }
@@ -3534,7 +3535,7 @@ static void s3c_hsotg_delete_debug(struct s3c_hsotg *hsotg)
 static int s3c_hsotg_probe(struct platform_device *pdev)
 {
 	struct s3c_hsotg_plat *plat = dev_get_platdata(&pdev->dev);
-	struct usb_phy *phy;
+	struct phy *phy;
 	struct device *dev = &pdev->dev;
 	struct s3c_hsotg_ep *eps;
 	struct s3c_hsotg *hsotg;
@@ -3549,7 +3550,7 @@ static int s3c_hsotg_probe(struct platform_device *pdev)
 		return -ENOMEM;
 	}
 
-	phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
+	phy = devm_phy_get(&pdev->dev, "usb2-phy");
 	if (IS_ERR(phy)) {
 		/* Fallback for pdata */
 		plat = dev_get_platdata(&pdev->dev);
-- 
1.7.9.5

[PATCH v5 6/9] phy: Add support for S5PV210 to the Exynos USB 2.0 PHY driver

[Kamil Debski]

From: Mateusz Krawczuk <mat.krawczuk@gmail.com>

Add support for the Samsung's S5PV210 SoC to the Exynos USB 2.0 PHY driver.

Signed-off-by: Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
[k.debski@samsung.com: cleanup and commit description]
[k.debski@samsung.com: make changes accordingly to the mailing list
comments]
Signed-off-by: Kamil Debski <k.debski@samsung.com>
---
 .../devicetree/bindings/phy/samsung-phy.txt        |    1 +
 drivers/phy/Kconfig                                |   10 +
 drivers/phy/Makefile                               |    1 +
 drivers/phy/phy-s5pv210-usb2.c                     |  199 ++++++++++++++++++++
 drivers/phy/phy-samsung-usb2.c                     |    6 +
 drivers/phy/phy-samsung-usb2.h                     |    1 +
 6 files changed, 218 insertions(+)
 create mode 100644 drivers/phy/phy-s5pv210-usb2.c

diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index 39d52cc..eb40460 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -26,6 +26,7 @@ Samsung S5P/EXYNOS SoC series USB PHY
 
 Required properties:
 - compatible : should be one of the listed compatibles:
+	- "samsung,s5pv210-usb2-phy"
 	- "samsung,exynos4210-usb2-phy"
 	- "samsung,exynos4212-usb2-phy"
 - reg : a list of registers used by phy driver
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 8e5cce1..b2c51ce 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -61,6 +61,16 @@ config PHY_SAMSUNG_USB2
 	  particular SoCs has to be enabled in addition to this driver. Number
 	  and type of supported phys depends on the SoC.
 
+config PHY_S5PV210_USB2
+	bool "Support for S5PV210"
+	depends on PHY_SAMSUNG_USB2
+	depends on ARCH_S5PV210
+	help
+	  Enable USB PHY support for S5PV210. This option requires that Samsung
+	  USB 2.0 PHY driver is enabled and means that support for this
+	  particular SoC is compiled in the driver. In case of S5PV210 two phys
+	  are available - device and host.
+
 config PHY_EXYNOS4210_USB2
 	bool "Support for Exynos 4210"
 	depends on PHY_SAMSUNG_USB2
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 9f4befd..fefc6c2 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -8,5 +8,6 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)	+= phy-exynos-mipi-video.o
 obj-$(CONFIG_OMAP_USB2)			+= phy-omap-usb2.o
 obj-$(CONFIG_TWL4030_USB)		+= phy-twl4030-usb.o
 obj-$(CONFIG_PHY_SAMSUNG_USB2)		+= phy-samsung-usb2.o
+obj-$(CONFIG_PHY_S5PV210_USB2)		+= phy-s5pv210-usb2.o
 obj-$(CONFIG_PHY_EXYNOS4210_USB2)	+= phy-exynos4210-usb2.o
 obj-$(CONFIG_PHY_EXYNOS4212_USB2)	+= phy-exynos4212-usb2.o
diff --git a/drivers/phy/phy-s5pv210-usb2.c b/drivers/phy/phy-s5pv210-usb2.c
new file mode 100644
index 0000000..58797a7
--- /dev/null
+++ b/drivers/phy/phy-s5pv210-usb2.c
@@ -0,0 +1,199 @@
+/*
+ * Samsung SoC USB 1.1/2.0 PHY driver - S5PV210 support
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Authors: Kamil Debski <k.debski@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/phy/phy.h>
+#include "phy-samsung-usb2.h"
+
+/* Exynos USB PHY registers */
+
+/* PHY power control */
+#define S5PV210_UPHYPWR			0x0
+
+#define S5PV210_UPHYPWR_PHY0_SUSPEND	BIT(0)
+#define S5PV210_UPHYPWR_PHY0_PWR	BIT(3)
+#define S5PV210_UPHYPWR_PHY0_OTG_PWR	BIT(4)
+#define S5PV210_UPHYPWR_PHY0	( \
+	S5PV210_UPHYPWR_PHY0_SUSPEND | \
+	S5PV210_UPHYPWR_PHY0_PWR | \
+	S5PV210_UPHYPWR_PHY0_OTG_PWR)
+
+#define S5PV210_UPHYPWR_PHY1_SUSPEND	BIT(6)
+#define S5PV210_UPHYPWR_PHY1_PWR	BIT(7)
+#define S5PV210_UPHYPWR_PHY1 ( \
+	S5PV210_UPHYPWR_PHY1_SUSPEND | \
+	S5PV210_UPHYPWR_PHY1_PWR)
+
+/* PHY clock control */
+#define S5PV210_UPHYCLK			0x4
+
+#define S5PV210_UPHYCLK_PHYFSEL_MASK	(0x3 << 0)
+#define S5PV210_UPHYCLK_PHYFSEL_48MHZ	(0x0 << 0)
+#define S5PV210_UPHYCLK_PHYFSEL_24MHZ	(0x3 << 0)
+#define S5PV210_UPHYCLK_PHYFSEL_12MHZ	(0x2 << 0)
+
+#define S5PV210_UPHYCLK_PHY0_ID_PULLUP	BIT(2)
+#define S5PV210_UPHYCLK_PHY0_COMMON_ON	BIT(4)
+#define S5PV210_UPHYCLK_PHY1_COMMON_ON	BIT(7)
+
+/* PHY reset control */
+#define S5PV210_UPHYRST			0x8
+
+#define S5PV210_URSTCON_PHY0		BIT(0)
+#define S5PV210_URSTCON_OTG_HLINK	BIT(1)
+#define S5PV210_URSTCON_OTG_PHYLINK	BIT(2)
+#define S5PV210_URSTCON_PHY1_ALL	BIT(3)
+#define S5PV210_URSTCON_HOST_LINK_ALL	BIT(4)
+
+/* Isolation, configured in the power management unit */
+#define S5PV210_USB_ISOL_DEVICE_OFFSET	0x704
+#define S5PV210_USB_ISOL_DEVICE		BIT(0)
+#define S5PV210_USB_ISOL_HOST_OFFSET	0x708
+#define S5PV210_USB_ISOL_HOST		BIT(1)
+
+
+enum s5pv210_phy_id {
+	S5PV210_DEVICE,
+	S5PV210_HOST,
+	S5PV210_NUM_PHYS,
+};
+
+/*
+ * s5pv210_rate_to_clk() converts the supplied clock rate to the value that
+ * can be written to the phy register.
+ */
+static int s5pv210_rate_to_clk(unsigned long rate, u32 *reg)
+{
+	pr_info("%lu\n", rate);
+	switch (rate) {
+	case 12 * MHZ:
+		*reg = S5PV210_UPHYCLK_PHYFSEL_12MHZ;
+		break;
+	case 24 * MHZ:
+		*reg = S5PV210_UPHYCLK_PHYFSEL_24MHZ;
+		break;
+	case 48 * MHZ:
+		*reg = S5PV210_UPHYCLK_PHYFSEL_48MHZ;
+		break;
+	default:
+		return -EINVAL;
+	}
+}
+
+static void s5pv210_isol(struct samsung_usb2_phy_instance *inst, bool on)
+{
+	struct samsung_usb2_phy_driver *drv = inst->drv;
+	u32 mask;
+	u32 tmp;
+
+	if (!drv->reg_isol)
+		return;
+
+	switch (inst->cfg->id) {
+	case S5PV210_DEVICE:
+		mask = S5PV210_USB_ISOL_DEVICE;
+		break;
+	case S5PV210_HOST:
+		mask = S5PV210_USB_ISOL_HOST;
+		break;
+	default:
+		return;
+	};
+
+	regmap_update_bits(drv->reg_pmu, offset, mask, on ? 0 : mask);
+}
+
+static void s5pv210_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on)
+{
+	struct samsung_usb2_phy_driver *drv = inst->drv;
+	u32 rstbits = 0;
+	u32 phypwr = 0;
+	u32 rst;
+	u32 pwr;
+
+	switch (inst->cfg->id) {
+	case S5PV210_DEVICE:
+		phypwr =	S5PV210_UPHYPWR_PHY0;
+		rstbits =	S5PV210_URSTCON_PHY0;
+		break;
+	case S5PV210_HOST:
+		phypwr =	S5PV210_UPHYPWR_PHY1;
+		rstbits =	S5PV210_URSTCON_PHY1_ALL |
+				S5PV210_URSTCON_HOST_LINK_ALL;
+		break;
+	};
+
+	if (on) {
+		writel(inst->clk, drv->reg_phy + S5PV210_UPHYCLK);
+
+		pwr = readl(drv->reg_phy + S5PV210_UPHYPWR);
+		pwr &= ~phypwr;
+		writel(pwr, drv->reg_phy + S5PV210_UPHYPWR);
+
+		rst = readl(drv->reg_phy + S5PV210_UPHYRST);
+		rst |= rstbits;
+		writel(rst, drv->reg_phy + S5PV210_UPHYRST);
+		udelay(10);
+		rst &= ~rstbits;
+		writel(rst, drv->reg_phy + S5PV210_UPHYRST);
+	} else {
+		pwr = readl(drv->reg_phy + S5PV210_UPHYPWR);
+		pwr |= phypwr;
+		writel(pwr, drv->reg_phy + S5PV210_UPHYPWR);
+	}
+}
+
+static int s5pv210_power_on(struct samsung_usb2_phy_instance *inst)
+{
+	struct samsung_usb2_phy_driver *drv = inst->drv;
+
+	s5pv210_isol(inst, 0);
+	s5pv210_phy_pwr(inst, 1);
+
+	return 0;
+}
+
+static int s5pv210_power_off(struct samsung_usb2_phy_instance *inst)
+{
+	struct samsung_usb2_phy_driver *drv = inst->drv;
+
+	s5pv210_phy_pwr(inst, 0);
+	s5pv210_isol(inst, 1);
+
+	return 0;
+}
+
+
+static const struct samsung_usb2_common_phy s5pv210_phys[] = {
+	{
+		.label		= "device",
+		.id		= S5PV210_DEVICE,
+		.rate_to_clk	= s5pv210_rate_to_clk,
+		.power_on	= s5pv210_power_on,
+		.power_off	= s5pv210_power_off,
+	},
+	{
+		.label		= "host",
+		.id		= S5PV210_HOST,
+		.rate_to_clk	= s5pv210_rate_to_clk,
+		.power_on	= s5pv210_power_on,
+		.power_off	= s5pv210_power_off,
+	},
+	{},
+};
+
+const struct samsung_usb2_phy_config s5pv210_usb2_phy_config = {
+	.cpu		= TYPE_S5PV210,
+	.num_phys	= S5PV210_NUM_PHYS,
+	.phys		= s5pv210_phys,
+};
+
diff --git a/drivers/phy/phy-samsung-usb2.c b/drivers/phy/phy-samsung-usb2.c
index 3c09e0e..464a626 100644
--- a/drivers/phy/phy-samsung-usb2.c
+++ b/drivers/phy/phy-samsung-usb2.c
@@ -95,6 +95,12 @@ static struct phy *samsung_usb2_phy_xlate(struct device *dev,
 }
 
 static const struct of_device_id samsung_usb2_phy_of_match[] = {
+#ifdef CONFIG_PHY_S5PV210_USB2
+	{
+		.compatible = "samsung,s5pv210-usb2-phy",
+		.data = &s5pv210_usb2_phy_config,
+	},
+#endif
 #ifdef CONFIG_PHY_EXYNOS4210_USB2
 	{
 		.compatible = "samsung,exynos4210-usb2-phy",
diff --git a/drivers/phy/phy-samsung-usb2.h b/drivers/phy/phy-samsung-usb2.h
index ab89f91..5f5b240 100644
--- a/drivers/phy/phy-samsung-usb2.h
+++ b/drivers/phy/phy-samsung-usb2.h
@@ -61,6 +61,7 @@ struct samsung_usb2_phy_config {
 	bool has_mode_switch;
 };
 
+extern const struct samsung_usb2_phy_config s5pv210_usb2_phy_config;
 extern const struct samsung_usb2_phy_config exynos4210_usb2_phy_config;
 extern const struct samsung_usb2_phy_config exynos4212_usb2_phy_config;
 #endif
-- 
1.7.9.5

[PATCH v5 7/9] phy: Add Exynos 5250 support to the Exynos USB 2.0 PHY driver

[Kamil Debski]

Add support for Exynos 5250. This driver is to replace the old
USB 2.0 PHY driver.

Signed-off-by: Kamil Debski <k.debski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 .../devicetree/bindings/phy/samsung-phy.txt        |    1 +
 drivers/phy/Kconfig                                |   11 +
 drivers/phy/Makefile                               |    1 +
 drivers/phy/phy-exynos5250-usb2.c                  |  356 ++++++++++++++++++++
 drivers/phy/phy-samsung-usb2.c                     |    6 +
 drivers/phy/phy-samsung-usb2.h                     |    1 +
 6 files changed, 376 insertions(+)
 create mode 100644 drivers/phy/phy-exynos5250-usb2.c

diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index eb40460..afc47c2 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -29,6 +29,7 @@ Required properties:
 	- "samsung,s5pv210-usb2-phy"
 	- "samsung,exynos4210-usb2-phy"
 	- "samsung,exynos4212-usb2-phy"
+	- "samsung,exynos5250-usb2-phy"
 - reg : a list of registers used by phy driver
 	- first and obligatory is the location of phy modules registers
 - samsung,sysreg-phandle - handle to syscon used to control the system registers
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index b2c51ce..726410f 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -90,4 +90,15 @@ config PHY_EXYNOS4212_USB2
 	  Samsung USB 2.0 PHY driver is enabled and means that support for this
 	  particular SoC is compiled in the driver. In case of Exynos 4212 four
 	  phys are available - device, host, HSIC0 and HSIC1.
+
+config PHY_EXYNOS5250_USB2
+	bool "Support for Exynos 5250"
+	depends on PHY_SAMSUNG_USB2
+	depends on SOC_EXYNOS5250
+	help
+	  Enable USB PHY support for Exynos 5250. This option requires that
+	  Samsung USB 2.0 PHY driver is enabled and means that support for this
+	  particular SoC is compiled in the driver. In case of Exynos 5250 four
+	  phys are available - device, host, HSIC0 and HSIC.
+
 endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index fefc6c2..33c3ac1 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_PHY_SAMSUNG_USB2)		+= phy-samsung-usb2.o
 obj-$(CONFIG_PHY_S5PV210_USB2)		+= phy-s5pv210-usb2.o
 obj-$(CONFIG_PHY_EXYNOS4210_USB2)	+= phy-exynos4210-usb2.o
 obj-$(CONFIG_PHY_EXYNOS4212_USB2)	+= phy-exynos4212-usb2.o
+obj-$(CONFIG_PHY_EXYNOS5250_USB2)	+= phy-exynos5250-usb2.o
diff --git a/drivers/phy/phy-exynos5250-usb2.c b/drivers/phy/phy-exynos5250-usb2.c
new file mode 100644
index 0000000..b9b3b98
--- /dev/null
+++ b/drivers/phy/phy-exynos5250-usb2.c
@@ -0,0 +1,356 @@
+/*
+ * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 5250 support
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Author: Kamil Debski <k.debski@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+#include "phy-samsung-usb2.h"
+
+/* Exynos USB PHY registers */
+#define EXYNOS_5250_REFCLKSEL_CRYSTAL	0x0
+#define EXYNOS_5250_REFCLKSEL_XO	0x1
+#define EXYNOS_5250_REFCLKSEL_CLKCORE	0x2
+
+#define EXYNOS_5250_FSEL_9MHZ6		0x0
+#define EXYNOS_5250_FSEL_10MHZ		0x1
+#define EXYNOS_5250_FSEL_12MHZ		0x2
+#define EXYNOS_5250_FSEL_19MHZ2		0x3
+#define EXYNOS_5250_FSEL_20MHZ		0x4
+#define EXYNOS_5250_FSEL_24MHZ		0x5
+#define EXYNOS_5250_FSEL_50MHZ		0x7
+
+/* Normal host */
+#define EXYNOS_5250_HOSTPHYCTRL0			0x0
+
+#define EXYNOS_5250_HOSTPHYCTRL0_PHYSWRSTALL		BIT(31)
+#define EXYNOS_5250_HOSTPHYCTRL0_REFCLKSEL_SHIFT	19
+#define EXYNOS_5250_HOSTPHYCTRL0_REFCLKSEL_MASK	\
+		(0x3 << EXYNOS_5250_HOSTPHYCTRL0_REFCLKSEL_SHIFT)
+#define EXYNOS_5250_HOSTPHYCTRL0_FSEL_SHIFT		16
+#define EXYNOS_5250_HOSTPHYCTRL0_FSEL_MASK \
+		(0x7 << EXYNOS_5250_HOSTPHYCTRL0_FSEL_SHIFT)
+#define EXYNOS_5250_HOSTPHYCTRL0_TESTBURNIN		BIT(11)
+#define EXYNOS_5250_HOSTPHYCTRL0_RETENABLE		BIT(10)
+#define EXYNOS_5250_HOSTPHYCTRL0_COMMON_ON_N		BIT(9)
+#define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_MASK		(0x3 << 7)
+#define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_DUAL		(0x0 << 7)
+#define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_ID0		(0x1 << 7)
+#define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_ANALOGTEST	(0x2 << 7)
+#define EXYNOS_5250_HOSTPHYCTRL0_SIDDQ			BIT(6)
+#define EXYNOS_5250_HOSTPHYCTRL0_FORCESLEEP		BIT(5)
+#define EXYNOS_5250_HOSTPHYCTRL0_FORCESUSPEND		BIT(4)
+#define EXYNOS_5250_HOSTPHYCTRL0_WORDINTERFACE		BIT(3)
+#define EXYNOS_5250_HOSTPHYCTRL0_UTMISWRST		BIT(2)
+#define EXYNOS_5250_HOSTPHYCTRL0_LINKSWRST		BIT(1)
+#define EXYNOS_5250_HOSTPHYCTRL0_PHYSWRST		BIT(0)
+
+/* HSIC0 & HSCI1 */
+#define EXYNOS_5250_HOSTPHYCTRL1			0x10
+#define EXYNOS_5250_HOSTPHYCTRL2			0x20
+
+#define EXYNOS_5250_HOSTPHYCTRLX_REFCLKSEL_MASK		(0x3 << 23)
+#define EXYNOS_5250_HOSTPHYCTRLX_REFCLKDIV_MASK		(0x7f << 16)
+#define EXYNOS_5250_HOSTPHYCTRLX_SIDDQ			BIT(6)
+#define EXYNOS_5250_HOSTPHYCTRLX_FORCESLEEP		BIT(5)
+#define EXYNOS_5250_HOSTPHYCTRLX_FORCESUSPEND		BIT(4)
+#define EXYNOS_5250_HOSTPHYCTRLX_WORDINTERFACE		BIT(3)
+#define EXYNOS_5250_HOSTPHYCTRLX_UTMISWRST		BIT(2)
+#define EXYNOS_5250_HOSTPHYCTRLX_PHYSWRST		BIT(0)
+
+/* EHCI control */
+#define EXYNOS_5250_HOSTEHCICTRL			0x30
+#define EXYNOS_5250_HOSTEHCICTRL_ENAINCRXALIGN		BIT(29)
+#define EXYNOS_5250_HOSTEHCICTRL_ENAINCR4		BIT(28)
+#define EXYNOS_5250_HOSTEHCICTRL_ENAINCR8		BIT(27)
+#define EXYNOS_5250_HOSTEHCICTRL_ENAINCR16		BIT(26)
+#define EXYNOS_5250_HOSTEHCICTRL_AUTOPPDONOVRCUREN	BIT(25)
+#define EXYNOS_5250_HOSTEHCICTRL_FLADJVAL0_SHIFT	19
+#define EXYNOS_5250_HOSTEHCICTRL_FLADJVAL0_MASK	\
+		(0x3f << EXYNOS_5250_HOSTEHCICTRL_FLADJVAL0_SHIFT)
+#define EXYNOS_5250_HOSTEHCICTRL_FLADJVAL1_SHIFT	13
+#define EXYNOS_5250_HOSTEHCICTRL_FLADJVAL1_MASK	\
+		(0x3f << EXYNOS_5250_HOSTEHCICTRL_FLADJVAL1_SHIFT)
+#define EXYNOS_5250_HOSTEHCICTRL_FLADJVAL2_SHIFT	7
+#define EXYNOS_5250_HOSTEHCICTRL_FLADJVAL0_MASK	\
+		(0x3f << EXYNOS_5250_HOSTEHCICTRL_FLADJVAL0_SHIFT)
+#define EXYNOS_5250_HOSTEHCICTRL_FLADJVALHOST_SHIFT	1
+#define EXYNOS_5250_HOSTEHCICTRL_FLADJVALHOST_MASK \
+		(0x1 << EXYNOS_5250_HOSTEHCICTRL_FLADJVALHOST_SHIFT)
+#define EXYNOS_5250_HOSTEHCICTRL_SIMULATIONMODE		BIT(0)
+
+/* OHCI control */
+#define EXYNOS_5250_HOSTOHCICTRL                        0x34
+#define EXYNOS_5250_HOSTOHCICTRL_FRAMELENVAL_SHIFT	1
+#define EXYNOS_5250_HOSTOHCICTRL_FRAMELENVAL_MASK \
+		(0x3ff << EXYNOS_5250_HOSTOHCICTRL_FRAMELENVAL_SHIFT)
+#define EXYNOS_5250_HOSTOHCICTRL_FRAMELENVALEN		BIT(0)
+
+/* USBOTG */
+#define EXYNOS_5250_USBOTGSYS				0x38
+#define EXYNOS_5250_USBOTGSYS_PHYLINK_SW_RESET		BIT(14)
+#define EXYNOS_5250_USBOTGSYS_LINK_SW_RST_UOTG		BIT(13)
+#define EXYNOS_5250_USBOTGSYS_PHY_SW_RST		BIT(12)
+#define EXYNOS_5250_USBOTGSYS_REFCLKSEL_SHIFT		9
+#define EXYNOS_5250_USBOTGSYS_REFCLKSEL_MASK \
+		(0x3 << EXYNOS_5250_USBOTGSYS_REFCLKSEL_SHIFT)
+#define EXYNOS_5250_USBOTGSYS_ID_PULLUP			BIT(8)
+#define EXYNOS_5250_USBOTGSYS_COMMON_ON			BIT(7)
+#define EXYNOS_5250_USBOTGSYS_FSEL_SHIFT		4
+#define EXYNOS_5250_USBOTGSYS_FSEL_MASK \
+		(0x3 << EXYNOS_5250_USBOTGSYS_FSEL_SHIFT)
+#define EXYNOS_5250_USBOTGSYS_FORCE_SLEEP		BIT(3)
+#define EXYNOS_5250_USBOTGSYS_OTGDISABLE		BIT(2)
+#define EXYNOS_5250_USBOTGSYS_SIDDQ_UOTG		BIT(1)
+#define EXYNOS_5250_USBOTGSYS_FORCE_SUSPEND		BIT(0)
+
+/* Isolation, configured in the power management unit */
+#define EXYNOS_5250_USB_ISOL_OTG_OFFSET		0x704
+#define EXYNOS_5250_USB_ISOL_OTG		BIT(0)
+#define EXYNOS_5250_USB_ISOL_HOST_OFFSET	0x708
+#define EXYNOS_5250_USB_ISOL_HOST		BIT(0)
+
+/* Mode swtich register */
+#define EXYNOS_5250_MODE_SWITCH_OFFSET		0x230
+#define EXYNOS_5250_MODE_SWITCH_MASK		1
+#define EXYNOS_5250_MODE_SWITCH_DEVICE		0
+#define EXYNOS_5250_MODE_SWITCH_HOST		1
+
+enum exynos4x12_phy_id {
+	EXYNOS5250_DEVICE,
+	EXYNOS5250_HOST,
+	EXYNOS5250_HSIC0,
+	EXYNOS5250_HSIC1,
+	EXYNOS5250_NUM_PHYS,
+};
+
+/*
+ * exynos5250_rate_to_clk() converts the supplied clock rate to the value that
+ * can be written to the phy register.
+ */
+static int exynos5250_rate_to_clk(unsigned long rate, u32 *reg)
+{
+	/* EXYNOS_5250_FSEL_MASK */
+
+	switch (rate) {
+	case 9600 * KHZ:
+		*reg = EXYNOS_5250_FSEL_9MHZ6;
+		break;
+	case 10 * MHZ:
+		*reg = EXYNOS_5250_FSEL_10MHZ;
+		break;
+	case 12 * MHZ:
+		*reg = EXYNOS_5250_FSEL_12MHZ;
+		break;
+	case 19200 * KHZ:
+		*reg = EXYNOS_5250_FSEL_19MHZ2;
+		break;
+	case 20 * MHZ:
+		*reg = EXYNOS_5250_FSEL_20MHZ;
+		break;
+	case 24 * MHZ:
+		*reg = EXYNOS_5250_FSEL_24MHZ;
+		break;
+	case 50 * MHZ:
+		*reg = EXYNOS_5250_FSEL_50MHZ;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static void exynos5250_isol(struct samsung_usb2_phy_instance *inst, bool on)
+{
+	struct samsung_usb2_phy_driver *drv = inst->drv;
+	u32 offset;
+	u32 mask;
+
+	switch (inst->cfg->id) {
+	case EXYNOS5250_DEVICE:
+		offset = EXYNOS_5250_USB_ISOL_OTG_OFFSET;
+		mask = EXYNOS_5250_USB_ISOL_OTG;
+		break;
+	case EXYNOS5250_HOST:
+		offset = EXYNOS_5250_USB_ISOL_HOST_OFFSET;
+		mask = EXYNOS_5250_USB_ISOL_HOST;
+		break;
+	default:
+		return;
+	};
+
+	regmap_update_bits(drv->reg_pmu, offset, mask, on ? 0 : mask);
+}
+
+static void exynos5250_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on)
+{
+	struct samsung_usb2_phy_driver *drv = inst->drv;
+	u32 ctrl0;
+	u32 otg;
+	u32 ehci;
+	u32 ohci;
+
+	switch (inst->cfg->id) {
+	case EXYNOS5250_DEVICE:
+		regmap_update_bits(drv->reg_sys,
+			EXYNOS_5250_MODE_SWITCH_OFFSET,
+			EXYNOS_5250_MODE_SWITCH_MASK,
+			EXYNOS_5250_MODE_SWITCH_DEVICE);
+
+		/* OTG configuration */
+		otg = readl(drv->reg_phy + EXYNOS_5250_USBOTGSYS);
+		/* The clock */
+		otg &= ~EXYNOS_5250_USBOTGSYS_FSEL_MASK;
+		otg |= inst->clk_reg_val << EXYNOS_5250_USBOTGSYS_FSEL_SHIFT;
+		/* Reset */
+		otg &= ~(EXYNOS_5250_USBOTGSYS_FORCE_SUSPEND |
+			EXYNOS_5250_USBOTGSYS_FORCE_SLEEP |
+			EXYNOS_5250_USBOTGSYS_SIDDQ_UOTG);
+		otg |=	EXYNOS_5250_USBOTGSYS_PHY_SW_RST |
+			EXYNOS_5250_USBOTGSYS_PHYLINK_SW_RESET |
+			EXYNOS_5250_USBOTGSYS_LINK_SW_RST_UOTG |
+			EXYNOS_5250_USBOTGSYS_OTGDISABLE;
+		/* Ref clock */
+		otg &=	~EXYNOS_5250_USBOTGSYS_REFCLKSEL_MASK;
+		otg |=  EXYNOS_5250_REFCLKSEL_CLKCORE <<
+					EXYNOS_5250_USBOTGSYS_REFCLKSEL_SHIFT;
+		writel(otg, drv->reg_phy + EXYNOS_5250_USBOTGSYS);
+		udelay(100);
+		otg &= ~(EXYNOS_5250_USBOTGSYS_PHY_SW_RST |
+			EXYNOS_5250_USBOTGSYS_LINK_SW_RST_UOTG |
+			EXYNOS_5250_USBOTGSYS_PHYLINK_SW_RESET |
+			EXYNOS_5250_USBOTGSYS_OTGDISABLE);
+		writel(otg, drv->reg_phy + EXYNOS_5250_USBOTGSYS);
+
+
+		break;
+	case EXYNOS5250_HOST:
+		/* Host registers configuration */
+		ctrl0 = readl(drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0);
+		/* The clock */
+		ctrl0 &= ~EXYNOS_5250_HOSTPHYCTRL0_FSEL_MASK;
+		ctrl0 |= inst->clk_reg_val <<
+					EXYNOS_5250_HOSTPHYCTRL0_FSEL_SHIFT;
+
+		/* Reset */
+		ctrl0 &=	~(EXYNOS_5250_HOSTPHYCTRL0_PHYSWRST |
+				EXYNOS_5250_HOSTPHYCTRL0_PHYSWRSTALL |
+				EXYNOS_5250_HOSTPHYCTRL0_SIDDQ |
+				EXYNOS_5250_HOSTPHYCTRL0_FORCESUSPEND |
+				EXYNOS_5250_HOSTPHYCTRL0_FORCESLEEP);
+		ctrl0 |=	EXYNOS_5250_HOSTPHYCTRL0_LINKSWRST |
+				EXYNOS_5250_HOSTPHYCTRL0_UTMISWRST |
+				EXYNOS_5250_HOSTPHYCTRL0_COMMON_ON_N;
+		writel(ctrl0, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0);
+		udelay(10);
+		ctrl0 &=	~(EXYNOS_5250_HOSTPHYCTRL0_LINKSWRST |
+				EXYNOS_5250_HOSTPHYCTRL0_UTMISWRST);
+		writel(ctrl0, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0);
+
+		/* OTG configuration */
+		otg = readl(drv->reg_phy + EXYNOS_5250_USBOTGSYS);
+		/* The clock */
+		otg &= ~EXYNOS_5250_USBOTGSYS_FSEL_MASK;
+		otg |= inst->clk_reg_val << EXYNOS_5250_USBOTGSYS_FSEL_SHIFT;
+		/* Reset */
+		otg &= ~(EXYNOS_5250_USBOTGSYS_FORCE_SUSPEND |
+			EXYNOS_5250_USBOTGSYS_FORCE_SLEEP |
+			EXYNOS_5250_USBOTGSYS_SIDDQ_UOTG);
+		otg |=	EXYNOS_5250_USBOTGSYS_PHY_SW_RST |
+			EXYNOS_5250_USBOTGSYS_PHYLINK_SW_RESET |
+			EXYNOS_5250_USBOTGSYS_LINK_SW_RST_UOTG |
+			EXYNOS_5250_USBOTGSYS_OTGDISABLE;
+		/* Ref clock */
+		otg &=	~EXYNOS_5250_USBOTGSYS_REFCLKSEL_MASK;
+		otg |=  EXYNOS_5250_REFCLKSEL_CLKCORE <<
+					EXYNOS_5250_USBOTGSYS_REFCLKSEL_SHIFT;
+		writel(otg, drv->reg_phy + EXYNOS_5250_USBOTGSYS);
+		udelay(10);
+		otg &= ~(EXYNOS_5250_USBOTGSYS_PHY_SW_RST |
+			EXYNOS_5250_USBOTGSYS_LINK_SW_RST_UOTG |
+			EXYNOS_5250_USBOTGSYS_PHYLINK_SW_RESET);
+
+		/* Enable EHCI DMA burst */
+		ehci = readl(drv->reg_phy + EXYNOS_5250_HOSTEHCICTRL);
+		ehci |=	EXYNOS_5250_HOSTEHCICTRL_ENAINCRXALIGN |
+			EXYNOS_5250_HOSTEHCICTRL_ENAINCR4 |
+			EXYNOS_5250_HOSTEHCICTRL_ENAINCR8 |
+			EXYNOS_5250_HOSTEHCICTRL_ENAINCR16;
+		writel(ehci, drv->reg_phy + EXYNOS_5250_HOSTEHCICTRL);
+
+		/* OHCI settings */
+		ohci = readl(drv->reg_phy + EXYNOS_5250_HOSTOHCICTRL);
+		/* Following code is based on the old driver */
+		ohci |=	0x1 << 3;
+		writel(ohci, drv->reg_phy + EXYNOS_5250_HOSTOHCICTRL);
+
+		break;
+	}
+}
+
+static int exynos5250_power_on(struct samsung_usb2_phy_instance *inst)
+{
+	inst->enabled = 1;
+	exynos5250_phy_pwr(inst, 1);
+	exynos5250_isol(inst, 0);
+
+	return 0;
+}
+
+static int exynos5250_power_off(struct samsung_usb2_phy_instance *inst)
+{
+	inst->enabled = 0;
+	exynos5250_isol(inst, 1);
+	exynos5250_phy_pwr(inst, 0);
+
+	return 0;
+}
+
+
+static const struct samsung_usb2_common_phy exynos5250_phys[] = {
+	{
+		.label		= "device",
+		.id		= EXYNOS5250_DEVICE,
+		.rate_to_clk	= exynos5250_rate_to_clk,
+		.power_on	= exynos5250_power_on,
+		.power_off	= exynos5250_power_off,
+	},
+	{
+		.label		= "host",
+		.id		= EXYNOS5250_HOST,
+		.rate_to_clk	= exynos5250_rate_to_clk,
+		.power_on	= exynos5250_power_on,
+		.power_off	= exynos5250_power_off,
+	},
+	{
+		.label		= "hsic0",
+		.id		= EXYNOS5250_HSIC0,
+		.rate_to_clk	= exynos5250_rate_to_clk,
+		.power_on	= exynos5250_power_on,
+		.power_off	= exynos5250_power_off,
+	},
+	{
+		.label		= "hsic1",
+		.id		= EXYNOS5250_HSIC1,
+		.rate_to_clk	= exynos5250_rate_to_clk,
+		.power_on	= exynos5250_power_on,
+		.power_off	= exynos5250_power_off,
+	},
+	{},
+};
+
+const struct samsung_usb2_phy_config exynos5250_usb2_phy_config = {
+	.num_phys		= EXYNOS5250_NUM_PHYS,
+	.phys			= exynos5250_phys,
+	.has_mode_switch	= 1,
+};
+
diff --git a/drivers/phy/phy-samsung-usb2.c b/drivers/phy/phy-samsung-usb2.c
index 464a626..76c2df0 100644
--- a/drivers/phy/phy-samsung-usb2.c
+++ b/drivers/phy/phy-samsung-usb2.c
@@ -113,6 +113,12 @@ static const struct of_device_id samsung_usb2_phy_of_match[] = {
 		.data = &exynos4212_usb2_phy_config,
 	},
 #endif
+#ifdef CONFIG_PHY_EXYNOS5250_USB2
+	{
+		.compatible = "samsung,exynos5250-usb2-phy",
+		.data = &exynos5250_usb2_phy_config,
+	},
+#endif
 	{ },
 };
 
diff --git a/drivers/phy/phy-samsung-usb2.h b/drivers/phy/phy-samsung-usb2.h
index 5f5b240..ffc3296 100644
--- a/drivers/phy/phy-samsung-usb2.h
+++ b/drivers/phy/phy-samsung-usb2.h
@@ -64,5 +64,6 @@ struct samsung_usb2_phy_config {
 extern const struct samsung_usb2_phy_config s5pv210_usb2_phy_config;
 extern const struct samsung_usb2_phy_config exynos4210_usb2_phy_config;
 extern const struct samsung_usb2_phy_config exynos4212_usb2_phy_config;
+extern const struct samsung_usb2_phy_config exynos5250_usb2_phy_config;
 #endif
 
-- 
1.7.9.5

[PATCH v2 8/9] dts: Add usb2phy to Exynos 4

[Kamil Debski]

Add support to PHY of USB2 of the Exynos 4 SoC.

Signed-off-by: Kamil Debski <k.debski@samsung.com>
---
 .../devicetree/bindings/arm/samsung/pmu.txt        |    2 ++
 arch/arm/boot/dts/exynos4.dtsi                     |   31 ++++++++++++++++++++
 arch/arm/boot/dts/exynos4210.dtsi                  |   17 +++++++++++
 arch/arm/boot/dts/exynos4x12.dtsi                  |   17 +++++++++++
 4 files changed, 67 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
index 307e727..bfccab0 100644
--- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
@@ -3,6 +3,8 @@ SAMSUNG Exynos SoC series PMU Registers
 Properties:
  - name : should be 'syscon';
  - compatible : should contain two values. First value must be one from following list:
+		   - "samsung,exynos4210-pmu" - for Exynos4210 SoC,
+		   - "samsung,exynos4212-pmu" - for Exynos4212 SoC,
 		   - "samsung,exynos5250-pmu" - for Exynos5250 SoC,
 		   - "samsung,exynos5420-pmu" - for Exynos5420 SoC.
 		second value must be always "syscon".
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index a73eeb5..031d07a 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -253,6 +253,17 @@
 		status = "disabled";
 	};
 
+	usbotg@12480000 {
+		compatible = "samsung,s3c6400-hsotg";
+		reg = <0x12480000 0x20000>;
+		interrupts = <0 71 0>;
+		clocks = <&clock 305>;
+		clock-names = "otg";
+		phys = <&usb2phy 0>;
+		phy-names = "usb2-phy";
+		status = "disabled";
+	};
+
 	ehci@12580000 {
 		compatible = "samsung,exynos4210-ehci";
 		reg = <0x12580000 0x100>;
@@ -260,6 +271,26 @@
 		clocks = <&clock 304>;
 		clock-names = "usbhost";
 		status = "disabled";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		port@0 {
+			phys = <&usb2phy 1>;
+			phy-names = "host";
+			reg = <0>;
+			status = "disabled";
+		};
+		port@1 {
+			phys = <&usb2phy 2>;
+			phy-names = "hsic0";
+			reg = <1>;
+			status = "disabled";
+		};
+		port@2 {
+			phys = <&usb2phy 3>;
+			phy-names = "hsic1";
+			reg = <2>;
+			status = "disabled";
+		};
 	};
 
 	ohci@12590000 {
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 057d682..f9d06bb 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -155,4 +155,21 @@
 			samsung,lcd-wb;
 		};
 	};
+
+	pmu_reg: syscon@10020000 {
+		compatible = "samsung,exynos4210-pmu", "syscon";
+		reg = <0x10020000 0x4000>;
+	};
+
+	usb2phy: phy@125B0000 {
+		compatible = "samsung,exynos4210-usb2-phy";
+		reg = <0x125B0000 0x100>;
+		clocks = <&clock 305>, <&clock 2>, <&clock 2>, <&clock 2>,
+								<&clock 2>;
+		clock-names = "phy", "device", "host", "hsic0", "hsic1";
+		status = "disabled";
+		#phy-cells = <1>;
+		samsung,sysreg-phandle = <&sys_reg>;
+		samsung,pmureg-phandle = <&pmu_reg>;
+	};
 };
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index ad531fe..7121111 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -176,4 +176,21 @@
 			};
 		};
 	};
+
+	pmu_reg: syscon@10020000 {
+		compatible = "samsung,exynos4212-pmu", "syscon";
+		reg = <0x10020000 0x4000>;
+	};
+
+	usb2phy: phy@125B0000 {
+		compatible = "samsung,exynos4212-usb2-phy";
+		reg = <0x125B0000 0x100>;
+		clocks = <&clock 305>, <&clock 2>, <&clock 2>, <&clock 2>,
+								<&clock 2>;
+		clock-names = "phy", "device", "host", "hsic0", "hsic1";
+		status = "disabled";
+		#phy-cells = <1>;
+		samsung,sysreg-phandle = <&sys_reg>;
+		samsung,pmureg-phandle = <&pmu_reg>;
+	};
 };
-- 
1.7.9.5

[PATCH v2 9/9] dts: Add usb2phy to Exynos 5250

[Kamil Debski]

Add support to PHY of USB2 of the Exynos 5250 SoC.

Signed-off-by: Kamil Debski <k.debski@samsung.com>
---
 arch/arm/boot/dts/exynos5250.dtsi |   33 ++++++++++++-------
 drivers/phy/phy-exynos5250-usb2.c |   64 +++++++++++++++++++++++++++++++++----
 2 files changed, 78 insertions(+), 19 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 2f264ad..922e0ed 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -163,6 +163,11 @@
 		interrupts = <0 47 0>;
 	};
 
+	sys_syscon: syscon@10040000 {
+		compatible = "samsung,exynos5250-sys", "syscon";
+		reg = <0x10050000 0x5000>;
+	};
+
 	pmu_syscon: syscon@10040000 {
 		compatible = "samsung,exynos5250-pmu", "syscon";
 		reg = <0x10040000 0x5000>;
@@ -505,6 +510,14 @@
 
 		clocks = <&clock 285>;
 		clock-names = "usbhost";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		port@0 {
+			reg = <0>;
+			phys = <&usb2_phy 1>;
+			phy-names = "host";
+			status = "ok";
+		};
 	};
 
 	usb@12120000 {
@@ -516,19 +529,15 @@
 		clock-names = "usbhost";
 	};
 
-	usb2_phy: usbphy@12130000 {
-		compatible = "samsung,exynos5250-usb2phy";
+	usb2_phy: phy@12130000 {
+		compatible = "samsung,exynos5250-usb2-phy";
 		reg = <0x12130000 0x100>;
-		clocks = <&clock 1>, <&clock 285>;
-		clock-names = "ext_xtal", "usbhost";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		usbphy-sys {
-			reg = <0x10040704 0x8>,
-			      <0x10050230 0x4>;
-		};
+		clocks = <&clock 285>, <&clock 1>, <&clock 1>, <&clock 1>,
+								<&clock 1>;
+		clock-names = "phy", "device", "host", "hsic0", "hsic1";
+		#phy-cells = <1>;
+		samsung,sysreg-phandle = <&sys_syscon>;
+		samsung,pmureg-phandle = <&pmu_syscon>;
 	};
 
 	amba {
diff --git a/drivers/phy/phy-exynos5250-usb2.c b/drivers/phy/phy-exynos5250-usb2.c
index b9b3b98..337bf82 100644
--- a/drivers/phy/phy-exynos5250-usb2.c
+++ b/drivers/phy/phy-exynos5250-usb2.c
@@ -58,7 +58,13 @@
 #define EXYNOS_5250_HOSTPHYCTRL2			0x20
 
 #define EXYNOS_5250_HOSTPHYCTRLX_REFCLKSEL_MASK		(0x3 << 23)
+#define EXYNOS_5250_HOSTPHYCTRLX_REFCLKSEL_DEFAULT	(0x2 << 23)
 #define EXYNOS_5250_HOSTPHYCTRLX_REFCLKDIV_MASK		(0x7f << 16)
+#define EXYNOS_5250_HOSTPHYCTRLX_REFCLKDIV_12		(0x24 << 16)
+#define EXYNOS_5250_HOSTPHYCTRLX_REFCLKDIV_15		(0x1c << 16)
+#define EXYNOS_5250_HOSTPHYCTRLX_REFCLKDIV_16		(0x1a << 16)
+#define EXYNOS_5250_HOSTPHYCTRLX_REFCLKDIV_19_2		(0x15 << 16)
+#define EXYNOS_5250_HOSTPHYCTRLX_REFCLKDIV_20		(0x14 << 16)
 #define EXYNOS_5250_HOSTPHYCTRLX_SIDDQ			BIT(6)
 #define EXYNOS_5250_HOSTPHYCTRLX_FORCESLEEP		BIT(5)
 #define EXYNOS_5250_HOSTPHYCTRLX_FORCESUSPEND		BIT(4)
@@ -191,13 +197,14 @@ static void exynos5250_isol(struct samsung_usb2_phy_instance *inst, bool on)
 	regmap_update_bits(drv->reg_pmu, offset, mask, on ? 0 : mask);
 }
 
-static void exynos5250_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on)
+static int exynos5250_power_on(struct samsung_usb2_phy_instance *inst)
 {
 	struct samsung_usb2_phy_driver *drv = inst->drv;
 	u32 ctrl0;
 	u32 otg;
 	u32 ehci;
 	u32 ohci;
+	u32 hsic;
 
 	switch (inst->cfg->id) {
 	case EXYNOS5250_DEVICE:
@@ -234,6 +241,8 @@ static void exynos5250_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on)
 
 		break;
 	case EXYNOS5250_HOST:
+	case EXYNOS5250_HSIC0:
+	case EXYNOS5250_HSIC1:
 		/* Host registers configuration */
 		ctrl0 = readl(drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0);
 		/* The clock */
@@ -279,6 +288,18 @@ static void exynos5250_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on)
 			EXYNOS_5250_USBOTGSYS_LINK_SW_RST_UOTG |
 			EXYNOS_5250_USBOTGSYS_PHYLINK_SW_RESET);
 
+		/* HSIC phy configuration */
+		hsic = (EXYNOS_5250_HOSTPHYCTRLX_REFCLKDIV_12 |
+				EXYNOS_5250_HOSTPHYCTRLX_REFCLKSEL_DEFAULT |
+				EXYNOS_5250_HOSTPHYCTRLX_PHYSWRST);
+		writel(hsic, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL1);
+		writel(hsic, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL2);
+		udelay(10);
+		hsic &= ~EXYNOS_5250_HOSTPHYCTRLX_PHYSWRST;
+		writel(hsic, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL1);
+		writel(hsic, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL2);
+		udelay(80);
+
 		/* Enable EHCI DMA burst */
 		ehci = readl(drv->reg_phy + EXYNOS_5250_HOSTEHCICTRL);
 		ehci |=	EXYNOS_5250_HOSTEHCICTRL_ENAINCRXALIGN |
@@ -295,12 +316,7 @@ static void exynos5250_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on)
 
 		break;
 	}
-}
-
-static int exynos5250_power_on(struct samsung_usb2_phy_instance *inst)
-{
 	inst->enabled = 1;
-	exynos5250_phy_pwr(inst, 1);
 	exynos5250_isol(inst, 0);
 
 	return 0;
@@ -308,9 +324,43 @@ static int exynos5250_power_on(struct samsung_usb2_phy_instance *inst)
 
 static int exynos5250_power_off(struct samsung_usb2_phy_instance *inst)
 {
+	struct samsung_usb2_phy_driver *drv = inst->drv;
+	u32 ctrl0;
+	u32 otg;
+	u32 hsic;
+
 	inst->enabled = 0;
 	exynos5250_isol(inst, 1);
-	exynos5250_phy_pwr(inst, 0);
+
+	switch (inst->cfg->id) {
+	case EXYNOS5250_DEVICE:
+		otg = readl(drv->reg_phy + EXYNOS_5250_USBOTGSYS);
+		otg |= (EXYNOS_5250_USBOTGSYS_FORCE_SUSPEND |
+			EXYNOS_5250_USBOTGSYS_SIDDQ_UOTG |
+			EXYNOS_5250_USBOTGSYS_FORCE_SLEEP);
+		writel(otg, drv->reg_phy + EXYNOS_5250_USBOTGSYS);
+		break;
+	case EXYNOS5250_HOST:
+		ctrl0 = readl(drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0);
+		ctrl0 |= (EXYNOS_5250_HOSTPHYCTRL0_SIDDQ |
+				EXYNOS_5250_HOSTPHYCTRL0_FORCESUSPEND |
+				EXYNOS_5250_HOSTPHYCTRL0_FORCESLEEP |
+				EXYNOS_5250_HOSTPHYCTRL0_PHYSWRST |
+				EXYNOS_5250_HOSTPHYCTRL0_PHYSWRSTALL);
+		writel(ctrl0, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0);
+		break;
+	case EXYNOS5250_HSIC0:
+	case EXYNOS5250_HSIC1:
+		hsic = (EXYNOS_5250_HOSTPHYCTRLX_REFCLKDIV_12 |
+				EXYNOS_5250_HOSTPHYCTRLX_REFCLKSEL_DEFAULT |
+				EXYNOS_5250_HOSTPHYCTRLX_SIDDQ |
+				EXYNOS_5250_HOSTPHYCTRLX_FORCESLEEP |
+				EXYNOS_5250_HOSTPHYCTRLX_FORCESUSPEND
+				);
+		writel(hsic, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL1);
+		writel(hsic, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL2);
+		break;
+	}
 
 	return 0;
 }
-- 
1.7.9.5

[PATCH RFC alternative ver 1] phy: Exynos 421x USB 2.0 PHY support

[Kamil Debski]

This the alternative version of the support for Exynos 421x USB 2.0 PHY
in the Generic PHY framework. In this version the support for Exynos
4210 and 4212 was joined into one file.

Signed-off-by: Kamil Debski <k.debski@samsung.com>
---
Hi,

Me and Kishon were discussing for quite a long time the way how Exynos 4
should be handled. I have decided to post the original patches and try
to make an alternative version with support for Exynos 4210 and 4212 joined
in one file. I have prepared two versions. The first one has 506 lines (vs
563 when two files are used). When doing the second version I was a little
more aggresive in removing code. This was done at a cost of adding if's
deciding which SoC version the driver is dealing with in some internal functions.
This resulted in a better number of removed lines - the second version has
only 452 lines (vs 563 original and 506 version 1).

Personally I like the original approach. One of my goals was to create a driver
that would be clear and easy to understand. I see that this was done at a cost of
having the code a little longer.

The first alternative version mostly was done by removing duplicate defines of
register values. The code clarity suffers a bit, but is still acceptable in my
opinion.

As to the second alternative version. It has the fewest lines, but I am not an
enthusiast of using "if this is SoC" in functions.

Anyway - please have a look at these two alternative versions in addition to
looking at the original patch "phy: Add new Exynos USB PHY driver".

Best wishes,
Kamil Debski
---
 drivers/phy/phy-exynos4212-usb2.c |  506 +++++++++++++++++++++++++++++++++++++
 1 file changed, 506 insertions(+)
 create mode 100644 drivers/phy/phy-exynos4212-usb2.c

diff --git a/drivers/phy/phy-exynos4212-usb2.c b/drivers/phy/phy-exynos4212-usb2.c
new file mode 100644
index 0000000..3fa22d0
--- /dev/null
+++ b/drivers/phy/phy-exynos4212-usb2.c
@@ -0,0 +1,506 @@
+/*
+ * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 4210 and 4212 support
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Author: Kamil Debski <k.debski@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+#include "phy-samsung-usb2.h"
+
+/* Exynos USB PHY registers */
+
+/* PHY power control */
+#define EXYNOS_421x_UPHYPWR			0x0
+
+#define EXYNOS_421x_UPHYPWR_PHY0_SUSPEND	BIT(0)
+#define EXYNOS_421x_UPHYPWR_PHY0_PWR		BIT(3)
+#define EXYNOS_421x_UPHYPWR_PHY0_OTG_PWR	BIT(4)
+#define EXYNOS_421x_UPHYPWR_PHY0_SLEEP		BIT(5)
+#define EXYNOS_421x_UPHYPWR_PHY0 ( \
+	EXYNOS_421x_UPHYPWR_PHY0_SUSPEND | \
+	EXYNOS_421x_UPHYPWR_PHY0_PWR | \
+	EXYNOS_421x_UPHYPWR_PHY0_OTG_PWR | \
+	EXYNOS_421x_UPHYPWR_PHY0_SLEEP)
+
+#define EXYNOS_421x_UPHYPWR_PHY1_SUSPEND	BIT(6)
+#define EXYNOS_421x_UPHYPWR_PHY1_PWR		BIT(7)
+#define EXYNOS_421x_UPHYPWR_PHY1_SLEEP		BIT(8)
+#define EXYNOS_421x_UPHYPWR_PHY1 ( \
+	EXYNOS_421x_UPHYPWR_PHY1_SUSPEND | \
+	EXYNOS_421x_UPHYPWR_PHY1_PWR | \
+	EXYNOS_421x_UPHYPWR_PHY1_SLEEP)
+
+#define EXYNOS_4210_UPHYPWR_HSCI0_SUSPEND	BIT(9)
+#define EXYNOS_4210_UPHYPWR_HSCI0_SLEEP		BIT(10)
+#define EXYNOS_4210_UPHYPWR_HSCI0 ( \
+	EXYNOS_4210_UPHYPWR_HSCI0_SUSPEND | \
+	EXYNOS_4210_UPHYPWR_HSCI0_SLEEP)
+
+#define EXYNOS_4210_UPHYPWR_HSCI1_SUSPEND	BIT(11)
+#define EXYNOS_4210_UPHYPWR_HSCI1_SLEEP		BIT(12)
+#define EXYNOS_4210_UPHYPWR_HSCI1 ( \
+	EXYNOS_4210_UPHYPWR_HSCI1_SUSPEND | \
+	EXYNOS_4210_UPHYPWR_HSCI1_SLEEP)
+
+#define EXYNOS_4212_UPHYPWR_HSCI0_SUSPEND	BIT(9)
+#define EXYNOS_4212_UPHYPWR_HSCI0_PWR		BIT(10)
+#define EXYNOS_4212_UPHYPWR_HSCI0_SLEEP		BIT(11)
+#define EXYNOS_4212_UPHYPWR_HSCI0 ( \
+	EXYNOS_4212_UPHYPWR_HSCI0_SUSPEND | \
+	EXYNOS_4212_UPHYPWR_HSCI0_PWR | \
+	EXYNOS_4212_UPHYPWR_HSCI0_SLEEP)
+
+#define EXYNOS_4212_UPHYPWR_HSCI1_SUSPEND	BIT(12)
+#define EXYNOS_4212_UPHYPWR_HSCI1_PWR		BIT(13)
+#define EXYNOS_4212_UPHYPWR_HSCI1_SLEEP		BIT(14)
+#define EXYNOS_4212_UPHYPWR_HSCI1 ( \
+	EXYNOS_4212_UPHYPWR_HSCI1_SUSPEND | \
+	EXYNOS_4212_UPHYPWR_HSCI1_PWR | \
+	EXYNOS_4212_UPHYPWR_HSCI1_SLEEP)
+
+/* PHY clock control */
+#define EXYNOS_421x_UPHYCLK			0x4
+
+#define EXYNOS_421x_UPHYCLK_PHY0_COMMON_ON	BIT(4)
+#define EXYNOS_421x_UPHYCLK_PHY1_COMMON_ON	BIT(7)
+
+#define EXYNOS_4210_UPHYCLK_PHYFSEL_MASK	(0x3 << 0)
+#define EXYNOS_4210_UPHYCLK_PHYFSEL_48MHZ	(0x0 << 0)
+#define EXYNOS_4210_UPHYCLK_PHYFSEL_24MHZ	(0x3 << 0)
+#define EXYNOS_4210_UPHYCLK_PHYFSEL_12MHZ	(0x2 << 0)
+
+#define EXYNOS_4210_UPHYCLK_PHY0_ID_PULLUP	BIT(2)
+
+#define EXYNOS_4212_UPHYCLK_PHYFSEL_MASK	(0x7 << 0)
+#define EXYNOS_4212_UPHYCLK_PHYFSEL_9MHZ6	(0x0 << 0)
+#define EXYNOS_4212_UPHYCLK_PHYFSEL_10MHZ	(0x1 << 0)
+#define EXYNOS_4212_UPHYCLK_PHYFSEL_12MHZ	(0x2 << 0)
+#define EXYNOS_4212_UPHYCLK_PHYFSEL_19MHZ2	(0x3 << 0)
+#define EXYNOS_4212_UPHYCLK_PHYFSEL_20MHZ	(0x4 << 0)
+#define EXYNOS_4212_UPHYCLK_PHYFSEL_24MHZ	(0x5 << 0)
+#define EXYNOS_4212_UPHYCLK_PHYFSEL_50MHZ	(0x7 << 0)
+
+#define EXYNOS_4212_UPHYCLK_PHY0_ID_PULLUP	BIT(3)
+
+#define EXYNOS_4212_UPHYCLK_HSIC_REFCLK_MASK	(0x7f << 10)
+#define EXYNOS_4212_UPHYCLK_HSIC_REFCLK_12MHZ	(0x24 << 10)
+#define EXYNOS_4212_UPHYCLK_HSIC_REFCLK_15MHZ	(0x1c << 10)
+#define EXYNOS_4212_UPHYCLK_HSIC_REFCLK_16MHZ	(0x1a << 10)
+#define EXYNOS_4212_UPHYCLK_HSIC_REFCLK_19MHZ2	(0x15 << 10)
+#define EXYNOS_4212_UPHYCLK_HSIC_REFCLK_20MHZ	(0x14 << 10)
+
+/* PHY reset control */
+#define EXYNOS_421x_UPHYRST			0x8
+
+#define EXYNOS_421x_URSTCON_PHY0		BIT(0)
+#define EXYNOS_421x_URSTCON_OTG_HLINK		BIT(1)
+#define EXYNOS_421x_URSTCON_OTG_PHYLINK		BIT(2)
+
+#define EXYNOS_4210_URSTCON_PHY1_ALL		BIT(3)
+#define EXYNOS_4210_URSTCON_PHY1_P0		BIT(4)
+#define EXYNOS_4210_URSTCON_PHY1_P1P2		BIT(5)
+#define EXYNOS_4210_URSTCON_HOST_LINK_ALL	BIT(6)
+#define EXYNOS_4210_URSTCON_HOST_LINK_P0	BIT(7)
+#define EXYNOS_4210_URSTCON_HOST_LINK_P1	BIT(8)
+#define EXYNOS_4210_URSTCON_HOST_LINK_P2	BIT(9)
+
+#define EXYNOS_4212_URSTCON_HOST_PHY		BIT(3)
+#define EXYNOS_4212_URSTCON_PHY1		BIT(4)
+#define EXYNOS_4212_URSTCON_HSIC0		BIT(5)
+#define EXYNOS_4212_URSTCON_HSIC1		BIT(6)
+#define EXYNOS_4212_URSTCON_HOST_LINK_ALL	BIT(7)
+#define EXYNOS_4212_URSTCON_HOST_LINK_P0	BIT(8)
+#define EXYNOS_4212_URSTCON_HOST_LINK_P1	BIT(9)
+#define EXYNOS_4212_URSTCON_HOST_LINK_P2	BIT(10)
+
+/* Isolation, configured in the power management unit */
+#define EXYNOS_4210_USB_ISOL_DEVICE_OFFSET	0x704
+#define EXYNOS_4210_USB_ISOL_DEVICE		BIT(0)
+#define EXYNOS_4210_USB_ISOL_HOST_OFFSET	0x708
+#define EXYNOS_4210_USB_ISOL_HOST		BIT(0)
+
+#define EXYNOS_4212_USB_ISOL_OFFSET		0x704
+#define EXYNOS_4212_USB_ISOL_OTG		BIT(0)
+#define EXYNOS_4212_USB_ISOL_HSIC0_OFFSET	0x708
+#define EXYNOS_4212_USB_ISOL_HSIC0		BIT(0)
+#define EXYNOS_4212_USB_ISOL_HSIC1_OFFSET	0x70c
+#define EXYNOS_4212_USB_ISOL_HSIC1		BIT(0)
+
+/* USBYPHY1 Floating prevention */
+#define EXYNOS_4210_UPHY1CON			0x34
+#define EXYNOS_4210_UPHY1CON_FLOAT_PREVENTION	0x1
+
+/* Mode switching SUB Device <-> Host */
+#define EXYNOS_421x_MODE_SWITCH_OFFSET		0x21c
+#define EXYNOS_421x_MODE_SWITCH_MASK		1
+#define EXYNOS_421x_MODE_SWITCH_DEVICE		0
+#define EXYNOS_421x_MODE_SWITCH_HOST		1
+
+enum exynos4210_phy_id {
+	EXYNOS4210_DEVICE,
+	EXYNOS4210_HOST,
+	EXYNOS4210_HSIC0,
+	EXYNOS4210_HSIC1,
+	EXYNOS4210_NUM_PHYS,
+};
+
+enum exynos4212_phy_id {
+	EXYNOS4212_DEVICE,
+	EXYNOS4212_HOST,
+	EXYNOS4212_HSIC0,
+	EXYNOS4212_HSIC1,
+	EXYNOS4212_NUM_PHYS,
+};
+
+/*
+ * exynos4210_rate_to_clk() converts the supplied clock rate to the value that
+ * can be written to the phy register.
+ */
+static int exynos4210_rate_to_clk(unsigned long rate, u32 *reg)
+{
+	switch (rate) {
+	case 12 * MHZ:
+		*reg = EXYNOS_4210_UPHYCLK_PHYFSEL_12MHZ;
+		break;
+	case 24 * MHZ:
+		*reg = EXYNOS_4210_UPHYCLK_PHYFSEL_24MHZ;
+		break;
+	case 48 * MHZ:
+		*reg = EXYNOS_4210_UPHYCLK_PHYFSEL_48MHZ;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/*
+ * exynos4212_rate_to_clk() converts the supplied clock rate to the value that
+ * can be written to the phy register.
+ */
+static int exynos4212_rate_to_clk(unsigned long rate, u32 *reg)
+{
+	/* EXYNOS_4212_UPHYCLK_PHYFSEL_MASK */
+
+	switch (rate) {
+	case 9600 * KHZ:
+		*reg = EXYNOS_4212_UPHYCLK_PHYFSEL_9MHZ6;
+		break;
+	case 10 * MHZ:
+		*reg = EXYNOS_4212_UPHYCLK_PHYFSEL_10MHZ;
+		break;
+	case 12 * MHZ:
+		*reg = EXYNOS_4212_UPHYCLK_PHYFSEL_12MHZ;
+		break;
+	case 19200 * KHZ:
+		*reg = EXYNOS_4212_UPHYCLK_PHYFSEL_19MHZ2;
+		break;
+	case 20 * MHZ:
+		*reg = EXYNOS_4212_UPHYCLK_PHYFSEL_20MHZ;
+		break;
+	case 24 * MHZ:
+		*reg = EXYNOS_4212_UPHYCLK_PHYFSEL_24MHZ;
+		break;
+	case 50 * MHZ:
+		*reg = EXYNOS_4212_UPHYCLK_PHYFSEL_50MHZ;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static void exynos4210_isol(struct samsung_usb2_phy_instance *inst, bool on)
+{
+	struct samsung_usb2_phy_driver *drv = inst->drv;
+	u32 offset;
+	u32 mask;
+
+	switch (inst->cfg->id) {
+	case EXYNOS4210_DEVICE:
+		offset = EXYNOS_4210_USB_ISOL_DEVICE_OFFSET;
+		mask = EXYNOS_4210_USB_ISOL_DEVICE;
+		break;
+	case EXYNOS4210_HOST:
+		offset = EXYNOS_4210_USB_ISOL_HOST_OFFSET;
+		mask = EXYNOS_4210_USB_ISOL_HOST;
+		break;
+	default:
+		return;
+	};
+
+	regmap_update_bits(drv->reg_pmu, offset, mask, on ? 0 : mask);
+}
+
+static void exynos4212_isol(struct samsung_usb2_phy_instance *inst, bool on)
+{
+	struct samsung_usb2_phy_driver *drv = inst->drv;
+	u32 offset;
+	u32 mask;
+
+	switch (inst->cfg->id) {
+	case EXYNOS4212_DEVICE:
+	case EXYNOS4212_HOST:
+		offset = EXYNOS_4212_USB_ISOL_OFFSET;
+		mask = EXYNOS_4212_USB_ISOL_OTG;
+		break;
+	case EXYNOS4212_HSIC0:
+		offset = EXYNOS_4212_USB_ISOL_HSIC0_OFFSET;
+		mask = EXYNOS_4212_USB_ISOL_HSIC0;
+		break;
+	case EXYNOS4212_HSIC1:
+		offset = EXYNOS_4212_USB_ISOL_HSIC1_OFFSET;
+		mask = EXYNOS_4212_USB_ISOL_HSIC1;
+		break;
+	default:
+		return;
+	};
+
+	regmap_update_bits(drv->reg_pmu, offset, mask, on ? 0 : mask);
+}
+
+static void exynos4210_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on)
+{
+	struct samsung_usb2_phy_driver *drv = inst->drv;
+	u32 rstbits = 0;
+	u32 phypwr = 0;
+	u32 rst;
+	u32 pwr;
+
+	switch (inst->cfg->id) {
+	case EXYNOS4210_DEVICE:
+		phypwr =	EXYNOS_421x_UPHYPWR_PHY0;
+		rstbits =	EXYNOS_421x_URSTCON_PHY0;
+		break;
+	case EXYNOS4210_HOST:
+		phypwr =	EXYNOS_421x_UPHYPWR_PHY1;
+		rstbits =	EXYNOS_4210_URSTCON_PHY1_ALL |
+				EXYNOS_4210_URSTCON_PHY1_P0 |
+				EXYNOS_4210_URSTCON_PHY1_P1P2 |
+				EXYNOS_4210_URSTCON_HOST_LINK_ALL |
+				EXYNOS_4210_URSTCON_HOST_LINK_P0;
+		writel(on, drv->reg_phy + EXYNOS_4210_UPHY1CON);
+		break;
+	case EXYNOS4210_HSIC0:
+		phypwr =	EXYNOS_4210_UPHYPWR_HSCI0;
+		rstbits =	EXYNOS_4210_URSTCON_PHY1_P1P2 |
+				EXYNOS_4210_URSTCON_HOST_LINK_P1;
+		break;
+	case EXYNOS4210_HSIC1:
+		phypwr =	EXYNOS_4210_UPHYPWR_HSCI1;
+		rstbits =	EXYNOS_4210_URSTCON_PHY1_P1P2 |
+				EXYNOS_4210_URSTCON_HOST_LINK_P2;
+		break;
+	};
+
+	if (on) {
+		writel(inst->clk_reg_val, drv->reg_phy + EXYNOS_421x_UPHYCLK);
+
+		pwr = readl(drv->reg_phy + EXYNOS_421x_UPHYPWR);
+		pwr &= ~phypwr;
+		writel(pwr, drv->reg_phy + EXYNOS_421x_UPHYPWR);
+
+		rst = readl(drv->reg_phy + EXYNOS_421x_UPHYRST);
+		rst |= rstbits;
+		writel(rst, drv->reg_phy + EXYNOS_421x_UPHYRST);
+		udelay(10);
+		rst &= ~rstbits;
+		writel(rst, drv->reg_phy + EXYNOS_421x_UPHYRST);
+	} else {
+		pwr = readl(drv->reg_phy + EXYNOS_421x_UPHYPWR);
+		pwr |= phypwr;
+		writel(pwr, drv->reg_phy + EXYNOS_421x_UPHYPWR);
+	}
+}
+
+static void exynos4212_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on)
+{
+	struct samsung_usb2_phy_driver *drv = inst->drv;
+	u32 rstbits = 0;
+	u32 phypwr = 0;
+	u32 rst;
+	u32 pwr;
+
+	switch (inst->cfg->id) {
+	case EXYNOS4212_DEVICE:
+		phypwr =	EXYNOS_421x_UPHYPWR_PHY0;
+		rstbits =	EXYNOS_421x_URSTCON_PHY0;
+		break;
+	case EXYNOS4212_HOST:
+		phypwr =	EXYNOS_421x_UPHYPWR_PHY1;
+		rstbits =	EXYNOS_4212_URSTCON_HOST_PHY;
+		break;
+	case EXYNOS4212_HSIC0:
+		phypwr =	EXYNOS_4212_UPHYPWR_HSCI0;
+		rstbits =	EXYNOS_4212_URSTCON_HSIC1 |
+				EXYNOS_4212_URSTCON_HOST_LINK_P0 |
+				EXYNOS_4212_URSTCON_HOST_PHY;
+		break;
+	case EXYNOS4212_HSIC1:
+		phypwr =	EXYNOS_4212_UPHYPWR_HSCI1;
+		rstbits =	EXYNOS_4212_URSTCON_HSIC1 |
+				EXYNOS_4212_URSTCON_HOST_LINK_P1;
+		break;
+	};
+
+	if (on) {
+		writel(inst->clk_reg_val, drv->reg_phy + EXYNOS_421x_UPHYCLK);
+
+		pwr = readl(drv->reg_phy + EXYNOS_421x_UPHYPWR);
+		pwr &= ~phypwr;
+		writel(pwr, drv->reg_phy + EXYNOS_421x_UPHYPWR);
+
+		rst = readl(drv->reg_phy + EXYNOS_421x_UPHYRST);
+		rst |= rstbits;
+		writel(rst, drv->reg_phy + EXYNOS_421x_UPHYRST);
+		udelay(10);
+		rst &= ~rstbits;
+		writel(rst, drv->reg_phy + EXYNOS_421x_UPHYRST);
+	} else {
+		pwr = readl(drv->reg_phy + EXYNOS_421x_UPHYPWR);
+		pwr |= phypwr;
+		writel(pwr, drv->reg_phy + EXYNOS_421x_UPHYPWR);
+	}
+}
+
+static int exynos4210_power_on(struct samsung_usb2_phy_instance *inst)
+{
+	/* Order of initialisation is important - first power then isolation */
+	exynos4210_phy_pwr(inst, 1);
+	exynos4210_isol(inst, 0);
+
+	return 0;
+}
+
+static int exynos4210_power_off(struct samsung_usb2_phy_instance *inst)
+{
+	exynos4210_isol(inst, 1);
+	exynos4210_phy_pwr(inst, 0);
+
+	return 0;
+}
+
+static int exynos4212_power_on(struct samsung_usb2_phy_instance *inst)
+{
+	struct samsung_usb2_phy_driver *drv = inst->drv;
+
+	inst->enabled = 1;
+	exynos4212_phy_pwr(inst, 1);
+	exynos4212_isol(inst, 0);
+
+	/* Power on the device, as it is necessary for HSIC to work */
+	if (inst->cfg->id == EXYNOS4212_HSIC0) {
+		struct samsung_usb2_phy_instance *device =
+					&drv->instances[EXYNOS4212_DEVICE];
+		exynos4212_phy_pwr(device, 1);
+		exynos4212_isol(device, 0);
+	}
+
+	return 0;
+}
+
+static int exynos4212_power_off(struct samsung_usb2_phy_instance *inst)
+{
+	struct samsung_usb2_phy_driver *drv = inst->drv;
+	struct samsung_usb2_phy_instance *device =
+					&drv->instances[EXYNOS4212_DEVICE];
+
+	inst->enabled = 0;
+	exynos4212_isol(inst, 1);
+	exynos4212_phy_pwr(inst, 0);
+
+	if (inst->cfg->id == EXYNOS4212_HSIC0 && !device->enabled) {
+		exynos4212_isol(device, 1);
+		exynos4212_phy_pwr(device, 0);
+	}
+
+	return 0;
+}
+
+static const struct samsung_usb2_common_phy exynos4210_phys[] = {
+	{
+		.label		= "device",
+		.id		= EXYNOS4210_DEVICE,
+		.rate_to_clk	= exynos4210_rate_to_clk,
+		.power_on	= exynos4210_power_on,
+		.power_off	= exynos4210_power_off,
+	},
+	{
+		.label		= "host",
+		.id		= EXYNOS4210_HOST,
+		.rate_to_clk	= exynos4210_rate_to_clk,
+		.power_on	= exynos4210_power_on,
+		.power_off	= exynos4210_power_off,
+	},
+	{
+		.label		= "hsic0",
+		.id		= EXYNOS4210_HSIC0,
+		.rate_to_clk	= exynos4210_rate_to_clk,
+		.power_on	= exynos4210_power_on,
+		.power_off	= exynos4210_power_off,
+	},
+	{
+		.label		= "hsic1",
+		.id		= EXYNOS4210_HSIC1,
+		.rate_to_clk	= exynos4210_rate_to_clk,
+		.power_on	= exynos4210_power_on,
+		.power_off	= exynos4210_power_off,
+	},
+	{},
+};
+
+const struct samsung_usb2_phy_config exynos4210_usb2_phy_config = {
+	.num_phys		= EXYNOS4210_NUM_PHYS,
+	.phys			= exynos4210_phys,
+	.has_mode_switch	= 1,
+};
+
+
+static const struct samsung_usb2_common_phy exynos4212_phys[] = {
+	{
+		.label		= "device",
+		.id		= EXYNOS4212_DEVICE,
+		.rate_to_clk	= exynos4212_rate_to_clk,
+		.power_on	= exynos4212_power_on,
+		.power_off	= exynos4212_power_off,
+	},
+	{
+		.label		= "host",
+		.id		= EXYNOS4212_HOST,
+		.rate_to_clk	= exynos4212_rate_to_clk,
+		.power_on	= exynos4212_power_on,
+		.power_off	= exynos4212_power_off,
+	},
+	{
+		.label		= "hsic0",
+		.id		= EXYNOS4212_HSIC0,
+		.rate_to_clk	= exynos4212_rate_to_clk,
+		.power_on	= exynos4212_power_on,
+		.power_off	= exynos4212_power_off,
+	},
+	{
+		.label		= "hsic1",
+		.id		= EXYNOS4212_HSIC1,
+		.rate_to_clk	= exynos4212_rate_to_clk,
+		.power_on	= exynos4212_power_on,
+		.power_off	= exynos4212_power_off,
+	},
+	{},
+};
+
+const struct samsung_usb2_phy_config exynos4212_usb2_phy_config = {
+	.num_phys		= EXYNOS4212_NUM_PHYS,
+	.phys			= exynos4212_phys,
+	.has_mode_switch	= 1,
+};
+
-- 
1.7.9.5

[PATCH RFC alternative ver 2] phy: Exynos 421x USB 2.0 PHY support

[Kamil Debski]

This the alternative version of the support for Exynos 421x USB 2.0 PHY
in the Generic PHY framework. In this version the support for Exynos
4210 and 4212 was joined into one file.

Signed-off-by: Kamil Debski <k.debski@samsung.com>
---
Hi,

This is the second alternative version. Please look at
"[PATCH RFC alternative ver 1] phy: Exynos 421x USB 2.0 PHY support" for
detailed description.

Best wishes,
Kamil Debski
---
 drivers/phy/phy-exynos4212-usb2.c |  452 +++++++++++++++++++++++++++++++++++++
 drivers/phy/phy-samsung-usb2.h    |    1 +
 2 files changed, 453 insertions(+)
 create mode 100644 drivers/phy/phy-exynos4212-usb2.c

diff --git a/drivers/phy/phy-exynos4212-usb2.c b/drivers/phy/phy-exynos4212-usb2.c
new file mode 100644
index 0000000..8f7578a
--- /dev/null
+++ b/drivers/phy/phy-exynos4212-usb2.c
@@ -0,0 +1,452 @@
+/*
+ * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 4210 and 4212 support
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Author: Kamil Debski <k.debski@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+#include "phy-samsung-usb2.h"
+
+/* Exynos USB PHY registers */
+
+/* PHY power control */
+#define EXYNOS_421x_UPHYPWR			0x0
+
+#define EXYNOS_421x_UPHYPWR_PHY0_SUSPEND	BIT(0)
+#define EXYNOS_421x_UPHYPWR_PHY0_PWR		BIT(3)
+#define EXYNOS_421x_UPHYPWR_PHY0_OTG_PWR	BIT(4)
+#define EXYNOS_421x_UPHYPWR_PHY0_SLEEP		BIT(5)
+#define EXYNOS_421x_UPHYPWR_PHY0 ( \
+	EXYNOS_421x_UPHYPWR_PHY0_SUSPEND | \
+	EXYNOS_421x_UPHYPWR_PHY0_PWR | \
+	EXYNOS_421x_UPHYPWR_PHY0_OTG_PWR | \
+	EXYNOS_421x_UPHYPWR_PHY0_SLEEP)
+
+#define EXYNOS_421x_UPHYPWR_PHY1_SUSPEND	BIT(6)
+#define EXYNOS_421x_UPHYPWR_PHY1_PWR		BIT(7)
+#define EXYNOS_421x_UPHYPWR_PHY1_SLEEP		BIT(8)
+#define EXYNOS_421x_UPHYPWR_PHY1 ( \
+	EXYNOS_421x_UPHYPWR_PHY1_SUSPEND | \
+	EXYNOS_421x_UPHYPWR_PHY1_PWR | \
+	EXYNOS_421x_UPHYPWR_PHY1_SLEEP)
+
+#define EXYNOS_4210_UPHYPWR_HSCI0_SUSPEND	BIT(9)
+#define EXYNOS_4210_UPHYPWR_HSCI0_SLEEP		BIT(10)
+#define EXYNOS_4210_UPHYPWR_HSCI0 ( \
+	EXYNOS_4210_UPHYPWR_HSCI0_SUSPEND | \
+	EXYNOS_4210_UPHYPWR_HSCI0_SLEEP)
+
+#define EXYNOS_4210_UPHYPWR_HSCI1_SUSPEND	BIT(11)
+#define EXYNOS_4210_UPHYPWR_HSCI1_SLEEP		BIT(12)
+#define EXYNOS_4210_UPHYPWR_HSCI1 ( \
+	EXYNOS_4210_UPHYPWR_HSCI1_SUSPEND | \
+	EXYNOS_4210_UPHYPWR_HSCI1_SLEEP)
+
+#define EXYNOS_4212_UPHYPWR_HSCI0_SUSPEND	BIT(9)
+#define EXYNOS_4212_UPHYPWR_HSCI0_PWR		BIT(10)
+#define EXYNOS_4212_UPHYPWR_HSCI0_SLEEP		BIT(11)
+#define EXYNOS_4212_UPHYPWR_HSCI0 ( \
+	EXYNOS_4212_UPHYPWR_HSCI0_SUSPEND | \
+	EXYNOS_4212_UPHYPWR_HSCI0_PWR | \
+	EXYNOS_4212_UPHYPWR_HSCI0_SLEEP)
+
+#define EXYNOS_4212_UPHYPWR_HSCI1_SUSPEND	BIT(12)
+#define EXYNOS_4212_UPHYPWR_HSCI1_PWR		BIT(13)
+#define EXYNOS_4212_UPHYPWR_HSCI1_SLEEP		BIT(14)
+#define EXYNOS_4212_UPHYPWR_HSCI1 ( \
+	EXYNOS_4212_UPHYPWR_HSCI1_SUSPEND | \
+	EXYNOS_4212_UPHYPWR_HSCI1_PWR | \
+	EXYNOS_4212_UPHYPWR_HSCI1_SLEEP)
+
+/* PHY clock control */
+#define EXYNOS_421x_UPHYCLK			0x4
+
+#define EXYNOS_421x_UPHYCLK_PHY0_COMMON_ON	BIT(4)
+#define EXYNOS_421x_UPHYCLK_PHY1_COMMON_ON	BIT(7)
+
+#define EXYNOS_4210_UPHYCLK_PHYFSEL_MASK	(0x3 << 0)
+#define EXYNOS_4210_UPHYCLK_PHYFSEL_48MHZ	(0x0 << 0)
+#define EXYNOS_4210_UPHYCLK_PHYFSEL_24MHZ	(0x3 << 0)
+#define EXYNOS_4210_UPHYCLK_PHYFSEL_12MHZ	(0x2 << 0)
+
+#define EXYNOS_4210_UPHYCLK_PHY0_ID_PULLUP	BIT(2)
+
+#define EXYNOS_4212_UPHYCLK_PHYFSEL_MASK	(0x7 << 0)
+#define EXYNOS_4212_UPHYCLK_PHYFSEL_9MHZ6	(0x0 << 0)
+#define EXYNOS_4212_UPHYCLK_PHYFSEL_10MHZ	(0x1 << 0)
+#define EXYNOS_4212_UPHYCLK_PHYFSEL_12MHZ	(0x2 << 0)
+#define EXYNOS_4212_UPHYCLK_PHYFSEL_19MHZ2	(0x3 << 0)
+#define EXYNOS_4212_UPHYCLK_PHYFSEL_20MHZ	(0x4 << 0)
+#define EXYNOS_4212_UPHYCLK_PHYFSEL_24MHZ	(0x5 << 0)
+#define EXYNOS_4212_UPHYCLK_PHYFSEL_50MHZ	(0x7 << 0)
+
+#define EXYNOS_4212_UPHYCLK_PHY0_ID_PULLUP	BIT(3)
+
+#define EXYNOS_4212_UPHYCLK_HSIC_REFCLK_MASK	(0x7f << 10)
+#define EXYNOS_4212_UPHYCLK_HSIC_REFCLK_12MHZ	(0x24 << 10)
+#define EXYNOS_4212_UPHYCLK_HSIC_REFCLK_15MHZ	(0x1c << 10)
+#define EXYNOS_4212_UPHYCLK_HSIC_REFCLK_16MHZ	(0x1a << 10)
+#define EXYNOS_4212_UPHYCLK_HSIC_REFCLK_19MHZ2	(0x15 << 10)
+#define EXYNOS_4212_UPHYCLK_HSIC_REFCLK_20MHZ	(0x14 << 10)
+
+/* PHY reset control */
+#define EXYNOS_421x_UPHYRST			0x8
+
+#define EXYNOS_421x_URSTCON_PHY0		BIT(0)
+#define EXYNOS_421x_URSTCON_OTG_HLINK		BIT(1)
+#define EXYNOS_421x_URSTCON_OTG_PHYLINK		BIT(2)
+
+#define EXYNOS_4210_URSTCON_PHY1_ALL		BIT(3)
+#define EXYNOS_4210_URSTCON_PHY1_P0		BIT(4)
+#define EXYNOS_4210_URSTCON_PHY1_P1P2		BIT(5)
+#define EXYNOS_4210_URSTCON_HOST_LINK_ALL	BIT(6)
+#define EXYNOS_4210_URSTCON_HOST_LINK_P0	BIT(7)
+#define EXYNOS_4210_URSTCON_HOST_LINK_P1	BIT(8)
+#define EXYNOS_4210_URSTCON_HOST_LINK_P2	BIT(9)
+
+#define EXYNOS_4212_URSTCON_HOST_PHY		BIT(3)
+#define EXYNOS_4212_URSTCON_PHY1		BIT(4)
+#define EXYNOS_4212_URSTCON_HSIC0		BIT(5)
+#define EXYNOS_4212_URSTCON_HSIC1		BIT(6)
+#define EXYNOS_4212_URSTCON_HOST_LINK_ALL	BIT(7)
+#define EXYNOS_4212_URSTCON_HOST_LINK_P0	BIT(8)
+#define EXYNOS_4212_URSTCON_HOST_LINK_P1	BIT(9)
+#define EXYNOS_4212_URSTCON_HOST_LINK_P2	BIT(10)
+
+/* Isolation, configured in the power management unit */
+#define EXYNOS_4210_USB_ISOL_DEVICE_OFFSET	0x704
+#define EXYNOS_4210_USB_ISOL_DEVICE		BIT(0)
+#define EXYNOS_4210_USB_ISOL_HOST_OFFSET	0x708
+#define EXYNOS_4210_USB_ISOL_HOST		BIT(0)
+
+#define EXYNOS_4212_USB_ISOL_OFFSET		0x704
+#define EXYNOS_4212_USB_ISOL_OTG		BIT(0)
+#define EXYNOS_4212_USB_ISOL_HSIC0_OFFSET	0x708
+#define EXYNOS_4212_USB_ISOL_HSIC0		BIT(0)
+#define EXYNOS_4212_USB_ISOL_HSIC1_OFFSET	0x70c
+#define EXYNOS_4212_USB_ISOL_HSIC1		BIT(0)
+
+/* USBYPHY1 Floating prevention */
+#define EXYNOS_4210_UPHY1CON			0x34
+#define EXYNOS_4210_UPHY1CON_FLOAT_PREVENTION	0x1
+
+/* Mode switching SUB Device <-> Host */
+#define EXYNOS_421x_MODE_SWITCH_OFFSET		0x21c
+#define EXYNOS_421x_MODE_SWITCH_MASK		1
+#define EXYNOS_421x_MODE_SWITCH_DEVICE		0
+#define EXYNOS_421x_MODE_SWITCH_HOST		1
+
+enum exynos421x_phy_id {
+	EXYNOS421x_DEVICE,
+	EXYNOS421x_HOST,
+	EXYNOS421x_HSIC0,
+	EXYNOS421x_HSIC1,
+	EXYNOS421x_NUM_PHYS,
+};
+
+/*
+ * exynos4210_rate_to_clk() converts the supplied clock rate to the value that
+ * can be written to the phy register.
+ */
+static int exynos4210_rate_to_clk(unsigned long rate, u32 *reg)
+{
+	switch (rate) {
+	case 12 * MHZ:
+		*reg = EXYNOS_4210_UPHYCLK_PHYFSEL_12MHZ;
+		break;
+	case 24 * MHZ:
+		*reg = EXYNOS_4210_UPHYCLK_PHYFSEL_24MHZ;
+		break;
+	case 48 * MHZ:
+		*reg = EXYNOS_4210_UPHYCLK_PHYFSEL_48MHZ;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/*
+ * exynos4212_rate_to_clk() converts the supplied clock rate to the value that
+ * can be written to the phy register.
+ */
+static int exynos4212_rate_to_clk(unsigned long rate, u32 *reg)
+{
+	/* EXYNOS_4212_UPHYCLK_PHYFSEL_MASK */
+
+	switch (rate) {
+	case 9600 * KHZ:
+		*reg = EXYNOS_4212_UPHYCLK_PHYFSEL_9MHZ6;
+		break;
+	case 10 * MHZ:
+		*reg = EXYNOS_4212_UPHYCLK_PHYFSEL_10MHZ;
+		break;
+	case 12 * MHZ:
+		*reg = EXYNOS_4212_UPHYCLK_PHYFSEL_12MHZ;
+		break;
+	case 19200 * KHZ:
+		*reg = EXYNOS_4212_UPHYCLK_PHYFSEL_19MHZ2;
+		break;
+	case 20 * MHZ:
+		*reg = EXYNOS_4212_UPHYCLK_PHYFSEL_20MHZ;
+		break;
+	case 24 * MHZ:
+		*reg = EXYNOS_4212_UPHYCLK_PHYFSEL_24MHZ;
+		break;
+	case 50 * MHZ:
+		*reg = EXYNOS_4212_UPHYCLK_PHYFSEL_50MHZ;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static void exynos421x_isol(struct samsung_usb2_phy_instance *inst, bool on)
+{
+	struct samsung_usb2_phy_driver *drv = inst->drv;
+	u32 offset;
+	u32 mask;
+
+	if (inst->cfg->is_exynos4212) {
+		switch (inst->cfg->id) {
+		case EXYNOS421x_DEVICE:
+		case EXYNOS421x_HOST:
+			offset = EXYNOS_4212_USB_ISOL_OFFSET;
+			mask = EXYNOS_4212_USB_ISOL_OTG;
+			break;
+		case EXYNOS421x_HSIC0:
+			offset = EXYNOS_4212_USB_ISOL_HSIC0_OFFSET;
+			mask = EXYNOS_4212_USB_ISOL_HSIC0;
+			break;
+		case EXYNOS421x_HSIC1:
+			offset = EXYNOS_4212_USB_ISOL_HSIC1_OFFSET;
+			mask = EXYNOS_4212_USB_ISOL_HSIC1;
+			break;
+		default:
+			return;
+		};
+	} else {
+		switch (inst->cfg->id) {
+		case EXYNOS421x_DEVICE:
+			offset = EXYNOS_4210_USB_ISOL_DEVICE_OFFSET;
+			mask = EXYNOS_4210_USB_ISOL_DEVICE;
+			break;
+		case EXYNOS421x_HOST:
+			offset = EXYNOS_4210_USB_ISOL_HOST_OFFSET;
+			mask = EXYNOS_4210_USB_ISOL_HOST;
+			break;
+		default:
+			return;
+		}
+	}
+
+	regmap_update_bits(drv->reg_pmu, offset, mask, on ? 0 : mask);
+}
+
+static void exynos421x_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on)
+{
+	struct samsung_usb2_phy_driver *drv = inst->drv;
+	u32 rstbits = 0;
+	u32 phypwr = 0;
+	u32 rst;
+	u32 pwr;
+
+	if (inst->cfg->is_exynos4212) {
+		switch (inst->cfg->id) {
+		case EXYNOS421x_DEVICE:
+			phypwr =	EXYNOS_421x_UPHYPWR_PHY0;
+			rstbits =	EXYNOS_421x_URSTCON_PHY0;
+			break;
+		case EXYNOS421x_HOST:
+			phypwr =	EXYNOS_421x_UPHYPWR_PHY1;
+			rstbits =	EXYNOS_4212_URSTCON_HOST_PHY;
+			break;
+		case EXYNOS421x_HSIC0:
+			phypwr =	EXYNOS_4212_UPHYPWR_HSCI0;
+			rstbits =	EXYNOS_4212_URSTCON_HSIC1 |
+					EXYNOS_4212_URSTCON_HOST_LINK_P0 |
+					EXYNOS_4212_URSTCON_HOST_PHY;
+			break;
+		case EXYNOS421x_HSIC1:
+			phypwr =	EXYNOS_4212_UPHYPWR_HSCI1;
+			rstbits =	EXYNOS_4212_URSTCON_HSIC1 |
+					EXYNOS_4212_URSTCON_HOST_LINK_P1;
+			break;
+		};
+	} else {
+		switch (inst->cfg->id) {
+		case EXYNOS421x_DEVICE:
+			phypwr =	EXYNOS_421x_UPHYPWR_PHY0;
+			rstbits =	EXYNOS_421x_URSTCON_PHY0;
+			break;
+		case EXYNOS421x_HOST:
+			phypwr =	EXYNOS_421x_UPHYPWR_PHY1;
+			rstbits =	EXYNOS_4210_URSTCON_PHY1_ALL |
+					EXYNOS_4210_URSTCON_PHY1_P0 |
+					EXYNOS_4210_URSTCON_PHY1_P1P2 |
+					EXYNOS_4210_URSTCON_HOST_LINK_ALL |
+					EXYNOS_4210_URSTCON_HOST_LINK_P0;
+			writel(on, drv->reg_phy + EXYNOS_4210_UPHY1CON);
+			break;
+		case EXYNOS421x_HSIC0:
+			phypwr =	EXYNOS_4210_UPHYPWR_HSCI0;
+			rstbits =	EXYNOS_4210_URSTCON_PHY1_P1P2 |
+					EXYNOS_4210_URSTCON_HOST_LINK_P1;
+			break;
+		case EXYNOS421x_HSIC1:
+			phypwr =	EXYNOS_4210_UPHYPWR_HSCI1;
+			rstbits =	EXYNOS_4210_URSTCON_PHY1_P1P2 |
+					EXYNOS_4210_URSTCON_HOST_LINK_P2;
+			break;
+		};
+	}
+
+	if (on) {
+		writel(inst->clk_reg_val, drv->reg_phy + EXYNOS_421x_UPHYCLK);
+
+		pwr = readl(drv->reg_phy + EXYNOS_421x_UPHYPWR);
+		pwr &= ~phypwr;
+		writel(pwr, drv->reg_phy + EXYNOS_421x_UPHYPWR);
+
+		rst = readl(drv->reg_phy + EXYNOS_421x_UPHYRST);
+		rst |= rstbits;
+		writel(rst, drv->reg_phy + EXYNOS_421x_UPHYRST);
+		udelay(10);
+		rst &= ~rstbits;
+		writel(rst, drv->reg_phy + EXYNOS_421x_UPHYRST);
+	} else {
+		pwr = readl(drv->reg_phy + EXYNOS_421x_UPHYPWR);
+		pwr |= phypwr;
+		writel(pwr, drv->reg_phy + EXYNOS_421x_UPHYPWR);
+	}
+}
+
+static int exynos421x_power_on(struct samsung_usb2_phy_instance *inst)
+{
+	struct samsung_usb2_phy_driver *drv = inst->drv;
+
+	inst->enabled = 1;
+	exynos421x_phy_pwr(inst, 1);
+	exynos421x_isol(inst, 0);
+
+	/* Power on the device, as it is necessary for HSIC to work */
+	if (inst->cfg->is_exynos4212 && inst->cfg->id == EXYNOS421x_HSIC0) {
+		struct samsung_usb2_phy_instance *device =
+					&drv->instances[EXYNOS421x_DEVICE];
+		exynos421x_phy_pwr(device, 1);
+		exynos421x_isol(device, 0);
+	}
+
+	return 0;
+}
+
+static int exynos421x_power_off(struct samsung_usb2_phy_instance *inst)
+{
+	struct samsung_usb2_phy_driver *drv = inst->drv;
+	struct samsung_usb2_phy_instance *device =
+					&drv->instances[EXYNOS421x_DEVICE];
+
+	inst->enabled = 0;
+	exynos421x_isol(inst, 1);
+	exynos421x_phy_pwr(inst, 0);
+
+	if (inst->cfg->is_exynos4212 && inst->cfg->id == EXYNOS421x_HSIC0 &&
+							!device->enabled) {
+		exynos421x_isol(device, 1);
+		exynos421x_phy_pwr(device, 0);
+	}
+
+	return 0;
+}
+
+static const struct samsung_usb2_common_phy exynos4210_phys[] = {
+	{
+		.label		= "device",
+		.id		= EXYNOS421x_DEVICE,
+		.rate_to_clk	= exynos4210_rate_to_clk,
+		.power_on	= exynos421x_power_on,
+		.power_off	= exynos421x_power_off,
+	},
+	{
+		.label		= "host",
+		.id		= EXYNOS421x_HOST,
+		.rate_to_clk	= exynos4210_rate_to_clk,
+		.power_on	= exynos421x_power_on,
+		.power_off	= exynos421x_power_off,
+	},
+	{
+		.label		= "hsic0",
+		.id		= EXYNOS421x_HSIC0,
+		.rate_to_clk	= exynos4210_rate_to_clk,
+		.power_on	= exynos421x_power_on,
+		.power_off	= exynos421x_power_off,
+	},
+	{
+		.label		= "hsic1",
+		.id		= EXYNOS421x_HSIC1,
+		.rate_to_clk	= exynos4210_rate_to_clk,
+		.power_on	= exynos421x_power_on,
+		.power_off	= exynos421x_power_off,
+	},
+	{},
+};
+
+const struct samsung_usb2_phy_config exynos4210_usb2_phy_config = {
+	.num_phys		= EXYNOS421x_NUM_PHYS,
+	.phys			= exynos4210_phys,
+	.has_mode_switch	= 1,
+};
+
+static const struct samsung_usb2_common_phy exynos4212_phys[] = {
+	{
+		.label		= "device",
+		.id		= EXYNOS421x_DEVICE,
+		.rate_to_clk	= exynos4212_rate_to_clk,
+		.power_on	= exynos421x_power_on,
+		.power_off	= exynos421x_power_off,
+		.is_exynos4212	= 1,
+	},
+	{
+		.label		= "host",
+		.id		= EXYNOS421x_HOST,
+		.rate_to_clk	= exynos4212_rate_to_clk,
+		.power_on	= exynos421x_power_on,
+		.power_off	= exynos421x_power_off,
+		.is_exynos4212	= 1,
+	},
+	{
+		.label		= "hsic0",
+		.id		= EXYNOS421x_HSIC0,
+		.rate_to_clk	= exynos4212_rate_to_clk,
+		.power_on	= exynos421x_power_on,
+		.power_off	= exynos421x_power_off,
+		.is_exynos4212	= 1,
+	},
+	{
+		.label		= "hsic1",
+		.id		= EXYNOS421x_HSIC1,
+		.rate_to_clk	= exynos4212_rate_to_clk,
+		.power_on	= exynos421x_power_on,
+		.power_off	= exynos421x_power_off,
+		.is_exynos4212	= 1,
+	},
+	{},
+};
+
+const struct samsung_usb2_phy_config exynos4212_usb2_phy_config = {
+	.num_phys		= EXYNOS421x_NUM_PHYS,
+	.phys			= exynos4212_phys,
+	.has_mode_switch	= 1,
+};
+
diff --git a/drivers/phy/phy-samsung-usb2.h b/drivers/phy/phy-samsung-usb2.h
index ab89f91..db02692 100644
--- a/drivers/phy/phy-samsung-usb2.h
+++ b/drivers/phy/phy-samsung-usb2.h
@@ -52,6 +52,7 @@ struct samsung_usb2_common_phy {
 	int (*power_off)(struct samsung_usb2_phy_instance *);
 	unsigned int id;
 	char *label;
+	bool is_exynos4212;
 };
 
 
-- 
1.7.9.5

Re: [PATCH v5 4/9] usb: ehci-s5p: Change to use phy provided by the generic phy framework

[Vivek Gautam]

Hi Kamil,


On Fri, Dec 20, 2013 at 6:54 PM, Kamil Debski <k.debski@samsung.com> wrote:
> Change the phy provider used from the old one using the USB phy
> framework to a new one using the Generic phy framework.
>
> Signed-off-by: Kamil Debski <k.debski@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>

Commit title:
s/ehci-s5p/ehci-exynos

> ---
>  Documentation/devicetree/bindings/usb/usb-ehci.txt |   35 +++++++
>  drivers/usb/host/ehci-exynos.c                     |   97 +++++++++++++-------
>  2 files changed, 98 insertions(+), 34 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/usb/usb-ehci.txt b/Documentation/devicetree/bindings/usb/usb-ehci.txt
> index fa18612..413f7cd 100644
> --- a/Documentation/devicetree/bindings/usb/usb-ehci.txt
> +++ b/Documentation/devicetree/bindings/usb/usb-ehci.txt
> @@ -14,6 +14,10 @@ If controller implementation operates with big endian descriptors,
>  If both big endian registers and descriptors are used by the controller
>  implementation, "big-endian" property can be specified instead of having
>  both "big-endian-regs" and "big-endian-desc".
> +  - port: if in the SoC there are EHCI phys, they should be listed here.
> +One phy per port. Each port should have its reg entry with a consecutive
> +number. Also it should contain phys and phy-names entries specifying the
> +phy used by the port.
>
>  Example (Sequoia 440EPx):
>      ehci@e0000300 {
> @@ -23,3 +27,34 @@ Example (Sequoia 440EPx):
>            reg = <0 e0000300 90 0 e0000390 70>;
>            big-endian;
>     };
> +
> +Example (Exynos 4212):
> +    ehci@12580000 {
> +        compatible = "samsung,exynos4210-ehci";
> +        reg = <0x12580000 0x20000>;
> +        interrupts = <0 70 0>;
> +        clocks = <&clock 304>, <&clock 305>;
> +        clock-names = "usbhost", "otg";
> +        status = "disabled";
> +        #address-cells = <1>;
> +        #size-cells = <0>;
> +        port@0 {
> +            reg = <0>;
> +            phys = <&usb2phy 1>;
> +            phy-names = "host";
> +            status = "disabled";
> +        };
> +        port@1 {
> +            reg = <1>;
> +            phys = <&usb2phy 2>;
> +            phy-names = "hsic0";
> +            status = "disabled";
> +        };
> +        port@2 {
> +            reg = <2>;
> +            phys = <&usb2phy 3>;
> +            phy-names = "hsic1";
> +            status = "disabled";
> +        };
> +    };

Should we place above documentation in
"Documentation/devicetree/bindings/usb/exynos-usb.txt" ?
or is it something that i am missing.

> +
> diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c
> index d1d8c47..7c35501 100644
> --- a/drivers/usb/host/ehci-exynos.c
> +++ b/drivers/usb/host/ehci-exynos.c
> @@ -19,12 +19,12 @@
>  #include <linux/module.h>
>  #include <linux/of.h>
>  #include <linux/of_gpio.h>
> +#include <linux/phy/phy.h>
>  #include <linux/platform_device.h>
>  #include <linux/usb/phy.h>
>  #include <linux/usb/samsung_usb_phy.h>
>  #include <linux/usb.h>
>  #include <linux/usb/hcd.h>
> -#include <linux/usb/otg.h>
>
>  #include "ehci.h"
>
> @@ -42,10 +42,10 @@
>  static const char hcd_name[] = "ehci-exynos";
>  static struct hc_driver __read_mostly exynos_ehci_hc_driver;
>
> +#define PHY_NUMBER 3
>  struct exynos_ehci_hcd {
>         struct clk *clk;
> -       struct usb_phy *phy;
> -       struct usb_otg *otg;
> +       struct phy *phy[PHY_NUMBER];
>  };
>
>  #define to_exynos_ehci(hcd) (struct exynos_ehci_hcd *)(hcd_to_ehci(hcd)->priv)
> @@ -69,13 +69,43 @@ static void exynos_setup_vbus_gpio(struct platform_device *pdev)
>                 dev_err(dev, "can't request ehci vbus gpio %d", gpio);
>  }
>
> +static int exynos_phys_on(struct phy *p[])
> +{
> +       int i;
> +       int ret = 0;
> +
> +       for (i = 0; ret == 0 && i < PHY_NUMBER; i++)
> +               if (p[i])
> +                       ret = phy_power_on(p[i]);
> +       if (ret)
> +               for (i--; i > 0; i--)
> +                       if (p[i])
> +                               phy_power_off(p[i]);

So we are turning off, say, port0 phy in case port1 phy power_on fails;
can't we still leave a usb2.0 phy(a normal host phy) 'on' in case the
HSIC phy fails ?

> +
> +       return ret;
> +}
> +
> +static int exynos_phys_off(struct phy *p[])
> +{
> +       int i;
> +       int ret = 0;
> +
> +       for (i = 0; ret == 0 && i < PHY_NUMBER; i++)
> +               if (p[i])
> +                       ret = phy_power_off(p[i]);
> +
> +       return ret;
> +}
> +
>  static int exynos_ehci_probe(struct platform_device *pdev)
>  {
>         struct exynos_ehci_hcd *exynos_ehci;
>         struct usb_hcd *hcd;
>         struct ehci_hcd *ehci;
>         struct resource *res;
> -       struct usb_phy *phy;
> +       struct phy *phy;
> +       struct device_node *child;
> +       int phy_number;
>         int irq;
>         int err;
>
> @@ -102,14 +132,26 @@ static int exynos_ehci_probe(struct platform_device *pdev)
>                                         "samsung,exynos5440-ehci"))
>                 goto skip_phy;
>
> -       phy = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2);
> -       if (IS_ERR(phy)) {
> -               usb_put_hcd(hcd);
> -               dev_warn(&pdev->dev, "no platform data or transceiver defined\n");
> -               return -EPROBE_DEFER;
> -       } else {
> -               exynos_ehci->phy = phy;
> -               exynos_ehci->otg = phy->otg;
> +       for_each_available_child_of_node(pdev->dev.of_node, child) {
> +               err = of_property_read_u32(child, "reg", &phy_number);
> +               if (err) {
> +                       dev_err(&pdev->dev, "Failed to parse device tree\n");
> +                       of_node_put(child);
> +                       return err;
> +               }
> +               if (phy_number >= PHY_NUMBER) {
> +                       dev_err(&pdev->dev, "Failed to parse device tree - number out of range\n");
> +                       of_node_put(child);
> +                       return -EINVAL;
> +               }
> +               phy = devm_of_phy_get(&pdev->dev, child, 0);
> +               of_node_put(child);
> +               if (IS_ERR(phy)) {
> +                       dev_err(&pdev->dev, "Failed to get phy number %d",
> +                                                               phy_number);
> +                       return PTR_ERR(phy);
> +               }
> +               exynos_ehci->phy[phy_number] = phy;
>         }
>
>  skip_phy:
> @@ -149,11 +191,11 @@ skip_phy:
>                 goto fail_io;
>         }
>
> -       if (exynos_ehci->otg)
> -               exynos_ehci->otg->set_host(exynos_ehci->otg, &hcd->self);
> -
> -       if (exynos_ehci->phy)
> -               usb_phy_init(exynos_ehci->phy);
> +       err = exynos_phys_on(exynos_ehci->phy);
> +       if (err) {
> +               dev_err(&pdev->dev, "Failed to enabled phys\n");
> +               goto fail_io;
> +       }
>
>         ehci = hcd_to_ehci(hcd);
>         ehci->caps = hcd->regs;
> @@ -173,8 +215,7 @@ skip_phy:
>         return 0;
>
>  fail_add_hcd:
> -       if (exynos_ehci->phy)
> -               usb_phy_shutdown(exynos_ehci->phy);
> +       exynos_phys_off(exynos_ehci->phy);
>  fail_io:
>         clk_disable_unprepare(exynos_ehci->clk);
>  fail_clk:
> @@ -189,11 +230,7 @@ static int exynos_ehci_remove(struct platform_device *pdev)
>
>         usb_remove_hcd(hcd);
>
> -       if (exynos_ehci->otg)
> -               exynos_ehci->otg->set_host(exynos_ehci->otg, &hcd->self);
> -
> -       if (exynos_ehci->phy)
> -               usb_phy_shutdown(exynos_ehci->phy);
> +       exynos_phys_off(exynos_ehci->phy);
>
>         clk_disable_unprepare(exynos_ehci->clk);
>
> @@ -213,11 +250,7 @@ static int exynos_ehci_suspend(struct device *dev)
>
>         rc = ehci_suspend(hcd, do_wakeup);
>
> -       if (exynos_ehci->otg)
> -               exynos_ehci->otg->set_host(exynos_ehci->otg, &hcd->self);
> -
> -       if (exynos_ehci->phy)
> -               usb_phy_shutdown(exynos_ehci->phy);
> +       exynos_phys_off(exynos_ehci->phy);
>
>         clk_disable_unprepare(exynos_ehci->clk);
>
> @@ -231,11 +264,7 @@ static int exynos_ehci_resume(struct device *dev)
>
>         clk_prepare_enable(exynos_ehci->clk);
>
> -       if (exynos_ehci->otg)
> -               exynos_ehci->otg->set_host(exynos_ehci->otg, &hcd->self);
> -
> -       if (exynos_ehci->phy)
> -               usb_phy_init(exynos_ehci->phy);
> +       exynos_phys_on(exynos_ehci->phy);
>
>         /* DMA burst Enable */
>         writel(EHCI_INSNREG00_ENABLE_DMA_BURST, EHCI_INSNREG00(hcd->regs));
> --

Rest all looks good. :-)
I tested this patch along with other patches in the series on smdk5250.

Tested-by: Vivek Gautam <gautam.vivek@samsung.com>

> 1.7.9.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



-- 
Best Regards
Vivek Gautam
Samsung R&D Institute, Bangalore
India

Re: [PATCH v2 9/9] dts: Add usb2phy to Exynos 5250

[Vivek Gautam]

Hi Kamil,


On Fri, Dec 20, 2013 at 6:54 PM, Kamil Debski <k.debski@samsung.com> wrote:
> Add support to PHY of USB2 of the Exynos 5250 SoC.
>
> Signed-off-by: Kamil Debski <k.debski@samsung.com>
> ---
>  arch/arm/boot/dts/exynos5250.dtsi |   33 ++++++++++++-------
>  drivers/phy/phy-exynos5250-usb2.c |   64 +++++++++++++++++++++++++++++++++----
>  2 files changed, 78 insertions(+), 19 deletions(-)
>
> diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
> index 2f264ad..922e0ed 100644
> --- a/arch/arm/boot/dts/exynos5250.dtsi
> +++ b/arch/arm/boot/dts/exynos5250.dtsi
> @@ -163,6 +163,11 @@
>                 interrupts = <0 47 0>;
>         };
>
> +       sys_syscon: syscon@10040000 {
> +               compatible = "samsung,exynos5250-sys", "syscon";
> +               reg = <0x10050000 0x5000>;
> +       };
> +
>         pmu_syscon: syscon@10040000 {
>                 compatible = "samsung,exynos5250-pmu", "syscon";
>                 reg = <0x10040000 0x5000>;
> @@ -505,6 +510,14 @@
>
>                 clocks = <&clock 285>;
>                 clock-names = "usbhost";
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +               port@0 {
> +                       reg = <0>;
> +                       phys = <&usb2_phy 1>;
> +                       phy-names = "host";
> +                       status = "ok";
> +               };
>         };
>
>         usb@12120000 {
> @@ -516,19 +529,15 @@
>                 clock-names = "usbhost";
>         };
>
> -       usb2_phy: usbphy@12130000 {
> -               compatible = "samsung,exynos5250-usb2phy";
> +       usb2_phy: phy@12130000 {
> +               compatible = "samsung,exynos5250-usb2-phy";
>                 reg = <0x12130000 0x100>;
> -               clocks = <&clock 1>, <&clock 285>;
> -               clock-names = "ext_xtal", "usbhost";
> -               #address-cells = <1>;
> -               #size-cells = <1>;
> -               ranges;
> -
> -               usbphy-sys {
> -                       reg = <0x10040704 0x8>,
> -                             <0x10050230 0x4>;
> -               };
> +               clocks = <&clock 285>, <&clock 1>, <&clock 1>, <&clock 1>,
> +                                                               <&clock 1>;
> +               clock-names = "phy", "device", "host", "hsic0", "hsic1";
> +               #phy-cells = <1>;
> +               samsung,sysreg-phandle = <&sys_syscon>;
> +               samsung,pmureg-phandle = <&pmu_syscon>;
>         };
>
>         amba {
> diff --git a/drivers/phy/phy-exynos5250-usb2.c b/drivers/phy/phy-exynos5250-usb2.c
> index b9b3b98..337bf82 100644
> --- a/drivers/phy/phy-exynos5250-usb2.c
> +++ b/drivers/phy/phy-exynos5250-usb2.c

Separate patches for dt and driver ?
I think you wanted to move these changes to :
[PATCH v5 7/9] phy: Add Exynos 5250 support to the Exynos USB 2.0 PHY driver

> @@ -58,7 +58,13 @@
>  #define EXYNOS_5250_HOSTPHYCTRL2                       0x20

Shouldn't we leave the naming as EXYNOS_5250_HSICPHYCTRL2 instead of
EXYNOS_5250_HOSTPHYCTRL2 ? That will go in sync with the user-manual too.
and similar for EXYNOS_5250_HOSTPHYCTRL1 and below bit definitions too ?

>
>  #define EXYNOS_5250_HOSTPHYCTRLX_REFCLKSEL_MASK                (0x3 << 23)
> +#define EXYNOS_5250_HOSTPHYCTRLX_REFCLKSEL_DEFAULT     (0x2 << 23)
>  #define EXYNOS_5250_HOSTPHYCTRLX_REFCLKDIV_MASK                (0x7f << 16)
> +#define EXYNOS_5250_HOSTPHYCTRLX_REFCLKDIV_12          (0x24 << 16)
> +#define EXYNOS_5250_HOSTPHYCTRLX_REFCLKDIV_15          (0x1c << 16)
> +#define EXYNOS_5250_HOSTPHYCTRLX_REFCLKDIV_16          (0x1a << 16)
> +#define EXYNOS_5250_HOSTPHYCTRLX_REFCLKDIV_19_2                (0x15 << 16)
> +#define EXYNOS_5250_HOSTPHYCTRLX_REFCLKDIV_20          (0x14 << 16)
>  #define EXYNOS_5250_HOSTPHYCTRLX_SIDDQ                 BIT(6)
>  #define EXYNOS_5250_HOSTPHYCTRLX_FORCESLEEP            BIT(5)
>  #define EXYNOS_5250_HOSTPHYCTRLX_FORCESUSPEND          BIT(4)
> @@ -191,13 +197,14 @@ static void exynos5250_isol(struct samsung_usb2_phy_instance *inst, bool on)
>         regmap_update_bits(drv->reg_pmu, offset, mask, on ? 0 : mask);
>  }
>
> -static void exynos5250_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on)
> +static int exynos5250_power_on(struct samsung_usb2_phy_instance *inst)

void ? we really don't have much to return in this function.

>  {
>         struct samsung_usb2_phy_driver *drv = inst->drv;
>         u32 ctrl0;
>         u32 otg;
>         u32 ehci;
>         u32 ohci;
> +       u32 hsic;
>
>         switch (inst->cfg->id) {
>         case EXYNOS5250_DEVICE:
> @@ -234,6 +241,8 @@ static void exynos5250_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on)
>
>                 break;
>         case EXYNOS5250_HOST:
> +       case EXYNOS5250_HSIC0:
> +       case EXYNOS5250_HSIC1:
>                 /* Host registers configuration */
>                 ctrl0 = readl(drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0);
>                 /* The clock */
> @@ -279,6 +288,18 @@ static void exynos5250_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on)
>                         EXYNOS_5250_USBOTGSYS_LINK_SW_RST_UOTG |
>                         EXYNOS_5250_USBOTGSYS_PHYLINK_SW_RESET);
>
> +               /* HSIC phy configuration */
> +               hsic = (EXYNOS_5250_HOSTPHYCTRLX_REFCLKDIV_12 |
> +                               EXYNOS_5250_HOSTPHYCTRLX_REFCLKSEL_DEFAULT |
> +                               EXYNOS_5250_HOSTPHYCTRLX_PHYSWRST);
> +               writel(hsic, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL1);
> +               writel(hsic, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL2);
> +               udelay(10);
> +               hsic &= ~EXYNOS_5250_HOSTPHYCTRLX_PHYSWRST;
> +               writel(hsic, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL1);
> +               writel(hsic, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL2);
> +               udelay(80);
> +
>                 /* Enable EHCI DMA burst */
>                 ehci = readl(drv->reg_phy + EXYNOS_5250_HOSTEHCICTRL);
>                 ehci |= EXYNOS_5250_HOSTEHCICTRL_ENAINCRXALIGN |
> @@ -295,12 +316,7 @@ static void exynos5250_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on)
>
>                 break;
>         }
> -}
> -
> -static int exynos5250_power_on(struct samsung_usb2_phy_instance *inst)
> -{
>         inst->enabled = 1;
> -       exynos5250_phy_pwr(inst, 1);
>         exynos5250_isol(inst, 0);
>
>         return 0;
> @@ -308,9 +324,43 @@ static int exynos5250_power_on(struct samsung_usb2_phy_instance *inst)
>
>  static int exynos5250_power_off(struct samsung_usb2_phy_instance *inst)

ditto

>  {
> +       struct samsung_usb2_phy_driver *drv = inst->drv;
> +       u32 ctrl0;
> +       u32 otg;
> +       u32 hsic;
> +
>         inst->enabled = 0;
>         exynos5250_isol(inst, 1);
> -       exynos5250_phy_pwr(inst, 0);
> +
> +       switch (inst->cfg->id) {
> +       case EXYNOS5250_DEVICE:
> +               otg = readl(drv->reg_phy + EXYNOS_5250_USBOTGSYS);
> +               otg |= (EXYNOS_5250_USBOTGSYS_FORCE_SUSPEND |
> +                       EXYNOS_5250_USBOTGSYS_SIDDQ_UOTG |
> +                       EXYNOS_5250_USBOTGSYS_FORCE_SLEEP);
> +               writel(otg, drv->reg_phy + EXYNOS_5250_USBOTGSYS);
> +               break;
> +       case EXYNOS5250_HOST:
> +               ctrl0 = readl(drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0);
> +               ctrl0 |= (EXYNOS_5250_HOSTPHYCTRL0_SIDDQ |
> +                               EXYNOS_5250_HOSTPHYCTRL0_FORCESUSPEND |
> +                               EXYNOS_5250_HOSTPHYCTRL0_FORCESLEEP |
> +                               EXYNOS_5250_HOSTPHYCTRL0_PHYSWRST |
> +                               EXYNOS_5250_HOSTPHYCTRL0_PHYSWRSTALL);
> +               writel(ctrl0, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0);
> +               break;
> +       case EXYNOS5250_HSIC0:
> +       case EXYNOS5250_HSIC1:
> +               hsic = (EXYNOS_5250_HOSTPHYCTRLX_REFCLKDIV_12 |
> +                               EXYNOS_5250_HOSTPHYCTRLX_REFCLKSEL_DEFAULT |
> +                               EXYNOS_5250_HOSTPHYCTRLX_SIDDQ |
> +                               EXYNOS_5250_HOSTPHYCTRLX_FORCESLEEP |
> +                               EXYNOS_5250_HOSTPHYCTRLX_FORCESUSPEND
> +                               );
> +               writel(hsic, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL1);
> +               writel(hsic, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL2);
> +               break;
> +       }
>
>         return 0;
>  }
> --
> 1.7.9.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



-- 
Best Regards
Vivek Gautam
Samsung R&D Institute, Bangalore
India

RE: [PATCH v5 4/9] usb: ehci-s5p: Change to use phy provided by the generic phy framework

[Kamil Debski]

Hi Vivek,

> From: Vivek Gautam [mailto:gautamvivek1987@gmail.com]
> Sent: Thursday, December 26, 2013 11:14 AM
> 
> Hi Kamil,
> 
> 
> On Fri, Dec 20, 2013 at 6:54 PM, Kamil Debski <k.debski@samsung.com>
> wrote:
> > Change the phy provider used from the old one using the USB phy
> > framework to a new one using the Generic phy framework.
> >
> > Signed-off-by: Kamil Debski <k.debski@samsung.com>
> > Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> 
> Commit title:
> s/ehci-s5p/ehci-exynos

Thank you for spotting this.

> 
> > ---
> >  Documentation/devicetree/bindings/usb/usb-ehci.txt |   35 +++++++
> >  drivers/usb/host/ehci-exynos.c                     |   97
> +++++++++++++-------
> >  2 files changed, 98 insertions(+), 34 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/usb/usb-ehci.txt
> > b/Documentation/devicetree/bindings/usb/usb-ehci.txt
> > index fa18612..413f7cd 100644
> > --- a/Documentation/devicetree/bindings/usb/usb-ehci.txt
> > +++ b/Documentation/devicetree/bindings/usb/usb-ehci.txt
> > @@ -14,6 +14,10 @@ If controller implementation operates with big
> > endian descriptors,  If both big endian registers and descriptors are
> > used by the controller  implementation, "big-endian" property can be
> > specified instead of having  both "big-endian-regs" and "big-endian-
> desc".
> > +  - port: if in the SoC there are EHCI phys, they should be listed
> here.
> > +One phy per port. Each port should have its reg entry with a
> > +consecutive number. Also it should contain phys and phy-names
> entries
> > +specifying the phy used by the port.
> >
> >  Example (Sequoia 440EPx):
> >      ehci@e0000300 {
> > @@ -23,3 +27,34 @@ Example (Sequoia 440EPx):
> >            reg = <0 e0000300 90 0 e0000390 70>;
> >            big-endian;
> >     };
> > +
> > +Example (Exynos 4212):
> > +    ehci@12580000 {
> > +        compatible = "samsung,exynos4210-ehci";
> > +        reg = <0x12580000 0x20000>;
> > +        interrupts = <0 70 0>;
> > +        clocks = <&clock 304>, <&clock 305>;
> > +        clock-names = "usbhost", "otg";
> > +        status = "disabled";
> > +        #address-cells = <1>;
> > +        #size-cells = <0>;
> > +        port@0 {
> > +            reg = <0>;
> > +            phys = <&usb2phy 1>;
> > +            phy-names = "host";
> > +            status = "disabled";
> > +        };
> > +        port@1 {
> > +            reg = <1>;
> > +            phys = <&usb2phy 2>;
> > +            phy-names = "hsic0";
> > +            status = "disabled";
> > +        };
> > +        port@2 {
> > +            reg = <2>;
> > +            phys = <&usb2phy 3>;
> > +            phy-names = "hsic1";
> > +            status = "disabled";
> > +        };
> > +    };
> 
> Should we place above documentation in
> "Documentation/devicetree/bindings/usb/exynos-usb.txt" ?
> or is it something that i am missing. 

Indeed, this should go to exynos-usb.txt instead of usb-ehci.txt.
Thanks!

> > +
> > diff --git a/drivers/usb/host/ehci-exynos.c
> > b/drivers/usb/host/ehci-exynos.c index d1d8c47..7c35501 100644
> > --- a/drivers/usb/host/ehci-exynos.c
> > +++ b/drivers/usb/host/ehci-exynos.c
> > @@ -19,12 +19,12 @@
> >  #include <linux/module.h>
> >  #include <linux/of.h>
> >  #include <linux/of_gpio.h>
> > +#include <linux/phy/phy.h>
> >  #include <linux/platform_device.h>
> >  #include <linux/usb/phy.h>
> >  #include <linux/usb/samsung_usb_phy.h>  #include <linux/usb.h>
> > #include <linux/usb/hcd.h> -#include <linux/usb/otg.h>
> >
> >  #include "ehci.h"
> >
> > @@ -42,10 +42,10 @@
> >  static const char hcd_name[] = "ehci-exynos";  static struct
> > hc_driver __read_mostly exynos_ehci_hc_driver;
> >
> > +#define PHY_NUMBER 3
> >  struct exynos_ehci_hcd {
> >         struct clk *clk;
> > -       struct usb_phy *phy;
> > -       struct usb_otg *otg;
> > +       struct phy *phy[PHY_NUMBER];
> >  };
> >
> >  #define to_exynos_ehci(hcd) (struct exynos_ehci_hcd
> > *)(hcd_to_ehci(hcd)->priv) @@ -69,13 +69,43 @@ static void
> exynos_setup_vbus_gpio(struct platform_device *pdev)
> >                 dev_err(dev, "can't request ehci vbus gpio %d",
> gpio);
> > }
> >
> > +static int exynos_phys_on(struct phy *p[]) {
> > +       int i;
> > +       int ret = 0;
> > +
> > +       for (i = 0; ret == 0 && i < PHY_NUMBER; i++)
> > +               if (p[i])
> > +                       ret = phy_power_on(p[i]);
> > +       if (ret)
> > +               for (i--; i > 0; i--)
> > +                       if (p[i])
> > +                               phy_power_off(p[i]);
> 
> So we are turning off, say, port0 phy in case port1 phy power_on fails;
> can't we still leave a usb2.0 phy(a normal host phy) 'on' in case the
> HSIC phy fails ?

Currently all phys are can be either switched on or off. So if powering on
one phy fails (and exynos_phy_on returns an error code), I would expect
that no phy is switched on. I think that doing otherwise could leave
the phys in strange state - some phys are on, some are off and the power_on
call returned an error.

> > +
> > +       return ret;
> > +}
> > +
> > +static int exynos_phys_off(struct phy *p[]) {
> > +       int i;
> > +       int ret = 0;
> > +
> > +       for (i = 0; ret == 0 && i < PHY_NUMBER; i++)
> > +               if (p[i])
> > +                       ret = phy_power_off(p[i]);
> > +
> > +       return ret;
> > +}
> > +
> >  static int exynos_ehci_probe(struct platform_device *pdev)  {
> >         struct exynos_ehci_hcd *exynos_ehci;
> >         struct usb_hcd *hcd;
> >         struct ehci_hcd *ehci;
> >         struct resource *res;
> > -       struct usb_phy *phy;
> > +       struct phy *phy;
> > +       struct device_node *child;
> > +       int phy_number;
> >         int irq;
> >         int err;
> >
> > @@ -102,14 +132,26 @@ static int exynos_ehci_probe(struct
> platform_device *pdev)
> >                                         "samsung,exynos5440-ehci"))
> >                 goto skip_phy;
> >
> > -       phy = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2);
> > -       if (IS_ERR(phy)) {
> > -               usb_put_hcd(hcd);
> > -               dev_warn(&pdev->dev, "no platform data or transceiver
> defined\n");
> > -               return -EPROBE_DEFER;
> > -       } else {
> > -               exynos_ehci->phy = phy;
> > -               exynos_ehci->otg = phy->otg;
> > +       for_each_available_child_of_node(pdev->dev.of_node, child) {
> > +               err = of_property_read_u32(child, "reg",
> &phy_number);
> > +               if (err) {
> > +                       dev_err(&pdev->dev, "Failed to parse device
> tree\n");
> > +                       of_node_put(child);
> > +                       return err;
> > +               }
> > +               if (phy_number >= PHY_NUMBER) {
> > +                       dev_err(&pdev->dev, "Failed to parse device
> tree - number out of range\n");
> > +                       of_node_put(child);
> > +                       return -EINVAL;
> > +               }
> > +               phy = devm_of_phy_get(&pdev->dev, child, 0);
> > +               of_node_put(child);
> > +               if (IS_ERR(phy)) {
> > +                       dev_err(&pdev->dev, "Failed to get phy number
> %d",
> > +
> phy_number);
> > +                       return PTR_ERR(phy);
> > +               }
> > +               exynos_ehci->phy[phy_number] = phy;
> >         }
> >
> >  skip_phy:
> > @@ -149,11 +191,11 @@ skip_phy:
> >                 goto fail_io;
> >         }
> >
> > -       if (exynos_ehci->otg)
> > -               exynos_ehci->otg->set_host(exynos_ehci->otg, &hcd-
> >self);
> > -
> > -       if (exynos_ehci->phy)
> > -               usb_phy_init(exynos_ehci->phy);
> > +       err = exynos_phys_on(exynos_ehci->phy);
> > +       if (err) {
> > +               dev_err(&pdev->dev, "Failed to enabled phys\n");
> > +               goto fail_io;
> > +       }
> >
> >         ehci = hcd_to_ehci(hcd);
> >         ehci->caps = hcd->regs;
> > @@ -173,8 +215,7 @@ skip_phy:
> >         return 0;
> >
> >  fail_add_hcd:
> > -       if (exynos_ehci->phy)
> > -               usb_phy_shutdown(exynos_ehci->phy);
> > +       exynos_phys_off(exynos_ehci->phy);
> >  fail_io:
> >         clk_disable_unprepare(exynos_ehci->clk);
> >  fail_clk:
> > @@ -189,11 +230,7 @@ static int exynos_ehci_remove(struct
> > platform_device *pdev)
> >
> >         usb_remove_hcd(hcd);
> >
> > -       if (exynos_ehci->otg)
> > -               exynos_ehci->otg->set_host(exynos_ehci->otg, &hcd-
> >self);
> > -
> > -       if (exynos_ehci->phy)
> > -               usb_phy_shutdown(exynos_ehci->phy);
> > +       exynos_phys_off(exynos_ehci->phy);
> >
> >         clk_disable_unprepare(exynos_ehci->clk);
> >
> > @@ -213,11 +250,7 @@ static int exynos_ehci_suspend(struct device
> > *dev)
> >
> >         rc = ehci_suspend(hcd, do_wakeup);
> >
> > -       if (exynos_ehci->otg)
> > -               exynos_ehci->otg->set_host(exynos_ehci->otg, &hcd-
> >self);
> > -
> > -       if (exynos_ehci->phy)
> > -               usb_phy_shutdown(exynos_ehci->phy);
> > +       exynos_phys_off(exynos_ehci->phy);
> >
> >         clk_disable_unprepare(exynos_ehci->clk);
> >
> > @@ -231,11 +264,7 @@ static int exynos_ehci_resume(struct device
> *dev)
> >
> >         clk_prepare_enable(exynos_ehci->clk);
> >
> > -       if (exynos_ehci->otg)
> > -               exynos_ehci->otg->set_host(exynos_ehci->otg, &hcd-
> >self);
> > -
> > -       if (exynos_ehci->phy)
> > -               usb_phy_init(exynos_ehci->phy);
> > +       exynos_phys_on(exynos_ehci->phy);
> >
> >         /* DMA burst Enable */
> >         writel(EHCI_INSNREG00_ENABLE_DMA_BURST,
> > EHCI_INSNREG00(hcd->regs));
> > --
> 
> Rest all looks good. :-)
> I tested this patch along with other patches in the series on smdk5250.

Thank you :)

> Tested-by: Vivek Gautam <gautam.vivek@samsung.com>
> 

Best wishes,
-- 
Kamil Debski
Samsung R&D Institute Poland

RE: [PATCH v2 9/9] dts: Add usb2phy to Exynos 5250

[Kamil Debski]

Hi,

> From: Vivek Gautam [mailto:gautamvivek1987@gmail.com]
> Sent: Thursday, December 26, 2013 11:32 AM
> 
> Hi Kamil,
> 
> 
> On Fri, Dec 20, 2013 at 6:54 PM, Kamil Debski <k.debski@samsung.com>
> wrote:
> > Add support to PHY of USB2 of the Exynos 5250 SoC.
> >
> > Signed-off-by: Kamil Debski <k.debski@samsung.com>
> > ---
> >  arch/arm/boot/dts/exynos5250.dtsi |   33 ++++++++++++-------
> >  drivers/phy/phy-exynos5250-usb2.c |   64
> +++++++++++++++++++++++++++++++++----
> >  2 files changed, 78 insertions(+), 19 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/exynos5250.dtsi
> > b/arch/arm/boot/dts/exynos5250.dtsi
> > index 2f264ad..922e0ed 100644
> > --- a/arch/arm/boot/dts/exynos5250.dtsi
> > +++ b/arch/arm/boot/dts/exynos5250.dtsi
> > @@ -163,6 +163,11 @@
> >                 interrupts = <0 47 0>;
> >         };
> >
> > +       sys_syscon: syscon@10040000 {
> > +               compatible = "samsung,exynos5250-sys", "syscon";
> > +               reg = <0x10050000 0x5000>;
> > +       };
> > +
> >         pmu_syscon: syscon@10040000 {
> >                 compatible = "samsung,exynos5250-pmu", "syscon";
> >                 reg = <0x10040000 0x5000>; @@ -505,6 +510,14 @@
> >
> >                 clocks = <&clock 285>;
> >                 clock-names = "usbhost";
> > +               #address-cells = <1>;
> > +               #size-cells = <0>;
> > +               port@0 {
> > +                       reg = <0>;
> > +                       phys = <&usb2_phy 1>;
> > +                       phy-names = "host";
> > +                       status = "ok";
> > +               };
> >         };
> >
> >         usb@12120000 {
> > @@ -516,19 +529,15 @@
> >                 clock-names = "usbhost";
> >         };
> >
> > -       usb2_phy: usbphy@12130000 {
> > -               compatible = "samsung,exynos5250-usb2phy";
> > +       usb2_phy: phy@12130000 {
> > +               compatible = "samsung,exynos5250-usb2-phy";
> >                 reg = <0x12130000 0x100>;
> > -               clocks = <&clock 1>, <&clock 285>;
> > -               clock-names = "ext_xtal", "usbhost";
> > -               #address-cells = <1>;
> > -               #size-cells = <1>;
> > -               ranges;
> > -
> > -               usbphy-sys {
> > -                       reg = <0x10040704 0x8>,
> > -                             <0x10050230 0x4>;
> > -               };
> > +               clocks = <&clock 285>, <&clock 1>, <&clock 1>,
> <&clock 1>,
> > +
> <&clock 1>;
> > +               clock-names = "phy", "device", "host", "hsic0",
> "hsic1";
> > +               #phy-cells = <1>;
> > +               samsung,sysreg-phandle = <&sys_syscon>;
> > +               samsung,pmureg-phandle = <&pmu_syscon>;
> >         };
> >
> >         amba {
> > diff --git a/drivers/phy/phy-exynos5250-usb2.c
> > b/drivers/phy/phy-exynos5250-usb2.c
> > index b9b3b98..337bf82 100644
> > --- a/drivers/phy/phy-exynos5250-usb2.c
> > +++ b/drivers/phy/phy-exynos5250-usb2.c
> 
> Separate patches for dt and driver ?
> I think you wanted to move these changes to :
> [PATCH v5 7/9] phy: Add Exynos 5250 support to the Exynos USB 2.0 PHY
> driver

Good point. I am planning to reorganise this patchset to prevent breaking
git bisect. I wanted to wait for more comments to this version, so I could
address any issues that may be reported.

> 
> > @@ -58,7 +58,13 @@
> >  #define EXYNOS_5250_HOSTPHYCTRL2                       0x20
> 
> Shouldn't we leave the naming as EXYNOS_5250_HSICPHYCTRL2 instead of
> EXYNOS_5250_HOSTPHYCTRL2 ? That will go in sync with the user-manual
> too.
> and similar for EXYNOS_5250_HOSTPHYCTRL1 and below bit definitions too
> ?

Thank you for pointing this out.

> >
> >  #define EXYNOS_5250_HOSTPHYCTRLX_REFCLKSEL_MASK                (0x3
> << 23)
> > +#define EXYNOS_5250_HOSTPHYCTRLX_REFCLKSEL_DEFAULT     (0x2 << 23)
> >  #define EXYNOS_5250_HOSTPHYCTRLX_REFCLKDIV_MASK                (0x7f
> << 16)
> > +#define EXYNOS_5250_HOSTPHYCTRLX_REFCLKDIV_12          (0x24 << 16)
> > +#define EXYNOS_5250_HOSTPHYCTRLX_REFCLKDIV_15          (0x1c << 16)
> > +#define EXYNOS_5250_HOSTPHYCTRLX_REFCLKDIV_16          (0x1a << 16)
> > +#define EXYNOS_5250_HOSTPHYCTRLX_REFCLKDIV_19_2                (0x15
> << 16)
> > +#define EXYNOS_5250_HOSTPHYCTRLX_REFCLKDIV_20          (0x14 << 16)
> >  #define EXYNOS_5250_HOSTPHYCTRLX_SIDDQ                 BIT(6)
> >  #define EXYNOS_5250_HOSTPHYCTRLX_FORCESLEEP            BIT(5)
> >  #define EXYNOS_5250_HOSTPHYCTRLX_FORCESUSPEND          BIT(4)
> > @@ -191,13 +197,14 @@ static void exynos5250_isol(struct
> samsung_usb2_phy_instance *inst, bool on)
> >         regmap_update_bits(drv->reg_pmu, offset, mask, on ? 0 :
> mask);
> > }
> >
> > -static void exynos5250_phy_pwr(struct samsung_usb2_phy_instance
> > *inst, bool on)
> > +static int exynos5250_power_on(struct samsung_usb2_phy_instance
> > +*inst)
> 
> void ? we really don't have much to return in this function.

Initially the idea was to enable the return of an error code. However,
I see that for all currently supported SoCs the ops always returns 0.
So I will consider switching to void.

> 
> >  {
> >         struct samsung_usb2_phy_driver *drv = inst->drv;
> >         u32 ctrl0;
> >         u32 otg;
> >         u32 ehci;
> >         u32 ohci;
> > +       u32 hsic;
> >
> >         switch (inst->cfg->id) {
> >         case EXYNOS5250_DEVICE:
> > @@ -234,6 +241,8 @@ static void exynos5250_phy_pwr(struct
> > samsung_usb2_phy_instance *inst, bool on)
> >
> >                 break;
> >         case EXYNOS5250_HOST:
> > +       case EXYNOS5250_HSIC0:
> > +       case EXYNOS5250_HSIC1:
> >                 /* Host registers configuration */
> >                 ctrl0 = readl(drv->reg_phy +
> EXYNOS_5250_HOSTPHYCTRL0);
> >                 /* The clock */
> > @@ -279,6 +288,18 @@ static void exynos5250_phy_pwr(struct
> samsung_usb2_phy_instance *inst, bool on)
> >                         EXYNOS_5250_USBOTGSYS_LINK_SW_RST_UOTG |
> >                         EXYNOS_5250_USBOTGSYS_PHYLINK_SW_RESET);
> >
> > +               /* HSIC phy configuration */
> > +               hsic = (EXYNOS_5250_HOSTPHYCTRLX_REFCLKDIV_12 |
> > +
> EXYNOS_5250_HOSTPHYCTRLX_REFCLKSEL_DEFAULT |
> > +                               EXYNOS_5250_HOSTPHYCTRLX_PHYSWRST);
> > +               writel(hsic, drv->reg_phy +
> EXYNOS_5250_HOSTPHYCTRL1);
> > +               writel(hsic, drv->reg_phy +
> EXYNOS_5250_HOSTPHYCTRL2);
> > +               udelay(10);
> > +               hsic &= ~EXYNOS_5250_HOSTPHYCTRLX_PHYSWRST;
> > +               writel(hsic, drv->reg_phy +
> EXYNOS_5250_HOSTPHYCTRL1);
> > +               writel(hsic, drv->reg_phy +
> EXYNOS_5250_HOSTPHYCTRL2);
> > +               udelay(80);
> > +
> >                 /* Enable EHCI DMA burst */
> >                 ehci = readl(drv->reg_phy +
> EXYNOS_5250_HOSTEHCICTRL);
> >                 ehci |= EXYNOS_5250_HOSTEHCICTRL_ENAINCRXALIGN | @@
> > -295,12 +316,7 @@ static void exynos5250_phy_pwr(struct
> > samsung_usb2_phy_instance *inst, bool on)
> >
> >                 break;
> >         }
> > -}
> > -
> > -static int exynos5250_power_on(struct samsung_usb2_phy_instance
> > *inst) -{
> >         inst->enabled = 1;
> > -       exynos5250_phy_pwr(inst, 1);
> >         exynos5250_isol(inst, 0);
> >
> >         return 0;
> > @@ -308,9 +324,43 @@ static int exynos5250_power_on(struct
> > samsung_usb2_phy_instance *inst)
> >
> >  static int exynos5250_power_off(struct samsung_usb2_phy_instance
> > *inst)
> 
> ditto
> 
> >  {
> > +       struct samsung_usb2_phy_driver *drv = inst->drv;
> > +       u32 ctrl0;
> > +       u32 otg;
> > +       u32 hsic;
> > +
> >         inst->enabled = 0;
> >         exynos5250_isol(inst, 1);
> > -       exynos5250_phy_pwr(inst, 0);
> > +
> > +       switch (inst->cfg->id) {
> > +       case EXYNOS5250_DEVICE:
> > +               otg = readl(drv->reg_phy + EXYNOS_5250_USBOTGSYS);
> > +               otg |= (EXYNOS_5250_USBOTGSYS_FORCE_SUSPEND |
> > +                       EXYNOS_5250_USBOTGSYS_SIDDQ_UOTG |
> > +                       EXYNOS_5250_USBOTGSYS_FORCE_SLEEP);
> > +               writel(otg, drv->reg_phy + EXYNOS_5250_USBOTGSYS);
> > +               break;
> > +       case EXYNOS5250_HOST:
> > +               ctrl0 = readl(drv->reg_phy +
> EXYNOS_5250_HOSTPHYCTRL0);
> > +               ctrl0 |= (EXYNOS_5250_HOSTPHYCTRL0_SIDDQ |
> > +                               EXYNOS_5250_HOSTPHYCTRL0_FORCESUSPEND
> |
> > +                               EXYNOS_5250_HOSTPHYCTRL0_FORCESLEEP |
> > +                               EXYNOS_5250_HOSTPHYCTRL0_PHYSWRST |
> > +
> EXYNOS_5250_HOSTPHYCTRL0_PHYSWRSTALL);
> > +               writel(ctrl0, drv->reg_phy +
> EXYNOS_5250_HOSTPHYCTRL0);
> > +               break;
> > +       case EXYNOS5250_HSIC0:
> > +       case EXYNOS5250_HSIC1:
> > +               hsic = (EXYNOS_5250_HOSTPHYCTRLX_REFCLKDIV_12 |
> > +
> EXYNOS_5250_HOSTPHYCTRLX_REFCLKSEL_DEFAULT |
> > +                               EXYNOS_5250_HOSTPHYCTRLX_SIDDQ |
> > +                               EXYNOS_5250_HOSTPHYCTRLX_FORCESLEEP |
> > +                               EXYNOS_5250_HOSTPHYCTRLX_FORCESUSPEND
> > +                               );
> > +               writel(hsic, drv->reg_phy +
> EXYNOS_5250_HOSTPHYCTRL1);
> > +               writel(hsic, drv->reg_phy +
> EXYNOS_5250_HOSTPHYCTRL2);
> > +               break;
> > +       }
> >
> >         return 0;
> >  }
> > --
> > 1.7.9.5
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe
> > linux-samsung-soc" in the body of a message to
> > majordomo@vger.kernel.org More majordomo info at
> > http://vger.kernel.org/majordomo-info.html
> 
> 
> 
> --
> Best Regards
> Vivek Gautam
> Samsung R&D Institute, Bangalore
> India

Best wishes,
-- 
Kamil Debski
Samsung R&D Institute Poland

RE: [PATCH v5 0/9] phy: Add new Exynos USB 2.0 PHY driver

[Kamil Debski]

Hi Kishon,

I wanted to ask about your comments to this patchset. As I mentioned 
there are two alternative version where the Exynos 4210 and 4212
support is merged in one file.

I would be grateful if you had some time to look at the patchset
and share your comments.

Best wishes and happy new year!
-- 
Kamil Debski
Samsung R&D Institute Poland


> From: Kamil Debski [mailto:k.debski@samsung.com]
> Sent: Friday, December 20, 2013 2:24 PM
> 
> Hi,
> 
> This is the fifth version of the patchset. It adds a new Exynos USB 2.0
> PHY driver. The driver uses the Generic PHY Framework.
> 
> I would like to thank everyone who contributed with comments and took
> the time to read through the patches in the previous versions of this
> patchset.
> We had a lengthy discussion with Kishon about how the driver should
> look like.
> This patchset contains the updated version of my original idea, where
> support for Exynos 4210 and 4212 is done in separate files. Kishon's
> idea is to join these two into a single file. I have prepared two
> alternative version which I will send soon after this patchset.
> 
> Just like the fourth version this patch depends on:
> [PATCH V11 1/3] ARM: dts: Add pmu sysreg node to exynos5250 and
> exynos5420 dtsi files [1].
> 
> Best wishes,
> Kamil Debski
> 
> [1] - http://www.spinics.net/lists/linux-samsung-soc/msg24528.html
> 
> ----------------
> Changes from v4:
> 1) phy: core: Add an exported of_phy_get function
> - the new exported function of_phy_get was changed to take the phy's
> name as a
>   parameter instead of the index
> 2) phy: core: Add devm_of_phy_get to phy-core
> - fixes made in the comments to devm_of_phy_get
> 3) phy: Add new Exynos USB PHY driver
> - move the documentation from a new to an existing file - samsung-
> phy.txt
> - fix typos and uppercase hex addresses
> - add more explanations to Kconfig (checkpatch still complains, but I
> find it
>   hard to think what else could I add)
> - add selects MFD_SYSCON as the driver needs it (Thank you, Tobias!)
> - cleanup included headers in both *.c and .h files
> - use BIT(x) macro instead of (1 << x)
> - replaced HOST and DEV with PHY0 and PHY1 in phy-exynos4212-usb2.c,
> the
>   registers are described as PHYx in the documentation hence the
> decision to
>   leave the PHYx naming
> - fixed typo in exynos4210_rate_to_clk reg -> *reg
> - change hax_mode_switch and enabled type to bool
> 4) usb: ehci-s5p: Change to use phy provided by the generic phy
> framework
> - Put the issue of phy->otg in order - since the new phy driver does
> not provide
>   this field. With the new driver the switch between host and device is
> done in
>   power_on of the respective host and device phys.
> 5) usb: s3c-hsotg: Use the new Exynos USB phy driver with the generic
> phy
>    framework
> - fixed the example in the documentation
> 6) phy: Add support for S5PV210 to the Exynos USB PHY driver
> - include files cleanup
> - use BIT(x) macro instead of (1 << x)
> 7) phy: Add Exynos 5250 support to the Exynos USB 2.0 PHY driver
> - include files cleanup
> - use BIT(x) macro instead of (1 << x)
> 8) dts: Add usb2phy to Exynos 4
> - no changes
> 9) dts: Add usb2phy to Exynos 5250
> - no changes
> 
> ----------------
> Changes from v3:
> - using PMU and system registers indirectly via syscon
> - change labelling
> - change Kconfig name
> - fixed typos/stray whitespace
> - move of_phy_provider_register() to the end of probe
> - add a regular error return code to the rate_to_clk functions
> - cleanup code and remove unused code
> - change struct names to avoid collisions
> - add mechanism to support multiple phys by the ehci driver
> 
> ----------------
> Changes from v2:
> - rebase all patches to the usb-next branch
> - fixes in the documentation file
>   - remove wrong entries in the phy node (ranges, and #address- &
> #size-cells)
>   - add clocks and clock-names as required properites
>   - rephrase a few sentences
> - fixes in the ehci-exynos.c file
>   - move phy_name variable next to phy in exynos_ehci_hcd
>   - remove otg from exynos_ehci_hcd as it was no longer used
>   - move devm_phy_get after the Exynos5440 skip_phy check
> - fixes in the s3c-hsotg.c file
>   - cosmetic fixes (remove empty line that was wrongfully added)
> - fixes in the main driver
>   - remove cpu_type in favour for a boolean flag matched with the
> compatible
>     value
>   - rename files, structures, variables and Kconfig entires - change
> from simple
>     "uphy" to "usb2_phy"
>   - fix multiline comments style
>   - simplify #ifdefs in of_device_id
>   - fix Kconfig description
>   - change dev_info to dev_dbg where reasonable
>   - cosmetic changes (remove wrongful blank lines)
>   - remove unnecessary reference counting
> 
> ----------------
> Changes from v1:
> - the changes include minor fixes of the hardware initialization of the
> PHY
>   module
> - some other minor fixes were introduced
> 
> ----------------------
> Original cover letter:
> 
> Hi,
> 
> This patch adds a new drive for USB PHYs for Samsung SoCs. The driver
> is using the Generic PHY Framework created by Kishon Vijay Abrahan I.
> It can be found here https://lkml.org/lkml/2013/8/21/29. This patch
> adds support to Exynos4 family of SoCs. Support for Exynos3 and Exynos5
> is planned to be added in the near future.
> 
> I welcome your comments.
> 
> ----------------------
> 
> [1] https://lkml.org/lkml/2013/8/21/29
> 
> Kamil Debski (8):
>   phy: core: Add an exported of_phy_get function
>   phy: core: Add devm_of_phy_get to phy-core
>   phy: Add new Exynos USB PHY driver
>   usb: ehci-s5p: Change to use phy provided by the generic phy
>     framework
>   usb: s3c-hsotg: Use the new Exynos USB phy driver with the generic
>     phy framework
>   phy: Add Exynos 5250 support to the Exynos USB 2.0 PHY driver
>   dts: Add usb2phy to Exynos 4
>   dts: Add usb2phy to Exynos 5250
> 
> Mateusz Krawczuk (1):
>   phy: Add support for S5PV210 to the Exynos USB PHY driver
> 
>  .../devicetree/bindings/arm/samsung/pmu.txt        |    2 +
>  .../devicetree/bindings/phy/samsung-phy.txt        |   57 +++
>  .../devicetree/bindings/usb/samsung-hsotg.txt      |    4 +
>  Documentation/devicetree/bindings/usb/usb-ehci.txt |   35 ++
>  arch/arm/boot/dts/exynos4.dtsi                     |   31 ++
>  arch/arm/boot/dts/exynos4210.dtsi                  |   17 +
>  arch/arm/boot/dts/exynos4x12.dtsi                  |   17 +
>  arch/arm/boot/dts/exynos5250.dtsi                  |   33 +-
>  drivers/phy/Kconfig                                |   50 +++
>  drivers/phy/Makefile                               |    5 +
>  drivers/phy/phy-core.c                             |   76 +++-
>  drivers/phy/phy-exynos4210-usb2.c                  |  257
> +++++++++++++
>  drivers/phy/phy-exynos4212-usb2.c                  |  306
> +++++++++++++++
>  drivers/phy/phy-exynos5250-usb2.c                  |  406
> ++++++++++++++++++++
>  drivers/phy/phy-s5pv210-usb2.c                     |  199 ++++++++++
>  drivers/phy/phy-samsung-usb2.c                     |  238 ++++++++++++
>  drivers/phy/phy-samsung-usb2.h                     |   69 ++++
>  drivers/usb/gadget/s3c-hsotg.c                     |   11 +-
>  drivers/usb/host/ehci-exynos.c                     |   97 +++--
>  include/linux/phy/phy.h                            |    3 +
>  20 files changed, 1853 insertions(+), 60 deletions(-)  create mode
> 100644 drivers/phy/phy-exynos4210-usb2.c  create mode 100644
> drivers/phy/phy-exynos4212-usb2.c  create mode 100644 drivers/phy/phy-
> exynos5250-usb2.c  create mode 100644 drivers/phy/phy-s5pv210-usb2.c
> create mode 100644 drivers/phy/phy-samsung-usb2.c  create mode 100644
> drivers/phy/phy-samsung-usb2.h
> 
> --
> 1.7.9.5

Re: [PATCH v5 0/9] phy: Add new Exynos USB 2.0 PHY driver

[Kishon Vijay Abraham I]

Hi Kamil,

On Thursday 02 January 2014 09:50 PM, Kamil Debski wrote:
> Hi Kishon,
>
> I wanted to ask about your comments to this patchset. As I mentioned
> there are two alternative version where the Exynos 4210 and 4212
> support is merged in one file.
>
> I would be grateful if you had some time to look at the patchset
> and share your comments.
>
> Best wishes and happy new year!

Thanks for doing that :-). I'll review your patches once I'm back to 
work on Monday.

Wish you also a happy new year :-)

Cheers
Kishon
>

[PATCH v6 6/9] phy: Add support for S5PV210 to the Exynos USB 2.0 PHY driver

[Tomasz Figa]

From: Mateusz Krawczuk <mat.krawczuk@gmail.com>

Add support for the Samsung's S5PV210 SoC to the Exynos USB 2.0 PHY driver.

Signed-off-by: Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
[k.debski@samsung.com: cleanup and commit description]
[k.debski@samsung.com: make changes accordingly to the mailing list
comments]
Signed-off-by: Kamil Debski <k.debski@samsung.com>
[tomasz.figa@gmail.com: fix compilation issues and UPHYCLK register
setup]
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
---
 .../devicetree/bindings/phy/samsung-phy.txt        |   1 +
 drivers/phy/Kconfig                                |  10 ++
 drivers/phy/Makefile                               |   1 +
 drivers/phy/phy-s5pv210-usb2.c                     | 188 +++++++++++++++++++++
 drivers/phy/phy-samsung-usb2.c                     |   6 +
 drivers/phy/phy-samsung-usb2.h                     |   1 +
 6 files changed, 207 insertions(+)
 create mode 100644 drivers/phy/phy-s5pv210-usb2.c

Changes since v5:
 - Fixed compilation issues.
 - Fixed incorrect value written to UPHYCLK register.

diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index 39d52cc..eb40460 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -26,6 +26,7 @@ Samsung S5P/EXYNOS SoC series USB PHY
 
 Required properties:
 - compatible : should be one of the listed compatibles:
+	- "samsung,s5pv210-usb2-phy"
 	- "samsung,exynos4210-usb2-phy"
 	- "samsung,exynos4212-usb2-phy"
 - reg : a list of registers used by phy driver
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 55b49d1..8298d7c 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -61,6 +61,16 @@ config PHY_SAMSUNG_USB2
 	  particular SoCs has to be enabled in addition to this driver. Number
 	  and type of supported phys depends on the SoC.
 
+config PHY_S5PV210_USB2
+	bool "Support for S5PV210"
+	depends on PHY_SAMSUNG_USB2
+	depends on ARCH_S5PV210
+	help
+	  Enable USB PHY support for S5PV210. This option requires that Samsung
+	  USB 2.0 PHY driver is enabled and means that support for this
+	  particular SoC is compiled in the driver. In case of S5PV210 two phys
+	  are available - device and host.
+
 config PHY_EXYNOS4210_USB2
 	bool "Support for Exynos 4210"
 	depends on PHY_SAMSUNG_USB2
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 9f4befd..fefc6c2 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -8,5 +8,6 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)	+= phy-exynos-mipi-video.o
 obj-$(CONFIG_OMAP_USB2)			+= phy-omap-usb2.o
 obj-$(CONFIG_TWL4030_USB)		+= phy-twl4030-usb.o
 obj-$(CONFIG_PHY_SAMSUNG_USB2)		+= phy-samsung-usb2.o
+obj-$(CONFIG_PHY_S5PV210_USB2)		+= phy-s5pv210-usb2.o
 obj-$(CONFIG_PHY_EXYNOS4210_USB2)	+= phy-exynos4210-usb2.o
 obj-$(CONFIG_PHY_EXYNOS4212_USB2)	+= phy-exynos4212-usb2.o
diff --git a/drivers/phy/phy-s5pv210-usb2.c b/drivers/phy/phy-s5pv210-usb2.c
new file mode 100644
index 0000000..f96764c
--- /dev/null
+++ b/drivers/phy/phy-s5pv210-usb2.c
@@ -0,0 +1,188 @@
+/*
+ * Samsung SoC USB 1.1/2.0 PHY driver - S5PV210 support
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Authors: Kamil Debski <k.debski@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/phy/phy.h>
+#include "phy-samsung-usb2.h"
+
+/* Exynos USB PHY registers */
+
+/* PHY power control */
+#define S5PV210_UPHYPWR			0x0
+
+#define S5PV210_UPHYPWR_PHY0_SUSPEND	BIT(0)
+#define S5PV210_UPHYPWR_PHY0_PWR	BIT(3)
+#define S5PV210_UPHYPWR_PHY0_OTG_PWR	BIT(4)
+#define S5PV210_UPHYPWR_PHY0	( \
+	S5PV210_UPHYPWR_PHY0_SUSPEND | \
+	S5PV210_UPHYPWR_PHY0_PWR | \
+	S5PV210_UPHYPWR_PHY0_OTG_PWR)
+
+#define S5PV210_UPHYPWR_PHY1_SUSPEND	BIT(6)
+#define S5PV210_UPHYPWR_PHY1_PWR	BIT(7)
+#define S5PV210_UPHYPWR_PHY1 ( \
+	S5PV210_UPHYPWR_PHY1_SUSPEND | \
+	S5PV210_UPHYPWR_PHY1_PWR)
+
+/* PHY clock control */
+#define S5PV210_UPHYCLK			0x4
+
+#define S5PV210_UPHYCLK_PHYFSEL_MASK	(0x3 << 0)
+#define S5PV210_UPHYCLK_PHYFSEL_48MHZ	(0x0 << 0)
+#define S5PV210_UPHYCLK_PHYFSEL_24MHZ	(0x3 << 0)
+#define S5PV210_UPHYCLK_PHYFSEL_12MHZ	(0x2 << 0)
+
+#define S5PV210_UPHYCLK_PHY0_ID_PULLUP	BIT(2)
+#define S5PV210_UPHYCLK_PHY0_COMMON_ON	BIT(4)
+#define S5PV210_UPHYCLK_PHY1_COMMON_ON	BIT(7)
+
+/* PHY reset control */
+#define S5PV210_UPHYRST			0x8
+
+#define S5PV210_URSTCON_PHY0		BIT(0)
+#define S5PV210_URSTCON_OTG_HLINK	BIT(1)
+#define S5PV210_URSTCON_OTG_PHYLINK	BIT(2)
+#define S5PV210_URSTCON_PHY1_ALL	BIT(3)
+#define S5PV210_URSTCON_HOST_LINK_ALL	BIT(4)
+
+/* Isolation, configured in the power management unit */
+#define S5PV210_USB_ISOL_OFFSET		0x680c
+#define S5PV210_USB_ISOL_DEVICE		BIT(0)
+#define S5PV210_USB_ISOL_HOST		BIT(1)
+
+
+enum s5pv210_phy_id {
+	S5PV210_DEVICE,
+	S5PV210_HOST,
+	S5PV210_NUM_PHYS,
+};
+
+/*
+ * s5pv210_rate_to_clk() converts the supplied clock rate to the value that
+ * can be written to the phy register.
+ */
+static int s5pv210_rate_to_clk(unsigned long rate, u32 *reg)
+{
+	switch (rate) {
+	case 12 * MHZ:
+		*reg = S5PV210_UPHYCLK_PHYFSEL_12MHZ;
+		break;
+	case 24 * MHZ:
+		*reg = S5PV210_UPHYCLK_PHYFSEL_24MHZ;
+		break;
+	case 48 * MHZ:
+		*reg = S5PV210_UPHYCLK_PHYFSEL_48MHZ;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static void s5pv210_isol(struct samsung_usb2_phy_instance *inst, bool on)
+{
+	struct samsung_usb2_phy_driver *drv = inst->drv;
+	u32 mask;
+
+	switch (inst->cfg->id) {
+	case S5PV210_DEVICE:
+		mask = S5PV210_USB_ISOL_DEVICE;
+		break;
+	case S5PV210_HOST:
+		mask = S5PV210_USB_ISOL_HOST;
+		break;
+	default:
+		return;
+	};
+
+	regmap_update_bits(drv->reg_pmu, S5PV210_USB_ISOL_OFFSET,
+							mask, on ? 0 : mask);
+}
+
+static void s5pv210_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on)
+{
+	struct samsung_usb2_phy_driver *drv = inst->drv;
+	u32 rstbits = 0;
+	u32 phypwr = 0;
+	u32 rst;
+	u32 pwr;
+
+	switch (inst->cfg->id) {
+	case S5PV210_DEVICE:
+		phypwr =	S5PV210_UPHYPWR_PHY0;
+		rstbits =	S5PV210_URSTCON_PHY0;
+		break;
+	case S5PV210_HOST:
+		phypwr =	S5PV210_UPHYPWR_PHY1;
+		rstbits =	S5PV210_URSTCON_PHY1_ALL |
+				S5PV210_URSTCON_HOST_LINK_ALL;
+		break;
+	};
+
+	if (on) {
+		writel(inst->clk_reg_val, drv->reg_phy + S5PV210_UPHYCLK);
+
+		pwr = readl(drv->reg_phy + S5PV210_UPHYPWR);
+		pwr &= ~phypwr;
+		writel(pwr, drv->reg_phy + S5PV210_UPHYPWR);
+
+		rst = readl(drv->reg_phy + S5PV210_UPHYRST);
+		rst |= rstbits;
+		writel(rst, drv->reg_phy + S5PV210_UPHYRST);
+		udelay(10);
+		rst &= ~rstbits;
+		writel(rst, drv->reg_phy + S5PV210_UPHYRST);
+	} else {
+		pwr = readl(drv->reg_phy + S5PV210_UPHYPWR);
+		pwr |= phypwr;
+		writel(pwr, drv->reg_phy + S5PV210_UPHYPWR);
+	}
+}
+
+static int s5pv210_power_on(struct samsung_usb2_phy_instance *inst)
+{
+	s5pv210_isol(inst, 0);
+	s5pv210_phy_pwr(inst, 1);
+
+	return 0;
+}
+
+static int s5pv210_power_off(struct samsung_usb2_phy_instance *inst)
+{
+	s5pv210_phy_pwr(inst, 0);
+	s5pv210_isol(inst, 1);
+
+	return 0;
+}
+
+static const struct samsung_usb2_common_phy s5pv210_phys[S5PV210_NUM_PHYS] = {
+	[S5PV210_DEVICE] = {
+		.label		= "device",
+		.id		= S5PV210_DEVICE,
+		.rate_to_clk	= s5pv210_rate_to_clk,
+		.power_on	= s5pv210_power_on,
+		.power_off	= s5pv210_power_off,
+	},
+	[S5PV210_HOST] = {
+		.label		= "host",
+		.id		= S5PV210_HOST,
+		.rate_to_clk	= s5pv210_rate_to_clk,
+		.power_on	= s5pv210_power_on,
+		.power_off	= s5pv210_power_off,
+	},
+};
+
+const struct samsung_usb2_phy_config s5pv210_usb2_phy_config = {
+	.num_phys	= ARRAY_SIZE(s5pv210_phys),
+	.phys		= s5pv210_phys,
+};
diff --git a/drivers/phy/phy-samsung-usb2.c b/drivers/phy/phy-samsung-usb2.c
index 3c09e0e..464a626 100644
--- a/drivers/phy/phy-samsung-usb2.c
+++ b/drivers/phy/phy-samsung-usb2.c
@@ -95,6 +95,12 @@ static struct phy *samsung_usb2_phy_xlate(struct device *dev,
 }
 
 static const struct of_device_id samsung_usb2_phy_of_match[] = {
+#ifdef CONFIG_PHY_S5PV210_USB2
+	{
+		.compatible = "samsung,s5pv210-usb2-phy",
+		.data = &s5pv210_usb2_phy_config,
+	},
+#endif
 #ifdef CONFIG_PHY_EXYNOS4210_USB2
 	{
 		.compatible = "samsung,exynos4210-usb2-phy",
diff --git a/drivers/phy/phy-samsung-usb2.h b/drivers/phy/phy-samsung-usb2.h
index ab89f91..5f5b240 100644
--- a/drivers/phy/phy-samsung-usb2.h
+++ b/drivers/phy/phy-samsung-usb2.h
@@ -61,6 +61,7 @@ struct samsung_usb2_phy_config {
 	bool has_mode_switch;
 };
 
+extern const struct samsung_usb2_phy_config s5pv210_usb2_phy_config;
 extern const struct samsung_usb2_phy_config exynos4210_usb2_phy_config;
 extern const struct samsung_usb2_phy_config exynos4212_usb2_phy_config;
 #endif
-- 
1.8.5.2

Re: [PATCH v4 1/9] phy: core: Add an exported of_phy_get function

[Kishon Vijay Abraham I]

Hi,

On Friday 20 December 2013 06:54 PM, Kamil Debski wrote:
> Previously the of_phy_get function took a struct device * and
> was declared static. It was impossible to call it from
> another driver and thus it was impossible to get phy defined
> for a given node. The old function was renamed to _of_phy_get
> and was left for internal use. of_phy_get function was added
> and it was exported. The function enables to get a phy for
> a given device tree node.
>
> Signed-off-by: Kamil Debski <k.debski@samsung.com>
> ---
>   drivers/phy/phy-core.c  |   45 ++++++++++++++++++++++++++++++++++++---------
>   include/linux/phy/phy.h |    1 +
>   2 files changed, 37 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
> index 03cf8fb..d6f8c34 100644
> --- a/drivers/phy/phy-core.c
> +++ b/drivers/phy/phy-core.c
> @@ -240,8 +240,8 @@ out:
>   EXPORT_SYMBOL_GPL(phy_power_off);
>
>   /**
> - * of_phy_get() - lookup and obtain a reference to a phy by phandle
> - * @dev: device that requests this phy
> + * _of_phy_get() - lookup and obtain a reference to a phy by phandle
> + * @np: device_node for which to get the phy
>    * @index: the index of the phy
>    *
>    * Returns the phy associated with the given phandle value,
> @@ -250,20 +250,17 @@ EXPORT_SYMBOL_GPL(phy_power_off);
>    * not yet loaded. This function uses of_xlate call back function provided
>    * while registering the phy_provider to find the phy instance.
>    */
> -static struct phy *of_phy_get(struct device *dev, int index)
> +static struct phy *_of_phy_get(struct device_node *np, int index)
>   {
>   	int ret;
>   	struct phy_provider *phy_provider;
>   	struct phy *phy = NULL;
>   	struct of_phandle_args args;
>
> -	ret = of_parse_phandle_with_args(dev->of_node, "phys", "#phy-cells",
> +	ret = of_parse_phandle_with_args(np, "phys", "#phy-cells",
>   		index, &args);
> -	if (ret) {
> -		dev_dbg(dev, "failed to get phy in %s node\n",
> -			dev->of_node->full_name);
> +	if (ret)
>   		return ERR_PTR(-ENODEV);
> -	}
>
>   	mutex_lock(&phy_provider_mutex);
>   	phy_provider = of_phy_provider_lookup(args.np);
> @@ -283,6 +280,36 @@ err0:
>   }
>
>   /**
> + * of_phy_get() - lookup and obtain a reference to a phy using a device_node.
> + * @np: device_node for which to get the phy
> + * @con_id: name of the phy from device's point of view
> + *
> + * Returns the phy driver, after getting a refcount to it; or
> + * -ENODEV if there is no such phy. The caller is responsible for
> + * calling phy_put() to release that count.
> + */
> +struct phy *of_phy_get(struct device_node *np, const char *con_id)
> +{
> +	struct phy *phy = NULL;
> +	int index = 0;
> +
> +	if (con_id)
> +		index = of_property_match_string(np, "phy-names", con_id);
> +
> +	phy = _of_phy_get(np, index);
> +	if (IS_ERR(phy))
> +		return phy;
> +
> +	if (!try_module_get(phy->ops->owner))
> +		return ERR_PTR(-EPROBE_DEFER);
> +
> +	get_device(&phy->dev);
> +
> +	return phy;
> +}
> +EXPORT_SYMBOL_GPL(of_phy_get);
> +
> +/**
>    * phy_put() - release the PHY
>    * @phy: the phy returned by phy_get()
>    *
> @@ -370,7 +397,7 @@ struct phy *phy_get(struct device *dev, const char *string)
>   	if (dev->of_node) {
>   		index = of_property_match_string(dev->of_node, "phy-names",
>   			string);
> -		phy = of_phy_get(dev, index);
> +		phy = _of_phy_get(dev->of_node, index);
>   		if (IS_ERR(phy)) {
>   			dev_err(dev, "unable to find phy\n");
>   			return phy;
> diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
> index 6d72269..bcb6274 100644
> --- a/include/linux/phy/phy.h
> +++ b/include/linux/phy/phy.h
> @@ -131,6 +131,7 @@ struct phy *phy_get(struct device *dev, const char *string);
>   struct phy *devm_phy_get(struct device *dev, const char *string);
>   void phy_put(struct phy *phy);
>   void devm_phy_put(struct device *dev, struct phy *phy);
> +struct phy *of_phy_get(struct device_node *np, const char *con_id);

Add a stub for of_phy_get if CONFIG_GENERIC_PHY is not set and this 
patch should be ready for merge.

Thanks
Kishon

Re: [PATCH v4 2/9] phy: core: Add devm_of_phy_get to phy-core

[Kishon Vijay Abraham I]

On Friday 20 December 2013 06:54 PM, Kamil Debski wrote:
> Adding devm_of_phy_get will allow to get phys by supplying a
> pointer to the struct device_node instead of struct device.
>
> Signed-off-by: Kamil Debski <k.debski@samsung.com>
> ---
>   drivers/phy/phy-core.c  |   31 +++++++++++++++++++++++++++++++
>   include/linux/phy/phy.h |    2 ++
>   2 files changed, 33 insertions(+)
>
> diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
> index d6f8c34..0551cc3 100644
> --- a/drivers/phy/phy-core.c
> +++ b/drivers/phy/phy-core.c
> @@ -450,6 +450,37 @@ struct phy *devm_phy_get(struct device *dev, const char *string)
>   EXPORT_SYMBOL_GPL(devm_phy_get);
>
>   /**
> + * devm_of_phy_get() - lookup and obtain a reference to a phy.
> + * @dev: device that requests this phy
> + * @np: node containing the phy
> + * @con_id: name of the phy from device's point of view
> + *
> + * Gets the phy using of_phy_get(), and associates a device with it using
> + * devres. On driver detach, release function is invoked on the devres data,
> + * then, devres data is freed.
> + */
> +struct phy *devm_of_phy_get(struct device *dev, struct device_node *np,
> +			    const char *con_id)
> +{
> +	struct phy **ptr, *phy;
> +
> +	ptr = devres_alloc(devm_phy_release, sizeof(*ptr), GFP_KERNEL);
> +	if (!ptr)
> +		return ERR_PTR(-ENOMEM);
> +
> +	phy = of_phy_get(np, con_id);
> +	if (!IS_ERR(phy)) {
> +		*ptr = phy;
> +		devres_add(dev, ptr);
> +	} else {
> +		devres_free(ptr);
> +	}
> +
> +	return phy;
> +}
> +EXPORT_SYMBOL_GPL(devm_of_phy_get);
> +
> +/**
>    * phy_create() - create a new phy
>    * @dev: device that is creating the new phy
>    * @ops: function pointers for performing phy operations
> diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
> index bcb6274..864914c 100644
> --- a/include/linux/phy/phy.h
> +++ b/include/linux/phy/phy.h
> @@ -129,6 +129,8 @@ int phy_power_on(struct phy *phy);
>   int phy_power_off(struct phy *phy);
>   struct phy *phy_get(struct device *dev, const char *string);
>   struct phy *devm_phy_get(struct device *dev, const char *string);
> +struct phy *devm_of_phy_get(struct device *dev, struct device_node *np,
> +			    const char *con_id);

stub for devm_of_phy_get also..

Thanks
Kishon
>   void phy_put(struct phy *phy);
>   void devm_phy_put(struct device *dev, struct phy *phy);
>   struct phy *of_phy_get(struct device_node *np, const char *con_id);
>

Re: [PATCH v5 3/9] phy: Add new Exynos USB 2.0 PHY driver

[Kishon Vijay Abraham I]

Hi,

On Friday 20 December 2013 06:54 PM, Kamil Debski wrote:
> Add a new driver for the Exynos USB 2.0 PHY. The new driver uses the generic
> PHY framework. The driver includes support for the Exynos 4x10 and 4x12
> SoC families.
>
> Signed-off-by: Kamil Debski <k.debski@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> ---
>   .../devicetree/bindings/phy/samsung-phy.txt        |   55 ++++
>   drivers/phy/Kconfig                                |   29 ++
>   drivers/phy/Makefile                               |    3 +
>   drivers/phy/phy-exynos4210-usb2.c                  |  257 ++++++++++++++++
>   drivers/phy/phy-exynos4212-usb2.c                  |  306 ++++++++++++++++++++
>   drivers/phy/phy-samsung-usb2.c                     |  226 +++++++++++++++
>   drivers/phy/phy-samsung-usb2.h                     |   67 +++++
>   7 files changed, 943 insertions(+)
>   create mode 100644 drivers/phy/phy-exynos4210-usb2.c
>   create mode 100644 drivers/phy/phy-exynos4212-usb2.c
>   create mode 100644 drivers/phy/phy-samsung-usb2.c
>   create mode 100644 drivers/phy/phy-samsung-usb2.h
>
.
.
<snip>
.
.

> diff --git a/drivers/phy/phy-samsung-usb2.h b/drivers/phy/phy-samsung-usb2.h
> new file mode 100644
> index 0000000..ab89f91
> --- /dev/null
> +++ b/drivers/phy/phy-samsung-usb2.h
> @@ -0,0 +1,67 @@
> +/*
> + * Samsung SoC USB 1.1/2.0 PHY driver
> + *
> + * Copyright (C) 2013 Samsung Electronics Co., Ltd.
> + * Author: Kamil Debski <k.debski@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#ifndef _PHY_EXYNOS_USB2_H
> +#define _PHY_EXYNOS_USB2_H
> +
> +#include <linux/clk.h>
> +#include <linux/phy/phy.h>
> +#include <linux/device.h>
> +#include <linux/regmap.h>
> +#include <linux/spinlock.h>
> +
> +#define KHZ 1000
> +#define MHZ (KHZ * KHZ)
> +
> +struct samsung_usb2_phy_driver;
> +struct samsung_usb2_phy_instance;
> +struct samsung_usb2_phy_config;
> +
> +struct samsung_usb2_phy_instance {
> +	const struct samsung_usb2_common_phy *cfg;
> +	struct clk *clk;
> +	struct phy *phy;
> +	struct samsung_usb2_phy_driver *drv;
> +	unsigned long rate;
> +	u32 clk_reg_val;
> +	bool enabled;
> +};
> +
> +struct samsung_usb2_phy_driver {
> +	const struct samsung_usb2_phy_config *cfg;
> +	struct clk *clk;
> +	struct device *dev;
> +	void __iomem *reg_phy;
> +	struct regmap *reg_pmu;
> +	struct regmap *reg_sys;
> +	spinlock_t lock;
> +	struct samsung_usb2_phy_instance instances[0];

I think having instances as array here would allocate more space while 
allocating 'samsung_usb2_phy_driver' in 'samsung_usb2_phy_probe'.

Thanks
Kishon

Re: [PATCH RFC alternative ver 1] phy: Exynos 421x USB 2.0 PHY support

[Kishon Vijay Abraham I]

Hi,

On Friday 20 December 2013 06:54 PM, Kamil Debski wrote:
> This the alternative version of the support for Exynos 421x USB 2.0 PHY
> in the Generic PHY framework. In this version the support for Exynos
> 4210 and 4212 was joined into one file.
>
> Signed-off-by: Kamil Debski <k.debski@samsung.com>
> ---
> Hi,
>
> Me and Kishon were discussing for quite a long time the way how Exynos 4
> should be handled. I have decided to post the original patches and try
> to make an alternative version with support for Exynos 4210 and 4212 joined
> in one file. I have prepared two versions. The first one has 506 lines (vs
> 563 when two files are used). When doing the second version I was a little
> more aggresive in removing code. This was done at a cost of adding if's
> deciding which SoC version the driver is dealing with in some internal functions.
> This resulted in a better number of removed lines - the second version has
> only 452 lines (vs 563 original and 506 version 1).

Alright.. If the alternate approach doesn't give too much of advantage, 
lets stick with the original one. I would recommend creating a 
documentation (Documentation/phy/?) for the samsung PHY since that 
actually creates a layer on top of generic PHY framework. That would 
help while adding new samsung PHY drivers.

Btw thank you for preparing alternate versions for your original patches.

Cheers
Kishon

RE: [PATCH RFC alternative ver 1] phy: Exynos 421x USB 2.0 PHY support

[Kamil Debski]

Hi Kishon,

Thank you for your review.

> From: Kishon Vijay Abraham I [mailto:kishon@ti.com]
> Sent: Monday, January 06, 2014 11:24 AM
> 
> Hi,
> 
> On Friday 20 December 2013 06:54 PM, Kamil Debski wrote:
> > This the alternative version of the support for Exynos 421x USB 2.0
> > PHY in the Generic PHY framework. In this version the support for
> > Exynos
> > 4210 and 4212 was joined into one file.
> >
> > Signed-off-by: Kamil Debski <k.debski@samsung.com>
> > ---
> > Hi,
> >
> > Me and Kishon were discussing for quite a long time the way how
> Exynos
> > 4 should be handled. I have decided to post the original patches and
> > try to make an alternative version with support for Exynos 4210 and
> > 4212 joined in one file. I have prepared two versions. The first one
> > has 506 lines (vs
> > 563 when two files are used). When doing the second version I was a
> > little more aggresive in removing code. This was done at a cost of
> > adding if's deciding which SoC version the driver is dealing with in
> some internal functions.
> > This resulted in a better number of removed lines - the second
> version
> > has only 452 lines (vs 563 original and 506 version 1).
> 
> Alright.. If the alternate approach doesn't give too much of advantage,
> lets stick with the original one. I would recommend creating a
> documentation (Documentation/phy/?) for the samsung PHY since that
> actually creates a layer on top of generic PHY framework. That would
> help while adding new samsung PHY drivers.

Ok, I will prepare an updated set of patches with the documentation
added. Also I will fix other issues you pointed out in reply to other
patches from this series.

> 
> Btw thank you for preparing alternate versions for your original
> patches.

No problem :)

Best wishes,
-- 
Kamil Debski
Samsung R&D Institute Poland

RE: [PATCH v5 3/9] phy: Add new Exynos USB 2.0 PHY driver

[Kamil Debski]

Hi,

> From: Kishon Vijay Abraham I [mailto:kishon@ti.com]
> Sent: Monday, January 06, 2014 11:12 AM
> 
> Hi,
> 
> On Friday 20 December 2013 06:54 PM, Kamil Debski wrote:
> > Add a new driver for the Exynos USB 2.0 PHY. The new driver uses the
> > generic PHY framework. The driver includes support for the Exynos
> 4x10
> > and 4x12 SoC families.
> >
> > Signed-off-by: Kamil Debski <k.debski@samsung.com>
> > Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> > ---
> >   .../devicetree/bindings/phy/samsung-phy.txt        |   55 ++++
> >   drivers/phy/Kconfig                                |   29 ++
> >   drivers/phy/Makefile                               |    3 +
> >   drivers/phy/phy-exynos4210-usb2.c                  |  257
> ++++++++++++++++
> >   drivers/phy/phy-exynos4212-usb2.c                  |  306
> ++++++++++++++++++++
> >   drivers/phy/phy-samsung-usb2.c                     |  226
> +++++++++++++++
> >   drivers/phy/phy-samsung-usb2.h                     |   67 +++++
> >   7 files changed, 943 insertions(+)
> >   create mode 100644 drivers/phy/phy-exynos4210-usb2.c
> >   create mode 100644 drivers/phy/phy-exynos4212-usb2.c
> >   create mode 100644 drivers/phy/phy-samsung-usb2.c
> >   create mode 100644 drivers/phy/phy-samsung-usb2.h
> >
> .
> .
> <snip>
> .
> .
> 
> > diff --git a/drivers/phy/phy-samsung-usb2.h
> > b/drivers/phy/phy-samsung-usb2.h new file mode 100644 index
> > 0000000..ab89f91
> > --- /dev/null
> > +++ b/drivers/phy/phy-samsung-usb2.h
> > @@ -0,0 +1,67 @@
> > +/*
> > + * Samsung SoC USB 1.1/2.0 PHY driver
> > + *
> > + * Copyright (C) 2013 Samsung Electronics Co., Ltd.
> > + * Author: Kamil Debski <k.debski@samsung.com>
> > + *
> > + * This program is free software; you can redistribute it and/or
> > +modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + */
> > +
> > +#ifndef _PHY_EXYNOS_USB2_H
> > +#define _PHY_EXYNOS_USB2_H
> > +
> > +#include <linux/clk.h>
> > +#include <linux/phy/phy.h>
> > +#include <linux/device.h>
> > +#include <linux/regmap.h>
> > +#include <linux/spinlock.h>
> > +
> > +#define KHZ 1000
> > +#define MHZ (KHZ * KHZ)
> > +
> > +struct samsung_usb2_phy_driver;
> > +struct samsung_usb2_phy_instance;
> > +struct samsung_usb2_phy_config;
> > +
> > +struct samsung_usb2_phy_instance {
> > +	const struct samsung_usb2_common_phy *cfg;
> > +	struct clk *clk;
> > +	struct phy *phy;
> > +	struct samsung_usb2_phy_driver *drv;
> > +	unsigned long rate;
> > +	u32 clk_reg_val;
> > +	bool enabled;
> > +};
> > +
> > +struct samsung_usb2_phy_driver {
> > +	const struct samsung_usb2_phy_config *cfg;
> > +	struct clk *clk;
> > +	struct device *dev;
> > +	void __iomem *reg_phy;
> > +	struct regmap *reg_pmu;
> > +	struct regmap *reg_sys;
> > +	spinlock_t lock;
> > +	struct samsung_usb2_phy_instance instances[0];
> 
> I think having instances as array here would allocate more space while
> allocating 'samsung_usb2_phy_driver' in 'samsung_usb2_phy_probe'.
> 

I am not sure if I understand you correctly here. Maybe I will explain
what I intended to write. An array with size 0 at the end of a structure
takes no space in the structure. The benefit of using it is that after
the structure one can allocate a number of the array elements and
address them easily. Another option would be placing pointer in the
samsung_usb2_phy_instance and allocate memory separately, but this would
involve two allocations and a pointer would be always present in the 
structure.

Best wishes,
-- 
Kamil Debski
Samsung R&D Institute Poland

Re: [PATCH v5 3/9] phy: Add new Exynos USB 2.0 PHY driver

[Kishon Vijay Abraham I]

Hi,

On Wednesday 08 January 2014 11:26 PM, Kamil Debski wrote:
> Hi,
> 
>> From: Kishon Vijay Abraham I [mailto:kishon@ti.com]
>> Sent: Monday, January 06, 2014 11:12 AM
>>
>> Hi,
>>
>> On Friday 20 December 2013 06:54 PM, Kamil Debski wrote:
>>> Add a new driver for the Exynos USB 2.0 PHY. The new driver uses the
>>> generic PHY framework. The driver includes support for the Exynos
>> 4x10
>>> and 4x12 SoC families.
>>>
>>> Signed-off-by: Kamil Debski <k.debski@samsung.com>
>>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>>> ---
>>>   .../devicetree/bindings/phy/samsung-phy.txt        |   55 ++++
>>>   drivers/phy/Kconfig                                |   29 ++
>>>   drivers/phy/Makefile                               |    3 +
>>>   drivers/phy/phy-exynos4210-usb2.c                  |  257
>> ++++++++++++++++
>>>   drivers/phy/phy-exynos4212-usb2.c                  |  306
>> ++++++++++++++++++++
>>>   drivers/phy/phy-samsung-usb2.c                     |  226
>> +++++++++++++++
>>>   drivers/phy/phy-samsung-usb2.h                     |   67 +++++
>>>   7 files changed, 943 insertions(+)
>>>   create mode 100644 drivers/phy/phy-exynos4210-usb2.c
>>>   create mode 100644 drivers/phy/phy-exynos4212-usb2.c
>>>   create mode 100644 drivers/phy/phy-samsung-usb2.c
>>>   create mode 100644 drivers/phy/phy-samsung-usb2.h
>>>
>> .
>> .
>> <snip>
>> .
>> .
>>
>>> diff --git a/drivers/phy/phy-samsung-usb2.h
>>> b/drivers/phy/phy-samsung-usb2.h new file mode 100644 index
>>> 0000000..ab89f91
>>> --- /dev/null
>>> +++ b/drivers/phy/phy-samsung-usb2.h
>>> @@ -0,0 +1,67 @@
>>> +/*
>>> + * Samsung SoC USB 1.1/2.0 PHY driver
>>> + *
>>> + * Copyright (C) 2013 Samsung Electronics Co., Ltd.
>>> + * Author: Kamil Debski <k.debski@samsung.com>
>>> + *
>>> + * This program is free software; you can redistribute it and/or
>>> +modify
>>> + * it under the terms of the GNU General Public License version 2 as
>>> + * published by the Free Software Foundation.
>>> + */
>>> +
>>> +#ifndef _PHY_EXYNOS_USB2_H
>>> +#define _PHY_EXYNOS_USB2_H
>>> +
>>> +#include <linux/clk.h>
>>> +#include <linux/phy/phy.h>
>>> +#include <linux/device.h>
>>> +#include <linux/regmap.h>
>>> +#include <linux/spinlock.h>
>>> +
>>> +#define KHZ 1000
>>> +#define MHZ (KHZ * KHZ)
>>> +
>>> +struct samsung_usb2_phy_driver;
>>> +struct samsung_usb2_phy_instance;
>>> +struct samsung_usb2_phy_config;
>>> +
>>> +struct samsung_usb2_phy_instance {
>>> +	const struct samsung_usb2_common_phy *cfg;
>>> +	struct clk *clk;
>>> +	struct phy *phy;
>>> +	struct samsung_usb2_phy_driver *drv;
>>> +	unsigned long rate;
>>> +	u32 clk_reg_val;
>>> +	bool enabled;
>>> +};
>>> +
>>> +struct samsung_usb2_phy_driver {
>>> +	const struct samsung_usb2_phy_config *cfg;
>>> +	struct clk *clk;
>>> +	struct device *dev;
>>> +	void __iomem *reg_phy;
>>> +	struct regmap *reg_pmu;
>>> +	struct regmap *reg_sys;
>>> +	spinlock_t lock;
>>> +	struct samsung_usb2_phy_instance instances[0];
>>
>> I think having instances as array here would allocate more space while
>> allocating 'samsung_usb2_phy_driver' in 'samsung_usb2_phy_probe'.
>>
> 
> I am not sure if I understand you correctly here. Maybe I will explain
> what I intended to write. An array with size 0 at the end of a structure
> takes no space in the structure. The benefit of using it is that after
> the structure one can allocate a number of the array elements and
> address them easily. Another option would be placing pointer in the
> samsung_usb2_phy_instance and allocate memory separately, but this would
> involve two allocations and a pointer would be always present in the 
> structure.

Al-right.. makes sense.

Thanks
Kishon
> 
> Best wishes,
>