* Re: [PATCH v4 6/9] ARM: dts: Add memory bus node for Exynos4210
@ 2015-01-19 9:33 MyungJoo Ham
0 siblings, 0 replies; 2+ messages in thread
From: MyungJoo Ham @ 2015-01-19 9:33 UTC (permalink / raw)
To: 최찬우, kgene
Cc: 박경민,
rafael.j.wysocki, mark.rutland, ABHILASH KESAVAN, tomasz.figa,
Krzysztof Kozlowski, Bartlomiej Zolnierkiewicz, robh+dt,
대인기,
linux-pm, linux-kernel, linux-arm-kernel, linux-samsung-soc
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>
> This patch adds the memory bus node for Exynos4210 SoC. Exynos4210 SoC has
> one memory bus to translate data between DRAM and eMMC/sub-IPs because
> Exynos4210 must need only one regulator for memory bus.
>
> Following list specifies the detailed relation between memory bus clock and
> sub-IPs:
> - DMC/ACP clock : DMC (Dynamic Memory Controller)
> - ACLK200 clock : LCD0
> - ACLK100 clock : PERIL/PERIR/MFC(PCLK)
> - ACLK160 clock : CAM/TV/LCD0/LCD1
> - ACLK133 clock : FSYS/GPS
> - GDL/GDR clock : leftbus/rightbus
> - SCLK_MFC clock : MFC
>
> Cc: Kukjin Kim <kgene@kernel.org>
> Cc: Myungjoo Ham <myungjoo.ham@samsung.com>
> Cc: Kyungmin Park <kyungmin.park@samsung.com>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: MyungJoo Ham <myungjoo.ham@samsung.com>
Revisiting good old days..?
(good to see the first busfreq driver experimented with is
being DT-nized... :) )
Cheers,
MyungJoo
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^ permalink raw reply [flat|nested] 2+ messages in thread
* [PATCH v4 6/9] ARM: dts: Add memory bus node for Exynos4210
2015-01-15 1:50 [PATCH v4 0/9] devfreq: Add generic exynos memory-bus frequency driver Chanwoo Choi
@ 2015-01-15 1:50 ` Chanwoo Choi
0 siblings, 0 replies; 2+ messages in thread
From: Chanwoo Choi @ 2015-01-15 1:50 UTC (permalink / raw)
To: myungjoo.ham, kgene
Cc: kyungmin.park, rafael.j.wysocki, mark.rutland, a.kesavan,
tomasz.figa, k.kozlowski, b.zolnierkie, robh+dt, cw00.choi,
inki.dae, linux-pm, linux-kernel, linux-arm-kernel,
linux-samsung-soc
This patch adds the memory bus node for Exynos4210 SoC. Exynos4210 SoC has
one memory bus to translate data between DRAM and eMMC/sub-IPs because
Exynos4210 must need only one regulator for memory bus.
Following list specifies the detailed relation between memory bus clock and
sub-IPs:
- DMC/ACP clock : DMC (Dynamic Memory Controller)
- ACLK200 clock : LCD0
- ACLK100 clock : PERIL/PERIR/MFC(PCLK)
- ACLK160 clock : CAM/TV/LCD0/LCD1
- ACLK133 clock : FSYS/GPS
- GDL/GDR clock : leftbus/rightbus
- SCLK_MFC clock : MFC
Cc: Kukjin Kim <kgene@kernel.org>
Cc: Myungjoo Ham <myungjoo.ham@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
arch/arm/boot/dts/exynos4210.dtsi | 93 +++++++++++++++++++++++++++++++++++++++
1 file changed, 93 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index b2598de..c039409 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -48,6 +48,99 @@
};
};
+ memory_bus: memory_bus@0 {
+ compatible = "samsung,exynos-memory-bus";
+
+ operating-points = <
+ 400000 1150000
+ 267000 1050000
+ 133000 1025000>;
+ status = "disabled";
+
+ blocks {
+ dmc_block: memory_bus_block1 {
+ clocks = <&clock CLK_DIV_DMC>;
+ clock-names = "memory-bus";
+ frequency = <
+ 400000
+ 267000
+ 133000>;
+ };
+
+ acp_block: memory_bus_block2 {
+ clocks = <&clock CLK_DIV_ACP>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 160000
+ 133000>;
+ };
+
+ peri_block: memory_bus_block3 {
+ clocks = <&clock CLK_ACLK100>;
+ clock-names = "memory-bus";
+ frequency = <
+ 100000
+ 100000
+ 100000>;
+ };
+
+ fsys_block: memory_bus_block4 {
+ clocks = <&clock CLK_ACLK133>;
+ clock-names = "memory-bus";
+ frequency = <
+ 133000
+ 133000
+ 100000>;
+ };
+
+ display_block: memory_bus_block5 {
+ clocks = <&clock CLK_ACLK160>;
+ clock-names = "memory-bus";
+ frequency = <
+ 160000
+ 133000
+ 100000>;
+ };
+
+ lcd0_block: memory_bus_block6 {
+ clocks = <&clock CLK_ACLK200>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 160000
+ 100000>;
+ };
+
+ leftbus_block: memory_bus_block7 {
+ clocks = <&clock CLK_DIV_GDL>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 160000
+ 100000>;
+ };
+
+ rightbus_block: memory_bus_block8 {
+ clocks = <&clock CLK_DIV_GDR>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 160000
+ 100000>;
+ };
+
+ mfc_block: memory_bus_block9 {
+ clocks = <&clock CLK_SCLK_MFC>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 160000
+ 100000>;
+ };
+ };
+ };
+
pmu_system_controller: system-controller@10020000 {
clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
"clkout4", "clkout8", "clkout9";
--
1.8.5.5
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2015-01-19 9:33 [PATCH v4 6/9] ARM: dts: Add memory bus node for Exynos4210 MyungJoo Ham
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2015-01-15 1:50 ` [PATCH v4 6/9] ARM: dts: Add memory bus node for Exynos4210 Chanwoo Choi
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