* [PATCH V6 0/4] perf/x86/amd: AMD Family 16h Data Breakpoint Extensions
@ 2013-12-11 12:28 suravee.suthikulpanit
2013-12-11 12:28 ` [PATCH 1/4] perf/x86/amd: AMD support for bp_len > HW_BREAKPOINT_LEN_8 suravee.suthikulpanit
` (4 more replies)
0 siblings, 5 replies; 11+ messages in thread
From: suravee.suthikulpanit @ 2013-12-11 12:28 UTC (permalink / raw)
To: fweisbec, mingo, mingo, jacob.w.shin
Cc: oleg, a.p.zijlstra, acme, hpa, linux-kernel, sherry.hurwitz,
Suravee Suthikulpanit
From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
The following patchset enables hardware breakpoint bp_len greater than
HW_BREAKPOINT_LEN_8 on AMD Family 16h and later.
$ perf stat -e mem:0x1000/16:w a.out
^^
bp_len
This will count writes to [0x1000 ~ 0x1010)
V6:
* Minor clean up in patch 1 and 2 based on comment from Frederic and Oleg.
* Split out changes in patch1 into patch4 per Frederic request.
V5:
* Rebase onto 3.12.0-rc3.
* Modify the tools/perf/util/parse-events.y due to change in
parse_events_add_breakpoint().
V4:
Even more per Oleg's suggestion:
* Further simplify info->len and info->mask setting switch statement
V3:
More per Oleg's suggestion:
* Use already existing bp_len instead of changing userland API and
in kernel turn bp_len into proper AMD hardware breakpoint address
mask.
V2:
Per Oleg's suggestions:
* Moved testing of bp_addr_mask to validate_hw_breakpoint()
* Changed perf tool syntax to mem:<addr>[/addr_mask][:access]
Jacob Shin (4):
perf/x86/amd: AMD support for bp_len > HW_BREAKPOINT_LEN_8
perf tools: allow user to specify hardware breakpoint bp_len
perf tools: add hardware breakpoint bp_len test cases
perf/x86: Remove get_hbp_len and replace with bp_len
arch/x86/include/asm/cpufeature.h | 2 ++
arch/x86/include/asm/debugreg.h | 5 +++
arch/x86/include/asm/hw_breakpoint.h | 1 +
arch/x86/include/uapi/asm/msr-index.h | 4 +++
arch/x86/kernel/cpu/amd.c | 19 +++++++++++
arch/x86/kernel/hw_breakpoint.c | 45 ++++++++++----------------
tools/perf/Documentation/perf-record.txt | 7 ++--
tools/perf/tests/parse-events.c | 55 ++++++++++++++++++++++++++++++++
tools/perf/util/parse-events.c | 21 ++++++------
tools/perf/util/parse-events.h | 2 +-
tools/perf/util/parse-events.l | 1 +
tools/perf/util/parse-events.y | 26 +++++++++++++--
12 files changed, 145 insertions(+), 43 deletions(-)
--
1.8.1.2
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 1/4] perf/x86/amd: AMD support for bp_len > HW_BREAKPOINT_LEN_8
2013-12-11 12:28 [PATCH V6 0/4] perf/x86/amd: AMD Family 16h Data Breakpoint Extensions suravee.suthikulpanit
@ 2013-12-11 12:28 ` suravee.suthikulpanit
2014-01-09 1:24 ` Frederic Weisbecker
2013-12-11 12:28 ` [PATCH 2/4] perf tools: allow user to specify hardware breakpoint bp_len suravee.suthikulpanit
` (3 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: suravee.suthikulpanit @ 2013-12-11 12:28 UTC (permalink / raw)
To: fweisbec, mingo, mingo, jacob.w.shin
Cc: oleg, a.p.zijlstra, acme, hpa, linux-kernel, sherry.hurwitz,
Suravee Suthikulpanit
From: Jacob Shin <jacob.w.shin@gmail.com>
Implement hardware breakpoint address mask for AMD Family 16h and
above processors. CPUID feature bit indicates hardware support for
DRn_ADDR_MASK MSRs. These masks further qualify DRn/DR7 hardware
breakpoint addresses to allow matching of larger addresses ranges.
Valuable advice and pseudo code from Oleg Nesterov <oleg@redhat.com>
Signed-off-by: Jacob Shin <jacob.w.shin@gmail.com>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
---
arch/x86/include/asm/cpufeature.h | 2 ++
arch/x86/include/asm/debugreg.h | 5 +++++
arch/x86/include/asm/hw_breakpoint.h | 1 +
arch/x86/include/uapi/asm/msr-index.h | 4 ++++
arch/x86/kernel/cpu/amd.c | 19 +++++++++++++++++++
arch/x86/kernel/hw_breakpoint.c | 20 ++++++++++++++++----
6 files changed, 47 insertions(+), 4 deletions(-)
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 89270b4..2e8b0b2 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -170,6 +170,7 @@
#define X86_FEATURE_TOPOEXT (6*32+22) /* topology extensions CPUID leafs */
#define X86_FEATURE_PERFCTR_CORE (6*32+23) /* core performance counter extensions */
#define X86_FEATURE_PERFCTR_NB (6*32+24) /* NB performance counter extensions */
+#define X86_FEATURE_BPEXT (6*32+26) /* data breakpoint extension */
#define X86_FEATURE_PERFCTR_L2 (6*32+28) /* L2 performance counter extensions */
/*
@@ -332,6 +333,7 @@ extern const char * const x86_power_flags[32];
#define cpu_has_cx16 boot_cpu_has(X86_FEATURE_CX16)
#define cpu_has_eager_fpu boot_cpu_has(X86_FEATURE_EAGER_FPU)
#define cpu_has_topoext boot_cpu_has(X86_FEATURE_TOPOEXT)
+#define cpu_has_bpext boot_cpu_has(X86_FEATURE_BPEXT)
#ifdef CONFIG_X86_64
diff --git a/arch/x86/include/asm/debugreg.h b/arch/x86/include/asm/debugreg.h
index 4b528a9..145b009 100644
--- a/arch/x86/include/asm/debugreg.h
+++ b/arch/x86/include/asm/debugreg.h
@@ -114,5 +114,10 @@ static inline void debug_stack_usage_inc(void) { }
static inline void debug_stack_usage_dec(void) { }
#endif /* X86_64 */
+#ifdef CONFIG_CPU_SUP_AMD
+extern void set_dr_addr_mask(unsigned long mask, int dr);
+#else
+static inline void set_dr_addr_mask(unsigned long mask, int dr) { }
+#endif
#endif /* _ASM_X86_DEBUGREG_H */
diff --git a/arch/x86/include/asm/hw_breakpoint.h b/arch/x86/include/asm/hw_breakpoint.h
index ef1c4d2..6c98be8 100644
--- a/arch/x86/include/asm/hw_breakpoint.h
+++ b/arch/x86/include/asm/hw_breakpoint.h
@@ -12,6 +12,7 @@
*/
struct arch_hw_breakpoint {
unsigned long address;
+ unsigned long mask;
u8 len;
u8 type;
};
diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h
index 37813b5..bf8388e 100644
--- a/arch/x86/include/uapi/asm/msr-index.h
+++ b/arch/x86/include/uapi/asm/msr-index.h
@@ -207,6 +207,10 @@
/* Fam 16h MSRs */
#define MSR_F16H_L2I_PERF_CTL 0xc0010230
#define MSR_F16H_L2I_PERF_CTR 0xc0010231
+#define MSR_F16H_DR1_ADDR_MASK 0xc0011019
+#define MSR_F16H_DR2_ADDR_MASK 0xc001101a
+#define MSR_F16H_DR3_ADDR_MASK 0xc001101b
+#define MSR_F16H_DR0_ADDR_MASK 0xc0011027
/* Fam 15h MSRs */
#define MSR_F15H_PERF_CTL 0xc0010200
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index bca023b..b4d895a 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -909,3 +909,22 @@ static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
return false;
}
+
+void set_dr_addr_mask(unsigned long mask, int dr)
+{
+ if (!cpu_has_bpext)
+ return;
+
+ switch (dr) {
+ case 0:
+ wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0);
+ break;
+ case 1:
+ case 2:
+ case 3:
+ wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0);
+ break;
+ default:
+ break;
+ }
+}
diff --git a/arch/x86/kernel/hw_breakpoint.c b/arch/x86/kernel/hw_breakpoint.c
index f66ff16..647b675 100644
--- a/arch/x86/kernel/hw_breakpoint.c
+++ b/arch/x86/kernel/hw_breakpoint.c
@@ -128,6 +128,8 @@ int arch_install_hw_breakpoint(struct perf_event *bp)
*dr7 |= encode_dr7(i, info->len, info->type);
set_debugreg(*dr7, 7);
+ if (info->mask)
+ set_dr_addr_mask(info->mask, i);
return 0;
}
@@ -163,6 +165,8 @@ void arch_uninstall_hw_breakpoint(struct perf_event *bp)
*dr7 &= ~__encode_dr7(i, info->len, info->type);
set_debugreg(*dr7, 7);
+ if (info->mask)
+ set_dr_addr_mask(0, i);
}
static int get_hbp_len(u8 hbp_len)
@@ -279,6 +283,8 @@ static int arch_build_bp_info(struct perf_event *bp)
}
/* Len */
+ info->mask = 0;
+
switch (bp->attr.bp_len) {
case HW_BREAKPOINT_LEN_1:
info->len = X86_BREAKPOINT_LEN_1;
@@ -295,11 +301,17 @@ static int arch_build_bp_info(struct perf_event *bp)
break;
#endif
default:
- return -EINVAL;
+ if (!is_power_of_2(bp->attr.bp_len))
+ return -EINVAL;
+ if (!cpu_has_bpext)
+ return -EOPNOTSUPP;
+ info->mask = bp->attr.bp_len - 1;
+ info->len = X86_BREAKPOINT_LEN_1;
}
return 0;
}
+
/*
* Validate the arch-specific HW Breakpoint register settings
*/
@@ -314,11 +326,11 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp)
if (ret)
return ret;
- ret = -EINVAL;
-
switch (info->len) {
case X86_BREAKPOINT_LEN_1:
align = 0;
+ if (info->mask)
+ align = info->mask;
break;
case X86_BREAKPOINT_LEN_2:
align = 1;
@@ -332,7 +344,7 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp)
break;
#endif
default:
- return ret;
+ WARN_ON_ONCE(1);
}
/*
--
1.8.1.2
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 2/4] perf tools: allow user to specify hardware breakpoint bp_len
2013-12-11 12:28 [PATCH V6 0/4] perf/x86/amd: AMD Family 16h Data Breakpoint Extensions suravee.suthikulpanit
2013-12-11 12:28 ` [PATCH 1/4] perf/x86/amd: AMD support for bp_len > HW_BREAKPOINT_LEN_8 suravee.suthikulpanit
@ 2013-12-11 12:28 ` suravee.suthikulpanit
2013-12-11 12:28 ` [PATCH 3/4] perf tools: add hardware breakpoint bp_len test cases suravee.suthikulpanit
` (2 subsequent siblings)
4 siblings, 0 replies; 11+ messages in thread
From: suravee.suthikulpanit @ 2013-12-11 12:28 UTC (permalink / raw)
To: fweisbec, mingo, mingo, jacob.w.shin
Cc: oleg, a.p.zijlstra, acme, hpa, linux-kernel, sherry.hurwitz,
Suravee Suthikulpanit
From: Jacob Shin <jacob.w.shin@gmail.com>
Currently bp_len is given a default value of 4. Allow user to override it:
$ perf stat -e mem:0x1000/8
^
bp_len
If no value is given, it will default to 4 as it did before.
Signed-off-by: Jacob Shin <jacob.w.shin@gmail.com>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
---
tools/perf/Documentation/perf-record.txt | 7 +++++--
tools/perf/util/parse-events.c | 21 +++++++++++----------
tools/perf/util/parse-events.h | 2 +-
tools/perf/util/parse-events.l | 1 +
tools/perf/util/parse-events.y | 26 ++++++++++++++++++++++++--
5 files changed, 42 insertions(+), 15 deletions(-)
diff --git a/tools/perf/Documentation/perf-record.txt b/tools/perf/Documentation/perf-record.txt
index 43b42c4..7b4f594 100644
--- a/tools/perf/Documentation/perf-record.txt
+++ b/tools/perf/Documentation/perf-record.txt
@@ -33,12 +33,15 @@ OPTIONS
- a raw PMU event (eventsel+umask) in the form of rNNN where NNN is a
hexadecimal event descriptor.
- - a hardware breakpoint event in the form of '\mem:addr[:access]'
+ - a hardware breakpoint event in the form of '\mem:addr[/len][:access]'
where addr is the address in memory you want to break in.
Access is the memory access type (read, write, execute) it can
- be passed as follows: '\mem:addr[:[r][w][x]]'.
+ be passed as follows: '\mem:addr[:[r][w][x]]'. len is the range,
+ number of bytes from specified addr, which the breakpoint will cover.
If you want to profile read-write accesses in 0x1000, just set
'mem:0x1000:rw'.
+ If you want to profile write accesses in [0x1000~1008), just set
+ 'mem:0x1000/8:w'.
--filter=<filter>::
Event filter.
diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c
index 6de6f89..2a15f24 100644
--- a/tools/perf/util/parse-events.c
+++ b/tools/perf/util/parse-events.c
@@ -515,7 +515,7 @@ do { \
}
int parse_events_add_breakpoint(struct list_head *list, int *idx,
- void *ptr, char *type)
+ void *ptr, char *type, u64 len)
{
struct perf_event_attr attr;
@@ -525,14 +525,15 @@ int parse_events_add_breakpoint(struct list_head *list, int *idx,
if (parse_breakpoint_type(type, &attr))
return -EINVAL;
- /*
- * We should find a nice way to override the access length
- * Provide some defaults for now
- */
- if (attr.bp_type == HW_BREAKPOINT_X)
- attr.bp_len = sizeof(long);
- else
- attr.bp_len = HW_BREAKPOINT_LEN_4;
+ /* Provide some defaults if len is not specified */
+ if (!len) {
+ if (attr.bp_type == HW_BREAKPOINT_X)
+ len = sizeof(long);
+ else
+ len = HW_BREAKPOINT_LEN_4;
+ }
+
+ attr.bp_len = len;
attr.type = PERF_TYPE_BREAKPOINT;
attr.sample_period = 1;
@@ -1240,7 +1241,7 @@ void print_events(const char *event_glob, bool name_only)
printf("\n");
printf(" %-50s [%s]\n",
- "mem:<addr>[:access]",
+ "mem:<addr>[/len][:access]",
event_type_descriptors[PERF_TYPE_BREAKPOINT]);
printf("\n");
}
diff --git a/tools/perf/util/parse-events.h b/tools/perf/util/parse-events.h
index f1cb4c4..54a20df 100644
--- a/tools/perf/util/parse-events.h
+++ b/tools/perf/util/parse-events.h
@@ -93,7 +93,7 @@ int parse_events_add_numeric(struct list_head *list, int *idx,
int parse_events_add_cache(struct list_head *list, int *idx,
char *type, char *op_result1, char *op_result2);
int parse_events_add_breakpoint(struct list_head *list, int *idx,
- void *ptr, char *type);
+ void *ptr, char *type, u64 len);
int parse_events_add_pmu(struct list_head *list, int *idx,
char *pmu , struct list_head *head_config);
void parse_events__set_leader(char *name, struct list_head *list);
diff --git a/tools/perf/util/parse-events.l b/tools/perf/util/parse-events.l
index 3432995..199e18a 100644
--- a/tools/perf/util/parse-events.l
+++ b/tools/perf/util/parse-events.l
@@ -141,6 +141,7 @@ branch_type { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_BRANCH_SAMPLE_TYPE
<mem>{
{modifier_bp} { return str(yyscanner, PE_MODIFIER_BP); }
: { return ':'; }
+"/" { return '/'; }
{num_dec} { return value(yyscanner, 10); }
{num_hex} { return value(yyscanner, 16); }
/*
diff --git a/tools/perf/util/parse-events.y b/tools/perf/util/parse-events.y
index 4eb67ec..c9adf4d 100644
--- a/tools/perf/util/parse-events.y
+++ b/tools/perf/util/parse-events.y
@@ -276,6 +276,28 @@ PE_NAME_CACHE_TYPE
}
event_legacy_mem:
+PE_PREFIX_MEM PE_VALUE '/' PE_VALUE ':' PE_MODIFIER_BP sep_dc
+{
+ struct parse_events_evlist *data = _data;
+ struct list_head *list;
+
+ ALLOC_LIST(list);
+ ABORT_ON(parse_events_add_breakpoint(list, &data->idx,
+ (void *) $2, $6, $4));
+ $$ = list;
+}
+|
+PE_PREFIX_MEM PE_VALUE '/' PE_VALUE sep_dc
+{
+ struct parse_events_evlist *data = _data;
+ struct list_head *list;
+
+ ALLOC_LIST(list);
+ ABORT_ON(parse_events_add_breakpoint(list, &data->idx,
+ (void *) $2, NULL, $4));
+ $$ = list;
+}
+|
PE_PREFIX_MEM PE_VALUE ':' PE_MODIFIER_BP sep_dc
{
struct parse_events_evlist *data = _data;
@@ -283,7 +305,7 @@ PE_PREFIX_MEM PE_VALUE ':' PE_MODIFIER_BP sep_dc
ALLOC_LIST(list);
ABORT_ON(parse_events_add_breakpoint(list, &data->idx,
- (void *) $2, $4));
+ (void *) $2, $4, 0));
$$ = list;
}
|
@@ -294,7 +316,7 @@ PE_PREFIX_MEM PE_VALUE sep_dc
ALLOC_LIST(list);
ABORT_ON(parse_events_add_breakpoint(list, &data->idx,
- (void *) $2, NULL));
+ (void *) $2, NULL, 0));
$$ = list;
}
--
1.8.1.2
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 3/4] perf tools: add hardware breakpoint bp_len test cases
2013-12-11 12:28 [PATCH V6 0/4] perf/x86/amd: AMD Family 16h Data Breakpoint Extensions suravee.suthikulpanit
2013-12-11 12:28 ` [PATCH 1/4] perf/x86/amd: AMD support for bp_len > HW_BREAKPOINT_LEN_8 suravee.suthikulpanit
2013-12-11 12:28 ` [PATCH 2/4] perf tools: allow user to specify hardware breakpoint bp_len suravee.suthikulpanit
@ 2013-12-11 12:28 ` suravee.suthikulpanit
2013-12-11 12:28 ` [PATCH 4/4] perf/x86: Remove get_hbp_len and replace with bp_len suravee.suthikulpanit
2014-01-08 19:00 ` [PATCH V6 0/4] perf/x86/amd: AMD Family 16h Data Breakpoint Extensions Suravee Suthikulanit
4 siblings, 0 replies; 11+ messages in thread
From: suravee.suthikulpanit @ 2013-12-11 12:28 UTC (permalink / raw)
To: fweisbec, mingo, mingo, jacob.w.shin
Cc: oleg, a.p.zijlstra, acme, hpa, linux-kernel, sherry.hurwitz,
Suravee Suthikulpanit
From: Jacob Shin <jacob.w.shin@gmail.com>
Signed-off-by: Jacob Shin <jacob.w.shin@gmail.com>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
---
tools/perf/tests/parse-events.c | 55 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 55 insertions(+)
diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-events.c
index 3cbd104..0c5bffc 100644
--- a/tools/perf/tests/parse-events.c
+++ b/tools/perf/tests/parse-events.c
@@ -1114,6 +1114,49 @@ static int test__pinned_group(struct perf_evlist *evlist)
return 0;
}
+static int test__checkevent_breakpoint_len(struct perf_evlist *evlist)
+{
+ struct perf_evsel *evsel = perf_evlist__first(evlist);
+
+ TEST_ASSERT_VAL("wrong number of entries", 1 == evlist->nr_entries);
+ TEST_ASSERT_VAL("wrong type", PERF_TYPE_BREAKPOINT == evsel->attr.type);
+ TEST_ASSERT_VAL("wrong config", 0 == evsel->attr.config);
+ TEST_ASSERT_VAL("wrong bp_type", (HW_BREAKPOINT_R | HW_BREAKPOINT_W) ==
+ evsel->attr.bp_type);
+ TEST_ASSERT_VAL("wrong bp_len", HW_BREAKPOINT_LEN_1 ==
+ evsel->attr.bp_len);
+
+ return 0;
+}
+
+static int test__checkevent_breakpoint_len_w(struct perf_evlist *evlist)
+{
+ struct perf_evsel *evsel = perf_evlist__first(evlist);
+
+ TEST_ASSERT_VAL("wrong number of entries", 1 == evlist->nr_entries);
+ TEST_ASSERT_VAL("wrong type", PERF_TYPE_BREAKPOINT == evsel->attr.type);
+ TEST_ASSERT_VAL("wrong config", 0 == evsel->attr.config);
+ TEST_ASSERT_VAL("wrong bp_type", HW_BREAKPOINT_W ==
+ evsel->attr.bp_type);
+ TEST_ASSERT_VAL("wrong bp_len", HW_BREAKPOINT_LEN_2 ==
+ evsel->attr.bp_len);
+
+ return 0;
+}
+
+static int
+test__checkevent_breakpoint_len_rw_modifier(struct perf_evlist *evlist)
+{
+ struct perf_evsel *evsel = perf_evlist__first(evlist);
+
+ TEST_ASSERT_VAL("wrong exclude_user", !evsel->attr.exclude_user);
+ TEST_ASSERT_VAL("wrong exclude_kernel", evsel->attr.exclude_kernel);
+ TEST_ASSERT_VAL("wrong exclude_hv", evsel->attr.exclude_hv);
+ TEST_ASSERT_VAL("wrong precise_ip", !evsel->attr.precise_ip);
+
+ return test__checkevent_breakpoint_rw(evlist);
+}
+
static int count_tracepoints(void)
{
char events_path[PATH_MAX];
@@ -1346,6 +1389,18 @@ static struct evlist_test test__events[] = {
.name = "{cycles,cache-misses,branch-misses}:D",
.check = test__pinned_group,
},
+ [42] = {
+ .name = "mem:0/1",
+ .check = test__checkevent_breakpoint_len,
+ },
+ [43] = {
+ .name = "mem:0/2:w",
+ .check = test__checkevent_breakpoint_len_w,
+ },
+ [44] = {
+ .name = "mem:0/4:rw:u",
+ .check = test__checkevent_breakpoint_len_rw_modifier,
+ },
};
static struct evlist_test test__events_pmu[] = {
--
1.8.1.2
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 4/4] perf/x86: Remove get_hbp_len and replace with bp_len
2013-12-11 12:28 [PATCH V6 0/4] perf/x86/amd: AMD Family 16h Data Breakpoint Extensions suravee.suthikulpanit
` (2 preceding siblings ...)
2013-12-11 12:28 ` [PATCH 3/4] perf tools: add hardware breakpoint bp_len test cases suravee.suthikulpanit
@ 2013-12-11 12:28 ` suravee.suthikulpanit
2014-01-08 19:00 ` [PATCH V6 0/4] perf/x86/amd: AMD Family 16h Data Breakpoint Extensions Suravee Suthikulanit
4 siblings, 0 replies; 11+ messages in thread
From: suravee.suthikulpanit @ 2013-12-11 12:28 UTC (permalink / raw)
To: fweisbec, mingo, mingo, jacob.w.shin
Cc: oleg, a.p.zijlstra, acme, hpa, linux-kernel, sherry.hurwitz,
Suravee Suthikulpanit
From: Jacob Shin <jacob.w.shin@gmail.com>
Clean up the logic for determining the breakpoint length
Signed-off-by: Jacob Shin <jacob.w.shin@gmail.com>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
---
arch/x86/kernel/hw_breakpoint.c | 25 +------------------------
1 file changed, 1 insertion(+), 24 deletions(-)
diff --git a/arch/x86/kernel/hw_breakpoint.c b/arch/x86/kernel/hw_breakpoint.c
index 647b675..4ada2c3 100644
--- a/arch/x86/kernel/hw_breakpoint.c
+++ b/arch/x86/kernel/hw_breakpoint.c
@@ -169,29 +169,6 @@ void arch_uninstall_hw_breakpoint(struct perf_event *bp)
set_dr_addr_mask(0, i);
}
-static int get_hbp_len(u8 hbp_len)
-{
- unsigned int len_in_bytes = 0;
-
- switch (hbp_len) {
- case X86_BREAKPOINT_LEN_1:
- len_in_bytes = 1;
- break;
- case X86_BREAKPOINT_LEN_2:
- len_in_bytes = 2;
- break;
- case X86_BREAKPOINT_LEN_4:
- len_in_bytes = 4;
- break;
-#ifdef CONFIG_X86_64
- case X86_BREAKPOINT_LEN_8:
- len_in_bytes = 8;
- break;
-#endif
- }
- return len_in_bytes;
-}
-
/*
* Check for virtual address in kernel space.
*/
@@ -202,7 +179,7 @@ int arch_check_bp_in_kernelspace(struct perf_event *bp)
struct arch_hw_breakpoint *info = counter_arch_bp(bp);
va = info->address;
- len = get_hbp_len(info->len);
+ len = bp->attr.bp_len;
return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
}
--
1.8.1.2
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH V6 0/4] perf/x86/amd: AMD Family 16h Data Breakpoint Extensions
2013-12-11 12:28 [PATCH V6 0/4] perf/x86/amd: AMD Family 16h Data Breakpoint Extensions suravee.suthikulpanit
` (3 preceding siblings ...)
2013-12-11 12:28 ` [PATCH 4/4] perf/x86: Remove get_hbp_len and replace with bp_len suravee.suthikulpanit
@ 2014-01-08 19:00 ` Suravee Suthikulanit
2014-01-09 1:52 ` Frederic Weisbecker
4 siblings, 1 reply; 11+ messages in thread
From: Suravee Suthikulanit @ 2014-01-08 19:00 UTC (permalink / raw)
To: fweisbec, mingo, mingo, jacob.w.shin
Cc: oleg, a.p.zijlstra, acme, hpa, linux-kernel, sherry.hurwitz,
Suravee Suthikulpanit
Ping. Are there any other concerns regarding this patch?
Thank you,
Suravee
On 12/11/2013 6:28 AM, suravee.suthikulpanit@amd.com wrote:
> From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
>
> The following patchset enables hardware breakpoint bp_len greater than
> HW_BREAKPOINT_LEN_8 on AMD Family 16h and later.
>
> $ perf stat -e mem:0x1000/16:w a.out
> ^^
> bp_len
>
> This will count writes to [0x1000 ~ 0x1010)
>
> V6:
> * Minor clean up in patch 1 and 2 based on comment from Frederic and Oleg.
> * Split out changes in patch1 into patch4 per Frederic request.
>
> V5:
> * Rebase onto 3.12.0-rc3.
> * Modify the tools/perf/util/parse-events.y due to change in
> parse_events_add_breakpoint().
>
> V4:
> Even more per Oleg's suggestion:
> * Further simplify info->len and info->mask setting switch statement
>
> V3:
> More per Oleg's suggestion:
> * Use already existing bp_len instead of changing userland API and
> in kernel turn bp_len into proper AMD hardware breakpoint address
> mask.
>
> V2:
> Per Oleg's suggestions:
> * Moved testing of bp_addr_mask to validate_hw_breakpoint()
> * Changed perf tool syntax to mem:<addr>[/addr_mask][:access]
>
> Jacob Shin (4):
> perf/x86/amd: AMD support for bp_len > HW_BREAKPOINT_LEN_8
> perf tools: allow user to specify hardware breakpoint bp_len
> perf tools: add hardware breakpoint bp_len test cases
> perf/x86: Remove get_hbp_len and replace with bp_len
>
> arch/x86/include/asm/cpufeature.h | 2 ++
> arch/x86/include/asm/debugreg.h | 5 +++
> arch/x86/include/asm/hw_breakpoint.h | 1 +
> arch/x86/include/uapi/asm/msr-index.h | 4 +++
> arch/x86/kernel/cpu/amd.c | 19 +++++++++++
> arch/x86/kernel/hw_breakpoint.c | 45 ++++++++++----------------
> tools/perf/Documentation/perf-record.txt | 7 ++--
> tools/perf/tests/parse-events.c | 55 ++++++++++++++++++++++++++++++++
> tools/perf/util/parse-events.c | 21 ++++++------
> tools/perf/util/parse-events.h | 2 +-
> tools/perf/util/parse-events.l | 1 +
> tools/perf/util/parse-events.y | 26 +++++++++++++--
> 12 files changed, 145 insertions(+), 43 deletions(-)
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/4] perf/x86/amd: AMD support for bp_len > HW_BREAKPOINT_LEN_8
2013-12-11 12:28 ` [PATCH 1/4] perf/x86/amd: AMD support for bp_len > HW_BREAKPOINT_LEN_8 suravee.suthikulpanit
@ 2014-01-09 1:24 ` Frederic Weisbecker
0 siblings, 0 replies; 11+ messages in thread
From: Frederic Weisbecker @ 2014-01-09 1:24 UTC (permalink / raw)
To: suravee.suthikulpanit
Cc: mingo, mingo, jacob.w.shin, oleg, a.p.zijlstra, acme, hpa,
linux-kernel, sherry.hurwitz
On Wed, Dec 11, 2013 at 06:28:23AM -0600, suravee.suthikulpanit@amd.com wrote:
> @@ -295,11 +301,17 @@ static int arch_build_bp_info(struct perf_event *bp)
> break;
> #endif
> default:
> - return -EINVAL;
> + if (!is_power_of_2(bp->attr.bp_len))
> + return -EINVAL;
> + if (!cpu_has_bpext)
> + return -EOPNOTSUPP;
> + info->mask = bp->attr.bp_len - 1;
> + info->len = X86_BREAKPOINT_LEN_1;
I think I asked this before but I can't remember. So dr7 must have
length as LEN_1 for breakpoint extension?
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V6 0/4] perf/x86/amd: AMD Family 16h Data Breakpoint Extensions
2014-01-08 19:00 ` [PATCH V6 0/4] perf/x86/amd: AMD Family 16h Data Breakpoint Extensions Suravee Suthikulanit
@ 2014-01-09 1:52 ` Frederic Weisbecker
2014-02-25 15:09 ` Suravee Suthikulanit
0 siblings, 1 reply; 11+ messages in thread
From: Frederic Weisbecker @ 2014-01-09 1:52 UTC (permalink / raw)
To: Suravee Suthikulanit
Cc: mingo, mingo, jacob.w.shin, oleg, a.p.zijlstra, acme, hpa,
linux-kernel, sherry.hurwitz
Hi Suravee,
On Wed, Jan 08, 2014 at 01:00:36PM -0600, Suravee Suthikulanit wrote:
> Ping. Are there any other concerns regarding this patch?
>
> Thank you,
>
> Suravee
The patches look good. I'll apply the series and propose it to the perf maintainers.
Thanks!
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V6 0/4] perf/x86/amd: AMD Family 16h Data Breakpoint Extensions
2014-01-09 1:52 ` Frederic Weisbecker
@ 2014-02-25 15:09 ` Suravee Suthikulanit
2014-02-25 15:49 ` Frederic Weisbecker
0 siblings, 1 reply; 11+ messages in thread
From: Suravee Suthikulanit @ 2014-02-25 15:09 UTC (permalink / raw)
To: Frederic Weisbecker
Cc: mingo, mingo, jacob.w.shin, oleg, a.p.zijlstra, acme, hpa,
linux-kernel, Hurwitz, Sherry
On 1/8/2014 7:52 PM, Frederic Weisbecker wrote:
> This message has been archived. View the original item
> <http://ausev2.amd.com/EnterpriseVault/ViewMessage.asp?VaultId=1EBD12133601C6E47868220A36CFE2B201110000amdvault.amd.com&SavesetId=201402081892875~201401090153030000~Z~D12198340FA0E3A8078F6DDADF1DAC51>
> Hi Suravee,
>
> On Wed, Jan 08, 2014 at 01:00:36PM -0600, Suravee Suthikulanit wrote:
> > Ping. Are there any other concerns regarding this patch?
> >
> > Thank you,
> >
> > Suravee
>
> The patches look good. I'll apply the series and propose it to the perf
> maintainers.
>
> Thanks!
>
Frederic,
I am following up with this patch set.
Suravee
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V6 0/4] perf/x86/amd: AMD Family 16h Data Breakpoint Extensions
2014-02-25 15:09 ` Suravee Suthikulanit
@ 2014-02-25 15:49 ` Frederic Weisbecker
2014-04-28 23:01 ` Suravee Suthikulanit
0 siblings, 1 reply; 11+ messages in thread
From: Frederic Weisbecker @ 2014-02-25 15:49 UTC (permalink / raw)
To: Suravee Suthikulanit
Cc: mingo, mingo, jacob.w.shin, oleg, a.p.zijlstra, acme, hpa,
linux-kernel, Hurwitz, Sherry
On Tue, Feb 25, 2014 at 09:09:29AM -0600, Suravee Suthikulanit wrote:
> On 1/8/2014 7:52 PM, Frederic Weisbecker wrote:
> >This message has been archived. View the original item
> ><http://ausev2.amd.com/EnterpriseVault/ViewMessage.asp?VaultId=1EBD12133601C6E47868220A36CFE2B201110000amdvault.amd.com&SavesetId=201402081892875~201401090153030000~Z~D12198340FA0E3A8078F6DDADF1DAC51>
> >Hi Suravee,
> >
> >On Wed, Jan 08, 2014 at 01:00:36PM -0600, Suravee Suthikulanit wrote:
> > > Ping. Are there any other concerns regarding this patch?
> > >
> > > Thank you,
> > >
> > > Suravee
> >
> >The patches look good. I'll apply the series and propose it to the perf
> >maintainers.
> >
> >Thanks!
> >
>
> Frederic,
>
> I am following up with this patch set.
Thanks for the reminder. I'm applying this right now and will propose for 3.15.
Thanks.
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V6 0/4] perf/x86/amd: AMD Family 16h Data Breakpoint Extensions
2014-02-25 15:49 ` Frederic Weisbecker
@ 2014-04-28 23:01 ` Suravee Suthikulanit
0 siblings, 0 replies; 11+ messages in thread
From: Suravee Suthikulanit @ 2014-04-28 23:01 UTC (permalink / raw)
To: Frederic Weisbecker
Cc: mingo, mingo, jacob.w.shin, oleg, a.p.zijlstra, acme, hpa,
linux-kernel, Hurwitz, Sherry
On 2/25/2014 9:49 AM, Frederic Weisbecker wrote:
> This message has been archived. View the original item
> <http://ausev2.amd.com/EnterpriseVault/ViewMessage.asp?VaultId=1EBD12133601C6E47868220A36CFE2B201110000amdvault.amd.com&SavesetId=201403275961891~201402251548080000~Z~F07F5E04B0F823C085F9DFEECF2BA521>
> On Tue, Feb 25, 2014 at 09:09:29AM -0600, Suravee Suthikulanit wrote:
> > On 1/8/2014 7:52 PM, Frederic Weisbecker wrote:
> > >This message has been archived. View the original item
> >
> ><http://ausev2.amd.com/EnterpriseVault/ViewMessage.asp?VaultId=1EBD12133601C6E47868220A36CFE2B201110000amdvault.amd.com&SavesetId=201402081892875~201401090153030000~Z~D12198340FA0E3A8078F6DDADF1DAC51>
> > >Hi Suravee,
> > >
> > >On Wed, Jan 08, 2014 at 01:00:36PM -0600, Suravee Suthikulanit wrote:
> > > > Ping. Are there any other concerns regarding this patch?
> > > >
> > > > Thank you,
> > > >
> > > > Suravee
> > >
> > >The patches look good. I'll apply the series and propose it to the perf
> > >maintainers.
> > >
> > >Thanks!
> > >
> >
> > Frederic,
> >
> > I am following up with this patch set.
>
> Thanks for the reminder. I'm applying this right now and will propose
> for 3.15.
>
> Thanks.
>
Frederic,
I am still not seeing these patch set in the 3.15.0-rc3. Are you still
planning to include this in the 3.15?
Thanks,
Suravee
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2014-04-28 23:16 UTC | newest]
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-- links below jump to the message on this page --
2013-12-11 12:28 [PATCH V6 0/4] perf/x86/amd: AMD Family 16h Data Breakpoint Extensions suravee.suthikulpanit
2013-12-11 12:28 ` [PATCH 1/4] perf/x86/amd: AMD support for bp_len > HW_BREAKPOINT_LEN_8 suravee.suthikulpanit
2014-01-09 1:24 ` Frederic Weisbecker
2013-12-11 12:28 ` [PATCH 2/4] perf tools: allow user to specify hardware breakpoint bp_len suravee.suthikulpanit
2013-12-11 12:28 ` [PATCH 3/4] perf tools: add hardware breakpoint bp_len test cases suravee.suthikulpanit
2013-12-11 12:28 ` [PATCH 4/4] perf/x86: Remove get_hbp_len and replace with bp_len suravee.suthikulpanit
2014-01-08 19:00 ` [PATCH V6 0/4] perf/x86/amd: AMD Family 16h Data Breakpoint Extensions Suravee Suthikulanit
2014-01-09 1:52 ` Frederic Weisbecker
2014-02-25 15:09 ` Suravee Suthikulanit
2014-02-25 15:49 ` Frederic Weisbecker
2014-04-28 23:01 ` Suravee Suthikulanit
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