[PATCHv4 0/7] Support new Exynos3250 SoC based on Cortex-A7 dual core

[PATCHv4 0/7] Support new Exynos3250 SoC based on Cortex-A7 dual core

[Chanwoo Choi]

This patchset support new Exynos3250 Samsung SoC based on Cortex-A7 dual core.
Exynos3250 is a System-On-Chip (SoC) that is based on 32-bit RISC processor
for Smartphone. It is desigend with the 28nm low-power high-K metal gate process
and provides the best performance features.

This patchset include some patches such as:
- Support booting of Exynos3250
- Supoort uart/mct/adc/gic/i2c/spi/power-domain/pmu/mshc/pwm/amba
- Support the clock control for Exynos3250 using common clk framework

[Pinctrl patch for Exynos3250]
The pinctrl patch for Exynos3250 has been merged in pinctrl.git of Linus Walleij
- [1] https://lkml.org/lkml/2014/4/23/72

This patchset is based on following git repo/branch.
- git repo : git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
- branch   : for-next (Linux 3.15-rc1)

Changes from v3:
- Remove all dependency about following patchset to remove static memory
  mapping for SYSRAM[1] / PMU ([2] or [3]). If following patchset merged,
  I'll send a further patches to support SYSRAM/PMU for secondary CPU.
 [1] http://www.spinics.net/lists/arm-kernel/msg323011.html
 [2] https://lkml.org/lkml/2014/4/2/48
 [3] http://www.spinics.net/lists/arm-kernel/msg316013.html

Changes from v2:
- Remove static memory mapping about SYSRAM/PMU such as following patches:
  ARM: EXYNOS: Add IO mapping for non-secure SYSRAM of Exynos3250
  ARM: EXYNOS: Add IO mapping for PMU of Exynos3250
- Add description for secondary CPU boot of Exynos4212/Exynos3250
- Fix description in exynos_cpu_die() to remove particular SoC series
- Fix minor coding style
- Add documentation for Exynos3250 clock controller

Changes from v1:
- Add new "samsung,exynos3" compatible name
- Add comment about exynos_cpu_boot in Exynos4212
- Remove unnecessary 'goto' statement in firmware.c
- Use read_cpuid_part_number() function instead of assembler directly
- Post separated pinctrl patch from this patchset
  : https://lkml.org/lkml/2014/4/13/156
- Remove unused pmu interrupts due to Exynos3250 dual-core
- Cosolidate all the patches related to exynos3250.dtsi into one patch
- Fix gic compatible name to "cortex-a15-gic" because Cortex-A7 GIC is same
- Add sign-off of sender to all this patches
- Fix minor typo

Chanwoo Choi (4):
  ARM: EXYNOS: Add Exynos3250 SoC ID
  ARM: EXYNOS: Support secondary CPU boot of Exynos3250
  ARM: EXYNOS: Enter a15 lowpower mode for Exynos3250 based on Cortex-a7
  dt-bindings: add documentation for Exynos3250 clock controller

Kyungmin Park (1):
  ARM: EXYNOS: Support secondary CPU boot of Exynos4212

Tomasz Figa (2):
  clk: samsung: exynos3250: Add clocks using common clock framework
  ARM: dts: Add device tree sources for Exynos3250

 .../devicetree/bindings/clock/exynos3250-clock.txt |  41 +
 arch/arm/boot/dts/exynos3250-pinctrl.dtsi          | 477 +++++++++++
 arch/arm/boot/dts/exynos3250.dtsi                  | 405 +++++++++
 arch/arm/boot/dts/exynos4212-tizenw.dts            | 926 +++++++++++++++++++++
 arch/arm/mach-exynos/Kconfig                       |  22 +
 arch/arm/mach-exynos/exynos.c                      |   2 +
 arch/arm/mach-exynos/firmware.c                    |  21 +-
 arch/arm/mach-exynos/hotplug.c                     |  19 +-
 arch/arm/plat-samsung/include/plat/cpu.h           |  10 +
 drivers/clk/samsung/Makefile                       |   1 +
 drivers/clk/samsung/clk-exynos3250.c               | 785 +++++++++++++++++
 include/dt-bindings/clock/exynos3250.h             | 256 ++++++
 12 files changed, 2957 insertions(+), 8 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/exynos3250-clock.txt
 create mode 100644 arch/arm/boot/dts/exynos3250-pinctrl.dtsi
 create mode 100644 arch/arm/boot/dts/exynos3250.dtsi
 create mode 100644 arch/arm/boot/dts/exynos4212-tizenw.dts
 create mode 100644 drivers/clk/samsung/clk-exynos3250.c
 create mode 100644 include/dt-bindings/clock/exynos3250.h

-- 
1.8.0

[PATCHv4 1/7] ARM: EXYNOS: Add Exynos3250 SoC ID

[Chanwoo Choi]

This patch add Exynos3250's SoC ID. Exynos 3250 is System-On-Chip(SoC) that
is based on the 32-bit RISC processor for Smartphone. Exynos3250 uses Cortex-A7
dual cores and has a target speed of 1.0GHz.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 arch/arm/mach-exynos/Kconfig             | 22 ++++++++++++++++++++++
 arch/arm/mach-exynos/exynos.c            |  2 ++
 arch/arm/plat-samsung/include/plat/cpu.h | 10 ++++++++++
 3 files changed, 34 insertions(+)

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index fc8bf18..6da8a68 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -11,6 +11,17 @@ if ARCH_EXYNOS
 
 menu "SAMSUNG EXYNOS SoCs Support"
 
+config ARCH_EXYNOS3
+	bool "SAMSUNG EXYNOS3"
+	select ARM_AMBA
+	select CLKSRC_OF
+	select HAVE_ARM_SCU if SMP
+	select HAVE_SMP
+	select PINCTRL
+	select PM_GENERIC_DOMAINS if PM_RUNTIME
+	help
+	  Samsung EXYNOS3 SoCs based systems
+
 config ARCH_EXYNOS4
 	bool "SAMSUNG EXYNOS4"
 	default y
@@ -41,6 +52,17 @@ config ARCH_EXYNOS5
 
 comment "EXYNOS SoCs"
 
+config SOC_EXYNOS3250
+	bool "SAMSUNG EXYNOS3250"
+	default y
+	depends on ARCH_EXYNOS3
+	select ARCH_HAS_BANDGAP
+	select ARM_CPU_SUSPEND if PM
+	select PINCTRL_EXYNOS
+	select SAMSUNG_DMADEV
+	help
+	  Enable EXYNOS3250 CPU support
+
 config CPU_EXYNOS4210
 	bool "SAMSUNG EXYNOS4210"
 	default y
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 6a5fe18..e7dc6fd 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -346,6 +346,8 @@ static void __init exynos_dt_machine_init(void)
 }
 
 static char const *exynos_dt_compat[] __initconst = {
+	"samsung,exynos3",
+	"samsung,exynos3250",
 	"samsung,exynos4",
 	"samsung,exynos4210",
 	"samsung,exynos4212",
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 5992b8d..3d808f6b 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -43,6 +43,9 @@ extern unsigned long samsung_cpu_id;
 #define S5PV210_CPU_ID		0x43110000
 #define S5PV210_CPU_MASK	0xFFFFF000
 
+#define EXYNOS3250_SOC_ID       0xE3472000
+#define EXYNOS3_SOC_MASK        0xFFFFF000
+
 #define EXYNOS4210_CPU_ID	0x43210000
 #define EXYNOS4212_CPU_ID	0x43220000
 #define EXYNOS4412_CPU_ID	0xE4412200
@@ -68,6 +71,7 @@ IS_SAMSUNG_CPU(s5p6440, S5P6440_CPU_ID, S5P64XX_CPU_MASK)
 IS_SAMSUNG_CPU(s5p6450, S5P6450_CPU_ID, S5P64XX_CPU_MASK)
 IS_SAMSUNG_CPU(s5pc100, S5PC100_CPU_ID, S5PC100_CPU_MASK)
 IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
+IS_SAMSUNG_CPU(exynos3250, EXYNOS3250_SOC_ID, EXYNOS3_SOC_MASK)
 IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
 IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
 IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
@@ -126,6 +130,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
 # define soc_is_s5pv210()	0
 #endif
 
+#if defined(CONFIG_SOC_EXYNOS3250)
+# define soc_is_exynos3250()    is_samsung_exynos3250()
+#else
+# define soc_is_exynos3250()    0
+#endif
+
 #if defined(CONFIG_CPU_EXYNOS4210)
 # define soc_is_exynos4210()	is_samsung_exynos4210()
 #else
-- 
1.8.0

[PATCHv4 2/7] ARM: EXYNOS: Support secondary CPU boot of Exynos4212

[Chanwoo Choi]

From: Kyungmin Park <kyungmin.park@samsung.com>

This patch fix the offset of CPU boot address and change parameter of smc call
of SMC_CMD_CPU1BOOT command for Exynos4212.

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 arch/arm/mach-exynos/firmware.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index 932129e..aa01c42 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -18,6 +18,8 @@
 
 #include <mach/map.h>
 
+#include <plat/cpu.h>
+
 #include "smc.h"
 
 static int exynos_do_idle(void)
@@ -28,13 +30,24 @@ static int exynos_do_idle(void)
 
 static int exynos_cpu_boot(int cpu)
 {
+	/*
+	 * The second parameter of SMC_CMD_CPU1BOOT command means CPU id.
+	 * But, Exynos4212 has only one secondary CPU so second parameter
+	 * isn't used for informing secure firmware about CPU id.
+	 */
+	if (soc_is_exynos4212())
+		cpu = 0;
+
 	exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
 	return 0;
 }
 
 static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
 {
-	void __iomem *boot_reg = S5P_VA_SYSRAM_NS + 0x1c + 4*cpu;
+	void __iomem *boot_reg = S5P_VA_SYSRAM_NS + 0x1c;
+
+	if (!soc_is_exynos4212())
+		boot_reg += 4*cpu;
 
 	__raw_writel(boot_addr, boot_reg);
 	return 0;
-- 
1.8.0

[PATCHv4 3/7] ARM: EXYNOS: Support secondary CPU boot of Exynos3250

[Chanwoo Choi]

This patch fix the offset of CPU boot address and don't need to send smc call
of SMC_CMD_CPU1BOOT command for secondary CPU boot because Exynos3250 removes
WFE in secure mode.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 arch/arm/mach-exynos/firmware.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index aa01c42..386d01d 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -31,11 +31,17 @@ static int exynos_do_idle(void)
 static int exynos_cpu_boot(int cpu)
 {
 	/*
+	 * Exynos3250 doesn't need to send smc command for secondary CPU boot
+	 * because Exynos3250 removes WFE in secure mode.
+	 */
+	if (soc_is_exynos3250())
+		return 0;
+	/*
 	 * The second parameter of SMC_CMD_CPU1BOOT command means CPU id.
 	 * But, Exynos4212 has only one secondary CPU so second parameter
 	 * isn't used for informing secure firmware about CPU id.
 	 */
-	if (soc_is_exynos4212())
+	else if (soc_is_exynos4212())
 		cpu = 0;
 
 	exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
@@ -46,7 +52,7 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
 {
 	void __iomem *boot_reg = S5P_VA_SYSRAM_NS + 0x1c;
 
-	if (!soc_is_exynos4212())
+	if (!soc_is_exynos4212() && !soc_is_exynos3250())
 		boot_reg += 4*cpu;
 
 	__raw_writel(boot_addr, boot_reg);
-- 
1.8.0

[PATCHv4 4/7] ARM: EXYNOS: Enter a15 lowpower mode for Exynos3250 based on Cortex-a7

[Chanwoo Choi]

This patch decide proper lowpower mode of either a15 or a9 according to own ID
from Main ID register.

Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Marc Zynigier <marc.zyngier@arm.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 arch/arm/mach-exynos/hotplug.c | 19 ++++++++++++-------
 1 file changed, 12 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index 5eead53..acf3119 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -135,16 +135,21 @@ void __ref exynos_cpu_die(unsigned int cpu)
 	int primary_part = 0;
 
 	/*
-	 * we're ready for shutdown now, so do it.
-	 * Exynos4 is A9 based while Exynos5 is A15; check the CPU part
-	 * number by reading the Main ID register and then perform the
-	 * appropriate sequence for entering low power.
+	 * Prepare the CPU for shutting down. The required sequence of
+	 * operations depends on core type. CPUID part number can be used to
+	 * determine the right way.
 	 */
-	asm("mrc p15, 0, %0, c0, c0, 0" : "=r"(primary_part) : : "cc");
-	if ((primary_part & 0xfff0) == 0xc0f0)
+	primary_part = read_cpuid_part_number();
+
+	switch (primary_part) {
+	case ARM_CPU_PART_CORTEX_A7:
+	case ARM_CPU_PART_CORTEX_A15:
 		cpu_enter_lowpower_a15();
-	else
+		break;
+	default:
 		cpu_enter_lowpower_a9();
+		break;
+	}
 
 	platform_do_lowpower(cpu, &spurious);
 
-- 
1.8.0

[PATCHv4 5/7] clk: samsung: exynos3250: Add clocks using common clock framework

[Chanwoo Choi]

From: Tomasz Figa <t.figa@samsung.com>

This patch add new the clock drvier of Exynos3250 SoC based on Cortex-A7
using common clock framework. The CMU (Clock Management Unit) of Exynos3250
control PLLs(Phase Locked Loops) and generate system clocks for CPU, buses,
and function clocks for individual IPs.

The CMU of Exynos3250 includes following clock doamins:
- CPU block for Cortex-A7 MPCore processor
- LEFTBUS/RIGHTBUS block
- TOP block for G3D/MFC/LCD0/ISP/CAM/FSYS/MFC/PERIL/PERIR

Cc: Mike Turquette <mturquette@linaro.org>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Hyunhee Kim <hyunhee.kim@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Karol Wrona <k.wrona@samsung.com>
Signed-off-by: YoungJun Cho <yj44.cho@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 drivers/clk/samsung/Makefile           |   1 +
 drivers/clk/samsung/clk-exynos3250.c   | 785 +++++++++++++++++++++++++++++++++
 include/dt-bindings/clock/exynos3250.h | 256 +++++++++++
 3 files changed, 1042 insertions(+)
 create mode 100644 drivers/clk/samsung/clk-exynos3250.c
 create mode 100644 include/dt-bindings/clock/exynos3250.h

diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 8eb4799..d120797 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -3,6 +3,7 @@
 #
 
 obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-pll.o
+obj-$(CONFIG_SOC_EXYNOS3250)	+= clk-exynos3250.o
 obj-$(CONFIG_ARCH_EXYNOS4)	+= clk-exynos4.o
 obj-$(CONFIG_SOC_EXYNOS5250)	+= clk-exynos5250.o
 obj-$(CONFIG_SOC_EXYNOS5420)	+= clk-exynos5420.o
diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
new file mode 100644
index 0000000..0574a76
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos3250.c
@@ -0,0 +1,785 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos3250 SoC.
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/syscore_ops.h>
+
+#include <dt-bindings/clock/exynos3250.h>
+
+#include "clk.h"
+#include "clk-pll.h"
+
+#define SRC_LEFTBUS		0x4200
+#define DIV_LEFTBUS		0x4500
+#define GATE_IP_LEFTBUS		0x4800
+#define SRC_RIGHTBUS		0x8200
+#define DIV_RIGHTBUS		0x8500
+#define GATE_IP_RIGHTBUS	0x8800
+#define GATE_IP_PERIR		0x8960
+#define MPLL_LOCK		0xc010
+#define MPLL_CON0		0xc110
+#define VPLL_LOCK		0xc020
+#define VPLL_CON0		0xc120
+#define UPLL_LOCK		0xc030
+#define UPLL_CON0		0xc130
+#define SRC_TOP0		0xc210
+#define SRC_TOP1		0xc214
+#define SRC_CAM			0xc220
+#define SRC_MFC			0xc228
+#define SRC_G3D			0xc22c
+#define SRC_LCD			0xc234
+#define SRC_ISP			0xc238
+#define SRC_FSYS		0xc240
+#define SRC_PERIL0		0xc250
+#define SRC_PERIL1		0xc254
+#define SRC_MASK_TOP		0xc310
+#define SRC_MASK_CAM		0xc320
+#define SRC_MASK_LCD		0xc334
+#define SRC_MASK_ISP		0xc338
+#define SRC_MASK_FSYS		0xc340
+#define SRC_MASK_PERIL0		0xc350
+#define SRC_MASK_PERIL1		0xc354
+#define DIV_TOP			0xc510
+#define DIV_CAM			0xc520
+#define DIV_MFC			0xc528
+#define DIV_G3D			0xc52c
+#define DIV_LCD			0xc534
+#define DIV_ISP			0xc538
+#define DIV_FSYS0		0xc540
+#define DIV_FSYS1		0xc544
+#define DIV_FSYS2		0xc548
+#define DIV_PERIL0		0xc550
+#define DIV_PERIL1		0xc554
+#define DIV_PERIL3		0xc55c
+#define DIV_PERIL4		0xc560
+#define DIV_PERIL5		0xc564
+#define DIV_CAM1		0xc568
+#define CLKDIV2_RATIO		0xc580
+#define GATE_SCLK_CAM		0xc820
+#define GATE_SCLK_MFC		0xc828
+#define GATE_SCLK_G3D		0xc82c
+#define GATE_SCLK_LCD		0xc834
+#define GATE_SCLK_ISP_TOP	0xc838
+#define GATE_SCLK_FSYS		0xc840
+#define GATE_SCLK_PERIL		0xc850
+#define GATE_IP_CAM		0xc920
+#define GATE_IP_MFC		0xc928
+#define GATE_IP_G3D		0xc92c
+#define GATE_IP_LCD		0xc934
+#define GATE_IP_ISP		0xc938
+#define GATE_IP_FSYS		0xc940
+#define GATE_IP_PERIL		0xc950
+#define GATE_BLOCK		0xc970
+#define APLL_LOCK		0x14000
+#define APLL_CON0		0x14100
+#define SRC_CPU			0x14200
+#define DIV_CPU0		0x14500
+#define DIV_CPU1		0x14504
+
+/* list of PLLs to be registered */
+enum exynos3250_plls {
+	apll, mpll, vpll, upll,
+	nr_plls
+};
+
+void __iomem *reg_base;
+
+/*
+ * Support for CMU save/restore across system suspends
+ */
+#ifdef CONFIG_PM_SLEEP
+static struct samsung_clk_reg_dump *exynos3250_clk_regs;
+
+static unsigned long exynos3250_cmu_clk_regs[] __initdata = {
+	SRC_LEFTBUS,
+	DIV_LEFTBUS,
+	GATE_IP_LEFTBUS,
+	SRC_RIGHTBUS,
+	DIV_RIGHTBUS,
+	GATE_IP_RIGHTBUS,
+	GATE_IP_PERIR,
+	MPLL_LOCK,
+	MPLL_CON0,
+	VPLL_LOCK,
+	VPLL_CON0,
+	UPLL_LOCK,
+	UPLL_CON0,
+	SRC_TOP0,
+	SRC_TOP1,
+	SRC_CAM,
+	SRC_MFC,
+	SRC_G3D,
+	SRC_LCD,
+	SRC_ISP,
+	SRC_FSYS,
+	SRC_PERIL0,
+	SRC_PERIL1,
+	SRC_MASK_TOP,
+	SRC_MASK_CAM,
+	SRC_MASK_LCD,
+	SRC_MASK_ISP,
+	SRC_MASK_FSYS,
+	SRC_MASK_PERIL0,
+	SRC_MASK_PERIL1,
+	DIV_TOP,
+	DIV_CAM,
+	DIV_MFC,
+	DIV_G3D,
+	DIV_LCD,
+	DIV_ISP,
+	DIV_FSYS0,
+	DIV_FSYS1,
+	DIV_FSYS2,
+	DIV_PERIL0,
+	DIV_PERIL1,
+	DIV_PERIL3,
+	DIV_PERIL4,
+	DIV_PERIL5,
+	DIV_CAM1,
+	CLKDIV2_RATIO,
+	GATE_SCLK_CAM,
+	GATE_SCLK_MFC,
+	GATE_SCLK_G3D,
+	GATE_SCLK_LCD,
+	GATE_SCLK_ISP_TOP,
+	GATE_SCLK_FSYS,
+	GATE_SCLK_PERIL,
+	GATE_IP_CAM,
+	GATE_IP_MFC,
+	GATE_IP_G3D,
+	GATE_IP_LCD,
+	GATE_IP_ISP,
+	GATE_IP_FSYS,
+	GATE_IP_PERIL,
+	GATE_BLOCK,
+	APLL_LOCK,
+	SRC_CPU,
+	DIV_CPU0,
+	DIV_CPU1,
+};
+
+static int exynos3250_clk_suspend(void)
+{
+	samsung_clk_save(reg_base, exynos3250_clk_regs,
+				ARRAY_SIZE(exynos3250_cmu_clk_regs));
+	return 0;
+}
+
+static void exynos3250_clk_resume(void)
+{
+	samsung_clk_restore(reg_base, exynos3250_clk_regs,
+				ARRAY_SIZE(exynos3250_cmu_clk_regs));
+}
+
+static struct syscore_ops exynos3250_clk_syscore_ops = {
+	.suspend = exynos3250_clk_suspend,
+	.resume = exynos3250_clk_resume,
+};
+
+static void exynos3250_clk_sleep_init(void)
+{
+	exynos3250_clk_regs =
+		samsung_clk_alloc_reg_dump(exynos3250_cmu_clk_regs,
+					   ARRAY_SIZE(exynos3250_cmu_clk_regs));
+	if (!exynos3250_clk_regs) {
+		pr_warn("%s: Failed to allocate sleep save data\n", __func__);
+		goto err;
+	}
+
+	register_syscore_ops(&exynos3250_clk_syscore_ops);
+	return;
+err:
+	kfree(exynos3250_clk_regs);
+}
+#else
+static inline void exynos3250_clk_sleep_init(void) { }
+#endif
+
+/* list of all parent clock list */
+PNAME(mout_vpllsrc_p)		= { "fin_pll", };
+
+PNAME(mout_apll_p)		= { "fin_pll", "fout_apll", };
+PNAME(mout_mpll_p)		= { "fin_pll", "fout_mpll", };
+PNAME(mout_vpll_p)		= { "fin_pll", "fout_vpll", };
+PNAME(mout_upll_p)		= { "fin_pll", "fout_upll", };
+
+PNAME(mout_mpll_user_p)		= { "fin_pll", "div_mpll_pre", };
+PNAME(mout_epll_user_p)		= { "fin_pll", "mout_epll", };
+PNAME(mout_core_p)		= { "mout_apll", "mout_mpll_user_c", };
+PNAME(mout_hpm_p)		= { "mout_apll", "mout_mpll_user_c", };
+
+PNAME(mout_ebi_p)		= { "div_aclk_200", "div_aclk_160", };
+PNAME(mout_ebi_1_p)		= { "mout_ebi", "mout_vpll", };
+
+PNAME(mout_gdl_p)		= { "mout_mpll_user_l", };
+PNAME(mout_gdr_p)		= { "mout_mpll_user_r", };
+
+PNAME(mout_aclk_400_mcuisp_sub_p)
+				= { "fin_pll", "div_aclk_400_mcuisp", };
+PNAME(mout_aclk_266_0_p)	= { "div_mpll_pre", "mout_vpll", };
+PNAME(mout_aclk_266_1_p)	= { "mout_epll_user", };
+PNAME(mout_aclk_266_p)		= { "mout_aclk_266_0", "mout_aclk_266_1", };
+PNAME(mout_aclk_266_sub_p)	= { "fin_pll", "div_aclk_266", };
+
+PNAME(group_div_mpll_pre_p)	= { "div_mpll_pre", };
+PNAME(group_epll_vpll_p)	= { "mout_epll_user", "mout_vpll" };
+PNAME(group_sclk_p)		= { "xxti", "xusbxti",
+				    "none", "none",
+				    "none", "none", "div_mpll_pre",
+				    "mout_epll_user", "mout_vpll", };
+PNAME(group_sclk_audio_p)	= { "audiocdclk", "none",
+				    "none", "none",
+				    "xxti", "xusbxti",
+				    "div_mpll_pre", "mout_epll_user",
+				    "mout_vpll", };
+PNAME(group_sclk_cam_blk_p)	= { "xxti", "xusbxti",
+				    "none", "none", "none",
+				    "none", "div_mpll_pre",
+				    "mout_epll_user", "mout_vpll",
+				    "div_cam_blk_320", };
+PNAME(group_sclk_fimd0_p)	= { "xxti", "xusbxti",
+				    "m_bitclkhsdiv4_2l", "none",
+				    "none", "none", "div_mpll_pre",
+				    "mout_epll_user", "mout_vpll",
+				    "none", "none", "none",
+				    "div_lcd_blk_145", };
+
+PNAME(mout_mfc_p)		= { "mout_mfc_0", "mout_mfc_1" };
+PNAME(mout_g3d_p)		= { "mout_g3d_0", "mout_g3d_1" };
+
+static struct samsung_fixed_rate_clock fixed_rate_clks[] __initdata = {
+};
+
+static struct samsung_fixed_factor_clock fixed_factor_clks[] __initdata = {
+	FFACTOR(0, "sclk_mpll_1600", "mout_mpll", 1, 1, 0),
+	FFACTOR(0, "sclk_mpll_mif", "mout_mpll", 1, 2, 0),
+	FFACTOR(0, "sclk_bpll", "fout_bpll", 1, 2, 0),
+	FFACTOR(0, "div_cam_blk_320", "sclk_mpll_1600", 1, 5, 0),
+	FFACTOR(0, "div_lcd_blk_145", "sclk_mpll_1600", 1, 11, 0),
+
+	FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0),
+};
+
+static struct samsung_mux_clock mux_clks[] __initdata = {
+	/*
+	 * NOTE: Following table is sorted by register address in ascending
+	 * order and then bitfield shift in descending order, as it is done
+	 * in the User's Manual. When adding new entries, please make sure
+	 * that the order is preserved, to avoid merge conflicts and make
+	 * further work with defined data easier.
+	 */
+
+	/* SRC_LEFTBUS */
+	MUX(CLK_MOUT_MPLL_USER_L, "mout_mpll_user_l", mout_mpll_user_p,
+	    SRC_LEFTBUS, 4, 1),
+	MUX(CLK_MOUT_GDL, "mout_gdl", mout_gdl_p, SRC_LEFTBUS, 0, 1),
+
+	/* SRC_RIGHTBUS */
+	MUX(CLK_MOUT_MPLL_USER_R, "mout_mpll_user_r", mout_mpll_user_p,
+	    SRC_RIGHTBUS, 4, 1),
+	MUX(CLK_MOUT_GDR, "mout_gdr", mout_gdr_p, SRC_RIGHTBUS, 0, 1),
+
+	/* SRC_TOP0 */
+	MUX(CLK_MOUT_EBI, "mout_ebi", mout_ebi_p, SRC_TOP0, 28, 1),
+	MUX(CLK_MOUT_ACLK_200, "mout_aclk_200", group_div_mpll_pre_p,SRC_TOP0, 24, 1),
+	MUX(CLK_MOUT_ACLK_160, "mout_aclk_160", group_div_mpll_pre_p, SRC_TOP0, 20, 1),
+	MUX(CLK_MOUT_ACLK_100, "mout_aclk_100", group_div_mpll_pre_p, SRC_TOP0, 16, 1),
+	MUX(CLK_MOUT_ACLK_266_1, "mout_aclk_266_1", mout_aclk_266_1_p, SRC_TOP0, 14, 1),
+	MUX(CLK_MOUT_ACLK_266_0, "mout_aclk_266_0", mout_aclk_266_0_p, SRC_TOP0, 13, 1),
+	MUX(CLK_MOUT_ACLK_266, "mout_aclk_266", mout_aclk_266_p, SRC_TOP0, 12, 1),
+	MUX(CLK_MOUT_VPLL, "mout_vpll", mout_vpll_p, SRC_TOP0, 8, 1),
+	MUX(CLK_MOUT_EPLL_USER, "mout_epll_user", mout_epll_user_p, SRC_TOP0, 4, 1),
+	MUX(CLK_MOUT_EBI_1, "mout_ebi_1", mout_ebi_1_p, SRC_TOP0, 0, 1),
+
+	/* SRC_TOP1 */
+	MUX(CLK_MOUT_UPLL, "mout_upll", mout_upll_p, SRC_TOP1, 28, 1),
+	MUX(CLK_MOUT_ACLK_400_MCUISP_SUB, "mout_aclk_400_mcuisp_sub", mout_aclk_400_mcuisp_sub_p,
+		SRC_TOP1, 24, 1),
+	MUX(CLK_MOUT_ACLK_266_SUB, "mout_aclk_266_sub", mout_aclk_266_sub_p, SRC_TOP1, 20, 1),
+	MUX(CLK_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_TOP1, 12, 1),
+	MUX(CLK_MOUT_ACLK_400_MCUISP, "mout_aclk_400_mcuisp", group_div_mpll_pre_p, SRC_TOP1, 8, 1),
+	MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
+
+	/* SRC_CAM */
+	MUX(CLK_MOUT_CAM1, "mout_cam1", group_sclk_p, SRC_CAM, 20, 4),
+	MUX(CLK_MOUT_CAM_BLK, "mout_cam_blk", group_sclk_cam_blk_p, SRC_CAM, 0, 4),
+
+	/* SRC_MFC */
+	MUX(CLK_MOUT_MFC, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
+	MUX(CLK_MOUT_MFC_1, "mout_mfc_1", group_epll_vpll_p, SRC_MFC, 4, 1),
+	MUX(CLK_MOUT_MFC_0, "mout_mfc_0", group_div_mpll_pre_p, SRC_MFC, 0, 1),
+
+	/* SRC_G3D */
+	MUX(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1),
+	MUX(CLK_MOUT_G3D_1, "mout_g3d_1", group_epll_vpll_p, SRC_G3D, 4, 1),
+	MUX(CLK_MOUT_G3D_0, "mout_g3d_0", group_div_mpll_pre_p, SRC_G3D, 0, 1),
+
+	/* SRC_LCD */
+	MUX(CLK_MOUT_MIPI0, "mout_mipi0", group_sclk_p, SRC_LCD, 12, 4),
+	MUX(CLK_MOUT_FIMD0, "mout_fimd0", group_sclk_fimd0_p, SRC_LCD, 0, 4),
+
+	/* SRC_ISP */
+	MUX(CLK_MOUT_UART_ISP, "mout_uart_isp", group_sclk_p, SRC_ISP, 12, 4),
+	MUX(CLK_MOUT_SPI1_ISP, "mout_spi1_isp", group_sclk_p, SRC_ISP, 8, 4),
+	MUX(CLK_MOUT_SPI0_ISP, "mout_spi0_isp", group_sclk_p, SRC_ISP, 4, 4),
+
+	/* SRC_FSYS */
+	MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),
+	MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 3),
+	MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 3),
+
+	/* SRC_PERIL0 */
+	MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),
+	MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),
+
+	/* SRC_PERIL1 */
+	MUX(CLK_MOUT_SPI1, "mout_spi1", group_sclk_p, SRC_PERIL1, 20, 4),
+	MUX(CLK_MOUT_SPI0, "mout_spi0", group_sclk_p, SRC_PERIL1, 16, 4),
+	MUX(CLK_MOUT_AUDIO, "mout_audio", group_sclk_audio_p, SRC_PERIL1, 4, 4),
+
+	/* SRC_CPU */
+	MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p,
+	    SRC_CPU, 24, 1),
+	MUX(CLK_MOUT_HPM, "mout_hpm", mout_hpm_p, SRC_CPU, 20, 1),
+	MUX(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1),
+	MUX(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
+};
+
+static struct samsung_div_clock div_clks[] __initdata = {
+	/*
+	 * NOTE: Following table is sorted by register address in ascending
+	 * order and then bitfield shift in descending order, as it is done
+	 * in the User's Manual. When adding new entries, please make sure
+	 * that the order is preserved, to avoid merge conflicts and make
+	 * further work with defined data easier.
+	 */
+
+	/* DIV_LEFTBUS */
+	DIV(CLK_DIV_GPL, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
+	DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 4),
+
+	/* DIV_RIGHTBUS */
+	DIV(CLK_DIV_GPR, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
+	DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 4),
+
+	/* DIV_TOP */
+	DIV(CLK_DIV_MPLL_PRE, "div_mpll_pre", "sclk_mpll_mif", DIV_TOP, 28, 2),
+	DIV(CLK_DIV_ACLK_400_MCUISP, "div_aclk_400_mcuisp",
+	    "mout_aclk_400_mcuisp", DIV_TOP, 24, 3),
+	DIV(CLK_DIV_EBI, "div_ebi", "mout_ebi_1", DIV_TOP, 16, 3),
+	DIV(CLK_DIV_ACLK_200, "div_aclk_200", "mout_aclk_200", DIV_TOP, 12, 3),
+	DIV(CLK_DIV_ACLK_160, "div_aclk_160", "mout_aclk_160", DIV_TOP, 8, 3),
+	DIV(CLK_DIV_ACLK_100, "div_aclk_100", "mout_aclk_100", DIV_TOP, 4, 4),
+	DIV(CLK_DIV_ACLK_266, "div_aclk_266", "mout_aclk_266", DIV_TOP, 0, 3),
+
+	/* DIV_CAM */
+	DIV(CLK_DIV_CAM1, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
+	DIV(CLK_DIV_CAM_BLK, "div_cam_blk", "mout_cam_blk", DIV_CAM, 0, 4),
+
+	/* DIV_MFC */
+	DIV(CLK_DIV_MFC, "div_mfc", "mout_mfc", DIV_MFC, 0, 4),
+
+	/* DIV_G3D */
+	DIV(CLK_DIV_G3D, "div_g3d", "mout_g3d", DIV_G3D, 0, 4),
+
+	/* DIV_LCD */
+	DIV_F(CLK_DIV_MIPI0_PRE, "div_mipi0_pre", "div_mipi0", DIV_LCD, 20, 4,
+		CLK_SET_RATE_PARENT, 0),
+	DIV(CLK_DIV_MIPI0, "div_mipi0", "mout_mipi0", DIV_LCD, 16, 4),
+	DIV(CLK_DIV_FIMD0, "div_fimd0", "mout_fimd0", DIV_LCD, 0, 4),
+
+	/* DIV_ISP */
+	DIV(CLK_DIV_UART_ISP, "div_uart_isp", "mout_uart_isp", DIV_ISP, 28, 4),
+	DIV_F(CLK_DIV_SPI1_ISP_PRE, "div_spi1_isp_pre", "div_spi1_isp",
+		DIV_ISP, 20, 8, CLK_SET_RATE_PARENT, 0),
+	DIV(CLK_DIV_SPI1_ISP, "div_spi1_isp", "mout_spi1_isp", DIV_ISP, 16, 4),
+	DIV_F(CLK_DIV_SPI0_ISP_PRE, "div_spi0_isp_pre", "div_spi0_isp",
+		DIV_ISP, 8, 8, CLK_SET_RATE_PARENT, 0),
+	DIV(CLK_DIV_SPI0_ISP, "div_spi0_isp", "mout_spi0_isp", DIV_ISP, 0, 4),
+
+	/* DIV_FSYS0 */
+	DIV_F(CLK_DIV_TSADC_PRE, "div_tsadc_pre", "div_tsadc", DIV_FSYS0, 8, 8,
+		CLK_SET_RATE_PARENT, 0),
+	DIV(CLK_DIV_TSADC, "div_tsadc", "mout_tsadc", DIV_FSYS0, 0, 4),
+
+	/* DIV_FSYS1 */
+	DIV_F(CLK_DIV_MMC1_PRE, "div_mmc1_pre", "div_mmc1", DIV_FSYS1, 24, 8,
+		CLK_SET_RATE_PARENT, 0),
+	DIV(CLK_DIV_MMC1, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
+	DIV_F(CLK_DIV_MMC0_PRE, "div_mmc0_pre", "div_mmc0", DIV_FSYS1, 8, 8,
+		CLK_SET_RATE_PARENT, 0),
+	DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
+
+	/* DIV_PERIL0 */
+	DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
+	DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
+
+	/* DIV_PERIL1 */
+	DIV_F(CLK_DIV_SPI1_PRE, "div_spi1_pre", "div_spi1", DIV_PERIL1, 24, 8,
+		CLK_SET_RATE_PARENT, 0),
+	DIV(CLK_DIV_SPI1, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
+	DIV_F(CLK_DIV_SPI0_PRE, "div_spi0_pre", "div_spi0", DIV_PERIL1, 8, 8,
+		CLK_SET_RATE_PARENT, 0),
+	DIV(CLK_DIV_SPI0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
+
+	/* DIV_PERIL4 */
+	DIV(CLK_DIV_PCM, "div_pcm", "div_audio", DIV_PERIL4, 20, 8),
+	DIV(CLK_DIV_AUDIO, "div_audio", "mout_audio", DIV_PERIL4, 16, 4),
+
+	/* DIV_PERIL5 */
+	DIV(CLK_DIV_I2S, "div_i2s", "div_audio", DIV_PERIL5, 8, 6),
+
+	/* DIV_CPU0 */
+	DIV(CLK_DIV_CORE2, "div_core2", "div_core", DIV_CPU0, 28, 3),
+	DIV(CLK_DIV_APLL, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
+	DIV(CLK_DIV_PCLK_DBG, "div_pclk_dbg", "div_core2", DIV_CPU0, 20, 3),
+	DIV(CLK_DIV_ATB, "div_atb", "div_core2", DIV_CPU0, 16, 3),
+	DIV(CLK_DIV_COREM, "div_corem", "div_core2", DIV_CPU0, 4, 3),
+	DIV(CLK_DIV_CORE, "div_core", "mout_core", DIV_CPU0, 0, 3),
+
+	/* DIV_CPU1 */
+	DIV(CLK_DIV_HPM, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
+	DIV(CLK_DIV_COPY, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
+};
+
+static struct samsung_gate_clock gate_clks[] __initdata = {
+	/*
+	 * NOTE: Following table is sorted by register address in ascending
+	 * order and then bitfield shift in descending order, as it is done
+	 * in the User's Manual. When adding new entries, please make sure
+	 * that the order is preserved, to avoid merge conflicts and make
+	 * further work with defined data easier.
+	 */
+
+	/* GATE_IP_LEFTBUS */
+	GATE(CLK_ASYNC_G3D, "async_g3d", "div_aclk_100", GATE_IP_LEFTBUS, 6,
+		CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_ASYNC_MFCL, "async_mfcl", "div_aclk_100", GATE_IP_LEFTBUS, 4,
+		CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_PPMULEFT, "ppmuleft", "div_aclk_100", GATE_IP_LEFTBUS, 1,
+		CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GPIO_LEFT, "gpio_left", "div_aclk_100", GATE_IP_LEFTBUS, 0,
+		CLK_IGNORE_UNUSED, 0),
+
+	/* GATE_IP_RIGHTBUS */
+	GATE(CLK_ASYNC_ISPMX, "async_ispmx", "div_aclk_100",
+		GATE_IP_RIGHTBUS, 9, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_ASYNC_FSYSD, "async_fsysd", "div_aclk_100",
+		GATE_IP_RIGHTBUS, 5, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_ASYNC_LCD0X, "async_lcd0x", "div_aclk_100",
+		GATE_IP_RIGHTBUS, 3, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_ASYNC_CAMX, "async_camx", "div_aclk_100", GATE_IP_RIGHTBUS, 2,
+		CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_PPMURIGHT, "ppmuright", "div_aclk_100", GATE_IP_RIGHTBUS, 1,
+		CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GPIO_RIGHT, "gpio_right", "div_aclk_100", GATE_IP_RIGHTBUS, 0,
+		CLK_IGNORE_UNUSED, 0),
+
+	/* GATE_IP_PERIR */
+	GATE(CLK_MONOCNT, "monocnt", "div_aclk_100", GATE_IP_PERIR, 22,
+		CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_TZPC6, "tzpc6", "div_aclk_100", GATE_IP_PERIR, 21,
+		CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_PROVISIONKEY1, "provisionkey1", "div_aclk_100",
+		GATE_IP_PERIR, 20, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_PROVISIONKEY0, "provisionkey0", "div_aclk_100",
+		GATE_IP_PERIR, 19, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_CMU_ISPPART, "cmu_isppart", "div_aclk_100", GATE_IP_PERIR, 18,
+		CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_TMU_APBIF, "tmu_apbif", "div_aclk_100",
+		GATE_IP_PERIR, 17, 0, 0),
+	GATE(CLK_KEYIF, "keyif", "div_aclk_100", GATE_IP_PERIR, 16, 0, 0),
+	GATE(CLK_RTC, "rtc", "div_aclk_100", GATE_IP_PERIR, 15, 0, 0),
+	GATE(CLK_WDT, "wdt", "div_aclk_100", GATE_IP_PERIR, 14, 0, 0),
+	GATE(CLK_MCT, "mct", "div_aclk_100", GATE_IP_PERIR, 13, 0, 0),
+	GATE(CLK_SECKEY, "seckey", "div_aclk_100", GATE_IP_PERIR, 12,
+		CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_TZPC5, "tzpc5", "div_aclk_100", GATE_IP_PERIR, 10,
+		CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_TZPC4, "tzpc4", "div_aclk_100", GATE_IP_PERIR, 9,
+		CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_TZPC3, "tzpc3", "div_aclk_100", GATE_IP_PERIR, 8,
+		CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_TZPC2, "tzpc2", "div_aclk_100", GATE_IP_PERIR, 7,
+		CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_TZPC1, "tzpc1", "div_aclk_100", GATE_IP_PERIR, 6,
+		CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_TZPC0, "tzpc0", "div_aclk_100", GATE_IP_PERIR, 5,
+		CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_CMU_COREPART, "cmu_corepart", "div_aclk_100", GATE_IP_PERIR, 4,
+		CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_CMU_TOPPART, "cmu_toppart", "div_aclk_100", GATE_IP_PERIR, 3,
+		CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_PMU_APBIF, "pmu_apbif", "div_aclk_100", GATE_IP_PERIR, 2,
+		CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_SYSREG, "sysreg", "div_aclk_100", GATE_IP_PERIR, 1,
+		CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_CHIP_ID, "chip_id", "div_aclk_100", GATE_IP_PERIR, 0,
+		CLK_IGNORE_UNUSED, 0),
+
+	/* GATE_SCLK_CAM */
+	GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_cam_blk",
+		GATE_SCLK_CAM, 8, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_SCLK_M2MSCALER, "sclk_m2mscaler", "div_cam_blk",
+		GATE_SCLK_CAM, 2, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_SCLK_GSCALER1, "sclk_gscaler1", "div_cam_blk",
+		GATE_SCLK_CAM, 1, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_SCLK_GSCALER0, "sclk_gscaler0", "div_cam_blk",
+		GATE_SCLK_CAM, 0, CLK_SET_RATE_PARENT, 0),
+
+	/* GATE_SCLK_MFC */
+	GATE(CLK_SCLK_MFC, "sclk_mfc", "div_mfc",
+		GATE_SCLK_MFC, 0, CLK_SET_RATE_PARENT, 0),
+
+	/* GATE_SCLK_G3D */
+	GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d",
+		GATE_SCLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
+
+	/* GATE_SCLK_LCD */
+	GATE(CLK_SCLK_MIPIDPHY2L, "sclk_mipidphy2l", "div_mipi0",
+		GATE_SCLK_LCD, 4, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi0_pre",
+		GATE_SCLK_LCD, 3, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0",
+		GATE_SCLK_LCD, 0, CLK_SET_RATE_PARENT, 0),
+
+	/* GATE_SCLK_ISP_TOP */
+	GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
+		GATE_SCLK_ISP_TOP, 4, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "div_uart_isp",
+		GATE_SCLK_ISP_TOP, 3, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "div_spi1_isp",
+		GATE_SCLK_ISP_TOP, 2, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "div_spi0_isp",
+		GATE_SCLK_ISP_TOP, 1, CLK_SET_RATE_PARENT, 0),
+
+	/* GATE_SCLK_FSYS */
+	GATE(CLK_SCLK_UPLL, "sclk_upll", "mout_upll", GATE_SCLK_FSYS, 10, 0, 0),
+	GATE(CLK_SCLK_TSADC, "sclk_tsadc", "div_tsadc_pre",
+		GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",
+		GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre",
+		GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",
+		GATE_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
+
+	/* GATE_SCLK_PERIL */
+	GATE(CLK_SCLK_I2S, "sclk_i2s", "div_i2s",
+		GATE_SCLK_PERIL, 18, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_SCLK_PCM, "sclk_pcm", "div_pcm",
+		GATE_SCLK_PERIL, 16, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi1_pre",
+		GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
+		GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
+		GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
+		GATE_SCLK_PERIL, 0, CLK_SET_RATE_PARENT, 0),
+
+	/* GATE_IP_CAM */
+	GATE(CLK_QEJPEG, "qejpeg", "div_cam_blk_320", GATE_IP_CAM, 19,
+		CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_PIXELASYNCM1, "pixelasyncm1", "div_cam_blk_320",
+		GATE_IP_CAM, 18, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_PIXELASYNCM0, "pixelasyncm0", "div_cam_blk_320",
+		GATE_IP_CAM, 17, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_PPMUCAMIF, "ppmucamif", "div_cam_blk_320",
+		GATE_IP_CAM, 16, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_QEM2MSCALER, "qem2mscaler", "div_cam_blk_320",
+		GATE_IP_CAM, 14, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_QEGSCALER1, "qegscaler1", "div_cam_blk_320",
+		GATE_IP_CAM, 13, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_QEGSCALER0, "qegscaler0", "div_cam_blk_320",
+		GATE_IP_CAM, 12, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_SMMUJPEG, "smmujpeg", "div_cam_blk_320",
+		GATE_IP_CAM, 11, 0, 0),
+	GATE(CLK_SMMUM2M2SCALER, "smmum2m2scaler", "div_cam_blk_320",
+		GATE_IP_CAM, 9, 0, 0),
+	GATE(CLK_SMMUGSCALER1, "smmugscaler1", "div_cam_blk_320",
+		GATE_IP_CAM, 8, 0, 0),
+	GATE(CLK_SMMUGSCALER0, "smmugscaler0", "div_cam_blk_320",
+		GATE_IP_CAM, 7, 0, 0),
+	GATE(CLK_JPEG, "jpeg", "div_cam_blk_320", GATE_IP_CAM, 6, 0, 0),
+	GATE(CLK_M2MSCALER, "m2mscaler", "div_cam_blk_320",
+		GATE_IP_CAM, 2, 0, 0),
+	GATE(CLK_GSCALER1, "gscaler1", "div_cam_blk_320", GATE_IP_CAM, 1, 0, 0),
+	GATE(CLK_GSCALER0, "gscaler0", "div_cam_blk_320", GATE_IP_CAM, 0, 0, 0),
+
+	/* GATE_IP_MFC */
+	GATE(CLK_QEMFC, "qemfc", "div_aclk_200", GATE_IP_MFC, 5,
+		CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_PPMUMFC_L, "ppmumfc_l", "div_aclk_200", GATE_IP_MFC, 3,
+		CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_SMMUMFC_L, "smmumfc_l", "div_aclk_200", GATE_IP_MFC, 1, 0, 0),
+	GATE(CLK_MFC, "mfc", "div_aclk_200", GATE_IP_MFC, 0, 0, 0),
+
+	/* GATE_IP_G3D */
+	GATE(CLK_SMMUG3D, "smmug3d", "div_aclk_200", GATE_IP_G3D, 3, 0, 0),
+	GATE(CLK_QEG3D, "qeg3d", "div_aclk_200", GATE_IP_G3D, 2,
+		CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_PPMUG3D, "ppmug3d", "div_aclk_200", GATE_IP_G3D, 1,
+		CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_G3D, "g3d", "div_aclk_200", GATE_IP_G3D, 0, 0, 0),
+
+	/* GATE_IP_LCD */
+	GATE(CLK_QE_CH1_LCD, "qe_ch1_lcd", "div_aclk_160", GATE_IP_LCD, 7,
+		CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_QE_CH0_LCD, "qe_ch0_lcd", "div_aclk_160", GATE_IP_LCD, 6,
+		CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_PPMULCD0, "ppmulcd0", "div_aclk_160", GATE_IP_LCD, 5,
+		CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_SMMUFIMD0, "smmufimd0", "div_aclk_160", GATE_IP_LCD, 4, 0, 0),
+	GATE(CLK_DSIM0, "dsim0", "div_aclk_160", GATE_IP_LCD, 3, 0, 0),
+	GATE(CLK_SMIES, "smies", "div_aclk_160", GATE_IP_LCD, 2, 0, 0),
+	GATE(CLK_FIMD0, "fimd0", "div_aclk_160", GATE_IP_LCD, 0, 0, 0),
+
+	/* GATE_IP_ISP */
+	GATE(CLK_CAM1, "cam1", "mout_aclk_266_sub", GATE_IP_ISP, 5, 0, 0),
+	GATE(CLK_UART_ISP_TOP, "uart_isp_top", "mout_aclk_266_sub",
+		GATE_IP_ISP, 3, 0, 0),
+	GATE(CLK_SPI1_ISP_TOP, "spi1_isp_top", "mout_aclk_266_sub",
+		GATE_IP_ISP, 2, 0, 0),
+	GATE(CLK_SPI0_ISP_TOP, "spi0_isp_top", "mout_aclk_266_sub",
+		GATE_IP_ISP, 1, 0, 0),
+
+	/* GATE_IP_FSYS */
+	GATE(CLK_TSADC, "tsadc", "div_aclk_200", GATE_IP_FSYS, 20, 0, 0),
+	GATE(CLK_PPMUFILE, "ppmufile", "div_aclk_200", GATE_IP_FSYS, 17,
+		CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0),
+	GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
+	GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
+	GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
+	GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
+	GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
+	GATE(CLK_PDMA0, "pdma0", "div_aclk_200", GATE_IP_FSYS, 0, 0, 0),
+
+	/* GATE_IP_PERIL */
+	GATE(CLK_PWM, "pwm", "div_aclk_100", GATE_IP_PERIL, 24, 0, 0),
+	GATE(CLK_PCM, "pcm", "div_aclk_100", GATE_IP_PERIL, 23, 0, 0),
+	GATE(CLK_I2S, "i2s", "div_aclk_100", GATE_IP_PERIL, 21, 0, 0),
+	GATE(CLK_SPI1, "spi1", "div_aclk_100", GATE_IP_PERIL, 17, 0, 0),
+	GATE(CLK_SPI0, "spi0", "div_aclk_100", GATE_IP_PERIL, 16, 0, 0),
+	GATE(CLK_I2C7, "i2c7", "div_aclk_100", GATE_IP_PERIL, 13, 0, 0),
+	GATE(CLK_I2C6, "i2c6", "div_aclk_100", GATE_IP_PERIL, 12, 0, 0),
+	GATE(CLK_I2C5, "i2c5", "div_aclk_100", GATE_IP_PERIL, 11, 0, 0),
+	GATE(CLK_I2C4, "i2c4", "div_aclk_100", GATE_IP_PERIL, 10, 0, 0),
+	GATE(CLK_I2C3, "i2c3", "div_aclk_100", GATE_IP_PERIL, 9, 0, 0),
+	GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
+	GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
+	GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
+	GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
+	GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
+
+	/* GATE_BLOCK */
+	GATE(CLK_BLOCK_LCD, "block_lcd", "div_aclk_160", GATE_BLOCK, 4, 0, 0),
+	GATE(CLK_BLOCK_G3D, "block_g3d", "div_aclk_200", GATE_BLOCK, 3, 0, 0),
+};
+
+/* APLL & MPLL & BPLL & UPLL */
+static struct samsung_pll_rate_table exynos3250_pll_rates[] = {
+	PLL_35XX_RATE(1200000000, 400, 4, 1),
+	PLL_35XX_RATE(1100000000, 275, 3, 1),
+	PLL_35XX_RATE(1066000000, 533, 6, 1),
+	PLL_35XX_RATE(1000000000, 250, 3, 1),
+	PLL_35XX_RATE( 960000000, 320, 4, 1),
+	PLL_35XX_RATE( 900000000, 300, 4, 1),
+	PLL_35XX_RATE( 850000000, 425, 6, 1),
+	PLL_35XX_RATE( 800000000, 200, 3, 1),
+	PLL_35XX_RATE( 700000000, 175, 3, 1),
+	PLL_35XX_RATE( 667000000, 667, 12, 1),
+	PLL_35XX_RATE( 600000000, 400, 4, 2),
+	PLL_35XX_RATE( 533000000, 533, 6, 2),
+	PLL_35XX_RATE( 520000000, 260, 3, 2),
+	PLL_35XX_RATE( 500000000, 250, 3, 2),
+	PLL_35XX_RATE( 400000000, 200, 3, 2),
+	PLL_35XX_RATE( 200000000, 200, 3, 3),
+	PLL_35XX_RATE( 100000000, 200, 3, 4),
+	{ /* sentinel */ }
+};
+
+/* VPLL */
+static struct samsung_pll_rate_table exynos3250_vpll_rates[] = {
+	PLL_36XX_RATE(600000000, 100, 2, 1,     0),
+	PLL_36XX_RATE(533000000, 267, 3, 2, 32668),
+	PLL_36XX_RATE(519231000, 173, 2, 2,  5046),
+	PLL_36XX_RATE(500000000, 250, 3, 2,     0),
+	PLL_36XX_RATE(445500000, 149, 2, 2, 32768),
+	PLL_36XX_RATE(445055000, 148, 2, 2, 23047),
+	PLL_36XX_RATE(400000000, 200, 3, 2,     0),
+	PLL_36XX_RATE(371250000, 124, 2, 2, 49512),
+	PLL_36XX_RATE(370879000, 185, 3, 2, 28803),
+	PLL_36XX_RATE(340000000, 170, 3, 2,     0),
+	PLL_36XX_RATE(335000000, 112, 2, 2, 43691),
+	PLL_36XX_RATE(333000000, 111, 2, 2,     0),
+	PLL_36XX_RATE(330000000, 110, 2, 2,     0),
+	PLL_36XX_RATE(320000000, 107, 2, 2, 43691),
+	PLL_36XX_RATE(300000000, 100, 2, 2,     0),
+	PLL_36XX_RATE(275000000, 275, 3, 3,     0),
+	PLL_36XX_RATE(222750000, 149, 2, 3, 32768),
+	PLL_36XX_RATE(222528000, 148, 2, 3, 23069),
+	PLL_36XX_RATE(160000000, 160, 3, 3,     0),
+	PLL_36XX_RATE(148500000,  99, 2, 3,     0),
+	PLL_36XX_RATE(148352000,  99, 2, 3, 59070),
+	PLL_36XX_RATE(108000000, 144, 2, 4,     0),
+	PLL_36XX_RATE( 74250000,  99, 2, 4,     0),
+	PLL_36XX_RATE( 74176000,  99, 3, 4, 59070),
+	PLL_36XX_RATE( 54054000, 216, 3, 5, 14156),
+	PLL_36XX_RATE( 54000000, 144, 2, 5,     0),
+	{ /* sentinel */ }
+};
+
+static struct samsung_pll_clock exynos3250_plls[nr_plls] __initdata = {
+	[apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
+			APLL_LOCK, APLL_CON0, NULL),
+	[mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
+			MPLL_LOCK, MPLL_CON0, NULL),
+	[vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll",
+			VPLL_LOCK, VPLL_CON0, NULL),
+	[upll] = PLL(pll_35xx, CLK_FOUT_UPLL, "fout_upll", "fin_pll",
+			UPLL_LOCK, UPLL_CON0, NULL),
+};
+
+static void __init exynos3250_cmu_init(struct device_node *np)
+{
+	reg_base = of_iomap(np, 0);
+	if (!reg_base)
+		panic("%s: failed to map registers\n", __func__);
+
+	samsung_clk_init(np, reg_base, CLK_NR_CLKS);
+
+	samsung_clk_register_fixed_factor(fixed_factor_clks,
+					  ARRAY_SIZE(fixed_factor_clks));
+
+	exynos3250_plls[apll].rate_table = exynos3250_pll_rates;
+	exynos3250_plls[mpll].rate_table = exynos3250_pll_rates;
+	exynos3250_plls[vpll].rate_table = exynos3250_vpll_rates;
+	exynos3250_plls[upll].rate_table = exynos3250_pll_rates;
+
+	samsung_clk_register_pll(exynos3250_plls, ARRAY_SIZE(exynos3250_plls),
+				 reg_base);
+
+	samsung_clk_register_fixed_rate(fixed_rate_clks,
+					ARRAY_SIZE(fixed_rate_clks));
+
+	samsung_clk_register_mux(mux_clks, ARRAY_SIZE(mux_clks));
+	samsung_clk_register_div(div_clks, ARRAY_SIZE(div_clks));
+	samsung_clk_register_gate(gate_clks, ARRAY_SIZE(gate_clks));
+
+	exynos3250_clk_sleep_init();
+}
+CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init);
diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h
new file mode 100644
index 0000000..3efb323
--- /dev/null
+++ b/include/dt-bindings/clock/exynos3250.h
@@ -0,0 +1,256 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * 	Author: Tomasz Figa <t.figa@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants for Samsung Exynos3250 clock controllers.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H
+#define _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H
+
+/*
+ * Let each exported clock get a unique index, which is used on DT-enabled
+ * platforms to lookup the clock from a clock specifier. These indices are
+ * therefore considered an ABI and so must not be changed. This implies
+ * that new clocks should be added either in free spaces between clock groups
+ * or at the end.
+ */
+
+
+/*
+ * Main CMU
+ */
+
+#define CLK_OSCSEL			1
+#define CLK_FIN_PLL			2
+#define CLK_FOUT_APLL			3
+#define CLK_FOUT_VPLL			4
+#define CLK_FOUT_UPLL			5
+#define CLK_FOUT_MPLL			6
+
+/* Muxes */
+#define CLK_MOUT_MPLL_USER_L		16
+#define CLK_MOUT_GDL			17
+#define CLK_MOUT_MPLL_USER_R		18
+#define CLK_MOUT_GDR			19
+#define CLK_MOUT_EBI			20
+#define CLK_MOUT_ACLK_200		21
+#define CLK_MOUT_ACLK_160		22
+#define CLK_MOUT_ACLK_100		23
+#define CLK_MOUT_ACLK_266_1		24
+#define CLK_MOUT_ACLK_266_0		25
+#define CLK_MOUT_ACLK_266		26
+#define CLK_MOUT_VPLL			27
+#define CLK_MOUT_EPLL_USER		28
+#define CLK_MOUT_EBI_1			29
+#define CLK_MOUT_UPLL			30
+#define CLK_MOUT_ACLK_400_MCUISP_SUB	31
+#define CLK_MOUT_MPLL			32
+#define CLK_MOUT_ACLK_400_MCUISP	33
+#define CLK_MOUT_VPLLSRC		34
+#define CLK_MOUT_CAM1			35
+#define CLK_MOUT_CAM_BLK		36
+#define CLK_MOUT_MFC			37
+#define CLK_MOUT_MFC_1			38
+#define CLK_MOUT_MFC_0			39
+#define CLK_MOUT_G3D			40
+#define CLK_MOUT_G3D_1			41
+#define CLK_MOUT_G3D_0			42
+#define CLK_MOUT_MIPI0			43
+#define CLK_MOUT_FIMD0			44
+#define CLK_MOUT_UART_ISP		45
+#define CLK_MOUT_SPI1_ISP		46
+#define CLK_MOUT_SPI0_ISP		47
+#define CLK_MOUT_TSADC			48
+#define CLK_MOUT_MMC1			49
+#define CLK_MOUT_MMC0			50
+#define CLK_MOUT_UART1			51
+#define CLK_MOUT_UART0			52
+#define CLK_MOUT_SPI1			53
+#define CLK_MOUT_SPI0			54
+#define CLK_MOUT_AUDIO			55
+#define CLK_MOUT_MPLL_USER_C		56
+#define CLK_MOUT_HPM			57
+#define CLK_MOUT_CORE			58
+#define CLK_MOUT_APLL			59
+#define CLK_MOUT_ACLK_266_SUB		60
+
+/* Dividers */
+#define CLK_DIV_GPL			64
+#define CLK_DIV_GDL			65
+#define CLK_DIV_GPR			66
+#define CLK_DIV_GDR			67
+#define CLK_DIV_MPLL_PRE		68
+#define CLK_DIV_ACLK_400_MCUISP		69
+#define CLK_DIV_EBI			70
+#define CLK_DIV_ACLK_200		71
+#define CLK_DIV_ACLK_160		72
+#define CLK_DIV_ACLK_100		73
+#define CLK_DIV_ACLK_266		74
+#define CLK_DIV_CAM1			75
+#define CLK_DIV_CAM_BLK			76
+#define CLK_DIV_MFC			77
+#define CLK_DIV_G3D			78
+#define CLK_DIV_MIPI0_PRE		79
+#define CLK_DIV_MIPI0			80
+#define CLK_DIV_FIMD0			81
+#define CLK_DIV_UART_ISP		82
+#define CLK_DIV_SPI1_ISP_PRE		83
+#define CLK_DIV_SPI1_ISP		84
+#define CLK_DIV_SPI0_ISP_PRE		85
+#define CLK_DIV_SPI0_ISP		86
+#define CLK_DIV_TSADC_PRE		87
+#define CLK_DIV_TSADC			88
+#define CLK_DIV_MMC1_PRE		89
+#define CLK_DIV_MMC1			90
+#define CLK_DIV_MMC0_PRE		91
+#define CLK_DIV_MMC0			92
+#define CLK_DIV_UART1			93
+#define CLK_DIV_UART0			94
+#define CLK_DIV_SPI1_PRE		95
+#define CLK_DIV_SPI1			96
+#define CLK_DIV_SPI0_PRE		97
+#define CLK_DIV_SPI0			98
+#define CLK_DIV_PCM			99
+#define CLK_DIV_AUDIO			100
+#define CLK_DIV_I2S			101
+#define CLK_DIV_CORE2			102
+#define CLK_DIV_APLL			103
+#define CLK_DIV_PCLK_DBG		104
+#define CLK_DIV_ATB			105
+#define CLK_DIV_COREM			106
+#define CLK_DIV_CORE			107
+#define CLK_DIV_HPM			108
+#define CLK_DIV_COPY			109
+
+/* Gates */
+#define CLK_ASYNC_G3D			128
+#define CLK_ASYNC_MFCL			129
+#define CLK_PPMULEFT			130
+#define CLK_GPIO_LEFT			131
+#define CLK_ASYNC_ISPMX			132
+#define CLK_ASYNC_FSYSD			133
+#define CLK_ASYNC_LCD0X			134
+#define CLK_ASYNC_CAMX			135
+#define CLK_PPMURIGHT			136
+#define CLK_GPIO_RIGHT			137
+#define CLK_MONOCNT			138
+#define CLK_TZPC6			139
+#define CLK_PROVISIONKEY1		140
+#define CLK_PROVISIONKEY0		141
+#define CLK_CMU_ISPPART			142
+#define CLK_TMU_APBIF			143
+#define CLK_KEYIF			144
+#define CLK_RTC				145
+#define CLK_WDT				146
+#define CLK_MCT				147
+#define CLK_SECKEY			148
+#define CLK_TZPC5			149
+#define CLK_TZPC4			150
+#define CLK_TZPC3			151
+#define CLK_TZPC2			152
+#define CLK_TZPC1			153
+#define CLK_TZPC0			154
+#define CLK_CMU_COREPART		155
+#define CLK_CMU_TOPPART			156
+#define CLK_PMU_APBIF			157
+#define CLK_SYSREG			158
+#define CLK_CHIP_ID			159
+#define CLK_QEJPEG			160
+#define CLK_PIXELASYNCM1		161
+#define CLK_PIXELASYNCM0		162
+#define CLK_PPMUCAMIF			163
+#define CLK_QEM2MSCALER			164
+#define CLK_QEGSCALER1			165
+#define CLK_QEGSCALER0			166
+#define CLK_SMMUJPEG			167
+#define CLK_SMMUM2M2SCALER		168
+#define CLK_SMMUGSCALER1		169
+#define CLK_SMMUGSCALER0		170
+#define CLK_JPEG			171
+#define CLK_M2MSCALER			172
+#define CLK_GSCALER1			173
+#define CLK_GSCALER0			174
+#define CLK_QEMFC			175
+#define CLK_PPMUMFC_L			176
+#define CLK_SMMUMFC_L			177
+#define CLK_MFC				178
+#define CLK_SMMUG3D			179
+#define CLK_QEG3D			180
+#define CLK_PPMUG3D			181
+#define CLK_G3D				182
+#define CLK_QE_CH1_LCD			183
+#define CLK_QE_CH0_LCD			184
+#define CLK_PPMULCD0			185
+#define CLK_SMMUFIMD0			186
+#define CLK_DSIM0			187
+#define CLK_FIMD0			188
+#define CLK_CAM1			189
+#define CLK_UART_ISP_TOP		190
+#define CLK_SPI1_ISP_TOP		191
+#define CLK_SPI0_ISP_TOP		192
+#define CLK_TSADC			193
+#define CLK_PPMUFILE			194
+#define CLK_USBOTG			195
+#define CLK_USBHOST			196
+#define CLK_SROMC			197
+#define CLK_SDMMC1			198
+#define CLK_SDMMC0			199
+#define CLK_PDMA1			200
+#define CLK_PDMA0			201
+#define CLK_PWM				202
+#define CLK_PCM				203
+#define CLK_I2S				204
+#define CLK_SPI1			205
+#define CLK_SPI0			206
+#define CLK_I2C7			207
+#define CLK_I2C6			208
+#define CLK_I2C5			209
+#define CLK_I2C4			210
+#define CLK_I2C3			211
+#define CLK_I2C2			212
+#define CLK_I2C1			213
+#define CLK_I2C0			214
+#define CLK_UART1			215
+#define CLK_UART0			216
+#define CLK_BLOCK_LCD			217
+#define CLK_BLOCK_G3D			218
+#define CLK_SMIES			219
+
+/* Special clocks */
+#define CLK_SCLK_JPEG			224
+#define CLK_SCLK_M2MSCALER		225
+#define CLK_SCLK_GSCALER1		226
+#define CLK_SCLK_GSCALER0		227
+#define CLK_SCLK_MFC			228
+#define CLK_SCLK_G3D			229
+#define CLK_SCLK_MIPIDPHY2L		230
+#define CLK_SCLK_MIPI0			231
+#define CLK_SCLK_FIMD0			232
+#define CLK_SCLK_CAM1			233
+#define CLK_SCLK_UART_ISP		234
+#define CLK_SCLK_SPI1_ISP		235
+#define CLK_SCLK_SPI0_ISP		236
+#define CLK_SCLK_UPLL			237
+#define CLK_SCLK_TSADC			238
+#define CLK_SCLK_EBI			239
+#define CLK_SCLK_MMC1			240
+#define CLK_SCLK_MMC0			241
+#define CLK_SCLK_I2S			242
+#define CLK_SCLK_PCM			243
+#define CLK_SCLK_SPI1			244
+#define CLK_SCLK_SPI0			245
+#define CLK_SCLK_UART1			246
+#define CLK_SCLK_UART0			247
+
+/*
+ * Total number of clocks of main CMU.
+ * NOTE: Must be equal to last clock ID increased by one.
+ */
+#define CLK_NR_CLKS			248
+
+#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */
-- 
1.8.0

[PATCHv4 6/7] dt-bindings: add documentation for Exynos3250 clock controller

[Chanwoo Choi]

The Exynos3250 clocks are statically listed and registered using the
Samsung specific common clock helper functions. Both device tree based
clock lookup and clkdev based clock lookups are supported.

Cc: Mike Turquette <mturquette@linaro.org>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Randy Dunlap <rdunlap@infradead.org>
Cc: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 .../devicetree/bindings/clock/exynos3250-clock.txt | 41 ++++++++++++++++++++++
 1 file changed, 41 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/exynos3250-clock.txt

diff --git a/Documentation/devicetree/bindings/clock/exynos3250-clock.txt b/Documentation/devicetree/bindings/clock/exynos3250-clock.txt
new file mode 100644
index 0000000..aadc9c5
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos3250-clock.txt
@@ -0,0 +1,41 @@
+* Samsung Exynos3250 Clock Controller
+
+The Exynos3250 clock controller generates and supplies clock to various
+controllers within the Exynos3250 SoC.
+
+Required Properties:
+
+- compatible: should be one of the following.
+  - "samsung,exynos3250-cmu" - controller compatible with Exynos3250 SoC.
+
+- reg: physical base address of the controller and length of memory mapped
+  region.
+
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos3250.h header and can be used in device
+tree sources.
+
+Example 1: An example of a clock controller node is listed below.
+
+	cmu: clock-controller@10030000 {
+		compatible = "samsung,exynos3250-cmu";
+		reg = <0x10030000 0x20000>;
+		#clock-cells = <1>;
+	};
+
+Example 2: UART controller node that consumes the clock generated by the clock
+	   controller. Refer to the standard clock bindings for information
+	   about 'clocks' and 'clock-names' property.
+
+	serial@13800000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x13800000 0x100>;
+		interrupts = <0 109 0>;
+		clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
+		clock-names = "uart", "clk_uart_baud0";
+	};
-- 
1.8.0

[PATCHv4 7/7] ARM: dts: Add device tree sources for Exynos3250

[Chanwoo Choi]

From: Tomasz Figa <t.figa@samsung.com>

This patch add new exynos3250.dtsi to support Exynos3250 SoC based on Cortex-A7
dual core and includes following dt nodes:

- GIC interrupt controller
- Pinctrl to control GPIOs
- Clock controller
- CPU information (Cortex-A7 dual core)
- UART to support serial port
- MCT (Multi Core Timer)
- ADC (Analog Digital Converter)
- I2C/SPI bus
- Power domain
- PMU (Performance Monitoring Unit)
- MSHC (Mobile Storage Host Controller)
- PWM (Pluse Width Modulation)
- AMBA bus

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Hyunhee Kim <hyunhee.kim@samsung.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Cc: Ben Dooks <ben-linux@fluff.org>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: devicetree@vger.kernel.org
---
 arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 477 +++++++++++++++
 arch/arm/boot/dts/exynos3250.dtsi         | 405 +++++++++++++
 arch/arm/boot/dts/exynos4212-tizenw.dts   | 926 ++++++++++++++++++++++++++++++
 3 files changed, 1808 insertions(+)
 create mode 100644 arch/arm/boot/dts/exynos3250-pinctrl.dtsi
 create mode 100644 arch/arm/boot/dts/exynos3250.dtsi
 create mode 100644 arch/arm/boot/dts/exynos4212-tizenw.dts

diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
new file mode 100644
index 0000000..976490b
--- /dev/null
+++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
@@ -0,0 +1,477 @@
+/*
+ * Samsung's Exynos3250 SoCs pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Samsung's Exynos3250 SoCs pin-mux and pin-config optiosn are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/ {
+	pinctrl@11400000 {
+		gpa0: gpa0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpa1: gpa1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpb: gpb {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpc0: gpc0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpc1: gpc1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpd0: gpd0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpd1: gpd1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		uart0_data: uart0-data {
+			samsung,pins = "gpa0-0", "gpa0-1";
+			samsung,pin-function = <0x2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		uart0_fctl: uart0-fctl {
+			samsung,pins = "gpa0-2", "gpa0-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		uart1_data: uart1-data {
+			samsung,pins = "gpa0-4", "gpa0-5";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		uart1_fctl: uart1-fctl {
+			samsung,pins = "gpa0-6", "gpa0-7";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2c2_bus: i2c2-bus {
+			samsung,pins = "gpa0-6", "gpa0-7";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2c3_bus: i2c3-bus {
+			samsung,pins = "gpa1-2", "gpa1-3";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		spi0_bus: spi0-bus {
+			samsung,pins = "gpb-0", "gpb-2", "gpb-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2c4_bus: i2c4-bus {
+			samsung,pins = "gpb-0", "gpb-1";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		spi1_bus: spi1-bus {
+			samsung,pins = "gpb-4", "gpb-6", "gpb-7";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2c5_bus: i2c5-bus {
+			samsung,pins = "gpb-2", "gpb-3";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2s2_bus: i2s2-bus {
+			samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
+					"gpc1-4";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		pcm2_bus: pcm2-bus {
+			samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
+					"gpc1-4";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2c6_bus: i2c6-bus {
+			samsung,pins = "gpc1-3", "gpc1-4";
+			samsung,pin-function = <4>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		pwm0_out: pwm0-out {
+			samsung,pins = "gpd0-0";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		pwm1_out: pwm1-out {
+			samsung,pins = "gpd0-1";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2c7_bus: i2c7-bus {
+			samsung,pins = "gpd0-2", "gpd0-3";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		pwm2_out: pwm2-out {
+			samsung,pins = "gpd0-2";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		pwm3_out: pwm3-out {
+			samsung,pins = "gpd0-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2c0_bus: i2c0-bus {
+			samsung,pins = "gpd1-0", "gpd1-1";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		mipi0_clk: mipi0-clk {
+			samsung,pins = "gpd1-0", "gpd1-1";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2c1_bus: i2c1-bus {
+			samsung,pins = "gpd1-2", "gpd1-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+	};
+
+	pinctrl@11000000 {
+		gpe0: gpe0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpe1: gpe1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpe2: gpe2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpk0: gpk0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpk1: gpk1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpk2: gpk2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpl0: gpl0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpm0: gpm0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpm1: gpm1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpm2: gpm2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpm3: gpm3 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpm4: gpm4 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpx0: gpx0 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			interrupt-parent = <&gic>;
+			interrupts = <0 32 0>, <0 33 0>, <0 34 0>, <0 35 0>,
+					<0 36 0>, <0 37 0>, <0 38 0>, <0 39 0>;
+			#interrupt-cells = <2>;
+		};
+
+		gpx1: gpx1 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			interrupt-parent = <&gic>;
+			interrupts = <0 40 0>, <0 41 0>, <0 42 0>, <0 43 0>,
+					<0 44 0>, <0 45 0>, <0 46 0>, <0 47 0>;
+			#interrupt-cells = <2>;
+		};
+
+		gpx2: gpx2 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpx3: gpx3 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		sd0_clk: sd0-clk {
+			samsung,pins = "gpk0-0";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <3>;
+		};
+
+		sd0_cmd: sd0-cmd {
+			samsung,pins = "gpk0-1";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <3>;
+		};
+
+		sd0_cd: sd0-cd {
+			samsung,pins = "gpk0-2";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <3>;
+		};
+
+		sd0_rdqs: sd0-rdqs {
+			samsung,pins = "gpk0-7";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <3>;
+		};
+
+		sd0_bus1: sd0-bus-width1 {
+			samsung,pins = "gpk0-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <3>;
+		};
+
+		sd0_bus4: sd0-bus-width4 {
+			samsung,pins = "gpk0-4", "gpk0-5", "gpk0-6";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <3>;
+		};
+
+		sd0_bus8: sd0-bus-width8 {
+			samsung,pins = "gpl0-0", "gpl0-1", "gpl0-2", "gpl0-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <3>;
+		};
+
+		sd1_clk: sd1-clk {
+			samsung,pins = "gpk1-0";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <3>;
+		};
+
+		sd1_cmd: sd1-cmd {
+			samsung,pins = "gpk1-1";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <3>;
+		};
+
+		sd1_cd: sd1-cd {
+			samsung,pins = "gpk1-2";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <3>;
+		};
+
+		sd1_bus1: sd1-bus-width1 {
+			samsung,pins = "gpk1-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <3>;
+		};
+
+		sd1_bus4: sd1-bus-width4 {
+			samsung,pins = "gpk1-4", "gpk1-5", "gpk1-6";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <3>;
+		};
+
+		cam_port_b_io: cam-port-b-io {
+			samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3",
+					"gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7",
+					"gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		cam_port_b_clk_active: cam-port-b-clk-active {
+			samsung,pins = "gpm2-2";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <3>;
+		};
+
+		cam_port_b_clk_idle: cam-port-b-clk-idle {
+			samsung,pins = "gpm2-2";
+			samsung,pin-function = <0>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		fimc_is_i2c0: fimc-is-i2c0 {
+			samsung,pins = "gpm4-0", "gpm4-1";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		fimc_is_i2c1: fimc-is-i2c1 {
+			samsung,pins = "gpm4-2", "gpm4-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		fimc_is_uart: fimc-is-uart {
+			samsung,pins = "gpm3-5", "gpm3-7";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
new file mode 100644
index 0000000..5be3dd3
--- /dev/null
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -0,0 +1,405 @@
+/*
+ * Samsung's Exynos3250 SoC device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
+ * based board files can include this file and provide values for board specfic
+ * bindings.
+ *
+ * Note: This file does not include device nodes for all the controllers in
+ * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
+ * nodes can be added to this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "skeleton.dtsi"
+#include "exynos3250-pinctrl.dtsi"
+#include <dt-bindings/clock/exynos3250.h>
+
+/ {
+	compatible = "samsung,exynos3250";
+	interrupt-parent = <&gic>;
+
+	aliases {
+		pinctrl0 = &pinctrl_0;
+		pinctrl1 = &pinctrl_1;
+		mshc0 = &mshc_0;
+		mshc1 = &mshc_1;
+		spi0 = &spi_0;
+		spi1 = &spi_1;
+		i2c0 = &i2c_0;
+		i2c1 = &i2c_1;
+		i2c2 = &i2c_2;
+		i2c3 = &i2c_3;
+		i2c4 = &i2c_4;
+		i2c5 = &i2c_5;
+		i2c6 = &i2c_6;
+		i2c7 = &i2c_7;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0>;
+			clock-frequency = <1000000000>;
+		};
+	};
+
+	fixed-rate-clocks {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		xusbxti: clock@0 {
+			compatible = "fixed-clock";
+			reg = <0>;
+			clock-frequency = <0>;
+			#clock-cells = <0>;
+			clock-output-names = "xusbxti";
+		};
+
+		xxti: clock@1 {
+			compatible = "fixed-clock";
+			reg = <1>;
+			clock-frequency = <0>;
+			#clock-cells = <0>;
+			clock-output-names = "xxti";
+		};
+
+		xtcxo: clock@2 {
+			compatible = "fixed-clock";
+			reg = <2>;
+			clock-frequency = <0>;
+			#clock-cells = <0>;
+			clock-output-names = "xtcxo";
+		};
+	};
+
+	chipid@10000000 {
+		compatible = "samsung,exynos4210-chipid";
+		reg = <0x10000000 0x100>;
+	};
+
+	sys_reg: syscon@10010000 {
+		compatible = "samsung,exynos3-sysreg", "syscon";
+		reg = <0x10010000 0x400>;
+	};
+
+	pd_cam: cam-power-domain@10023C00 {
+		compatible = "samsung,exynos4210-pd";
+		reg = <0x10023C00 0x20>;
+	};
+
+	pd_mfc: mfc-power-domain@10023C40 {
+		compatible = "samsung,exynos4210-pd";
+		reg = <0x10023C40 0x20>;
+	};
+
+	pd_g3d: g3d-power-domain@10023C60 {
+		compatible = "samsung,exynos4210-pd";
+		reg = <0x10023C60 0x20>;
+	};
+
+	pd_lcd0: lcd0-power-domain@10023C80 {
+		compatible = "samsung,exynos4210-pd";
+		reg = <0x10023C80 0x20>;
+	};
+
+	pd_isp: isp-power-domain@10023CA0 {
+		compatible = "samsung,exynos4210-pd";
+		reg = <0x10023CA0 0x20>;
+	};
+
+	cmu: clock-controller@10030000 {
+		compatible = "samsung,exynos3250-cmu";
+		reg = <0x10030000 0x20000>;
+		#clock-cells = <1>;
+	};
+
+	rtc@10070000 {
+		compatible = "samsung,s3c6410-rtc";
+		reg = <0x10070000 0x100>;
+		interrupts = <0 73 0>, <0 74 0>;
+		status = "disabled";
+	};
+
+	gic: interrupt-controller@10481000 {
+		compatible = "arm,cortex-a15-gic";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		reg = <0x10481000 0x1000>,
+		      <0x10482000 0x1000>,
+		      <0x10484000 0x2000>,
+		      <0x10486000 0x2000>;
+		      interrupts = <1 9 0xf04>;
+	};
+
+	mct@10050000 {
+		compatible = "samsung,exynos4210-mct";
+		reg = <0x10050000 0x800>;
+		interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
+			     <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
+		clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
+		clock-names = "fin_pll", "mct";
+	};
+
+	pinctrl_1: pinctrl@11000000 {
+		compatible = "samsung,exynos3250-pinctrl";
+		reg = <0x11000000 0x1000>;
+		interrupts = <0 225 0>;
+
+		wakeup-interrupt-controller {
+			compatible = "samsung,exynos4210-wakeup-eint";
+			interrupt-parent = <&gic>;
+			interrupts = <0 48 0>;
+		};
+	};
+
+	pinctrl_0: pinctrl@11400000 {
+		compatible = "samsung,exynos3250-pinctrl";
+		reg = <0x11400000 0x1000>;
+		interrupts = <0 240 0>;
+	};
+
+	mshc_0: mshc@12510000 {
+		compatible = "samsung,exynos5250-dw-mshc";
+		reg = <0x12510000 0x1000>;
+		interrupts = <0 142 0>;
+		clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
+		clock-names = "biu", "ciu";
+		fifo-depth = <0x80>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	mshc_1: mshc@12520000 {
+		compatible = "samsung,exynos5250-dw-mshc";
+		reg = <0x12520000 0x1000>;
+		interrupts = <0 143 0>;
+		clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
+		clock-names = "biu", "ciu";
+		fifo-depth = <0x80>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	amba {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "arm,amba-bus";
+		interrupt-parent = <&gic>;
+		ranges;
+
+		pdma0: pdma@12680000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0x12680000 0x1000>;
+			interrupts = <0 138 0>;
+			clocks = <&cmu CLK_PDMA0>;
+			clock-names = "apb_pclk";
+			#dma-cells = <1>;
+			#dma-channels = <8>;
+			#dma-requests = <32>;
+		};
+
+		pdma1: pdma@12690000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0x12690000 0x1000>;
+			interrupts = <0 139 0>;
+			clocks = <&cmu CLK_PDMA1>;
+			clock-names = "apb_pclk";
+			#dma-cells = <1>;
+			#dma-channels = <8>;
+			#dma-requests = <32>;
+		};
+	};
+
+	adc: adc@126C0000 {
+		compatible = "samsung,exynos-adc-v3";
+		reg = <0x126C0000 0x100>, <0x10020718 0x4>;
+		interrupts = <0 137 0>;
+		clock-names = "adc", "sclk_tsadc";
+		clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
+		#io-channel-cells = <1>;
+		io-channel-ranges;
+		status = "disabled";
+	};
+
+	serial@13800000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x13800000 0x100>;
+		interrupts = <0 109 0>;
+		clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
+		clock-names = "uart", "clk_uart_baud0";
+		status = "disabled";
+	};
+
+	serial@13810000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x13810000 0x100>;
+		interrupts = <0 110 0>;
+		clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
+		clock-names = "uart", "clk_uart_baud0";
+		status = "disabled";
+	};
+
+	i2c_0: i2c@13860000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x13860000 0x100>;
+		interrupts = <0 113 0>;
+		clocks = <&cmu CLK_I2C0>;
+		clock-names = "i2c";
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c0_bus>;
+		status = "disabled";
+	};
+
+	i2c_1: i2c@13870000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x13870000 0x100>;
+		interrupts = <0 114 0>;
+		clocks = <&cmu CLK_I2C1>;
+		clock-names = "i2c";
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c1_bus>;
+		status = "disabled";
+	};
+
+	i2c_2: i2c@13880000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x13880000 0x100>;
+		interrupts = <0 115 0>;
+		clocks = <&cmu CLK_I2C2>;
+		clock-names = "i2c";
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c2_bus>;
+		status = "disabled";
+	};
+
+	i2c_3: i2c@13890000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x13890000 0x100>;
+		interrupts = <0 116 0>;
+		clocks = <&cmu CLK_I2C3>;
+		clock-names = "i2c";
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c3_bus>;
+		status = "disabled";
+	};
+
+	i2c_4: i2c@138A0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x138A0000 0x100>;
+		interrupts = <0 117 0>;
+		clocks = <&cmu CLK_I2C4>;
+		clock-names = "i2c";
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c4_bus>;
+		status = "disabled";
+	};
+
+	i2c_5: i2c@138B0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x138B0000 0x100>;
+		interrupts = <0 118 0>;
+		clocks = <&cmu CLK_I2C5>;
+		clock-names = "i2c";
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c5_bus>;
+		status = "disabled";
+	};
+
+	i2c_6: i2c@138C0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x138C0000 0x100>;
+		interrupts = <0 119 0>;
+		clocks = <&cmu CLK_I2C6>;
+		clock-names = "i2c";
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c6_bus>;
+		status = "disabled";
+	};
+
+	i2c_7: i2c@138D0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x138D0000 0x100>;
+		interrupts = <0 120 0>;
+		clocks = <&cmu CLK_I2C7>;
+		clock-names = "i2c";
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c7_bus>;
+		status = "disabled";
+	};
+
+	spi_0: spi@13920000 {
+		compatible = "samsung,exynos4210-spi";
+		reg = <0x13920000 0x100>;
+		interrupts = <0 121 0>;
+		dmas = <&pdma0 7>, <&pdma0 6>;
+		dma-names = "tx", "rx";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
+		clock-names = "spi", "spi_busclk0";
+		samsung,spi-src-clk = <0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&spi0_bus>;
+		status = "disabled";
+	};
+
+	spi_1: spi@13930000 {
+		compatible = "samsung,exynos4210-spi";
+		reg = <0x13930000 0x100>;
+		interrupts = <0 122 0>;
+		dmas = <&pdma1 7>, <&pdma1 6>;
+		dma-names = "tx", "rx";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
+		clock-names = "spi", "spi_busclk0";
+		samsung,spi-src-clk = <0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&spi1_bus>;
+		status = "disabled";
+	};
+
+	pwm: pwm@139D0000 {
+		compatible = "samsung,exynos4210-pwm";
+		reg = <0x139D0000 0x1000>;
+		interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
+			     <0 107 0>, <0 108 0>;
+		#pwm-cells = <3>;
+		status = "disabled";
+	};
+
+	pmu {
+		compatible = "arm,cortex-a7-pmu";
+		interrupts = <0 18 0>, <0 19 0>;
+	};
+};
diff --git a/arch/arm/boot/dts/exynos4212-tizenw.dts b/arch/arm/boot/dts/exynos4212-tizenw.dts
new file mode 100644
index 0000000..aed7060
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4212-tizenw.dts
@@ -0,0 +1,926 @@
+/*
+ * Samsung's Exynos4212 based Tizen-W board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Device tree source file for Samsung's Tizen-W board which is based on
+ * Samsung's Exynos4212 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ "exynos4212.dtsi"
+
+/ {
+	model = "Samsung Tizen-W board based on Exynos4212";
+	compatible = "samsung,tizen-w";
+
+	aliases {
+		/* 15...16 reserved for i2c0_isp, i2c1_isp */
+		i2c16 = &i2c1_isp;
+	};
+
+	memory {
+		reg =  <0x40000000 0x08000000
+			0x48000000 0x08000000
+			0x50000000 0x08000000
+			0x58000000 0x07F00000>;
+
+			reserved-memory {
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				contig_mem: region@48000000 {
+					compatible = "linux,contiguous-memory-region";
+					reg = <0x48000000 0x1000000>;
+					linux,default-contiguous-region;
+				};
+			};
+	};
+
+	chosen {
+		bootargs = "console=ttySAC1,115200N8 root=/dev/mmcblk0p5 rootwait earlyprintk panic=5";
+	};
+
+	pinctrl@11000000 {
+		cam-port-b-clk-active {
+			samsung,pin-drv = <2>;
+		};
+	};
+
+	firmware@0204F000 {
+		compatible = "samsung,secure-firmware";
+		reg = <0x0204F000 0x1000>;
+	};
+
+	vemmc_reg: voltage-regulator@0 {
+	        compatible = "regulator-fixed";
+		regulator-name = "VMEM_VDD_2.8V";
+		regulator-min-microvolt = <2800000>;
+		regulator-max-microvolt = <2800000>;
+		gpio = <&gpk0 2 0>;
+		enable-active-high;
+	};
+
+	rtc@10070000 {
+		status = "okay";
+	};
+
+	mshc@12550000 {
+		num-slots = <1>;
+		supports-highspeed;
+		broken-cd;
+		non-removable;
+		caps-mmc-erase;
+		fifo-depth = <0x80>;
+		card-detect-delay = <200>;
+		clocks = <&clock 301>, <&clock 149>;
+		clock-names = "biu", "ciu";
+		vmmc-supply = <&vemmc_reg>;
+		clock-frequency = <400000000>;
+		samsung,dw-mshc-ciu-div = <0>;
+		samsung,dw-mshc-sdr-timing = <2 3>;
+		samsung,dw-mshc-ddr-timing = <1 2>;
+		pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
+		pinctrl-names = "default";
+		status = "okay";
+
+		slot@0 {
+			reg = <0>;
+			bus-width = <8>;
+		};
+	};
+
+	adc: adc@126C0000 {
+		vdd-supply = <&ldo3_reg>;
+		status = "okay";
+
+		ncp15wb473@0 {
+			compatible = "ntc,ncp15wb473";
+			pullup-uv = <1800000>;	 /* VCC_1.8V_AP */
+			pullup-ohm = <100000>;	 /* 100K */
+			pulldown-ohm = <100000>; /* 100K */
+			io-channels = <&adc 1>;  /* AP temperature */
+		};
+
+		ncp15wb473@1 {
+			compatible = "ntc,ncp15wb473";
+			pullup-uv = <1800000>;	 /* VCC_1.8V_AP */
+			pullup-ohm = <100000>;	 /* 100K */
+			pulldown-ohm = <100000>; /* 100K */
+			io-channels = <&adc 2>;  /* Battery temperature */
+		};
+	};
+
+	serial@13800000 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&uart0_data &uart0_fctl>;
+		status = "okay";
+	};
+
+	serial@13810000 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&uart1_data>;
+		status = "okay";
+	};
+
+	fixed-rate-clocks {
+		xxti {
+			compatible = "samsung,clock-xxti", "fixed-clock";
+			clock-frequency = <0>;
+		};
+
+		xusbxti {
+			compatible = "samsung,clock-xusbxti", "fixed-clock";
+			clock-frequency = <24000000>;
+		};
+	};
+
+	cpufreq {
+		freq_table = <0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF
+			      0xFFFFFFFF 0xFFFFFFFF 800000 700000  600000
+			      500000 400000 300000 200000 100000>;
+		vdd_arm-supply = <&buck2_reg>;
+		status = "okay";
+	};
+
+	busfreq {
+		compatible = "samsung,exynos4x12-busfreq";
+		vdd_int-supply = <&buck3_reg>;
+		vdd_mif-supply = <&buck1_reg>;
+		user-max-freq = <133000>;
+		status = "okay";
+	};
+
+	gpio-keys@0 {
+		compatible = "gpio-keys";
+
+		key@116 {
+			interrupt-parent = <&gpx2>;
+			interrupts = <7 0>;
+			gpios = <&gpx2 7 1>;
+			linux,code = <116>;
+			label = "power";
+			debounce-interval = <10>;
+			gpio-key,wakeup;
+		};
+	};
+
+	haptic {
+		compatible = "linux,regulator-haptic";
+		haptic-supply = <&ldo20_reg>;
+		min-microvolt = <1100000>;
+		max-microvolt = <2000000>;
+	};
+
+	sec_reboot@ {
+		compatible = "samsung,sec-reboot";
+		power-gpio = <&gpx2 7 0>;
+		extcon = <&muic>;
+	};
+
+	charger-manager@ {
+		compatible = "charger-manager";
+
+		psy-name = "battery";
+
+		polling-mode = <1>;		/* Polling external power */
+		polling-interval-ms = <30000>;	/* Polling period */
+
+		fullbatt-uV = <4300>;
+		fullbatt-soc = <100>;
+		fullbatt-full-capacity = <0>;
+		fullbatt-vchkdrop-ms = <30000>;
+		fullbatt-vchkdrop-uV = <500>;
+
+		battery-present = <3>;		/* CM_CHARGER_STAT */
+
+		charging-max-duration-minute = <360>;
+		discharging-max-duration-minute = <90>;
+
+		psy-fuelgauge-name = "max17040";
+
+		measure-battery-temp;
+		measure-battery-temp-type = <2>; /* Read temp from hwmon */
+
+		io-channels = <&adc 2>;
+		iio-adc-overheat = <2500>;
+		iio-adc-cold = <0>;
+
+		hwmon-name = "ncp15wb473.13";	/* Battery temperature*/
+		hwmon-property = "temp1_input";
+		hwmon-milli-centigrade-overheat = <45000>;
+		hwmon-milli-centigrade-cold = <5000>; /* minus value */
+		vinchg1-supply = <&charger_reg>;
+
+		psy-chargers {
+			psy-charger-max14577 {
+				psy-charger-name = "max14577-charger";
+			};
+		};
+
+		charger-regulators {
+			charger-vinchg1 {
+				regulator-name = "vinchg1";
+				charger-cables {
+					cable-USB {
+						cable-name = "USB";
+						extcon-name = "max14577-muic";
+						min-current-uA = <475000>;
+						max-current-uA = <500000>;
+					};
+
+					cable-TA {
+						cable-name = "TA";
+						extcon-name = "max14577-muic";
+						min-current-uA = <475000>;
+						max-current-uA = <500000>;
+					};
+				};
+			};
+		};
+	};
+
+	i2c@13870000 {
+		samsung,i2c-sda-delay = <100>;
+		samsung,i2c-slave-addr = <0x10>;
+		samsung,i2c-max-bus-freq = <400000>;
+		pinctrl-0 = <&i2c1_bus>;
+		pinctrl-names = "default";
+		status = "okay";
+
+		fuel-gauge@36 {
+			compatible = "maxim,max17048";
+			reg = <0x36>;
+			interrupt-parent = <&gpx1>;
+			interrupts = <2 8>;
+		};
+	};
+
+	i2c@13880000 {
+		samsung,i2c-sda-delay = <100>;
+		samsung,i2c-slave-addr = <0x10>;
+		samsung,i2c-max-bus-freq = <400000>;
+		pinctrl-0 = <&i2c2_bus>;
+		pinctrl-names = "default";
+		status = "okay";
+
+		max14577@25 {
+			compatible = "maxim,max14577";
+			reg = <0x25>;
+			interrupt-parent = <&gpx1>;
+			interrupts = <5 0>;
+
+			muic: max14577-muic {
+				compatible = "maxim,max14577-muic";
+			};
+			regulators {
+				compatible = "maxim,max14577-regulator";
+				safeout_reg: SAFEOUT@1 {
+					regulator-name = "SAFEOUT";
+				};
+				charger_reg: CHARGER@0 {
+					regulator-name = "CHARGER";
+					regulator-min-microamp = <90000>;
+					regulator-max-microamp = <950000>;
+					regulator-boot-on;
+				};
+			};
+		};
+	};
+
+	i2c@13890000 {
+		samsung,i2c-sda-delay = <100>;
+		samsung,i2c-slave-addr = <0x10>;
+		samsung,i2c-max-bus-freq = <400000>;
+		pinctrl-0 = <&i2c3_bus>;
+		pinctrl-names = "default";
+		status = "okay";
+
+		touchscreen-mms128@48 {
+			compatible = "melfas,mms128";
+			reg = <0x48>;
+			interrupt-parent = <&gpm2>;
+			interrupts = <3 2>;
+			max_x = <320>;
+			max_y = <320>;
+			invert_x = <0>;
+			invert_y = <0>;
+			gpios = <&gpm2 3 2>,
+				<&gpa1 2 0>,
+				<&gpa1 3 0>;
+			tsp_vendor = "MELFAS";
+			tsp_ic = "MMS128S";
+			tsp_tx = <7>;
+			tsp_rx = <7>;
+			config_fw_version = "V700_ME_0910";
+			tsp_avdd_3.3v-supply = <&ldo21_reg>;
+			tsp_vdd_1.8v-supply = <&ldo25_reg>;
+		};
+	};
+
+	i2c@138D0000 {
+		samsung,i2c-sda-delay = <100>;
+		samsung,i2c-slave-addr = <0x10>;
+		samsung,i2c-max-bus-freq = <100000>;
+		pinctrl-0 = <&i2c7_bus>;
+		pinctrl-names = "default";
+		status = "okay";
+
+		s5m8767_pmic@66 {
+			compatible = "samsung,s5m8767-pmic";
+			interrupt-parent = <&gpx0>;
+			interrupts = <7 0>;
+			reg = <0x66>;
+
+			s5m8767,pmic-buck2-ramp-enable;
+			s5m8767,pmic-buck3-ramp-enable;
+			s5m8767,pmic-buck4-ramp-enable;
+			s5m8767,pmic-buck-ramp-delay = <25>;
+
+			s5m8767,pmic-buck-ds-gpios = <&gpf0 5 0>,
+						      <&gpx2 0 0>,
+						      <&gpx2 1 0>;
+			wakeup;
+
+			s5m8767_osc: clocks {
+				compatible = "samsung,s5m8767-clk";
+				#clock-cells = <1>;
+				clock-output-names = "s5m8767_ap",
+						"s5m8767_cp", "s5m8767_bt";
+			};
+
+			regulators {
+				ldo1_reg: LDO1 {
+					regulator-name = "VALIVE_1.0V_AP";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-always-on;
+					op_mode = <1>; /* Normal Mode */
+				};
+
+				ldo2_reg: LDO2 {
+					regulator-name = "VM1M2_1.2V_AP";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+					op_mode = <1>; /* Normal Mode */
+				};
+
+				ldo3_reg: LDO3 {
+					regulator-name = "VCC_1.8V_AP";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+					op_mode = <1>; /* Normal Mode */
+				};
+
+				ldo4_reg: LDO4 {
+					regulator-name = "VDDQ_PRE_1.8V";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+					op_mode = <1>; /* Normal Mode */
+				};
+
+				ldo5_reg: LDO5 {
+					regulator-name = "UNUSED_LDO5";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+					op_mode = <0>; /* Always OFF */
+				};
+
+				ldo6_reg: LDO6 {
+					regulator-name = "VMPLL_1.1V_AP";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-always-on;
+					op_mode = <1>; /* Normal Mode */
+				};
+
+				ldo7_reg: LDO7 {
+					regulator-name = "VPLL_1.1V_AP";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-always-on;
+					op_mode = <3>; /* Standby Mode */
+				};
+
+				ldo8_reg: LDO8 {
+					regulator-name = "VMIPI_1.0V_AP";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					op_mode = <3>; /* Standby Mode */
+				};
+
+				ldo9_reg: LDO9 {
+					regulator-name = "UNUSED_LDO9";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+					op_mode = <0>; /* Always OFF */
+				};
+
+				ldo10_reg: LDO10 {
+					regulator-name = "VMIPI_1.8V_AP";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					op_mode = <3>; /* Standby Mode */
+				};
+
+				ldo11_reg: LDO11 {
+					regulator-name = "VABB1_1.95V_AP";
+					regulator-min-microvolt = <1950000>;
+					regulator-max-microvolt = <1950000>;
+					op_mode = <3>; /* Standby Mode */
+				};
+
+				ldo12_reg: LDO12 {
+					regulator-name = "VUOTG_3.0V_AP";
+					regulator-min-microvolt = <3000000>;
+					regulator-max-microvolt = <3000000>;
+					op_mode = <1>; /* Normal Mode */
+				};
+
+				ldo13_reg: LDO13 {
+					regulator-name = "UNUSED_LDO13";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+					op_mode = <0>; /* Always OFF */
+				};
+
+				ldo14_reg: LDO14 {
+					regulator-name = "VABB02_1.95V_AP";
+					regulator-min-microvolt = <1950000>;
+					regulator-max-microvolt = <1950000>;
+					op_mode = <3>; /* Standby Mode */
+				};
+
+				ldo15_reg: LDO15 {
+					regulator-name = "VHSIC_1.0V_AP";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					op_mode = <1>; /* Normal Mode */
+				};
+
+				ldo16_reg: LDO16 {
+					regulator-name = "VHSIC_1.8V_AP";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					op_mode = <1>; /* Normal Mode */
+				};
+
+				ldo17_reg: LDO17 {
+					regulator-name = "VCC_AP_2.8V";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+					regulator-always-on;
+					op_mode = <1>; /* Normal Mode */
+				};
+
+				ldo19_reg: LDO19 {
+					regulator-name = "CAM_AF_2.8V";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+					op_mode = <3>; /* Standby Mode */
+				};
+
+				ldo20_reg: LDO20 {
+					regulator-name = "VDD_MOT_2.7V";
+					regulator-min-microvolt = <1100000>;
+					regulator-max-microvolt = <2700000>;
+					op_mode = <3>; /* Standby Mode */
+				};
+
+				ldo21_reg: LDO21 {
+					regulator-name = "TSP_AVDD_3.3V";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					op_mode = <1>; /* Normal Mode */
+				};
+
+				ldo22_reg: LDO22 {
+					regulator-name = "VCC_3.3V_LCD";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					op_mode = <1>; /* Normal Mode */
+				};
+
+				ldo24_reg: LDO24 {
+					regulator-name = "CAM_SENSOR_A2.8V";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+					op_mode = <3>; /* Standby Mode */
+				};
+
+				ldo25_reg: LDO25 {
+					regulator-name = "TSP_VDD_1.8V";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					op_mode = <1>; /* Normal Mode */
+				};
+
+				ldo26_reg: LDO26 {
+					regulator-name = "VCC_1.8V_LCD";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					op_mode = <1>; /* Normal Mode */
+				};
+
+				ldo27_reg: LDO27 {
+					regulator-name = "CAM_1.8V";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					op_mode = <3>; /* Standby Mode */
+				};
+
+				buck1_reg: BUCK1 {
+					regulator-name = "vdd_mif";
+					regulator-min-microvolt = <850000>;
+					regulator-max-microvolt	= <1100000>;
+					regulator-always-on;
+					op_mode = <3>; /* Standby Mode */
+				};
+
+				buck2_reg: BUCK2 {
+					regulator-name = "vdd_arm";
+					regulator-min-microvolt = <850000>;
+					regulator-max-microvolt	= <1500000>;
+					regulator-always-on;
+					op_mode = <3>; /* Standby Mode */
+				};
+
+				buck3_reg: BUCK3 {
+					regulator-name = "vdd_int";
+					regulator-min-microvolt = <850000>;
+					regulator-max-microvolt	= <1100000>;
+					regulator-always-on;
+					op_mode = <3>; /* Standby Mode */
+				};
+
+				buck4_reg: BUCK4 {
+					regulator-name = "vdd_g3d";
+					regulator-min-microvolt = <600000>;
+					regulator-max-microvolt	= <1075000>;
+					op_mode = <3>; /* Standby Mode */
+				};
+
+				buck5_reg: BUCK5 {
+					regulator-name = "VMEM_1.2V_AP";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt	= <1200000>;
+					regulator-always-on;
+					op_mode = <1>; /* Normal Mode */
+				};
+
+				buck6_reg: BUCK6 {
+					regulator-name = "UNUSED_BUCK6";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt	= <1200000>;
+					op_mode = <0>; /* Always OFF */
+				};
+
+				buck7_reg: BUCK7 {
+					regulator-name = "VCC_SUB_2.0V";
+					regulator-min-microvolt = <2000000>;
+					regulator-max-microvolt	= <2000000>;
+					op_mode = <3>; /* Standby Mode */
+				};
+
+				buck8_reg: BUCK8 {
+					regulator-name = "VCC_SUB_1.35V";
+					regulator-min-microvolt = <1350000>;
+					regulator-max-microvolt	= <1350000>;
+					op_mode = <3>; /* Standby Mode */
+				};
+			};
+		};
+
+		s5m8767_rtc@ {
+			compatible = "samsung,s5m8767-rtc";
+		};
+	};
+
+	spi_0: spi@13920000 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&spi0_bus>;
+		status = "okay";
+
+		ymu831: ymu831-spi {
+			compatible = "yamaha,ymu831";
+			spi-max-frequency = <10000000>;
+			interrupt-parent = <&gpx1>;
+			interrupts = <4 0>;
+			reg = <0x0>;
+			codec-en-gpios = <&gpx3 6 0>;
+			controller-data {
+				cs-gpio = <&gpb 1 0>;
+				samsung,spi-feedback-delay = <2>;
+			};
+		};
+	};
+
+	spi_1: spi@13930000 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&spi1_bus>;
+		status = "okay";
+		spi-cpha;
+
+		shub_spi: shub {
+			compatible = "samsung,ssp-spi";
+			spi-max-frequency = <5000000>;
+			interrupt-parent = <&gpx0>;
+                        interrupts = <2 0>;
+			ap-mcu-int = <&gpx0 0 0>;
+			mcu-ap-int1 = <&gpx0 2 0>;
+			mcu-ap-int2 = <&gpx0 4 0>;
+			mcu-reset = <&gpx0 5 0>;
+			reg = <0>;
+			controller-data {
+				cs-gpio = <&gpb 5 0>;
+				samsung,spi-feedback-dealy = <0>;
+			};
+		};
+	};
+
+	mipi_lcd: mipi_panel {
+		compatible = "samsung,s6e63j0x03";
+		lcd-panel-name = "s6e63j0x03";
+		reset-gpio = <&gpf2 1 0>;	/* mux function : output */
+		te-gpio = <&gpx0 6 0>;		/* mux function : input */
+		det-gpio = <&gpx1 7 0>;		/* mux function : input */
+		reset-delay = <5>;
+		power-on-delay = <30>;
+		power-off-delay = <120>;
+		was-enabled;
+		vdd3-supply = <&ldo26_reg>;
+		vci-supply = <&ldo22_reg>;
+		samsung,panel-width-mm = <29>;
+		samsung,panel-height-mm = <29>;
+		samsung,panel-frame-freq = <30>;	/* Hz */
+
+		display-timings {
+			native-mode = <&timing0>;
+
+			timing0: timing-0 {
+				clock-frequency = <0>;
+				hactive = <320>;
+				vactive = <320>;
+				hfront-porch = <1>;
+				hback-porch = <1>;
+				hsync-len = <1>;
+				vfront-porch = <150>;
+				vback-porch = <1>;
+				vsync-len = <2>;
+			};
+		};
+
+		cpu-timings {
+			cs_setup = <0>;
+			wr_setup = <0>;
+			wr_act = <1>;
+			wr_hold = <0>;
+		};
+	};
+
+	dsi@11C80000 {
+		client = <&mipi_lcd>;
+		source = <&fimd>;
+		vdd11-supply = <&ldo8_reg>;
+		vdd18-supply = <&ldo10_reg>;
+		status = "okay";
+
+		mipi-dsi-config {
+			interface = <0>;	/* command mode */
+			pixel_format = <7>;	/* RGB 24BPP */
+			auto_flush = <0>;
+			eot_disable = <0>;
+			auto_vertical_cnt = <0>;
+			hse = <0>;
+			hfp = <0>;
+			hbp = <0>;
+			hsa = <0>;
+			no_data_lane = <0>;	/* use 1 lane */
+			byte_clk = <0>;
+			burst_mode = <3>;
+			p = <3>;		/* p m s : 250Mbps */
+			m = <125>;
+			s = <2>;
+			pll_stable_time = <500>;
+			esc_clk = <20000000>;
+			stop_holding_cnt = <0xf>;
+			bta_timeout = <0xff>;
+			rx_timeout = <0xffff>;
+			virtual_ch = <0>;
+			cmd_allow = <0xf>;
+		};
+	};
+
+	fimd@11c00000 {
+		display = <&mipi_lcd>;
+		display-bus = <&dsi_0>;
+		dsi-enable;
+		vidout-i80-ldi0;
+		vidout-pnrmode-rgb;
+		default_win = <3>;
+		gamma-tbl = <0x000C0000 0x005C002C 0x00EC009C 0x01B00148
+				0x02940228 0x032402E4 0x038C035C 0x03DC03B8
+				0x000003FC 0x00100000 0x00680034 0x00F800A8
+				0x01C00154 0x02980230 0x032802E8 0x03900360
+				0x03DC03B8 0x000003FC 0x00100000 0x00680034
+				0x00F800A8 0x01C00154 0x02980230 0x032802E8
+				0x03900360 0x03DC03B8 0x000003FC 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000
+				0x00000000>;
+		status = "okay";
+	};
+
+	gpu@13000000 {
+		status = "okay";
+		clock-names = "pll", "mux1", "mux2", "sclk", "block", "g3d";
+		clocks = <&clock 17>, <&clock 392>, <&clock 394>,
+				<&clock 172>, <&clock 483>, <&clock 276>;
+		vdd_g3d-supply = <&buck4_reg>;
+		control-regulator;
+		dvfs {
+			step@0 {
+				rate = <80000000>;
+				min_uv = <600000>;
+				max_uv = <600000>;
+				downthreshold = <0>;
+				upthreshold = <255>;
+			};
+			step@1 {
+				rate = <80000000>;
+				min_uv = <900000>;
+				max_uv = <900000>;
+				downthreshold = <0>;
+				upthreshold = <255>;
+			};
+		};
+	};
+
+	hsotg@12480000 {
+		status = "okay";
+		vusb_core-supply = <&safeout_reg>;
+		vusb_d-supply = <&ldo15_reg>;
+		vusb_a-supply = <&ldo12_reg>;
+		extcon = <&muic>;
+	};
+
+	exynos-usbphy@125B0000 {
+		status = "okay";
+	};
+
+	rfkill-gpio {
+		compatible = "rfkill-gpio";
+		clocks = <&s5m8767_osc 2 /*S2MPS11_CLK_BT*/>;
+		clock-names = "bt_clk32k";
+
+		bt {
+			label = "bluetooth";
+			type = <2>;
+			reset-gpio = <&gpx3 0 0>;
+			shutdown-gpio = <&gpl0 6 0>;
+			wake-gpio = <&gpx3 1 0>;
+			host-wake-gpio = <&gpx2 6 0>;
+			clock = "bt_clk32k";
+		};
+	};
+
+	codec@13400000 {
+		status = "okay";
+	};
+
+	i2s0: i2s@03830000 {
+		pinctrl-0 = <&i2s0_bus>;
+		pinctrl-names = "default";
+		status = "okay";
+		assigned-clock-parents = <&clock_audss 3 &clock_audss 0>,
+			<&clock_audss 0 &clock 6>;
+		assigned-clock-rates = <&clock_audss 1 96000000>,
+			<&clock_audss 2 96000000>;
+	};
+
+	sound {
+		compatible = "tizenw,ymu831";
+		clocks = <&clock 2>, <&clock 396>, <&clock 21>, <&clock 6>,
+		       <&s5m8767_osc 2 /*S2MPS11_CLK_BT*/>; 
+		clock-names = "parent", "out-mux", "out", "pll", "clk_32k";
+		/* EPLL */
+		samsung,i2s-controller = <&i2s0>;
+		samsung,audio-codec = <&ymu831>;
+		samsung,model = "ymu831";
+	};
+
+	camera {
+		status = "okay";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&cam_port_b_clk_active>;
+
+		fimc_0: fimc@11800000 {
+			clock-frequency = <80000000>;
+			status = "okay";
+		};
+
+		fimc_1: fimc@11810000 {
+			clock-frequency = <80000000>;
+			status = "okay";
+		};
+
+		fimc_2: fimc@11820000 {
+			clock-frequency = <80000000>;
+			status = "okay";
+		};
+
+		fimc_3: fimc@11830000 {
+			clock-frequency = <80000000>;
+			status = "okay";
+		};
+
+		csis_1: csis@11890000 {
+			status = "okay";
+			vddcore-supply = <&ldo8_reg>;
+			vddio-supply = <&ldo10_reg>;
+			clock-frequency = <80000000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* Camera D (4) MIPI CSI-2 (CSIS1) */
+			port@4 {
+				reg = <4>;
+				csis1_ep: endpoint {
+					remote-endpoint = <&is_s5k6a3_ep>;
+					data-lanes = <1>;
+					samsung,csis-hs-settle = <18>;
+					samsung,csis-wclk;
+				};
+			};
+		};
+
+		fimc-is@12000000 {
+			samsung,aclk-frequency = <80000000>;
+			samsung,aclk-axi-frequency = <80000000>;
+			samsung,mcuisp-frequency = <400000000>;
+			status = "okay";
+
+			fimc-isp@12000000 {
+				status = "okay";
+			};
+
+			fimc_lite_1: fimc-lite@123A0000 {
+				status = "okay";
+			};
+
+			i2c1_isp: i2c-isp@12140000 {
+				pinctrl-0 = <&fimc_is_i2c1>;
+				pinctrl-names = "default";
+
+				s5k6a3@10 {
+					compatible = "samsung,s5k6a3";
+					reg = <0x10>;
+					svdda-supply = <&ldo24_reg>;
+					svddio-supply = <&ldo27_reg>;
+					afvdd-supply = <&ldo19_reg>;
+					gpios = <&gpj1 0 0>;
+					clocks = <&camera 1>; /* CAM_B_CLKOUT */
+					clock-names = "extclk";
+					clock-frequency = <24000000>;
+					port {
+						is_s5k6a3_ep: endpoint {
+							remote-endpoint = <&csis1_ep>;
+							data-lanes = <1>;
+						};
+					};
+				};
+			};
+		};
+	};
+
+	jack {
+		compatible = "samsung,extcon-port";
+		extcon = <&muic>;
+
+		samsung,extcon-online-usb;
+		samsung,extcon-online-charger;
+	};
+
+	tmu@100C0000 {
+		vtmu-supply = <&ldo10_reg>;
+		sampling-interval = <5000>;
+		t0_on = <0x1e0>;
+		t0_off = <0x960>;
+		t1_on = <0x960>;
+		t1_off = <0x30>;
+		status = "okay";
+	};
+
+	exynos-drm {
+		compatible = "samsung,exynos-drm";
+		crtcs = <&fimd>;
+		connectors = <&dsi_0>;
+	};
+};
-- 
1.8.0

Re: [PATCHv4 3/7] ARM: EXYNOS: Support secondary CPU boot of Exynos3250

[Tushar Behera]

On 04/25/2014 06:46 AM, Chanwoo Choi wrote:
> This patch fix the offset of CPU boot address and don't need to send smc call
> of SMC_CMD_CPU1BOOT command for secondary CPU boot because Exynos3250 removes
> WFE in secure mode.
> 
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
> ---
>  arch/arm/mach-exynos/firmware.c | 10 ++++++++--
>  1 file changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
> index aa01c42..386d01d 100644
> --- a/arch/arm/mach-exynos/firmware.c
> +++ b/arch/arm/mach-exynos/firmware.c
> @@ -31,11 +31,17 @@ static int exynos_do_idle(void)
>  static int exynos_cpu_boot(int cpu)
>  {
>  	/*
> +	 * Exynos3250 doesn't need to send smc command for secondary CPU boot
> +	 * because Exynos3250 removes WFE in secure mode.
> +	 */
> +	if (soc_is_exynos3250())
> +		return 0;
> +	/*
>  	 * The second parameter of SMC_CMD_CPU1BOOT command means CPU id.
>  	 * But, Exynos4212 has only one secondary CPU so second parameter
>  	 * isn't used for informing secure firmware about CPU id.
>  	 */
> -	if (soc_is_exynos4212())
> +	else if (soc_is_exynos4212())

This changes is not required.

>  		cpu = 0;
>  
>  	exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
> @@ -46,7 +52,7 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
>  {
>  	void __iomem *boot_reg = S5P_VA_SYSRAM_NS + 0x1c;
>  
> -	if (!soc_is_exynos4212())
> +	if (!soc_is_exynos4212() && !soc_is_exynos3250())
>  		boot_reg += 4*cpu;
>  
>  	__raw_writel(boot_addr, boot_reg);
> 


-- 
Tushar Behera

Re: [PATCHv4 7/7] ARM: dts: Add device tree sources for Exynos3250

[Tushar Behera]

On 04/25/2014 06:46 AM, Chanwoo Choi wrote:
> From: Tomasz Figa <t.figa@samsung.com>
> 
> This patch add new exynos3250.dtsi to support Exynos3250 SoC based on Cortex-A7
> dual core and includes following dt nodes:
> 

[ ... ]

> ---
>  arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 477 +++++++++++++++
>  arch/arm/boot/dts/exynos3250.dtsi         | 405 +++++++++++++
>  arch/arm/boot/dts/exynos4212-tizenw.dts   | 926 ++++++++++++++++++++++++++++++

exynos4412-tizenw.dts related changes are unrelated.

-- 
Tushar Behera

Re: [PATCHv4 7/7] ARM: dts: Add device tree sources for Exynos3250

[Chanwoo Choi]

On 04/25/2014 01:38 PM, Tushar Behera wrote:
> On 04/25/2014 06:46 AM, Chanwoo Choi wrote:
>> From: Tomasz Figa <t.figa@samsung.com>
>>
>> This patch add new exynos3250.dtsi to support Exynos3250 SoC based on Cortex-A7
>> dual core and includes following dt nodes:
>>
> 
> [ ... ]
> 
>> ---
>>  arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 477 +++++++++++++++
>>  arch/arm/boot/dts/exynos3250.dtsi         | 405 +++++++++++++
>>  arch/arm/boot/dts/exynos4212-tizenw.dts   | 926 ++++++++++++++++++++++++++++++
> 
> exynos4412-tizenw.dts related changes are unrelated.


Right, It is may mistake.
I'll resend this patch.

Thanks,
Chanwoo Choi

Re: [PATCHv4 3/7] ARM: EXYNOS: Support secondary CPU boot of Exynos3250

[Chanwoo Choi]

Hi,

On 04/25/2014 01:30 PM, Tushar Behera wrote:
> On 04/25/2014 06:46 AM, Chanwoo Choi wrote:
>> This patch fix the offset of CPU boot address and don't need to send smc call
>> of SMC_CMD_CPU1BOOT command for secondary CPU boot because Exynos3250 removes
>> WFE in secure mode.
>>
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
>> ---
>>  arch/arm/mach-exynos/firmware.c | 10 ++++++++--
>>  1 file changed, 8 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
>> index aa01c42..386d01d 100644
>> --- a/arch/arm/mach-exynos/firmware.c
>> +++ b/arch/arm/mach-exynos/firmware.c
>> @@ -31,11 +31,17 @@ static int exynos_do_idle(void)
>>  static int exynos_cpu_boot(int cpu)
>>  {
>>  	/*
>> +	 * Exynos3250 doesn't need to send smc command for secondary CPU boot
>> +	 * because Exynos3250 removes WFE in secure mode.
>> +	 */
>> +	if (soc_is_exynos3250())
>> +		return 0;
>> +	/*
>>  	 * The second parameter of SMC_CMD_CPU1BOOT command means CPU id.
>>  	 * But, Exynos4212 has only one secondary CPU so second parameter
>>  	 * isn't used for informing secure firmware about CPU id.
>>  	 */
>> -	if (soc_is_exynos4212())
>> +	else if (soc_is_exynos4212())
> 
> This changes is not required.

Do you mean it as following?

	if (soc_is_exynos3250())
		return 0

	if (soc_is_exynos4212())
		cpu = 0;

> 
>>  		cpu = 0;
>>  
>>  	exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
>> @@ -46,7 +52,7 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
>>  {
>>  	void __iomem *boot_reg = S5P_VA_SYSRAM_NS + 0x1c;
>>  
>> -	if (!soc_is_exynos4212())
>> +	if (!soc_is_exynos4212() && !soc_is_exynos3250())
>>  		boot_reg += 4*cpu;
>>  
>>  	__raw_writel(boot_addr, boot_reg);
>>
> 
> 

Re: [PATCHv4 3/7] ARM: EXYNOS: Support secondary CPU boot of Exynos3250

[Tushar Behera]

On 04/25/2014 11:13 AM, Chanwoo Choi wrote:
> Hi,
> 
> On 04/25/2014 01:30 PM, Tushar Behera wrote:
>> On 04/25/2014 06:46 AM, Chanwoo Choi wrote:
>>> This patch fix the offset of CPU boot address and don't need to send smc call
>>> of SMC_CMD_CPU1BOOT command for secondary CPU boot because Exynos3250 removes
>>> WFE in secure mode.
>>>
>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>> Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
>>> ---
>>>  arch/arm/mach-exynos/firmware.c | 10 ++++++++--
>>>  1 file changed, 8 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
>>> index aa01c42..386d01d 100644
>>> --- a/arch/arm/mach-exynos/firmware.c
>>> +++ b/arch/arm/mach-exynos/firmware.c
>>> @@ -31,11 +31,17 @@ static int exynos_do_idle(void)
>>>  static int exynos_cpu_boot(int cpu)
>>>  {
>>>  	/*
>>> +	 * Exynos3250 doesn't need to send smc command for secondary CPU boot
>>> +	 * because Exynos3250 removes WFE in secure mode.
>>> +	 */
>>> +	if (soc_is_exynos3250())
>>> +		return 0;
>>> +	/*
>>>  	 * The second parameter of SMC_CMD_CPU1BOOT command means CPU id.
>>>  	 * But, Exynos4212 has only one secondary CPU so second parameter
>>>  	 * isn't used for informing secure firmware about CPU id.
>>>  	 */
>>> -	if (soc_is_exynos4212())
>>> +	else if (soc_is_exynos4212())
>>
>> This changes is not required.
> 
> Do you mean it as following?
> 
> 	if (soc_is_exynos3250())
> 		return 0
> 
> 	if (soc_is_exynos4212())
> 		cpu = 0;
> 

Yes, logically the flow would be same and code would be more readable.

>>
>>>  		cpu = 0;
>>>  
>>>  	exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
>>> @@ -46,7 +52,7 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
>>>  {
>>>  	void __iomem *boot_reg = S5P_VA_SYSRAM_NS + 0x1c;
>>>  
>>> -	if (!soc_is_exynos4212())
>>> +	if (!soc_is_exynos4212() && !soc_is_exynos3250())
>>>  		boot_reg += 4*cpu;
>>>  
>>>  	__raw_writel(boot_addr, boot_reg);
>>>
>>
>>
> 


-- 
Tushar Behera

Re: [PATCHv4 3/7] ARM: EXYNOS: Support secondary CPU boot of Exynos3250

[Chanwoo Choi]

Hi,

On 04/25/2014 02:54 PM, Tushar Behera wrote:
> On 04/25/2014 11:13 AM, Chanwoo Choi wrote:
>> Hi,
>>
>> On 04/25/2014 01:30 PM, Tushar Behera wrote:
>>> On 04/25/2014 06:46 AM, Chanwoo Choi wrote:
>>>> This patch fix the offset of CPU boot address and don't need to send smc call
>>>> of SMC_CMD_CPU1BOOT command for secondary CPU boot because Exynos3250 removes
>>>> WFE in secure mode.
>>>>
>>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>>> Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
>>>> ---
>>>>  arch/arm/mach-exynos/firmware.c | 10 ++++++++--
>>>>  1 file changed, 8 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
>>>> index aa01c42..386d01d 100644
>>>> --- a/arch/arm/mach-exynos/firmware.c
>>>> +++ b/arch/arm/mach-exynos/firmware.c
>>>> @@ -31,11 +31,17 @@ static int exynos_do_idle(void)
>>>>  static int exynos_cpu_boot(int cpu)
>>>>  {
>>>>  	/*
>>>> +	 * Exynos3250 doesn't need to send smc command for secondary CPU boot
>>>> +	 * because Exynos3250 removes WFE in secure mode.
>>>> +	 */
>>>> +	if (soc_is_exynos3250())
>>>> +		return 0;
>>>> +	/*
>>>>  	 * The second parameter of SMC_CMD_CPU1BOOT command means CPU id.
>>>>  	 * But, Exynos4212 has only one secondary CPU so second parameter
>>>>  	 * isn't used for informing secure firmware about CPU id.
>>>>  	 */
>>>> -	if (soc_is_exynos4212())
>>>> +	else if (soc_is_exynos4212())
>>>
>>> This changes is not required.
>>
>> Do you mean it as following?
>>
>> 	if (soc_is_exynos3250())
>> 		return 0
>>
>> 	if (soc_is_exynos4212())
>> 		cpu = 0;
>>
> 
> Yes, logically the flow would be same and code would be more readable.

OK, I'll fix it.

Thanks,
Chanwoo Choi

Re: [PATCHv4 4/7] ARM: EXYNOS: Enter a15 lowpower mode for Exynos3250 based on Cortex-a7

[Tomasz Figa]

Hi Chanwoo,

On 25.04.2014 03:16, Chanwoo Choi wrote:
> This patch decide proper lowpower mode of either a15 or a9 according to own ID
> from Main ID register.
>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Marc Zynigier <marc.zyngier@arm.com>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
> ---
>   arch/arm/mach-exynos/hotplug.c | 19 ++++++++++++-------
>   1 file changed, 12 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
> index 5eead53..acf3119 100644
> --- a/arch/arm/mach-exynos/hotplug.c
> +++ b/arch/arm/mach-exynos/hotplug.c
> @@ -135,16 +135,21 @@ void __ref exynos_cpu_die(unsigned int cpu)
>   	int primary_part = 0;
>
>   	/*
> -	 * we're ready for shutdown now, so do it.
> -	 * Exynos4 is A9 based while Exynos5 is A15; check the CPU part
> -	 * number by reading the Main ID register and then perform the
> -	 * appropriate sequence for entering low power.
> +	 * Prepare the CPU for shutting down. The required sequence of
> +	 * operations depends on core type. CPUID part number can be used to
> +	 * determine the right way.
>   	 */
> -	asm("mrc p15, 0, %0, c0, c0, 0" : "=r"(primary_part) : : "cc");
> -	if ((primary_part & 0xfff0) == 0xc0f0)
> +	primary_part = read_cpuid_part_number();
> +
> +	switch (primary_part) {
> +	case ARM_CPU_PART_CORTEX_A7:
> +	case ARM_CPU_PART_CORTEX_A15:
>   		cpu_enter_lowpower_a15();
> -	else
> +		break;
> +	default:
>   		cpu_enter_lowpower_a9();
> +		break;
> +	}
>
>   	platform_do_lowpower(cpu, &spurious);
>
>

I have noticed Leela Krishna Amudala's patch [1] that removes this 
distinction completely and simply uses generic code. Could you check if 
this works on Exynos3250 as well? If yes, then this patch could be 
dropped and Leela's one would be enough.

[1] 
http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg29064.html

Best regards,
Tomasz

Re: [PATCHv4 4/7] ARM: EXYNOS: Enter a15 lowpower mode for Exynos3250 based on Cortex-a7

[Russell King - ARM Linux]

On Sat, Apr 26, 2014 at 02:25:03AM +0200, Tomasz Figa wrote:
> On 25.04.2014 03:16, Chanwoo Choi wrote:
>> This patch decide proper lowpower mode of either a15 or a9 according to own ID
>> from Main ID register.
>>
>> Cc: Arnd Bergmann <arnd@arndb.de>
>> Cc: Marc Zynigier <marc.zyngier@arm.com>
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
>> ---
>>   arch/arm/mach-exynos/hotplug.c | 19 ++++++++++++-------
>>   1 file changed, 12 insertions(+), 7 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
>> index 5eead53..acf3119 100644
>> --- a/arch/arm/mach-exynos/hotplug.c
>> +++ b/arch/arm/mach-exynos/hotplug.c
>> @@ -135,16 +135,21 @@ void __ref exynos_cpu_die(unsigned int cpu)
>>   	int primary_part = 0;
>>
>>   	/*
>> -	 * we're ready for shutdown now, so do it.
>> -	 * Exynos4 is A9 based while Exynos5 is A15; check the CPU part
>> -	 * number by reading the Main ID register and then perform the
>> -	 * appropriate sequence for entering low power.
>> +	 * Prepare the CPU for shutting down. The required sequence of
>> +	 * operations depends on core type. CPUID part number can be used to
>> +	 * determine the right way.
>>   	 */
>> -	asm("mrc p15, 0, %0, c0, c0, 0" : "=r"(primary_part) : : "cc");
>> -	if ((primary_part & 0xfff0) == 0xc0f0)
>> +	primary_part = read_cpuid_part_number();
>> +
>> +	switch (primary_part) {
>> +	case ARM_CPU_PART_CORTEX_A7:
>> +	case ARM_CPU_PART_CORTEX_A15:

Although I believe we're approaching the point where everyone just uses
ARM Ltd designed CPUs, it should be remembered that the part number
field is designer specific, so if we were being strict, we'd check both
the part number and the designer fields together.

-- 
FTTC broadband for 0.8mile line: now at 9.7Mbps down 460kbps up... slowly
improving, and getting towards what was expected from it.

Re: [PATCHv4 5/7] clk: samsung: exynos3250: Add clocks using common clock framework

[Tomasz Figa]

Hi Chanwoo,

On 25.04.2014 03:16, Chanwoo Choi wrote:
> From: Tomasz Figa <t.figa@samsung.com>
>
> This patch add new the clock drvier of Exynos3250 SoC based on Cortex-A7
> using common clock framework. The CMU (Clock Management Unit) of Exynos3250
> control PLLs(Phase Locked Loops) and generate system clocks for CPU, buses,
> and function clocks for individual IPs.
>
> The CMU of Exynos3250 includes following clock doamins:
> - CPU block for Cortex-A7 MPCore processor
> - LEFTBUS/RIGHTBUS block
> - TOP block for G3D/MFC/LCD0/ISP/CAM/FSYS/MFC/PERIL/PERIR

In original driver present in our internal tree I have separated several 
CMUs to account for certain factors caused by hardware design, which 
require such separation. Is there any reason why they were merged 
together into a single CMU again?

>
> Cc: Mike Turquette <mturquette@linaro.org>
> Cc: Kukjin Kim <kgene.kim@samsung.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Pawel Moll <pawel.moll@arm.com>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
> Cc: Kumar Gala <galak@codeaurora.org>
> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Signed-off-by: Hyunhee Kim <hyunhee.kim@samsung.com>
> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> Signed-off-by: Inki Dae <inki.dae@samsung.com>
> Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
> Signed-off-by: Karol Wrona <k.wrona@samsung.com>
> Signed-off-by: YoungJun Cho <yj44.cho@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> ---
>   drivers/clk/samsung/Makefile           |   1 +
>   drivers/clk/samsung/clk-exynos3250.c   | 785 +++++++++++++++++++++++++++++++++
>   include/dt-bindings/clock/exynos3250.h | 256 +++++++++++
>   3 files changed, 1042 insertions(+)
>   create mode 100644 drivers/clk/samsung/clk-exynos3250.c
>   create mode 100644 include/dt-bindings/clock/exynos3250.h
>
> diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
> index 8eb4799..d120797 100644
> --- a/drivers/clk/samsung/Makefile
> +++ b/drivers/clk/samsung/Makefile
> @@ -3,6 +3,7 @@
>   #
>
>   obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-pll.o
> +obj-$(CONFIG_SOC_EXYNOS3250)	+= clk-exynos3250.o
>   obj-$(CONFIG_ARCH_EXYNOS4)	+= clk-exynos4.o
>   obj-$(CONFIG_SOC_EXYNOS5250)	+= clk-exynos5250.o
>   obj-$(CONFIG_SOC_EXYNOS5420)	+= clk-exynos5420.o
> diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
> new file mode 100644
> index 0000000..0574a76
> --- /dev/null
> +++ b/drivers/clk/samsung/clk-exynos3250.c
> @@ -0,0 +1,785 @@
> +/*
> + * Copyright (c) 2014 Samsung Electronics Co., Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * Common Clock Framework support for Exynos3250 SoC.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clkdev.h>
> +#include <linux/clk-provider.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/syscore_ops.h>
> +
> +#include <dt-bindings/clock/exynos3250.h>
> +
> +#include "clk.h"
> +#include "clk-pll.h"
> +
> +#define SRC_LEFTBUS		0x4200
> +#define DIV_LEFTBUS		0x4500
> +#define GATE_IP_LEFTBUS		0x4800
> +#define SRC_RIGHTBUS		0x8200
> +#define DIV_RIGHTBUS		0x8500
> +#define GATE_IP_RIGHTBUS	0x8800
> +#define GATE_IP_PERIR		0x8960
> +#define MPLL_LOCK		0xc010
> +#define MPLL_CON0		0xc110
> +#define VPLL_LOCK		0xc020
> +#define VPLL_CON0		0xc120
> +#define UPLL_LOCK		0xc030
> +#define UPLL_CON0		0xc130
> +#define SRC_TOP0		0xc210
> +#define SRC_TOP1		0xc214
> +#define SRC_CAM			0xc220
> +#define SRC_MFC			0xc228
> +#define SRC_G3D			0xc22c
> +#define SRC_LCD			0xc234
> +#define SRC_ISP			0xc238
> +#define SRC_FSYS		0xc240
> +#define SRC_PERIL0		0xc250
> +#define SRC_PERIL1		0xc254
> +#define SRC_MASK_TOP		0xc310
> +#define SRC_MASK_CAM		0xc320
> +#define SRC_MASK_LCD		0xc334
> +#define SRC_MASK_ISP		0xc338
> +#define SRC_MASK_FSYS		0xc340
> +#define SRC_MASK_PERIL0		0xc350
> +#define SRC_MASK_PERIL1		0xc354
> +#define DIV_TOP			0xc510
> +#define DIV_CAM			0xc520
> +#define DIV_MFC			0xc528
> +#define DIV_G3D			0xc52c
> +#define DIV_LCD			0xc534
> +#define DIV_ISP			0xc538
> +#define DIV_FSYS0		0xc540
> +#define DIV_FSYS1		0xc544
> +#define DIV_FSYS2		0xc548
> +#define DIV_PERIL0		0xc550
> +#define DIV_PERIL1		0xc554
> +#define DIV_PERIL3		0xc55c
> +#define DIV_PERIL4		0xc560
> +#define DIV_PERIL5		0xc564
> +#define DIV_CAM1		0xc568
> +#define CLKDIV2_RATIO		0xc580
> +#define GATE_SCLK_CAM		0xc820
> +#define GATE_SCLK_MFC		0xc828
> +#define GATE_SCLK_G3D		0xc82c
> +#define GATE_SCLK_LCD		0xc834
> +#define GATE_SCLK_ISP_TOP	0xc838
> +#define GATE_SCLK_FSYS		0xc840
> +#define GATE_SCLK_PERIL		0xc850
> +#define GATE_IP_CAM		0xc920
> +#define GATE_IP_MFC		0xc928
> +#define GATE_IP_G3D		0xc92c
> +#define GATE_IP_LCD		0xc934
> +#define GATE_IP_ISP		0xc938
> +#define GATE_IP_FSYS		0xc940
> +#define GATE_IP_PERIL		0xc950
> +#define GATE_BLOCK		0xc970
> +#define APLL_LOCK		0x14000
> +#define APLL_CON0		0x14100
> +#define SRC_CPU			0x14200
> +#define DIV_CPU0		0x14500
> +#define DIV_CPU1		0x14504
> +
> +/* list of PLLs to be registered */
> +enum exynos3250_plls {
> +	apll, mpll, vpll, upll,
> +	nr_plls
> +};
> +
> +void __iomem *reg_base;

static void

> +
> +/*
> + * Support for CMU save/restore across system suspends
> + */
> +#ifdef CONFIG_PM_SLEEP
> +static struct samsung_clk_reg_dump *exynos3250_clk_regs;
> +
> +static unsigned long exynos3250_cmu_clk_regs[] __initdata = {
> +	SRC_LEFTBUS,
> +	DIV_LEFTBUS,
> +	GATE_IP_LEFTBUS,
> +	SRC_RIGHTBUS,
> +	DIV_RIGHTBUS,
> +	GATE_IP_RIGHTBUS,
> +	GATE_IP_PERIR,
> +	MPLL_LOCK,
> +	MPLL_CON0,
> +	VPLL_LOCK,
> +	VPLL_CON0,
> +	UPLL_LOCK,
> +	UPLL_CON0,
> +	SRC_TOP0,
> +	SRC_TOP1,
> +	SRC_CAM,
> +	SRC_MFC,
> +	SRC_G3D,
> +	SRC_LCD,
> +	SRC_ISP,
> +	SRC_FSYS,
> +	SRC_PERIL0,
> +	SRC_PERIL1,
> +	SRC_MASK_TOP,
> +	SRC_MASK_CAM,
> +	SRC_MASK_LCD,
> +	SRC_MASK_ISP,
> +	SRC_MASK_FSYS,
> +	SRC_MASK_PERIL0,
> +	SRC_MASK_PERIL1,
> +	DIV_TOP,
> +	DIV_CAM,
> +	DIV_MFC,
> +	DIV_G3D,
> +	DIV_LCD,
> +	DIV_ISP,
> +	DIV_FSYS0,
> +	DIV_FSYS1,
> +	DIV_FSYS2,
> +	DIV_PERIL0,
> +	DIV_PERIL1,
> +	DIV_PERIL3,
> +	DIV_PERIL4,
> +	DIV_PERIL5,
> +	DIV_CAM1,
> +	CLKDIV2_RATIO,
> +	GATE_SCLK_CAM,
> +	GATE_SCLK_MFC,
> +	GATE_SCLK_G3D,
> +	GATE_SCLK_LCD,
> +	GATE_SCLK_ISP_TOP,
> +	GATE_SCLK_FSYS,
> +	GATE_SCLK_PERIL,
> +	GATE_IP_CAM,
> +	GATE_IP_MFC,
> +	GATE_IP_G3D,
> +	GATE_IP_LCD,
> +	GATE_IP_ISP,
> +	GATE_IP_FSYS,
> +	GATE_IP_PERIL,
> +	GATE_BLOCK,
> +	APLL_LOCK,
> +	SRC_CPU,
> +	DIV_CPU0,
> +	DIV_CPU1,
> +};
> +
> +static int exynos3250_clk_suspend(void)
> +{
> +	samsung_clk_save(reg_base, exynos3250_clk_regs,
> +				ARRAY_SIZE(exynos3250_cmu_clk_regs));
> +	return 0;
> +}
> +
> +static void exynos3250_clk_resume(void)
> +{
> +	samsung_clk_restore(reg_base, exynos3250_clk_regs,
> +				ARRAY_SIZE(exynos3250_cmu_clk_regs));
> +}
> +
> +static struct syscore_ops exynos3250_clk_syscore_ops = {
> +	.suspend = exynos3250_clk_suspend,
> +	.resume = exynos3250_clk_resume,
> +};
> +
> +static void exynos3250_clk_sleep_init(void)
> +{
> +	exynos3250_clk_regs =
> +		samsung_clk_alloc_reg_dump(exynos3250_cmu_clk_regs,
> +					   ARRAY_SIZE(exynos3250_cmu_clk_regs));
> +	if (!exynos3250_clk_regs) {
> +		pr_warn("%s: Failed to allocate sleep save data\n", __func__);
> +		goto err;
> +	}
> +
> +	register_syscore_ops(&exynos3250_clk_syscore_ops);
> +	return;
> +err:
> +	kfree(exynos3250_clk_regs);
> +}
> +#else
> +static inline void exynos3250_clk_sleep_init(void) { }
> +#endif
> +
> +/* list of all parent clock list */
> +PNAME(mout_vpllsrc_p)		= { "fin_pll", };
> +
> +PNAME(mout_apll_p)		= { "fin_pll", "fout_apll", };
> +PNAME(mout_mpll_p)		= { "fin_pll", "fout_mpll", };
> +PNAME(mout_vpll_p)		= { "fin_pll", "fout_vpll", };
> +PNAME(mout_upll_p)		= { "fin_pll", "fout_upll", };
> +
> +PNAME(mout_mpll_user_p)		= { "fin_pll", "div_mpll_pre", };
> +PNAME(mout_epll_user_p)		= { "fin_pll", "mout_epll", };
> +PNAME(mout_core_p)		= { "mout_apll", "mout_mpll_user_c", };
> +PNAME(mout_hpm_p)		= { "mout_apll", "mout_mpll_user_c", };
> +
> +PNAME(mout_ebi_p)		= { "div_aclk_200", "div_aclk_160", };
> +PNAME(mout_ebi_1_p)		= { "mout_ebi", "mout_vpll", };
> +
> +PNAME(mout_gdl_p)		= { "mout_mpll_user_l", };
> +PNAME(mout_gdr_p)		= { "mout_mpll_user_r", };
> +
> +PNAME(mout_aclk_400_mcuisp_sub_p)
> +				= { "fin_pll", "div_aclk_400_mcuisp", };
> +PNAME(mout_aclk_266_0_p)	= { "div_mpll_pre", "mout_vpll", };
> +PNAME(mout_aclk_266_1_p)	= { "mout_epll_user", };
> +PNAME(mout_aclk_266_p)		= { "mout_aclk_266_0", "mout_aclk_266_1", };
> +PNAME(mout_aclk_266_sub_p)	= { "fin_pll", "div_aclk_266", };
> +
> +PNAME(group_div_mpll_pre_p)	= { "div_mpll_pre", };
> +PNAME(group_epll_vpll_p)	= { "mout_epll_user", "mout_vpll" };
> +PNAME(group_sclk_p)		= { "xxti", "xusbxti",
> +				    "none", "none",
> +				    "none", "none", "div_mpll_pre",
> +				    "mout_epll_user", "mout_vpll", };
> +PNAME(group_sclk_audio_p)	= { "audiocdclk", "none",
> +				    "none", "none",
> +				    "xxti", "xusbxti",
> +				    "div_mpll_pre", "mout_epll_user",
> +				    "mout_vpll", };
> +PNAME(group_sclk_cam_blk_p)	= { "xxti", "xusbxti",
> +				    "none", "none", "none",
> +				    "none", "div_mpll_pre",
> +				    "mout_epll_user", "mout_vpll",
> +				    "div_cam_blk_320", };
> +PNAME(group_sclk_fimd0_p)	= { "xxti", "xusbxti",
> +				    "m_bitclkhsdiv4_2l", "none",
> +				    "none", "none", "div_mpll_pre",
> +				    "mout_epll_user", "mout_vpll",
> +				    "none", "none", "none",
> +				    "div_lcd_blk_145", };
> +
> +PNAME(mout_mfc_p)		= { "mout_mfc_0", "mout_mfc_1" };
> +PNAME(mout_g3d_p)		= { "mout_g3d_0", "mout_g3d_1" };
> +
> +static struct samsung_fixed_rate_clock fixed_rate_clks[] __initdata = {
> +};

Any reason to have this empty array at all?

> +
> +static struct samsung_fixed_factor_clock fixed_factor_clks[] __initdata = {
> +	FFACTOR(0, "sclk_mpll_1600", "mout_mpll", 1, 1, 0),
> +	FFACTOR(0, "sclk_mpll_mif", "mout_mpll", 1, 2, 0),
> +	FFACTOR(0, "sclk_bpll", "fout_bpll", 1, 2, 0),
> +	FFACTOR(0, "div_cam_blk_320", "sclk_mpll_1600", 1, 5, 0),
> +	FFACTOR(0, "div_lcd_blk_145", "sclk_mpll_1600", 1, 11, 0),
> +
> +	FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0),

This is a hack. The real "fin_pll" is a mux driven by XOM pin which 
selects which clock input is used as main system oscillator. It should 
be implemented properly in this driver or at least appropriate comment 
should be added stressing the fact that it is a hack.

> +};
> +
> +static struct samsung_mux_clock mux_clks[] __initdata = {
> +	/*
> +	 * NOTE: Following table is sorted by register address in ascending
> +	 * order and then bitfield shift in descending order, as it is done
> +	 * in the User's Manual. When adding new entries, please make sure
> +	 * that the order is preserved, to avoid merge conflicts and make
> +	 * further work with defined data easier.
> +	 */
> +
> +	/* SRC_LEFTBUS */
> +	MUX(CLK_MOUT_MPLL_USER_L, "mout_mpll_user_l", mout_mpll_user_p,
> +	    SRC_LEFTBUS, 4, 1),
> +	MUX(CLK_MOUT_GDL, "mout_gdl", mout_gdl_p, SRC_LEFTBUS, 0, 1),
> +
> +	/* SRC_RIGHTBUS */
> +	MUX(CLK_MOUT_MPLL_USER_R, "mout_mpll_user_r", mout_mpll_user_p,
> +	    SRC_RIGHTBUS, 4, 1),
> +	MUX(CLK_MOUT_GDR, "mout_gdr", mout_gdr_p, SRC_RIGHTBUS, 0, 1),
> +
> +	/* SRC_TOP0 */
> +	MUX(CLK_MOUT_EBI, "mout_ebi", mout_ebi_p, SRC_TOP0, 28, 1),
> +	MUX(CLK_MOUT_ACLK_200, "mout_aclk_200", group_div_mpll_pre_p,SRC_TOP0, 24, 1),
> +	MUX(CLK_MOUT_ACLK_160, "mout_aclk_160", group_div_mpll_pre_p, SRC_TOP0, 20, 1),
> +	MUX(CLK_MOUT_ACLK_100, "mout_aclk_100", group_div_mpll_pre_p, SRC_TOP0, 16, 1),
> +	MUX(CLK_MOUT_ACLK_266_1, "mout_aclk_266_1", mout_aclk_266_1_p, SRC_TOP0, 14, 1),
> +	MUX(CLK_MOUT_ACLK_266_0, "mout_aclk_266_0", mout_aclk_266_0_p, SRC_TOP0, 13, 1),
> +	MUX(CLK_MOUT_ACLK_266, "mout_aclk_266", mout_aclk_266_p, SRC_TOP0, 12, 1),
> +	MUX(CLK_MOUT_VPLL, "mout_vpll", mout_vpll_p, SRC_TOP0, 8, 1),
> +	MUX(CLK_MOUT_EPLL_USER, "mout_epll_user", mout_epll_user_p, SRC_TOP0, 4, 1),
> +	MUX(CLK_MOUT_EBI_1, "mout_ebi_1", mout_ebi_1_p, SRC_TOP0, 0, 1),
> +
> +	/* SRC_TOP1 */
> +	MUX(CLK_MOUT_UPLL, "mout_upll", mout_upll_p, SRC_TOP1, 28, 1),
> +	MUX(CLK_MOUT_ACLK_400_MCUISP_SUB, "mout_aclk_400_mcuisp_sub", mout_aclk_400_mcuisp_sub_p,
> +		SRC_TOP1, 24, 1),
> +	MUX(CLK_MOUT_ACLK_266_SUB, "mout_aclk_266_sub", mout_aclk_266_sub_p, SRC_TOP1, 20, 1),
> +	MUX(CLK_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_TOP1, 12, 1),
> +	MUX(CLK_MOUT_ACLK_400_MCUISP, "mout_aclk_400_mcuisp", group_div_mpll_pre_p, SRC_TOP1, 8, 1),
> +	MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
> +
> +	/* SRC_CAM */
> +	MUX(CLK_MOUT_CAM1, "mout_cam1", group_sclk_p, SRC_CAM, 20, 4),
> +	MUX(CLK_MOUT_CAM_BLK, "mout_cam_blk", group_sclk_cam_blk_p, SRC_CAM, 0, 4),
> +
> +	/* SRC_MFC */
> +	MUX(CLK_MOUT_MFC, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
> +	MUX(CLK_MOUT_MFC_1, "mout_mfc_1", group_epll_vpll_p, SRC_MFC, 4, 1),
> +	MUX(CLK_MOUT_MFC_0, "mout_mfc_0", group_div_mpll_pre_p, SRC_MFC, 0, 1),
> +
> +	/* SRC_G3D */
> +	MUX(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1),
> +	MUX(CLK_MOUT_G3D_1, "mout_g3d_1", group_epll_vpll_p, SRC_G3D, 4, 1),
> +	MUX(CLK_MOUT_G3D_0, "mout_g3d_0", group_div_mpll_pre_p, SRC_G3D, 0, 1),
> +
> +	/* SRC_LCD */
> +	MUX(CLK_MOUT_MIPI0, "mout_mipi0", group_sclk_p, SRC_LCD, 12, 4),
> +	MUX(CLK_MOUT_FIMD0, "mout_fimd0", group_sclk_fimd0_p, SRC_LCD, 0, 4),
> +
> +	/* SRC_ISP */
> +	MUX(CLK_MOUT_UART_ISP, "mout_uart_isp", group_sclk_p, SRC_ISP, 12, 4),
> +	MUX(CLK_MOUT_SPI1_ISP, "mout_spi1_isp", group_sclk_p, SRC_ISP, 8, 4),
> +	MUX(CLK_MOUT_SPI0_ISP, "mout_spi0_isp", group_sclk_p, SRC_ISP, 4, 4),
> +
> +	/* SRC_FSYS */
> +	MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),
> +	MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 3),
> +	MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 3),
> +
> +	/* SRC_PERIL0 */
> +	MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),
> +	MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),
> +
> +	/* SRC_PERIL1 */
> +	MUX(CLK_MOUT_SPI1, "mout_spi1", group_sclk_p, SRC_PERIL1, 20, 4),
> +	MUX(CLK_MOUT_SPI0, "mout_spi0", group_sclk_p, SRC_PERIL1, 16, 4),
> +	MUX(CLK_MOUT_AUDIO, "mout_audio", group_sclk_audio_p, SRC_PERIL1, 4, 4),
> +
> +	/* SRC_CPU */
> +	MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p,
> +	    SRC_CPU, 24, 1),
> +	MUX(CLK_MOUT_HPM, "mout_hpm", mout_hpm_p, SRC_CPU, 20, 1),
> +	MUX(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1),
> +	MUX(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
> +};
> +
> +static struct samsung_div_clock div_clks[] __initdata = {
> +	/*
> +	 * NOTE: Following table is sorted by register address in ascending
> +	 * order and then bitfield shift in descending order, as it is done
> +	 * in the User's Manual. When adding new entries, please make sure
> +	 * that the order is preserved, to avoid merge conflicts and make
> +	 * further work with defined data easier.
> +	 */
> +
> +	/* DIV_LEFTBUS */
> +	DIV(CLK_DIV_GPL, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
> +	DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 4),
> +
> +	/* DIV_RIGHTBUS */
> +	DIV(CLK_DIV_GPR, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
> +	DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 4),
> +
> +	/* DIV_TOP */
> +	DIV(CLK_DIV_MPLL_PRE, "div_mpll_pre", "sclk_mpll_mif", DIV_TOP, 28, 2),
> +	DIV(CLK_DIV_ACLK_400_MCUISP, "div_aclk_400_mcuisp",
> +	    "mout_aclk_400_mcuisp", DIV_TOP, 24, 3),
> +	DIV(CLK_DIV_EBI, "div_ebi", "mout_ebi_1", DIV_TOP, 16, 3),
> +	DIV(CLK_DIV_ACLK_200, "div_aclk_200", "mout_aclk_200", DIV_TOP, 12, 3),
> +	DIV(CLK_DIV_ACLK_160, "div_aclk_160", "mout_aclk_160", DIV_TOP, 8, 3),
> +	DIV(CLK_DIV_ACLK_100, "div_aclk_100", "mout_aclk_100", DIV_TOP, 4, 4),
> +	DIV(CLK_DIV_ACLK_266, "div_aclk_266", "mout_aclk_266", DIV_TOP, 0, 3),
> +
> +	/* DIV_CAM */
> +	DIV(CLK_DIV_CAM1, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
> +	DIV(CLK_DIV_CAM_BLK, "div_cam_blk", "mout_cam_blk", DIV_CAM, 0, 4),
> +
> +	/* DIV_MFC */
> +	DIV(CLK_DIV_MFC, "div_mfc", "mout_mfc", DIV_MFC, 0, 4),
> +
> +	/* DIV_G3D */
> +	DIV(CLK_DIV_G3D, "div_g3d", "mout_g3d", DIV_G3D, 0, 4),
> +
> +	/* DIV_LCD */
> +	DIV_F(CLK_DIV_MIPI0_PRE, "div_mipi0_pre", "div_mipi0", DIV_LCD, 20, 4,
> +		CLK_SET_RATE_PARENT, 0),
> +	DIV(CLK_DIV_MIPI0, "div_mipi0", "mout_mipi0", DIV_LCD, 16, 4),
> +	DIV(CLK_DIV_FIMD0, "div_fimd0", "mout_fimd0", DIV_LCD, 0, 4),
> +
> +	/* DIV_ISP */
> +	DIV(CLK_DIV_UART_ISP, "div_uart_isp", "mout_uart_isp", DIV_ISP, 28, 4),
> +	DIV_F(CLK_DIV_SPI1_ISP_PRE, "div_spi1_isp_pre", "div_spi1_isp",
> +		DIV_ISP, 20, 8, CLK_SET_RATE_PARENT, 0),
> +	DIV(CLK_DIV_SPI1_ISP, "div_spi1_isp", "mout_spi1_isp", DIV_ISP, 16, 4),
> +	DIV_F(CLK_DIV_SPI0_ISP_PRE, "div_spi0_isp_pre", "div_spi0_isp",
> +		DIV_ISP, 8, 8, CLK_SET_RATE_PARENT, 0),
> +	DIV(CLK_DIV_SPI0_ISP, "div_spi0_isp", "mout_spi0_isp", DIV_ISP, 0, 4),
> +
> +	/* DIV_FSYS0 */
> +	DIV_F(CLK_DIV_TSADC_PRE, "div_tsadc_pre", "div_tsadc", DIV_FSYS0, 8, 8,
> +		CLK_SET_RATE_PARENT, 0),
> +	DIV(CLK_DIV_TSADC, "div_tsadc", "mout_tsadc", DIV_FSYS0, 0, 4),
> +
> +	/* DIV_FSYS1 */
> +	DIV_F(CLK_DIV_MMC1_PRE, "div_mmc1_pre", "div_mmc1", DIV_FSYS1, 24, 8,
> +		CLK_SET_RATE_PARENT, 0),
> +	DIV(CLK_DIV_MMC1, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
> +	DIV_F(CLK_DIV_MMC0_PRE, "div_mmc0_pre", "div_mmc0", DIV_FSYS1, 8, 8,
> +		CLK_SET_RATE_PARENT, 0),
> +	DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
> +
> +	/* DIV_PERIL0 */
> +	DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
> +	DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
> +
> +	/* DIV_PERIL1 */
> +	DIV_F(CLK_DIV_SPI1_PRE, "div_spi1_pre", "div_spi1", DIV_PERIL1, 24, 8,
> +		CLK_SET_RATE_PARENT, 0),
> +	DIV(CLK_DIV_SPI1, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
> +	DIV_F(CLK_DIV_SPI0_PRE, "div_spi0_pre", "div_spi0", DIV_PERIL1, 8, 8,
> +		CLK_SET_RATE_PARENT, 0),
> +	DIV(CLK_DIV_SPI0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
> +
> +	/* DIV_PERIL4 */
> +	DIV(CLK_DIV_PCM, "div_pcm", "div_audio", DIV_PERIL4, 20, 8),
> +	DIV(CLK_DIV_AUDIO, "div_audio", "mout_audio", DIV_PERIL4, 16, 4),
> +
> +	/* DIV_PERIL5 */
> +	DIV(CLK_DIV_I2S, "div_i2s", "div_audio", DIV_PERIL5, 8, 6),
> +
> +	/* DIV_CPU0 */
> +	DIV(CLK_DIV_CORE2, "div_core2", "div_core", DIV_CPU0, 28, 3),
> +	DIV(CLK_DIV_APLL, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
> +	DIV(CLK_DIV_PCLK_DBG, "div_pclk_dbg", "div_core2", DIV_CPU0, 20, 3),
> +	DIV(CLK_DIV_ATB, "div_atb", "div_core2", DIV_CPU0, 16, 3),
> +	DIV(CLK_DIV_COREM, "div_corem", "div_core2", DIV_CPU0, 4, 3),
> +	DIV(CLK_DIV_CORE, "div_core", "mout_core", DIV_CPU0, 0, 3),
> +
> +	/* DIV_CPU1 */
> +	DIV(CLK_DIV_HPM, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
> +	DIV(CLK_DIV_COPY, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
> +};
> +
> +static struct samsung_gate_clock gate_clks[] __initdata = {
> +	/*
> +	 * NOTE: Following table is sorted by register address in ascending
> +	 * order and then bitfield shift in descending order, as it is done
> +	 * in the User's Manual. When adding new entries, please make sure
> +	 * that the order is preserved, to avoid merge conflicts and make
> +	 * further work with defined data easier.
> +	 */
> +
> +	/* GATE_IP_LEFTBUS */
> +	GATE(CLK_ASYNC_G3D, "async_g3d", "div_aclk_100", GATE_IP_LEFTBUS, 6,
> +		CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_ASYNC_MFCL, "async_mfcl", "div_aclk_100", GATE_IP_LEFTBUS, 4,
> +		CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_PPMULEFT, "ppmuleft", "div_aclk_100", GATE_IP_LEFTBUS, 1,
> +		CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_GPIO_LEFT, "gpio_left", "div_aclk_100", GATE_IP_LEFTBUS, 0,
> +		CLK_IGNORE_UNUSED, 0),
> +
> +	/* GATE_IP_RIGHTBUS */
> +	GATE(CLK_ASYNC_ISPMX, "async_ispmx", "div_aclk_100",
> +		GATE_IP_RIGHTBUS, 9, CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_ASYNC_FSYSD, "async_fsysd", "div_aclk_100",
> +		GATE_IP_RIGHTBUS, 5, CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_ASYNC_LCD0X, "async_lcd0x", "div_aclk_100",
> +		GATE_IP_RIGHTBUS, 3, CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_ASYNC_CAMX, "async_camx", "div_aclk_100", GATE_IP_RIGHTBUS, 2,
> +		CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_PPMURIGHT, "ppmuright", "div_aclk_100", GATE_IP_RIGHTBUS, 1,
> +		CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_GPIO_RIGHT, "gpio_right", "div_aclk_100", GATE_IP_RIGHTBUS, 0,
> +		CLK_IGNORE_UNUSED, 0),
> +
> +	/* GATE_IP_PERIR */
> +	GATE(CLK_MONOCNT, "monocnt", "div_aclk_100", GATE_IP_PERIR, 22,
> +		CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_TZPC6, "tzpc6", "div_aclk_100", GATE_IP_PERIR, 21,
> +		CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_PROVISIONKEY1, "provisionkey1", "div_aclk_100",
> +		GATE_IP_PERIR, 20, CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_PROVISIONKEY0, "provisionkey0", "div_aclk_100",
> +		GATE_IP_PERIR, 19, CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_CMU_ISPPART, "cmu_isppart", "div_aclk_100", GATE_IP_PERIR, 18,
> +		CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_TMU_APBIF, "tmu_apbif", "div_aclk_100",
> +		GATE_IP_PERIR, 17, 0, 0),
> +	GATE(CLK_KEYIF, "keyif", "div_aclk_100", GATE_IP_PERIR, 16, 0, 0),
> +	GATE(CLK_RTC, "rtc", "div_aclk_100", GATE_IP_PERIR, 15, 0, 0),
> +	GATE(CLK_WDT, "wdt", "div_aclk_100", GATE_IP_PERIR, 14, 0, 0),
> +	GATE(CLK_MCT, "mct", "div_aclk_100", GATE_IP_PERIR, 13, 0, 0),
> +	GATE(CLK_SECKEY, "seckey", "div_aclk_100", GATE_IP_PERIR, 12,
> +		CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_TZPC5, "tzpc5", "div_aclk_100", GATE_IP_PERIR, 10,
> +		CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_TZPC4, "tzpc4", "div_aclk_100", GATE_IP_PERIR, 9,
> +		CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_TZPC3, "tzpc3", "div_aclk_100", GATE_IP_PERIR, 8,
> +		CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_TZPC2, "tzpc2", "div_aclk_100", GATE_IP_PERIR, 7,
> +		CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_TZPC1, "tzpc1", "div_aclk_100", GATE_IP_PERIR, 6,
> +		CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_TZPC0, "tzpc0", "div_aclk_100", GATE_IP_PERIR, 5,
> +		CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_CMU_COREPART, "cmu_corepart", "div_aclk_100", GATE_IP_PERIR, 4,
> +		CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_CMU_TOPPART, "cmu_toppart", "div_aclk_100", GATE_IP_PERIR, 3,
> +		CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_PMU_APBIF, "pmu_apbif", "div_aclk_100", GATE_IP_PERIR, 2,
> +		CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_SYSREG, "sysreg", "div_aclk_100", GATE_IP_PERIR, 1,
> +		CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_CHIP_ID, "chip_id", "div_aclk_100", GATE_IP_PERIR, 0,
> +		CLK_IGNORE_UNUSED, 0),
> +
> +	/* GATE_SCLK_CAM */
> +	GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_cam_blk",
> +		GATE_SCLK_CAM, 8, CLK_SET_RATE_PARENT, 0),
> +	GATE(CLK_SCLK_M2MSCALER, "sclk_m2mscaler", "div_cam_blk",
> +		GATE_SCLK_CAM, 2, CLK_SET_RATE_PARENT, 0),
> +	GATE(CLK_SCLK_GSCALER1, "sclk_gscaler1", "div_cam_blk",
> +		GATE_SCLK_CAM, 1, CLK_SET_RATE_PARENT, 0),
> +	GATE(CLK_SCLK_GSCALER0, "sclk_gscaler0", "div_cam_blk",
> +		GATE_SCLK_CAM, 0, CLK_SET_RATE_PARENT, 0),
> +
> +	/* GATE_SCLK_MFC */
> +	GATE(CLK_SCLK_MFC, "sclk_mfc", "div_mfc",
> +		GATE_SCLK_MFC, 0, CLK_SET_RATE_PARENT, 0),
> +
> +	/* GATE_SCLK_G3D */
> +	GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d",
> +		GATE_SCLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
> +
> +	/* GATE_SCLK_LCD */
> +	GATE(CLK_SCLK_MIPIDPHY2L, "sclk_mipidphy2l", "div_mipi0",
> +		GATE_SCLK_LCD, 4, CLK_SET_RATE_PARENT, 0),
> +	GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi0_pre",
> +		GATE_SCLK_LCD, 3, CLK_SET_RATE_PARENT, 0),
> +	GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0",
> +		GATE_SCLK_LCD, 0, CLK_SET_RATE_PARENT, 0),
> +
> +	/* GATE_SCLK_ISP_TOP */
> +	GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
> +		GATE_SCLK_ISP_TOP, 4, CLK_SET_RATE_PARENT, 0),
> +	GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "div_uart_isp",
> +		GATE_SCLK_ISP_TOP, 3, CLK_SET_RATE_PARENT, 0),
> +	GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "div_spi1_isp",
> +		GATE_SCLK_ISP_TOP, 2, CLK_SET_RATE_PARENT, 0),
> +	GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "div_spi0_isp",
> +		GATE_SCLK_ISP_TOP, 1, CLK_SET_RATE_PARENT, 0),
> +
> +	/* GATE_SCLK_FSYS */
> +	GATE(CLK_SCLK_UPLL, "sclk_upll", "mout_upll", GATE_SCLK_FSYS, 10, 0, 0),
> +	GATE(CLK_SCLK_TSADC, "sclk_tsadc", "div_tsadc_pre",
> +		GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
> +	GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",
> +		GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),
> +	GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre",
> +		GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
> +	GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",
> +		GATE_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
> +
> +	/* GATE_SCLK_PERIL */
> +	GATE(CLK_SCLK_I2S, "sclk_i2s", "div_i2s",
> +		GATE_SCLK_PERIL, 18, CLK_SET_RATE_PARENT, 0),
> +	GATE(CLK_SCLK_PCM, "sclk_pcm", "div_pcm",
> +		GATE_SCLK_PERIL, 16, CLK_SET_RATE_PARENT, 0),
> +	GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi1_pre",
> +		GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
> +	GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
> +		GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
> +	GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
> +		GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
> +	GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
> +		GATE_SCLK_PERIL, 0, CLK_SET_RATE_PARENT, 0),
> +
> +	/* GATE_IP_CAM */
> +	GATE(CLK_QEJPEG, "qejpeg", "div_cam_blk_320", GATE_IP_CAM, 19,
> +		CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_PIXELASYNCM1, "pixelasyncm1", "div_cam_blk_320",
> +		GATE_IP_CAM, 18, CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_PIXELASYNCM0, "pixelasyncm0", "div_cam_blk_320",
> +		GATE_IP_CAM, 17, CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_PPMUCAMIF, "ppmucamif", "div_cam_blk_320",
> +		GATE_IP_CAM, 16, CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_QEM2MSCALER, "qem2mscaler", "div_cam_blk_320",
> +		GATE_IP_CAM, 14, CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_QEGSCALER1, "qegscaler1", "div_cam_blk_320",
> +		GATE_IP_CAM, 13, CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_QEGSCALER0, "qegscaler0", "div_cam_blk_320",
> +		GATE_IP_CAM, 12, CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_SMMUJPEG, "smmujpeg", "div_cam_blk_320",
> +		GATE_IP_CAM, 11, 0, 0),
> +	GATE(CLK_SMMUM2M2SCALER, "smmum2m2scaler", "div_cam_blk_320",
> +		GATE_IP_CAM, 9, 0, 0),
> +	GATE(CLK_SMMUGSCALER1, "smmugscaler1", "div_cam_blk_320",
> +		GATE_IP_CAM, 8, 0, 0),
> +	GATE(CLK_SMMUGSCALER0, "smmugscaler0", "div_cam_blk_320",
> +		GATE_IP_CAM, 7, 0, 0),
> +	GATE(CLK_JPEG, "jpeg", "div_cam_blk_320", GATE_IP_CAM, 6, 0, 0),
> +	GATE(CLK_M2MSCALER, "m2mscaler", "div_cam_blk_320",
> +		GATE_IP_CAM, 2, 0, 0),
> +	GATE(CLK_GSCALER1, "gscaler1", "div_cam_blk_320", GATE_IP_CAM, 1, 0, 0),
> +	GATE(CLK_GSCALER0, "gscaler0", "div_cam_blk_320", GATE_IP_CAM, 0, 0, 0),
> +
> +	/* GATE_IP_MFC */
> +	GATE(CLK_QEMFC, "qemfc", "div_aclk_200", GATE_IP_MFC, 5,
> +		CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_PPMUMFC_L, "ppmumfc_l", "div_aclk_200", GATE_IP_MFC, 3,
> +		CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_SMMUMFC_L, "smmumfc_l", "div_aclk_200", GATE_IP_MFC, 1, 0, 0),
> +	GATE(CLK_MFC, "mfc", "div_aclk_200", GATE_IP_MFC, 0, 0, 0),
> +
> +	/* GATE_IP_G3D */
> +	GATE(CLK_SMMUG3D, "smmug3d", "div_aclk_200", GATE_IP_G3D, 3, 0, 0),
> +	GATE(CLK_QEG3D, "qeg3d", "div_aclk_200", GATE_IP_G3D, 2,
> +		CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_PPMUG3D, "ppmug3d", "div_aclk_200", GATE_IP_G3D, 1,
> +		CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_G3D, "g3d", "div_aclk_200", GATE_IP_G3D, 0, 0, 0),
> +
> +	/* GATE_IP_LCD */
> +	GATE(CLK_QE_CH1_LCD, "qe_ch1_lcd", "div_aclk_160", GATE_IP_LCD, 7,
> +		CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_QE_CH0_LCD, "qe_ch0_lcd", "div_aclk_160", GATE_IP_LCD, 6,
> +		CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_PPMULCD0, "ppmulcd0", "div_aclk_160", GATE_IP_LCD, 5,
> +		CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_SMMUFIMD0, "smmufimd0", "div_aclk_160", GATE_IP_LCD, 4, 0, 0),
> +	GATE(CLK_DSIM0, "dsim0", "div_aclk_160", GATE_IP_LCD, 3, 0, 0),
> +	GATE(CLK_SMIES, "smies", "div_aclk_160", GATE_IP_LCD, 2, 0, 0),
> +	GATE(CLK_FIMD0, "fimd0", "div_aclk_160", GATE_IP_LCD, 0, 0, 0),
> +
> +	/* GATE_IP_ISP */
> +	GATE(CLK_CAM1, "cam1", "mout_aclk_266_sub", GATE_IP_ISP, 5, 0, 0),
> +	GATE(CLK_UART_ISP_TOP, "uart_isp_top", "mout_aclk_266_sub",
> +		GATE_IP_ISP, 3, 0, 0),
> +	GATE(CLK_SPI1_ISP_TOP, "spi1_isp_top", "mout_aclk_266_sub",
> +		GATE_IP_ISP, 2, 0, 0),
> +	GATE(CLK_SPI0_ISP_TOP, "spi0_isp_top", "mout_aclk_266_sub",
> +		GATE_IP_ISP, 1, 0, 0),
> +
> +	/* GATE_IP_FSYS */
> +	GATE(CLK_TSADC, "tsadc", "div_aclk_200", GATE_IP_FSYS, 20, 0, 0),
> +	GATE(CLK_PPMUFILE, "ppmufile", "div_aclk_200", GATE_IP_FSYS, 17,
> +		CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0),
> +	GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
> +	GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
> +	GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
> +	GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
> +	GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
> +	GATE(CLK_PDMA0, "pdma0", "div_aclk_200", GATE_IP_FSYS, 0, 0, 0),
> +
> +	/* GATE_IP_PERIL */
> +	GATE(CLK_PWM, "pwm", "div_aclk_100", GATE_IP_PERIL, 24, 0, 0),
> +	GATE(CLK_PCM, "pcm", "div_aclk_100", GATE_IP_PERIL, 23, 0, 0),
> +	GATE(CLK_I2S, "i2s", "div_aclk_100", GATE_IP_PERIL, 21, 0, 0),
> +	GATE(CLK_SPI1, "spi1", "div_aclk_100", GATE_IP_PERIL, 17, 0, 0),
> +	GATE(CLK_SPI0, "spi0", "div_aclk_100", GATE_IP_PERIL, 16, 0, 0),
> +	GATE(CLK_I2C7, "i2c7", "div_aclk_100", GATE_IP_PERIL, 13, 0, 0),
> +	GATE(CLK_I2C6, "i2c6", "div_aclk_100", GATE_IP_PERIL, 12, 0, 0),
> +	GATE(CLK_I2C5, "i2c5", "div_aclk_100", GATE_IP_PERIL, 11, 0, 0),
> +	GATE(CLK_I2C4, "i2c4", "div_aclk_100", GATE_IP_PERIL, 10, 0, 0),
> +	GATE(CLK_I2C3, "i2c3", "div_aclk_100", GATE_IP_PERIL, 9, 0, 0),
> +	GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
> +	GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
> +	GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
> +	GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
> +	GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
> +
> +	/* GATE_BLOCK */
> +	GATE(CLK_BLOCK_LCD, "block_lcd", "div_aclk_160", GATE_BLOCK, 4, 0, 0),
> +	GATE(CLK_BLOCK_G3D, "block_g3d", "div_aclk_200", GATE_BLOCK, 3, 0, 0),

Are there only 2 gate block clocks? By the way, how are they going to be 
handled by respective drivers? There is no mainline support for them 
right now, but you should be aware that adding them will cause common 
clock framework to disable them if not claimed by any driver.

> +};
> +
> +/* APLL & MPLL & BPLL & UPLL */
> +static struct samsung_pll_rate_table exynos3250_pll_rates[] = {
> +	PLL_35XX_RATE(1200000000, 400, 4, 1),
> +	PLL_35XX_RATE(1100000000, 275, 3, 1),
> +	PLL_35XX_RATE(1066000000, 533, 6, 1),
> +	PLL_35XX_RATE(1000000000, 250, 3, 1),
> +	PLL_35XX_RATE( 960000000, 320, 4, 1),
> +	PLL_35XX_RATE( 900000000, 300, 4, 1),
> +	PLL_35XX_RATE( 850000000, 425, 6, 1),
> +	PLL_35XX_RATE( 800000000, 200, 3, 1),
> +	PLL_35XX_RATE( 700000000, 175, 3, 1),
> +	PLL_35XX_RATE( 667000000, 667, 12, 1),
> +	PLL_35XX_RATE( 600000000, 400, 4, 2),
> +	PLL_35XX_RATE( 533000000, 533, 6, 2),
> +	PLL_35XX_RATE( 520000000, 260, 3, 2),
> +	PLL_35XX_RATE( 500000000, 250, 3, 2),
> +	PLL_35XX_RATE( 400000000, 200, 3, 2),
> +	PLL_35XX_RATE( 200000000, 200, 3, 3),
> +	PLL_35XX_RATE( 100000000, 200, 3, 4),
> +	{ /* sentinel */ }
> +};
> +
> +/* VPLL */
> +static struct samsung_pll_rate_table exynos3250_vpll_rates[] = {
> +	PLL_36XX_RATE(600000000, 100, 2, 1,     0),
> +	PLL_36XX_RATE(533000000, 267, 3, 2, 32668),
> +	PLL_36XX_RATE(519231000, 173, 2, 2,  5046),
> +	PLL_36XX_RATE(500000000, 250, 3, 2,     0),
> +	PLL_36XX_RATE(445500000, 149, 2, 2, 32768),
> +	PLL_36XX_RATE(445055000, 148, 2, 2, 23047),
> +	PLL_36XX_RATE(400000000, 200, 3, 2,     0),
> +	PLL_36XX_RATE(371250000, 124, 2, 2, 49512),
> +	PLL_36XX_RATE(370879000, 185, 3, 2, 28803),
> +	PLL_36XX_RATE(340000000, 170, 3, 2,     0),
> +	PLL_36XX_RATE(335000000, 112, 2, 2, 43691),
> +	PLL_36XX_RATE(333000000, 111, 2, 2,     0),
> +	PLL_36XX_RATE(330000000, 110, 2, 2,     0),
> +	PLL_36XX_RATE(320000000, 107, 2, 2, 43691),
> +	PLL_36XX_RATE(300000000, 100, 2, 2,     0),
> +	PLL_36XX_RATE(275000000, 275, 3, 3,     0),
> +	PLL_36XX_RATE(222750000, 149, 2, 3, 32768),
> +	PLL_36XX_RATE(222528000, 148, 2, 3, 23069),
> +	PLL_36XX_RATE(160000000, 160, 3, 3,     0),
> +	PLL_36XX_RATE(148500000,  99, 2, 3,     0),
> +	PLL_36XX_RATE(148352000,  99, 2, 3, 59070),
> +	PLL_36XX_RATE(108000000, 144, 2, 4,     0),
> +	PLL_36XX_RATE( 74250000,  99, 2, 4,     0),
> +	PLL_36XX_RATE( 74176000,  99, 3, 4, 59070),
> +	PLL_36XX_RATE( 54054000, 216, 3, 5, 14156),
> +	PLL_36XX_RATE( 54000000, 144, 2, 5,     0),

Are all these frequencies above calculated exactly? For correct 
operation of rate setting code, it is necessary for frequency values 
specified in these arrays to be exact, not rounded.

Best regards,
Tomasz

Re: [PATCHv4 1/7] ARM: EXYNOS: Add Exynos3250 SoC ID

[Tomasz Figa]

Hi Chanwoo,

On 25.04.2014 03:16, Chanwoo Choi wrote:
> This patch add Exynos3250's SoC ID. Exynos 3250 is System-On-Chip(SoC) that
> is based on the 32-bit RISC processor for Smartphone. Exynos3250 uses Cortex-A7
> dual cores and has a target speed of 1.0GHz.
>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
> ---
>   arch/arm/mach-exynos/Kconfig             | 22 ++++++++++++++++++++++
>   arch/arm/mach-exynos/exynos.c            |  2 ++
>   arch/arm/plat-samsung/include/plat/cpu.h | 10 ++++++++++
>   3 files changed, 34 insertions(+)

You can add my

Reviewed-by: Tomasz Figa <t.figa@samsung.com>

Best regards,
Tomasz

Re: [PATCHv4 2/7] ARM: EXYNOS: Support secondary CPU boot of Exynos4212

[Tomasz Figa]

Hi,

On 25.04.2014 03:16, Chanwoo Choi wrote:
> From: Kyungmin Park <kyungmin.park@samsung.com>
>
> This patch fix the offset of CPU boot address and change parameter of smc call
> of SMC_CMD_CPU1BOOT command for Exynos4212.
>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---
>   arch/arm/mach-exynos/firmware.c | 15 ++++++++++++++-
>   1 file changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
> index 932129e..aa01c42 100644
> --- a/arch/arm/mach-exynos/firmware.c
> +++ b/arch/arm/mach-exynos/firmware.c
> @@ -18,6 +18,8 @@
>
>   #include <mach/map.h>
>
> +#include <plat/cpu.h>
> +
>   #include "smc.h"
>
>   static int exynos_do_idle(void)
> @@ -28,13 +30,24 @@ static int exynos_do_idle(void)
>
>   static int exynos_cpu_boot(int cpu)
>   {
> +	/*
> +	 * The second parameter of SMC_CMD_CPU1BOOT command means CPU id.
> +	 * But, Exynos4212 has only one secondary CPU so second parameter
> +	 * isn't used for informing secure firmware about CPU id.
> +	 */
> +	if (soc_is_exynos4212())
> +		cpu = 0;
> +
>   	exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
>   	return 0;
>   }
>
>   static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
>   {
> -	void __iomem *boot_reg = S5P_VA_SYSRAM_NS + 0x1c + 4*cpu;
> +	void __iomem *boot_reg = S5P_VA_SYSRAM_NS + 0x1c;
> +
> +	if (!soc_is_exynos4212())
> +		boot_reg += 4*cpu;
>
>   	__raw_writel(boot_addr, boot_reg);
>   	return 0;
>

This patch should be applied independently of Exynos3250 support. 
Kukjin, what do you think?

Anyway,

Reviewed-by: Tomasz Figa <t.figa@samsung.com>

Best regards,
Tomasz

Re: [PATCHv4 7/7] ARM: dts: Add device tree sources for Exynos3250

[Tomasz Figa]

Hi Chanwoo,

On 25.04.2014 03:16, Chanwoo Choi wrote:
> From: Tomasz Figa <t.figa@samsung.com>
>
> This patch add new exynos3250.dtsi to support Exynos3250 SoC based on Cortex-A7
> dual core and includes following dt nodes:
>
> - GIC interrupt controller
> - Pinctrl to control GPIOs
> - Clock controller
> - CPU information (Cortex-A7 dual core)
> - UART to support serial port
> - MCT (Multi Core Timer)
> - ADC (Analog Digital Converter)
> - I2C/SPI bus
> - Power domain
> - PMU (Performance Monitoring Unit)
> - MSHC (Mobile Storage Host Controller)
> - PWM (Pluse Width Modulation)
> - AMBA bus
>
> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> Signed-off-by: Inki Dae <inki.dae@samsung.com>
> Signed-off-by: Hyunhee Kim <hyunhee.kim@samsung.com>
> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
> Cc: Ben Dooks <ben-linux@fluff.org>
> Cc: Kukjin Kim <kgene.kim@samsung.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Pawel Moll <pawel.moll@arm.com>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
> Cc: Kumar Gala <galak@codeaurora.org>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: devicetree@vger.kernel.org
> ---
>   arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 477 +++++++++++++++
>   arch/arm/boot/dts/exynos3250.dtsi         | 405 +++++++++++++
>   arch/arm/boot/dts/exynos4212-tizenw.dts   | 926 ++++++++++++++++++++++++++++++
>   3 files changed, 1808 insertions(+)
>   create mode 100644 arch/arm/boot/dts/exynos3250-pinctrl.dtsi
>   create mode 100644 arch/arm/boot/dts/exynos3250.dtsi
>   create mode 100644 arch/arm/boot/dts/exynos4212-tizenw.dts
>
> diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
> new file mode 100644
> index 0000000..976490b
> --- /dev/null
> +++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
> @@ -0,0 +1,477 @@
> +/*
> + * Samsung's Exynos3250 SoCs pin-mux and pin-config device tree source
> + *
> + * Copyright (c) 2014 Samsung Electronics Co., Ltd.
> + *		http://www.samsung.com
> + *
> + * Samsung's Exynos3250 SoCs pin-mux and pin-config optiosn are listed as device
> + * tree nodes are listed in this file.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +/ {
> +	pinctrl@11400000 {

Could you use references instead of re-specifying the whole tree 
hierarchy in every file a node is used?

Instead of

/ {
	pinctrl@11400000 {

	};
};

one may simply use

&pinctrl_0 {

};

You might just need to change the location of #include 
"exynos3250-pinctrl.dtsi" from top of exynos3250.dtsi to bottom of it.

> +		gpa0: gpa0 {
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +		};
> +
> +		gpa1: gpa1 {
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +		};
> +
> +		gpb: gpb {
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +		};
> +
> +		gpc0: gpc0 {
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +		};
> +
> +		gpc1: gpc1 {
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +		};
> +
> +		gpd0: gpd0 {
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +		};
> +
> +		gpd1: gpd1 {
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +		};
> +
> +		uart0_data: uart0-data {
> +			samsung,pins = "gpa0-0", "gpa0-1";
> +			samsung,pin-function = <0x2>;
> +			samsung,pin-pud = <0>;
> +			samsung,pin-drv = <0>;
> +		};
> +
> +		uart0_fctl: uart0-fctl {
> +			samsung,pins = "gpa0-2", "gpa0-3";
> +			samsung,pin-function = <2>;
> +			samsung,pin-pud = <0>;
> +			samsung,pin-drv = <0>;
> +		};
> +
> +		uart1_data: uart1-data {
> +			samsung,pins = "gpa0-4", "gpa0-5";
> +			samsung,pin-function = <2>;
> +			samsung,pin-pud = <0>;
> +			samsung,pin-drv = <0>;
> +		};
> +
> +		uart1_fctl: uart1-fctl {
> +			samsung,pins = "gpa0-6", "gpa0-7";
> +			samsung,pin-function = <2>;
> +			samsung,pin-pud = <0>;
> +			samsung,pin-drv = <0>;
> +		};
> +
> +		i2c2_bus: i2c2-bus {
> +			samsung,pins = "gpa0-6", "gpa0-7";
> +			samsung,pin-function = <3>;
> +			samsung,pin-pud = <3>;
> +			samsung,pin-drv = <0>;
> +		};
> +
> +		i2c3_bus: i2c3-bus {
> +			samsung,pins = "gpa1-2", "gpa1-3";
> +			samsung,pin-function = <3>;
> +			samsung,pin-pud = <3>;
> +			samsung,pin-drv = <0>;
> +		};
> +
> +		spi0_bus: spi0-bus {
> +			samsung,pins = "gpb-0", "gpb-2", "gpb-3";
> +			samsung,pin-function = <2>;
> +			samsung,pin-pud = <3>;
> +			samsung,pin-drv = <0>;
> +		};
> +
> +		i2c4_bus: i2c4-bus {
> +			samsung,pins = "gpb-0", "gpb-1";
> +			samsung,pin-function = <3>;
> +			samsung,pin-pud = <3>;
> +			samsung,pin-drv = <0>;
> +		};
> +
> +		spi1_bus: spi1-bus {
> +			samsung,pins = "gpb-4", "gpb-6", "gpb-7";
> +			samsung,pin-function = <2>;
> +			samsung,pin-pud = <3>;
> +			samsung,pin-drv = <0>;
> +		};
> +
> +		i2c5_bus: i2c5-bus {
> +			samsung,pins = "gpb-2", "gpb-3";
> +			samsung,pin-function = <3>;
> +			samsung,pin-pud = <3>;
> +			samsung,pin-drv = <0>;
> +		};
> +
> +		i2s2_bus: i2s2-bus {
> +			samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
> +					"gpc1-4";
> +			samsung,pin-function = <2>;
> +			samsung,pin-pud = <0>;
> +			samsung,pin-drv = <0>;
> +		};
> +
> +		pcm2_bus: pcm2-bus {
> +			samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
> +					"gpc1-4";
> +			samsung,pin-function = <3>;
> +			samsung,pin-pud = <0>;
> +			samsung,pin-drv = <0>;
> +		};
> +
> +		i2c6_bus: i2c6-bus {
> +			samsung,pins = "gpc1-3", "gpc1-4";
> +			samsung,pin-function = <4>;
> +			samsung,pin-pud = <3>;
> +			samsung,pin-drv = <0>;
> +		};
> +
> +		pwm0_out: pwm0-out {
> +			samsung,pins = "gpd0-0";
> +			samsung,pin-function = <2>;
> +			samsung,pin-pud = <0>;
> +			samsung,pin-drv = <0>;
> +		};
> +
> +		pwm1_out: pwm1-out {
> +			samsung,pins = "gpd0-1";
> +			samsung,pin-function = <2>;
> +			samsung,pin-pud = <0>;
> +			samsung,pin-drv = <0>;
> +		};
> +
> +		i2c7_bus: i2c7-bus {
> +			samsung,pins = "gpd0-2", "gpd0-3";
> +			samsung,pin-function = <3>;
> +			samsung,pin-pud = <3>;
> +			samsung,pin-drv = <0>;
> +		};
> +
> +		pwm2_out: pwm2-out {
> +			samsung,pins = "gpd0-2";
> +			samsung,pin-function = <2>;
> +			samsung,pin-pud = <0>;
> +			samsung,pin-drv = <0>;
> +		};
> +
> +		pwm3_out: pwm3-out {
> +			samsung,pins = "gpd0-3";
> +			samsung,pin-function = <2>;
> +			samsung,pin-pud = <0>;
> +			samsung,pin-drv = <0>;
> +		};
> +
> +		i2c0_bus: i2c0-bus {
> +			samsung,pins = "gpd1-0", "gpd1-1";
> +			samsung,pin-function = <2>;
> +			samsung,pin-pud = <3>;
> +			samsung,pin-drv = <0>;
> +		};
> +
> +		mipi0_clk: mipi0-clk {
> +			samsung,pins = "gpd1-0", "gpd1-1";
> +			samsung,pin-function = <3>;
> +			samsung,pin-pud = <0>;
> +			samsung,pin-drv = <0>;
> +		};
> +
> +		i2c1_bus: i2c1-bus {
> +			samsung,pins = "gpd1-2", "gpd1-3";
> +			samsung,pin-function = <2>;
> +			samsung,pin-pud = <3>;
> +			samsung,pin-drv = <0>;
> +		};
> +	};
> +
> +	pinctrl@11000000 {
> +		gpe0: gpe0 {
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +		};
> +
> +		gpe1: gpe1 {
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +		};
> +
> +		gpe2: gpe2 {
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +		};
> +
> +		gpk0: gpk0 {
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +		};
> +
> +		gpk1: gpk1 {
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +		};
> +
> +		gpk2: gpk2 {
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +		};
> +
> +		gpl0: gpl0 {
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +		};
> +
> +		gpm0: gpm0 {
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +		};
> +
> +		gpm1: gpm1 {
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +		};
> +
> +		gpm2: gpm2 {
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +		};
> +
> +		gpm3: gpm3 {
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +		};
> +
> +		gpm4: gpm4 {
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +		};
> +
> +		gpx0: gpx0 {
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +
> +			interrupt-controller;
> +			interrupt-parent = <&gic>;
> +			interrupts = <0 32 0>, <0 33 0>, <0 34 0>, <0 35 0>,
> +					<0 36 0>, <0 37 0>, <0 38 0>, <0 39 0>;
> +			#interrupt-cells = <2>;
> +		};
> +
> +		gpx1: gpx1 {
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +
> +			interrupt-controller;
> +			interrupt-parent = <&gic>;
> +			interrupts = <0 40 0>, <0 41 0>, <0 42 0>, <0 43 0>,
> +					<0 44 0>, <0 45 0>, <0 46 0>, <0 47 0>;
> +			#interrupt-cells = <2>;
> +		};
> +
> +		gpx2: gpx2 {
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +		};
> +
> +		gpx3: gpx3 {
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +		};
> +
> +		sd0_clk: sd0-clk {
> +			samsung,pins = "gpk0-0";
> +			samsung,pin-function = <2>;
> +			samsung,pin-pud = <0>;
> +			samsung,pin-drv = <3>;
> +		};
> +
> +		sd0_cmd: sd0-cmd {
> +			samsung,pins = "gpk0-1";
> +			samsung,pin-function = <2>;
> +			samsung,pin-pud = <0>;
> +			samsung,pin-drv = <3>;
> +		};
> +
> +		sd0_cd: sd0-cd {
> +			samsung,pins = "gpk0-2";
> +			samsung,pin-function = <2>;
> +			samsung,pin-pud = <3>;
> +			samsung,pin-drv = <3>;
> +		};
> +
> +		sd0_rdqs: sd0-rdqs {
> +			samsung,pins = "gpk0-7";
> +			samsung,pin-function = <2>;
> +			samsung,pin-pud = <0>;
> +			samsung,pin-drv = <3>;
> +		};
> +
> +		sd0_bus1: sd0-bus-width1 {
> +			samsung,pins = "gpk0-3";
> +			samsung,pin-function = <2>;
> +			samsung,pin-pud = <3>;
> +			samsung,pin-drv = <3>;
> +		};
> +
> +		sd0_bus4: sd0-bus-width4 {
> +			samsung,pins = "gpk0-4", "gpk0-5", "gpk0-6";
> +			samsung,pin-function = <2>;
> +			samsung,pin-pud = <3>;
> +			samsung,pin-drv = <3>;
> +		};
> +
> +		sd0_bus8: sd0-bus-width8 {
> +			samsung,pins = "gpl0-0", "gpl0-1", "gpl0-2", "gpl0-3";
> +			samsung,pin-function = <2>;
> +			samsung,pin-pud = <3>;
> +			samsung,pin-drv = <3>;
> +		};
> +
> +		sd1_clk: sd1-clk {
> +			samsung,pins = "gpk1-0";
> +			samsung,pin-function = <2>;
> +			samsung,pin-pud = <0>;
> +			samsung,pin-drv = <3>;
> +		};
> +
> +		sd1_cmd: sd1-cmd {
> +			samsung,pins = "gpk1-1";
> +			samsung,pin-function = <2>;
> +			samsung,pin-pud = <0>;
> +			samsung,pin-drv = <3>;
> +		};
> +
> +		sd1_cd: sd1-cd {
> +			samsung,pins = "gpk1-2";
> +			samsung,pin-function = <2>;
> +			samsung,pin-pud = <3>;
> +			samsung,pin-drv = <3>;
> +		};
> +
> +		sd1_bus1: sd1-bus-width1 {
> +			samsung,pins = "gpk1-3";
> +			samsung,pin-function = <2>;
> +			samsung,pin-pud = <3>;
> +			samsung,pin-drv = <3>;
> +		};
> +
> +		sd1_bus4: sd1-bus-width4 {
> +			samsung,pins = "gpk1-4", "gpk1-5", "gpk1-6";
> +			samsung,pin-function = <2>;
> +			samsung,pin-pud = <3>;
> +			samsung,pin-drv = <3>;
> +		};
> +
> +		cam_port_b_io: cam-port-b-io {
> +			samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3",
> +					"gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7",
> +					"gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1";
> +			samsung,pin-function = <3>;
> +			samsung,pin-pud = <3>;
> +			samsung,pin-drv = <0>;
> +		};
> +
> +		cam_port_b_clk_active: cam-port-b-clk-active {
> +			samsung,pins = "gpm2-2";
> +			samsung,pin-function = <3>;
> +			samsung,pin-pud = <0>;
> +			samsung,pin-drv = <3>;
> +		};
> +
> +		cam_port_b_clk_idle: cam-port-b-clk-idle {
> +			samsung,pins = "gpm2-2";
> +			samsung,pin-function = <0>;
> +			samsung,pin-pud = <0>;
> +			samsung,pin-drv = <0>;
> +		};
> +
> +		fimc_is_i2c0: fimc-is-i2c0 {
> +			samsung,pins = "gpm4-0", "gpm4-1";
> +			samsung,pin-function = <2>;
> +			samsung,pin-pud = <0>;
> +			samsung,pin-drv = <0>;
> +		};
> +
> +		fimc_is_i2c1: fimc-is-i2c1 {
> +			samsung,pins = "gpm4-2", "gpm4-3";
> +			samsung,pin-function = <2>;
> +			samsung,pin-pud = <0>;
> +			samsung,pin-drv = <0>;
> +		};
> +
> +		fimc_is_uart: fimc-is-uart {
> +			samsung,pins = "gpm3-5", "gpm3-7";
> +			samsung,pin-function = <3>;
> +			samsung,pin-pud = <0>;
> +			samsung,pin-drv = <0>;
> +		};
> +	};
> +};
> diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
> new file mode 100644
> index 0000000..5be3dd3
> --- /dev/null
> +++ b/arch/arm/boot/dts/exynos3250.dtsi
> @@ -0,0 +1,405 @@
> +/*
> + * Samsung's Exynos3250 SoC device tree source
> + *
> + * Copyright (c) 2014 Samsung Electronics Co., Ltd.
> + *		http://www.samsung.com
> + *
> + * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
> + * based board files can include this file and provide values for board specfic
> + * bindings.
> + *
> + * Note: This file does not include device nodes for all the controllers in
> + * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
> + * nodes can be added to this file.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include "skeleton.dtsi"
> +#include "exynos3250-pinctrl.dtsi"
> +#include <dt-bindings/clock/exynos3250.h>
> +
> +/ {
> +	compatible = "samsung,exynos3250";
> +	interrupt-parent = <&gic>;
> +
> +	aliases {
> +		pinctrl0 = &pinctrl_0;
> +		pinctrl1 = &pinctrl_1;
> +		mshc0 = &mshc_0;
> +		mshc1 = &mshc_1;
> +		spi0 = &spi_0;
> +		spi1 = &spi_1;
> +		i2c0 = &i2c_0;
> +		i2c1 = &i2c_1;
> +		i2c2 = &i2c_2;
> +		i2c3 = &i2c_3;
> +		i2c4 = &i2c_4;
> +		i2c5 = &i2c_5;
> +		i2c6 = &i2c_6;
> +		i2c7 = &i2c_7;
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a7";
> +			reg = <0>;
> +			clock-frequency = <1000000000>;
> +		};

Why only one CPU? I believe Exynos3250 is dual core. Also are physical 
IDs of the cores really 0 and 1? On Exynos4210 for example they are 
0x900 and 0x901, while on Exynos4212 they are 0xa00 and 0xa01. Please 
check this.

> +	};
> +
> +	fixed-rate-clocks {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		xusbxti: clock@0 {
> +			compatible = "fixed-clock";
> +			reg = <0>;
> +			clock-frequency = <0>;
> +			#clock-cells = <0>;
> +			clock-output-names = "xusbxti";
> +		};
> +
> +		xxti: clock@1 {
> +			compatible = "fixed-clock";
> +			reg = <1>;
> +			clock-frequency = <0>;
> +			#clock-cells = <0>;
> +			clock-output-names = "xxti";
> +		};
> +
> +		xtcxo: clock@2 {
> +			compatible = "fixed-clock";
> +			reg = <2>;
> +			clock-frequency = <0>;
> +			#clock-cells = <0>;
> +			clock-output-names = "xtcxo";
> +		};
> +	};
> +
> +	chipid@10000000 {
> +		compatible = "samsung,exynos4210-chipid";
> +		reg = <0x10000000 0x100>;
> +	};
> +
> +	sys_reg: syscon@10010000 {
> +		compatible = "samsung,exynos3-sysreg", "syscon";
> +		reg = <0x10010000 0x400>;
> +	};
> +
> +	pd_cam: cam-power-domain@10023C00 {
> +		compatible = "samsung,exynos4210-pd";
> +		reg = <0x10023C00 0x20>;
> +	};
> +
> +	pd_mfc: mfc-power-domain@10023C40 {
> +		compatible = "samsung,exynos4210-pd";
> +		reg = <0x10023C40 0x20>;
> +	};
> +
> +	pd_g3d: g3d-power-domain@10023C60 {
> +		compatible = "samsung,exynos4210-pd";
> +		reg = <0x10023C60 0x20>;
> +	};
> +
> +	pd_lcd0: lcd0-power-domain@10023C80 {
> +		compatible = "samsung,exynos4210-pd";
> +		reg = <0x10023C80 0x20>;
> +	};
> +
> +	pd_isp: isp-power-domain@10023CA0 {
> +		compatible = "samsung,exynos4210-pd";
> +		reg = <0x10023CA0 0x20>;
> +	};
> +
> +	cmu: clock-controller@10030000 {
> +		compatible = "samsung,exynos3250-cmu";
> +		reg = <0x10030000 0x20000>;
> +		#clock-cells = <1>;
> +	};
> +
> +	rtc@10070000 {

Please add label to the node, so it can be referenced from board dts 
files added later (using the method I explained above).

> +		compatible = "samsung,s3c6410-rtc";
> +		reg = <0x10070000 0x100>;
> +		interrupts = <0 73 0>, <0 74 0>;
> +		status = "disabled";
> +	};
> +
> +	gic: interrupt-controller@10481000 {
> +		compatible = "arm,cortex-a15-gic";
> +		#interrupt-cells = <3>;
> +		interrupt-controller;
> +		reg = <0x10481000 0x1000>,
> +		      <0x10482000 0x1000>,
> +		      <0x10484000 0x2000>,
> +		      <0x10486000 0x2000>;
> +		      interrupts = <1 9 0xf04>;
> +	};
> +
> +	mct@10050000 {
> +		compatible = "samsung,exynos4210-mct";
> +		reg = <0x10050000 0x800>;
> +		interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
> +			     <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
> +		clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
> +		clock-names = "fin_pll", "mct";
> +	};
> +
> +	pinctrl_1: pinctrl@11000000 {
> +		compatible = "samsung,exynos3250-pinctrl";
> +		reg = <0x11000000 0x1000>;
> +		interrupts = <0 225 0>;
> +
> +		wakeup-interrupt-controller {
> +			compatible = "samsung,exynos4210-wakeup-eint";
> +			interrupt-parent = <&gic>;
> +			interrupts = <0 48 0>;
> +		};
> +	};
> +
> +	pinctrl_0: pinctrl@11400000 {
> +		compatible = "samsung,exynos3250-pinctrl";
> +		reg = <0x11400000 0x1000>;
> +		interrupts = <0 240 0>;
> +	};
> +
> +	mshc_0: mshc@12510000 {
> +		compatible = "samsung,exynos5250-dw-mshc";
> +		reg = <0x12510000 0x1000>;
> +		interrupts = <0 142 0>;
> +		clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
> +		clock-names = "biu", "ciu";
> +		fifo-depth = <0x80>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		status = "disabled";
> +	};
> +
> +	mshc_1: mshc@12520000 {
> +		compatible = "samsung,exynos5250-dw-mshc";
> +		reg = <0x12520000 0x1000>;
> +		interrupts = <0 143 0>;
> +		clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
> +		clock-names = "biu", "ciu";
> +		fifo-depth = <0x80>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		status = "disabled";
> +	};
> +
> +	amba {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "arm,amba-bus";
> +		interrupt-parent = <&gic>;
> +		ranges;
> +
> +		pdma0: pdma@12680000 {
> +			compatible = "arm,pl330", "arm,primecell";
> +			reg = <0x12680000 0x1000>;
> +			interrupts = <0 138 0>;
> +			clocks = <&cmu CLK_PDMA0>;
> +			clock-names = "apb_pclk";
> +			#dma-cells = <1>;
> +			#dma-channels = <8>;
> +			#dma-requests = <32>;
> +		};
> +
> +		pdma1: pdma@12690000 {
> +			compatible = "arm,pl330", "arm,primecell";
> +			reg = <0x12690000 0x1000>;
> +			interrupts = <0 139 0>;
> +			clocks = <&cmu CLK_PDMA1>;
> +			clock-names = "apb_pclk";
> +			#dma-cells = <1>;
> +			#dma-channels = <8>;
> +			#dma-requests = <32>;
> +		};
> +	};
> +
> +	adc: adc@126C0000 {
> +		compatible = "samsung,exynos-adc-v3";
> +		reg = <0x126C0000 0x100>, <0x10020718 0x4>;
> +		interrupts = <0 137 0>;
> +		clock-names = "adc", "sclk_tsadc";
> +		clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
> +		#io-channel-cells = <1>;
> +		io-channel-ranges;
> +		status = "disabled";
> +	};
> +
> +	serial@13800000 {

Please add label.

> +		compatible = "samsung,exynos4210-uart";
> +		reg = <0x13800000 0x100>;
> +		interrupts = <0 109 0>;
> +		clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
> +		clock-names = "uart", "clk_uart_baud0";
> +		status = "disabled";
> +	};
> +
> +	serial@13810000 {

Ditto.

Best regards,
Tomasz

RE: [PATCHv4 2/7] ARM: EXYNOS: Support secondary CPU boot of Exynos4212

[Kukjin Kim]

Tomasz Figa wrote:
> 
> Hi,
> 
Hi,

> On 25.04.2014 03:16, Chanwoo Choi wrote:
> > From: Kyungmin Park <kyungmin.park@samsung.com>
> >
> > This patch fix the offset of CPU boot address and change parameter of
> smc call
> > of SMC_CMD_CPU1BOOT command for Exynos4212.
> >
> > Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> > Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> > ---
> >   arch/arm/mach-exynos/firmware.c | 15 ++++++++++++++-
> >   1 file changed, 14 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-
> exynos/firmware.c
> > index 932129e..aa01c42 100644
> > --- a/arch/arm/mach-exynos/firmware.c
> > +++ b/arch/arm/mach-exynos/firmware.c
> > @@ -18,6 +18,8 @@
> >
> >   #include <mach/map.h>
> >
> > +#include <plat/cpu.h>
> > +
> >   #include "smc.h"
> >
> >   static int exynos_do_idle(void)
> > @@ -28,13 +30,24 @@ static int exynos_do_idle(void)
> >
> >   static int exynos_cpu_boot(int cpu)
> >   {
> > +	/*
> > +	 * The second parameter of SMC_CMD_CPU1BOOT command means CPU id.
> > +	 * But, Exynos4212 has only one secondary CPU so second parameter
> > +	 * isn't used for informing secure firmware about CPU id.
> > +	 */
> > +	if (soc_is_exynos4212())
> > +		cpu = 0;
> > +
> >   	exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
> >   	return 0;
> >   }
> >
> >   static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
> >   {
> > -	void __iomem *boot_reg = S5P_VA_SYSRAM_NS + 0x1c + 4*cpu;
> > +	void __iomem *boot_reg = S5P_VA_SYSRAM_NS + 0x1c;
> > +
> > +	if (!soc_is_exynos4212())
> > +		boot_reg += 4*cpu;
> >
> >   	__raw_writel(boot_addr, boot_reg);
> >   	return 0;
> >
> 
> This patch should be applied independently of Exynos3250 support.
> Kukjin, what do you think?
> 
Yes, this should be separated. I will pick this into fixes.

> Anyway,
> 
> Reviewed-by: Tomasz Figa <t.figa@samsung.com>
> 
Thanks,
Kukjin

Re: [PATCHv4 7/7] ARM: dts: Add device tree sources for Exynos3250

[Tomasz Figa]

On 26.04.2014 02:51, Tomasz Figa wrote:
> Hi Chanwoo,
>
> On 25.04.2014 03:16, Chanwoo Choi wrote:
>> From: Tomasz Figa <t.figa@samsung.com>
>>
>> This patch add new exynos3250.dtsi to support Exynos3250 SoC based on
>> Cortex-A7
>> dual core and includes following dt nodes:
>>
>> - GIC interrupt controller
>> - Pinctrl to control GPIOs
>> - Clock controller
>> - CPU information (Cortex-A7 dual core)
>> - UART to support serial port
>> - MCT (Multi Core Timer)
>> - ADC (Analog Digital Converter)
>> - I2C/SPI bus
>> - Power domain
>> - PMU (Performance Monitoring Unit)
>> - MSHC (Mobile Storage Host Controller)
>> - PWM (Pluse Width Modulation)
>> - AMBA bus
>>
>> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>> Signed-off-by: Inki Dae <inki.dae@samsung.com>
>> Signed-off-by: Hyunhee Kim <hyunhee.kim@samsung.com>
>> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
>> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
>> Cc: Ben Dooks <ben-linux@fluff.org>
>> Cc: Kukjin Kim <kgene.kim@samsung.com>
>> Cc: Rob Herring <robh+dt@kernel.org>
>> Cc: Pawel Moll <pawel.moll@arm.com>
>> Cc: Mark Rutland <mark.rutland@arm.com>
>> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
>> Cc: Kumar Gala <galak@codeaurora.org>
>> Cc: Russell King <linux@arm.linux.org.uk>
>> Cc: devicetree@vger.kernel.org
>> ---
>>   arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 477 +++++++++++++++
>>   arch/arm/boot/dts/exynos3250.dtsi         | 405 +++++++++++++
>>   arch/arm/boot/dts/exynos4212-tizenw.dts   | 926
>> ++++++++++++++++++++++++++++++
>>   3 files changed, 1808 insertions(+)
>>   create mode 100644 arch/arm/boot/dts/exynos3250-pinctrl.dtsi
>>   create mode 100644 arch/arm/boot/dts/exynos3250.dtsi
>>   create mode 100644 arch/arm/boot/dts/exynos4212-tizenw.dts
>>
>> diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
>> b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
>> new file mode 100644
>> index 0000000..976490b
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
>> @@ -0,0 +1,477 @@
>> +/*
>> + * Samsung's Exynos3250 SoCs pin-mux and pin-config device tree source
>> + *
>> + * Copyright (c) 2014 Samsung Electronics Co., Ltd.
>> + *        http://www.samsung.com
>> + *
>> + * Samsung's Exynos3250 SoCs pin-mux and pin-config optiosn are
>> listed as device
>> + * tree nodes are listed in this file.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> +*/
>> +
>> +/ {
>> +    pinctrl@11400000 {
>
> Could you use references instead of re-specifying the whole tree
> hierarchy in every file a node is used?
>
> Instead of
>
> / {
>      pinctrl@11400000 {
>
>      };
> };
>
> one may simply use
>
> &pinctrl_0 {
>
> };
>
> You might just need to change the location of #include
> "exynos3250-pinctrl.dtsi" from top of exynos3250.dtsi to bottom of it.

Oh, well, you also should move all nodes of on-SoC devices under a 
simple-bus node called soc. You can see the patch adding dts file for 
Exynos5260 for an example [1].

[1] http://thread.gmane.org/gmane.linux.kernel.samsung-soc/29360/focus=29361

Best regards,
Tomasz

Re: [PATCHv4 4/7] ARM: EXYNOS: Enter a15 lowpower mode for Exynos3250 based on Cortex-a7

[Chanwoo Choi]

Hi Tomasz,

On 04/26/2014 09:25 AM, Tomasz Figa wrote:
> Hi Chanwoo,
> 
> On 25.04.2014 03:16, Chanwoo Choi wrote:
>> This patch decide proper lowpower mode of either a15 or a9 according to own ID
>> from Main ID register.
>>
>> Cc: Arnd Bergmann <arnd@arndb.de>
>> Cc: Marc Zynigier <marc.zyngier@arm.com>
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
>> ---
>>   arch/arm/mach-exynos/hotplug.c | 19 ++++++++++++-------
>>   1 file changed, 12 insertions(+), 7 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
>> index 5eead53..acf3119 100644
>> --- a/arch/arm/mach-exynos/hotplug.c
>> +++ b/arch/arm/mach-exynos/hotplug.c
>> @@ -135,16 +135,21 @@ void __ref exynos_cpu_die(unsigned int cpu)
>>       int primary_part = 0;
>>
>>       /*
>> -     * we're ready for shutdown now, so do it.
>> -     * Exynos4 is A9 based while Exynos5 is A15; check the CPU part
>> -     * number by reading the Main ID register and then perform the
>> -     * appropriate sequence for entering low power.
>> +     * Prepare the CPU for shutting down. The required sequence of
>> +     * operations depends on core type. CPUID part number can be used to
>> +     * determine the right way.
>>        */
>> -    asm("mrc p15, 0, %0, c0, c0, 0" : "=r"(primary_part) : : "cc");
>> -    if ((primary_part & 0xfff0) == 0xc0f0)
>> +    primary_part = read_cpuid_part_number();
>> +
>> +    switch (primary_part) {
>> +    case ARM_CPU_PART_CORTEX_A7:
>> +    case ARM_CPU_PART_CORTEX_A15:
>>           cpu_enter_lowpower_a15();
>> -    else
>> +        break;
>> +    default:
>>           cpu_enter_lowpower_a9();
>> +        break;
>> +    }
>>
>>       platform_do_lowpower(cpu, &spurious);
>>
>>
> 
> I have noticed Leela Krishna Amudala's patch [1] that removes this distinction completely and simply uses generic code. Could you check if this works on Exynos3250 as well? If yes, then this patch could be dropped and Leela's one would be enough.
> 
> [1] http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg29064.html

OK, I tested this patch[1] to turn on secondary CPu on Exynos3250.
I'll drop following patch on next posting(v5) by using Leela Krishna Amudala's patch [1].
- ARM: EXYNOS: Enter a15 lowpower mode for Exynos3250 based on Cortex-a7

Best Regards,
Chanwoo Choi

Re: [PATCHv4 7/7] ARM: dts: Add device tree sources for Exynos3250

[Chanwoo Choi]

Hi Tomasz,

On 04/26/2014 09:51 AM, Tomasz Figa wrote:
> Hi Chanwoo,
> 
> On 25.04.2014 03:16, Chanwoo Choi wrote:
>> From: Tomasz Figa <t.figa@samsung.com>
>>
>> This patch add new exynos3250.dtsi to support Exynos3250 SoC based on Cortex-A7
>> dual core and includes following dt nodes:
>>
>> - GIC interrupt controller
>> - Pinctrl to control GPIOs
>> - Clock controller
>> - CPU information (Cortex-A7 dual core)
>> - UART to support serial port
>> - MCT (Multi Core Timer)
>> - ADC (Analog Digital Converter)
>> - I2C/SPI bus
>> - Power domain
>> - PMU (Performance Monitoring Unit)
>> - MSHC (Mobile Storage Host Controller)
>> - PWM (Pluse Width Modulation)
>> - AMBA bus
>>
>> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>> Signed-off-by: Inki Dae <inki.dae@samsung.com>
>> Signed-off-by: Hyunhee Kim <hyunhee.kim@samsung.com>
>> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
>> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
>> Cc: Ben Dooks <ben-linux@fluff.org>
>> Cc: Kukjin Kim <kgene.kim@samsung.com>
>> Cc: Rob Herring <robh+dt@kernel.org>
>> Cc: Pawel Moll <pawel.moll@arm.com>
>> Cc: Mark Rutland <mark.rutland@arm.com>
>> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
>> Cc: Kumar Gala <galak@codeaurora.org>
>> Cc: Russell King <linux@arm.linux.org.uk>
>> Cc: devicetree@vger.kernel.org
>> ---
>>   arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 477 +++++++++++++++
>>   arch/arm/boot/dts/exynos3250.dtsi         | 405 +++++++++++++
>>   arch/arm/boot/dts/exynos4212-tizenw.dts   | 926 ++++++++++++++++++++++++++++++
>>   3 files changed, 1808 insertions(+)
>>   create mode 100644 arch/arm/boot/dts/exynos3250-pinctrl.dtsi
>>   create mode 100644 arch/arm/boot/dts/exynos3250.dtsi
>>   create mode 100644 arch/arm/boot/dts/exynos4212-tizenw.dts
>>
>> diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
>> new file mode 100644
>> index 0000000..976490b
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
>> @@ -0,0 +1,477 @@
>> +/*
>> + * Samsung's Exynos3250 SoCs pin-mux and pin-config device tree source
>> + *
>> + * Copyright (c) 2014 Samsung Electronics Co., Ltd.
>> + *        http://www.samsung.com
>> + *
>> + * Samsung's Exynos3250 SoCs pin-mux and pin-config optiosn are listed as device
>> + * tree nodes are listed in this file.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> +*/
>> +
>> +/ {
>> +    pinctrl@11400000 {
> 
> Could you use references instead of re-specifying the whole tree hierarchy in every file a node is used?
> 
> Instead of
> 
> / {
>     pinctrl@11400000 {
> 
>     };
> };
> 
> one may simply use
> 
> &pinctrl_0 {
> 
> };
> 
> You might just need to change the location of #include "exynos3250-pinctrl.dtsi" from top of exynos3250.dtsi to bottom of it.
> 

OK, I'll change it.

>> +        gpa0: gpa0 {
>> +            gpio-controller;
>> +            #gpio-cells = <2>;
>> +
>> +            interrupt-controller;
>> +            #interrupt-cells = <2>;
>> +        };
>> +
>> +        gpa1: gpa1 {
>> +            gpio-controller;
>> +            #gpio-cells = <2>;
>> +
>> +            interrupt-controller;
>> +            #interrupt-cells = <2>;
>> +        };
>> +
>> +        gpb: gpb {
>> +            gpio-controller;
>> +            #gpio-cells = <2>;
>> +
>> +            interrupt-controller;
>> +            #interrupt-cells = <2>;
>> +        };
>> +
>> +        gpc0: gpc0 {
>> +            gpio-controller;
>> +            #gpio-cells = <2>;
>> +
>> +            interrupt-controller;
>> +            #interrupt-cells = <2>;
>> +        };
>> +
>> +        gpc1: gpc1 {
>> +            gpio-controller;
>> +            #gpio-cells = <2>;
>> +
>> +            interrupt-controller;
>> +            #interrupt-cells = <2>;
>> +        };
>> +
>> +        gpd0: gpd0 {
>> +            gpio-controller;
>> +            #gpio-cells = <2>;
>> +
>> +            interrupt-controller;
>> +            #interrupt-cells = <2>;
>> +        };
>> +
>> +        gpd1: gpd1 {
>> +            gpio-controller;
>> +            #gpio-cells = <2>;
>> +
>> +            interrupt-controller;
>> +            #interrupt-cells = <2>;
>> +        };
>> +
>> +        uart0_data: uart0-data {
>> +            samsung,pins = "gpa0-0", "gpa0-1";
>> +            samsung,pin-function = <0x2>;
>> +            samsung,pin-pud = <0>;
>> +            samsung,pin-drv = <0>;
>> +        };
>> +
>> +        uart0_fctl: uart0-fctl {
>> +            samsung,pins = "gpa0-2", "gpa0-3";
>> +            samsung,pin-function = <2>;
>> +            samsung,pin-pud = <0>;
>> +            samsung,pin-drv = <0>;
>> +        };
>> +
>> +        uart1_data: uart1-data {
>> +            samsung,pins = "gpa0-4", "gpa0-5";
>> +            samsung,pin-function = <2>;
>> +            samsung,pin-pud = <0>;
>> +            samsung,pin-drv = <0>;
>> +        };
>> +
>> +        uart1_fctl: uart1-fctl {
>> +            samsung,pins = "gpa0-6", "gpa0-7";
>> +            samsung,pin-function = <2>;
>> +            samsung,pin-pud = <0>;
>> +            samsung,pin-drv = <0>;
>> +        };
>> +
>> +        i2c2_bus: i2c2-bus {
>> +            samsung,pins = "gpa0-6", "gpa0-7";
>> +            samsung,pin-function = <3>;
>> +            samsung,pin-pud = <3>;
>> +            samsung,pin-drv = <0>;
>> +        };
>> +
>> +        i2c3_bus: i2c3-bus {
>> +            samsung,pins = "gpa1-2", "gpa1-3";
>> +            samsung,pin-function = <3>;
>> +            samsung,pin-pud = <3>;
>> +            samsung,pin-drv = <0>;
>> +        };
>> +
>> +        spi0_bus: spi0-bus {
>> +            samsung,pins = "gpb-0", "gpb-2", "gpb-3";
>> +            samsung,pin-function = <2>;
>> +            samsung,pin-pud = <3>;
>> +            samsung,pin-drv = <0>;
>> +        };
>> +
>> +        i2c4_bus: i2c4-bus {
>> +            samsung,pins = "gpb-0", "gpb-1";
>> +            samsung,pin-function = <3>;
>> +            samsung,pin-pud = <3>;
>> +            samsung,pin-drv = <0>;
>> +        };
>> +
>> +        spi1_bus: spi1-bus {
>> +            samsung,pins = "gpb-4", "gpb-6", "gpb-7";
>> +            samsung,pin-function = <2>;
>> +            samsung,pin-pud = <3>;
>> +            samsung,pin-drv = <0>;
>> +        };
>> +
>> +        i2c5_bus: i2c5-bus {
>> +            samsung,pins = "gpb-2", "gpb-3";
>> +            samsung,pin-function = <3>;
>> +            samsung,pin-pud = <3>;
>> +            samsung,pin-drv = <0>;
>> +        };
>> +
>> +        i2s2_bus: i2s2-bus {
>> +            samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
>> +                    "gpc1-4";
>> +            samsung,pin-function = <2>;
>> +            samsung,pin-pud = <0>;
>> +            samsung,pin-drv = <0>;
>> +        };
>> +
>> +        pcm2_bus: pcm2-bus {
>> +            samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
>> +                    "gpc1-4";
>> +            samsung,pin-function = <3>;
>> +            samsung,pin-pud = <0>;
>> +            samsung,pin-drv = <0>;
>> +        };
>> +
>> +        i2c6_bus: i2c6-bus {
>> +            samsung,pins = "gpc1-3", "gpc1-4";
>> +            samsung,pin-function = <4>;
>> +            samsung,pin-pud = <3>;
>> +            samsung,pin-drv = <0>;
>> +        };
>> +
>> +        pwm0_out: pwm0-out {
>> +            samsung,pins = "gpd0-0";
>> +            samsung,pin-function = <2>;
>> +            samsung,pin-pud = <0>;
>> +            samsung,pin-drv = <0>;
>> +        };
>> +
>> +        pwm1_out: pwm1-out {
>> +            samsung,pins = "gpd0-1";
>> +            samsung,pin-function = <2>;
>> +            samsung,pin-pud = <0>;
>> +            samsung,pin-drv = <0>;
>> +        };
>> +
>> +        i2c7_bus: i2c7-bus {
>> +            samsung,pins = "gpd0-2", "gpd0-3";
>> +            samsung,pin-function = <3>;
>> +            samsung,pin-pud = <3>;
>> +            samsung,pin-drv = <0>;
>> +        };
>> +
>> +        pwm2_out: pwm2-out {
>> +            samsung,pins = "gpd0-2";
>> +            samsung,pin-function = <2>;
>> +            samsung,pin-pud = <0>;
>> +            samsung,pin-drv = <0>;
>> +        };
>> +
>> +        pwm3_out: pwm3-out {
>> +            samsung,pins = "gpd0-3";
>> +            samsung,pin-function = <2>;
>> +            samsung,pin-pud = <0>;
>> +            samsung,pin-drv = <0>;
>> +        };
>> +
>> +        i2c0_bus: i2c0-bus {
>> +            samsung,pins = "gpd1-0", "gpd1-1";
>> +            samsung,pin-function = <2>;
>> +            samsung,pin-pud = <3>;
>> +            samsung,pin-drv = <0>;
>> +        };
>> +
>> +        mipi0_clk: mipi0-clk {
>> +            samsung,pins = "gpd1-0", "gpd1-1";
>> +            samsung,pin-function = <3>;
>> +            samsung,pin-pud = <0>;
>> +            samsung,pin-drv = <0>;
>> +        };
>> +
>> +        i2c1_bus: i2c1-bus {
>> +            samsung,pins = "gpd1-2", "gpd1-3";
>> +            samsung,pin-function = <2>;
>> +            samsung,pin-pud = <3>;
>> +            samsung,pin-drv = <0>;
>> +        };
>> +    };
>> +
>> +    pinctrl@11000000 {
>> +        gpe0: gpe0 {
>> +            gpio-controller;
>> +            #gpio-cells = <2>;
>> +        };
>> +
>> +        gpe1: gpe1 {
>> +            gpio-controller;
>> +            #gpio-cells = <2>;
>> +        };
>> +
>> +        gpe2: gpe2 {
>> +            gpio-controller;
>> +            #gpio-cells = <2>;
>> +        };
>> +
>> +        gpk0: gpk0 {
>> +            gpio-controller;
>> +            #gpio-cells = <2>;
>> +
>> +            interrupt-controller;
>> +            #interrupt-cells = <2>;
>> +        };
>> +
>> +        gpk1: gpk1 {
>> +            gpio-controller;
>> +            #gpio-cells = <2>;
>> +
>> +            interrupt-controller;
>> +            #interrupt-cells = <2>;
>> +        };
>> +
>> +        gpk2: gpk2 {
>> +            gpio-controller;
>> +            #gpio-cells = <2>;
>> +
>> +            interrupt-controller;
>> +            #interrupt-cells = <2>;
>> +        };
>> +
>> +        gpl0: gpl0 {
>> +            gpio-controller;
>> +            #gpio-cells = <2>;
>> +
>> +            interrupt-controller;
>> +            #interrupt-cells = <2>;
>> +        };
>> +
>> +        gpm0: gpm0 {
>> +            gpio-controller;
>> +            #gpio-cells = <2>;
>> +
>> +            interrupt-controller;
>> +            #interrupt-cells = <2>;
>> +        };
>> +
>> +        gpm1: gpm1 {
>> +            gpio-controller;
>> +            #gpio-cells = <2>;
>> +
>> +            interrupt-controller;
>> +            #interrupt-cells = <2>;
>> +        };
>> +
>> +        gpm2: gpm2 {
>> +            gpio-controller;
>> +            #gpio-cells = <2>;
>> +
>> +            interrupt-controller;
>> +            #interrupt-cells = <2>;
>> +        };
>> +
>> +        gpm3: gpm3 {
>> +            gpio-controller;
>> +            #gpio-cells = <2>;
>> +
>> +            interrupt-controller;
>> +            #interrupt-cells = <2>;
>> +        };
>> +
>> +        gpm4: gpm4 {
>> +            gpio-controller;
>> +            #gpio-cells = <2>;
>> +
>> +            interrupt-controller;
>> +            #interrupt-cells = <2>;
>> +        };
>> +
>> +        gpx0: gpx0 {
>> +            gpio-controller;
>> +            #gpio-cells = <2>;
>> +
>> +            interrupt-controller;
>> +            interrupt-parent = <&gic>;
>> +            interrupts = <0 32 0>, <0 33 0>, <0 34 0>, <0 35 0>,
>> +                    <0 36 0>, <0 37 0>, <0 38 0>, <0 39 0>;
>> +            #interrupt-cells = <2>;
>> +        };
>> +
>> +        gpx1: gpx1 {
>> +            gpio-controller;
>> +            #gpio-cells = <2>;
>> +
>> +            interrupt-controller;
>> +            interrupt-parent = <&gic>;
>> +            interrupts = <0 40 0>, <0 41 0>, <0 42 0>, <0 43 0>,
>> +                    <0 44 0>, <0 45 0>, <0 46 0>, <0 47 0>;
>> +            #interrupt-cells = <2>;
>> +        };
>> +
>> +        gpx2: gpx2 {
>> +            gpio-controller;
>> +            #gpio-cells = <2>;
>> +
>> +            interrupt-controller;
>> +            #interrupt-cells = <2>;
>> +        };
>> +
>> +        gpx3: gpx3 {
>> +            gpio-controller;
>> +            #gpio-cells = <2>;
>> +
>> +            interrupt-controller;
>> +            #interrupt-cells = <2>;
>> +        };
>> +
>> +        sd0_clk: sd0-clk {
>> +            samsung,pins = "gpk0-0";
>> +            samsung,pin-function = <2>;
>> +            samsung,pin-pud = <0>;
>> +            samsung,pin-drv = <3>;
>> +        };
>> +
>> +        sd0_cmd: sd0-cmd {
>> +            samsung,pins = "gpk0-1";
>> +            samsung,pin-function = <2>;
>> +            samsung,pin-pud = <0>;
>> +            samsung,pin-drv = <3>;
>> +        };
>> +
>> +        sd0_cd: sd0-cd {
>> +            samsung,pins = "gpk0-2";
>> +            samsung,pin-function = <2>;
>> +            samsung,pin-pud = <3>;
>> +            samsung,pin-drv = <3>;
>> +        };
>> +
>> +        sd0_rdqs: sd0-rdqs {
>> +            samsung,pins = "gpk0-7";
>> +            samsung,pin-function = <2>;
>> +            samsung,pin-pud = <0>;
>> +            samsung,pin-drv = <3>;
>> +        };
>> +
>> +        sd0_bus1: sd0-bus-width1 {
>> +            samsung,pins = "gpk0-3";
>> +            samsung,pin-function = <2>;
>> +            samsung,pin-pud = <3>;
>> +            samsung,pin-drv = <3>;
>> +        };
>> +
>> +        sd0_bus4: sd0-bus-width4 {
>> +            samsung,pins = "gpk0-4", "gpk0-5", "gpk0-6";
>> +            samsung,pin-function = <2>;
>> +            samsung,pin-pud = <3>;
>> +            samsung,pin-drv = <3>;
>> +        };
>> +
>> +        sd0_bus8: sd0-bus-width8 {
>> +            samsung,pins = "gpl0-0", "gpl0-1", "gpl0-2", "gpl0-3";
>> +            samsung,pin-function = <2>;
>> +            samsung,pin-pud = <3>;
>> +            samsung,pin-drv = <3>;
>> +        };
>> +
>> +        sd1_clk: sd1-clk {
>> +            samsung,pins = "gpk1-0";
>> +            samsung,pin-function = <2>;
>> +            samsung,pin-pud = <0>;
>> +            samsung,pin-drv = <3>;
>> +        };
>> +
>> +        sd1_cmd: sd1-cmd {
>> +            samsung,pins = "gpk1-1";
>> +            samsung,pin-function = <2>;
>> +            samsung,pin-pud = <0>;
>> +            samsung,pin-drv = <3>;
>> +        };
>> +
>> +        sd1_cd: sd1-cd {
>> +            samsung,pins = "gpk1-2";
>> +            samsung,pin-function = <2>;
>> +            samsung,pin-pud = <3>;
>> +            samsung,pin-drv = <3>;
>> +        };
>> +
>> +        sd1_bus1: sd1-bus-width1 {
>> +            samsung,pins = "gpk1-3";
>> +            samsung,pin-function = <2>;
>> +            samsung,pin-pud = <3>;
>> +            samsung,pin-drv = <3>;
>> +        };
>> +
>> +        sd1_bus4: sd1-bus-width4 {
>> +            samsung,pins = "gpk1-4", "gpk1-5", "gpk1-6";
>> +            samsung,pin-function = <2>;
>> +            samsung,pin-pud = <3>;
>> +            samsung,pin-drv = <3>;
>> +        };
>> +
>> +        cam_port_b_io: cam-port-b-io {
>> +            samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3",
>> +                    "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7",
>> +                    "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1";
>> +            samsung,pin-function = <3>;
>> +            samsung,pin-pud = <3>;
>> +            samsung,pin-drv = <0>;
>> +        };
>> +
>> +        cam_port_b_clk_active: cam-port-b-clk-active {
>> +            samsung,pins = "gpm2-2";
>> +            samsung,pin-function = <3>;
>> +            samsung,pin-pud = <0>;
>> +            samsung,pin-drv = <3>;
>> +        };
>> +
>> +        cam_port_b_clk_idle: cam-port-b-clk-idle {
>> +            samsung,pins = "gpm2-2";
>> +            samsung,pin-function = <0>;
>> +            samsung,pin-pud = <0>;
>> +            samsung,pin-drv = <0>;
>> +        };
>> +
>> +        fimc_is_i2c0: fimc-is-i2c0 {
>> +            samsung,pins = "gpm4-0", "gpm4-1";
>> +            samsung,pin-function = <2>;
>> +            samsung,pin-pud = <0>;
>> +            samsung,pin-drv = <0>;
>> +        };
>> +
>> +        fimc_is_i2c1: fimc-is-i2c1 {
>> +            samsung,pins = "gpm4-2", "gpm4-3";
>> +            samsung,pin-function = <2>;
>> +            samsung,pin-pud = <0>;
>> +            samsung,pin-drv = <0>;
>> +        };
>> +
>> +        fimc_is_uart: fimc-is-uart {
>> +            samsung,pins = "gpm3-5", "gpm3-7";
>> +            samsung,pin-function = <3>;
>> +            samsung,pin-pud = <0>;
>> +            samsung,pin-drv = <0>;
>> +        };
>> +    };
>> +};
>> diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
>> new file mode 100644
>> index 0000000..5be3dd3
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/exynos3250.dtsi
>> @@ -0,0 +1,405 @@
>> +/*
>> + * Samsung's Exynos3250 SoC device tree source
>> + *
>> + * Copyright (c) 2014 Samsung Electronics Co., Ltd.
>> + *        http://www.samsung.com
>> + *
>> + * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
>> + * based board files can include this file and provide values for board specfic
>> + * bindings.
>> + *
>> + * Note: This file does not include device nodes for all the controllers in
>> + * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
>> + * nodes can be added to this file.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include "skeleton.dtsi"
>> +#include "exynos3250-pinctrl.dtsi"
>> +#include <dt-bindings/clock/exynos3250.h>
>> +
>> +/ {
>> +    compatible = "samsung,exynos3250";
>> +    interrupt-parent = <&gic>;
>> +
>> +    aliases {
>> +        pinctrl0 = &pinctrl_0;
>> +        pinctrl1 = &pinctrl_1;
>> +        mshc0 = &mshc_0;
>> +        mshc1 = &mshc_1;
>> +        spi0 = &spi_0;
>> +        spi1 = &spi_1;
>> +        i2c0 = &i2c_0;
>> +        i2c1 = &i2c_1;
>> +        i2c2 = &i2c_2;
>> +        i2c3 = &i2c_3;
>> +        i2c4 = &i2c_4;
>> +        i2c5 = &i2c_5;
>> +        i2c6 = &i2c_6;
>> +        i2c7 = &i2c_7;
>> +    };
>> +
>> +    cpus {
>> +        #address-cells = <1>;
>> +        #size-cells = <0>;
>> +
>> +        cpu@0 {
>> +            device_type = "cpu";
>> +            compatible = "arm,cortex-a7";
>> +            reg = <0>;
>> +            clock-frequency = <1000000000>;
>> +        };
> 
> Why only one CPU? I believe Exynos3250 is dual core. 

I'll add cpu1 information.

> Also are physical IDs of the cores really 0 and 1? On Exynos4210 for example they are 0x900 and 0x901, while on Exynos4212 they are 0xa00 and 0xa01. Please check this.

The 'reg' property means only hardware id(hwid) of CPU.
You can check it on arm_dt_init_cpu_maps() in arch/arm/kernel/devtree.c.h.
or Documentation/devicetree/bindings/arm/cpus.txt.

>> +    };
>> +
>> +    fixed-rate-clocks {
>> +        compatible = "simple-bus";
>> +        #address-cells = <1>;
>> +        #size-cells = <0>;
>> +
>> +        xusbxti: clock@0 {
>> +            compatible = "fixed-clock";
>> +            reg = <0>;
>> +            clock-frequency = <0>;
>> +            #clock-cells = <0>;
>> +            clock-output-names = "xusbxti";
>> +        };
>> +
>> +        xxti: clock@1 {
>> +            compatible = "fixed-clock";
>> +            reg = <1>;
>> +            clock-frequency = <0>;
>> +            #clock-cells = <0>;
>> +            clock-output-names = "xxti";
>> +        };
>> +
>> +        xtcxo: clock@2 {
>> +            compatible = "fixed-clock";
>> +            reg = <2>;
>> +            clock-frequency = <0>;
>> +            #clock-cells = <0>;
>> +            clock-output-names = "xtcxo";
>> +        };
>> +    };
>> +
>> +    chipid@10000000 {
>> +        compatible = "samsung,exynos4210-chipid";
>> +        reg = <0x10000000 0x100>;
>> +    };
>> +
>> +    sys_reg: syscon@10010000 {
>> +        compatible = "samsung,exynos3-sysreg", "syscon";
>> +        reg = <0x10010000 0x400>;
>> +    };
>> +
>> +    pd_cam: cam-power-domain@10023C00 {
>> +        compatible = "samsung,exynos4210-pd";
>> +        reg = <0x10023C00 0x20>;
>> +    };
>> +
>> +    pd_mfc: mfc-power-domain@10023C40 {
>> +        compatible = "samsung,exynos4210-pd";
>> +        reg = <0x10023C40 0x20>;
>> +    };
>> +
>> +    pd_g3d: g3d-power-domain@10023C60 {
>> +        compatible = "samsung,exynos4210-pd";
>> +        reg = <0x10023C60 0x20>;
>> +    };
>> +
>> +    pd_lcd0: lcd0-power-domain@10023C80 {
>> +        compatible = "samsung,exynos4210-pd";
>> +        reg = <0x10023C80 0x20>;
>> +    };
>> +
>> +    pd_isp: isp-power-domain@10023CA0 {
>> +        compatible = "samsung,exynos4210-pd";
>> +        reg = <0x10023CA0 0x20>;
>> +    };
>> +
>> +    cmu: clock-controller@10030000 {
>> +        compatible = "samsung,exynos3250-cmu";
>> +        reg = <0x10030000 0x20000>;
>> +        #clock-cells = <1>;
>> +    };
>> +
>> +    rtc@10070000 {
> 
> Please add label to the node, so it can be referenced from board dts files added later (using the method I explained above).

OK, I'll add lable as following:

	rtc_0: rtc@10070000 {

> 
>> +        compatible = "samsung,s3c6410-rtc";
>> +        reg = <0x10070000 0x100>;
>> +        interrupts = <0 73 0>, <0 74 0>;
>> +        status = "disabled";
>> +    };
>> +
>> +    gic: interrupt-controller@10481000 {
>> +        compatible = "arm,cortex-a15-gic";
>> +        #interrupt-cells = <3>;
>> +        interrupt-controller;
>> +        reg = <0x10481000 0x1000>,
>> +              <0x10482000 0x1000>,
>> +              <0x10484000 0x2000>,
>> +              <0x10486000 0x2000>;
>> +              interrupts = <1 9 0xf04>;
>> +    };
>> +
>> +    mct@10050000 {
>> +        compatible = "samsung,exynos4210-mct";
>> +        reg = <0x10050000 0x800>;
>> +        interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
>> +                 <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
>> +        clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
>> +        clock-names = "fin_pll", "mct";
>> +    };
>> +
>> +    pinctrl_1: pinctrl@11000000 {
>> +        compatible = "samsung,exynos3250-pinctrl";
>> +        reg = <0x11000000 0x1000>;
>> +        interrupts = <0 225 0>;
>> +
>> +        wakeup-interrupt-controller {
>> +            compatible = "samsung,exynos4210-wakeup-eint";
>> +            interrupt-parent = <&gic>;
>> +            interrupts = <0 48 0>;
>> +        };
>> +    };
>> +
>> +    pinctrl_0: pinctrl@11400000 {
>> +        compatible = "samsung,exynos3250-pinctrl";
>> +        reg = <0x11400000 0x1000>;
>> +        interrupts = <0 240 0>;
>> +    };
>> +
>> +    mshc_0: mshc@12510000 {
>> +        compatible = "samsung,exynos5250-dw-mshc";
>> +        reg = <0x12510000 0x1000>;
>> +        interrupts = <0 142 0>;
>> +        clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
>> +        clock-names = "biu", "ciu";
>> +        fifo-depth = <0x80>;
>> +        #address-cells = <1>;
>> +        #size-cells = <0>;
>> +        status = "disabled";
>> +    };
>> +
>> +    mshc_1: mshc@12520000 {
>> +        compatible = "samsung,exynos5250-dw-mshc";
>> +        reg = <0x12520000 0x1000>;
>> +        interrupts = <0 143 0>;
>> +        clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
>> +        clock-names = "biu", "ciu";
>> +        fifo-depth = <0x80>;
>> +        #address-cells = <1>;
>> +        #size-cells = <0>;
>> +        status = "disabled";
>> +    };
>> +
>> +    amba {
>> +        #address-cells = <1>;
>> +        #size-cells = <1>;
>> +        compatible = "arm,amba-bus";
>> +        interrupt-parent = <&gic>;
>> +        ranges;
>> +
>> +        pdma0: pdma@12680000 {
>> +            compatible = "arm,pl330", "arm,primecell";
>> +            reg = <0x12680000 0x1000>;
>> +            interrupts = <0 138 0>;
>> +            clocks = <&cmu CLK_PDMA0>;
>> +            clock-names = "apb_pclk";
>> +            #dma-cells = <1>;
>> +            #dma-channels = <8>;
>> +            #dma-requests = <32>;
>> +        };
>> +
>> +        pdma1: pdma@12690000 {
>> +            compatible = "arm,pl330", "arm,primecell";
>> +            reg = <0x12690000 0x1000>;
>> +            interrupts = <0 139 0>;
>> +            clocks = <&cmu CLK_PDMA1>;
>> +            clock-names = "apb_pclk";
>> +            #dma-cells = <1>;
>> +            #dma-channels = <8>;
>> +            #dma-requests = <32>;
>> +        };
>> +    };
>> +
>> +    adc: adc@126C0000 {
>> +        compatible = "samsung,exynos-adc-v3";
>> +        reg = <0x126C0000 0x100>, <0x10020718 0x4>;
>> +        interrupts = <0 137 0>;
>> +        clock-names = "adc", "sclk_tsadc";
>> +        clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
>> +        #io-channel-cells = <1>;
>> +        io-channel-ranges;
>> +        status = "disabled";
>> +    };
>> +
>> +    serial@13800000 {
> 
> Please add label.

OK, I'll add lable as following:

	serial_0: serial@13800000 {

> 
>> +        compatible = "samsung,exynos4210-uart";
>> +        reg = <0x13800000 0x100>;
>> +        interrupts = <0 109 0>;
>> +        clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
>> +        clock-names = "uart", "clk_uart_baud0";
>> +        status = "disabled";
>> +    };
>> +
>> +    serial@13810000 {

OK, I'll add lable as following:

	serial_1: serial@13800000 {


Thanks for your review.

Best regards,
Chanwoo Choi

Re: [PATCHv4 7/7] ARM: dts: Add device tree sources for Exynos3250

[Tomasz Figa]

Hi Chanwoo,

On 09.05.2014 03:06, Chanwoo Choi wrote:
> On 04/26/2014 09:51 AM, Tomasz Figa wrote:
>> On 25.04.2014 03:16, Chanwoo Choi wrote:

[snip]

>>> +    cpus {
>>> +        #address-cells = <1>;
>>> +        #size-cells = <0>;
>>> +
>>> +        cpu@0 {
>>> +            device_type = "cpu";
>>> +            compatible = "arm,cortex-a7";
>>> +            reg = <0>;
>>> +            clock-frequency = <1000000000>;
>>> +        };
>>
>> Why only one CPU? I believe Exynos3250 is dual core.
>
> I'll add cpu1 information.
>
>> Also are physical IDs of the cores really 0 and 1? On Exynos4210 for example they are 0x900 and 0x901, while on Exynos4212 they are 0xa00 and 0xa01. Please check this.
>
> The 'reg' property means only hardware id(hwid) of CPU.
> You can check it on arm_dt_init_cpu_maps() in arch/arm/kernel/devtree.c.h.
> or Documentation/devicetree/bindings/arm/cpus.txt.
>

Well, as described in Documentation/devicetree/bindings/arm/cpus.txt, on 
32-bit ARM v7 or later CPUs the "reg" property should be equal to the 
lower 24-bits of MPIDR value of given CPU, which in addition to core ID 
includes also cluster ID, which can be non-zero, even on single cluster 
SoCs (like it is on Exynos4210 and 4x12).

>>> +    };
>>> +
>>> +    fixed-rate-clocks {
>>> +        compatible = "simple-bus";
>>> +        #address-cells = <1>;
>>> +        #size-cells = <0>;

[snip]

>>> +    cmu: clock-controller@10030000 {
>>> +        compatible = "samsung,exynos3250-cmu";
>>> +        reg = <0x10030000 0x20000>;
>>> +        #clock-cells = <1>;
>>> +    };
>>> +
>>> +    rtc@10070000 {
>>
>> Please add label to the node, so it can be referenced from board dts files added later (using the method I explained above).
>
> OK, I'll add lable as following:
>
> 	rtc_0: rtc@10070000 {

There is no need to suffix the RTC with _0, as there is just one RTC in 
the SoC. So in this case rtc: rtc@10070000 will be enough.

>
>>
>>> +        compatible = "samsung,s3c6410-rtc";
>>> +        reg = <0x10070000 0x100>;
>>> +        interrupts = <0 73 0>, <0 74 0>;
>>> +        status = "disabled";
>>> +    };

[snip]

>>> +    adc: adc@126C0000 {
>>> +        compatible = "samsung,exynos-adc-v3";
>>> +        reg = <0x126C0000 0x100>, <0x10020718 0x4>;
>>> +        interrupts = <0 137 0>;
>>> +        clock-names = "adc", "sclk_tsadc";
>>> +        clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
>>> +        #io-channel-cells = <1>;
>>> +        io-channel-ranges;
>>> +        status = "disabled";
>>> +    };
>>> +
>>> +    serial@13800000 {
>>
>> Please add label.
>
> OK, I'll add lable as following:
>
> 	serial_0: serial@13800000 {
>

OK. In this case there are multiple instances of serial controller 
available so the _0 suffix is fine.

>>
>>> +        compatible = "samsung,exynos4210-uart";
>>> +        reg = <0x13800000 0x100>;
>>> +        interrupts = <0 109 0>;
>>> +        clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
>>> +        clock-names = "uart", "clk_uart_baud0";
>>> +        status = "disabled";
>>> +    };
>>> +
>>> +    serial@13810000 {
>
> OK, I'll add lable as following:
>
> 	serial_1: serial@13800000 {
>

OK.

>
> Thanks for your review.

You're welcome. Thanks for addressing my comments.

Best regards,
Tomasz

Re: [PATCHv4 7/7] ARM: dts: Add device tree sources for Exynos3250

[Chanwoo Choi]

Hi Tomasz,

On 04/26/2014 08:38 PM, Tomasz Figa wrote:
> On 26.04.2014 02:51, Tomasz Figa wrote:
>> Hi Chanwoo,
>>
>> On 25.04.2014 03:16, Chanwoo Choi wrote:
>>> From: Tomasz Figa <t.figa@samsung.com>
>>>
>>> This patch add new exynos3250.dtsi to support Exynos3250 SoC based on
>>> Cortex-A7
>>> dual core and includes following dt nodes:
>>>
>>> - GIC interrupt controller
>>> - Pinctrl to control GPIOs
>>> - Clock controller
>>> - CPU information (Cortex-A7 dual core)
>>> - UART to support serial port
>>> - MCT (Multi Core Timer)
>>> - ADC (Analog Digital Converter)
>>> - I2C/SPI bus
>>> - Power domain
>>> - PMU (Performance Monitoring Unit)
>>> - MSHC (Mobile Storage Host Controller)
>>> - PWM (Pluse Width Modulation)
>>> - AMBA bus
>>>
>>> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>>> Signed-off-by: Inki Dae <inki.dae@samsung.com>
>>> Signed-off-by: Hyunhee Kim <hyunhee.kim@samsung.com>
>>> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
>>> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
>>> Cc: Ben Dooks <ben-linux@fluff.org>
>>> Cc: Kukjin Kim <kgene.kim@samsung.com>
>>> Cc: Rob Herring <robh+dt@kernel.org>
>>> Cc: Pawel Moll <pawel.moll@arm.com>
>>> Cc: Mark Rutland <mark.rutland@arm.com>
>>> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
>>> Cc: Kumar Gala <galak@codeaurora.org>
>>> Cc: Russell King <linux@arm.linux.org.uk>
>>> Cc: devicetree@vger.kernel.org
>>> ---
>>>   arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 477 +++++++++++++++
>>>   arch/arm/boot/dts/exynos3250.dtsi         | 405 +++++++++++++
>>>   arch/arm/boot/dts/exynos4212-tizenw.dts   | 926
>>> ++++++++++++++++++++++++++++++
>>>   3 files changed, 1808 insertions(+)
>>>   create mode 100644 arch/arm/boot/dts/exynos3250-pinctrl.dtsi
>>>   create mode 100644 arch/arm/boot/dts/exynos3250.dtsi
>>>   create mode 100644 arch/arm/boot/dts/exynos4212-tizenw.dts
>>>
>>> diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
>>> b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
>>> new file mode 100644
>>> index 0000000..976490b
>>> --- /dev/null
>>> +++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
>>> @@ -0,0 +1,477 @@
>>> +/*
>>> + * Samsung's Exynos3250 SoCs pin-mux and pin-config device tree source
>>> + *
>>> + * Copyright (c) 2014 Samsung Electronics Co., Ltd.
>>> + *        http://www.samsung.com
>>> + *
>>> + * Samsung's Exynos3250 SoCs pin-mux and pin-config optiosn are
>>> listed as device
>>> + * tree nodes are listed in this file.
>>> + *
>>> + * This program is free software; you can redistribute it and/or modify
>>> + * it under the terms of the GNU General Public License version 2 as
>>> + * published by the Free Software Foundation.
>>> +*/
>>> +
>>> +/ {
>>> +    pinctrl@11400000 {
>>
>> Could you use references instead of re-specifying the whole tree
>> hierarchy in every file a node is used?
>>
>> Instead of
>>
>> / {
>>      pinctrl@11400000 {
>>
>>      };
>> };
>>
>> one may simply use
>>
>> &pinctrl_0 {
>>
>> };
>>
>> You might just need to change the location of #include
>> "exynos3250-pinctrl.dtsi" from top of exynos3250.dtsi to bottom of it.
> 
> Oh, well, you also should move all nodes of on-SoC devices under a simple-bus node called soc. You can see the patch adding dts file for Exynos5260 for an example [1].
> 
> [1] http://thread.gmane.org/gmane.linux.kernel.samsung-soc/29360/focus=29361


OK, I'll move nodes dependent on SoC under 'soc' dt node as example patch[1] except for 'amba-bus' dt node.

Thanks,
Chanwoo Choi

Re: [PATCHv4 7/7] ARM: dts: Add device tree sources for Exynos3250

[Chanwoo Choi]

Hi Tomasz,

On 05/09/2014 02:02 PM, Tomasz Figa wrote:
> Hi Chanwoo,
> 
> On 09.05.2014 03:06, Chanwoo Choi wrote:
>> On 04/26/2014 09:51 AM, Tomasz Figa wrote:
>>> On 25.04.2014 03:16, Chanwoo Choi wrote:
> 
> [snip]
> 
>>>> +    cpus {
>>>> +        #address-cells = <1>;
>>>> +        #size-cells = <0>;
>>>> +
>>>> +        cpu@0 {
>>>> +            device_type = "cpu";
>>>> +            compatible = "arm,cortex-a7";
>>>> +            reg = <0>;
>>>> +            clock-frequency = <1000000000>;
>>>> +        };
>>>
>>> Why only one CPU? I believe Exynos3250 is dual core.
>>
>> I'll add cpu1 information.
>>
>>> Also are physical IDs of the cores really 0 and 1? On Exynos4210 for example they are 0x900 and 0x901, while on Exynos4212 they are 0xa00 and 0xa01. Please check this.
>>
>> The 'reg' property means only hardware id(hwid) of CPU.
>> You can check it on arm_dt_init_cpu_maps() in arch/arm/kernel/devtree.c.h.
>> or Documentation/devicetree/bindings/arm/cpus.txt.
>>
> 
> Well, as described in Documentation/devicetree/bindings/arm/cpus.txt, on 32-bit ARM v7 or later CPUs the "reg" property should be equal to the lower 24-bits of MPIDR value of given CPU, which in addition to core ID includes also cluster ID, which can be non-zero, even on single cluster SoCs (like it is on Exynos4210 and 4x12).

I checked the lower 24-bit of MPIDR value for Exynos3250 in arm_dt_init_cpu_maps().
- the lower 24-bit of MPIDR for CPU0 is '0x0'.

> 
>>>> +    };
>>>> +
>>>> +    fixed-rate-clocks {
>>>> +        compatible = "simple-bus";
>>>> +        #address-cells = <1>;
>>>> +        #size-cells = <0>;
> 
> [snip]
> 
>>>> +    cmu: clock-controller@10030000 {
>>>> +        compatible = "samsung,exynos3250-cmu";
>>>> +        reg = <0x10030000 0x20000>;
>>>> +        #clock-cells = <1>;
>>>> +    };
>>>> +
>>>> +    rtc@10070000 {
>>>
>>> Please add label to the node, so it can be referenced from board dts files added later (using the method I explained above).
>>
>> OK, I'll add lable as following:
>>
>>     rtc_0: rtc@10070000 {
> 
> There is no need to suffix the RTC with _0, as there is just one RTC in the SoC. So in this case rtc: rtc@10070000 will be enough.

OK, I'll modify it without prefix('_0).

Best Regards,
Chanwoo Choi

Re: [PATCHv4 7/7] ARM: dts: Add device tree sources for Exynos3250

[Tomasz Figa]

On 09.05.2014 08:49, Chanwoo Choi wrote:
> Hi Tomasz,
> 
> On 04/26/2014 08:38 PM, Tomasz Figa wrote:
>> On 26.04.2014 02:51, Tomasz Figa wrote:
>>> Hi Chanwoo,
>>>
>>> On 25.04.2014 03:16, Chanwoo Choi wrote:
>>>> From: Tomasz Figa <t.figa@samsung.com>
>>>>
>>>> This patch add new exynos3250.dtsi to support Exynos3250 SoC based on
>>>> Cortex-A7
>>>> dual core and includes following dt nodes:
>>>>
>>>> - GIC interrupt controller
>>>> - Pinctrl to control GPIOs
>>>> - Clock controller
>>>> - CPU information (Cortex-A7 dual core)
>>>> - UART to support serial port
>>>> - MCT (Multi Core Timer)
>>>> - ADC (Analog Digital Converter)
>>>> - I2C/SPI bus
>>>> - Power domain
>>>> - PMU (Performance Monitoring Unit)
>>>> - MSHC (Mobile Storage Host Controller)
>>>> - PWM (Pluse Width Modulation)
>>>> - AMBA bus
>>>>
>>>> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
>>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>>>> Signed-off-by: Inki Dae <inki.dae@samsung.com>
>>>> Signed-off-by: Hyunhee Kim <hyunhee.kim@samsung.com>
>>>> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
>>>> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
>>>> Cc: Ben Dooks <ben-linux@fluff.org>
>>>> Cc: Kukjin Kim <kgene.kim@samsung.com>
>>>> Cc: Rob Herring <robh+dt@kernel.org>
>>>> Cc: Pawel Moll <pawel.moll@arm.com>
>>>> Cc: Mark Rutland <mark.rutland@arm.com>
>>>> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
>>>> Cc: Kumar Gala <galak@codeaurora.org>
>>>> Cc: Russell King <linux@arm.linux.org.uk>
>>>> Cc: devicetree@vger.kernel.org
>>>> ---
>>>>   arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 477 +++++++++++++++
>>>>   arch/arm/boot/dts/exynos3250.dtsi         | 405 +++++++++++++
>>>>   arch/arm/boot/dts/exynos4212-tizenw.dts   | 926
>>>> ++++++++++++++++++++++++++++++
>>>>   3 files changed, 1808 insertions(+)
>>>>   create mode 100644 arch/arm/boot/dts/exynos3250-pinctrl.dtsi
>>>>   create mode 100644 arch/arm/boot/dts/exynos3250.dtsi
>>>>   create mode 100644 arch/arm/boot/dts/exynos4212-tizenw.dts
>>>>
>>>> diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
>>>> b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
>>>> new file mode 100644
>>>> index 0000000..976490b
>>>> --- /dev/null
>>>> +++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
>>>> @@ -0,0 +1,477 @@
>>>> +/*
>>>> + * Samsung's Exynos3250 SoCs pin-mux and pin-config device tree source
>>>> + *
>>>> + * Copyright (c) 2014 Samsung Electronics Co., Ltd.
>>>> + *        http://www.samsung.com
>>>> + *
>>>> + * Samsung's Exynos3250 SoCs pin-mux and pin-config optiosn are
>>>> listed as device
>>>> + * tree nodes are listed in this file.
>>>> + *
>>>> + * This program is free software; you can redistribute it and/or modify
>>>> + * it under the terms of the GNU General Public License version 2 as
>>>> + * published by the Free Software Foundation.
>>>> +*/
>>>> +
>>>> +/ {
>>>> +    pinctrl@11400000 {
>>>
>>> Could you use references instead of re-specifying the whole tree
>>> hierarchy in every file a node is used?
>>>
>>> Instead of
>>>
>>> / {
>>>      pinctrl@11400000 {
>>>
>>>      };
>>> };
>>>
>>> one may simply use
>>>
>>> &pinctrl_0 {
>>>
>>> };
>>>
>>> You might just need to change the location of #include
>>> "exynos3250-pinctrl.dtsi" from top of exynos3250.dtsi to bottom of it.
>>
>> Oh, well, you also should move all nodes of on-SoC devices under a simple-bus node called soc. You can see the patch adding dts file for Exynos5260 for an example [1].
>>
>> [1] http://thread.gmane.org/gmane.linux.kernel.samsung-soc/29360/focus=29361
> 
> 
> OK, I'll move nodes dependent on SoC under 'soc' dt node as example patch[1] except for 'amba-bus' dt node.

I don't see any reason why amba-bus node shouldn't be under soc node as
well. Any on-chip devices should be.

Best regards,
Tomasz

Re: [PATCHv4 7/7] ARM: dts: Add device tree sources for Exynos3250

[Tomasz Figa]

On 09.05.2014 09:10, Chanwoo Choi wrote:
> Hi Tomasz,
> 
> On 05/09/2014 02:02 PM, Tomasz Figa wrote:
>> Hi Chanwoo,
>>
>> On 09.05.2014 03:06, Chanwoo Choi wrote:
>>> On 04/26/2014 09:51 AM, Tomasz Figa wrote:
>>>> On 25.04.2014 03:16, Chanwoo Choi wrote:
>>
>> [snip]
>>
>>>>> +    cpus {
>>>>> +        #address-cells = <1>;
>>>>> +        #size-cells = <0>;
>>>>> +
>>>>> +        cpu@0 {
>>>>> +            device_type = "cpu";
>>>>> +            compatible = "arm,cortex-a7";
>>>>> +            reg = <0>;
>>>>> +            clock-frequency = <1000000000>;
>>>>> +        };
>>>>
>>>> Why only one CPU? I believe Exynos3250 is dual core.
>>>
>>> I'll add cpu1 information.
>>>
>>>> Also are physical IDs of the cores really 0 and 1? On Exynos4210 for example they are 0x900 and 0x901, while on Exynos4212 they are 0xa00 and 0xa01. Please check this.
>>>
>>> The 'reg' property means only hardware id(hwid) of CPU.
>>> You can check it on arm_dt_init_cpu_maps() in arch/arm/kernel/devtree.c.h.
>>> or Documentation/devicetree/bindings/arm/cpus.txt.
>>>
>>
>> Well, as described in Documentation/devicetree/bindings/arm/cpus.txt, on 32-bit ARM v7 or later CPUs the "reg" property should be equal to the lower 24-bits of MPIDR value of given CPU, which in addition to core ID includes also cluster ID, which can be non-zero, even on single cluster SoCs (like it is on Exynos4210 and 4x12).
> 
> I checked the lower 24-bit of MPIDR value for Exynos3250 in arm_dt_init_cpu_maps().
> - the lower 24-bit of MPIDR for CPU0 is '0x0'.

Fair enough. Thanks.

Best regards,
Tomasz

Re: [PATCHv4 7/7] ARM: dts: Add device tree sources for Exynos3250

[Chanwoo Choi]

Hi Tomasz,

On 05/09/2014 05:01 PM, Tomasz Figa wrote:
> On 09.05.2014 08:49, Chanwoo Choi wrote:
>> Hi Tomasz,
>>
>> On 04/26/2014 08:38 PM, Tomasz Figa wrote:
>>> On 26.04.2014 02:51, Tomasz Figa wrote:
>>>> Hi Chanwoo,
>>>>
>>>> On 25.04.2014 03:16, Chanwoo Choi wrote:
>>>>> From: Tomasz Figa <t.figa@samsung.com>
>>>>>
>>>>> This patch add new exynos3250.dtsi to support Exynos3250 SoC based on
>>>>> Cortex-A7
>>>>> dual core and includes following dt nodes:
>>>>>
>>>>> - GIC interrupt controller
>>>>> - Pinctrl to control GPIOs
>>>>> - Clock controller
>>>>> - CPU information (Cortex-A7 dual core)
>>>>> - UART to support serial port
>>>>> - MCT (Multi Core Timer)
>>>>> - ADC (Analog Digital Converter)
>>>>> - I2C/SPI bus
>>>>> - Power domain
>>>>> - PMU (Performance Monitoring Unit)
>>>>> - MSHC (Mobile Storage Host Controller)
>>>>> - PWM (Pluse Width Modulation)
>>>>> - AMBA bus
>>>>>
>>>>> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
>>>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>>>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>>>>> Signed-off-by: Inki Dae <inki.dae@samsung.com>
>>>>> Signed-off-by: Hyunhee Kim <hyunhee.kim@samsung.com>
>>>>> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
>>>>> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
>>>>> Cc: Ben Dooks <ben-linux@fluff.org>
>>>>> Cc: Kukjin Kim <kgene.kim@samsung.com>
>>>>> Cc: Rob Herring <robh+dt@kernel.org>
>>>>> Cc: Pawel Moll <pawel.moll@arm.com>
>>>>> Cc: Mark Rutland <mark.rutland@arm.com>
>>>>> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
>>>>> Cc: Kumar Gala <galak@codeaurora.org>
>>>>> Cc: Russell King <linux@arm.linux.org.uk>
>>>>> Cc: devicetree@vger.kernel.org
>>>>> ---
>>>>>   arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 477 +++++++++++++++
>>>>>   arch/arm/boot/dts/exynos3250.dtsi         | 405 +++++++++++++
>>>>>   arch/arm/boot/dts/exynos4212-tizenw.dts   | 926
>>>>> ++++++++++++++++++++++++++++++
>>>>>   3 files changed, 1808 insertions(+)
>>>>>   create mode 100644 arch/arm/boot/dts/exynos3250-pinctrl.dtsi
>>>>>   create mode 100644 arch/arm/boot/dts/exynos3250.dtsi
>>>>>   create mode 100644 arch/arm/boot/dts/exynos4212-tizenw.dts
>>>>>
>>>>> diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
>>>>> b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
>>>>> new file mode 100644
>>>>> index 0000000..976490b
>>>>> --- /dev/null
>>>>> +++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
>>>>> @@ -0,0 +1,477 @@
>>>>> +/*
>>>>> + * Samsung's Exynos3250 SoCs pin-mux and pin-config device tree source
>>>>> + *
>>>>> + * Copyright (c) 2014 Samsung Electronics Co., Ltd.
>>>>> + *        http://www.samsung.com
>>>>> + *
>>>>> + * Samsung's Exynos3250 SoCs pin-mux and pin-config optiosn are
>>>>> listed as device
>>>>> + * tree nodes are listed in this file.
>>>>> + *
>>>>> + * This program is free software; you can redistribute it and/or modify
>>>>> + * it under the terms of the GNU General Public License version 2 as
>>>>> + * published by the Free Software Foundation.
>>>>> +*/
>>>>> +
>>>>> +/ {
>>>>> +    pinctrl@11400000 {
>>>>
>>>> Could you use references instead of re-specifying the whole tree
>>>> hierarchy in every file a node is used?
>>>>
>>>> Instead of
>>>>
>>>> / {
>>>>      pinctrl@11400000 {
>>>>
>>>>      };
>>>> };
>>>>
>>>> one may simply use
>>>>
>>>> &pinctrl_0 {
>>>>
>>>> };
>>>>
>>>> You might just need to change the location of #include
>>>> "exynos3250-pinctrl.dtsi" from top of exynos3250.dtsi to bottom of it.
>>>
>>> Oh, well, you also should move all nodes of on-SoC devices under a simple-bus node called soc. You can see the patch adding dts file for Exynos5260 for an example [1].
>>>
>>> [1] http://thread.gmane.org/gmane.linux.kernel.samsung-soc/29360/focus=29361
>>
>>
>> OK, I'll move nodes dependent on SoC under 'soc' dt node as example patch[1] except for 'amba-bus' dt node.
> 
> I don't see any reason why amba-bus node shouldn't be under soc node as
> well. Any on-chip devices should be.

I didn't understand the correct meaning of 'simple-bus'.
OK, I'll move 'amba-bus' dt node under 'soc' dt node.

Best Regards,
Chanwoo Choi

Re: [PATCHv4 5/7] clk: samsung: exynos3250: Add clocks using common clock framework

[Chanwoo Choi]

Hi Tomasz,

On 04/26/2014 09:39 AM, Tomasz Figa wrote:
> Hi Chanwoo,
> 
> On 25.04.2014 03:16, Chanwoo Choi wrote:
>> From: Tomasz Figa <t.figa@samsung.com>
>>
>> This patch add new the clock drvier of Exynos3250 SoC based on Cortex-A7
>> using common clock framework. The CMU (Clock Management Unit) of Exynos3250
>> control PLLs(Phase Locked Loops) and generate system clocks for CPU, buses,
>> and function clocks for individual IPs.
>>
>> The CMU of Exynos3250 includes following clock doamins:
>> - CPU block for Cortex-A7 MPCore processor
>> - LEFTBUS/RIGHTBUS block
>> - TOP block for G3D/MFC/LCD0/ISP/CAM/FSYS/MFC/PERIL/PERIR
> 
> In original driver present in our internal tree I have separated several CMUs to account for certain factors caused by hardware design, which require such separation. Is there any reason why they were merged together into a single CMU again?

This patch just include clocks in CMU clocks without CMU_DMC/CMU_ISP.
I'll send a further patches to support CMU_DMC/CMU_ISP after verifying it.

> 
>>
>> Cc: Mike Turquette <mturquette@linaro.org>
>> Cc: Kukjin Kim <kgene.kim@samsung.com>
>> Cc: Rob Herring <robh+dt@kernel.org>
>> Cc: Pawel Moll <pawel.moll@arm.com>
>> Cc: Mark Rutland <mark.rutland@arm.com>
>> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
>> Cc: Kumar Gala <galak@codeaurora.org>
>> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> Signed-off-by: Hyunhee Kim <hyunhee.kim@samsung.com>
>> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
>> Signed-off-by: Inki Dae <inki.dae@samsung.com>
>> Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
>> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
>> Signed-off-by: Karol Wrona <k.wrona@samsung.com>
>> Signed-off-by: YoungJun Cho <yj44.cho@samsung.com>
>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>> ---
>>   drivers/clk/samsung/Makefile           |   1 +
>>   drivers/clk/samsung/clk-exynos3250.c   | 785 +++++++++++++++++++++++++++++++++
>>   include/dt-bindings/clock/exynos3250.h | 256 +++++++++++
>>   3 files changed, 1042 insertions(+)
>>   create mode 100644 drivers/clk/samsung/clk-exynos3250.c
>>   create mode 100644 include/dt-bindings/clock/exynos3250.h
>>
>> diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
>> index 8eb4799..d120797 100644
>> --- a/drivers/clk/samsung/Makefile
>> +++ b/drivers/clk/samsung/Makefile
>> @@ -3,6 +3,7 @@
>>   #
>>
>>   obj-$(CONFIG_COMMON_CLK)    += clk.o clk-pll.o
>> +obj-$(CONFIG_SOC_EXYNOS3250)    += clk-exynos3250.o
>>   obj-$(CONFIG_ARCH_EXYNOS4)    += clk-exynos4.o
>>   obj-$(CONFIG_SOC_EXYNOS5250)    += clk-exynos5250.o
>>   obj-$(CONFIG_SOC_EXYNOS5420)    += clk-exynos5420.o
>> diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
>> new file mode 100644
>> index 0000000..0574a76
>> --- /dev/null
>> +++ b/drivers/clk/samsung/clk-exynos3250.c
>> @@ -0,0 +1,785 @@
>> +/*
>> + * Copyright (c) 2014 Samsung Electronics Co., Ltd.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * Common Clock Framework support for Exynos3250 SoC.
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/clkdev.h>
>> +#include <linux/clk-provider.h>
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/syscore_ops.h>
>> +
>> +#include <dt-bindings/clock/exynos3250.h>
>> +
>> +#include "clk.h"
>> +#include "clk-pll.h"
>> +
>> +#define SRC_LEFTBUS        0x4200
>> +#define DIV_LEFTBUS        0x4500
>> +#define GATE_IP_LEFTBUS        0x4800
>> +#define SRC_RIGHTBUS        0x8200
>> +#define DIV_RIGHTBUS        0x8500
>> +#define GATE_IP_RIGHTBUS    0x8800
>> +#define GATE_IP_PERIR        0x8960
>> +#define MPLL_LOCK        0xc010
>> +#define MPLL_CON0        0xc110
>> +#define VPLL_LOCK        0xc020
>> +#define VPLL_CON0        0xc120
>> +#define UPLL_LOCK        0xc030
>> +#define UPLL_CON0        0xc130
>> +#define SRC_TOP0        0xc210
>> +#define SRC_TOP1        0xc214
>> +#define SRC_CAM            0xc220
>> +#define SRC_MFC            0xc228
>> +#define SRC_G3D            0xc22c
>> +#define SRC_LCD            0xc234
>> +#define SRC_ISP            0xc238
>> +#define SRC_FSYS        0xc240
>> +#define SRC_PERIL0        0xc250
>> +#define SRC_PERIL1        0xc254
>> +#define SRC_MASK_TOP        0xc310
>> +#define SRC_MASK_CAM        0xc320
>> +#define SRC_MASK_LCD        0xc334
>> +#define SRC_MASK_ISP        0xc338
>> +#define SRC_MASK_FSYS        0xc340
>> +#define SRC_MASK_PERIL0        0xc350
>> +#define SRC_MASK_PERIL1        0xc354
>> +#define DIV_TOP            0xc510
>> +#define DIV_CAM            0xc520
>> +#define DIV_MFC            0xc528
>> +#define DIV_G3D            0xc52c
>> +#define DIV_LCD            0xc534
>> +#define DIV_ISP            0xc538
>> +#define DIV_FSYS0        0xc540
>> +#define DIV_FSYS1        0xc544
>> +#define DIV_FSYS2        0xc548
>> +#define DIV_PERIL0        0xc550
>> +#define DIV_PERIL1        0xc554
>> +#define DIV_PERIL3        0xc55c
>> +#define DIV_PERIL4        0xc560
>> +#define DIV_PERIL5        0xc564
>> +#define DIV_CAM1        0xc568
>> +#define CLKDIV2_RATIO        0xc580
>> +#define GATE_SCLK_CAM        0xc820
>> +#define GATE_SCLK_MFC        0xc828
>> +#define GATE_SCLK_G3D        0xc82c
>> +#define GATE_SCLK_LCD        0xc834
>> +#define GATE_SCLK_ISP_TOP    0xc838
>> +#define GATE_SCLK_FSYS        0xc840
>> +#define GATE_SCLK_PERIL        0xc850
>> +#define GATE_IP_CAM        0xc920
>> +#define GATE_IP_MFC        0xc928
>> +#define GATE_IP_G3D        0xc92c
>> +#define GATE_IP_LCD        0xc934
>> +#define GATE_IP_ISP        0xc938
>> +#define GATE_IP_FSYS        0xc940
>> +#define GATE_IP_PERIL        0xc950
>> +#define GATE_BLOCK        0xc970
>> +#define APLL_LOCK        0x14000
>> +#define APLL_CON0        0x14100
>> +#define SRC_CPU            0x14200
>> +#define DIV_CPU0        0x14500
>> +#define DIV_CPU1        0x14504
>> +
>> +/* list of PLLs to be registered */
>> +enum exynos3250_plls {
>> +    apll, mpll, vpll, upll,
>> +    nr_plls
>> +};
>> +
>> +void __iomem *reg_base;
> 
> static void

I'll fix it.

> 
>> +
>> +/*
>> + * Support for CMU save/restore across system suspends
>> + */
>> +#ifdef CONFIG_PM_SLEEP
>> +static struct samsung_clk_reg_dump *exynos3250_clk_regs;
>> +
>> +static unsigned long exynos3250_cmu_clk_regs[] __initdata = {
>> +    SRC_LEFTBUS,
>> +    DIV_LEFTBUS,
>> +    GATE_IP_LEFTBUS,
>> +    SRC_RIGHTBUS,
>> +    DIV_RIGHTBUS,
>> +    GATE_IP_RIGHTBUS,
>> +    GATE_IP_PERIR,
>> +    MPLL_LOCK,
>> +    MPLL_CON0,
>> +    VPLL_LOCK,
>> +    VPLL_CON0,
>> +    UPLL_LOCK,
>> +    UPLL_CON0,
>> +    SRC_TOP0,
>> +    SRC_TOP1,
>> +    SRC_CAM,
>> +    SRC_MFC,
>> +    SRC_G3D,
>> +    SRC_LCD,
>> +    SRC_ISP,
>> +    SRC_FSYS,
>> +    SRC_PERIL0,
>> +    SRC_PERIL1,
>> +    SRC_MASK_TOP,
>> +    SRC_MASK_CAM,
>> +    SRC_MASK_LCD,
>> +    SRC_MASK_ISP,
>> +    SRC_MASK_FSYS,
>> +    SRC_MASK_PERIL0,
>> +    SRC_MASK_PERIL1,
>> +    DIV_TOP,
>> +    DIV_CAM,
>> +    DIV_MFC,
>> +    DIV_G3D,
>> +    DIV_LCD,
>> +    DIV_ISP,
>> +    DIV_FSYS0,
>> +    DIV_FSYS1,
>> +    DIV_FSYS2,
>> +    DIV_PERIL0,
>> +    DIV_PERIL1,
>> +    DIV_PERIL3,
>> +    DIV_PERIL4,
>> +    DIV_PERIL5,
>> +    DIV_CAM1,
>> +    CLKDIV2_RATIO,
>> +    GATE_SCLK_CAM,
>> +    GATE_SCLK_MFC,
>> +    GATE_SCLK_G3D,
>> +    GATE_SCLK_LCD,
>> +    GATE_SCLK_ISP_TOP,
>> +    GATE_SCLK_FSYS,
>> +    GATE_SCLK_PERIL,
>> +    GATE_IP_CAM,
>> +    GATE_IP_MFC,
>> +    GATE_IP_G3D,
>> +    GATE_IP_LCD,
>> +    GATE_IP_ISP,
>> +    GATE_IP_FSYS,
>> +    GATE_IP_PERIL,
>> +    GATE_BLOCK,
>> +    APLL_LOCK,
>> +    SRC_CPU,
>> +    DIV_CPU0,
>> +    DIV_CPU1,
>> +};
>> +
>> +static int exynos3250_clk_suspend(void)
>> +{
>> +    samsung_clk_save(reg_base, exynos3250_clk_regs,
>> +                ARRAY_SIZE(exynos3250_cmu_clk_regs));
>> +    return 0;
>> +}
>> +
>> +static void exynos3250_clk_resume(void)
>> +{
>> +    samsung_clk_restore(reg_base, exynos3250_clk_regs,
>> +                ARRAY_SIZE(exynos3250_cmu_clk_regs));
>> +}
>> +
>> +static struct syscore_ops exynos3250_clk_syscore_ops = {
>> +    .suspend = exynos3250_clk_suspend,
>> +    .resume = exynos3250_clk_resume,
>> +};
>> +
>> +static void exynos3250_clk_sleep_init(void)
>> +{
>> +    exynos3250_clk_regs =
>> +        samsung_clk_alloc_reg_dump(exynos3250_cmu_clk_regs,
>> +                       ARRAY_SIZE(exynos3250_cmu_clk_regs));
>> +    if (!exynos3250_clk_regs) {
>> +        pr_warn("%s: Failed to allocate sleep save data\n", __func__);
>> +        goto err;
>> +    }
>> +
>> +    register_syscore_ops(&exynos3250_clk_syscore_ops);
>> +    return;
>> +err:
>> +    kfree(exynos3250_clk_regs);
>> +}
>> +#else
>> +static inline void exynos3250_clk_sleep_init(void) { }
>> +#endif
>> +
>> +/* list of all parent clock list */
>> +PNAME(mout_vpllsrc_p)        = { "fin_pll", };
>> +
>> +PNAME(mout_apll_p)        = { "fin_pll", "fout_apll", };
>> +PNAME(mout_mpll_p)        = { "fin_pll", "fout_mpll", };
>> +PNAME(mout_vpll_p)        = { "fin_pll", "fout_vpll", };
>> +PNAME(mout_upll_p)        = { "fin_pll", "fout_upll", };
>> +
>> +PNAME(mout_mpll_user_p)        = { "fin_pll", "div_mpll_pre", };
>> +PNAME(mout_epll_user_p)        = { "fin_pll", "mout_epll", };
>> +PNAME(mout_core_p)        = { "mout_apll", "mout_mpll_user_c", };
>> +PNAME(mout_hpm_p)        = { "mout_apll", "mout_mpll_user_c", };
>> +
>> +PNAME(mout_ebi_p)        = { "div_aclk_200", "div_aclk_160", };
>> +PNAME(mout_ebi_1_p)        = { "mout_ebi", "mout_vpll", };
>> +
>> +PNAME(mout_gdl_p)        = { "mout_mpll_user_l", };
>> +PNAME(mout_gdr_p)        = { "mout_mpll_user_r", };
>> +
>> +PNAME(mout_aclk_400_mcuisp_sub_p)
>> +                = { "fin_pll", "div_aclk_400_mcuisp", };
>> +PNAME(mout_aclk_266_0_p)    = { "div_mpll_pre", "mout_vpll", };
>> +PNAME(mout_aclk_266_1_p)    = { "mout_epll_user", };
>> +PNAME(mout_aclk_266_p)        = { "mout_aclk_266_0", "mout_aclk_266_1", };
>> +PNAME(mout_aclk_266_sub_p)    = { "fin_pll", "div_aclk_266", };
>> +
>> +PNAME(group_div_mpll_pre_p)    = { "div_mpll_pre", };
>> +PNAME(group_epll_vpll_p)    = { "mout_epll_user", "mout_vpll" };
>> +PNAME(group_sclk_p)        = { "xxti", "xusbxti",
>> +                    "none", "none",
>> +                    "none", "none", "div_mpll_pre",
>> +                    "mout_epll_user", "mout_vpll", };
>> +PNAME(group_sclk_audio_p)    = { "audiocdclk", "none",
>> +                    "none", "none",
>> +                    "xxti", "xusbxti",
>> +                    "div_mpll_pre", "mout_epll_user",
>> +                    "mout_vpll", };
>> +PNAME(group_sclk_cam_blk_p)    = { "xxti", "xusbxti",
>> +                    "none", "none", "none",
>> +                    "none", "div_mpll_pre",
>> +                    "mout_epll_user", "mout_vpll",
>> +                    "div_cam_blk_320", };
>> +PNAME(group_sclk_fimd0_p)    = { "xxti", "xusbxti",
>> +                    "m_bitclkhsdiv4_2l", "none",
>> +                    "none", "none", "div_mpll_pre",
>> +                    "mout_epll_user", "mout_vpll",
>> +                    "none", "none", "none",
>> +                    "div_lcd_blk_145", };
>> +
>> +PNAME(mout_mfc_p)        = { "mout_mfc_0", "mout_mfc_1" };
>> +PNAME(mout_g3d_p)        = { "mout_g3d_0", "mout_g3d_1" };
>> +
>> +static struct samsung_fixed_rate_clock fixed_rate_clks[] __initdata = {
>> +};
> 
> Any reason to have this empty array at all?

OK, I'll delete empty array.

> 
>> +
>> +static struct samsung_fixed_factor_clock fixed_factor_clks[] __initdata = {
>> +    FFACTOR(0, "sclk_mpll_1600", "mout_mpll", 1, 1, 0),
>> +    FFACTOR(0, "sclk_mpll_mif", "mout_mpll", 1, 2, 0),
>> +    FFACTOR(0, "sclk_bpll", "fout_bpll", 1, 2, 0),
>> +    FFACTOR(0, "div_cam_blk_320", "sclk_mpll_1600", 1, 5, 0),
>> +    FFACTOR(0, "div_lcd_blk_145", "sclk_mpll_1600", 1, 11, 0),
>> +
>> +    FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0),
> 
> This is a hack. The real "fin_pll" is a mux driven by XOM pin which selects which clock input is used as main system oscillator. It should be implemented properly in this driver or at least appropriate comment should be added stressing the fact that it is a hack.

OK, I'll add comment about it and if you ok, I'll send a further patchset to set relation
between fin_pll and xusbxti/xxti by reading XOM pin of chipid register.

> 
>> +};
>> +
>> +static struct samsung_mux_clock mux_clks[] __initdata = {
>> +    /*
>> +     * NOTE: Following table is sorted by register address in ascending
>> +     * order and then bitfield shift in descending order, as it is done
>> +     * in the User's Manual. When adding new entries, please make sure
>> +     * that the order is preserved, to avoid merge conflicts and make
>> +     * further work with defined data easier.
>> +     */
>> +
>> +    /* SRC_LEFTBUS */
>> +    MUX(CLK_MOUT_MPLL_USER_L, "mout_mpll_user_l", mout_mpll_user_p,
>> +        SRC_LEFTBUS, 4, 1),
>> +    MUX(CLK_MOUT_GDL, "mout_gdl", mout_gdl_p, SRC_LEFTBUS, 0, 1),
>> +
>> +    /* SRC_RIGHTBUS */
>> +    MUX(CLK_MOUT_MPLL_USER_R, "mout_mpll_user_r", mout_mpll_user_p,
>> +        SRC_RIGHTBUS, 4, 1),
>> +    MUX(CLK_MOUT_GDR, "mout_gdr", mout_gdr_p, SRC_RIGHTBUS, 0, 1),
>> +
>> +    /* SRC_TOP0 */
>> +    MUX(CLK_MOUT_EBI, "mout_ebi", mout_ebi_p, SRC_TOP0, 28, 1),
>> +    MUX(CLK_MOUT_ACLK_200, "mout_aclk_200", group_div_mpll_pre_p,SRC_TOP0, 24, 1),
>> +    MUX(CLK_MOUT_ACLK_160, "mout_aclk_160", group_div_mpll_pre_p, SRC_TOP0, 20, 1),
>> +    MUX(CLK_MOUT_ACLK_100, "mout_aclk_100", group_div_mpll_pre_p, SRC_TOP0, 16, 1),
>> +    MUX(CLK_MOUT_ACLK_266_1, "mout_aclk_266_1", mout_aclk_266_1_p, SRC_TOP0, 14, 1),
>> +    MUX(CLK_MOUT_ACLK_266_0, "mout_aclk_266_0", mout_aclk_266_0_p, SRC_TOP0, 13, 1),
>> +    MUX(CLK_MOUT_ACLK_266, "mout_aclk_266", mout_aclk_266_p, SRC_TOP0, 12, 1),
>> +    MUX(CLK_MOUT_VPLL, "mout_vpll", mout_vpll_p, SRC_TOP0, 8, 1),
>> +    MUX(CLK_MOUT_EPLL_USER, "mout_epll_user", mout_epll_user_p, SRC_TOP0, 4, 1),
>> +    MUX(CLK_MOUT_EBI_1, "mout_ebi_1", mout_ebi_1_p, SRC_TOP0, 0, 1),
>> +
>> +    /* SRC_TOP1 */
>> +    MUX(CLK_MOUT_UPLL, "mout_upll", mout_upll_p, SRC_TOP1, 28, 1),
>> +    MUX(CLK_MOUT_ACLK_400_MCUISP_SUB, "mout_aclk_400_mcuisp_sub", mout_aclk_400_mcuisp_sub_p,
>> +        SRC_TOP1, 24, 1),
>> +    MUX(CLK_MOUT_ACLK_266_SUB, "mout_aclk_266_sub", mout_aclk_266_sub_p, SRC_TOP1, 20, 1),
>> +    MUX(CLK_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_TOP1, 12, 1),
>> +    MUX(CLK_MOUT_ACLK_400_MCUISP, "mout_aclk_400_mcuisp", group_div_mpll_pre_p, SRC_TOP1, 8, 1),
>> +    MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
>> +
>> +    /* SRC_CAM */
>> +    MUX(CLK_MOUT_CAM1, "mout_cam1", group_sclk_p, SRC_CAM, 20, 4),
>> +    MUX(CLK_MOUT_CAM_BLK, "mout_cam_blk", group_sclk_cam_blk_p, SRC_CAM, 0, 4),
>> +
>> +    /* SRC_MFC */
>> +    MUX(CLK_MOUT_MFC, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
>> +    MUX(CLK_MOUT_MFC_1, "mout_mfc_1", group_epll_vpll_p, SRC_MFC, 4, 1),
>> +    MUX(CLK_MOUT_MFC_0, "mout_mfc_0", group_div_mpll_pre_p, SRC_MFC, 0, 1),
>> +
>> +    /* SRC_G3D */
>> +    MUX(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1),
>> +    MUX(CLK_MOUT_G3D_1, "mout_g3d_1", group_epll_vpll_p, SRC_G3D, 4, 1),
>> +    MUX(CLK_MOUT_G3D_0, "mout_g3d_0", group_div_mpll_pre_p, SRC_G3D, 0, 1),
>> +
>> +    /* SRC_LCD */
>> +    MUX(CLK_MOUT_MIPI0, "mout_mipi0", group_sclk_p, SRC_LCD, 12, 4),
>> +    MUX(CLK_MOUT_FIMD0, "mout_fimd0", group_sclk_fimd0_p, SRC_LCD, 0, 4),
>> +
>> +    /* SRC_ISP */
>> +    MUX(CLK_MOUT_UART_ISP, "mout_uart_isp", group_sclk_p, SRC_ISP, 12, 4),
>> +    MUX(CLK_MOUT_SPI1_ISP, "mout_spi1_isp", group_sclk_p, SRC_ISP, 8, 4),
>> +    MUX(CLK_MOUT_SPI0_ISP, "mout_spi0_isp", group_sclk_p, SRC_ISP, 4, 4),
>> +
>> +    /* SRC_FSYS */
>> +    MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),
>> +    MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 3),
>> +    MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 3),
>> +
>> +    /* SRC_PERIL0 */
>> +    MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),
>> +    MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),
>> +
>> +    /* SRC_PERIL1 */
>> +    MUX(CLK_MOUT_SPI1, "mout_spi1", group_sclk_p, SRC_PERIL1, 20, 4),
>> +    MUX(CLK_MOUT_SPI0, "mout_spi0", group_sclk_p, SRC_PERIL1, 16, 4),
>> +    MUX(CLK_MOUT_AUDIO, "mout_audio", group_sclk_audio_p, SRC_PERIL1, 4, 4),
>> +
>> +    /* SRC_CPU */
>> +    MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p,
>> +        SRC_CPU, 24, 1),
>> +    MUX(CLK_MOUT_HPM, "mout_hpm", mout_hpm_p, SRC_CPU, 20, 1),
>> +    MUX(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1),
>> +    MUX(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
>> +};
>> +
>> +static struct samsung_div_clock div_clks[] __initdata = {
>> +    /*
>> +     * NOTE: Following table is sorted by register address in ascending
>> +     * order and then bitfield shift in descending order, as it is done
>> +     * in the User's Manual. When adding new entries, please make sure
>> +     * that the order is preserved, to avoid merge conflicts and make
>> +     * further work with defined data easier.
>> +     */
>> +
>> +    /* DIV_LEFTBUS */
>> +    DIV(CLK_DIV_GPL, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
>> +    DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 4),
>> +
>> +    /* DIV_RIGHTBUS */
>> +    DIV(CLK_DIV_GPR, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
>> +    DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 4),
>> +
>> +    /* DIV_TOP */
>> +    DIV(CLK_DIV_MPLL_PRE, "div_mpll_pre", "sclk_mpll_mif", DIV_TOP, 28, 2),
>> +    DIV(CLK_DIV_ACLK_400_MCUISP, "div_aclk_400_mcuisp",
>> +        "mout_aclk_400_mcuisp", DIV_TOP, 24, 3),
>> +    DIV(CLK_DIV_EBI, "div_ebi", "mout_ebi_1", DIV_TOP, 16, 3),
>> +    DIV(CLK_DIV_ACLK_200, "div_aclk_200", "mout_aclk_200", DIV_TOP, 12, 3),
>> +    DIV(CLK_DIV_ACLK_160, "div_aclk_160", "mout_aclk_160", DIV_TOP, 8, 3),
>> +    DIV(CLK_DIV_ACLK_100, "div_aclk_100", "mout_aclk_100", DIV_TOP, 4, 4),
>> +    DIV(CLK_DIV_ACLK_266, "div_aclk_266", "mout_aclk_266", DIV_TOP, 0, 3),
>> +
>> +    /* DIV_CAM */
>> +    DIV(CLK_DIV_CAM1, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
>> +    DIV(CLK_DIV_CAM_BLK, "div_cam_blk", "mout_cam_blk", DIV_CAM, 0, 4),
>> +
>> +    /* DIV_MFC */
>> +    DIV(CLK_DIV_MFC, "div_mfc", "mout_mfc", DIV_MFC, 0, 4),
>> +
>> +    /* DIV_G3D */
>> +    DIV(CLK_DIV_G3D, "div_g3d", "mout_g3d", DIV_G3D, 0, 4),
>> +
>> +    /* DIV_LCD */
>> +    DIV_F(CLK_DIV_MIPI0_PRE, "div_mipi0_pre", "div_mipi0", DIV_LCD, 20, 4,
>> +        CLK_SET_RATE_PARENT, 0),
>> +    DIV(CLK_DIV_MIPI0, "div_mipi0", "mout_mipi0", DIV_LCD, 16, 4),
>> +    DIV(CLK_DIV_FIMD0, "div_fimd0", "mout_fimd0", DIV_LCD, 0, 4),
>> +
>> +    /* DIV_ISP */
>> +    DIV(CLK_DIV_UART_ISP, "div_uart_isp", "mout_uart_isp", DIV_ISP, 28, 4),
>> +    DIV_F(CLK_DIV_SPI1_ISP_PRE, "div_spi1_isp_pre", "div_spi1_isp",
>> +        DIV_ISP, 20, 8, CLK_SET_RATE_PARENT, 0),
>> +    DIV(CLK_DIV_SPI1_ISP, "div_spi1_isp", "mout_spi1_isp", DIV_ISP, 16, 4),
>> +    DIV_F(CLK_DIV_SPI0_ISP_PRE, "div_spi0_isp_pre", "div_spi0_isp",
>> +        DIV_ISP, 8, 8, CLK_SET_RATE_PARENT, 0),
>> +    DIV(CLK_DIV_SPI0_ISP, "div_spi0_isp", "mout_spi0_isp", DIV_ISP, 0, 4),
>> +
>> +    /* DIV_FSYS0 */
>> +    DIV_F(CLK_DIV_TSADC_PRE, "div_tsadc_pre", "div_tsadc", DIV_FSYS0, 8, 8,
>> +        CLK_SET_RATE_PARENT, 0),
>> +    DIV(CLK_DIV_TSADC, "div_tsadc", "mout_tsadc", DIV_FSYS0, 0, 4),
>> +
>> +    /* DIV_FSYS1 */
>> +    DIV_F(CLK_DIV_MMC1_PRE, "div_mmc1_pre", "div_mmc1", DIV_FSYS1, 24, 8,
>> +        CLK_SET_RATE_PARENT, 0),
>> +    DIV(CLK_DIV_MMC1, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
>> +    DIV_F(CLK_DIV_MMC0_PRE, "div_mmc0_pre", "div_mmc0", DIV_FSYS1, 8, 8,
>> +        CLK_SET_RATE_PARENT, 0),
>> +    DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
>> +
>> +    /* DIV_PERIL0 */
>> +    DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
>> +    DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
>> +
>> +    /* DIV_PERIL1 */
>> +    DIV_F(CLK_DIV_SPI1_PRE, "div_spi1_pre", "div_spi1", DIV_PERIL1, 24, 8,
>> +        CLK_SET_RATE_PARENT, 0),
>> +    DIV(CLK_DIV_SPI1, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
>> +    DIV_F(CLK_DIV_SPI0_PRE, "div_spi0_pre", "div_spi0", DIV_PERIL1, 8, 8,
>> +        CLK_SET_RATE_PARENT, 0),
>> +    DIV(CLK_DIV_SPI0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
>> +
>> +    /* DIV_PERIL4 */
>> +    DIV(CLK_DIV_PCM, "div_pcm", "div_audio", DIV_PERIL4, 20, 8),
>> +    DIV(CLK_DIV_AUDIO, "div_audio", "mout_audio", DIV_PERIL4, 16, 4),
>> +
>> +    /* DIV_PERIL5 */
>> +    DIV(CLK_DIV_I2S, "div_i2s", "div_audio", DIV_PERIL5, 8, 6),
>> +
>> +    /* DIV_CPU0 */
>> +    DIV(CLK_DIV_CORE2, "div_core2", "div_core", DIV_CPU0, 28, 3),
>> +    DIV(CLK_DIV_APLL, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
>> +    DIV(CLK_DIV_PCLK_DBG, "div_pclk_dbg", "div_core2", DIV_CPU0, 20, 3),
>> +    DIV(CLK_DIV_ATB, "div_atb", "div_core2", DIV_CPU0, 16, 3),
>> +    DIV(CLK_DIV_COREM, "div_corem", "div_core2", DIV_CPU0, 4, 3),
>> +    DIV(CLK_DIV_CORE, "div_core", "mout_core", DIV_CPU0, 0, 3),
>> +
>> +    /* DIV_CPU1 */
>> +    DIV(CLK_DIV_HPM, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
>> +    DIV(CLK_DIV_COPY, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
>> +};
>> +
>> +static struct samsung_gate_clock gate_clks[] __initdata = {
>> +    /*
>> +     * NOTE: Following table is sorted by register address in ascending
>> +     * order and then bitfield shift in descending order, as it is done
>> +     * in the User's Manual. When adding new entries, please make sure
>> +     * that the order is preserved, to avoid merge conflicts and make
>> +     * further work with defined data easier.
>> +     */
>> +
>> +    /* GATE_IP_LEFTBUS */
>> +    GATE(CLK_ASYNC_G3D, "async_g3d", "div_aclk_100", GATE_IP_LEFTBUS, 6,
>> +        CLK_IGNORE_UNUSED, 0),
>> +    GATE(CLK_ASYNC_MFCL, "async_mfcl", "div_aclk_100", GATE_IP_LEFTBUS, 4,
>> +        CLK_IGNORE_UNUSED, 0),
>> +    GATE(CLK_PPMULEFT, "ppmuleft", "div_aclk_100", GATE_IP_LEFTBUS, 1,
>> +        CLK_IGNORE_UNUSED, 0),
>> +    GATE(CLK_GPIO_LEFT, "gpio_left", "div_aclk_100", GATE_IP_LEFTBUS, 0,
>> +        CLK_IGNORE_UNUSED, 0),
>> +
>> +    /* GATE_IP_RIGHTBUS */
>> +    GATE(CLK_ASYNC_ISPMX, "async_ispmx", "div_aclk_100",
>> +        GATE_IP_RIGHTBUS, 9, CLK_IGNORE_UNUSED, 0),
>> +    GATE(CLK_ASYNC_FSYSD, "async_fsysd", "div_aclk_100",
>> +        GATE_IP_RIGHTBUS, 5, CLK_IGNORE_UNUSED, 0),
>> +    GATE(CLK_ASYNC_LCD0X, "async_lcd0x", "div_aclk_100",
>> +        GATE_IP_RIGHTBUS, 3, CLK_IGNORE_UNUSED, 0),
>> +    GATE(CLK_ASYNC_CAMX, "async_camx", "div_aclk_100", GATE_IP_RIGHTBUS, 2,
>> +        CLK_IGNORE_UNUSED, 0),
>> +    GATE(CLK_PPMURIGHT, "ppmuright", "div_aclk_100", GATE_IP_RIGHTBUS, 1,
>> +        CLK_IGNORE_UNUSED, 0),
>> +    GATE(CLK_GPIO_RIGHT, "gpio_right", "div_aclk_100", GATE_IP_RIGHTBUS, 0,
>> +        CLK_IGNORE_UNUSED, 0),
>> +
>> +    /* GATE_IP_PERIR */
>> +    GATE(CLK_MONOCNT, "monocnt", "div_aclk_100", GATE_IP_PERIR, 22,
>> +        CLK_IGNORE_UNUSED, 0),
>> +    GATE(CLK_TZPC6, "tzpc6", "div_aclk_100", GATE_IP_PERIR, 21,
>> +        CLK_IGNORE_UNUSED, 0),
>> +    GATE(CLK_PROVISIONKEY1, "provisionkey1", "div_aclk_100",
>> +        GATE_IP_PERIR, 20, CLK_IGNORE_UNUSED, 0),
>> +    GATE(CLK_PROVISIONKEY0, "provisionkey0", "div_aclk_100",
>> +        GATE_IP_PERIR, 19, CLK_IGNORE_UNUSED, 0),
>> +    GATE(CLK_CMU_ISPPART, "cmu_isppart", "div_aclk_100", GATE_IP_PERIR, 18,
>> +        CLK_IGNORE_UNUSED, 0),
>> +    GATE(CLK_TMU_APBIF, "tmu_apbif", "div_aclk_100",
>> +        GATE_IP_PERIR, 17, 0, 0),
>> +    GATE(CLK_KEYIF, "keyif", "div_aclk_100", GATE_IP_PERIR, 16, 0, 0),
>> +    GATE(CLK_RTC, "rtc", "div_aclk_100", GATE_IP_PERIR, 15, 0, 0),
>> +    GATE(CLK_WDT, "wdt", "div_aclk_100", GATE_IP_PERIR, 14, 0, 0),
>> +    GATE(CLK_MCT, "mct", "div_aclk_100", GATE_IP_PERIR, 13, 0, 0),
>> +    GATE(CLK_SECKEY, "seckey", "div_aclk_100", GATE_IP_PERIR, 12,
>> +        CLK_IGNORE_UNUSED, 0),
>> +    GATE(CLK_TZPC5, "tzpc5", "div_aclk_100", GATE_IP_PERIR, 10,
>> +        CLK_IGNORE_UNUSED, 0),
>> +    GATE(CLK_TZPC4, "tzpc4", "div_aclk_100", GATE_IP_PERIR, 9,
>> +        CLK_IGNORE_UNUSED, 0),
>> +    GATE(CLK_TZPC3, "tzpc3", "div_aclk_100", GATE_IP_PERIR, 8,
>> +        CLK_IGNORE_UNUSED, 0),
>> +    GATE(CLK_TZPC2, "tzpc2", "div_aclk_100", GATE_IP_PERIR, 7,
>> +        CLK_IGNORE_UNUSED, 0),
>> +    GATE(CLK_TZPC1, "tzpc1", "div_aclk_100", GATE_IP_PERIR, 6,
>> +        CLK_IGNORE_UNUSED, 0),
>> +    GATE(CLK_TZPC0, "tzpc0", "div_aclk_100", GATE_IP_PERIR, 5,
>> +        CLK_IGNORE_UNUSED, 0),
>> +    GATE(CLK_CMU_COREPART, "cmu_corepart", "div_aclk_100", GATE_IP_PERIR, 4,
>> +        CLK_IGNORE_UNUSED, 0),
>> +    GATE(CLK_CMU_TOPPART, "cmu_toppart", "div_aclk_100", GATE_IP_PERIR, 3,
>> +        CLK_IGNORE_UNUSED, 0),
>> +    GATE(CLK_PMU_APBIF, "pmu_apbif", "div_aclk_100", GATE_IP_PERIR, 2,
>> +        CLK_IGNORE_UNUSED, 0),
>> +    GATE(CLK_SYSREG, "sysreg", "div_aclk_100", GATE_IP_PERIR, 1,
>> +        CLK_IGNORE_UNUSED, 0),
>> +    GATE(CLK_CHIP_ID, "chip_id", "div_aclk_100", GATE_IP_PERIR, 0,
>> +        CLK_IGNORE_UNUSED, 0),
>> +
>> +    /* GATE_SCLK_CAM */
>> +    GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_cam_blk",
>> +        GATE_SCLK_CAM, 8, CLK_SET_RATE_PARENT, 0),
>> +    GATE(CLK_SCLK_M2MSCALER, "sclk_m2mscaler", "div_cam_blk",
>> +        GATE_SCLK_CAM, 2, CLK_SET_RATE_PARENT, 0),
>> +    GATE(CLK_SCLK_GSCALER1, "sclk_gscaler1", "div_cam_blk",
>> +        GATE_SCLK_CAM, 1, CLK_SET_RATE_PARENT, 0),
>> +    GATE(CLK_SCLK_GSCALER0, "sclk_gscaler0", "div_cam_blk",
>> +        GATE_SCLK_CAM, 0, CLK_SET_RATE_PARENT, 0),
>> +
>> +    /* GATE_SCLK_MFC */
>> +    GATE(CLK_SCLK_MFC, "sclk_mfc", "div_mfc",
>> +        GATE_SCLK_MFC, 0, CLK_SET_RATE_PARENT, 0),
>> +
>> +    /* GATE_SCLK_G3D */
>> +    GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d",
>> +        GATE_SCLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
>> +
>> +    /* GATE_SCLK_LCD */
>> +    GATE(CLK_SCLK_MIPIDPHY2L, "sclk_mipidphy2l", "div_mipi0",
>> +        GATE_SCLK_LCD, 4, CLK_SET_RATE_PARENT, 0),
>> +    GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi0_pre",
>> +        GATE_SCLK_LCD, 3, CLK_SET_RATE_PARENT, 0),
>> +    GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0",
>> +        GATE_SCLK_LCD, 0, CLK_SET_RATE_PARENT, 0),
>> +
>> +    /* GATE_SCLK_ISP_TOP */
>> +    GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
>> +        GATE_SCLK_ISP_TOP, 4, CLK_SET_RATE_PARENT, 0),
>> +    GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "div_uart_isp",
>> +        GATE_SCLK_ISP_TOP, 3, CLK_SET_RATE_PARENT, 0),
>> +    GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "div_spi1_isp",
>> +        GATE_SCLK_ISP_TOP, 2, CLK_SET_RATE_PARENT, 0),
>> +    GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "div_spi0_isp",
>> +        GATE_SCLK_ISP_TOP, 1, CLK_SET_RATE_PARENT, 0),
>> +
>> +    /* GATE_SCLK_FSYS */
>> +    GATE(CLK_SCLK_UPLL, "sclk_upll", "mout_upll", GATE_SCLK_FSYS, 10, 0, 0),
>> +    GATE(CLK_SCLK_TSADC, "sclk_tsadc", "div_tsadc_pre",
>> +        GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
>> +    GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",
>> +        GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),
>> +    GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre",
>> +        GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
>> +    GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",
>> +        GATE_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
>> +
>> +    /* GATE_SCLK_PERIL */
>> +    GATE(CLK_SCLK_I2S, "sclk_i2s", "div_i2s",
>> +        GATE_SCLK_PERIL, 18, CLK_SET_RATE_PARENT, 0),
>> +    GATE(CLK_SCLK_PCM, "sclk_pcm", "div_pcm",
>> +        GATE_SCLK_PERIL, 16, CLK_SET_RATE_PARENT, 0),
>> +    GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi1_pre",
>> +        GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
>> +    GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
>> +        GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
>> +    GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
>> +        GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
>> +    GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
>> +        GATE_SCLK_PERIL, 0, CLK_SET_RATE_PARENT, 0),
>> +
>> +    /* GATE_IP_CAM */
>> +    GATE(CLK_QEJPEG, "qejpeg", "div_cam_blk_320", GATE_IP_CAM, 19,
>> +        CLK_IGNORE_UNUSED, 0),
>> +    GATE(CLK_PIXELASYNCM1, "pixelasyncm1", "div_cam_blk_320",
>> +        GATE_IP_CAM, 18, CLK_IGNORE_UNUSED, 0),
>> +    GATE(CLK_PIXELASYNCM0, "pixelasyncm0", "div_cam_blk_320",
>> +        GATE_IP_CAM, 17, CLK_IGNORE_UNUSED, 0),
>> +    GATE(CLK_PPMUCAMIF, "ppmucamif", "div_cam_blk_320",
>> +        GATE_IP_CAM, 16, CLK_IGNORE_UNUSED, 0),
>> +    GATE(CLK_QEM2MSCALER, "qem2mscaler", "div_cam_blk_320",
>> +        GATE_IP_CAM, 14, CLK_IGNORE_UNUSED, 0),
>> +    GATE(CLK_QEGSCALER1, "qegscaler1", "div_cam_blk_320",
>> +        GATE_IP_CAM, 13, CLK_IGNORE_UNUSED, 0),
>> +    GATE(CLK_QEGSCALER0, "qegscaler0", "div_cam_blk_320",
>> +        GATE_IP_CAM, 12, CLK_IGNORE_UNUSED, 0),
>> +    GATE(CLK_SMMUJPEG, "smmujpeg", "div_cam_blk_320",
>> +        GATE_IP_CAM, 11, 0, 0),
>> +    GATE(CLK_SMMUM2M2SCALER, "smmum2m2scaler", "div_cam_blk_320",
>> +        GATE_IP_CAM, 9, 0, 0),
>> +    GATE(CLK_SMMUGSCALER1, "smmugscaler1", "div_cam_blk_320",
>> +        GATE_IP_CAM, 8, 0, 0),
>> +    GATE(CLK_SMMUGSCALER0, "smmugscaler0", "div_cam_blk_320",
>> +        GATE_IP_CAM, 7, 0, 0),
>> +    GATE(CLK_JPEG, "jpeg", "div_cam_blk_320", GATE_IP_CAM, 6, 0, 0),
>> +    GATE(CLK_M2MSCALER, "m2mscaler", "div_cam_blk_320",
>> +        GATE_IP_CAM, 2, 0, 0),
>> +    GATE(CLK_GSCALER1, "gscaler1", "div_cam_blk_320", GATE_IP_CAM, 1, 0, 0),
>> +    GATE(CLK_GSCALER0, "gscaler0", "div_cam_blk_320", GATE_IP_CAM, 0, 0, 0),
>> +
>> +    /* GATE_IP_MFC */
>> +    GATE(CLK_QEMFC, "qemfc", "div_aclk_200", GATE_IP_MFC, 5,
>> +        CLK_IGNORE_UNUSED, 0),
>> +    GATE(CLK_PPMUMFC_L, "ppmumfc_l", "div_aclk_200", GATE_IP_MFC, 3,
>> +        CLK_IGNORE_UNUSED, 0),
>> +    GATE(CLK_SMMUMFC_L, "smmumfc_l", "div_aclk_200", GATE_IP_MFC, 1, 0, 0),
>> +    GATE(CLK_MFC, "mfc", "div_aclk_200", GATE_IP_MFC, 0, 0, 0),
>> +
>> +    /* GATE_IP_G3D */
>> +    GATE(CLK_SMMUG3D, "smmug3d", "div_aclk_200", GATE_IP_G3D, 3, 0, 0),
>> +    GATE(CLK_QEG3D, "qeg3d", "div_aclk_200", GATE_IP_G3D, 2,
>> +        CLK_IGNORE_UNUSED, 0),
>> +    GATE(CLK_PPMUG3D, "ppmug3d", "div_aclk_200", GATE_IP_G3D, 1,
>> +        CLK_IGNORE_UNUSED, 0),
>> +    GATE(CLK_G3D, "g3d", "div_aclk_200", GATE_IP_G3D, 0, 0, 0),
>> +
>> +    /* GATE_IP_LCD */
>> +    GATE(CLK_QE_CH1_LCD, "qe_ch1_lcd", "div_aclk_160", GATE_IP_LCD, 7,
>> +        CLK_IGNORE_UNUSED, 0),
>> +    GATE(CLK_QE_CH0_LCD, "qe_ch0_lcd", "div_aclk_160", GATE_IP_LCD, 6,
>> +        CLK_IGNORE_UNUSED, 0),
>> +    GATE(CLK_PPMULCD0, "ppmulcd0", "div_aclk_160", GATE_IP_LCD, 5,
>> +        CLK_IGNORE_UNUSED, 0),
>> +    GATE(CLK_SMMUFIMD0, "smmufimd0", "div_aclk_160", GATE_IP_LCD, 4, 0, 0),
>> +    GATE(CLK_DSIM0, "dsim0", "div_aclk_160", GATE_IP_LCD, 3, 0, 0),
>> +    GATE(CLK_SMIES, "smies", "div_aclk_160", GATE_IP_LCD, 2, 0, 0),
>> +    GATE(CLK_FIMD0, "fimd0", "div_aclk_160", GATE_IP_LCD, 0, 0, 0),
>> +
>> +    /* GATE_IP_ISP */
>> +    GATE(CLK_CAM1, "cam1", "mout_aclk_266_sub", GATE_IP_ISP, 5, 0, 0),
>> +    GATE(CLK_UART_ISP_TOP, "uart_isp_top", "mout_aclk_266_sub",
>> +        GATE_IP_ISP, 3, 0, 0),
>> +    GATE(CLK_SPI1_ISP_TOP, "spi1_isp_top", "mout_aclk_266_sub",
>> +        GATE_IP_ISP, 2, 0, 0),
>> +    GATE(CLK_SPI0_ISP_TOP, "spi0_isp_top", "mout_aclk_266_sub",
>> +        GATE_IP_ISP, 1, 0, 0),
>> +
>> +    /* GATE_IP_FSYS */
>> +    GATE(CLK_TSADC, "tsadc", "div_aclk_200", GATE_IP_FSYS, 20, 0, 0),
>> +    GATE(CLK_PPMUFILE, "ppmufile", "div_aclk_200", GATE_IP_FSYS, 17,
>> +        CLK_IGNORE_UNUSED, 0),
>> +    GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0),
>> +    GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
>> +    GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
>> +    GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
>> +    GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
>> +    GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
>> +    GATE(CLK_PDMA0, "pdma0", "div_aclk_200", GATE_IP_FSYS, 0, 0, 0),
>> +
>> +    /* GATE_IP_PERIL */
>> +    GATE(CLK_PWM, "pwm", "div_aclk_100", GATE_IP_PERIL, 24, 0, 0),
>> +    GATE(CLK_PCM, "pcm", "div_aclk_100", GATE_IP_PERIL, 23, 0, 0),
>> +    GATE(CLK_I2S, "i2s", "div_aclk_100", GATE_IP_PERIL, 21, 0, 0),
>> +    GATE(CLK_SPI1, "spi1", "div_aclk_100", GATE_IP_PERIL, 17, 0, 0),
>> +    GATE(CLK_SPI0, "spi0", "div_aclk_100", GATE_IP_PERIL, 16, 0, 0),
>> +    GATE(CLK_I2C7, "i2c7", "div_aclk_100", GATE_IP_PERIL, 13, 0, 0),
>> +    GATE(CLK_I2C6, "i2c6", "div_aclk_100", GATE_IP_PERIL, 12, 0, 0),
>> +    GATE(CLK_I2C5, "i2c5", "div_aclk_100", GATE_IP_PERIL, 11, 0, 0),
>> +    GATE(CLK_I2C4, "i2c4", "div_aclk_100", GATE_IP_PERIL, 10, 0, 0),
>> +    GATE(CLK_I2C3, "i2c3", "div_aclk_100", GATE_IP_PERIL, 9, 0, 0),
>> +    GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
>> +    GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
>> +    GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
>> +    GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
>> +    GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
>> +
>> +    /* GATE_BLOCK */
>> +    GATE(CLK_BLOCK_LCD, "block_lcd", "div_aclk_160", GATE_BLOCK, 4, 0, 0),
>> +    GATE(CLK_BLOCK_G3D, "block_g3d", "div_aclk_200", GATE_BLOCK, 3, 0, 0),
> 
> Are there only 2 gate block clocks? By the way, how are they going to be handled by respective drivers? There is no mainline support for them right now, but you should be aware that adding them will cause common clock framework to disable them if not claimed by any driver.

OK, I'll add remaing clock gate of GATE_BLOCK as following.
- CLK_BLOCK_MFC MFC_BLK
- CLK_BLOCK_CAM CAM_BLK

> 
>> +};
>> +
>> +/* APLL & MPLL & BPLL & UPLL */
>> +static struct samsung_pll_rate_table exynos3250_pll_rates[] = {
>> +    PLL_35XX_RATE(1200000000, 400, 4, 1),
>> +    PLL_35XX_RATE(1100000000, 275, 3, 1),
>> +    PLL_35XX_RATE(1066000000, 533, 6, 1),
>> +    PLL_35XX_RATE(1000000000, 250, 3, 1),
>> +    PLL_35XX_RATE( 960000000, 320, 4, 1),
>> +    PLL_35XX_RATE( 900000000, 300, 4, 1),
>> +    PLL_35XX_RATE( 850000000, 425, 6, 1),
>> +    PLL_35XX_RATE( 800000000, 200, 3, 1),
>> +    PLL_35XX_RATE( 700000000, 175, 3, 1),
>> +    PLL_35XX_RATE( 667000000, 667, 12, 1),
>> +    PLL_35XX_RATE( 600000000, 400, 4, 2),
>> +    PLL_35XX_RATE( 533000000, 533, 6, 2),
>> +    PLL_35XX_RATE( 520000000, 260, 3, 2),
>> +    PLL_35XX_RATE( 500000000, 250, 3, 2),
>> +    PLL_35XX_RATE( 400000000, 200, 3, 2),
>> +    PLL_35XX_RATE( 200000000, 200, 3, 3),
>> +    PLL_35XX_RATE( 100000000, 200, 3, 4),
>> +    { /* sentinel */ }
>> +};
>> +
>> +/* VPLL */
>> +static struct samsung_pll_rate_table exynos3250_vpll_rates[] = {
>> +    PLL_36XX_RATE(600000000, 100, 2, 1,     0),
>> +    PLL_36XX_RATE(533000000, 267, 3, 2, 32668),
>> +    PLL_36XX_RATE(519231000, 173, 2, 2,  5046),
>> +    PLL_36XX_RATE(500000000, 250, 3, 2,     0),
>> +    PLL_36XX_RATE(445500000, 149, 2, 2, 32768),
>> +    PLL_36XX_RATE(445055000, 148, 2, 2, 23047),
>> +    PLL_36XX_RATE(400000000, 200, 3, 2,     0),
>> +    PLL_36XX_RATE(371250000, 124, 2, 2, 49512),
>> +    PLL_36XX_RATE(370879000, 185, 3, 2, 28803),
>> +    PLL_36XX_RATE(340000000, 170, 3, 2,     0),
>> +    PLL_36XX_RATE(335000000, 112, 2, 2, 43691),
>> +    PLL_36XX_RATE(333000000, 111, 2, 2,     0),
>> +    PLL_36XX_RATE(330000000, 110, 2, 2,     0),
>> +    PLL_36XX_RATE(320000000, 107, 2, 2, 43691),
>> +    PLL_36XX_RATE(300000000, 100, 2, 2,     0),
>> +    PLL_36XX_RATE(275000000, 275, 3, 3,     0),
>> +    PLL_36XX_RATE(222750000, 149, 2, 3, 32768),
>> +    PLL_36XX_RATE(222528000, 148, 2, 3, 23069),
>> +    PLL_36XX_RATE(160000000, 160, 3, 3,     0),
>> +    PLL_36XX_RATE(148500000,  99, 2, 3,     0),
>> +    PLL_36XX_RATE(148352000,  99, 2, 3, 59070),
>> +    PLL_36XX_RATE(108000000, 144, 2, 4,     0),
>> +    PLL_36XX_RATE( 74250000,  99, 2, 4,     0),
>> +    PLL_36XX_RATE( 74176000,  99, 3, 4, 59070),
>> +    PLL_36XX_RATE( 54054000, 216, 3, 5, 14156),
>> +    PLL_36XX_RATE( 54000000, 144, 2, 5,     0),
> 
> Are all these frequencies above calculated exactly? For correct operation of rate setting code, it is necessary for frequency values specified in these arrays to be exact, not rounded.

When I implemnted exynos3250_vpll_rates array, I used 'VPLL PMS Value' in Exynos3250 TRM without modification.
This rate value of exynos3250_vpll_rates is correct.

Best Regards,
Chanwoo Choi

Re: [PATCHv4 5/7] clk: samsung: exynos3250: Add clocks using common clock framework

[Tomasz Figa]

Hi Chanwoo,

On 13.05.2014 13:49, Chanwoo Choi wrote:
> Hi Tomasz,
> 
> On 04/26/2014 09:39 AM, Tomasz Figa wrote:
>> Hi Chanwoo,
>>
>> On 25.04.2014 03:16, Chanwoo Choi wrote:
>>> From: Tomasz Figa <t.figa@samsung.com>
>>>
>>> This patch add new the clock drvier of Exynos3250 SoC based on Cortex-A7
>>> using common clock framework. The CMU (Clock Management Unit) of Exynos3250
>>> control PLLs(Phase Locked Loops) and generate system clocks for CPU, buses,
>>> and function clocks for individual IPs.
>>>
>>> The CMU of Exynos3250 includes following clock doamins:
>>> - CPU block for Cortex-A7 MPCore processor
>>> - LEFTBUS/RIGHTBUS block
>>> - TOP block for G3D/MFC/LCD0/ISP/CAM/FSYS/MFC/PERIL/PERIR
>>
>> In original driver present in our internal tree I have separated several CMUs to account for certain factors caused by hardware design, which require such separation. Is there any reason why they were merged together into a single CMU again?
> 
> This patch just include clocks in CMU clocks without CMU_DMC/CMU_ISP.
> I'll send a further patches to support CMU_DMC/CMU_ISP after verifying it.
> 
>>
>>>
>>> Cc: Mike Turquette <mturquette@linaro.org>
>>> Cc: Kukjin Kim <kgene.kim@samsung.com>
>>> Cc: Rob Herring <robh+dt@kernel.org>
>>> Cc: Pawel Moll <pawel.moll@arm.com>
>>> Cc: Mark Rutland <mark.rutland@arm.com>
>>> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
>>> Cc: Kumar Gala <galak@codeaurora.org>
>>> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>> Signed-off-by: Hyunhee Kim <hyunhee.kim@samsung.com>
>>> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
>>> Signed-off-by: Inki Dae <inki.dae@samsung.com>
>>> Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
>>> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
>>> Signed-off-by: Karol Wrona <k.wrona@samsung.com>
>>> Signed-off-by: YoungJun Cho <yj44.cho@samsung.com>
>>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>>> ---
>>>   drivers/clk/samsung/Makefile           |   1 +
>>>   drivers/clk/samsung/clk-exynos3250.c   | 785 +++++++++++++++++++++++++++++++++
>>>   include/dt-bindings/clock/exynos3250.h | 256 +++++++++++
>>>   3 files changed, 1042 insertions(+)
>>>   create mode 100644 drivers/clk/samsung/clk-exynos3250.c
>>>   create mode 100644 include/dt-bindings/clock/exynos3250.h
>>>
>>> diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
>>> index 8eb4799..d120797 100644
>>> --- a/drivers/clk/samsung/Makefile
>>> +++ b/drivers/clk/samsung/Makefile
>>> @@ -3,6 +3,7 @@
>>>   #
>>>
>>>   obj-$(CONFIG_COMMON_CLK)    += clk.o clk-pll.o
>>> +obj-$(CONFIG_SOC_EXYNOS3250)    += clk-exynos3250.o
>>>   obj-$(CONFIG_ARCH_EXYNOS4)    += clk-exynos4.o
>>>   obj-$(CONFIG_SOC_EXYNOS5250)    += clk-exynos5250.o
>>>   obj-$(CONFIG_SOC_EXYNOS5420)    += clk-exynos5420.o
>>> diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
>>> new file mode 100644
>>> index 0000000..0574a76
>>> --- /dev/null
>>> +++ b/drivers/clk/samsung/clk-exynos3250.c
>>> @@ -0,0 +1,785 @@
>>> +/*
>>> + * Copyright (c) 2014 Samsung Electronics Co., Ltd.
>>> + *
>>> + * This program is free software; you can redistribute it and/or modify
>>> + * it under the terms of the GNU General Public License version 2 as
>>> + * published by the Free Software Foundation.
>>> + *
>>> + * Common Clock Framework support for Exynos3250 SoC.
>>> + */
>>> +
>>> +#include <linux/clk.h>
>>> +#include <linux/clkdev.h>
>>> +#include <linux/clk-provider.h>
>>> +#include <linux/of.h>
>>> +#include <linux/of_address.h>
>>> +#include <linux/platform_device.h>
>>> +#include <linux/syscore_ops.h>
>>> +
>>> +#include <dt-bindings/clock/exynos3250.h>
>>> +
>>> +#include "clk.h"
>>> +#include "clk-pll.h"
>>> +
>>> +#define SRC_LEFTBUS        0x4200
>>> +#define DIV_LEFTBUS        0x4500
>>> +#define GATE_IP_LEFTBUS        0x4800
>>> +#define SRC_RIGHTBUS        0x8200
>>> +#define DIV_RIGHTBUS        0x8500
>>> +#define GATE_IP_RIGHTBUS    0x8800
>>> +#define GATE_IP_PERIR        0x8960
>>> +#define MPLL_LOCK        0xc010
>>> +#define MPLL_CON0        0xc110
>>> +#define VPLL_LOCK        0xc020
>>> +#define VPLL_CON0        0xc120
>>> +#define UPLL_LOCK        0xc030
>>> +#define UPLL_CON0        0xc130
>>> +#define SRC_TOP0        0xc210
>>> +#define SRC_TOP1        0xc214
>>> +#define SRC_CAM            0xc220
>>> +#define SRC_MFC            0xc228
>>> +#define SRC_G3D            0xc22c
>>> +#define SRC_LCD            0xc234
>>> +#define SRC_ISP            0xc238
>>> +#define SRC_FSYS        0xc240
>>> +#define SRC_PERIL0        0xc250
>>> +#define SRC_PERIL1        0xc254
>>> +#define SRC_MASK_TOP        0xc310
>>> +#define SRC_MASK_CAM        0xc320
>>> +#define SRC_MASK_LCD        0xc334
>>> +#define SRC_MASK_ISP        0xc338
>>> +#define SRC_MASK_FSYS        0xc340
>>> +#define SRC_MASK_PERIL0        0xc350
>>> +#define SRC_MASK_PERIL1        0xc354
>>> +#define DIV_TOP            0xc510
>>> +#define DIV_CAM            0xc520
>>> +#define DIV_MFC            0xc528
>>> +#define DIV_G3D            0xc52c
>>> +#define DIV_LCD            0xc534
>>> +#define DIV_ISP            0xc538
>>> +#define DIV_FSYS0        0xc540
>>> +#define DIV_FSYS1        0xc544
>>> +#define DIV_FSYS2        0xc548
>>> +#define DIV_PERIL0        0xc550
>>> +#define DIV_PERIL1        0xc554
>>> +#define DIV_PERIL3        0xc55c
>>> +#define DIV_PERIL4        0xc560
>>> +#define DIV_PERIL5        0xc564
>>> +#define DIV_CAM1        0xc568
>>> +#define CLKDIV2_RATIO        0xc580
>>> +#define GATE_SCLK_CAM        0xc820
>>> +#define GATE_SCLK_MFC        0xc828
>>> +#define GATE_SCLK_G3D        0xc82c
>>> +#define GATE_SCLK_LCD        0xc834
>>> +#define GATE_SCLK_ISP_TOP    0xc838
>>> +#define GATE_SCLK_FSYS        0xc840
>>> +#define GATE_SCLK_PERIL        0xc850
>>> +#define GATE_IP_CAM        0xc920
>>> +#define GATE_IP_MFC        0xc928
>>> +#define GATE_IP_G3D        0xc92c
>>> +#define GATE_IP_LCD        0xc934
>>> +#define GATE_IP_ISP        0xc938
>>> +#define GATE_IP_FSYS        0xc940
>>> +#define GATE_IP_PERIL        0xc950
>>> +#define GATE_BLOCK        0xc970
>>> +#define APLL_LOCK        0x14000
>>> +#define APLL_CON0        0x14100
>>> +#define SRC_CPU            0x14200
>>> +#define DIV_CPU0        0x14500
>>> +#define DIV_CPU1        0x14504
>>> +
>>> +/* list of PLLs to be registered */
>>> +enum exynos3250_plls {
>>> +    apll, mpll, vpll, upll,
>>> +    nr_plls
>>> +};
>>> +
>>> +void __iomem *reg_base;
>>
>> static void
> 
> I'll fix it.
> 

OK.

>>
>>> +
>>> +/*
>>> + * Support for CMU save/restore across system suspends
>>> + */
>>> +#ifdef CONFIG_PM_SLEEP
>>> +static struct samsung_clk_reg_dump *exynos3250_clk_regs;
>>> +
>>> +static unsigned long exynos3250_cmu_clk_regs[] __initdata = {
>>> +    SRC_LEFTBUS,
>>> +    DIV_LEFTBUS,
>>> +    GATE_IP_LEFTBUS,
>>> +    SRC_RIGHTBUS,
>>> +    DIV_RIGHTBUS,
>>> +    GATE_IP_RIGHTBUS,
>>> +    GATE_IP_PERIR,
>>> +    MPLL_LOCK,
>>> +    MPLL_CON0,
>>> +    VPLL_LOCK,
>>> +    VPLL_CON0,
>>> +    UPLL_LOCK,
>>> +    UPLL_CON0,
>>> +    SRC_TOP0,
>>> +    SRC_TOP1,
>>> +    SRC_CAM,
>>> +    SRC_MFC,
>>> +    SRC_G3D,
>>> +    SRC_LCD,
>>> +    SRC_ISP,
>>> +    SRC_FSYS,
>>> +    SRC_PERIL0,
>>> +    SRC_PERIL1,
>>> +    SRC_MASK_TOP,
>>> +    SRC_MASK_CAM,
>>> +    SRC_MASK_LCD,
>>> +    SRC_MASK_ISP,
>>> +    SRC_MASK_FSYS,
>>> +    SRC_MASK_PERIL0,
>>> +    SRC_MASK_PERIL1,
>>> +    DIV_TOP,
>>> +    DIV_CAM,
>>> +    DIV_MFC,
>>> +    DIV_G3D,
>>> +    DIV_LCD,
>>> +    DIV_ISP,
>>> +    DIV_FSYS0,
>>> +    DIV_FSYS1,
>>> +    DIV_FSYS2,
>>> +    DIV_PERIL0,
>>> +    DIV_PERIL1,
>>> +    DIV_PERIL3,
>>> +    DIV_PERIL4,
>>> +    DIV_PERIL5,
>>> +    DIV_CAM1,
>>> +    CLKDIV2_RATIO,
>>> +    GATE_SCLK_CAM,
>>> +    GATE_SCLK_MFC,
>>> +    GATE_SCLK_G3D,
>>> +    GATE_SCLK_LCD,
>>> +    GATE_SCLK_ISP_TOP,
>>> +    GATE_SCLK_FSYS,
>>> +    GATE_SCLK_PERIL,
>>> +    GATE_IP_CAM,
>>> +    GATE_IP_MFC,
>>> +    GATE_IP_G3D,
>>> +    GATE_IP_LCD,
>>> +    GATE_IP_ISP,
>>> +    GATE_IP_FSYS,
>>> +    GATE_IP_PERIL,
>>> +    GATE_BLOCK,
>>> +    APLL_LOCK,
>>> +    SRC_CPU,
>>> +    DIV_CPU0,
>>> +    DIV_CPU1,
>>> +};
>>> +
>>> +static int exynos3250_clk_suspend(void)
>>> +{
>>> +    samsung_clk_save(reg_base, exynos3250_clk_regs,
>>> +                ARRAY_SIZE(exynos3250_cmu_clk_regs));
>>> +    return 0;
>>> +}
>>> +
>>> +static void exynos3250_clk_resume(void)
>>> +{
>>> +    samsung_clk_restore(reg_base, exynos3250_clk_regs,
>>> +                ARRAY_SIZE(exynos3250_cmu_clk_regs));
>>> +}
>>> +
>>> +static struct syscore_ops exynos3250_clk_syscore_ops = {
>>> +    .suspend = exynos3250_clk_suspend,
>>> +    .resume = exynos3250_clk_resume,
>>> +};
>>> +
>>> +static void exynos3250_clk_sleep_init(void)
>>> +{
>>> +    exynos3250_clk_regs =
>>> +        samsung_clk_alloc_reg_dump(exynos3250_cmu_clk_regs,
>>> +                       ARRAY_SIZE(exynos3250_cmu_clk_regs));
>>> +    if (!exynos3250_clk_regs) {
>>> +        pr_warn("%s: Failed to allocate sleep save data\n", __func__);
>>> +        goto err;
>>> +    }
>>> +
>>> +    register_syscore_ops(&exynos3250_clk_syscore_ops);
>>> +    return;
>>> +err:
>>> +    kfree(exynos3250_clk_regs);
>>> +}
>>> +#else
>>> +static inline void exynos3250_clk_sleep_init(void) { }
>>> +#endif
>>> +
>>> +/* list of all parent clock list */
>>> +PNAME(mout_vpllsrc_p)        = { "fin_pll", };
>>> +
>>> +PNAME(mout_apll_p)        = { "fin_pll", "fout_apll", };
>>> +PNAME(mout_mpll_p)        = { "fin_pll", "fout_mpll", };
>>> +PNAME(mout_vpll_p)        = { "fin_pll", "fout_vpll", };
>>> +PNAME(mout_upll_p)        = { "fin_pll", "fout_upll", };
>>> +
>>> +PNAME(mout_mpll_user_p)        = { "fin_pll", "div_mpll_pre", };
>>> +PNAME(mout_epll_user_p)        = { "fin_pll", "mout_epll", };
>>> +PNAME(mout_core_p)        = { "mout_apll", "mout_mpll_user_c", };
>>> +PNAME(mout_hpm_p)        = { "mout_apll", "mout_mpll_user_c", };
>>> +
>>> +PNAME(mout_ebi_p)        = { "div_aclk_200", "div_aclk_160", };
>>> +PNAME(mout_ebi_1_p)        = { "mout_ebi", "mout_vpll", };
>>> +
>>> +PNAME(mout_gdl_p)        = { "mout_mpll_user_l", };
>>> +PNAME(mout_gdr_p)        = { "mout_mpll_user_r", };
>>> +
>>> +PNAME(mout_aclk_400_mcuisp_sub_p)
>>> +                = { "fin_pll", "div_aclk_400_mcuisp", };
>>> +PNAME(mout_aclk_266_0_p)    = { "div_mpll_pre", "mout_vpll", };
>>> +PNAME(mout_aclk_266_1_p)    = { "mout_epll_user", };
>>> +PNAME(mout_aclk_266_p)        = { "mout_aclk_266_0", "mout_aclk_266_1", };
>>> +PNAME(mout_aclk_266_sub_p)    = { "fin_pll", "div_aclk_266", };
>>> +
>>> +PNAME(group_div_mpll_pre_p)    = { "div_mpll_pre", };
>>> +PNAME(group_epll_vpll_p)    = { "mout_epll_user", "mout_vpll" };
>>> +PNAME(group_sclk_p)        = { "xxti", "xusbxti",
>>> +                    "none", "none",
>>> +                    "none", "none", "div_mpll_pre",
>>> +                    "mout_epll_user", "mout_vpll", };
>>> +PNAME(group_sclk_audio_p)    = { "audiocdclk", "none",
>>> +                    "none", "none",
>>> +                    "xxti", "xusbxti",
>>> +                    "div_mpll_pre", "mout_epll_user",
>>> +                    "mout_vpll", };
>>> +PNAME(group_sclk_cam_blk_p)    = { "xxti", "xusbxti",
>>> +                    "none", "none", "none",
>>> +                    "none", "div_mpll_pre",
>>> +                    "mout_epll_user", "mout_vpll",
>>> +                    "div_cam_blk_320", };
>>> +PNAME(group_sclk_fimd0_p)    = { "xxti", "xusbxti",
>>> +                    "m_bitclkhsdiv4_2l", "none",
>>> +                    "none", "none", "div_mpll_pre",
>>> +                    "mout_epll_user", "mout_vpll",
>>> +                    "none", "none", "none",
>>> +                    "div_lcd_blk_145", };
>>> +
>>> +PNAME(mout_mfc_p)        = { "mout_mfc_0", "mout_mfc_1" };
>>> +PNAME(mout_g3d_p)        = { "mout_g3d_0", "mout_g3d_1" };
>>> +
>>> +static struct samsung_fixed_rate_clock fixed_rate_clks[] __initdata = {
>>> +};
>>
>> Any reason to have this empty array at all?
> 
> OK, I'll delete empty array.
> 

OK.

>>
>>> +
>>> +static struct samsung_fixed_factor_clock fixed_factor_clks[] __initdata = {
>>> +    FFACTOR(0, "sclk_mpll_1600", "mout_mpll", 1, 1, 0),
>>> +    FFACTOR(0, "sclk_mpll_mif", "mout_mpll", 1, 2, 0),
>>> +    FFACTOR(0, "sclk_bpll", "fout_bpll", 1, 2, 0),
>>> +    FFACTOR(0, "div_cam_blk_320", "sclk_mpll_1600", 1, 5, 0),
>>> +    FFACTOR(0, "div_lcd_blk_145", "sclk_mpll_1600", 1, 11, 0),
>>> +
>>> +    FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0),
>>
>> This is a hack. The real "fin_pll" is a mux driven by XOM pin which selects which clock input is used as main system oscillator. It should be implemented properly in this driver or at least appropriate comment should be added stressing the fact that it is a hack.
> 
> OK, I'll add comment about it and if you ok, I'll send a further patchset to set relation
> between fin_pll and xusbxti/xxti by reading XOM pin of chipid register.
> 

OK.

>>
>>> +};
>>> +
>>> +static struct samsung_mux_clock mux_clks[] __initdata = {
>>> +    /*
>>> +     * NOTE: Following table is sorted by register address in ascending
>>> +     * order and then bitfield shift in descending order, as it is done
>>> +     * in the User's Manual. When adding new entries, please make sure
>>> +     * that the order is preserved, to avoid merge conflicts and make
>>> +     * further work with defined data easier.
>>> +     */
>>> +
>>> +    /* SRC_LEFTBUS */
>>> +    MUX(CLK_MOUT_MPLL_USER_L, "mout_mpll_user_l", mout_mpll_user_p,
>>> +        SRC_LEFTBUS, 4, 1),
>>> +    MUX(CLK_MOUT_GDL, "mout_gdl", mout_gdl_p, SRC_LEFTBUS, 0, 1),
>>> +
>>> +    /* SRC_RIGHTBUS */
>>> +    MUX(CLK_MOUT_MPLL_USER_R, "mout_mpll_user_r", mout_mpll_user_p,
>>> +        SRC_RIGHTBUS, 4, 1),
>>> +    MUX(CLK_MOUT_GDR, "mout_gdr", mout_gdr_p, SRC_RIGHTBUS, 0, 1),
>>> +
>>> +    /* SRC_TOP0 */
>>> +    MUX(CLK_MOUT_EBI, "mout_ebi", mout_ebi_p, SRC_TOP0, 28, 1),
>>> +    MUX(CLK_MOUT_ACLK_200, "mout_aclk_200", group_div_mpll_pre_p,SRC_TOP0, 24, 1),
>>> +    MUX(CLK_MOUT_ACLK_160, "mout_aclk_160", group_div_mpll_pre_p, SRC_TOP0, 20, 1),
>>> +    MUX(CLK_MOUT_ACLK_100, "mout_aclk_100", group_div_mpll_pre_p, SRC_TOP0, 16, 1),
>>> +    MUX(CLK_MOUT_ACLK_266_1, "mout_aclk_266_1", mout_aclk_266_1_p, SRC_TOP0, 14, 1),
>>> +    MUX(CLK_MOUT_ACLK_266_0, "mout_aclk_266_0", mout_aclk_266_0_p, SRC_TOP0, 13, 1),
>>> +    MUX(CLK_MOUT_ACLK_266, "mout_aclk_266", mout_aclk_266_p, SRC_TOP0, 12, 1),
>>> +    MUX(CLK_MOUT_VPLL, "mout_vpll", mout_vpll_p, SRC_TOP0, 8, 1),
>>> +    MUX(CLK_MOUT_EPLL_USER, "mout_epll_user", mout_epll_user_p, SRC_TOP0, 4, 1),
>>> +    MUX(CLK_MOUT_EBI_1, "mout_ebi_1", mout_ebi_1_p, SRC_TOP0, 0, 1),
>>> +
>>> +    /* SRC_TOP1 */
>>> +    MUX(CLK_MOUT_UPLL, "mout_upll", mout_upll_p, SRC_TOP1, 28, 1),
>>> +    MUX(CLK_MOUT_ACLK_400_MCUISP_SUB, "mout_aclk_400_mcuisp_sub", mout_aclk_400_mcuisp_sub_p,
>>> +        SRC_TOP1, 24, 1),
>>> +    MUX(CLK_MOUT_ACLK_266_SUB, "mout_aclk_266_sub", mout_aclk_266_sub_p, SRC_TOP1, 20, 1),
>>> +    MUX(CLK_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_TOP1, 12, 1),
>>> +    MUX(CLK_MOUT_ACLK_400_MCUISP, "mout_aclk_400_mcuisp", group_div_mpll_pre_p, SRC_TOP1, 8, 1),
>>> +    MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
>>> +
>>> +    /* SRC_CAM */
>>> +    MUX(CLK_MOUT_CAM1, "mout_cam1", group_sclk_p, SRC_CAM, 20, 4),
>>> +    MUX(CLK_MOUT_CAM_BLK, "mout_cam_blk", group_sclk_cam_blk_p, SRC_CAM, 0, 4),
>>> +
>>> +    /* SRC_MFC */
>>> +    MUX(CLK_MOUT_MFC, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
>>> +    MUX(CLK_MOUT_MFC_1, "mout_mfc_1", group_epll_vpll_p, SRC_MFC, 4, 1),
>>> +    MUX(CLK_MOUT_MFC_0, "mout_mfc_0", group_div_mpll_pre_p, SRC_MFC, 0, 1),
>>> +
>>> +    /* SRC_G3D */
>>> +    MUX(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1),
>>> +    MUX(CLK_MOUT_G3D_1, "mout_g3d_1", group_epll_vpll_p, SRC_G3D, 4, 1),
>>> +    MUX(CLK_MOUT_G3D_0, "mout_g3d_0", group_div_mpll_pre_p, SRC_G3D, 0, 1),
>>> +
>>> +    /* SRC_LCD */
>>> +    MUX(CLK_MOUT_MIPI0, "mout_mipi0", group_sclk_p, SRC_LCD, 12, 4),
>>> +    MUX(CLK_MOUT_FIMD0, "mout_fimd0", group_sclk_fimd0_p, SRC_LCD, 0, 4),
>>> +
>>> +    /* SRC_ISP */
>>> +    MUX(CLK_MOUT_UART_ISP, "mout_uart_isp", group_sclk_p, SRC_ISP, 12, 4),
>>> +    MUX(CLK_MOUT_SPI1_ISP, "mout_spi1_isp", group_sclk_p, SRC_ISP, 8, 4),
>>> +    MUX(CLK_MOUT_SPI0_ISP, "mout_spi0_isp", group_sclk_p, SRC_ISP, 4, 4),
>>> +
>>> +    /* SRC_FSYS */
>>> +    MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),
>>> +    MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 3),
>>> +    MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 3),
>>> +
>>> +    /* SRC_PERIL0 */
>>> +    MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),
>>> +    MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),
>>> +
>>> +    /* SRC_PERIL1 */
>>> +    MUX(CLK_MOUT_SPI1, "mout_spi1", group_sclk_p, SRC_PERIL1, 20, 4),
>>> +    MUX(CLK_MOUT_SPI0, "mout_spi0", group_sclk_p, SRC_PERIL1, 16, 4),
>>> +    MUX(CLK_MOUT_AUDIO, "mout_audio", group_sclk_audio_p, SRC_PERIL1, 4, 4),
>>> +
>>> +    /* SRC_CPU */
>>> +    MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p,
>>> +        SRC_CPU, 24, 1),
>>> +    MUX(CLK_MOUT_HPM, "mout_hpm", mout_hpm_p, SRC_CPU, 20, 1),
>>> +    MUX(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1),
>>> +    MUX(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
>>> +};
>>> +
>>> +static struct samsung_div_clock div_clks[] __initdata = {
>>> +    /*
>>> +     * NOTE: Following table is sorted by register address in ascending
>>> +     * order and then bitfield shift in descending order, as it is done
>>> +     * in the User's Manual. When adding new entries, please make sure
>>> +     * that the order is preserved, to avoid merge conflicts and make
>>> +     * further work with defined data easier.
>>> +     */
>>> +
>>> +    /* DIV_LEFTBUS */
>>> +    DIV(CLK_DIV_GPL, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
>>> +    DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 4),
>>> +
>>> +    /* DIV_RIGHTBUS */
>>> +    DIV(CLK_DIV_GPR, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
>>> +    DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 4),
>>> +
>>> +    /* DIV_TOP */
>>> +    DIV(CLK_DIV_MPLL_PRE, "div_mpll_pre", "sclk_mpll_mif", DIV_TOP, 28, 2),
>>> +    DIV(CLK_DIV_ACLK_400_MCUISP, "div_aclk_400_mcuisp",
>>> +        "mout_aclk_400_mcuisp", DIV_TOP, 24, 3),
>>> +    DIV(CLK_DIV_EBI, "div_ebi", "mout_ebi_1", DIV_TOP, 16, 3),
>>> +    DIV(CLK_DIV_ACLK_200, "div_aclk_200", "mout_aclk_200", DIV_TOP, 12, 3),
>>> +    DIV(CLK_DIV_ACLK_160, "div_aclk_160", "mout_aclk_160", DIV_TOP, 8, 3),
>>> +    DIV(CLK_DIV_ACLK_100, "div_aclk_100", "mout_aclk_100", DIV_TOP, 4, 4),
>>> +    DIV(CLK_DIV_ACLK_266, "div_aclk_266", "mout_aclk_266", DIV_TOP, 0, 3),
>>> +
>>> +    /* DIV_CAM */
>>> +    DIV(CLK_DIV_CAM1, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
>>> +    DIV(CLK_DIV_CAM_BLK, "div_cam_blk", "mout_cam_blk", DIV_CAM, 0, 4),
>>> +
>>> +    /* DIV_MFC */
>>> +    DIV(CLK_DIV_MFC, "div_mfc", "mout_mfc", DIV_MFC, 0, 4),
>>> +
>>> +    /* DIV_G3D */
>>> +    DIV(CLK_DIV_G3D, "div_g3d", "mout_g3d", DIV_G3D, 0, 4),
>>> +
>>> +    /* DIV_LCD */
>>> +    DIV_F(CLK_DIV_MIPI0_PRE, "div_mipi0_pre", "div_mipi0", DIV_LCD, 20, 4,
>>> +        CLK_SET_RATE_PARENT, 0),
>>> +    DIV(CLK_DIV_MIPI0, "div_mipi0", "mout_mipi0", DIV_LCD, 16, 4),
>>> +    DIV(CLK_DIV_FIMD0, "div_fimd0", "mout_fimd0", DIV_LCD, 0, 4),
>>> +
>>> +    /* DIV_ISP */
>>> +    DIV(CLK_DIV_UART_ISP, "div_uart_isp", "mout_uart_isp", DIV_ISP, 28, 4),
>>> +    DIV_F(CLK_DIV_SPI1_ISP_PRE, "div_spi1_isp_pre", "div_spi1_isp",
>>> +        DIV_ISP, 20, 8, CLK_SET_RATE_PARENT, 0),
>>> +    DIV(CLK_DIV_SPI1_ISP, "div_spi1_isp", "mout_spi1_isp", DIV_ISP, 16, 4),
>>> +    DIV_F(CLK_DIV_SPI0_ISP_PRE, "div_spi0_isp_pre", "div_spi0_isp",
>>> +        DIV_ISP, 8, 8, CLK_SET_RATE_PARENT, 0),
>>> +    DIV(CLK_DIV_SPI0_ISP, "div_spi0_isp", "mout_spi0_isp", DIV_ISP, 0, 4),
>>> +
>>> +    /* DIV_FSYS0 */
>>> +    DIV_F(CLK_DIV_TSADC_PRE, "div_tsadc_pre", "div_tsadc", DIV_FSYS0, 8, 8,
>>> +        CLK_SET_RATE_PARENT, 0),
>>> +    DIV(CLK_DIV_TSADC, "div_tsadc", "mout_tsadc", DIV_FSYS0, 0, 4),
>>> +
>>> +    /* DIV_FSYS1 */
>>> +    DIV_F(CLK_DIV_MMC1_PRE, "div_mmc1_pre", "div_mmc1", DIV_FSYS1, 24, 8,
>>> +        CLK_SET_RATE_PARENT, 0),
>>> +    DIV(CLK_DIV_MMC1, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
>>> +    DIV_F(CLK_DIV_MMC0_PRE, "div_mmc0_pre", "div_mmc0", DIV_FSYS1, 8, 8,
>>> +        CLK_SET_RATE_PARENT, 0),
>>> +    DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
>>> +
>>> +    /* DIV_PERIL0 */
>>> +    DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
>>> +    DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
>>> +
>>> +    /* DIV_PERIL1 */
>>> +    DIV_F(CLK_DIV_SPI1_PRE, "div_spi1_pre", "div_spi1", DIV_PERIL1, 24, 8,
>>> +        CLK_SET_RATE_PARENT, 0),
>>> +    DIV(CLK_DIV_SPI1, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
>>> +    DIV_F(CLK_DIV_SPI0_PRE, "div_spi0_pre", "div_spi0", DIV_PERIL1, 8, 8,
>>> +        CLK_SET_RATE_PARENT, 0),
>>> +    DIV(CLK_DIV_SPI0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
>>> +
>>> +    /* DIV_PERIL4 */
>>> +    DIV(CLK_DIV_PCM, "div_pcm", "div_audio", DIV_PERIL4, 20, 8),
>>> +    DIV(CLK_DIV_AUDIO, "div_audio", "mout_audio", DIV_PERIL4, 16, 4),
>>> +
>>> +    /* DIV_PERIL5 */
>>> +    DIV(CLK_DIV_I2S, "div_i2s", "div_audio", DIV_PERIL5, 8, 6),
>>> +
>>> +    /* DIV_CPU0 */
>>> +    DIV(CLK_DIV_CORE2, "div_core2", "div_core", DIV_CPU0, 28, 3),
>>> +    DIV(CLK_DIV_APLL, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
>>> +    DIV(CLK_DIV_PCLK_DBG, "div_pclk_dbg", "div_core2", DIV_CPU0, 20, 3),
>>> +    DIV(CLK_DIV_ATB, "div_atb", "div_core2", DIV_CPU0, 16, 3),
>>> +    DIV(CLK_DIV_COREM, "div_corem", "div_core2", DIV_CPU0, 4, 3),
>>> +    DIV(CLK_DIV_CORE, "div_core", "mout_core", DIV_CPU0, 0, 3),
>>> +
>>> +    /* DIV_CPU1 */
>>> +    DIV(CLK_DIV_HPM, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
>>> +    DIV(CLK_DIV_COPY, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
>>> +};
>>> +
>>> +static struct samsung_gate_clock gate_clks[] __initdata = {
>>> +    /*
>>> +     * NOTE: Following table is sorted by register address in ascending
>>> +     * order and then bitfield shift in descending order, as it is done
>>> +     * in the User's Manual. When adding new entries, please make sure
>>> +     * that the order is preserved, to avoid merge conflicts and make
>>> +     * further work with defined data easier.
>>> +     */
>>> +
>>> +    /* GATE_IP_LEFTBUS */
>>> +    GATE(CLK_ASYNC_G3D, "async_g3d", "div_aclk_100", GATE_IP_LEFTBUS, 6,
>>> +        CLK_IGNORE_UNUSED, 0),
>>> +    GATE(CLK_ASYNC_MFCL, "async_mfcl", "div_aclk_100", GATE_IP_LEFTBUS, 4,
>>> +        CLK_IGNORE_UNUSED, 0),
>>> +    GATE(CLK_PPMULEFT, "ppmuleft", "div_aclk_100", GATE_IP_LEFTBUS, 1,
>>> +        CLK_IGNORE_UNUSED, 0),
>>> +    GATE(CLK_GPIO_LEFT, "gpio_left", "div_aclk_100", GATE_IP_LEFTBUS, 0,
>>> +        CLK_IGNORE_UNUSED, 0),
>>> +
>>> +    /* GATE_IP_RIGHTBUS */
>>> +    GATE(CLK_ASYNC_ISPMX, "async_ispmx", "div_aclk_100",
>>> +        GATE_IP_RIGHTBUS, 9, CLK_IGNORE_UNUSED, 0),
>>> +    GATE(CLK_ASYNC_FSYSD, "async_fsysd", "div_aclk_100",
>>> +        GATE_IP_RIGHTBUS, 5, CLK_IGNORE_UNUSED, 0),
>>> +    GATE(CLK_ASYNC_LCD0X, "async_lcd0x", "div_aclk_100",
>>> +        GATE_IP_RIGHTBUS, 3, CLK_IGNORE_UNUSED, 0),
>>> +    GATE(CLK_ASYNC_CAMX, "async_camx", "div_aclk_100", GATE_IP_RIGHTBUS, 2,
>>> +        CLK_IGNORE_UNUSED, 0),
>>> +    GATE(CLK_PPMURIGHT, "ppmuright", "div_aclk_100", GATE_IP_RIGHTBUS, 1,
>>> +        CLK_IGNORE_UNUSED, 0),
>>> +    GATE(CLK_GPIO_RIGHT, "gpio_right", "div_aclk_100", GATE_IP_RIGHTBUS, 0,
>>> +        CLK_IGNORE_UNUSED, 0),
>>> +
>>> +    /* GATE_IP_PERIR */
>>> +    GATE(CLK_MONOCNT, "monocnt", "div_aclk_100", GATE_IP_PERIR, 22,
>>> +        CLK_IGNORE_UNUSED, 0),
>>> +    GATE(CLK_TZPC6, "tzpc6", "div_aclk_100", GATE_IP_PERIR, 21,
>>> +        CLK_IGNORE_UNUSED, 0),
>>> +    GATE(CLK_PROVISIONKEY1, "provisionkey1", "div_aclk_100",
>>> +        GATE_IP_PERIR, 20, CLK_IGNORE_UNUSED, 0),
>>> +    GATE(CLK_PROVISIONKEY0, "provisionkey0", "div_aclk_100",
>>> +        GATE_IP_PERIR, 19, CLK_IGNORE_UNUSED, 0),
>>> +    GATE(CLK_CMU_ISPPART, "cmu_isppart", "div_aclk_100", GATE_IP_PERIR, 18,
>>> +        CLK_IGNORE_UNUSED, 0),
>>> +    GATE(CLK_TMU_APBIF, "tmu_apbif", "div_aclk_100",
>>> +        GATE_IP_PERIR, 17, 0, 0),
>>> +    GATE(CLK_KEYIF, "keyif", "div_aclk_100", GATE_IP_PERIR, 16, 0, 0),
>>> +    GATE(CLK_RTC, "rtc", "div_aclk_100", GATE_IP_PERIR, 15, 0, 0),
>>> +    GATE(CLK_WDT, "wdt", "div_aclk_100", GATE_IP_PERIR, 14, 0, 0),
>>> +    GATE(CLK_MCT, "mct", "div_aclk_100", GATE_IP_PERIR, 13, 0, 0),
>>> +    GATE(CLK_SECKEY, "seckey", "div_aclk_100", GATE_IP_PERIR, 12,
>>> +        CLK_IGNORE_UNUSED, 0),
>>> +    GATE(CLK_TZPC5, "tzpc5", "div_aclk_100", GATE_IP_PERIR, 10,
>>> +        CLK_IGNORE_UNUSED, 0),
>>> +    GATE(CLK_TZPC4, "tzpc4", "div_aclk_100", GATE_IP_PERIR, 9,
>>> +        CLK_IGNORE_UNUSED, 0),
>>> +    GATE(CLK_TZPC3, "tzpc3", "div_aclk_100", GATE_IP_PERIR, 8,
>>> +        CLK_IGNORE_UNUSED, 0),
>>> +    GATE(CLK_TZPC2, "tzpc2", "div_aclk_100", GATE_IP_PERIR, 7,
>>> +        CLK_IGNORE_UNUSED, 0),
>>> +    GATE(CLK_TZPC1, "tzpc1", "div_aclk_100", GATE_IP_PERIR, 6,
>>> +        CLK_IGNORE_UNUSED, 0),
>>> +    GATE(CLK_TZPC0, "tzpc0", "div_aclk_100", GATE_IP_PERIR, 5,
>>> +        CLK_IGNORE_UNUSED, 0),
>>> +    GATE(CLK_CMU_COREPART, "cmu_corepart", "div_aclk_100", GATE_IP_PERIR, 4,
>>> +        CLK_IGNORE_UNUSED, 0),
>>> +    GATE(CLK_CMU_TOPPART, "cmu_toppart", "div_aclk_100", GATE_IP_PERIR, 3,
>>> +        CLK_IGNORE_UNUSED, 0),
>>> +    GATE(CLK_PMU_APBIF, "pmu_apbif", "div_aclk_100", GATE_IP_PERIR, 2,
>>> +        CLK_IGNORE_UNUSED, 0),
>>> +    GATE(CLK_SYSREG, "sysreg", "div_aclk_100", GATE_IP_PERIR, 1,
>>> +        CLK_IGNORE_UNUSED, 0),
>>> +    GATE(CLK_CHIP_ID, "chip_id", "div_aclk_100", GATE_IP_PERIR, 0,
>>> +        CLK_IGNORE_UNUSED, 0),
>>> +
>>> +    /* GATE_SCLK_CAM */
>>> +    GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_cam_blk",
>>> +        GATE_SCLK_CAM, 8, CLK_SET_RATE_PARENT, 0),
>>> +    GATE(CLK_SCLK_M2MSCALER, "sclk_m2mscaler", "div_cam_blk",
>>> +        GATE_SCLK_CAM, 2, CLK_SET_RATE_PARENT, 0),
>>> +    GATE(CLK_SCLK_GSCALER1, "sclk_gscaler1", "div_cam_blk",
>>> +        GATE_SCLK_CAM, 1, CLK_SET_RATE_PARENT, 0),
>>> +    GATE(CLK_SCLK_GSCALER0, "sclk_gscaler0", "div_cam_blk",
>>> +        GATE_SCLK_CAM, 0, CLK_SET_RATE_PARENT, 0),
>>> +
>>> +    /* GATE_SCLK_MFC */
>>> +    GATE(CLK_SCLK_MFC, "sclk_mfc", "div_mfc",
>>> +        GATE_SCLK_MFC, 0, CLK_SET_RATE_PARENT, 0),
>>> +
>>> +    /* GATE_SCLK_G3D */
>>> +    GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d",
>>> +        GATE_SCLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
>>> +
>>> +    /* GATE_SCLK_LCD */
>>> +    GATE(CLK_SCLK_MIPIDPHY2L, "sclk_mipidphy2l", "div_mipi0",
>>> +        GATE_SCLK_LCD, 4, CLK_SET_RATE_PARENT, 0),
>>> +    GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi0_pre",
>>> +        GATE_SCLK_LCD, 3, CLK_SET_RATE_PARENT, 0),
>>> +    GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0",
>>> +        GATE_SCLK_LCD, 0, CLK_SET_RATE_PARENT, 0),
>>> +
>>> +    /* GATE_SCLK_ISP_TOP */
>>> +    GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
>>> +        GATE_SCLK_ISP_TOP, 4, CLK_SET_RATE_PARENT, 0),
>>> +    GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "div_uart_isp",
>>> +        GATE_SCLK_ISP_TOP, 3, CLK_SET_RATE_PARENT, 0),
>>> +    GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "div_spi1_isp",
>>> +        GATE_SCLK_ISP_TOP, 2, CLK_SET_RATE_PARENT, 0),
>>> +    GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "div_spi0_isp",
>>> +        GATE_SCLK_ISP_TOP, 1, CLK_SET_RATE_PARENT, 0),
>>> +
>>> +    /* GATE_SCLK_FSYS */
>>> +    GATE(CLK_SCLK_UPLL, "sclk_upll", "mout_upll", GATE_SCLK_FSYS, 10, 0, 0),
>>> +    GATE(CLK_SCLK_TSADC, "sclk_tsadc", "div_tsadc_pre",
>>> +        GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
>>> +    GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",
>>> +        GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),
>>> +    GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre",
>>> +        GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
>>> +    GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",
>>> +        GATE_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
>>> +
>>> +    /* GATE_SCLK_PERIL */
>>> +    GATE(CLK_SCLK_I2S, "sclk_i2s", "div_i2s",
>>> +        GATE_SCLK_PERIL, 18, CLK_SET_RATE_PARENT, 0),
>>> +    GATE(CLK_SCLK_PCM, "sclk_pcm", "div_pcm",
>>> +        GATE_SCLK_PERIL, 16, CLK_SET_RATE_PARENT, 0),
>>> +    GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi1_pre",
>>> +        GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
>>> +    GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
>>> +        GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
>>> +    GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
>>> +        GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
>>> +    GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
>>> +        GATE_SCLK_PERIL, 0, CLK_SET_RATE_PARENT, 0),
>>> +
>>> +    /* GATE_IP_CAM */
>>> +    GATE(CLK_QEJPEG, "qejpeg", "div_cam_blk_320", GATE_IP_CAM, 19,
>>> +        CLK_IGNORE_UNUSED, 0),
>>> +    GATE(CLK_PIXELASYNCM1, "pixelasyncm1", "div_cam_blk_320",
>>> +        GATE_IP_CAM, 18, CLK_IGNORE_UNUSED, 0),
>>> +    GATE(CLK_PIXELASYNCM0, "pixelasyncm0", "div_cam_blk_320",
>>> +        GATE_IP_CAM, 17, CLK_IGNORE_UNUSED, 0),
>>> +    GATE(CLK_PPMUCAMIF, "ppmucamif", "div_cam_blk_320",
>>> +        GATE_IP_CAM, 16, CLK_IGNORE_UNUSED, 0),
>>> +    GATE(CLK_QEM2MSCALER, "qem2mscaler", "div_cam_blk_320",
>>> +        GATE_IP_CAM, 14, CLK_IGNORE_UNUSED, 0),
>>> +    GATE(CLK_QEGSCALER1, "qegscaler1", "div_cam_blk_320",
>>> +        GATE_IP_CAM, 13, CLK_IGNORE_UNUSED, 0),
>>> +    GATE(CLK_QEGSCALER0, "qegscaler0", "div_cam_blk_320",
>>> +        GATE_IP_CAM, 12, CLK_IGNORE_UNUSED, 0),
>>> +    GATE(CLK_SMMUJPEG, "smmujpeg", "div_cam_blk_320",
>>> +        GATE_IP_CAM, 11, 0, 0),
>>> +    GATE(CLK_SMMUM2M2SCALER, "smmum2m2scaler", "div_cam_blk_320",
>>> +        GATE_IP_CAM, 9, 0, 0),
>>> +    GATE(CLK_SMMUGSCALER1, "smmugscaler1", "div_cam_blk_320",
>>> +        GATE_IP_CAM, 8, 0, 0),
>>> +    GATE(CLK_SMMUGSCALER0, "smmugscaler0", "div_cam_blk_320",
>>> +        GATE_IP_CAM, 7, 0, 0),
>>> +    GATE(CLK_JPEG, "jpeg", "div_cam_blk_320", GATE_IP_CAM, 6, 0, 0),
>>> +    GATE(CLK_M2MSCALER, "m2mscaler", "div_cam_blk_320",
>>> +        GATE_IP_CAM, 2, 0, 0),
>>> +    GATE(CLK_GSCALER1, "gscaler1", "div_cam_blk_320", GATE_IP_CAM, 1, 0, 0),
>>> +    GATE(CLK_GSCALER0, "gscaler0", "div_cam_blk_320", GATE_IP_CAM, 0, 0, 0),
>>> +
>>> +    /* GATE_IP_MFC */
>>> +    GATE(CLK_QEMFC, "qemfc", "div_aclk_200", GATE_IP_MFC, 5,
>>> +        CLK_IGNORE_UNUSED, 0),
>>> +    GATE(CLK_PPMUMFC_L, "ppmumfc_l", "div_aclk_200", GATE_IP_MFC, 3,
>>> +        CLK_IGNORE_UNUSED, 0),
>>> +    GATE(CLK_SMMUMFC_L, "smmumfc_l", "div_aclk_200", GATE_IP_MFC, 1, 0, 0),
>>> +    GATE(CLK_MFC, "mfc", "div_aclk_200", GATE_IP_MFC, 0, 0, 0),
>>> +
>>> +    /* GATE_IP_G3D */
>>> +    GATE(CLK_SMMUG3D, "smmug3d", "div_aclk_200", GATE_IP_G3D, 3, 0, 0),
>>> +    GATE(CLK_QEG3D, "qeg3d", "div_aclk_200", GATE_IP_G3D, 2,
>>> +        CLK_IGNORE_UNUSED, 0),
>>> +    GATE(CLK_PPMUG3D, "ppmug3d", "div_aclk_200", GATE_IP_G3D, 1,
>>> +        CLK_IGNORE_UNUSED, 0),
>>> +    GATE(CLK_G3D, "g3d", "div_aclk_200", GATE_IP_G3D, 0, 0, 0),
>>> +
>>> +    /* GATE_IP_LCD */
>>> +    GATE(CLK_QE_CH1_LCD, "qe_ch1_lcd", "div_aclk_160", GATE_IP_LCD, 7,
>>> +        CLK_IGNORE_UNUSED, 0),
>>> +    GATE(CLK_QE_CH0_LCD, "qe_ch0_lcd", "div_aclk_160", GATE_IP_LCD, 6,
>>> +        CLK_IGNORE_UNUSED, 0),
>>> +    GATE(CLK_PPMULCD0, "ppmulcd0", "div_aclk_160", GATE_IP_LCD, 5,
>>> +        CLK_IGNORE_UNUSED, 0),
>>> +    GATE(CLK_SMMUFIMD0, "smmufimd0", "div_aclk_160", GATE_IP_LCD, 4, 0, 0),
>>> +    GATE(CLK_DSIM0, "dsim0", "div_aclk_160", GATE_IP_LCD, 3, 0, 0),
>>> +    GATE(CLK_SMIES, "smies", "div_aclk_160", GATE_IP_LCD, 2, 0, 0),
>>> +    GATE(CLK_FIMD0, "fimd0", "div_aclk_160", GATE_IP_LCD, 0, 0, 0),
>>> +
>>> +    /* GATE_IP_ISP */
>>> +    GATE(CLK_CAM1, "cam1", "mout_aclk_266_sub", GATE_IP_ISP, 5, 0, 0),
>>> +    GATE(CLK_UART_ISP_TOP, "uart_isp_top", "mout_aclk_266_sub",
>>> +        GATE_IP_ISP, 3, 0, 0),
>>> +    GATE(CLK_SPI1_ISP_TOP, "spi1_isp_top", "mout_aclk_266_sub",
>>> +        GATE_IP_ISP, 2, 0, 0),
>>> +    GATE(CLK_SPI0_ISP_TOP, "spi0_isp_top", "mout_aclk_266_sub",
>>> +        GATE_IP_ISP, 1, 0, 0),
>>> +
>>> +    /* GATE_IP_FSYS */
>>> +    GATE(CLK_TSADC, "tsadc", "div_aclk_200", GATE_IP_FSYS, 20, 0, 0),
>>> +    GATE(CLK_PPMUFILE, "ppmufile", "div_aclk_200", GATE_IP_FSYS, 17,
>>> +        CLK_IGNORE_UNUSED, 0),
>>> +    GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0),
>>> +    GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
>>> +    GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
>>> +    GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
>>> +    GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
>>> +    GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
>>> +    GATE(CLK_PDMA0, "pdma0", "div_aclk_200", GATE_IP_FSYS, 0, 0, 0),
>>> +
>>> +    /* GATE_IP_PERIL */
>>> +    GATE(CLK_PWM, "pwm", "div_aclk_100", GATE_IP_PERIL, 24, 0, 0),
>>> +    GATE(CLK_PCM, "pcm", "div_aclk_100", GATE_IP_PERIL, 23, 0, 0),
>>> +    GATE(CLK_I2S, "i2s", "div_aclk_100", GATE_IP_PERIL, 21, 0, 0),
>>> +    GATE(CLK_SPI1, "spi1", "div_aclk_100", GATE_IP_PERIL, 17, 0, 0),
>>> +    GATE(CLK_SPI0, "spi0", "div_aclk_100", GATE_IP_PERIL, 16, 0, 0),
>>> +    GATE(CLK_I2C7, "i2c7", "div_aclk_100", GATE_IP_PERIL, 13, 0, 0),
>>> +    GATE(CLK_I2C6, "i2c6", "div_aclk_100", GATE_IP_PERIL, 12, 0, 0),
>>> +    GATE(CLK_I2C5, "i2c5", "div_aclk_100", GATE_IP_PERIL, 11, 0, 0),
>>> +    GATE(CLK_I2C4, "i2c4", "div_aclk_100", GATE_IP_PERIL, 10, 0, 0),
>>> +    GATE(CLK_I2C3, "i2c3", "div_aclk_100", GATE_IP_PERIL, 9, 0, 0),
>>> +    GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
>>> +    GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
>>> +    GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
>>> +    GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
>>> +    GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
>>> +
>>> +    /* GATE_BLOCK */
>>> +    GATE(CLK_BLOCK_LCD, "block_lcd", "div_aclk_160", GATE_BLOCK, 4, 0, 0),
>>> +    GATE(CLK_BLOCK_G3D, "block_g3d", "div_aclk_200", GATE_BLOCK, 3, 0, 0),
>>
>> Are there only 2 gate block clocks? By the way, how are they going to be handled by respective drivers? There is no mainline support for them right now, but you should be aware that adding them will cause common clock framework to disable them if not claimed by any driver.
> 
> OK, I'll add remaing clock gate of GATE_BLOCK as following.
> - CLK_BLOCK_MFC MFC_BLK
> - CLK_BLOCK_CAM CAM_BLK
> 

I agree that in the end the block gates will have to be added. However
currently drivers do not request block gates and enable them.
Considering that common clock framework disables all unused clocks by
default, this will lead to all the gate block clocks being disabled,
which is not desired.

My opinion on this is that block gate clocks should be added in separate
patch along with patches adding code to get and enable them.

>>
>>> +};
>>> +
>>> +/* APLL & MPLL & BPLL & UPLL */
>>> +static struct samsung_pll_rate_table exynos3250_pll_rates[] = {
>>> +    PLL_35XX_RATE(1200000000, 400, 4, 1),
>>> +    PLL_35XX_RATE(1100000000, 275, 3, 1),
>>> +    PLL_35XX_RATE(1066000000, 533, 6, 1),
>>> +    PLL_35XX_RATE(1000000000, 250, 3, 1),
>>> +    PLL_35XX_RATE( 960000000, 320, 4, 1),
>>> +    PLL_35XX_RATE( 900000000, 300, 4, 1),
>>> +    PLL_35XX_RATE( 850000000, 425, 6, 1),
>>> +    PLL_35XX_RATE( 800000000, 200, 3, 1),
>>> +    PLL_35XX_RATE( 700000000, 175, 3, 1),
>>> +    PLL_35XX_RATE( 667000000, 667, 12, 1),
>>> +    PLL_35XX_RATE( 600000000, 400, 4, 2),
>>> +    PLL_35XX_RATE( 533000000, 533, 6, 2),
>>> +    PLL_35XX_RATE( 520000000, 260, 3, 2),
>>> +    PLL_35XX_RATE( 500000000, 250, 3, 2),
>>> +    PLL_35XX_RATE( 400000000, 200, 3, 2),
>>> +    PLL_35XX_RATE( 200000000, 200, 3, 3),
>>> +    PLL_35XX_RATE( 100000000, 200, 3, 4),
>>> +    { /* sentinel */ }
>>> +};
>>> +
>>> +/* VPLL */
>>> +static struct samsung_pll_rate_table exynos3250_vpll_rates[] = {
>>> +    PLL_36XX_RATE(600000000, 100, 2, 1,     0),
>>> +    PLL_36XX_RATE(533000000, 267, 3, 2, 32668),

The TRM actually lists this as 267, 3, 2, 32768, and according to the
equation it will be 535000015 Hz. Looks like a typo in the data sheet,
as 266, 3, 2, 32768 gives 533000015, which is almost exactly 533 MHz.

>>> +    PLL_36XX_RATE(519231000, 173, 2, 2,  5046),

519230991

>>> +    PLL_36XX_RATE(500000000, 250, 3, 2,     0),
>>> +    PLL_36XX_RATE(445500000, 149, 2, 2, 32768),

448500022

Also looks like a typo in the TRM, as 148, 2, 2, 32768 gives 445500022,
which is almost exactly 445.5 MHz.


>>> +    PLL_36XX_RATE(445055000, 148, 2, 2, 23047),

445055024

>>> +    PLL_36XX_RATE(400000000, 200, 3, 2,     0),
>>> +    PLL_36XX_RATE(371250000, 124, 2, 2, 49512),

The TRM lists this as 124, 2, 2, 49152 and calculated frequency is
374250034. This one also looks like a typo. 123, 2, 2, 49512 would give
371250034.

>>> +    PLL_36XX_RATE(370879000, 185, 3, 2, 28803),

370879011

>>> +    PLL_36XX_RATE(340000000, 170, 3, 2,     0),
>>> +    PLL_36XX_RATE(335000000, 112, 2, 2, 43691),

338000045

111, 2, 2, 43691 would give 335000045. A typo in TRM?

>>> +    PLL_36XX_RATE(333000000, 111, 2, 2,     0),
>>> +    PLL_36XX_RATE(330000000, 110, 2, 2,     0),
>>> +    PLL_36XX_RATE(320000000, 107, 2, 2, 43691),

323000045

106, 2, 2, 43691 would give 320000045.

>>> +    PLL_36XX_RATE(300000000, 100, 2, 2,     0),
>>> +    PLL_36XX_RATE(275000000, 275, 3, 3,     0),
>>> +    PLL_36XX_RATE(222750000, 149, 2, 3, 32768),

224250011

148, 2, 3, 32768 would give 222750011.

>>> +    PLL_36XX_RATE(222528000, 148, 2, 3, 23069),

222528015

>>> +    PLL_36XX_RATE(160000000, 160, 3, 3,     0),
>>> +    PLL_36XX_RATE(148500000,  99, 2, 3,     0),
>>> +    PLL_36XX_RATE(148352000,  99, 2, 3, 59070),

149852025

98, 2, 3, 59070 would give 148352025.

>>> +    PLL_36XX_RATE(108000000, 144, 2, 4,     0),
>>> +    PLL_36XX_RATE( 74250000,  99, 2, 4,     0),
>>> +    PLL_36XX_RATE( 74176000,  99, 3, 4, 59070),

The TRM seems to list this as 99, 2, 4 and calculated frequency will be
74926012, but 98, 2, 4, 59070 would give 74176012.

>>> +    PLL_36XX_RATE( 54054000, 216, 3, 5, 14156),

54054001

>>> +    PLL_36XX_RATE( 54000000, 144, 2, 5,     0),
>>
>> Are all these frequencies above calculated exactly? For correct operation of rate setting code, it is necessary for frequency values specified in these arrays to be exact, not rounded.
> 
> When I implemnted exynos3250_vpll_rates array, I used 'VPLL PMS Value' in Exynos3250 TRM without modification.
> This rate value of exynos3250_vpll_rates is correct.

Well, after checking the values using PLL equation for VPLL, as
specified in TRM and used by clk-pll.c, the values don't match.

Keep in mind that the values must be exact, _not_ rounded, while in the
TRM they are rounded. Moreover it looks like several frequencies in TRM
are off by 1 in M coefficient. Please see above.

Best regards,
Tomasz

Re: [PATCHv4 5/7] clk: samsung: exynos3250: Add clocks using common clock framework

[Chanwoo Choi]

Hi Tomasz,

On 05/14/2014 01:28 AM, Tomasz Figa wrote:
> Hi Chanwoo,
> 
> On 13.05.2014 13:49, Chanwoo Choi wrote:
>> Hi Tomasz,
>>
>> On 04/26/2014 09:39 AM, Tomasz Figa wrote:
>>> Hi Chanwoo,
>>>
>>> On 25.04.2014 03:16, Chanwoo Choi wrote:
>>>> From: Tomasz Figa <t.figa@samsung.com>
>>>>
>>>> This patch add new the clock drvier of Exynos3250 SoC based on Cortex-A7
>>>> using common clock framework. The CMU (Clock Management Unit) of Exynos3250
>>>> control PLLs(Phase Locked Loops) and generate system clocks for CPU, buses,
>>>> and function clocks for individual IPs.
>>>>
>>>> The CMU of Exynos3250 includes following clock doamins:
>>>> - CPU block for Cortex-A7 MPCore processor
>>>> - LEFTBUS/RIGHTBUS block
>>>> - TOP block for G3D/MFC/LCD0/ISP/CAM/FSYS/MFC/PERIL/PERIR
>>>
>>> In original driver present in our internal tree I have separated several CMUs to account for certain factors caused by hardware design, which require such separation. Is there any reason why they were merged together into a single CMU again?
>>
>> This patch just include clocks in CMU clocks without CMU_DMC/CMU_ISP.
>> I'll send a further patches to support CMU_DMC/CMU_ISP after verifying it.
>>
>>>
>>>>
>>>> Cc: Mike Turquette <mturquette@linaro.org>
>>>> Cc: Kukjin Kim <kgene.kim@samsung.com>
>>>> Cc: Rob Herring <robh+dt@kernel.org>
>>>> Cc: Pawel Moll <pawel.moll@arm.com>
>>>> Cc: Mark Rutland <mark.rutland@arm.com>
>>>> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
>>>> Cc: Kumar Gala <galak@codeaurora.org>
>>>> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
>>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>>> Signed-off-by: Hyunhee Kim <hyunhee.kim@samsung.com>
>>>> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
>>>> Signed-off-by: Inki Dae <inki.dae@samsung.com>
>>>> Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
>>>> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
>>>> Signed-off-by: Karol Wrona <k.wrona@samsung.com>
>>>> Signed-off-by: YoungJun Cho <yj44.cho@samsung.com>
>>>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>>>> ---
>>>>   drivers/clk/samsung/Makefile           |   1 +
>>>>   drivers/clk/samsung/clk-exynos3250.c   | 785 +++++++++++++++++++++++++++++++++
>>>>   include/dt-bindings/clock/exynos3250.h | 256 +++++++++++
>>>>   3 files changed, 1042 insertions(+)
>>>>   create mode 100644 drivers/clk/samsung/clk-exynos3250.c
>>>>   create mode 100644 include/dt-bindings/clock/exynos3250.h
>>>>
>>>> diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
>>>> index 8eb4799..d120797 100644
>>>> --- a/drivers/clk/samsung/Makefile
>>>> +++ b/drivers/clk/samsung/Makefile
>>>> @@ -3,6 +3,7 @@
>>>>   #
>>>>
>>>>   obj-$(CONFIG_COMMON_CLK)    += clk.o clk-pll.o
>>>> +obj-$(CONFIG_SOC_EXYNOS3250)    += clk-exynos3250.o
>>>>   obj-$(CONFIG_ARCH_EXYNOS4)    += clk-exynos4.o
>>>>   obj-$(CONFIG_SOC_EXYNOS5250)    += clk-exynos5250.o
>>>>   obj-$(CONFIG_SOC_EXYNOS5420)    += clk-exynos5420.o
>>>> diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
>>>> new file mode 100644
>>>> index 0000000..0574a76
>>>> --- /dev/null
>>>> +++ b/drivers/clk/samsung/clk-exynos3250.c
>>>> @@ -0,0 +1,785 @@
>>>> +/*
>>>> + * Copyright (c) 2014 Samsung Electronics Co., Ltd.
>>>> + *
>>>> + * This program is free software; you can redistribute it and/or modify
>>>> + * it under the terms of the GNU General Public License version 2 as
>>>> + * published by the Free Software Foundation.
>>>> + *
>>>> + * Common Clock Framework support for Exynos3250 SoC.
>>>> + */
>>>> +
>>>> +#include <linux/clk.h>
>>>> +#include <linux/clkdev.h>
>>>> +#include <linux/clk-provider.h>
>>>> +#include <linux/of.h>
>>>> +#include <linux/of_address.h>
>>>> +#include <linux/platform_device.h>
>>>> +#include <linux/syscore_ops.h>
>>>> +
>>>> +#include <dt-bindings/clock/exynos3250.h>
>>>> +
>>>> +#include "clk.h"
>>>> +#include "clk-pll.h"
>>>> +
>>>> +#define SRC_LEFTBUS        0x4200
>>>> +#define DIV_LEFTBUS        0x4500
>>>> +#define GATE_IP_LEFTBUS        0x4800
>>>> +#define SRC_RIGHTBUS        0x8200
>>>> +#define DIV_RIGHTBUS        0x8500
>>>> +#define GATE_IP_RIGHTBUS    0x8800
>>>> +#define GATE_IP_PERIR        0x8960
>>>> +#define MPLL_LOCK        0xc010
>>>> +#define MPLL_CON0        0xc110
>>>> +#define VPLL_LOCK        0xc020
>>>> +#define VPLL_CON0        0xc120
>>>> +#define UPLL_LOCK        0xc030
>>>> +#define UPLL_CON0        0xc130
>>>> +#define SRC_TOP0        0xc210
>>>> +#define SRC_TOP1        0xc214
>>>> +#define SRC_CAM            0xc220
>>>> +#define SRC_MFC            0xc228
>>>> +#define SRC_G3D            0xc22c
>>>> +#define SRC_LCD            0xc234
>>>> +#define SRC_ISP            0xc238
>>>> +#define SRC_FSYS        0xc240
>>>> +#define SRC_PERIL0        0xc250
>>>> +#define SRC_PERIL1        0xc254
>>>> +#define SRC_MASK_TOP        0xc310
>>>> +#define SRC_MASK_CAM        0xc320
>>>> +#define SRC_MASK_LCD        0xc334
>>>> +#define SRC_MASK_ISP        0xc338
>>>> +#define SRC_MASK_FSYS        0xc340
>>>> +#define SRC_MASK_PERIL0        0xc350
>>>> +#define SRC_MASK_PERIL1        0xc354
>>>> +#define DIV_TOP            0xc510
>>>> +#define DIV_CAM            0xc520
>>>> +#define DIV_MFC            0xc528
>>>> +#define DIV_G3D            0xc52c
>>>> +#define DIV_LCD            0xc534
>>>> +#define DIV_ISP            0xc538
>>>> +#define DIV_FSYS0        0xc540
>>>> +#define DIV_FSYS1        0xc544
>>>> +#define DIV_FSYS2        0xc548
>>>> +#define DIV_PERIL0        0xc550
>>>> +#define DIV_PERIL1        0xc554
>>>> +#define DIV_PERIL3        0xc55c
>>>> +#define DIV_PERIL4        0xc560
>>>> +#define DIV_PERIL5        0xc564
>>>> +#define DIV_CAM1        0xc568
>>>> +#define CLKDIV2_RATIO        0xc580
>>>> +#define GATE_SCLK_CAM        0xc820
>>>> +#define GATE_SCLK_MFC        0xc828
>>>> +#define GATE_SCLK_G3D        0xc82c
>>>> +#define GATE_SCLK_LCD        0xc834
>>>> +#define GATE_SCLK_ISP_TOP    0xc838
>>>> +#define GATE_SCLK_FSYS        0xc840
>>>> +#define GATE_SCLK_PERIL        0xc850
>>>> +#define GATE_IP_CAM        0xc920
>>>> +#define GATE_IP_MFC        0xc928
>>>> +#define GATE_IP_G3D        0xc92c
>>>> +#define GATE_IP_LCD        0xc934
>>>> +#define GATE_IP_ISP        0xc938
>>>> +#define GATE_IP_FSYS        0xc940
>>>> +#define GATE_IP_PERIL        0xc950
>>>> +#define GATE_BLOCK        0xc970
>>>> +#define APLL_LOCK        0x14000
>>>> +#define APLL_CON0        0x14100
>>>> +#define SRC_CPU            0x14200
>>>> +#define DIV_CPU0        0x14500
>>>> +#define DIV_CPU1        0x14504
>>>> +
>>>> +/* list of PLLs to be registered */
>>>> +enum exynos3250_plls {
>>>> +    apll, mpll, vpll, upll,
>>>> +    nr_plls
>>>> +};
>>>> +
>>>> +void __iomem *reg_base;
>>>
>>> static void
>>
>> I'll fix it.
>>
> 
> OK.
> 
>>>
>>>> +
>>>> +/*
>>>> + * Support for CMU save/restore across system suspends
>>>> + */
>>>> +#ifdef CONFIG_PM_SLEEP
>>>> +static struct samsung_clk_reg_dump *exynos3250_clk_regs;
>>>> +
>>>> +static unsigned long exynos3250_cmu_clk_regs[] __initdata = {
>>>> +    SRC_LEFTBUS,
>>>> +    DIV_LEFTBUS,
>>>> +    GATE_IP_LEFTBUS,
>>>> +    SRC_RIGHTBUS,
>>>> +    DIV_RIGHTBUS,
>>>> +    GATE_IP_RIGHTBUS,
>>>> +    GATE_IP_PERIR,
>>>> +    MPLL_LOCK,
>>>> +    MPLL_CON0,
>>>> +    VPLL_LOCK,
>>>> +    VPLL_CON0,
>>>> +    UPLL_LOCK,
>>>> +    UPLL_CON0,
>>>> +    SRC_TOP0,
>>>> +    SRC_TOP1,
>>>> +    SRC_CAM,
>>>> +    SRC_MFC,
>>>> +    SRC_G3D,
>>>> +    SRC_LCD,
>>>> +    SRC_ISP,
>>>> +    SRC_FSYS,
>>>> +    SRC_PERIL0,
>>>> +    SRC_PERIL1,
>>>> +    SRC_MASK_TOP,
>>>> +    SRC_MASK_CAM,
>>>> +    SRC_MASK_LCD,
>>>> +    SRC_MASK_ISP,
>>>> +    SRC_MASK_FSYS,
>>>> +    SRC_MASK_PERIL0,
>>>> +    SRC_MASK_PERIL1,
>>>> +    DIV_TOP,
>>>> +    DIV_CAM,
>>>> +    DIV_MFC,
>>>> +    DIV_G3D,
>>>> +    DIV_LCD,
>>>> +    DIV_ISP,
>>>> +    DIV_FSYS0,
>>>> +    DIV_FSYS1,
>>>> +    DIV_FSYS2,
>>>> +    DIV_PERIL0,
>>>> +    DIV_PERIL1,
>>>> +    DIV_PERIL3,
>>>> +    DIV_PERIL4,
>>>> +    DIV_PERIL5,
>>>> +    DIV_CAM1,
>>>> +    CLKDIV2_RATIO,
>>>> +    GATE_SCLK_CAM,
>>>> +    GATE_SCLK_MFC,
>>>> +    GATE_SCLK_G3D,
>>>> +    GATE_SCLK_LCD,
>>>> +    GATE_SCLK_ISP_TOP,
>>>> +    GATE_SCLK_FSYS,
>>>> +    GATE_SCLK_PERIL,
>>>> +    GATE_IP_CAM,
>>>> +    GATE_IP_MFC,
>>>> +    GATE_IP_G3D,
>>>> +    GATE_IP_LCD,
>>>> +    GATE_IP_ISP,
>>>> +    GATE_IP_FSYS,
>>>> +    GATE_IP_PERIL,
>>>> +    GATE_BLOCK,
>>>> +    APLL_LOCK,
>>>> +    SRC_CPU,
>>>> +    DIV_CPU0,
>>>> +    DIV_CPU1,
>>>> +};
>>>> +
>>>> +static int exynos3250_clk_suspend(void)
>>>> +{
>>>> +    samsung_clk_save(reg_base, exynos3250_clk_regs,
>>>> +                ARRAY_SIZE(exynos3250_cmu_clk_regs));
>>>> +    return 0;
>>>> +}
>>>> +
>>>> +static void exynos3250_clk_resume(void)
>>>> +{
>>>> +    samsung_clk_restore(reg_base, exynos3250_clk_regs,
>>>> +                ARRAY_SIZE(exynos3250_cmu_clk_regs));
>>>> +}
>>>> +
>>>> +static struct syscore_ops exynos3250_clk_syscore_ops = {
>>>> +    .suspend = exynos3250_clk_suspend,
>>>> +    .resume = exynos3250_clk_resume,
>>>> +};
>>>> +
>>>> +static void exynos3250_clk_sleep_init(void)
>>>> +{
>>>> +    exynos3250_clk_regs =
>>>> +        samsung_clk_alloc_reg_dump(exynos3250_cmu_clk_regs,
>>>> +                       ARRAY_SIZE(exynos3250_cmu_clk_regs));
>>>> +    if (!exynos3250_clk_regs) {
>>>> +        pr_warn("%s: Failed to allocate sleep save data\n", __func__);
>>>> +        goto err;
>>>> +    }
>>>> +
>>>> +    register_syscore_ops(&exynos3250_clk_syscore_ops);
>>>> +    return;
>>>> +err:
>>>> +    kfree(exynos3250_clk_regs);
>>>> +}
>>>> +#else
>>>> +static inline void exynos3250_clk_sleep_init(void) { }
>>>> +#endif
>>>> +
>>>> +/* list of all parent clock list */
>>>> +PNAME(mout_vpllsrc_p)        = { "fin_pll", };
>>>> +
>>>> +PNAME(mout_apll_p)        = { "fin_pll", "fout_apll", };
>>>> +PNAME(mout_mpll_p)        = { "fin_pll", "fout_mpll", };
>>>> +PNAME(mout_vpll_p)        = { "fin_pll", "fout_vpll", };
>>>> +PNAME(mout_upll_p)        = { "fin_pll", "fout_upll", };
>>>> +
>>>> +PNAME(mout_mpll_user_p)        = { "fin_pll", "div_mpll_pre", };
>>>> +PNAME(mout_epll_user_p)        = { "fin_pll", "mout_epll", };
>>>> +PNAME(mout_core_p)        = { "mout_apll", "mout_mpll_user_c", };
>>>> +PNAME(mout_hpm_p)        = { "mout_apll", "mout_mpll_user_c", };
>>>> +
>>>> +PNAME(mout_ebi_p)        = { "div_aclk_200", "div_aclk_160", };
>>>> +PNAME(mout_ebi_1_p)        = { "mout_ebi", "mout_vpll", };
>>>> +
>>>> +PNAME(mout_gdl_p)        = { "mout_mpll_user_l", };
>>>> +PNAME(mout_gdr_p)        = { "mout_mpll_user_r", };
>>>> +
>>>> +PNAME(mout_aclk_400_mcuisp_sub_p)
>>>> +                = { "fin_pll", "div_aclk_400_mcuisp", };
>>>> +PNAME(mout_aclk_266_0_p)    = { "div_mpll_pre", "mout_vpll", };
>>>> +PNAME(mout_aclk_266_1_p)    = { "mout_epll_user", };
>>>> +PNAME(mout_aclk_266_p)        = { "mout_aclk_266_0", "mout_aclk_266_1", };
>>>> +PNAME(mout_aclk_266_sub_p)    = { "fin_pll", "div_aclk_266", };
>>>> +
>>>> +PNAME(group_div_mpll_pre_p)    = { "div_mpll_pre", };
>>>> +PNAME(group_epll_vpll_p)    = { "mout_epll_user", "mout_vpll" };
>>>> +PNAME(group_sclk_p)        = { "xxti", "xusbxti",
>>>> +                    "none", "none",
>>>> +                    "none", "none", "div_mpll_pre",
>>>> +                    "mout_epll_user", "mout_vpll", };
>>>> +PNAME(group_sclk_audio_p)    = { "audiocdclk", "none",
>>>> +                    "none", "none",
>>>> +                    "xxti", "xusbxti",
>>>> +                    "div_mpll_pre", "mout_epll_user",
>>>> +                    "mout_vpll", };
>>>> +PNAME(group_sclk_cam_blk_p)    = { "xxti", "xusbxti",
>>>> +                    "none", "none", "none",
>>>> +                    "none", "div_mpll_pre",
>>>> +                    "mout_epll_user", "mout_vpll",
>>>> +                    "div_cam_blk_320", };
>>>> +PNAME(group_sclk_fimd0_p)    = { "xxti", "xusbxti",
>>>> +                    "m_bitclkhsdiv4_2l", "none",
>>>> +                    "none", "none", "div_mpll_pre",
>>>> +                    "mout_epll_user", "mout_vpll",
>>>> +                    "none", "none", "none",
>>>> +                    "div_lcd_blk_145", };
>>>> +
>>>> +PNAME(mout_mfc_p)        = { "mout_mfc_0", "mout_mfc_1" };
>>>> +PNAME(mout_g3d_p)        = { "mout_g3d_0", "mout_g3d_1" };
>>>> +
>>>> +static struct samsung_fixed_rate_clock fixed_rate_clks[] __initdata = {
>>>> +};
>>>
>>> Any reason to have this empty array at all?
>>
>> OK, I'll delete empty array.
>>
> 
> OK.
> 
>>>
>>>> +
>>>> +static struct samsung_fixed_factor_clock fixed_factor_clks[] __initdata = {
>>>> +    FFACTOR(0, "sclk_mpll_1600", "mout_mpll", 1, 1, 0),
>>>> +    FFACTOR(0, "sclk_mpll_mif", "mout_mpll", 1, 2, 0),
>>>> +    FFACTOR(0, "sclk_bpll", "fout_bpll", 1, 2, 0),
>>>> +    FFACTOR(0, "div_cam_blk_320", "sclk_mpll_1600", 1, 5, 0),
>>>> +    FFACTOR(0, "div_lcd_blk_145", "sclk_mpll_1600", 1, 11, 0),
>>>> +
>>>> +    FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0),
>>>
>>> This is a hack. The real "fin_pll" is a mux driven by XOM pin which selects which clock input is used as main system oscillator. It should be implemented properly in this driver or at least appropriate comment should be added stressing the fact that it is a hack.
>>
>> OK, I'll add comment about it and if you ok, I'll send a further patchset to set relation
>> between fin_pll and xusbxti/xxti by reading XOM pin of chipid register.
>>
> 
> OK.
> 
>>>
>>>> +};
>>>> +
>>>> +static struct samsung_mux_clock mux_clks[] __initdata = {
>>>> +    /*
>>>> +     * NOTE: Following table is sorted by register address in ascending
>>>> +     * order and then bitfield shift in descending order, as it is done
>>>> +     * in the User's Manual. When adding new entries, please make sure
>>>> +     * that the order is preserved, to avoid merge conflicts and make
>>>> +     * further work with defined data easier.
>>>> +     */
>>>> +
>>>> +    /* SRC_LEFTBUS */
>>>> +    MUX(CLK_MOUT_MPLL_USER_L, "mout_mpll_user_l", mout_mpll_user_p,
>>>> +        SRC_LEFTBUS, 4, 1),
>>>> +    MUX(CLK_MOUT_GDL, "mout_gdl", mout_gdl_p, SRC_LEFTBUS, 0, 1),
>>>> +
>>>> +    /* SRC_RIGHTBUS */
>>>> +    MUX(CLK_MOUT_MPLL_USER_R, "mout_mpll_user_r", mout_mpll_user_p,
>>>> +        SRC_RIGHTBUS, 4, 1),
>>>> +    MUX(CLK_MOUT_GDR, "mout_gdr", mout_gdr_p, SRC_RIGHTBUS, 0, 1),
>>>> +
>>>> +    /* SRC_TOP0 */
>>>> +    MUX(CLK_MOUT_EBI, "mout_ebi", mout_ebi_p, SRC_TOP0, 28, 1),
>>>> +    MUX(CLK_MOUT_ACLK_200, "mout_aclk_200", group_div_mpll_pre_p,SRC_TOP0, 24, 1),
>>>> +    MUX(CLK_MOUT_ACLK_160, "mout_aclk_160", group_div_mpll_pre_p, SRC_TOP0, 20, 1),
>>>> +    MUX(CLK_MOUT_ACLK_100, "mout_aclk_100", group_div_mpll_pre_p, SRC_TOP0, 16, 1),
>>>> +    MUX(CLK_MOUT_ACLK_266_1, "mout_aclk_266_1", mout_aclk_266_1_p, SRC_TOP0, 14, 1),
>>>> +    MUX(CLK_MOUT_ACLK_266_0, "mout_aclk_266_0", mout_aclk_266_0_p, SRC_TOP0, 13, 1),
>>>> +    MUX(CLK_MOUT_ACLK_266, "mout_aclk_266", mout_aclk_266_p, SRC_TOP0, 12, 1),
>>>> +    MUX(CLK_MOUT_VPLL, "mout_vpll", mout_vpll_p, SRC_TOP0, 8, 1),
>>>> +    MUX(CLK_MOUT_EPLL_USER, "mout_epll_user", mout_epll_user_p, SRC_TOP0, 4, 1),
>>>> +    MUX(CLK_MOUT_EBI_1, "mout_ebi_1", mout_ebi_1_p, SRC_TOP0, 0, 1),
>>>> +
>>>> +    /* SRC_TOP1 */
>>>> +    MUX(CLK_MOUT_UPLL, "mout_upll", mout_upll_p, SRC_TOP1, 28, 1),
>>>> +    MUX(CLK_MOUT_ACLK_400_MCUISP_SUB, "mout_aclk_400_mcuisp_sub", mout_aclk_400_mcuisp_sub_p,
>>>> +        SRC_TOP1, 24, 1),
>>>> +    MUX(CLK_MOUT_ACLK_266_SUB, "mout_aclk_266_sub", mout_aclk_266_sub_p, SRC_TOP1, 20, 1),
>>>> +    MUX(CLK_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_TOP1, 12, 1),
>>>> +    MUX(CLK_MOUT_ACLK_400_MCUISP, "mout_aclk_400_mcuisp", group_div_mpll_pre_p, SRC_TOP1, 8, 1),
>>>> +    MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
>>>> +
>>>> +    /* SRC_CAM */
>>>> +    MUX(CLK_MOUT_CAM1, "mout_cam1", group_sclk_p, SRC_CAM, 20, 4),
>>>> +    MUX(CLK_MOUT_CAM_BLK, "mout_cam_blk", group_sclk_cam_blk_p, SRC_CAM, 0, 4),
>>>> +
>>>> +    /* SRC_MFC */
>>>> +    MUX(CLK_MOUT_MFC, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
>>>> +    MUX(CLK_MOUT_MFC_1, "mout_mfc_1", group_epll_vpll_p, SRC_MFC, 4, 1),
>>>> +    MUX(CLK_MOUT_MFC_0, "mout_mfc_0", group_div_mpll_pre_p, SRC_MFC, 0, 1),
>>>> +
>>>> +    /* SRC_G3D */
>>>> +    MUX(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1),
>>>> +    MUX(CLK_MOUT_G3D_1, "mout_g3d_1", group_epll_vpll_p, SRC_G3D, 4, 1),
>>>> +    MUX(CLK_MOUT_G3D_0, "mout_g3d_0", group_div_mpll_pre_p, SRC_G3D, 0, 1),
>>>> +
>>>> +    /* SRC_LCD */
>>>> +    MUX(CLK_MOUT_MIPI0, "mout_mipi0", group_sclk_p, SRC_LCD, 12, 4),
>>>> +    MUX(CLK_MOUT_FIMD0, "mout_fimd0", group_sclk_fimd0_p, SRC_LCD, 0, 4),
>>>> +
>>>> +    /* SRC_ISP */
>>>> +    MUX(CLK_MOUT_UART_ISP, "mout_uart_isp", group_sclk_p, SRC_ISP, 12, 4),
>>>> +    MUX(CLK_MOUT_SPI1_ISP, "mout_spi1_isp", group_sclk_p, SRC_ISP, 8, 4),
>>>> +    MUX(CLK_MOUT_SPI0_ISP, "mout_spi0_isp", group_sclk_p, SRC_ISP, 4, 4),
>>>> +
>>>> +    /* SRC_FSYS */
>>>> +    MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),
>>>> +    MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 3),
>>>> +    MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 3),
>>>> +
>>>> +    /* SRC_PERIL0 */
>>>> +    MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),
>>>> +    MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),
>>>> +
>>>> +    /* SRC_PERIL1 */
>>>> +    MUX(CLK_MOUT_SPI1, "mout_spi1", group_sclk_p, SRC_PERIL1, 20, 4),
>>>> +    MUX(CLK_MOUT_SPI0, "mout_spi0", group_sclk_p, SRC_PERIL1, 16, 4),
>>>> +    MUX(CLK_MOUT_AUDIO, "mout_audio", group_sclk_audio_p, SRC_PERIL1, 4, 4),
>>>> +
>>>> +    /* SRC_CPU */
>>>> +    MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p,
>>>> +        SRC_CPU, 24, 1),
>>>> +    MUX(CLK_MOUT_HPM, "mout_hpm", mout_hpm_p, SRC_CPU, 20, 1),
>>>> +    MUX(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1),
>>>> +    MUX(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
>>>> +};
>>>> +
>>>> +static struct samsung_div_clock div_clks[] __initdata = {
>>>> +    /*
>>>> +     * NOTE: Following table is sorted by register address in ascending
>>>> +     * order and then bitfield shift in descending order, as it is done
>>>> +     * in the User's Manual. When adding new entries, please make sure
>>>> +     * that the order is preserved, to avoid merge conflicts and make
>>>> +     * further work with defined data easier.
>>>> +     */
>>>> +
>>>> +    /* DIV_LEFTBUS */
>>>> +    DIV(CLK_DIV_GPL, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
>>>> +    DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 4),
>>>> +
>>>> +    /* DIV_RIGHTBUS */
>>>> +    DIV(CLK_DIV_GPR, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
>>>> +    DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 4),
>>>> +
>>>> +    /* DIV_TOP */
>>>> +    DIV(CLK_DIV_MPLL_PRE, "div_mpll_pre", "sclk_mpll_mif", DIV_TOP, 28, 2),
>>>> +    DIV(CLK_DIV_ACLK_400_MCUISP, "div_aclk_400_mcuisp",
>>>> +        "mout_aclk_400_mcuisp", DIV_TOP, 24, 3),
>>>> +    DIV(CLK_DIV_EBI, "div_ebi", "mout_ebi_1", DIV_TOP, 16, 3),
>>>> +    DIV(CLK_DIV_ACLK_200, "div_aclk_200", "mout_aclk_200", DIV_TOP, 12, 3),
>>>> +    DIV(CLK_DIV_ACLK_160, "div_aclk_160", "mout_aclk_160", DIV_TOP, 8, 3),
>>>> +    DIV(CLK_DIV_ACLK_100, "div_aclk_100", "mout_aclk_100", DIV_TOP, 4, 4),
>>>> +    DIV(CLK_DIV_ACLK_266, "div_aclk_266", "mout_aclk_266", DIV_TOP, 0, 3),
>>>> +
>>>> +    /* DIV_CAM */
>>>> +    DIV(CLK_DIV_CAM1, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
>>>> +    DIV(CLK_DIV_CAM_BLK, "div_cam_blk", "mout_cam_blk", DIV_CAM, 0, 4),
>>>> +
>>>> +    /* DIV_MFC */
>>>> +    DIV(CLK_DIV_MFC, "div_mfc", "mout_mfc", DIV_MFC, 0, 4),
>>>> +
>>>> +    /* DIV_G3D */
>>>> +    DIV(CLK_DIV_G3D, "div_g3d", "mout_g3d", DIV_G3D, 0, 4),
>>>> +
>>>> +    /* DIV_LCD */
>>>> +    DIV_F(CLK_DIV_MIPI0_PRE, "div_mipi0_pre", "div_mipi0", DIV_LCD, 20, 4,
>>>> +        CLK_SET_RATE_PARENT, 0),
>>>> +    DIV(CLK_DIV_MIPI0, "div_mipi0", "mout_mipi0", DIV_LCD, 16, 4),
>>>> +    DIV(CLK_DIV_FIMD0, "div_fimd0", "mout_fimd0", DIV_LCD, 0, 4),
>>>> +
>>>> +    /* DIV_ISP */
>>>> +    DIV(CLK_DIV_UART_ISP, "div_uart_isp", "mout_uart_isp", DIV_ISP, 28, 4),
>>>> +    DIV_F(CLK_DIV_SPI1_ISP_PRE, "div_spi1_isp_pre", "div_spi1_isp",
>>>> +        DIV_ISP, 20, 8, CLK_SET_RATE_PARENT, 0),
>>>> +    DIV(CLK_DIV_SPI1_ISP, "div_spi1_isp", "mout_spi1_isp", DIV_ISP, 16, 4),
>>>> +    DIV_F(CLK_DIV_SPI0_ISP_PRE, "div_spi0_isp_pre", "div_spi0_isp",
>>>> +        DIV_ISP, 8, 8, CLK_SET_RATE_PARENT, 0),
>>>> +    DIV(CLK_DIV_SPI0_ISP, "div_spi0_isp", "mout_spi0_isp", DIV_ISP, 0, 4),
>>>> +
>>>> +    /* DIV_FSYS0 */
>>>> +    DIV_F(CLK_DIV_TSADC_PRE, "div_tsadc_pre", "div_tsadc", DIV_FSYS0, 8, 8,
>>>> +        CLK_SET_RATE_PARENT, 0),
>>>> +    DIV(CLK_DIV_TSADC, "div_tsadc", "mout_tsadc", DIV_FSYS0, 0, 4),
>>>> +
>>>> +    /* DIV_FSYS1 */
>>>> +    DIV_F(CLK_DIV_MMC1_PRE, "div_mmc1_pre", "div_mmc1", DIV_FSYS1, 24, 8,
>>>> +        CLK_SET_RATE_PARENT, 0),
>>>> +    DIV(CLK_DIV_MMC1, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
>>>> +    DIV_F(CLK_DIV_MMC0_PRE, "div_mmc0_pre", "div_mmc0", DIV_FSYS1, 8, 8,
>>>> +        CLK_SET_RATE_PARENT, 0),
>>>> +    DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
>>>> +
>>>> +    /* DIV_PERIL0 */
>>>> +    DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
>>>> +    DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
>>>> +
>>>> +    /* DIV_PERIL1 */
>>>> +    DIV_F(CLK_DIV_SPI1_PRE, "div_spi1_pre", "div_spi1", DIV_PERIL1, 24, 8,
>>>> +        CLK_SET_RATE_PARENT, 0),
>>>> +    DIV(CLK_DIV_SPI1, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
>>>> +    DIV_F(CLK_DIV_SPI0_PRE, "div_spi0_pre", "div_spi0", DIV_PERIL1, 8, 8,
>>>> +        CLK_SET_RATE_PARENT, 0),
>>>> +    DIV(CLK_DIV_SPI0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
>>>> +
>>>> +    /* DIV_PERIL4 */
>>>> +    DIV(CLK_DIV_PCM, "div_pcm", "div_audio", DIV_PERIL4, 20, 8),
>>>> +    DIV(CLK_DIV_AUDIO, "div_audio", "mout_audio", DIV_PERIL4, 16, 4),
>>>> +
>>>> +    /* DIV_PERIL5 */
>>>> +    DIV(CLK_DIV_I2S, "div_i2s", "div_audio", DIV_PERIL5, 8, 6),
>>>> +
>>>> +    /* DIV_CPU0 */
>>>> +    DIV(CLK_DIV_CORE2, "div_core2", "div_core", DIV_CPU0, 28, 3),
>>>> +    DIV(CLK_DIV_APLL, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
>>>> +    DIV(CLK_DIV_PCLK_DBG, "div_pclk_dbg", "div_core2", DIV_CPU0, 20, 3),
>>>> +    DIV(CLK_DIV_ATB, "div_atb", "div_core2", DIV_CPU0, 16, 3),
>>>> +    DIV(CLK_DIV_COREM, "div_corem", "div_core2", DIV_CPU0, 4, 3),
>>>> +    DIV(CLK_DIV_CORE, "div_core", "mout_core", DIV_CPU0, 0, 3),
>>>> +
>>>> +    /* DIV_CPU1 */
>>>> +    DIV(CLK_DIV_HPM, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
>>>> +    DIV(CLK_DIV_COPY, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
>>>> +};
>>>> +
>>>> +static struct samsung_gate_clock gate_clks[] __initdata = {
>>>> +    /*
>>>> +     * NOTE: Following table is sorted by register address in ascending
>>>> +     * order and then bitfield shift in descending order, as it is done
>>>> +     * in the User's Manual. When adding new entries, please make sure
>>>> +     * that the order is preserved, to avoid merge conflicts and make
>>>> +     * further work with defined data easier.
>>>> +     */
>>>> +
>>>> +    /* GATE_IP_LEFTBUS */
>>>> +    GATE(CLK_ASYNC_G3D, "async_g3d", "div_aclk_100", GATE_IP_LEFTBUS, 6,
>>>> +        CLK_IGNORE_UNUSED, 0),
>>>> +    GATE(CLK_ASYNC_MFCL, "async_mfcl", "div_aclk_100", GATE_IP_LEFTBUS, 4,
>>>> +        CLK_IGNORE_UNUSED, 0),
>>>> +    GATE(CLK_PPMULEFT, "ppmuleft", "div_aclk_100", GATE_IP_LEFTBUS, 1,
>>>> +        CLK_IGNORE_UNUSED, 0),
>>>> +    GATE(CLK_GPIO_LEFT, "gpio_left", "div_aclk_100", GATE_IP_LEFTBUS, 0,
>>>> +        CLK_IGNORE_UNUSED, 0),
>>>> +
>>>> +    /* GATE_IP_RIGHTBUS */
>>>> +    GATE(CLK_ASYNC_ISPMX, "async_ispmx", "div_aclk_100",
>>>> +        GATE_IP_RIGHTBUS, 9, CLK_IGNORE_UNUSED, 0),
>>>> +    GATE(CLK_ASYNC_FSYSD, "async_fsysd", "div_aclk_100",
>>>> +        GATE_IP_RIGHTBUS, 5, CLK_IGNORE_UNUSED, 0),
>>>> +    GATE(CLK_ASYNC_LCD0X, "async_lcd0x", "div_aclk_100",
>>>> +        GATE_IP_RIGHTBUS, 3, CLK_IGNORE_UNUSED, 0),
>>>> +    GATE(CLK_ASYNC_CAMX, "async_camx", "div_aclk_100", GATE_IP_RIGHTBUS, 2,
>>>> +        CLK_IGNORE_UNUSED, 0),
>>>> +    GATE(CLK_PPMURIGHT, "ppmuright", "div_aclk_100", GATE_IP_RIGHTBUS, 1,
>>>> +        CLK_IGNORE_UNUSED, 0),
>>>> +    GATE(CLK_GPIO_RIGHT, "gpio_right", "div_aclk_100", GATE_IP_RIGHTBUS, 0,
>>>> +        CLK_IGNORE_UNUSED, 0),
>>>> +
>>>> +    /* GATE_IP_PERIR */
>>>> +    GATE(CLK_MONOCNT, "monocnt", "div_aclk_100", GATE_IP_PERIR, 22,
>>>> +        CLK_IGNORE_UNUSED, 0),
>>>> +    GATE(CLK_TZPC6, "tzpc6", "div_aclk_100", GATE_IP_PERIR, 21,
>>>> +        CLK_IGNORE_UNUSED, 0),
>>>> +    GATE(CLK_PROVISIONKEY1, "provisionkey1", "div_aclk_100",
>>>> +        GATE_IP_PERIR, 20, CLK_IGNORE_UNUSED, 0),
>>>> +    GATE(CLK_PROVISIONKEY0, "provisionkey0", "div_aclk_100",
>>>> +        GATE_IP_PERIR, 19, CLK_IGNORE_UNUSED, 0),
>>>> +    GATE(CLK_CMU_ISPPART, "cmu_isppart", "div_aclk_100", GATE_IP_PERIR, 18,
>>>> +        CLK_IGNORE_UNUSED, 0),
>>>> +    GATE(CLK_TMU_APBIF, "tmu_apbif", "div_aclk_100",
>>>> +        GATE_IP_PERIR, 17, 0, 0),
>>>> +    GATE(CLK_KEYIF, "keyif", "div_aclk_100", GATE_IP_PERIR, 16, 0, 0),
>>>> +    GATE(CLK_RTC, "rtc", "div_aclk_100", GATE_IP_PERIR, 15, 0, 0),
>>>> +    GATE(CLK_WDT, "wdt", "div_aclk_100", GATE_IP_PERIR, 14, 0, 0),
>>>> +    GATE(CLK_MCT, "mct", "div_aclk_100", GATE_IP_PERIR, 13, 0, 0),
>>>> +    GATE(CLK_SECKEY, "seckey", "div_aclk_100", GATE_IP_PERIR, 12,
>>>> +        CLK_IGNORE_UNUSED, 0),
>>>> +    GATE(CLK_TZPC5, "tzpc5", "div_aclk_100", GATE_IP_PERIR, 10,
>>>> +        CLK_IGNORE_UNUSED, 0),
>>>> +    GATE(CLK_TZPC4, "tzpc4", "div_aclk_100", GATE_IP_PERIR, 9,
>>>> +        CLK_IGNORE_UNUSED, 0),
>>>> +    GATE(CLK_TZPC3, "tzpc3", "div_aclk_100", GATE_IP_PERIR, 8,
>>>> +        CLK_IGNORE_UNUSED, 0),
>>>> +    GATE(CLK_TZPC2, "tzpc2", "div_aclk_100", GATE_IP_PERIR, 7,
>>>> +        CLK_IGNORE_UNUSED, 0),
>>>> +    GATE(CLK_TZPC1, "tzpc1", "div_aclk_100", GATE_IP_PERIR, 6,
>>>> +        CLK_IGNORE_UNUSED, 0),
>>>> +    GATE(CLK_TZPC0, "tzpc0", "div_aclk_100", GATE_IP_PERIR, 5,
>>>> +        CLK_IGNORE_UNUSED, 0),
>>>> +    GATE(CLK_CMU_COREPART, "cmu_corepart", "div_aclk_100", GATE_IP_PERIR, 4,
>>>> +        CLK_IGNORE_UNUSED, 0),
>>>> +    GATE(CLK_CMU_TOPPART, "cmu_toppart", "div_aclk_100", GATE_IP_PERIR, 3,
>>>> +        CLK_IGNORE_UNUSED, 0),
>>>> +    GATE(CLK_PMU_APBIF, "pmu_apbif", "div_aclk_100", GATE_IP_PERIR, 2,
>>>> +        CLK_IGNORE_UNUSED, 0),
>>>> +    GATE(CLK_SYSREG, "sysreg", "div_aclk_100", GATE_IP_PERIR, 1,
>>>> +        CLK_IGNORE_UNUSED, 0),
>>>> +    GATE(CLK_CHIP_ID, "chip_id", "div_aclk_100", GATE_IP_PERIR, 0,
>>>> +        CLK_IGNORE_UNUSED, 0),
>>>> +
>>>> +    /* GATE_SCLK_CAM */
>>>> +    GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_cam_blk",
>>>> +        GATE_SCLK_CAM, 8, CLK_SET_RATE_PARENT, 0),
>>>> +    GATE(CLK_SCLK_M2MSCALER, "sclk_m2mscaler", "div_cam_blk",
>>>> +        GATE_SCLK_CAM, 2, CLK_SET_RATE_PARENT, 0),
>>>> +    GATE(CLK_SCLK_GSCALER1, "sclk_gscaler1", "div_cam_blk",
>>>> +        GATE_SCLK_CAM, 1, CLK_SET_RATE_PARENT, 0),
>>>> +    GATE(CLK_SCLK_GSCALER0, "sclk_gscaler0", "div_cam_blk",
>>>> +        GATE_SCLK_CAM, 0, CLK_SET_RATE_PARENT, 0),
>>>> +
>>>> +    /* GATE_SCLK_MFC */
>>>> +    GATE(CLK_SCLK_MFC, "sclk_mfc", "div_mfc",
>>>> +        GATE_SCLK_MFC, 0, CLK_SET_RATE_PARENT, 0),
>>>> +
>>>> +    /* GATE_SCLK_G3D */
>>>> +    GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d",
>>>> +        GATE_SCLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
>>>> +
>>>> +    /* GATE_SCLK_LCD */
>>>> +    GATE(CLK_SCLK_MIPIDPHY2L, "sclk_mipidphy2l", "div_mipi0",
>>>> +        GATE_SCLK_LCD, 4, CLK_SET_RATE_PARENT, 0),
>>>> +    GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi0_pre",
>>>> +        GATE_SCLK_LCD, 3, CLK_SET_RATE_PARENT, 0),
>>>> +    GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0",
>>>> +        GATE_SCLK_LCD, 0, CLK_SET_RATE_PARENT, 0),
>>>> +
>>>> +    /* GATE_SCLK_ISP_TOP */
>>>> +    GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
>>>> +        GATE_SCLK_ISP_TOP, 4, CLK_SET_RATE_PARENT, 0),
>>>> +    GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "div_uart_isp",
>>>> +        GATE_SCLK_ISP_TOP, 3, CLK_SET_RATE_PARENT, 0),
>>>> +    GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "div_spi1_isp",
>>>> +        GATE_SCLK_ISP_TOP, 2, CLK_SET_RATE_PARENT, 0),
>>>> +    GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "div_spi0_isp",
>>>> +        GATE_SCLK_ISP_TOP, 1, CLK_SET_RATE_PARENT, 0),
>>>> +
>>>> +    /* GATE_SCLK_FSYS */
>>>> +    GATE(CLK_SCLK_UPLL, "sclk_upll", "mout_upll", GATE_SCLK_FSYS, 10, 0, 0),
>>>> +    GATE(CLK_SCLK_TSADC, "sclk_tsadc", "div_tsadc_pre",
>>>> +        GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
>>>> +    GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",
>>>> +        GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),
>>>> +    GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre",
>>>> +        GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
>>>> +    GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",
>>>> +        GATE_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
>>>> +
>>>> +    /* GATE_SCLK_PERIL */
>>>> +    GATE(CLK_SCLK_I2S, "sclk_i2s", "div_i2s",
>>>> +        GATE_SCLK_PERIL, 18, CLK_SET_RATE_PARENT, 0),
>>>> +    GATE(CLK_SCLK_PCM, "sclk_pcm", "div_pcm",
>>>> +        GATE_SCLK_PERIL, 16, CLK_SET_RATE_PARENT, 0),
>>>> +    GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi1_pre",
>>>> +        GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
>>>> +    GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
>>>> +        GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
>>>> +    GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
>>>> +        GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
>>>> +    GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
>>>> +        GATE_SCLK_PERIL, 0, CLK_SET_RATE_PARENT, 0),
>>>> +
>>>> +    /* GATE_IP_CAM */
>>>> +    GATE(CLK_QEJPEG, "qejpeg", "div_cam_blk_320", GATE_IP_CAM, 19,
>>>> +        CLK_IGNORE_UNUSED, 0),
>>>> +    GATE(CLK_PIXELASYNCM1, "pixelasyncm1", "div_cam_blk_320",
>>>> +        GATE_IP_CAM, 18, CLK_IGNORE_UNUSED, 0),
>>>> +    GATE(CLK_PIXELASYNCM0, "pixelasyncm0", "div_cam_blk_320",
>>>> +        GATE_IP_CAM, 17, CLK_IGNORE_UNUSED, 0),
>>>> +    GATE(CLK_PPMUCAMIF, "ppmucamif", "div_cam_blk_320",
>>>> +        GATE_IP_CAM, 16, CLK_IGNORE_UNUSED, 0),
>>>> +    GATE(CLK_QEM2MSCALER, "qem2mscaler", "div_cam_blk_320",
>>>> +        GATE_IP_CAM, 14, CLK_IGNORE_UNUSED, 0),
>>>> +    GATE(CLK_QEGSCALER1, "qegscaler1", "div_cam_blk_320",
>>>> +        GATE_IP_CAM, 13, CLK_IGNORE_UNUSED, 0),
>>>> +    GATE(CLK_QEGSCALER0, "qegscaler0", "div_cam_blk_320",
>>>> +        GATE_IP_CAM, 12, CLK_IGNORE_UNUSED, 0),
>>>> +    GATE(CLK_SMMUJPEG, "smmujpeg", "div_cam_blk_320",
>>>> +        GATE_IP_CAM, 11, 0, 0),
>>>> +    GATE(CLK_SMMUM2M2SCALER, "smmum2m2scaler", "div_cam_blk_320",
>>>> +        GATE_IP_CAM, 9, 0, 0),
>>>> +    GATE(CLK_SMMUGSCALER1, "smmugscaler1", "div_cam_blk_320",
>>>> +        GATE_IP_CAM, 8, 0, 0),
>>>> +    GATE(CLK_SMMUGSCALER0, "smmugscaler0", "div_cam_blk_320",
>>>> +        GATE_IP_CAM, 7, 0, 0),
>>>> +    GATE(CLK_JPEG, "jpeg", "div_cam_blk_320", GATE_IP_CAM, 6, 0, 0),
>>>> +    GATE(CLK_M2MSCALER, "m2mscaler", "div_cam_blk_320",
>>>> +        GATE_IP_CAM, 2, 0, 0),
>>>> +    GATE(CLK_GSCALER1, "gscaler1", "div_cam_blk_320", GATE_IP_CAM, 1, 0, 0),
>>>> +    GATE(CLK_GSCALER0, "gscaler0", "div_cam_blk_320", GATE_IP_CAM, 0, 0, 0),
>>>> +
>>>> +    /* GATE_IP_MFC */
>>>> +    GATE(CLK_QEMFC, "qemfc", "div_aclk_200", GATE_IP_MFC, 5,
>>>> +        CLK_IGNORE_UNUSED, 0),
>>>> +    GATE(CLK_PPMUMFC_L, "ppmumfc_l", "div_aclk_200", GATE_IP_MFC, 3,
>>>> +        CLK_IGNORE_UNUSED, 0),
>>>> +    GATE(CLK_SMMUMFC_L, "smmumfc_l", "div_aclk_200", GATE_IP_MFC, 1, 0, 0),
>>>> +    GATE(CLK_MFC, "mfc", "div_aclk_200", GATE_IP_MFC, 0, 0, 0),
>>>> +
>>>> +    /* GATE_IP_G3D */
>>>> +    GATE(CLK_SMMUG3D, "smmug3d", "div_aclk_200", GATE_IP_G3D, 3, 0, 0),
>>>> +    GATE(CLK_QEG3D, "qeg3d", "div_aclk_200", GATE_IP_G3D, 2,
>>>> +        CLK_IGNORE_UNUSED, 0),
>>>> +    GATE(CLK_PPMUG3D, "ppmug3d", "div_aclk_200", GATE_IP_G3D, 1,
>>>> +        CLK_IGNORE_UNUSED, 0),
>>>> +    GATE(CLK_G3D, "g3d", "div_aclk_200", GATE_IP_G3D, 0, 0, 0),
>>>> +
>>>> +    /* GATE_IP_LCD */
>>>> +    GATE(CLK_QE_CH1_LCD, "qe_ch1_lcd", "div_aclk_160", GATE_IP_LCD, 7,
>>>> +        CLK_IGNORE_UNUSED, 0),
>>>> +    GATE(CLK_QE_CH0_LCD, "qe_ch0_lcd", "div_aclk_160", GATE_IP_LCD, 6,
>>>> +        CLK_IGNORE_UNUSED, 0),
>>>> +    GATE(CLK_PPMULCD0, "ppmulcd0", "div_aclk_160", GATE_IP_LCD, 5,
>>>> +        CLK_IGNORE_UNUSED, 0),
>>>> +    GATE(CLK_SMMUFIMD0, "smmufimd0", "div_aclk_160", GATE_IP_LCD, 4, 0, 0),
>>>> +    GATE(CLK_DSIM0, "dsim0", "div_aclk_160", GATE_IP_LCD, 3, 0, 0),
>>>> +    GATE(CLK_SMIES, "smies", "div_aclk_160", GATE_IP_LCD, 2, 0, 0),
>>>> +    GATE(CLK_FIMD0, "fimd0", "div_aclk_160", GATE_IP_LCD, 0, 0, 0),
>>>> +
>>>> +    /* GATE_IP_ISP */
>>>> +    GATE(CLK_CAM1, "cam1", "mout_aclk_266_sub", GATE_IP_ISP, 5, 0, 0),
>>>> +    GATE(CLK_UART_ISP_TOP, "uart_isp_top", "mout_aclk_266_sub",
>>>> +        GATE_IP_ISP, 3, 0, 0),
>>>> +    GATE(CLK_SPI1_ISP_TOP, "spi1_isp_top", "mout_aclk_266_sub",
>>>> +        GATE_IP_ISP, 2, 0, 0),
>>>> +    GATE(CLK_SPI0_ISP_TOP, "spi0_isp_top", "mout_aclk_266_sub",
>>>> +        GATE_IP_ISP, 1, 0, 0),
>>>> +
>>>> +    /* GATE_IP_FSYS */
>>>> +    GATE(CLK_TSADC, "tsadc", "div_aclk_200", GATE_IP_FSYS, 20, 0, 0),
>>>> +    GATE(CLK_PPMUFILE, "ppmufile", "div_aclk_200", GATE_IP_FSYS, 17,
>>>> +        CLK_IGNORE_UNUSED, 0),
>>>> +    GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0),
>>>> +    GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
>>>> +    GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
>>>> +    GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
>>>> +    GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
>>>> +    GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
>>>> +    GATE(CLK_PDMA0, "pdma0", "div_aclk_200", GATE_IP_FSYS, 0, 0, 0),
>>>> +
>>>> +    /* GATE_IP_PERIL */
>>>> +    GATE(CLK_PWM, "pwm", "div_aclk_100", GATE_IP_PERIL, 24, 0, 0),
>>>> +    GATE(CLK_PCM, "pcm", "div_aclk_100", GATE_IP_PERIL, 23, 0, 0),
>>>> +    GATE(CLK_I2S, "i2s", "div_aclk_100", GATE_IP_PERIL, 21, 0, 0),
>>>> +    GATE(CLK_SPI1, "spi1", "div_aclk_100", GATE_IP_PERIL, 17, 0, 0),
>>>> +    GATE(CLK_SPI0, "spi0", "div_aclk_100", GATE_IP_PERIL, 16, 0, 0),
>>>> +    GATE(CLK_I2C7, "i2c7", "div_aclk_100", GATE_IP_PERIL, 13, 0, 0),
>>>> +    GATE(CLK_I2C6, "i2c6", "div_aclk_100", GATE_IP_PERIL, 12, 0, 0),
>>>> +    GATE(CLK_I2C5, "i2c5", "div_aclk_100", GATE_IP_PERIL, 11, 0, 0),
>>>> +    GATE(CLK_I2C4, "i2c4", "div_aclk_100", GATE_IP_PERIL, 10, 0, 0),
>>>> +    GATE(CLK_I2C3, "i2c3", "div_aclk_100", GATE_IP_PERIL, 9, 0, 0),
>>>> +    GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
>>>> +    GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
>>>> +    GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
>>>> +    GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
>>>> +    GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
>>>> +
>>>> +    /* GATE_BLOCK */
>>>> +    GATE(CLK_BLOCK_LCD, "block_lcd", "div_aclk_160", GATE_BLOCK, 4, 0, 0),
>>>> +    GATE(CLK_BLOCK_G3D, "block_g3d", "div_aclk_200", GATE_BLOCK, 3, 0, 0),
>>>
>>> Are there only 2 gate block clocks? By the way, how are they going to be handled by respective drivers? There is no mainline support for them right now, but you should be aware that adding them will cause common clock framework to disable them if not claimed by any driver.
>>
>> OK, I'll add remaing clock gate of GATE_BLOCK as following.
>> - CLK_BLOCK_MFC MFC_BLK
>> - CLK_BLOCK_CAM CAM_BLK
>>
> 
> I agree that in the end the block gates will have to be added. However
> currently drivers do not request block gates and enable them.
> Considering that common clock framework disables all unused clocks by
> default, this will lead to all the gate block clocks being disabled,
> which is not desired.

You're right.

> 
> My opinion on this is that block gate clocks should be added in separate
> patch along with patches adding code to get and enable them.

OK, I'll remove the clocks of GATE_BLOCK on next posting(v6)

> 
>>>
>>>> +};
>>>> +
>>>> +/* APLL & MPLL & BPLL & UPLL */
>>>> +static struct samsung_pll_rate_table exynos3250_pll_rates[] = {
>>>> +    PLL_35XX_RATE(1200000000, 400, 4, 1),
>>>> +    PLL_35XX_RATE(1100000000, 275, 3, 1),
>>>> +    PLL_35XX_RATE(1066000000, 533, 6, 1),
>>>> +    PLL_35XX_RATE(1000000000, 250, 3, 1),
>>>> +    PLL_35XX_RATE( 960000000, 320, 4, 1),
>>>> +    PLL_35XX_RATE( 900000000, 300, 4, 1),
>>>> +    PLL_35XX_RATE( 850000000, 425, 6, 1),
>>>> +    PLL_35XX_RATE( 800000000, 200, 3, 1),
>>>> +    PLL_35XX_RATE( 700000000, 175, 3, 1),
>>>> +    PLL_35XX_RATE( 667000000, 667, 12, 1),
>>>> +    PLL_35XX_RATE( 600000000, 400, 4, 2),
>>>> +    PLL_35XX_RATE( 533000000, 533, 6, 2),
>>>> +    PLL_35XX_RATE( 520000000, 260, 3, 2),
>>>> +    PLL_35XX_RATE( 500000000, 250, 3, 2),
>>>> +    PLL_35XX_RATE( 400000000, 200, 3, 2),
>>>> +    PLL_35XX_RATE( 200000000, 200, 3, 3),
>>>> +    PLL_35XX_RATE( 100000000, 200, 3, 4),
>>>> +    { /* sentinel */ }
>>>> +};
>>>> +
>>>> +/* VPLL */
>>>> +static struct samsung_pll_rate_table exynos3250_vpll_rates[] = {
>>>> +    PLL_36XX_RATE(600000000, 100, 2, 1,     0),
>>>> +    PLL_36XX_RATE(533000000, 267, 3, 2, 32668),
> 
> The TRM actually lists this as 267, 3, 2, 32768, and according to the
> equation it will be 535000015 Hz. Looks like a typo in the data sheet,
> as 266, 3, 2, 32768 gives 533000015, which is almost exactly 533 MHz.
> 
>>>> +    PLL_36XX_RATE(519231000, 173, 2, 2,  5046),
> 
> 519230991
> 
>>>> +    PLL_36XX_RATE(500000000, 250, 3, 2,     0),
>>>> +    PLL_36XX_RATE(445500000, 149, 2, 2, 32768),
> 
> 448500022
> 
> Also looks like a typo in the TRM, as 148, 2, 2, 32768 gives 445500022,
> which is almost exactly 445.5 MHz.
> 
> 
>>>> +    PLL_36XX_RATE(445055000, 148, 2, 2, 23047),
> 
> 445055024
> 
>>>> +    PLL_36XX_RATE(400000000, 200, 3, 2,     0),
>>>> +    PLL_36XX_RATE(371250000, 124, 2, 2, 49512),
> 
> The TRM lists this as 124, 2, 2, 49152 and calculated frequency is
> 374250034. This one also looks like a typo. 123, 2, 2, 49512 would give
> 371250034.

When I calculated fout with following data:
- 124, 2, 2, 49512 would give 374266514.1
- 123, 2, 2, 49512 would give 371266514.1.

I think below value is proper. 
- 123, 2, 2, 49512 would give 371266514.1.

> 
>>>> +    PLL_36XX_RATE(370879000, 185, 3, 2, 28803),
> 
> 370879011
> 
>>>> +    PLL_36XX_RATE(340000000, 170, 3, 2,     0),
>>>> +    PLL_36XX_RATE(335000000, 112, 2, 2, 43691),
> 
> 338000045
> 
> 111, 2, 2, 43691 would give 335000045. A typo in TRM?
> 
>>>> +    PLL_36XX_RATE(333000000, 111, 2, 2,     0),
>>>> +    PLL_36XX_RATE(330000000, 110, 2, 2,     0),
>>>> +    PLL_36XX_RATE(320000000, 107, 2, 2, 43691),
> 
> 323000045
> 
> 106, 2, 2, 43691 would give 320000045.
> 
>>>> +    PLL_36XX_RATE(300000000, 100, 2, 2,     0),
>>>> +    PLL_36XX_RATE(275000000, 275, 3, 3,     0),
>>>> +    PLL_36XX_RATE(222750000, 149, 2, 3, 32768),
> 
> 224250011
> 
> 148, 2, 3, 32768 would give 222750011.
> 
>>>> +    PLL_36XX_RATE(222528000, 148, 2, 3, 23069),
> 
> 222528015
> 
>>>> +    PLL_36XX_RATE(160000000, 160, 3, 3,     0),
>>>> +    PLL_36XX_RATE(148500000,  99, 2, 3,     0),
>>>> +    PLL_36XX_RATE(148352000,  99, 2, 3, 59070),
> 
> 149852025
> 
> 98, 2, 3, 59070 would give 148352025.
> 
>>>> +    PLL_36XX_RATE(108000000, 144, 2, 4,     0),
>>>> +    PLL_36XX_RATE( 74250000,  99, 2, 4,     0),
>>>> +    PLL_36XX_RATE( 74176000,  99, 3, 4, 59070),
> 
> The TRM seems to list this as 99, 2, 4 and calculated frequency will be
> 74926012, but 98, 2, 4, 59070 would give 74176012.
> 
>>>> +    PLL_36XX_RATE( 54054000, 216, 3, 5, 14156),
> 
> 54054001
> 
>>>> +    PLL_36XX_RATE( 54000000, 144, 2, 5,     0),
>>>
>>> Are all these frequencies above calculated exactly? For correct operation of rate setting code, it is necessary for frequency values specified in these arrays to be exact, not rounded.
>>
>> When I implemnted exynos3250_vpll_rates array, I used 'VPLL PMS Value' in Exynos3250 TRM without modification.
>> This rate value of exynos3250_vpll_rates is correct.
> 
> Well, after checking the values using PLL equation for VPLL, as
> specified in TRM and used by clk-pll.c, the values don't match.
> 
> Keep in mind that the values must be exact, _not_ rounded, while in the
> TRM they are rounded. Moreover it looks like several frequencies in TRM
> are off by 1 in M coefficient. Please see above.

Thanks for your point out.

So, I calculated fout of VPLL using PLL equation in Exynos3250 TRM.

Following table show fout(Recalc rate) with fin_pll/mdiv/pdiv/sdiv/kdiv:
fin_pll		Recalc rate	TRM rate	mdiv	pdiv	sdiv	kdiv
24000000	600000000	600000000	100	2	1	0
24000000	533000015.3	533000000	266	3	2	32768
24000000	519230991.1	519231000	173	2	2	5046
24000000	500000000	500000000	250	3	2	0
24000000	445500022.9	445500000	148	2	2	32768
24000000	445055024	445055000	148	2	2	23047
24000000	400000000	400000000	200	3	2	0
24000000	371266514.1	371250000	123	2	2	49512
24000000	370879011.2	370879000	185	3	2	28803
24000000	340000000	340000000	170	3	2	0
24000000	335000045.8	335000000	111	2	2	43691
24000000	333000000	333000000	111	2	2	0
24000000	330000000	330000000	110	2	2	0
24000000	320000045.8	320000000	106	2	2	43691
24000000	300000000	300000000	100	2	2	0
24000000	275000000	275000000	275	3	3	0
24000000	222750011.4	222750000	148	2	3	32768
24000000	222528015.6	222528000	148	2	3	23069
24000000	160000000	160000000	160	3	3	0
24000000	148500000	148500000	99	2	3	0
24000000	148352025.6	148352000	98	2	3	59070
24000000	108000000	108000000	144	2	4	0
24000000	74250000	74250000	99	2	4	0
24000000	74176012.82	74176000	98	2	4	59070
24000000	54054001.68	54054000	216	3	5	14156
24000000	54000000	54000000	144	2	5	0


If you ok, I'll modify vpll_rates table as following:
+static struct samsung_pll_rate_table exynos3250_vpll_rates[] = {
+	PLL_36XX_RATE(600000000, 100, 2, 1,     0),
+	PLL_36XX_RATE(533000000, 266, 3, 2, 32768),
+	PLL_36XX_RATE(519230991, 173, 2, 2,  5046),
+	PLL_36XX_RATE(500000000, 250, 3, 2,     0),
+	PLL_36XX_RATE(445500022, 148, 2, 2, 32768),
+	PLL_36XX_RATE(445055024, 148, 2, 2, 23047),
+	PLL_36XX_RATE(400000000, 200, 3, 2,     0),
+	PLL_36XX_RATE(371266514, 123, 2, 2, 49512),
+	PLL_36XX_RATE(370879011, 185, 3, 2, 28803),
+	PLL_36XX_RATE(340000000, 170, 3, 2,     0),
+	PLL_36XX_RATE(335000045, 111, 2, 2, 43691),
+	PLL_36XX_RATE(333000000, 111, 2, 2,     0),
+	PLL_36XX_RATE(330000000, 110, 2, 2,     0),
+	PLL_36XX_RATE(320000045, 106, 2, 2, 43691),
+	PLL_36XX_RATE(300000000, 100, 2, 2,     0),
+	PLL_36XX_RATE(275000000, 275, 3, 3,     0),
+	PLL_36XX_RATE(222750011, 148, 2, 3, 32768),
+	PLL_36XX_RATE(222528015, 148, 2, 3, 23069),
+	PLL_36XX_RATE(160000000, 160, 3, 3,     0),
+	PLL_36XX_RATE(148500000,  99, 2, 3,     0),
+	PLL_36XX_RATE(148352025,  98, 2, 3, 59070),
+	PLL_36XX_RATE(108000000, 144, 2, 4,     0),
+	PLL_36XX_RATE( 74250000,  99, 2, 4,     0),
+	PLL_36XX_RATE( 74176012,  98, 2, 4, 59070),
+	PLL_36XX_RATE( 54054012, 216, 3, 5, 14156),
+	PLL_36XX_RATE( 54000000, 144, 2, 5,     0),
+	{ /* sentinel */ }
+};

Best Regards,
Chanwoo Choi

Re: [PATCHv4 5/7] clk: samsung: exynos3250: Add clocks using common clock framework

[Tomasz Figa]

Hi Chanwoo

On 14.05.2014 08:57, Chanwoo Choi wrote:
> On 05/14/2014 01:28 AM, Tomasz Figa wrote:
>> On 13.05.2014 13:49, Chanwoo Choi wrote:
>>> On 04/26/2014 09:39 AM, Tomasz Figa wrote:
>>>> On 25.04.2014 03:16, Chanwoo Choi wrote:
>>>>> +    /* GATE_BLOCK */
>>>>> +    GATE(CLK_BLOCK_LCD, "block_lcd", "div_aclk_160", GATE_BLOCK, 4, 0, 0),
>>>>> +    GATE(CLK_BLOCK_G3D, "block_g3d", "div_aclk_200", GATE_BLOCK, 3, 0, 0),
>>>>
>>>> Are there only 2 gate block clocks? By the way, how are they going to be handled by respective drivers? There is no mainline support for them right now, but you should be aware that adding them will cause common clock framework to disable them if not claimed by any driver.
>>>
>>> OK, I'll add remaing clock gate of GATE_BLOCK as following.
>>> - CLK_BLOCK_MFC MFC_BLK
>>> - CLK_BLOCK_CAM CAM_BLK
>>>
>>
>> I agree that in the end the block gates will have to be added. However
>> currently drivers do not request block gates and enable them.
>> Considering that common clock framework disables all unused clocks by
>> default, this will lead to all the gate block clocks being disabled,
>> which is not desired.
> 
> You're right.
> 
>>
>> My opinion on this is that block gate clocks should be added in separate
>> patch along with patches adding code to get and enable them.
> 
> OK, I'll remove the clocks of GATE_BLOCK on next posting(v6)
> 

OK, thanks.

By the way, if there are no other comments to v5 series than to this
patch, then you can simply send v6 of this single patch as a reply to v5.

>>
>>>>
>>>>> +};
>>>>> +
>>>>> +/* APLL & MPLL & BPLL & UPLL */
>>>>> +static struct samsung_pll_rate_table exynos3250_pll_rates[] = {
>>>>> +    PLL_35XX_RATE(1200000000, 400, 4, 1),
>>>>> +    PLL_35XX_RATE(1100000000, 275, 3, 1),
>>>>> +    PLL_35XX_RATE(1066000000, 533, 6, 1),
>>>>> +    PLL_35XX_RATE(1000000000, 250, 3, 1),
>>>>> +    PLL_35XX_RATE( 960000000, 320, 4, 1),
>>>>> +    PLL_35XX_RATE( 900000000, 300, 4, 1),
>>>>> +    PLL_35XX_RATE( 850000000, 425, 6, 1),
>>>>> +    PLL_35XX_RATE( 800000000, 200, 3, 1),
>>>>> +    PLL_35XX_RATE( 700000000, 175, 3, 1),
>>>>> +    PLL_35XX_RATE( 667000000, 667, 12, 1),
>>>>> +    PLL_35XX_RATE( 600000000, 400, 4, 2),
>>>>> +    PLL_35XX_RATE( 533000000, 533, 6, 2),
>>>>> +    PLL_35XX_RATE( 520000000, 260, 3, 2),
>>>>> +    PLL_35XX_RATE( 500000000, 250, 3, 2),
>>>>> +    PLL_35XX_RATE( 400000000, 200, 3, 2),
>>>>> +    PLL_35XX_RATE( 200000000, 200, 3, 3),
>>>>> +    PLL_35XX_RATE( 100000000, 200, 3, 4),
>>>>> +    { /* sentinel */ }
>>>>> +};
>>>>> +
>>>>> +/* VPLL */
>>>>> +static struct samsung_pll_rate_table exynos3250_vpll_rates[] = {
>>>>> +    PLL_36XX_RATE(600000000, 100, 2, 1,     0),
>>>>> +    PLL_36XX_RATE(533000000, 267, 3, 2, 32668),
>>
>> The TRM actually lists this as 267, 3, 2, 32768, and according to the
>> equation it will be 535000015 Hz. Looks like a typo in the data sheet,
>> as 266, 3, 2, 32768 gives 533000015, which is almost exactly 533 MHz.
>>
>>>>> +    PLL_36XX_RATE(519231000, 173, 2, 2,  5046),
>>
>> 519230991
>>
>>>>> +    PLL_36XX_RATE(500000000, 250, 3, 2,     0),
>>>>> +    PLL_36XX_RATE(445500000, 149, 2, 2, 32768),
>>
>> 448500022
>>
>> Also looks like a typo in the TRM, as 148, 2, 2, 32768 gives 445500022,
>> which is almost exactly 445.5 MHz.
>>
>>
>>>>> +    PLL_36XX_RATE(445055000, 148, 2, 2, 23047),
>>
>> 445055024
>>
>>>>> +    PLL_36XX_RATE(400000000, 200, 3, 2,     0),
>>>>> +    PLL_36XX_RATE(371250000, 124, 2, 2, 49512),
>>
>> The TRM lists this as 124, 2, 2, 49152 and calculated frequency is
>> 374250034. This one also looks like a typo. 123, 2, 2, 49512 would give
>> 371250034.
> 
> When I calculated fout with following data:
> - 124, 2, 2, 49512 would give 374266514.1
> - 123, 2, 2, 49512 would give 371266514.1.
> 
> I think below value is proper. 
> - 123, 2, 2, 49512 would give 371266514.1.
> 

Sorry, my bad, I made a typo as well ;). It should be 123, 2, 2, 49152.
The value I got was correct - 371250034.

>>
>>>>> +    PLL_36XX_RATE(370879000, 185, 3, 2, 28803),
>>
>> 370879011
>>
>>>>> +    PLL_36XX_RATE(340000000, 170, 3, 2,     0),
>>>>> +    PLL_36XX_RATE(335000000, 112, 2, 2, 43691),
>>
>> 338000045
>>
>> 111, 2, 2, 43691 would give 335000045. A typo in TRM?
>>
>>>>> +    PLL_36XX_RATE(333000000, 111, 2, 2,     0),
>>>>> +    PLL_36XX_RATE(330000000, 110, 2, 2,     0),
>>>>> +    PLL_36XX_RATE(320000000, 107, 2, 2, 43691),
>>
>> 323000045
>>
>> 106, 2, 2, 43691 would give 320000045.
>>
>>>>> +    PLL_36XX_RATE(300000000, 100, 2, 2,     0),
>>>>> +    PLL_36XX_RATE(275000000, 275, 3, 3,     0),
>>>>> +    PLL_36XX_RATE(222750000, 149, 2, 3, 32768),
>>
>> 224250011
>>
>> 148, 2, 3, 32768 would give 222750011.
>>
>>>>> +    PLL_36XX_RATE(222528000, 148, 2, 3, 23069),
>>
>> 222528015
>>
>>>>> +    PLL_36XX_RATE(160000000, 160, 3, 3,     0),
>>>>> +    PLL_36XX_RATE(148500000,  99, 2, 3,     0),
>>>>> +    PLL_36XX_RATE(148352000,  99, 2, 3, 59070),
>>
>> 149852025
>>
>> 98, 2, 3, 59070 would give 148352025.
>>
>>>>> +    PLL_36XX_RATE(108000000, 144, 2, 4,     0),
>>>>> +    PLL_36XX_RATE( 74250000,  99, 2, 4,     0),
>>>>> +    PLL_36XX_RATE( 74176000,  99, 3, 4, 59070),
>>
>> The TRM seems to list this as 99, 2, 4 and calculated frequency will be
>> 74926012, but 98, 2, 4, 59070 would give 74176012.
>>
>>>>> +    PLL_36XX_RATE( 54054000, 216, 3, 5, 14156),
>>
>> 54054001
>>
>>>>> +    PLL_36XX_RATE( 54000000, 144, 2, 5,     0),
>>>>
>>>> Are all these frequencies above calculated exactly? For correct operation of rate setting code, it is necessary for frequency values specified in these arrays to be exact, not rounded.
>>>
>>> When I implemnted exynos3250_vpll_rates array, I used 'VPLL PMS Value' in Exynos3250 TRM without modification.
>>> This rate value of exynos3250_vpll_rates is correct.
>>
>> Well, after checking the values using PLL equation for VPLL, as
>> specified in TRM and used by clk-pll.c, the values don't match.
>>
>> Keep in mind that the values must be exact, _not_ rounded, while in the
>> TRM they are rounded. Moreover it looks like several frequencies in TRM
>> are off by 1 in M coefficient. Please see above.
> 
> Thanks for your point out.
> 
> So, I calculated fout of VPLL using PLL equation in Exynos3250 TRM.
> 
> Following table show fout(Recalc rate) with fin_pll/mdiv/pdiv/sdiv/kdiv:
> fin_pll		Recalc rate	TRM rate	mdiv	pdiv	sdiv	kdiv
> 24000000	600000000	600000000	100	2	1	0
> 24000000	533000015.3	533000000	266	3	2	32768
> 24000000	519230991.1	519231000	173	2	2	5046
> 24000000	500000000	500000000	250	3	2	0
> 24000000	445500022.9	445500000	148	2	2	32768
> 24000000	445055024	445055000	148	2	2	23047
> 24000000	400000000	400000000	200	3	2	0
> 24000000	371266514.1	371250000	123	2	2	49512
> 24000000	370879011.2	370879000	185	3	2	28803
> 24000000	340000000	340000000	170	3	2	0
> 24000000	335000045.8	335000000	111	2	2	43691
> 24000000	333000000	333000000	111	2	2	0
> 24000000	330000000	330000000	110	2	2	0
> 24000000	320000045.8	320000000	106	2	2	43691
> 24000000	300000000	300000000	100	2	2	0
> 24000000	275000000	275000000	275	3	3	0
> 24000000	222750011.4	222750000	148	2	3	32768
> 24000000	222528015.6	222528000	148	2	3	23069
> 24000000	160000000	160000000	160	3	3	0
> 24000000	148500000	148500000	99	2	3	0
> 24000000	148352025.6	148352000	98	2	3	59070
> 24000000	108000000	108000000	144	2	4	0
> 24000000	74250000	74250000	99	2	4	0
> 24000000	74176012.82	74176000	98	2	4	59070
> 24000000	54054001.68	54054000	216	3	5	14156
> 24000000	54000000	54000000	144	2	5	0
> 
> 
> If you ok, I'll modify vpll_rates table as following:
> +static struct samsung_pll_rate_table exynos3250_vpll_rates[] = {
> +	PLL_36XX_RATE(600000000, 100, 2, 1,     0),
> +	PLL_36XX_RATE(533000000, 266, 3, 2, 32768),

According to the table above, shouldn't it be 533000015?

> +	PLL_36XX_RATE(519230991, 173, 2, 2,  5046),
> +	PLL_36XX_RATE(500000000, 250, 3, 2,     0),
> +	PLL_36XX_RATE(445500022, 148, 2, 2, 32768),
> +	PLL_36XX_RATE(445055024, 148, 2, 2, 23047),
> +	PLL_36XX_RATE(400000000, 200, 3, 2,     0),
> +	PLL_36XX_RATE(371266514, 123, 2, 2, 49512),
> +	PLL_36XX_RATE(370879011, 185, 3, 2, 28803),
> +	PLL_36XX_RATE(340000000, 170, 3, 2,     0),
> +	PLL_36XX_RATE(335000045, 111, 2, 2, 43691),
> +	PLL_36XX_RATE(333000000, 111, 2, 2,     0),
> +	PLL_36XX_RATE(330000000, 110, 2, 2,     0),
> +	PLL_36XX_RATE(320000045, 106, 2, 2, 43691),
> +	PLL_36XX_RATE(300000000, 100, 2, 2,     0),
> +	PLL_36XX_RATE(275000000, 275, 3, 3,     0),
> +	PLL_36XX_RATE(222750011, 148, 2, 3, 32768),
> +	PLL_36XX_RATE(222528015, 148, 2, 3, 23069),
> +	PLL_36XX_RATE(160000000, 160, 3, 3,     0),
> +	PLL_36XX_RATE(148500000,  99, 2, 3,     0),
> +	PLL_36XX_RATE(148352025,  98, 2, 3, 59070),
> +	PLL_36XX_RATE(108000000, 144, 2, 4,     0),
> +	PLL_36XX_RATE( 74250000,  99, 2, 4,     0),
> +	PLL_36XX_RATE( 74176012,  98, 2, 4, 59070),
> +	PLL_36XX_RATE( 54054012, 216, 3, 5, 14156),
> +	PLL_36XX_RATE( 54000000, 144, 2, 5,     0),
> +	{ /* sentinel */ }
> +};

There is one more thing, I found when analyzing this. clk-pll.c actually
uses 65536 (actually shift by 16) instead of 65535 in the equation given
in TRM and this gives better values. See samsung_pll36xx_recalc_rate().

By using script

>>> fin = 24000000
>>> def pll(m,p,s,k):
...     print (fin * (m * 65536 + k)) / (65536 * p * 2**s)
...

I'm getting better values, e.g.

>>> pll(266, 3, 2, 32768)
533000000

>>> pll(123, 2, 2, 49152)
371250000

Considering the fact that for PLL36xx Exynos5250 TRM uses 65536 as well,
this is probably the right equation. So please recalculate the values
again using:

FOUT = (MDIV + K/65536) x FIN/(PDIV x 2^SDIV)

or just my script above run in Python 2.x interpreter.

Best regards,
Tomasz