[PATCH v3 1/2] PCI: keystone: remove handle of PCI mode configuration

[PATCH v3 1/2] PCI: keystone: remove handle of PCI mode configuration

[Murali Karicheri]

Keystone PCI hardware supports both RC and EP modes and devcfg
register has bits to boot strap the device to either of these modes.
It seems proper to add this functionality to the boot loader rather
than in the driver as device will be operating in either mode, not
both any time. Currently the driver supports only RC mode and hence
register configuration in the driver is not needed and driver can
assume this is a RC hardware.

Also update the DT documentation accordingly.

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
---
	v3 - No change
	v2 - Added this separate patch to remove pci mode handling
 .../devicetree/bindings/pci/pci-keystone.txt       |    4 +---
 drivers/pci/host/pci-keystone.c                    |   21 ++------------------
 2 files changed, 3 insertions(+), 22 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/pci-keystone.txt b/Documentation/devicetree/bindings/pci/pci-keystone.txt
index ceb3e24..bedacf0 100644
--- a/Documentation/devicetree/bindings/pci/pci-keystone.txt
+++ b/Documentation/devicetree/bindings/pci/pci-keystone.txt
@@ -13,9 +13,7 @@ Required Properties:-
 
 compatibility: "ti,keystone-pcie"
 reg:	index 1 is the base address and length of DW application registers.
-	index 2 is the base address and length of PCI mode configuration
-	register.
-	index 3 is the base address and length of PCI device ID register.
+	index 2 is the base address and length of PCI device ID register.
 
 pcie_msi_intc : Interrupt controller device node for MSI IRQ chip
 	interrupt-cells: should be set to 1
diff --git a/drivers/pci/host/pci-keystone.c b/drivers/pci/host/pci-keystone.c
index ff8ed25..f1119eb 100644
--- a/drivers/pci/host/pci-keystone.c
+++ b/drivers/pci/host/pci-keystone.c
@@ -35,10 +35,6 @@
 #define MAX_MSI_HOST_IRQS		8
 #define MAX_LEGACY_HOST_IRQS		4
 
-/* RC mode settings masks */
-#define PCIE_RC_MODE		BIT(2)
-#define PCIE_MODE_MASK		(BIT(1) | BIT(2))
-
 /* DEV_STAT_CTRL */
 #define PCIE_CAP_BASE		0x70
 
@@ -355,7 +351,6 @@ static int __init ks_pcie_probe(struct platform_device *pdev)
 	void __iomem *reg_p;
 	struct phy *phy;
 	int ret = 0;
-	u32 val;
 
 	ks_pcie = devm_kzalloc(&pdev->dev, sizeof(*ks_pcie),
 				GFP_KERNEL);
@@ -365,18 +360,6 @@ static int __init ks_pcie_probe(struct platform_device *pdev)
 	}
 	pp = &ks_pcie->pp;
 
-	/* index 2 is the devcfg register for RC mode settings */
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
-	reg_p = devm_ioremap_resource(dev, res);
-	if (IS_ERR(reg_p))
-		return PTR_ERR(reg_p);
-
-	/* enable RC mode in devcfg */
-	val = readl(reg_p);
-	val &= ~PCIE_MODE_MASK;
-	val |= PCIE_RC_MODE;
-	writel(val, reg_p);
-
 	/* initialize SerDes Phy if present */
 	phy = devm_phy_get(dev, "pcie-phy");
 	if (!IS_ERR_OR_NULL(phy)) {
@@ -385,8 +368,8 @@ static int __init ks_pcie_probe(struct platform_device *pdev)
 			return ret;
 	}
 
-	/* index 3 is to read PCI DEVICE_ID */
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
+	/* index 2 is to read PCI DEVICE_ID */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
 	reg_p = devm_ioremap_resource(dev, res);
 	if (IS_ERR(reg_p))
 		return PTR_ERR(reg_p);
-- 
1.7.9.5

[PATCH v3 2/2] PCI: keystone: read pci device id dynamically to support multiple ports

[Murali Karicheri]

K2E SoC has two PCI ports. The SATA controller is connected to second
PCI port (port 1). To support multiple port handling in Keystone PCI
driver, read the PCI device ID dynamically by iomap/read/unmap during
probe and save it in driver's private data and update it in host init code.
The PCI device ID field in the RC's config space is not filled by
default by the hardware and has to be updated by the PCI driver by
reading the same from the SoC register indicated by reg index #2 in
DT bindings.

While at it remove the note for bootargs as this is no longer needed.

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
---
 v3 - removed handling of pcie-port and removed the documentation. Also
      updated commit log to reflect the real change.
 v2 - updated based on comment against v1. Removed handling of RC mode
      
 .../devicetree/bindings/pci/pci-keystone.txt       |    3 ---
 drivers/pci/host/pci-keystone.c                    |    9 +++++----
 drivers/pci/host/pci-keystone.h                    |    4 ++--
 3 files changed, 7 insertions(+), 9 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/pci-keystone.txt b/Documentation/devicetree/bindings/pci/pci-keystone.txt
index bedacf0..54eae29 100644
--- a/Documentation/devicetree/bindings/pci/pci-keystone.txt
+++ b/Documentation/devicetree/bindings/pci/pci-keystone.txt
@@ -61,6 +61,3 @@ Designware DT Properties not applicable for Keystone PCI
 
 1. pcie_bus clock-names not used.  Instead, a phandle to phys is used.
 
-Note for PCI driver usage
-=========================
-Driver requires pci=pcie_bus_perf in the bootargs for proper functioning.
diff --git a/drivers/pci/host/pci-keystone.c b/drivers/pci/host/pci-keystone.c
index f1119eb..a74f26e 100644
--- a/drivers/pci/host/pci-keystone.c
+++ b/drivers/pci/host/pci-keystone.c
@@ -253,8 +253,8 @@ static int keystone_pcie_fault(unsigned long addr, unsigned int fsr,
 
 static void __init ks_pcie_host_init(struct pcie_port *pp)
 {
-	u32 vendor_device_id, val;
 	struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
+	u32 val;
 
 	ks_pcie_establish_link(ks_pcie);
 	ks_dw_pcie_setup_rc_app_regs(ks_pcie);
@@ -263,8 +263,7 @@ static void __init ks_pcie_host_init(struct pcie_port *pp)
 			pp->dbi_base + PCI_IO_BASE);
 
 	/* update the Vendor ID */
-	vendor_device_id = readl(ks_pcie->va_reg_pciid);
-	writew((vendor_device_id >> 16), pp->dbi_base + PCI_DEVICE_ID);
+	writew(ks_pcie->device_id, pp->dbi_base + PCI_DEVICE_ID);
 
 	/* update the DEV_STAT_CTRL to publish right mrrs */
 	val = readl(pp->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL);
@@ -373,7 +372,9 @@ static int __init ks_pcie_probe(struct platform_device *pdev)
 	reg_p = devm_ioremap_resource(dev, res);
 	if (IS_ERR(reg_p))
 		return PTR_ERR(reg_p);
-	ks_pcie->va_reg_pciid = reg_p;
+	ks_pcie->device_id = readl(reg_p) >> 16;
+	devm_iounmap(dev, reg_p);
+	devm_release_mem_region(dev, res->start, resource_size(res));
 
 	pp->dev = dev;
 	platform_set_drvdata(pdev, ks_pcie);
diff --git a/drivers/pci/host/pci-keystone.h b/drivers/pci/host/pci-keystone.h
index 729ea7d..80cfa8e 100644
--- a/drivers/pci/host/pci-keystone.h
+++ b/drivers/pci/host/pci-keystone.h
@@ -19,8 +19,8 @@
 struct keystone_pcie {
 	struct	clk		*clk;
 	struct	pcie_port	pp;
-	void __iomem		*va_reg_pciid;
-
+	/* PCI Device ID */
+	u32			device_id;
 	int			num_legacy_host_irqs;
 	int			legacy_host_irqs[MAX_LEGACY_HOST_IRQS];
 	struct			device_node *legacy_intc_np;
-- 
1.7.9.5

Re: [PATCH v3 1/2] PCI: keystone: remove handle of PCI mode configuration

[Murali Karicheri]

On 09/10/2014 01:12 PM, Murali Karicheri wrote:
> Keystone PCI hardware supports both RC and EP modes and devcfg
> register has bits to boot strap the device to either of these modes.
> It seems proper to add this functionality to the boot loader rather
> than in the driver as device will be operating in either mode, not
> both any time. Currently the driver supports only RC mode and hence
> register configuration in the driver is not needed and driver can
> assume this is a RC hardware.
>
> Also update the DT documentation accordingly.
>
> Signed-off-by: Murali Karicheri<m-karicheri2@ti.com>
> Acked-by: Arnd Bergmann<arnd@arndb.de>
> ---
> 	v3 - No change
> 	v2 - Added this separate patch to remove pci mode handling
>   .../devicetree/bindings/pci/pci-keystone.txt       |    4 +---
>   drivers/pci/host/pci-keystone.c                    |   21 ++------------------
>   2 files changed, 3 insertions(+), 22 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/pci-keystone.txt b/Documentation/devicetree/bindings/pci/pci-keystone.txt
> index ceb3e24..bedacf0 100644
> --- a/Documentation/devicetree/bindings/pci/pci-keystone.txt
> +++ b/Documentation/devicetree/bindings/pci/pci-keystone.txt
> @@ -13,9 +13,7 @@ Required Properties:-
>
>   compatibility: "ti,keystone-pcie"
>   reg:	index 1 is the base address and length of DW application registers.
> -	index 2 is the base address and length of PCI mode configuration
> -	register.
> -	index 3 is the base address and length of PCI device ID register.
> +	index 2 is the base address and length of PCI device ID register.
>
>   pcie_msi_intc : Interrupt controller device node for MSI IRQ chip
>   	interrupt-cells: should be set to 1
> diff --git a/drivers/pci/host/pci-keystone.c b/drivers/pci/host/pci-keystone.c
> index ff8ed25..f1119eb 100644
> --- a/drivers/pci/host/pci-keystone.c
> +++ b/drivers/pci/host/pci-keystone.c
> @@ -35,10 +35,6 @@
>   #define MAX_MSI_HOST_IRQS		8
>   #define MAX_LEGACY_HOST_IRQS		4
>
> -/* RC mode settings masks */
> -#define PCIE_RC_MODE		BIT(2)
> -#define PCIE_MODE_MASK		(BIT(1) | BIT(2))
> -
>   /* DEV_STAT_CTRL */
>   #define PCIE_CAP_BASE		0x70
>
> @@ -355,7 +351,6 @@ static int __init ks_pcie_probe(struct platform_device *pdev)
>   	void __iomem *reg_p;
>   	struct phy *phy;
>   	int ret = 0;
> -	u32 val;
>
>   	ks_pcie = devm_kzalloc(&pdev->dev, sizeof(*ks_pcie),
>   				GFP_KERNEL);
> @@ -365,18 +360,6 @@ static int __init ks_pcie_probe(struct platform_device *pdev)
>   	}
>   	pp =&ks_pcie->pp;
>
> -	/* index 2 is the devcfg register for RC mode settings */
> -	res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
> -	reg_p = devm_ioremap_resource(dev, res);
> -	if (IS_ERR(reg_p))
> -		return PTR_ERR(reg_p);
> -
> -	/* enable RC mode in devcfg */
> -	val = readl(reg_p);
> -	val&= ~PCIE_MODE_MASK;
> -	val |= PCIE_RC_MODE;
> -	writel(val, reg_p);
> -
>   	/* initialize SerDes Phy if present */
>   	phy = devm_phy_get(dev, "pcie-phy");
>   	if (!IS_ERR_OR_NULL(phy)) {
> @@ -385,8 +368,8 @@ static int __init ks_pcie_probe(struct platform_device *pdev)
>   			return ret;
>   	}
>
> -	/* index 3 is to read PCI DEVICE_ID */
> -	res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
> +	/* index 2 is to read PCI DEVICE_ID */
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
>   	reg_p = devm_ioremap_resource(dev, res);
>   	if (IS_ERR(reg_p))
>   		return PTR_ERR(reg_p);
Bjorn,

These patches need to go onto host-keystone as well for v3.18. If you 
you have any comments, please let me know so that I can address them. I 
have incorporated comments from Arnd already.

Thanks.

Murali

Re: [PATCH v3 1/2] PCI: keystone: remove handle of PCI mode configuration

[Bjorn Helgaas]

On Wed, Sep 10, 2014 at 01:12:38PM -0400, Murali Karicheri wrote:
> Keystone PCI hardware supports both RC and EP modes and devcfg
> register has bits to boot strap the device to either of these modes.
> It seems proper to add this functionality to the boot loader rather
> than in the driver as device will be operating in either mode, not
> both any time. Currently the driver supports only RC mode and hence
> register configuration in the driver is not needed and driver can
> assume this is a RC hardware.
> 
> Also update the DT documentation accordingly.
> 
> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
> Acked-by: Arnd Bergmann <arnd@arndb.de>

Both applied to pci/host-keystone for v3.18, thanks!

> ---
> 	v3 - No change
> 	v2 - Added this separate patch to remove pci mode handling
>  .../devicetree/bindings/pci/pci-keystone.txt       |    4 +---
>  drivers/pci/host/pci-keystone.c                    |   21 ++------------------
>  2 files changed, 3 insertions(+), 22 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/pci-keystone.txt b/Documentation/devicetree/bindings/pci/pci-keystone.txt
> index ceb3e24..bedacf0 100644
> --- a/Documentation/devicetree/bindings/pci/pci-keystone.txt
> +++ b/Documentation/devicetree/bindings/pci/pci-keystone.txt
> @@ -13,9 +13,7 @@ Required Properties:-
>  
>  compatibility: "ti,keystone-pcie"
>  reg:	index 1 is the base address and length of DW application registers.
> -	index 2 is the base address and length of PCI mode configuration
> -	register.
> -	index 3 is the base address and length of PCI device ID register.
> +	index 2 is the base address and length of PCI device ID register.
>  
>  pcie_msi_intc : Interrupt controller device node for MSI IRQ chip
>  	interrupt-cells: should be set to 1
> diff --git a/drivers/pci/host/pci-keystone.c b/drivers/pci/host/pci-keystone.c
> index ff8ed25..f1119eb 100644
> --- a/drivers/pci/host/pci-keystone.c
> +++ b/drivers/pci/host/pci-keystone.c
> @@ -35,10 +35,6 @@
>  #define MAX_MSI_HOST_IRQS		8
>  #define MAX_LEGACY_HOST_IRQS		4
>  
> -/* RC mode settings masks */
> -#define PCIE_RC_MODE		BIT(2)
> -#define PCIE_MODE_MASK		(BIT(1) | BIT(2))
> -
>  /* DEV_STAT_CTRL */
>  #define PCIE_CAP_BASE		0x70
>  
> @@ -355,7 +351,6 @@ static int __init ks_pcie_probe(struct platform_device *pdev)
>  	void __iomem *reg_p;
>  	struct phy *phy;
>  	int ret = 0;
> -	u32 val;
>  
>  	ks_pcie = devm_kzalloc(&pdev->dev, sizeof(*ks_pcie),
>  				GFP_KERNEL);
> @@ -365,18 +360,6 @@ static int __init ks_pcie_probe(struct platform_device *pdev)
>  	}
>  	pp = &ks_pcie->pp;
>  
> -	/* index 2 is the devcfg register for RC mode settings */
> -	res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
> -	reg_p = devm_ioremap_resource(dev, res);
> -	if (IS_ERR(reg_p))
> -		return PTR_ERR(reg_p);
> -
> -	/* enable RC mode in devcfg */
> -	val = readl(reg_p);
> -	val &= ~PCIE_MODE_MASK;
> -	val |= PCIE_RC_MODE;
> -	writel(val, reg_p);
> -
>  	/* initialize SerDes Phy if present */
>  	phy = devm_phy_get(dev, "pcie-phy");
>  	if (!IS_ERR_OR_NULL(phy)) {
> @@ -385,8 +368,8 @@ static int __init ks_pcie_probe(struct platform_device *pdev)
>  			return ret;
>  	}
>  
> -	/* index 3 is to read PCI DEVICE_ID */
> -	res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
> +	/* index 2 is to read PCI DEVICE_ID */
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
>  	reg_p = devm_ioremap_resource(dev, res);
>  	if (IS_ERR(reg_p))
>  		return PTR_ERR(reg_p);
> -- 
> 1.7.9.5
>