Re: [tip:x86/apic] x86, irq: Use cached IOAPIC entry instead of reading from hardware

[Jiang Liu <jiang.liu@linux.intel.com>]

On 2014/11/28 19:53, Borislav Petkov wrote:
> On Fri, Nov 28, 2014 at 12:33:58PM +0100, Borislav Petkov wrote:
>> On Fri, Nov 28, 2014 at 10:31:44AM +0800, Jiang Liu wrote:
>>> 	Thanks for tracking down to this line of change. I have no
>>> platform to reproduce this bug, so could you please help to revert this
>>> commit and apply following patch to get some data about IOAPIC entry?
>>
>> Yep, the cached data differs from what's in the hw reg sometimes:
>>
>> dmesg | grep -i ioapic
>> [    0.000000] ACPI: IOAPIC (id[0x02] address[0xfec00000] gsi_base[0])
>> [    0.000000] IOAPIC[0]: apic_id 2, version 33, address 0xfec00000, GSI 0-23
>> [    0.429355] ioapic0 pin9, hardware reg a939, cached data 1a939
>> [    0.506249] ioapic0 pin9, hardware reg 1a939, cached data 1a939
>> [    0.521547] ACPI: Using IOAPIC for interrupt routing
>> [    1.313959] ioapic0 pin19, hardware reg a9c1, cached data 1a9c1
>> [    1.357875] ioapic0 pin12, hardware reg 93c, cached data 93c
>> [    1.359204] ioapic0 pin1, hardware reg 931, cached data 931
>> [    1.367423] ioapic0 pin8, hardware reg 938, cached data 938
>> [    7.560846] ioapic0 pin17, hardware reg a981, cached data 1a981
>> [    7.866814] ioapic0 pin18, hardware reg a9a1, cached data 1a9a1
>> [   10.141662] ioapic0 pin16, hardware reg a942, cached data 1a942
>>
>> This would explain the failure because the ahci ioapic pin19 has that
>> discrepancy:
>>
>> [    1.311476] ahci 0000:00:11.0: version 3.0
>> [    1.313374] ahci 0000:00:11.0: AHCI 0001.0200 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
>> [    1.313556] ahci 0000:00:11.0: flags: 64bit ncq sntf ilck pm led clo pmp pio slum part ccc 
>> [    1.313959] ioapic0 pin19, hardware reg a9c1, cached data 1a9c1
> 
> Ok, so this is interesting: the cached data has bit 16 set which,
> AFAICT, is in one of those io redirection table registers. That bit
> masks out interrupts and if set, those get ignored. Which would explain
> the timeoutting of the ATA commands because the IRQ is masked.
> 
> I don't know, though, why your cached data has bit 16 set....
Hi Borislav,
	Sorry, my previous test patch has some issue, but I think I
should have found the root cause now. Could you please try following
patch directly on top of tip/master without reverting any patch?
Thanks!
Gerry

diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index 5307320c08e6..ec193bc6712e 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -1885,7 +1885,7 @@ static int ioapic_set_affinity(struct irq_data
*irq_data,
        raw_spin_lock_irqsave(&ioapic_lock, flags);
        if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE) {
                cfg = irqd_cfg(irq_data);
-               data->entry.dest = SET_APIC_LOGICAL_ID(cfg->dest_apicid);
+               data->entry.dest = cfg->dest_apicid;
                data->entry.vector = cfg->vector;
                for_each_irq_pin(entry, data->irq_2_pin)
                        __ioapic_write_entry(entry->apic, entry->pin,

> 
> This is all a big IMHO of course...
>