From: Paolo Bonzini <pbonzini@redhat.com>
To: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>,
joro@8bytes.org, alex.williamson@redhat.com, gleb@kernel.org
Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
wei@redhat.com, sherry.hurwitz@amd.com
Subject: Re: [PART1 RFC 6/9] svm: Add interrupt injection via AVIC
Date: Fri, 12 Feb 2016 16:55:09 +0100 [thread overview]
Message-ID: <56BE005D.1040905@redhat.com> (raw)
In-Reply-To: <1455285574-27892-7-git-send-email-suravee.suthikulpanit@amd.com>
On 12/02/2016 14:59, Suravee Suthikulpanit wrote:
> +static bool avic_check_irr_pending(struct kvm_vcpu *vcpu)
> +{
> + int i;
> + u32 irr;
> + struct vcpu_svm *svm = to_svm(vcpu);
> +
> + for (i = 0; i < 8; i++) {
> + irr = *(avic_get_bk_page_entry(svm,
> + APIC_IRR + (0x10 * i)));
> + if (irr)
> + return true;
> + }
> +
> + return false;
> +}
> +
> +static bool svm_avic_check_ppr(struct vcpu_svm *svm)
> +{
> + u32 tpr = *(avic_get_bk_page_entry(svm, APIC_TASKPRI));
> + u32 ppr = *(avic_get_bk_page_entry(svm, APIC_PROCPRI));
> +
> + if (ppr && (ppr != tpr))
> + return true;
> +
> + return false;
> +}
> +
> +/* Note: Returns true means do not block */
> +static bool svm_apicv_intr_pending (struct kvm_vcpu *vcpu)
> +{
> + struct vcpu_svm *svm = to_svm(vcpu);
> +
> + if (!avic)
> + return false;
> +
> + if (atomic_read(&svm->avic_pending_cnt))
> + return true;
> +
> + return avic_check_irr_pending(vcpu);
> +}
> +
> +static void avic_post_vmrun(struct kvm_vcpu *vcpu)
> +{
> + struct vcpu_svm *svm = to_svm(vcpu);
> +
> + if (!avic)
> + return;
> +
> + if (atomic_read(&svm->avic_pending_cnt)) {
> + if (svm_avic_check_ppr(svm))
> + return;
> + if (avic_check_irr_pending(vcpu))
> + return;
> + /*
> + * At this point, if there is no interrupt pending.
> + * So, we decrement the pending count
> + */
> + atomic_dec(&svm->avic_pending_cnt);
> + }
> +}
> +
> static void svm_vcpu_run(struct kvm_vcpu *vcpu)
> {
> struct vcpu_svm *svm = to_svm(vcpu);
> @@ -4588,6 +4686,8 @@ static void svm_vcpu_run(struct kvm_vcpu *vcpu)
> if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
> kvm_after_handle_nmi(&svm->vcpu);
>
> + avic_post_vmrun(vcpu);
> +
> sync_cr8_to_lapic(vcpu);
>
> svm->next_rip = 0;
> @@ -5050,7 +5150,9 @@ static struct kvm_x86_ops svm_x86_ops = {
>
> .sched_in = svm_sched_in,
>
> + .apicv_intr_pending = svm_apicv_intr_pending,
> .pmu_ops = &amd_pmu_ops,
> + .deliver_posted_interrupt = svm_deliver_avic_intr,
> };
>
> static int __init svm_init(void)
> diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
> index 4244c2b..2def290 100644
> --- a/arch/x86/kvm/x86.c
> +++ b/arch/x86/kvm/x86.c
> @@ -8087,7 +8087,9 @@ int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
> if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
> kvm_x86_ops->check_nested_events(vcpu, false);
>
> - return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
> + return (kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu) ||
> + (kvm_x86_ops->apicv_intr_pending &&
> + kvm_x86_ops->apicv_intr_pending(vcpu)));
> }
I think this is not necessary. What you need is to make kvm_lapic's
regs field point to the backing page. Then when the processor writes to
IRR, kvm_apic_has_interrupt (called through kvm_vcpu_has_events) will
see it.
avic_pending_cnt shouldn't be necessary either.
Paolo
next prev parent reply other threads:[~2016-02-12 15:55 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-12 13:59 [PART1 RFC 0/9] KVM: x86: Introduce SVM AVIC support Suravee Suthikulpanit
2016-02-12 13:59 ` [PART1 RFC 1/9] KVM: x86: Misc LAPIC changes to exposes helper functions Suravee Suthikulpanit
2016-02-12 13:59 ` [PART1 RFC 2/9] svm: Introduce new AVIC VMCB registers Suravee Suthikulpanit
2016-02-12 13:59 ` [PART1 RFC 3/9] svm: clean up V_TPR, V_IRQ, V_INTR_PRIO, and V_INTR_MASKING Suravee Suthikulpanit
2016-02-12 13:59 ` [PART1 RFC 4/9] KVM: x86: Detect and Initialize AVIC support Suravee Suthikulpanit
2016-02-12 14:13 ` Borislav Petkov
2016-02-12 15:46 ` Suravee Suthikulpanit
2016-02-12 13:59 ` [PART1 RFC 5/9] svm: Add VMEXIT handlers for AVIC Suravee Suthikulpanit
2016-02-12 15:38 ` Paolo Bonzini
2016-02-15 19:22 ` Radim Krčmář
2016-02-16 6:29 ` Suravee Suthikulpanit
2016-02-16 12:15 ` Paolo Bonzini
2016-02-16 14:13 ` Radim Krčmář
2016-02-16 16:56 ` Paolo Bonzini
2016-02-16 18:06 ` Radim Krčmář
2016-02-18 2:25 ` Suravee Suthikulpanit
2016-02-18 14:18 ` Radim Krčmář
2016-02-18 14:51 ` Paolo Bonzini
2016-02-18 15:43 ` Radim Krčmář
2016-02-18 15:53 ` Paolo Bonzini
2016-02-18 16:27 ` Radim Krčmář
2016-02-18 17:18 ` Paolo Bonzini
2016-02-19 11:39 ` Suravee Suthikulpanit
2016-02-19 11:44 ` Paolo Bonzini
2016-02-19 11:59 ` Suravee Suthikulpanit
2016-03-03 10:42 ` Suravee Suthikulpanit
2016-03-03 10:50 ` Paolo Bonzini
2016-02-19 11:32 ` Suravee Suthikulpanit
2016-02-12 13:59 ` [PART1 RFC 6/9] svm: Add interrupt injection via AVIC Suravee Suthikulpanit
2016-02-12 14:16 ` Borislav Petkov
2016-02-12 15:54 ` Suravee Suthikulpanit
2016-02-12 17:14 ` Borislav Petkov
2016-02-12 18:21 ` Paolo Bonzini
2016-02-12 18:30 ` Borislav Petkov
2016-02-12 18:56 ` Paolo Bonzini
2016-02-12 19:33 ` Borislav Petkov
2016-02-16 7:50 ` Ingo Molnar
2016-02-16 8:39 ` [PATCH] x86/msr: Document msr-index.h rule for addition Borislav Petkov
2016-02-12 15:55 ` Paolo Bonzini [this message]
2016-02-12 16:21 ` [PART1 RFC 6/9] svm: Add interrupt injection via AVIC Suravee Suthikulpanit
2016-02-12 18:19 ` Paolo Bonzini
2016-02-12 19:36 ` Suravee Suthikulpanit
2016-02-19 11:57 ` Suravee Suthikulpanit
2016-02-12 13:59 ` [PART1 RFC 7/9] svm: Do not expose x2APIC when enable AVIC Suravee Suthikulpanit
2016-02-12 13:59 ` [PART1 RFC 8/9] svm: Do not intercept CR8 " Suravee Suthikulpanit
2016-02-12 15:48 ` Paolo Bonzini
2016-02-12 13:59 ` [PART1 RFC 9/9] svm: Manage vcpu load/unload " Suravee Suthikulpanit
2016-02-12 15:46 ` Paolo Bonzini
2016-02-12 18:13 ` [PART1 RFC 0/9] KVM: x86: Introduce SVM AVIC support Paolo Bonzini
2016-02-12 19:55 ` Suravee Suthikulpanit
2016-02-12 20:05 ` Paolo Bonzini
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