From: Aravind Gopalakrishnan <aravind.gopalakrishnan@amd.com>
To: Borislav Petkov <bp@alien8.de>
Cc: <tony.luck@intel.com>, <hpa@zytor.com>, <mingo@redhat.com>,
<tglx@linutronix.de>, <dougthompson@xmission.com>,
<mchehab@osg.samsung.com>, <x86@kernel.org>,
<linux-edac@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<ashok.raj@intel.com>, <gong.chen@linux.intel.com>,
<len.brown@intel.com>, <peterz@infradead.org>,
<ak@linux.intel.com>, <alexander.shishkin@linux.intel.com>
Subject: Re: [PATCH 4/4] x86/mce/AMD: Add comments for easier understanding
Date: Wed, 24 Feb 2016 12:26:44 -0600 [thread overview]
Message-ID: <56CDF5E4.4000206@amd.com> (raw)
In-Reply-To: <20160223123530.GB3673@pd.tnic>
On 2/23/2016 6:35 AM, Borislav Petkov wrote:
> On Tue, Feb 16, 2016 at 03:45:11PM -0600, Aravind Gopalakrishnan wrote:
>>
>> /*
>> + * Set the error_count and interrupt_enable sysfs attributes here.
>> + * This function gets called during the init phase and when someone
>> + * makes changes to either of the sysfs attributes.
>> + * During init phase, we also program Interrupt type as 'APIC' and
>> + * verify if LVT offset obtained from MCx_MISC is valid.
>> * Called via smp_call_function_single(), must be called with correct
>> * cpu affinity.
>> */
> I don't think that's what threshold_restart_bank() does...
Hmm, we call this from mce_threshold_block_init() with set_lvt_off = 1
to write LVT offset value to MCi_MISC.
And we call this from store_interrupt_enable() to program APIC INT TYPE-
if (tr->b->interrupt_enable)
hi |= INT_TYPE_APIC;
and from store_threshold_limit() to re-set the "error count"-
hi = (hi & ~MASK_ERR_COUNT_HI) |
(new_count & THRESHOLD_MAX);
So I thought it fit the description as to "what" it does..
> Also, that comment is too much - it shouldn't explain "what" but "why".
How about-
"This function provides user with capabilities to re-program the
'thresold_limit' and 'interrupt_enable' sysfs attributes"
>> @@ -262,6 +267,11 @@ static int setup_APIC_deferred_error(int reserved, int new)
>> return reserved;
>> }
>>
>> +/*
>> + * Obtain LVT offset from MSR_CU_DEF_ERR and call
>> + * setup_APIC_deferred_error() to program relevant APIC register.
>> + * Also, register a deferred error interrupt handler
>> + */
> No, that's basically spelling what the code does.
Ok, I'll remove this.
>> static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c)
>> {
>> u32 low = 0, high = 0;
>> @@ -338,6 +348,14 @@ nextaddr_out:
>> return addr;
>> }
>>
>> +/*
>> + * struct threshold_block descriptor tracks useful info regarding the
>> + * banks' MISC register. Among other things, it tracks whether interrupt
>> + * is possible for the given bank, the threshold limit and the sysfs object
>> + * that outputs these info.
> That should be in form of comments explaining what the members of struct
> threshold_block are, where that struct is defined.
Ok, I'll remove comments here and add it to arch/x86/include/asm/amd_nb.h
>> Initializing the struct here, programming
>> + * LVT offset for threshold interrupts and registering a interrupt handler
>> + * if we haven't already done so
> Also spelling the code.
Will remove this
Thanks,
-Aravind.
next prev parent reply other threads:[~2016-02-24 18:26 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-16 21:45 [PATCH 0/4] Updates to EDAC and AMD MCE driver Aravind Gopalakrishnan
2016-02-16 21:45 ` [PATCH 1/4] EDAC, MCE, AMD: Enable error decoding of Scalable MCA errors Aravind Gopalakrishnan
2016-02-23 12:37 ` Borislav Petkov
2016-02-23 22:50 ` Aravind Gopalakrishnan
2016-02-24 11:28 ` Borislav Petkov
2016-02-24 17:57 ` Aravind Gopalakrishnan
2016-02-16 21:45 ` [PATCH 2/4] x86/mce/AMD: Fix logic to obtain block address Aravind Gopalakrishnan
2016-02-18 15:38 ` Aravind Gopalakrishnan
2016-02-23 12:39 ` Borislav Petkov
2016-02-23 22:56 ` Aravind Gopalakrishnan
2016-02-24 11:33 ` Borislav Petkov
2016-02-24 18:02 ` Aravind Gopalakrishnan
2016-02-24 20:15 ` Boris Petkov
2016-02-16 21:45 ` [PATCH 3/4] x86/mce: Clarify comments regarding deferred error Aravind Gopalakrishnan
2016-02-23 12:11 ` Borislav Petkov
2016-02-23 23:02 ` Aravind Gopalakrishnan
2016-02-24 11:37 ` Borislav Petkov
2016-02-24 18:06 ` Aravind Gopalakrishnan
2016-02-24 20:13 ` Boris Petkov
2016-02-16 21:45 ` [PATCH 4/4] x86/mce/AMD: Add comments for easier understanding Aravind Gopalakrishnan
2016-02-23 12:35 ` Borislav Petkov
2016-02-24 18:26 ` Aravind Gopalakrishnan [this message]
2016-02-26 17:44 ` Borislav Petkov
2016-02-26 19:08 ` Aravind Gopalakrishnan
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