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From: William Wu <william.wu@rock-chips.com>
To: Felipe Balbi <balbi@kernel.org>,
	gregkh@linuxfoundation.org, heiko@sntech.de
Cc: briannorris@google.com, dianders@google.com,
	kever.yang@rock-chips.com, huangtao@rock-chips.com,
	frank.wang@rock-chips.com, eddie.cai@rock-chips.com,
	John.Youn@synopsys.com, linux-kernel@vger.kernel.org,
	linux-usb@vger.kernel.org
Subject: Re: [PATCH 3/4] usb: dwc3: make usb2 phy interface configurable in DT
Date: Mon, 09 May 2016 21:28:54 +0800	[thread overview]
Message-ID: <57309096.9010300@rock-chips.com> (raw)
In-Reply-To: <878tzj1l1o.fsf@intel.com>

On 05/09/2016 08:18 PM, Felipe Balbi wrote:
> Hi,
>
> William Wu <william.wu@rock-chips.com> writes:
>> Add snps,phyif_utmi_16_bits devicetree property. USB2 phy
> this needs a quirk_ prefix...
      Yes, maybe a quirk is more proper. As you mentioned,
      the PHYIf can be configured during coreconsultant.
      But for some specific usb cores(e.g. rk3399 soc dwc3),
      the default PHYIf configuration is error, so we need to
      reconfigure it by software.
>
>> interface is hardware property, and it's platform dependent,
>> so we need to configure it in devicetree to set the core to
>> support a UTMI+ PHY with an 8- or 16-bit interface.
>>
>> And refer to the dwc3 databook, the GUSB2PHYCFG.USBTRDTIM
>> must set to the corresponding value according to the usb2
>> phy interface.
> right, that's fine. But also note on section 8.1.1 Table 8-1 where it
> states:
>
> |-------------+------------------------------------------------------------|
> | GUSB2PHYCFG | Program the following PHY configuration fields: USBTrdTim, |
> |             | FSIntf, PHYIf, TOUTCal, or leave the default values if     |
> |             | the correct power-on values were selected during           |
> |             | coreConsultant configuration.  Note: The PHY must not      |
> |             | be enabled for auto-resume in device mode. Hence the       |
> |             | field GUSB2PHYCFG[15] (ULPIAutoRes) must be written        |
> |             | with '0' during the power-on initialization in case        |
> |             | the reset value is '1'.                                    |
> |             |                                                            |
> |-------------+------------------------------------------------------------|
>
> You only need this because your core was badly configured in
> coreConsultant.
>

  reply	other threads:[~2016-05-09 13:29 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-05-09 11:46 [PATCH 0/4] support rockchip dwc3 driver William Wu
2016-05-09 11:46 ` [PATCH 1/4] usb: dwc3: of-simple: add compatible for rockchip William Wu
2016-05-09 15:16   ` Doug Anderson
2016-05-10  7:14     ` Felipe Balbi
2016-05-10  7:39       ` William Wu
2016-05-10  8:11         ` Felipe Balbi
2016-05-10  8:27           ` William Wu
2016-05-09 19:24   ` Brian Norris
2016-05-10  7:15     ` Felipe Balbi
2016-05-10  8:14       ` William Wu
2016-05-09 11:46 ` [PATCH 2/4] usb: dwc3: add dis_u2_freeclk_exists_quirk William Wu
2016-05-09 11:46 ` [PATCH 3/4] usb: dwc3: make usb2 phy interface configurable in DT William Wu
2016-05-09 12:18   ` Felipe Balbi
2016-05-09 13:28     ` William Wu [this message]
2016-05-09 13:32       ` Felipe Balbi
2016-05-09 11:46 ` [PATCH 4/4] usb: dwc3: add dis_del_phy_power_chg_quirk William Wu
2016-05-13  9:24 ` [PATCH v2 0/5] support rockchip dwc3 driver William Wu
2016-05-13  9:24   ` [PATCH v2 1/5] usb: dwc3: of-simple: add compatible for rockchip William Wu
2016-05-13  9:24   ` [PATCH v2 2/5] usb: dwc3: add dis_u2_freeclk_exists_quirk William Wu
2016-05-13  9:24   ` [PATCH v2 3/5] usb: dwc3: add phyif_utmi_quirk William Wu
2016-05-13  9:25   ` [PATCH v2 4/5] usb: dwc3: add dis_del_phy_power_chg_quirk William Wu
2016-05-13  9:30   ` [PATCH v2 0/5] support rockchip dwc3 driver Heiko Stuebner
2016-05-13  9:37   ` Felipe Balbi
2016-05-13  9:48     ` William Wu

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