[PATCH 0/3] External Interrupt Controller (EIC) fixes

[PATCH 0/3] External Interrupt Controller (EIC) fixes

[Paul Burton]

This series fixes a few small issues with support for External Interrupt
Controllers (cpu_has_veic), ensuring that it is configured to service
all interrupts by default & that when a GIC is present it's enabled when
expected.

Applies atop v4.6.

Paul Burton (3):
  MIPS: Clear Status IPL field when using EIC
  MIPS: smp-cps: Clear Status IPL field when using EIC
  irqchip: mips-gic: Setup EIC mode on each CPU if it's in use

 arch/mips/kernel/irq.c         |  3 +++
 arch/mips/kernel/smp-cps.c     |  8 ++++++--
 drivers/irqchip/irq-mips-gic.c | 10 +++++++++-
 3 files changed, 18 insertions(+), 3 deletions(-)

-- 
2.8.2

[PATCH 1/3] MIPS: Clear Status IPL field when using EIC

[Paul Burton]

When using an external interrupt controller (EIC) the interrupt mask
bits in the cop0 Status register are reused for the Interrupt Priority
Level, and any interrupts with a priority lower than the field will be
ignored. Clear the field to 0 by default such that all interrupts are
serviced. Without doing so we default to arbitrarily ignoring all or
some subset of interrupts.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 arch/mips/kernel/irq.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
index 8eb5af8..f25f7ea 100644
--- a/arch/mips/kernel/irq.c
+++ b/arch/mips/kernel/irq.c
@@ -54,6 +54,9 @@ void __init init_IRQ(void)
 	for (i = 0; i < NR_IRQS; i++)
 		irq_set_noprobe(i);
 
+	if (cpu_has_veic)
+		clear_c0_status(ST0_IM);
+
 	arch_init_irq();
 }
 
-- 
2.8.2

[PATCH 2/3] MIPS: smp-cps: Clear Status IPL field when using EIC

[Paul Burton]

When using an external interrupt controller (EIC) the interrupt mask
bits in the cop0 Status register are reused for the Interrupt Priority
Level, and any interrupts with a priority lower than the field will be
ignored. Clear the field to 0 by default such that all interrupts are
serviced.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 arch/mips/kernel/smp-cps.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
index 253e140..f19f0d3 100644
--- a/arch/mips/kernel/smp-cps.c
+++ b/arch/mips/kernel/smp-cps.c
@@ -307,8 +307,12 @@ static void cps_init_secondary(void)
 	if (cpu_has_mipsmt)
 		dmt();
 
-	change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 |
-				 STATUSF_IP5 | STATUSF_IP6 | STATUSF_IP7);
+	if (cpu_has_veic)
+		clear_c0_status(ST0_IM);
+	else
+		change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 |
+					 STATUSF_IP4 | STATUSF_IP5 |
+					 STATUSF_IP6 | STATUSF_IP7);
 }
 
 static void cps_smp_finish(void)
-- 
2.8.2

[PATCH 3/3] irqchip: mips-gic: Setup EIC mode on each CPU if it's in use

[Paul Burton]

When EIC mode is in use (cpu_has_veic is true) enable it on each CPU
during GIC initialisation. Otherwise there may be a mismatch between the
hardware default interrupt model & that expected by the kernel.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 drivers/irqchip/irq-mips-gic.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index 4dffccf..bc23c92 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -956,7 +956,7 @@ static void __init __gic_init(unsigned long gic_base_addr,
 			      unsigned int cpu_vec, unsigned int irqbase,
 			      struct device_node *node)
 {
-	unsigned int gicconfig;
+	unsigned int gicconfig, cpu;
 	unsigned int v[2];
 
 	__gic_base_addr = gic_base_addr;
@@ -973,6 +973,14 @@ static void __init __gic_init(unsigned long gic_base_addr,
 	gic_vpes = gic_vpes + 1;
 
 	if (cpu_has_veic) {
+		/* Set EIC mode for all VPEs */
+		for_each_present_cpu(cpu) {
+			gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR),
+				  mips_cm_vp_id(cpu));
+			gic_write(GIC_REG(VPE_OTHER, GIC_VPE_CTL),
+				  GIC_VPE_CTL_EIC_MODE_MSK);
+		}
+
 		/* Always use vector 1 in EIC mode */
 		gic_cpu_pin = 0;
 		timer_cpu_pin = gic_cpu_pin;
-- 
2.8.2

Re: [PATCH 1/3] MIPS: Clear Status IPL field when using EIC

[Matt Redfearn]

On 17/05/16 15:31, Paul Burton wrote:
> When using an external interrupt controller (EIC) the interrupt mask
> bits in the cop0 Status register are reused for the Interrupt Priority
> Level, and any interrupts with a priority lower than the field will be
> ignored. Clear the field to 0 by default such that all interrupts are
> serviced. Without doing so we default to arbitrarily ignoring all or
> some subset of interrupts.
>
> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
> ---
>
>   arch/mips/kernel/irq.c | 3 +++
>   1 file changed, 3 insertions(+)
>
> diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
> index 8eb5af8..f25f7ea 100644
> --- a/arch/mips/kernel/irq.c
> +++ b/arch/mips/kernel/irq.c
> @@ -54,6 +54,9 @@ void __init init_IRQ(void)
>   	for (i = 0; i < NR_IRQS; i++)
>   		irq_set_noprobe(i);
>   
> +	if (cpu_has_veic)
> +		clear_c0_status(ST0_IM);
> +
>   	arch_init_irq();
>   }
>   
Hi Paul

Reviewed-by: Matt Redfearn <matt.redfearn@imgtec.com>
Tested-by: Matt Redfearn <matt.redfearn@imgtec.com>

Re: [PATCH 2/3] MIPS: smp-cps: Clear Status IPL field when using EIC

[Matt Redfearn]

On 17/05/16 15:31, Paul Burton wrote:
> When using an external interrupt controller (EIC) the interrupt mask
> bits in the cop0 Status register are reused for the Interrupt Priority
> Level, and any interrupts with a priority lower than the field will be
> ignored. Clear the field to 0 by default such that all interrupts are
> serviced.
>
> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
> ---
>
>   arch/mips/kernel/smp-cps.c | 8 ++++++--
>   1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
> index 253e140..f19f0d3 100644
> --- a/arch/mips/kernel/smp-cps.c
> +++ b/arch/mips/kernel/smp-cps.c
> @@ -307,8 +307,12 @@ static void cps_init_secondary(void)
>   	if (cpu_has_mipsmt)
>   		dmt();
>   
> -	change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 |
> -				 STATUSF_IP5 | STATUSF_IP6 | STATUSF_IP7);
> +	if (cpu_has_veic)
> +		clear_c0_status(ST0_IM);
> +	else
> +		change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 |
> +					 STATUSF_IP4 | STATUSF_IP5 |
> +					 STATUSF_IP6 | STATUSF_IP7);
>   }
>   
>   static void cps_smp_finish(void)
Hi Paul

Reviewed-by: Matt Redfearn <matt.redfearn@imgtec.com>
Tested-by: Matt Redfearn <matt.redfearn@imgtec.com>

Thanks,
Matt

Re: [PATCH 3/3] irqchip: mips-gic: Setup EIC mode on each CPU if it's in use

[Matt Redfearn]

On 17/05/16 15:31, Paul Burton wrote:
> When EIC mode is in use (cpu_has_veic is true) enable it on each CPU
> during GIC initialisation. Otherwise there may be a mismatch between the
> hardware default interrupt model & that expected by the kernel.
>
> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
> ---
>
>   drivers/irqchip/irq-mips-gic.c | 10 +++++++++-
>   1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
> index 4dffccf..bc23c92 100644
> --- a/drivers/irqchip/irq-mips-gic.c
> +++ b/drivers/irqchip/irq-mips-gic.c
> @@ -956,7 +956,7 @@ static void __init __gic_init(unsigned long gic_base_addr,
>   			      unsigned int cpu_vec, unsigned int irqbase,
>   			      struct device_node *node)
>   {
> -	unsigned int gicconfig;
> +	unsigned int gicconfig, cpu;
>   	unsigned int v[2];
>   
>   	__gic_base_addr = gic_base_addr;
> @@ -973,6 +973,14 @@ static void __init __gic_init(unsigned long gic_base_addr,
>   	gic_vpes = gic_vpes + 1;
>   
>   	if (cpu_has_veic) {
> +		/* Set EIC mode for all VPEs */
> +		for_each_present_cpu(cpu) {
> +			gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR),
> +				  mips_cm_vp_id(cpu));
> +			gic_write(GIC_REG(VPE_OTHER, GIC_VPE_CTL),
> +				  GIC_VPE_CTL_EIC_MODE_MSK);
> +		}
> +
>   		/* Always use vector 1 in EIC mode */
>   		gic_cpu_pin = 0;
>   		timer_cpu_pin = gic_cpu_pin;
Hi Paul

Reviewed-by: Matt Redfearn <matt.redfearn@imgtec.com>
Tested-by: Matt Redfearn <matt.redfearn@imgtec.com>

Thanks,
Matt

Re: [PATCH 0/3] External Interrupt Controller (EIC) fixes

[Thomas Gleixner]

On Tue, 17 May 2016, Paul Burton wrote:

> This series fixes a few small issues with support for External Interrupt
> Controllers (cpu_has_veic), ensuring that it is configured to service
> all interrupts by default & that when a GIC is present it's enabled when
> expected.
> 
> Applies atop v4.6.
> 
> Paul Burton (3):
>   MIPS: Clear Status IPL field when using EIC
>   MIPS: smp-cps: Clear Status IPL field when using EIC
>   irqchip: mips-gic: Setup EIC mode on each CPU if it's in use

I was not on CC for patch 1/3 and I assume this should go through one
tree. Ralf, can you pick that up with my acked-by for the irqchip change?

Thanks,

	tglx

Re: [PATCH 0/3] External Interrupt Controller (EIC) fixes

[Ralf Baechle]

On Thu, May 19, 2016 at 11:21:22AM +0200, Thomas Gleixner wrote:

> On Tue, 17 May 2016, Paul Burton wrote:
> 
> > This series fixes a few small issues with support for External Interrupt
> > Controllers (cpu_has_veic), ensuring that it is configured to service
> > all interrupts by default & that when a GIC is present it's enabled when
> > expected.
> > 
> > Applies atop v4.6.
> > 
> > Paul Burton (3):
> >   MIPS: Clear Status IPL field when using EIC
> >   MIPS: smp-cps: Clear Status IPL field when using EIC
> >   irqchip: mips-gic: Setup EIC mode on each CPU if it's in use
> 
> I was not on CC for patch 1/3 and I assume this should go through one
> tree. Ralf, can you pick that up with my acked-by for the irqchip change?

Yes, will do.

Thanks!

  Ralf