From: Marc Zyngier <marc.zyngier@arm.com>
To: Sudeep Holla <sudeep.holla@arm.com>, linux-kernel@vger.kernel.org
Cc: Christopher Covington <cov@codeaurora.org>,
Prashanth Prakash <pprakash@codeaurora.org>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>
Subject: Re: [PATCH v2] irqchip/gicv3: remove disabling redistributor and group1 non-secure interrupts
Date: Wed, 17 Aug 2016 14:02:43 +0100 [thread overview]
Message-ID: <57B46073.8090800@arm.com> (raw)
In-Reply-To: <1471438159-29992-1-git-send-email-sudeep.holla@arm.com>
On 17/08/16 13:49, Sudeep Holla wrote:
> As per the GICv3 specification, to power down a processor using GICv3
> and allow automatic power-on if an interrupt must be sent to a processor,
> software must set Enable to zero for all interrupt groups(by writing
> to GICC_CTLR or ICC_IGRPEN{0,1}_EL1/3 as appropriate.
>
> When commit 3708d52fc6bb ("irqchip: gic-v3: Implement CPU PM notifier")
> was introduced there were no firmware implementations(in particular PSCI)
> handling this.
>
> Linux kernel may not be aware of the CPU power state details and might
> fail to identify the power states that require quiescing the CPU
> interface. Even if it can be aware of those details, it can't determine
> which CPU power state have been triggered at the platform level and how
> the power control is implemented.
>
> This patch make disabling redistributor and group1 non-secure interrupts
> in the power down path and re-enabling of redistributor in the power-up
> path conditional. It will be handled in the kernel if and only if the
> non-secure accesses are permitted to access and modify control registers.
> It is left to the platform implementation otherwise.
>
> Cc: Marc Zyngier <marc.zyngier@arm.com>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Jason Cooper <jason@lakedaemon.net>
> Tested-by: Christopher Covington <cov@codeaurora.org>
> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
> ---
> drivers/irqchip/irq-gic-v3.c | 11 +++++++++--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> v1->v2:
> - Moved gic_dist_security_disabled inside CONFIG_CPU_PM to fix
> the build warning triggered otherwise.
>
> Hi Marc,
>
> Consider this as a fix for v4.8 as it fixes CPUIdle related boot hang on
> Qualcomm QDF2432 platform.
Applied, thanks.
M.
--
Jazz is not dead. It just smells funny...
prev parent reply other threads:[~2016-08-17 13:03 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-16 10:19 [PATCH] irqchip/gicv3: remove disabling redistributor and group1 non-secure interrupts Sudeep Holla
2016-08-16 19:21 ` Christopher Covington
2016-08-17 12:39 ` Sudeep Holla
2016-08-17 12:49 ` [PATCH v2] " Sudeep Holla
2016-08-17 13:02 ` Marc Zyngier [this message]
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