* [PATCH] mfd: da8xx-cfgchip: New header file for CFGCHIP registers
@ 2016-08-10 13:19 Kishon Vijay Abraham I
2016-08-30 14:22 ` Lee Jones
0 siblings, 1 reply; 5+ messages in thread
From: Kishon Vijay Abraham I @ 2016-08-10 13:19 UTC (permalink / raw)
To: kishon, david; +Cc: linux-kernel
From: David Lechner <david@lechnology.com>
Create a new header file for TI DA8XX SoC CFGCHIPx registers.
This will be used by a number of planned drivers including a new USB
PHY driver and common clock framework drivers.
The same defines *will* be removed from the platform_data header,
once all the users start using the new syscon device header.
This also fixes the following compiler error caused due to
a dependent patch not merged.
drivers/phy/phy-da8xx-usb.c:19:37:
fatal error: linux/mfd/da8xx-cfgchip.h: No such file or directory
#include <linux/mfd/da8xx-cfgchip.h>
Signed-off-by: David Lechner <david@lechnology.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Reported-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
include/linux/mfd/da8xx-cfgchip.h | 153 +++++++++++++++++++++++++++++++++++++
1 file changed, 153 insertions(+)
create mode 100644 include/linux/mfd/da8xx-cfgchip.h
diff --git a/include/linux/mfd/da8xx-cfgchip.h b/include/linux/mfd/da8xx-cfgchip.h
new file mode 100644
index 0000000..304985e
--- /dev/null
+++ b/include/linux/mfd/da8xx-cfgchip.h
@@ -0,0 +1,153 @@
+/*
+ * TI DaVinci DA8xx CHIPCFGx registers for syscon consumers.
+ *
+ * Copyright (C) 2016 David Lechner <david@lechnology.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __LINUX_MFD_DA8XX_CFGCHIP_H
+#define __LINUX_MFD_DA8XX_CFGCHIP_H
+
+#include <linux/bitops.h>
+
+/* register offset (32-bit registers) */
+#define CFGCHIP(n) ((n) * 4)
+
+/* CFGCHIP0 (PLL0/EDMA3_0) register bits */
+#define CFGCHIP0_PLL_MASTER_LOCK BIT(4)
+#define CFGCHIP0_EDMA30TC1DBS(n) ((n) << 2)
+#define CFGCHIP0_EDMA30TC1DBS_MASK CFGCHIP0_EDMA30TC1DBS(0x3)
+#define CFGCHIP0_EDMA30TC1DBS_16 CFGCHIP0_EDMA30TC1DBS(0x0)
+#define CFGCHIP0_EDMA30TC1DBS_32 CFGCHIP0_EDMA30TC1DBS(0x1)
+#define CFGCHIP0_EDMA30TC1DBS_64 CFGCHIP0_EDMA30TC1DBS(0x2)
+#define CFGCHIP0_EDMA30TC0DBS(n) ((n) << 0)
+#define CFGCHIP0_EDMA30TC0DBS_MASK CFGCHIP0_EDMA30TC0DBS(0x3)
+#define CFGCHIP0_EDMA30TC0DBS_16 CFGCHIP0_EDMA30TC0DBS(0x0)
+#define CFGCHIP0_EDMA30TC0DBS_32 CFGCHIP0_EDMA30TC0DBS(0x1)
+#define CFGCHIP0_EDMA30TC0DBS_64 CFGCHIP0_EDMA30TC0DBS(0x2)
+
+/* CFGCHIP1 (eCAP/HPI/EDMA3_1/eHRPWM TBCLK/McASP0 AMUTEIN) register bits */
+#define CFGCHIP1_CAP2SRC(n) ((n) << 27)
+#define CFGCHIP1_CAP2SRC_MASK CFGCHIP1_CAP2SRC(0x1f)
+#define CFGCHIP1_CAP2SRC_ECAP_PIN CFGCHIP1_CAP2SRC(0x0)
+#define CFGCHIP1_CAP2SRC_MCASP0_TX CFGCHIP1_CAP2SRC(0x1)
+#define CFGCHIP1_CAP2SRC_MCASP0_RX CFGCHIP1_CAP2SRC(0x2)
+#define CFGCHIP1_CAP2SRC_EMAC_C0_RX_THRESHOLD CFGCHIP1_CAP2SRC(0x7)
+#define CFGCHIP1_CAP2SRC_EMAC_C0_RX CFGCHIP1_CAP2SRC(0x8)
+#define CFGCHIP1_CAP2SRC_EMAC_C0_TX CFGCHIP1_CAP2SRC(0x9)
+#define CFGCHIP1_CAP2SRC_EMAC_C0_MISC CFGCHIP1_CAP2SRC(0xa)
+#define CFGCHIP1_CAP2SRC_EMAC_C1_RX_THRESHOLD CFGCHIP1_CAP2SRC(0xb)
+#define CFGCHIP1_CAP2SRC_EMAC_C1_RX CFGCHIP1_CAP2SRC(0xc)
+#define CFGCHIP1_CAP2SRC_EMAC_C1_TX CFGCHIP1_CAP2SRC(0xd)
+#define CFGCHIP1_CAP2SRC_EMAC_C1_MISC CFGCHIP1_CAP2SRC(0xe)
+#define CFGCHIP1_CAP2SRC_EMAC_C2_RX_THRESHOLD CFGCHIP1_CAP2SRC(0xf)
+#define CFGCHIP1_CAP2SRC_EMAC_C2_RX CFGCHIP1_CAP2SRC(0x10)
+#define CFGCHIP1_CAP2SRC_EMAC_C2_TX CFGCHIP1_CAP2SRC(0x11)
+#define CFGCHIP1_CAP2SRC_EMAC_C2_MISC CFGCHIP1_CAP2SRC(0x12)
+#define CFGCHIP1_CAP1SRC(n) ((n) << 22)
+#define CFGCHIP1_CAP1SRC_MASK CFGCHIP1_CAP1SRC(0x1f)
+#define CFGCHIP1_CAP1SRC_ECAP_PIN CFGCHIP1_CAP1SRC(0x0)
+#define CFGCHIP1_CAP1SRC_MCASP0_TX CFGCHIP1_CAP1SRC(0x1)
+#define CFGCHIP1_CAP1SRC_MCASP0_RX CFGCHIP1_CAP1SRC(0x2)
+#define CFGCHIP1_CAP1SRC_EMAC_C0_RX_THRESHOLD CFGCHIP1_CAP1SRC(0x7)
+#define CFGCHIP1_CAP1SRC_EMAC_C0_RX CFGCHIP1_CAP1SRC(0x8)
+#define CFGCHIP1_CAP1SRC_EMAC_C0_TX CFGCHIP1_CAP1SRC(0x9)
+#define CFGCHIP1_CAP1SRC_EMAC_C0_MISC CFGCHIP1_CAP1SRC(0xa)
+#define CFGCHIP1_CAP1SRC_EMAC_C1_RX_THRESHOLD CFGCHIP1_CAP1SRC(0xb)
+#define CFGCHIP1_CAP1SRC_EMAC_C1_RX CFGCHIP1_CAP1SRC(0xc)
+#define CFGCHIP1_CAP1SRC_EMAC_C1_TX CFGCHIP1_CAP1SRC(0xd)
+#define CFGCHIP1_CAP1SRC_EMAC_C1_MISC CFGCHIP1_CAP1SRC(0xe)
+#define CFGCHIP1_CAP1SRC_EMAC_C2_RX_THRESHOLD CFGCHIP1_CAP1SRC(0xf)
+#define CFGCHIP1_CAP1SRC_EMAC_C2_RX CFGCHIP1_CAP1SRC(0x10)
+#define CFGCHIP1_CAP1SRC_EMAC_C2_TX CFGCHIP1_CAP1SRC(0x11)
+#define CFGCHIP1_CAP1SRC_EMAC_C2_MISC CFGCHIP1_CAP1SRC(0x12)
+#define CFGCHIP1_CAP0SRC(n) ((n) << 17)
+#define CFGCHIP1_CAP0SRC_MASK CFGCHIP1_CAP0SRC(0x1f)
+#define CFGCHIP1_CAP0SRC_ECAP_PIN CFGCHIP1_CAP0SRC(0x0)
+#define CFGCHIP1_CAP0SRC_MCASP0_TX CFGCHIP1_CAP0SRC(0x1)
+#define CFGCHIP1_CAP0SRC_MCASP0_RX CFGCHIP1_CAP0SRC(0x2)
+#define CFGCHIP1_CAP0SRC_EMAC_C0_RX_THRESHOLD CFGCHIP1_CAP0SRC(0x7)
+#define CFGCHIP1_CAP0SRC_EMAC_C0_RX CFGCHIP1_CAP0SRC(0x8)
+#define CFGCHIP1_CAP0SRC_EMAC_C0_TX CFGCHIP1_CAP0SRC(0x9)
+#define CFGCHIP1_CAP0SRC_EMAC_C0_MISC CFGCHIP1_CAP0SRC(0xa)
+#define CFGCHIP1_CAP0SRC_EMAC_C1_RX_THRESHOLD CFGCHIP1_CAP0SRC(0xb)
+#define CFGCHIP1_CAP0SRC_EMAC_C1_RX CFGCHIP1_CAP0SRC(0xc)
+#define CFGCHIP1_CAP0SRC_EMAC_C1_TX CFGCHIP1_CAP0SRC(0xd)
+#define CFGCHIP1_CAP0SRC_EMAC_C1_MISC CFGCHIP1_CAP0SRC(0xe)
+#define CFGCHIP1_CAP0SRC_EMAC_C2_RX_THRESHOLD CFGCHIP1_CAP0SRC(0xf)
+#define CFGCHIP1_CAP0SRC_EMAC_C2_RX CFGCHIP1_CAP0SRC(0x10)
+#define CFGCHIP1_CAP0SRC_EMAC_C2_TX CFGCHIP1_CAP0SRC(0x11)
+#define CFGCHIP1_CAP0SRC_EMAC_C2_MISC CFGCHIP1_CAP0SRC(0x12)
+#define CFGCHIP1_HPIBYTEAD BIT(16)
+#define CFGCHIP1_HPIENA BIT(15)
+#define CFGCHIP0_EDMA31TC0DBS(n) ((n) << 13)
+#define CFGCHIP0_EDMA31TC0DBS_MASK CFGCHIP0_EDMA31TC0DBS(0x3)
+#define CFGCHIP0_EDMA31TC0DBS_16 CFGCHIP0_EDMA31TC0DBS(0x0)
+#define CFGCHIP0_EDMA31TC0DBS_32 CFGCHIP0_EDMA31TC0DBS(0x1)
+#define CFGCHIP0_EDMA31TC0DBS_64 CFGCHIP0_EDMA31TC0DBS(0x2)
+#define CFGCHIP1_TBCLKSYNC BIT(12)
+#define CFGCHIP1_AMUTESEL0(n) ((n) << 0)
+#define CFGCHIP1_AMUTESEL0_MASK CFGCHIP1_AMUTESEL0(0xf)
+#define CFGCHIP1_AMUTESEL0_LOW CFGCHIP1_AMUTESEL0(0x0)
+#define CFGCHIP1_AMUTESEL0_BANK_0 CFGCHIP1_AMUTESEL0(0x1)
+#define CFGCHIP1_AMUTESEL0_BANK_1 CFGCHIP1_AMUTESEL0(0x2)
+#define CFGCHIP1_AMUTESEL0_BANK_2 CFGCHIP1_AMUTESEL0(0x3)
+#define CFGCHIP1_AMUTESEL0_BANK_3 CFGCHIP1_AMUTESEL0(0x4)
+#define CFGCHIP1_AMUTESEL0_BANK_4 CFGCHIP1_AMUTESEL0(0x5)
+#define CFGCHIP1_AMUTESEL0_BANK_5 CFGCHIP1_AMUTESEL0(0x6)
+#define CFGCHIP1_AMUTESEL0_BANK_6 CFGCHIP1_AMUTESEL0(0x7)
+#define CFGCHIP1_AMUTESEL0_BANK_7 CFGCHIP1_AMUTESEL0(0x8)
+
+/* CFGCHIP2 (USB PHY) register bits */
+#define CFGCHIP2_PHYCLKGD BIT(17)
+#define CFGCHIP2_VBUSSENSE BIT(16)
+#define CFGCHIP2_RESET BIT(15)
+#define CFGCHIP2_OTGMODE(n) ((n) << 13)
+#define CFGCHIP2_OTGMODE_MASK CFGCHIP2_OTGMODE(0x3)
+#define CFGCHIP2_OTGMODE_NO_OVERRIDE CFGCHIP2_OTGMODE(0x0)
+#define CFGCHIP2_OTGMODE_FORCE_HOST CFGCHIP2_OTGMODE(0x1)
+#define CFGCHIP2_OTGMODE_FORCE_DEVICE CFGCHIP2_OTGMODE(0x2)
+#define CFGCHIP2_OTGMODE_FORCE_HOST_VBUS_LOW CFGCHIP2_OTGMODE(0x3)
+#define CFGCHIP2_USB1PHYCLKMUX BIT(12)
+#define CFGCHIP2_USB2PHYCLKMUX BIT(11)
+#define CFGCHIP2_PHYPWRDN BIT(10)
+#define CFGCHIP2_OTGPWRDN BIT(9)
+#define CFGCHIP2_DATPOL BIT(8)
+#define CFGCHIP2_USB1SUSPENDM BIT(7)
+#define CFGCHIP2_PHY_PLLON BIT(6)
+#define CFGCHIP2_SESENDEN BIT(5)
+#define CFGCHIP2_VBDTCTEN BIT(4)
+#define CFGCHIP2_REFFREQ(n) ((n) << 0)
+#define CFGCHIP2_REFFREQ_MASK CFGCHIP2_REFFREQ(0xf)
+#define CFGCHIP2_REFFREQ_12MHZ CFGCHIP2_REFFREQ(0x1)
+#define CFGCHIP2_REFFREQ_24MHZ CFGCHIP2_REFFREQ(0x2)
+#define CFGCHIP2_REFFREQ_48MHZ CFGCHIP2_REFFREQ(0x3)
+#define CFGCHIP2_REFFREQ_19_2MHZ CFGCHIP2_REFFREQ(0x4)
+#define CFGCHIP2_REFFREQ_38_4MHZ CFGCHIP2_REFFREQ(0x5)
+#define CFGCHIP2_REFFREQ_13MHZ CFGCHIP2_REFFREQ(0x6)
+#define CFGCHIP2_REFFREQ_26MHZ CFGCHIP2_REFFREQ(0x7)
+#define CFGCHIP2_REFFREQ_20MHZ CFGCHIP2_REFFREQ(0x8)
+#define CFGCHIP2_REFFREQ_40MHZ CFGCHIP2_REFFREQ(0x9)
+
+/* CFGCHIP3 (EMAC/uPP/PLL1/ASYNC3/PRU/DIV4.5/EMIFA) register bits */
+#define CFGCHIP3_RMII_SEL BIT(8)
+#define CFGCHIP3_UPP_TX_CLKSRC BIT(6)
+#define CFGCHIP3_PLL1_MASTER_LOCK BIT(5)
+#define CFGCHIP3_ASYNC3_CLKSRC BIT(4)
+#define CFGCHIP3_PRUEVTSEL BIT(3)
+#define CFGCHIP3_DIV45PENA BIT(2)
+#define CFGCHIP3_EMA_CLKSRC BIT(1)
+
+/* CFGCHIP4 (McASP0 AMUNTEIN) register bits */
+#define CFGCHIP4_AMUTECLR0 BIT(0)
+
+#endif /* __LINUX_MFD_DA8XX_CFGCHIP_H */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] mfd: da8xx-cfgchip: New header file for CFGCHIP registers
2016-08-10 13:19 [PATCH] mfd: da8xx-cfgchip: New header file for CFGCHIP registers Kishon Vijay Abraham I
@ 2016-08-30 14:22 ` Lee Jones
2016-08-30 14:24 ` Kishon Vijay Abraham I
0 siblings, 1 reply; 5+ messages in thread
From: Lee Jones @ 2016-08-30 14:22 UTC (permalink / raw)
To: Kishon Vijay Abraham I; +Cc: david, linux-kernel
On Wed, 10 Aug 2016, Kishon Vijay Abraham I wrote:
> From: David Lechner <david@lechnology.com>
>
> Create a new header file for TI DA8XX SoC CFGCHIPx registers.
> This will be used by a number of planned drivers including a new USB
> PHY driver and common clock framework drivers.
>
> The same defines *will* be removed from the platform_data header,
> once all the users start using the new syscon device header.
>
> This also fixes the following compiler error caused due to
> a dependent patch not merged.
> drivers/phy/phy-da8xx-usb.c:19:37:
> fatal error: linux/mfd/da8xx-cfgchip.h: No such file or directory
> #include <linux/mfd/da8xx-cfgchip.h>
>
> Signed-off-by: David Lechner <david@lechnology.com>
> Acked-by: Lee Jones <lee.jones@linaro.org>
> Reported-by: Arnd Bergmann <arnd@arndb.de>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> include/linux/mfd/da8xx-cfgchip.h | 153 +++++++++++++++++++++++++++++++++++++
> 1 file changed, 153 insertions(+)
Applied, thanks.
> diff --git a/include/linux/mfd/da8xx-cfgchip.h b/include/linux/mfd/da8xx-cfgchip.h
> new file mode 100644
> index 0000000..304985e
> --- /dev/null
> +++ b/include/linux/mfd/da8xx-cfgchip.h
> @@ -0,0 +1,153 @@
> +/*
> + * TI DaVinci DA8xx CHIPCFGx registers for syscon consumers.
> + *
> + * Copyright (C) 2016 David Lechner <david@lechnology.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef __LINUX_MFD_DA8XX_CFGCHIP_H
> +#define __LINUX_MFD_DA8XX_CFGCHIP_H
> +
> +#include <linux/bitops.h>
> +
> +/* register offset (32-bit registers) */
> +#define CFGCHIP(n) ((n) * 4)
> +
> +/* CFGCHIP0 (PLL0/EDMA3_0) register bits */
> +#define CFGCHIP0_PLL_MASTER_LOCK BIT(4)
> +#define CFGCHIP0_EDMA30TC1DBS(n) ((n) << 2)
> +#define CFGCHIP0_EDMA30TC1DBS_MASK CFGCHIP0_EDMA30TC1DBS(0x3)
> +#define CFGCHIP0_EDMA30TC1DBS_16 CFGCHIP0_EDMA30TC1DBS(0x0)
> +#define CFGCHIP0_EDMA30TC1DBS_32 CFGCHIP0_EDMA30TC1DBS(0x1)
> +#define CFGCHIP0_EDMA30TC1DBS_64 CFGCHIP0_EDMA30TC1DBS(0x2)
> +#define CFGCHIP0_EDMA30TC0DBS(n) ((n) << 0)
> +#define CFGCHIP0_EDMA30TC0DBS_MASK CFGCHIP0_EDMA30TC0DBS(0x3)
> +#define CFGCHIP0_EDMA30TC0DBS_16 CFGCHIP0_EDMA30TC0DBS(0x0)
> +#define CFGCHIP0_EDMA30TC0DBS_32 CFGCHIP0_EDMA30TC0DBS(0x1)
> +#define CFGCHIP0_EDMA30TC0DBS_64 CFGCHIP0_EDMA30TC0DBS(0x2)
> +
> +/* CFGCHIP1 (eCAP/HPI/EDMA3_1/eHRPWM TBCLK/McASP0 AMUTEIN) register bits */
> +#define CFGCHIP1_CAP2SRC(n) ((n) << 27)
> +#define CFGCHIP1_CAP2SRC_MASK CFGCHIP1_CAP2SRC(0x1f)
> +#define CFGCHIP1_CAP2SRC_ECAP_PIN CFGCHIP1_CAP2SRC(0x0)
> +#define CFGCHIP1_CAP2SRC_MCASP0_TX CFGCHIP1_CAP2SRC(0x1)
> +#define CFGCHIP1_CAP2SRC_MCASP0_RX CFGCHIP1_CAP2SRC(0x2)
> +#define CFGCHIP1_CAP2SRC_EMAC_C0_RX_THRESHOLD CFGCHIP1_CAP2SRC(0x7)
> +#define CFGCHIP1_CAP2SRC_EMAC_C0_RX CFGCHIP1_CAP2SRC(0x8)
> +#define CFGCHIP1_CAP2SRC_EMAC_C0_TX CFGCHIP1_CAP2SRC(0x9)
> +#define CFGCHIP1_CAP2SRC_EMAC_C0_MISC CFGCHIP1_CAP2SRC(0xa)
> +#define CFGCHIP1_CAP2SRC_EMAC_C1_RX_THRESHOLD CFGCHIP1_CAP2SRC(0xb)
> +#define CFGCHIP1_CAP2SRC_EMAC_C1_RX CFGCHIP1_CAP2SRC(0xc)
> +#define CFGCHIP1_CAP2SRC_EMAC_C1_TX CFGCHIP1_CAP2SRC(0xd)
> +#define CFGCHIP1_CAP2SRC_EMAC_C1_MISC CFGCHIP1_CAP2SRC(0xe)
> +#define CFGCHIP1_CAP2SRC_EMAC_C2_RX_THRESHOLD CFGCHIP1_CAP2SRC(0xf)
> +#define CFGCHIP1_CAP2SRC_EMAC_C2_RX CFGCHIP1_CAP2SRC(0x10)
> +#define CFGCHIP1_CAP2SRC_EMAC_C2_TX CFGCHIP1_CAP2SRC(0x11)
> +#define CFGCHIP1_CAP2SRC_EMAC_C2_MISC CFGCHIP1_CAP2SRC(0x12)
> +#define CFGCHIP1_CAP1SRC(n) ((n) << 22)
> +#define CFGCHIP1_CAP1SRC_MASK CFGCHIP1_CAP1SRC(0x1f)
> +#define CFGCHIP1_CAP1SRC_ECAP_PIN CFGCHIP1_CAP1SRC(0x0)
> +#define CFGCHIP1_CAP1SRC_MCASP0_TX CFGCHIP1_CAP1SRC(0x1)
> +#define CFGCHIP1_CAP1SRC_MCASP0_RX CFGCHIP1_CAP1SRC(0x2)
> +#define CFGCHIP1_CAP1SRC_EMAC_C0_RX_THRESHOLD CFGCHIP1_CAP1SRC(0x7)
> +#define CFGCHIP1_CAP1SRC_EMAC_C0_RX CFGCHIP1_CAP1SRC(0x8)
> +#define CFGCHIP1_CAP1SRC_EMAC_C0_TX CFGCHIP1_CAP1SRC(0x9)
> +#define CFGCHIP1_CAP1SRC_EMAC_C0_MISC CFGCHIP1_CAP1SRC(0xa)
> +#define CFGCHIP1_CAP1SRC_EMAC_C1_RX_THRESHOLD CFGCHIP1_CAP1SRC(0xb)
> +#define CFGCHIP1_CAP1SRC_EMAC_C1_RX CFGCHIP1_CAP1SRC(0xc)
> +#define CFGCHIP1_CAP1SRC_EMAC_C1_TX CFGCHIP1_CAP1SRC(0xd)
> +#define CFGCHIP1_CAP1SRC_EMAC_C1_MISC CFGCHIP1_CAP1SRC(0xe)
> +#define CFGCHIP1_CAP1SRC_EMAC_C2_RX_THRESHOLD CFGCHIP1_CAP1SRC(0xf)
> +#define CFGCHIP1_CAP1SRC_EMAC_C2_RX CFGCHIP1_CAP1SRC(0x10)
> +#define CFGCHIP1_CAP1SRC_EMAC_C2_TX CFGCHIP1_CAP1SRC(0x11)
> +#define CFGCHIP1_CAP1SRC_EMAC_C2_MISC CFGCHIP1_CAP1SRC(0x12)
> +#define CFGCHIP1_CAP0SRC(n) ((n) << 17)
> +#define CFGCHIP1_CAP0SRC_MASK CFGCHIP1_CAP0SRC(0x1f)
> +#define CFGCHIP1_CAP0SRC_ECAP_PIN CFGCHIP1_CAP0SRC(0x0)
> +#define CFGCHIP1_CAP0SRC_MCASP0_TX CFGCHIP1_CAP0SRC(0x1)
> +#define CFGCHIP1_CAP0SRC_MCASP0_RX CFGCHIP1_CAP0SRC(0x2)
> +#define CFGCHIP1_CAP0SRC_EMAC_C0_RX_THRESHOLD CFGCHIP1_CAP0SRC(0x7)
> +#define CFGCHIP1_CAP0SRC_EMAC_C0_RX CFGCHIP1_CAP0SRC(0x8)
> +#define CFGCHIP1_CAP0SRC_EMAC_C0_TX CFGCHIP1_CAP0SRC(0x9)
> +#define CFGCHIP1_CAP0SRC_EMAC_C0_MISC CFGCHIP1_CAP0SRC(0xa)
> +#define CFGCHIP1_CAP0SRC_EMAC_C1_RX_THRESHOLD CFGCHIP1_CAP0SRC(0xb)
> +#define CFGCHIP1_CAP0SRC_EMAC_C1_RX CFGCHIP1_CAP0SRC(0xc)
> +#define CFGCHIP1_CAP0SRC_EMAC_C1_TX CFGCHIP1_CAP0SRC(0xd)
> +#define CFGCHIP1_CAP0SRC_EMAC_C1_MISC CFGCHIP1_CAP0SRC(0xe)
> +#define CFGCHIP1_CAP0SRC_EMAC_C2_RX_THRESHOLD CFGCHIP1_CAP0SRC(0xf)
> +#define CFGCHIP1_CAP0SRC_EMAC_C2_RX CFGCHIP1_CAP0SRC(0x10)
> +#define CFGCHIP1_CAP0SRC_EMAC_C2_TX CFGCHIP1_CAP0SRC(0x11)
> +#define CFGCHIP1_CAP0SRC_EMAC_C2_MISC CFGCHIP1_CAP0SRC(0x12)
> +#define CFGCHIP1_HPIBYTEAD BIT(16)
> +#define CFGCHIP1_HPIENA BIT(15)
> +#define CFGCHIP0_EDMA31TC0DBS(n) ((n) << 13)
> +#define CFGCHIP0_EDMA31TC0DBS_MASK CFGCHIP0_EDMA31TC0DBS(0x3)
> +#define CFGCHIP0_EDMA31TC0DBS_16 CFGCHIP0_EDMA31TC0DBS(0x0)
> +#define CFGCHIP0_EDMA31TC0DBS_32 CFGCHIP0_EDMA31TC0DBS(0x1)
> +#define CFGCHIP0_EDMA31TC0DBS_64 CFGCHIP0_EDMA31TC0DBS(0x2)
> +#define CFGCHIP1_TBCLKSYNC BIT(12)
> +#define CFGCHIP1_AMUTESEL0(n) ((n) << 0)
> +#define CFGCHIP1_AMUTESEL0_MASK CFGCHIP1_AMUTESEL0(0xf)
> +#define CFGCHIP1_AMUTESEL0_LOW CFGCHIP1_AMUTESEL0(0x0)
> +#define CFGCHIP1_AMUTESEL0_BANK_0 CFGCHIP1_AMUTESEL0(0x1)
> +#define CFGCHIP1_AMUTESEL0_BANK_1 CFGCHIP1_AMUTESEL0(0x2)
> +#define CFGCHIP1_AMUTESEL0_BANK_2 CFGCHIP1_AMUTESEL0(0x3)
> +#define CFGCHIP1_AMUTESEL0_BANK_3 CFGCHIP1_AMUTESEL0(0x4)
> +#define CFGCHIP1_AMUTESEL0_BANK_4 CFGCHIP1_AMUTESEL0(0x5)
> +#define CFGCHIP1_AMUTESEL0_BANK_5 CFGCHIP1_AMUTESEL0(0x6)
> +#define CFGCHIP1_AMUTESEL0_BANK_6 CFGCHIP1_AMUTESEL0(0x7)
> +#define CFGCHIP1_AMUTESEL0_BANK_7 CFGCHIP1_AMUTESEL0(0x8)
> +
> +/* CFGCHIP2 (USB PHY) register bits */
> +#define CFGCHIP2_PHYCLKGD BIT(17)
> +#define CFGCHIP2_VBUSSENSE BIT(16)
> +#define CFGCHIP2_RESET BIT(15)
> +#define CFGCHIP2_OTGMODE(n) ((n) << 13)
> +#define CFGCHIP2_OTGMODE_MASK CFGCHIP2_OTGMODE(0x3)
> +#define CFGCHIP2_OTGMODE_NO_OVERRIDE CFGCHIP2_OTGMODE(0x0)
> +#define CFGCHIP2_OTGMODE_FORCE_HOST CFGCHIP2_OTGMODE(0x1)
> +#define CFGCHIP2_OTGMODE_FORCE_DEVICE CFGCHIP2_OTGMODE(0x2)
> +#define CFGCHIP2_OTGMODE_FORCE_HOST_VBUS_LOW CFGCHIP2_OTGMODE(0x3)
> +#define CFGCHIP2_USB1PHYCLKMUX BIT(12)
> +#define CFGCHIP2_USB2PHYCLKMUX BIT(11)
> +#define CFGCHIP2_PHYPWRDN BIT(10)
> +#define CFGCHIP2_OTGPWRDN BIT(9)
> +#define CFGCHIP2_DATPOL BIT(8)
> +#define CFGCHIP2_USB1SUSPENDM BIT(7)
> +#define CFGCHIP2_PHY_PLLON BIT(6)
> +#define CFGCHIP2_SESENDEN BIT(5)
> +#define CFGCHIP2_VBDTCTEN BIT(4)
> +#define CFGCHIP2_REFFREQ(n) ((n) << 0)
> +#define CFGCHIP2_REFFREQ_MASK CFGCHIP2_REFFREQ(0xf)
> +#define CFGCHIP2_REFFREQ_12MHZ CFGCHIP2_REFFREQ(0x1)
> +#define CFGCHIP2_REFFREQ_24MHZ CFGCHIP2_REFFREQ(0x2)
> +#define CFGCHIP2_REFFREQ_48MHZ CFGCHIP2_REFFREQ(0x3)
> +#define CFGCHIP2_REFFREQ_19_2MHZ CFGCHIP2_REFFREQ(0x4)
> +#define CFGCHIP2_REFFREQ_38_4MHZ CFGCHIP2_REFFREQ(0x5)
> +#define CFGCHIP2_REFFREQ_13MHZ CFGCHIP2_REFFREQ(0x6)
> +#define CFGCHIP2_REFFREQ_26MHZ CFGCHIP2_REFFREQ(0x7)
> +#define CFGCHIP2_REFFREQ_20MHZ CFGCHIP2_REFFREQ(0x8)
> +#define CFGCHIP2_REFFREQ_40MHZ CFGCHIP2_REFFREQ(0x9)
> +
> +/* CFGCHIP3 (EMAC/uPP/PLL1/ASYNC3/PRU/DIV4.5/EMIFA) register bits */
> +#define CFGCHIP3_RMII_SEL BIT(8)
> +#define CFGCHIP3_UPP_TX_CLKSRC BIT(6)
> +#define CFGCHIP3_PLL1_MASTER_LOCK BIT(5)
> +#define CFGCHIP3_ASYNC3_CLKSRC BIT(4)
> +#define CFGCHIP3_PRUEVTSEL BIT(3)
> +#define CFGCHIP3_DIV45PENA BIT(2)
> +#define CFGCHIP3_EMA_CLKSRC BIT(1)
> +
> +/* CFGCHIP4 (McASP0 AMUNTEIN) register bits */
> +#define CFGCHIP4_AMUTECLR0 BIT(0)
> +
> +#endif /* __LINUX_MFD_DA8XX_CFGCHIP_H */
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] mfd: da8xx-cfgchip: New header file for CFGCHIP registers
2016-08-30 14:22 ` Lee Jones
@ 2016-08-30 14:24 ` Kishon Vijay Abraham I
2016-08-31 11:29 ` Lee Jones
0 siblings, 1 reply; 5+ messages in thread
From: Kishon Vijay Abraham I @ 2016-08-30 14:24 UTC (permalink / raw)
To: Lee Jones; +Cc: david, linux-kernel
Hi Lee Jones,
On Tuesday 30 August 2016 07:52 PM, Lee Jones wrote:
> On Wed, 10 Aug 2016, Kishon Vijay Abraham I wrote:
>
>> From: David Lechner <david@lechnology.com>
>>
>> Create a new header file for TI DA8XX SoC CFGCHIPx registers.
>> This will be used by a number of planned drivers including a new USB
>> PHY driver and common clock framework drivers.
>>
>> The same defines *will* be removed from the platform_data header,
>> once all the users start using the new syscon device header.
>>
>> This also fixes the following compiler error caused due to
>> a dependent patch not merged.
>> drivers/phy/phy-da8xx-usb.c:19:37:
>> fatal error: linux/mfd/da8xx-cfgchip.h: No such file or directory
>> #include <linux/mfd/da8xx-cfgchip.h>
>>
>> Signed-off-by: David Lechner <david@lechnology.com>
>> Acked-by: Lee Jones <lee.jones@linaro.org>
>> Reported-by: Arnd Bergmann <arnd@arndb.de>
>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>> ---
>> include/linux/mfd/da8xx-cfgchip.h | 153 +++++++++++++++++++++++++++++++++++++
>> 1 file changed, 153 insertions(+)
>
> Applied, thanks.
I've already merged this in linux-phy tree since this was causing build
breakage. Can you drop this from your tree?
Thanks
Kishon
>
>> diff --git a/include/linux/mfd/da8xx-cfgchip.h b/include/linux/mfd/da8xx-cfgchip.h
>> new file mode 100644
>> index 0000000..304985e
>> --- /dev/null
>> +++ b/include/linux/mfd/da8xx-cfgchip.h
>> @@ -0,0 +1,153 @@
>> +/*
>> + * TI DaVinci DA8xx CHIPCFGx registers for syscon consumers.
>> + *
>> + * Copyright (C) 2016 David Lechner <david@lechnology.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#ifndef __LINUX_MFD_DA8XX_CFGCHIP_H
>> +#define __LINUX_MFD_DA8XX_CFGCHIP_H
>> +
>> +#include <linux/bitops.h>
>> +
>> +/* register offset (32-bit registers) */
>> +#define CFGCHIP(n) ((n) * 4)
>> +
>> +/* CFGCHIP0 (PLL0/EDMA3_0) register bits */
>> +#define CFGCHIP0_PLL_MASTER_LOCK BIT(4)
>> +#define CFGCHIP0_EDMA30TC1DBS(n) ((n) << 2)
>> +#define CFGCHIP0_EDMA30TC1DBS_MASK CFGCHIP0_EDMA30TC1DBS(0x3)
>> +#define CFGCHIP0_EDMA30TC1DBS_16 CFGCHIP0_EDMA30TC1DBS(0x0)
>> +#define CFGCHIP0_EDMA30TC1DBS_32 CFGCHIP0_EDMA30TC1DBS(0x1)
>> +#define CFGCHIP0_EDMA30TC1DBS_64 CFGCHIP0_EDMA30TC1DBS(0x2)
>> +#define CFGCHIP0_EDMA30TC0DBS(n) ((n) << 0)
>> +#define CFGCHIP0_EDMA30TC0DBS_MASK CFGCHIP0_EDMA30TC0DBS(0x3)
>> +#define CFGCHIP0_EDMA30TC0DBS_16 CFGCHIP0_EDMA30TC0DBS(0x0)
>> +#define CFGCHIP0_EDMA30TC0DBS_32 CFGCHIP0_EDMA30TC0DBS(0x1)
>> +#define CFGCHIP0_EDMA30TC0DBS_64 CFGCHIP0_EDMA30TC0DBS(0x2)
>> +
>> +/* CFGCHIP1 (eCAP/HPI/EDMA3_1/eHRPWM TBCLK/McASP0 AMUTEIN) register bits */
>> +#define CFGCHIP1_CAP2SRC(n) ((n) << 27)
>> +#define CFGCHIP1_CAP2SRC_MASK CFGCHIP1_CAP2SRC(0x1f)
>> +#define CFGCHIP1_CAP2SRC_ECAP_PIN CFGCHIP1_CAP2SRC(0x0)
>> +#define CFGCHIP1_CAP2SRC_MCASP0_TX CFGCHIP1_CAP2SRC(0x1)
>> +#define CFGCHIP1_CAP2SRC_MCASP0_RX CFGCHIP1_CAP2SRC(0x2)
>> +#define CFGCHIP1_CAP2SRC_EMAC_C0_RX_THRESHOLD CFGCHIP1_CAP2SRC(0x7)
>> +#define CFGCHIP1_CAP2SRC_EMAC_C0_RX CFGCHIP1_CAP2SRC(0x8)
>> +#define CFGCHIP1_CAP2SRC_EMAC_C0_TX CFGCHIP1_CAP2SRC(0x9)
>> +#define CFGCHIP1_CAP2SRC_EMAC_C0_MISC CFGCHIP1_CAP2SRC(0xa)
>> +#define CFGCHIP1_CAP2SRC_EMAC_C1_RX_THRESHOLD CFGCHIP1_CAP2SRC(0xb)
>> +#define CFGCHIP1_CAP2SRC_EMAC_C1_RX CFGCHIP1_CAP2SRC(0xc)
>> +#define CFGCHIP1_CAP2SRC_EMAC_C1_TX CFGCHIP1_CAP2SRC(0xd)
>> +#define CFGCHIP1_CAP2SRC_EMAC_C1_MISC CFGCHIP1_CAP2SRC(0xe)
>> +#define CFGCHIP1_CAP2SRC_EMAC_C2_RX_THRESHOLD CFGCHIP1_CAP2SRC(0xf)
>> +#define CFGCHIP1_CAP2SRC_EMAC_C2_RX CFGCHIP1_CAP2SRC(0x10)
>> +#define CFGCHIP1_CAP2SRC_EMAC_C2_TX CFGCHIP1_CAP2SRC(0x11)
>> +#define CFGCHIP1_CAP2SRC_EMAC_C2_MISC CFGCHIP1_CAP2SRC(0x12)
>> +#define CFGCHIP1_CAP1SRC(n) ((n) << 22)
>> +#define CFGCHIP1_CAP1SRC_MASK CFGCHIP1_CAP1SRC(0x1f)
>> +#define CFGCHIP1_CAP1SRC_ECAP_PIN CFGCHIP1_CAP1SRC(0x0)
>> +#define CFGCHIP1_CAP1SRC_MCASP0_TX CFGCHIP1_CAP1SRC(0x1)
>> +#define CFGCHIP1_CAP1SRC_MCASP0_RX CFGCHIP1_CAP1SRC(0x2)
>> +#define CFGCHIP1_CAP1SRC_EMAC_C0_RX_THRESHOLD CFGCHIP1_CAP1SRC(0x7)
>> +#define CFGCHIP1_CAP1SRC_EMAC_C0_RX CFGCHIP1_CAP1SRC(0x8)
>> +#define CFGCHIP1_CAP1SRC_EMAC_C0_TX CFGCHIP1_CAP1SRC(0x9)
>> +#define CFGCHIP1_CAP1SRC_EMAC_C0_MISC CFGCHIP1_CAP1SRC(0xa)
>> +#define CFGCHIP1_CAP1SRC_EMAC_C1_RX_THRESHOLD CFGCHIP1_CAP1SRC(0xb)
>> +#define CFGCHIP1_CAP1SRC_EMAC_C1_RX CFGCHIP1_CAP1SRC(0xc)
>> +#define CFGCHIP1_CAP1SRC_EMAC_C1_TX CFGCHIP1_CAP1SRC(0xd)
>> +#define CFGCHIP1_CAP1SRC_EMAC_C1_MISC CFGCHIP1_CAP1SRC(0xe)
>> +#define CFGCHIP1_CAP1SRC_EMAC_C2_RX_THRESHOLD CFGCHIP1_CAP1SRC(0xf)
>> +#define CFGCHIP1_CAP1SRC_EMAC_C2_RX CFGCHIP1_CAP1SRC(0x10)
>> +#define CFGCHIP1_CAP1SRC_EMAC_C2_TX CFGCHIP1_CAP1SRC(0x11)
>> +#define CFGCHIP1_CAP1SRC_EMAC_C2_MISC CFGCHIP1_CAP1SRC(0x12)
>> +#define CFGCHIP1_CAP0SRC(n) ((n) << 17)
>> +#define CFGCHIP1_CAP0SRC_MASK CFGCHIP1_CAP0SRC(0x1f)
>> +#define CFGCHIP1_CAP0SRC_ECAP_PIN CFGCHIP1_CAP0SRC(0x0)
>> +#define CFGCHIP1_CAP0SRC_MCASP0_TX CFGCHIP1_CAP0SRC(0x1)
>> +#define CFGCHIP1_CAP0SRC_MCASP0_RX CFGCHIP1_CAP0SRC(0x2)
>> +#define CFGCHIP1_CAP0SRC_EMAC_C0_RX_THRESHOLD CFGCHIP1_CAP0SRC(0x7)
>> +#define CFGCHIP1_CAP0SRC_EMAC_C0_RX CFGCHIP1_CAP0SRC(0x8)
>> +#define CFGCHIP1_CAP0SRC_EMAC_C0_TX CFGCHIP1_CAP0SRC(0x9)
>> +#define CFGCHIP1_CAP0SRC_EMAC_C0_MISC CFGCHIP1_CAP0SRC(0xa)
>> +#define CFGCHIP1_CAP0SRC_EMAC_C1_RX_THRESHOLD CFGCHIP1_CAP0SRC(0xb)
>> +#define CFGCHIP1_CAP0SRC_EMAC_C1_RX CFGCHIP1_CAP0SRC(0xc)
>> +#define CFGCHIP1_CAP0SRC_EMAC_C1_TX CFGCHIP1_CAP0SRC(0xd)
>> +#define CFGCHIP1_CAP0SRC_EMAC_C1_MISC CFGCHIP1_CAP0SRC(0xe)
>> +#define CFGCHIP1_CAP0SRC_EMAC_C2_RX_THRESHOLD CFGCHIP1_CAP0SRC(0xf)
>> +#define CFGCHIP1_CAP0SRC_EMAC_C2_RX CFGCHIP1_CAP0SRC(0x10)
>> +#define CFGCHIP1_CAP0SRC_EMAC_C2_TX CFGCHIP1_CAP0SRC(0x11)
>> +#define CFGCHIP1_CAP0SRC_EMAC_C2_MISC CFGCHIP1_CAP0SRC(0x12)
>> +#define CFGCHIP1_HPIBYTEAD BIT(16)
>> +#define CFGCHIP1_HPIENA BIT(15)
>> +#define CFGCHIP0_EDMA31TC0DBS(n) ((n) << 13)
>> +#define CFGCHIP0_EDMA31TC0DBS_MASK CFGCHIP0_EDMA31TC0DBS(0x3)
>> +#define CFGCHIP0_EDMA31TC0DBS_16 CFGCHIP0_EDMA31TC0DBS(0x0)
>> +#define CFGCHIP0_EDMA31TC0DBS_32 CFGCHIP0_EDMA31TC0DBS(0x1)
>> +#define CFGCHIP0_EDMA31TC0DBS_64 CFGCHIP0_EDMA31TC0DBS(0x2)
>> +#define CFGCHIP1_TBCLKSYNC BIT(12)
>> +#define CFGCHIP1_AMUTESEL0(n) ((n) << 0)
>> +#define CFGCHIP1_AMUTESEL0_MASK CFGCHIP1_AMUTESEL0(0xf)
>> +#define CFGCHIP1_AMUTESEL0_LOW CFGCHIP1_AMUTESEL0(0x0)
>> +#define CFGCHIP1_AMUTESEL0_BANK_0 CFGCHIP1_AMUTESEL0(0x1)
>> +#define CFGCHIP1_AMUTESEL0_BANK_1 CFGCHIP1_AMUTESEL0(0x2)
>> +#define CFGCHIP1_AMUTESEL0_BANK_2 CFGCHIP1_AMUTESEL0(0x3)
>> +#define CFGCHIP1_AMUTESEL0_BANK_3 CFGCHIP1_AMUTESEL0(0x4)
>> +#define CFGCHIP1_AMUTESEL0_BANK_4 CFGCHIP1_AMUTESEL0(0x5)
>> +#define CFGCHIP1_AMUTESEL0_BANK_5 CFGCHIP1_AMUTESEL0(0x6)
>> +#define CFGCHIP1_AMUTESEL0_BANK_6 CFGCHIP1_AMUTESEL0(0x7)
>> +#define CFGCHIP1_AMUTESEL0_BANK_7 CFGCHIP1_AMUTESEL0(0x8)
>> +
>> +/* CFGCHIP2 (USB PHY) register bits */
>> +#define CFGCHIP2_PHYCLKGD BIT(17)
>> +#define CFGCHIP2_VBUSSENSE BIT(16)
>> +#define CFGCHIP2_RESET BIT(15)
>> +#define CFGCHIP2_OTGMODE(n) ((n) << 13)
>> +#define CFGCHIP2_OTGMODE_MASK CFGCHIP2_OTGMODE(0x3)
>> +#define CFGCHIP2_OTGMODE_NO_OVERRIDE CFGCHIP2_OTGMODE(0x0)
>> +#define CFGCHIP2_OTGMODE_FORCE_HOST CFGCHIP2_OTGMODE(0x1)
>> +#define CFGCHIP2_OTGMODE_FORCE_DEVICE CFGCHIP2_OTGMODE(0x2)
>> +#define CFGCHIP2_OTGMODE_FORCE_HOST_VBUS_LOW CFGCHIP2_OTGMODE(0x3)
>> +#define CFGCHIP2_USB1PHYCLKMUX BIT(12)
>> +#define CFGCHIP2_USB2PHYCLKMUX BIT(11)
>> +#define CFGCHIP2_PHYPWRDN BIT(10)
>> +#define CFGCHIP2_OTGPWRDN BIT(9)
>> +#define CFGCHIP2_DATPOL BIT(8)
>> +#define CFGCHIP2_USB1SUSPENDM BIT(7)
>> +#define CFGCHIP2_PHY_PLLON BIT(6)
>> +#define CFGCHIP2_SESENDEN BIT(5)
>> +#define CFGCHIP2_VBDTCTEN BIT(4)
>> +#define CFGCHIP2_REFFREQ(n) ((n) << 0)
>> +#define CFGCHIP2_REFFREQ_MASK CFGCHIP2_REFFREQ(0xf)
>> +#define CFGCHIP2_REFFREQ_12MHZ CFGCHIP2_REFFREQ(0x1)
>> +#define CFGCHIP2_REFFREQ_24MHZ CFGCHIP2_REFFREQ(0x2)
>> +#define CFGCHIP2_REFFREQ_48MHZ CFGCHIP2_REFFREQ(0x3)
>> +#define CFGCHIP2_REFFREQ_19_2MHZ CFGCHIP2_REFFREQ(0x4)
>> +#define CFGCHIP2_REFFREQ_38_4MHZ CFGCHIP2_REFFREQ(0x5)
>> +#define CFGCHIP2_REFFREQ_13MHZ CFGCHIP2_REFFREQ(0x6)
>> +#define CFGCHIP2_REFFREQ_26MHZ CFGCHIP2_REFFREQ(0x7)
>> +#define CFGCHIP2_REFFREQ_20MHZ CFGCHIP2_REFFREQ(0x8)
>> +#define CFGCHIP2_REFFREQ_40MHZ CFGCHIP2_REFFREQ(0x9)
>> +
>> +/* CFGCHIP3 (EMAC/uPP/PLL1/ASYNC3/PRU/DIV4.5/EMIFA) register bits */
>> +#define CFGCHIP3_RMII_SEL BIT(8)
>> +#define CFGCHIP3_UPP_TX_CLKSRC BIT(6)
>> +#define CFGCHIP3_PLL1_MASTER_LOCK BIT(5)
>> +#define CFGCHIP3_ASYNC3_CLKSRC BIT(4)
>> +#define CFGCHIP3_PRUEVTSEL BIT(3)
>> +#define CFGCHIP3_DIV45PENA BIT(2)
>> +#define CFGCHIP3_EMA_CLKSRC BIT(1)
>> +
>> +/* CFGCHIP4 (McASP0 AMUNTEIN) register bits */
>> +#define CFGCHIP4_AMUTECLR0 BIT(0)
>> +
>> +#endif /* __LINUX_MFD_DA8XX_CFGCHIP_H */
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] mfd: da8xx-cfgchip: New header file for CFGCHIP registers
2016-08-30 14:24 ` Kishon Vijay Abraham I
@ 2016-08-31 11:29 ` Lee Jones
2016-08-31 11:32 ` Kishon Vijay Abraham I
0 siblings, 1 reply; 5+ messages in thread
From: Lee Jones @ 2016-08-31 11:29 UTC (permalink / raw)
To: Kishon Vijay Abraham I; +Cc: david, linux-kernel
On Tue, 30 Aug 2016, Kishon Vijay Abraham I wrote:
> Hi Lee Jones,
>
> On Tuesday 30 August 2016 07:52 PM, Lee Jones wrote:
> > On Wed, 10 Aug 2016, Kishon Vijay Abraham I wrote:
> >
> >> From: David Lechner <david@lechnology.com>
> >>
> >> Create a new header file for TI DA8XX SoC CFGCHIPx registers.
> >> This will be used by a number of planned drivers including a new USB
> >> PHY driver and common clock framework drivers.
> >>
> >> The same defines *will* be removed from the platform_data header,
> >> once all the users start using the new syscon device header.
> >>
> >> This also fixes the following compiler error caused due to
> >> a dependent patch not merged.
> >> drivers/phy/phy-da8xx-usb.c:19:37:
> >> fatal error: linux/mfd/da8xx-cfgchip.h: No such file or directory
> >> #include <linux/mfd/da8xx-cfgchip.h>
> >>
> >> Signed-off-by: David Lechner <david@lechnology.com>
> >> Acked-by: Lee Jones <lee.jones@linaro.org>
> >> Reported-by: Arnd Bergmann <arnd@arndb.de>
> >> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> >> ---
> >> include/linux/mfd/da8xx-cfgchip.h | 153 +++++++++++++++++++++++++++++++++++++
> >> 1 file changed, 153 insertions(+)
> >
> > Applied, thanks.
>
> I've already merged this in linux-phy tree since this was causing build
> breakage. Can you drop this from your tree?
I can, but I may need a pull-request depending on if anything breaks
in my tree.
> >> diff --git a/include/linux/mfd/da8xx-cfgchip.h b/include/linux/mfd/da8xx-cfgchip.h
> >> new file mode 100644
> >> index 0000000..304985e
> >> --- /dev/null
> >> +++ b/include/linux/mfd/da8xx-cfgchip.h
> >> @@ -0,0 +1,153 @@
> >> +/*
> >> + * TI DaVinci DA8xx CHIPCFGx registers for syscon consumers.
> >> + *
> >> + * Copyright (C) 2016 David Lechner <david@lechnology.com>
> >> + *
> >> + * This program is free software; you can redistribute it and/or modify
> >> + * it under the terms of the GNU General Public License as published by
> >> + * the Free Software Foundation; either version 2 of the License, or
> >> + * (at your option) any later version.
> >> + *
> >> + * This program is distributed in the hope that it will be useful,
> >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> >> + * GNU General Public License for more details.
> >> + */
> >> +
> >> +#ifndef __LINUX_MFD_DA8XX_CFGCHIP_H
> >> +#define __LINUX_MFD_DA8XX_CFGCHIP_H
> >> +
> >> +#include <linux/bitops.h>
> >> +
> >> +/* register offset (32-bit registers) */
> >> +#define CFGCHIP(n) ((n) * 4)
> >> +
> >> +/* CFGCHIP0 (PLL0/EDMA3_0) register bits */
> >> +#define CFGCHIP0_PLL_MASTER_LOCK BIT(4)
> >> +#define CFGCHIP0_EDMA30TC1DBS(n) ((n) << 2)
> >> +#define CFGCHIP0_EDMA30TC1DBS_MASK CFGCHIP0_EDMA30TC1DBS(0x3)
> >> +#define CFGCHIP0_EDMA30TC1DBS_16 CFGCHIP0_EDMA30TC1DBS(0x0)
> >> +#define CFGCHIP0_EDMA30TC1DBS_32 CFGCHIP0_EDMA30TC1DBS(0x1)
> >> +#define CFGCHIP0_EDMA30TC1DBS_64 CFGCHIP0_EDMA30TC1DBS(0x2)
> >> +#define CFGCHIP0_EDMA30TC0DBS(n) ((n) << 0)
> >> +#define CFGCHIP0_EDMA30TC0DBS_MASK CFGCHIP0_EDMA30TC0DBS(0x3)
> >> +#define CFGCHIP0_EDMA30TC0DBS_16 CFGCHIP0_EDMA30TC0DBS(0x0)
> >> +#define CFGCHIP0_EDMA30TC0DBS_32 CFGCHIP0_EDMA30TC0DBS(0x1)
> >> +#define CFGCHIP0_EDMA30TC0DBS_64 CFGCHIP0_EDMA30TC0DBS(0x2)
> >> +
> >> +/* CFGCHIP1 (eCAP/HPI/EDMA3_1/eHRPWM TBCLK/McASP0 AMUTEIN) register bits */
> >> +#define CFGCHIP1_CAP2SRC(n) ((n) << 27)
> >> +#define CFGCHIP1_CAP2SRC_MASK CFGCHIP1_CAP2SRC(0x1f)
> >> +#define CFGCHIP1_CAP2SRC_ECAP_PIN CFGCHIP1_CAP2SRC(0x0)
> >> +#define CFGCHIP1_CAP2SRC_MCASP0_TX CFGCHIP1_CAP2SRC(0x1)
> >> +#define CFGCHIP1_CAP2SRC_MCASP0_RX CFGCHIP1_CAP2SRC(0x2)
> >> +#define CFGCHIP1_CAP2SRC_EMAC_C0_RX_THRESHOLD CFGCHIP1_CAP2SRC(0x7)
> >> +#define CFGCHIP1_CAP2SRC_EMAC_C0_RX CFGCHIP1_CAP2SRC(0x8)
> >> +#define CFGCHIP1_CAP2SRC_EMAC_C0_TX CFGCHIP1_CAP2SRC(0x9)
> >> +#define CFGCHIP1_CAP2SRC_EMAC_C0_MISC CFGCHIP1_CAP2SRC(0xa)
> >> +#define CFGCHIP1_CAP2SRC_EMAC_C1_RX_THRESHOLD CFGCHIP1_CAP2SRC(0xb)
> >> +#define CFGCHIP1_CAP2SRC_EMAC_C1_RX CFGCHIP1_CAP2SRC(0xc)
> >> +#define CFGCHIP1_CAP2SRC_EMAC_C1_TX CFGCHIP1_CAP2SRC(0xd)
> >> +#define CFGCHIP1_CAP2SRC_EMAC_C1_MISC CFGCHIP1_CAP2SRC(0xe)
> >> +#define CFGCHIP1_CAP2SRC_EMAC_C2_RX_THRESHOLD CFGCHIP1_CAP2SRC(0xf)
> >> +#define CFGCHIP1_CAP2SRC_EMAC_C2_RX CFGCHIP1_CAP2SRC(0x10)
> >> +#define CFGCHIP1_CAP2SRC_EMAC_C2_TX CFGCHIP1_CAP2SRC(0x11)
> >> +#define CFGCHIP1_CAP2SRC_EMAC_C2_MISC CFGCHIP1_CAP2SRC(0x12)
> >> +#define CFGCHIP1_CAP1SRC(n) ((n) << 22)
> >> +#define CFGCHIP1_CAP1SRC_MASK CFGCHIP1_CAP1SRC(0x1f)
> >> +#define CFGCHIP1_CAP1SRC_ECAP_PIN CFGCHIP1_CAP1SRC(0x0)
> >> +#define CFGCHIP1_CAP1SRC_MCASP0_TX CFGCHIP1_CAP1SRC(0x1)
> >> +#define CFGCHIP1_CAP1SRC_MCASP0_RX CFGCHIP1_CAP1SRC(0x2)
> >> +#define CFGCHIP1_CAP1SRC_EMAC_C0_RX_THRESHOLD CFGCHIP1_CAP1SRC(0x7)
> >> +#define CFGCHIP1_CAP1SRC_EMAC_C0_RX CFGCHIP1_CAP1SRC(0x8)
> >> +#define CFGCHIP1_CAP1SRC_EMAC_C0_TX CFGCHIP1_CAP1SRC(0x9)
> >> +#define CFGCHIP1_CAP1SRC_EMAC_C0_MISC CFGCHIP1_CAP1SRC(0xa)
> >> +#define CFGCHIP1_CAP1SRC_EMAC_C1_RX_THRESHOLD CFGCHIP1_CAP1SRC(0xb)
> >> +#define CFGCHIP1_CAP1SRC_EMAC_C1_RX CFGCHIP1_CAP1SRC(0xc)
> >> +#define CFGCHIP1_CAP1SRC_EMAC_C1_TX CFGCHIP1_CAP1SRC(0xd)
> >> +#define CFGCHIP1_CAP1SRC_EMAC_C1_MISC CFGCHIP1_CAP1SRC(0xe)
> >> +#define CFGCHIP1_CAP1SRC_EMAC_C2_RX_THRESHOLD CFGCHIP1_CAP1SRC(0xf)
> >> +#define CFGCHIP1_CAP1SRC_EMAC_C2_RX CFGCHIP1_CAP1SRC(0x10)
> >> +#define CFGCHIP1_CAP1SRC_EMAC_C2_TX CFGCHIP1_CAP1SRC(0x11)
> >> +#define CFGCHIP1_CAP1SRC_EMAC_C2_MISC CFGCHIP1_CAP1SRC(0x12)
> >> +#define CFGCHIP1_CAP0SRC(n) ((n) << 17)
> >> +#define CFGCHIP1_CAP0SRC_MASK CFGCHIP1_CAP0SRC(0x1f)
> >> +#define CFGCHIP1_CAP0SRC_ECAP_PIN CFGCHIP1_CAP0SRC(0x0)
> >> +#define CFGCHIP1_CAP0SRC_MCASP0_TX CFGCHIP1_CAP0SRC(0x1)
> >> +#define CFGCHIP1_CAP0SRC_MCASP0_RX CFGCHIP1_CAP0SRC(0x2)
> >> +#define CFGCHIP1_CAP0SRC_EMAC_C0_RX_THRESHOLD CFGCHIP1_CAP0SRC(0x7)
> >> +#define CFGCHIP1_CAP0SRC_EMAC_C0_RX CFGCHIP1_CAP0SRC(0x8)
> >> +#define CFGCHIP1_CAP0SRC_EMAC_C0_TX CFGCHIP1_CAP0SRC(0x9)
> >> +#define CFGCHIP1_CAP0SRC_EMAC_C0_MISC CFGCHIP1_CAP0SRC(0xa)
> >> +#define CFGCHIP1_CAP0SRC_EMAC_C1_RX_THRESHOLD CFGCHIP1_CAP0SRC(0xb)
> >> +#define CFGCHIP1_CAP0SRC_EMAC_C1_RX CFGCHIP1_CAP0SRC(0xc)
> >> +#define CFGCHIP1_CAP0SRC_EMAC_C1_TX CFGCHIP1_CAP0SRC(0xd)
> >> +#define CFGCHIP1_CAP0SRC_EMAC_C1_MISC CFGCHIP1_CAP0SRC(0xe)
> >> +#define CFGCHIP1_CAP0SRC_EMAC_C2_RX_THRESHOLD CFGCHIP1_CAP0SRC(0xf)
> >> +#define CFGCHIP1_CAP0SRC_EMAC_C2_RX CFGCHIP1_CAP0SRC(0x10)
> >> +#define CFGCHIP1_CAP0SRC_EMAC_C2_TX CFGCHIP1_CAP0SRC(0x11)
> >> +#define CFGCHIP1_CAP0SRC_EMAC_C2_MISC CFGCHIP1_CAP0SRC(0x12)
> >> +#define CFGCHIP1_HPIBYTEAD BIT(16)
> >> +#define CFGCHIP1_HPIENA BIT(15)
> >> +#define CFGCHIP0_EDMA31TC0DBS(n) ((n) << 13)
> >> +#define CFGCHIP0_EDMA31TC0DBS_MASK CFGCHIP0_EDMA31TC0DBS(0x3)
> >> +#define CFGCHIP0_EDMA31TC0DBS_16 CFGCHIP0_EDMA31TC0DBS(0x0)
> >> +#define CFGCHIP0_EDMA31TC0DBS_32 CFGCHIP0_EDMA31TC0DBS(0x1)
> >> +#define CFGCHIP0_EDMA31TC0DBS_64 CFGCHIP0_EDMA31TC0DBS(0x2)
> >> +#define CFGCHIP1_TBCLKSYNC BIT(12)
> >> +#define CFGCHIP1_AMUTESEL0(n) ((n) << 0)
> >> +#define CFGCHIP1_AMUTESEL0_MASK CFGCHIP1_AMUTESEL0(0xf)
> >> +#define CFGCHIP1_AMUTESEL0_LOW CFGCHIP1_AMUTESEL0(0x0)
> >> +#define CFGCHIP1_AMUTESEL0_BANK_0 CFGCHIP1_AMUTESEL0(0x1)
> >> +#define CFGCHIP1_AMUTESEL0_BANK_1 CFGCHIP1_AMUTESEL0(0x2)
> >> +#define CFGCHIP1_AMUTESEL0_BANK_2 CFGCHIP1_AMUTESEL0(0x3)
> >> +#define CFGCHIP1_AMUTESEL0_BANK_3 CFGCHIP1_AMUTESEL0(0x4)
> >> +#define CFGCHIP1_AMUTESEL0_BANK_4 CFGCHIP1_AMUTESEL0(0x5)
> >> +#define CFGCHIP1_AMUTESEL0_BANK_5 CFGCHIP1_AMUTESEL0(0x6)
> >> +#define CFGCHIP1_AMUTESEL0_BANK_6 CFGCHIP1_AMUTESEL0(0x7)
> >> +#define CFGCHIP1_AMUTESEL0_BANK_7 CFGCHIP1_AMUTESEL0(0x8)
> >> +
> >> +/* CFGCHIP2 (USB PHY) register bits */
> >> +#define CFGCHIP2_PHYCLKGD BIT(17)
> >> +#define CFGCHIP2_VBUSSENSE BIT(16)
> >> +#define CFGCHIP2_RESET BIT(15)
> >> +#define CFGCHIP2_OTGMODE(n) ((n) << 13)
> >> +#define CFGCHIP2_OTGMODE_MASK CFGCHIP2_OTGMODE(0x3)
> >> +#define CFGCHIP2_OTGMODE_NO_OVERRIDE CFGCHIP2_OTGMODE(0x0)
> >> +#define CFGCHIP2_OTGMODE_FORCE_HOST CFGCHIP2_OTGMODE(0x1)
> >> +#define CFGCHIP2_OTGMODE_FORCE_DEVICE CFGCHIP2_OTGMODE(0x2)
> >> +#define CFGCHIP2_OTGMODE_FORCE_HOST_VBUS_LOW CFGCHIP2_OTGMODE(0x3)
> >> +#define CFGCHIP2_USB1PHYCLKMUX BIT(12)
> >> +#define CFGCHIP2_USB2PHYCLKMUX BIT(11)
> >> +#define CFGCHIP2_PHYPWRDN BIT(10)
> >> +#define CFGCHIP2_OTGPWRDN BIT(9)
> >> +#define CFGCHIP2_DATPOL BIT(8)
> >> +#define CFGCHIP2_USB1SUSPENDM BIT(7)
> >> +#define CFGCHIP2_PHY_PLLON BIT(6)
> >> +#define CFGCHIP2_SESENDEN BIT(5)
> >> +#define CFGCHIP2_VBDTCTEN BIT(4)
> >> +#define CFGCHIP2_REFFREQ(n) ((n) << 0)
> >> +#define CFGCHIP2_REFFREQ_MASK CFGCHIP2_REFFREQ(0xf)
> >> +#define CFGCHIP2_REFFREQ_12MHZ CFGCHIP2_REFFREQ(0x1)
> >> +#define CFGCHIP2_REFFREQ_24MHZ CFGCHIP2_REFFREQ(0x2)
> >> +#define CFGCHIP2_REFFREQ_48MHZ CFGCHIP2_REFFREQ(0x3)
> >> +#define CFGCHIP2_REFFREQ_19_2MHZ CFGCHIP2_REFFREQ(0x4)
> >> +#define CFGCHIP2_REFFREQ_38_4MHZ CFGCHIP2_REFFREQ(0x5)
> >> +#define CFGCHIP2_REFFREQ_13MHZ CFGCHIP2_REFFREQ(0x6)
> >> +#define CFGCHIP2_REFFREQ_26MHZ CFGCHIP2_REFFREQ(0x7)
> >> +#define CFGCHIP2_REFFREQ_20MHZ CFGCHIP2_REFFREQ(0x8)
> >> +#define CFGCHIP2_REFFREQ_40MHZ CFGCHIP2_REFFREQ(0x9)
> >> +
> >> +/* CFGCHIP3 (EMAC/uPP/PLL1/ASYNC3/PRU/DIV4.5/EMIFA) register bits */
> >> +#define CFGCHIP3_RMII_SEL BIT(8)
> >> +#define CFGCHIP3_UPP_TX_CLKSRC BIT(6)
> >> +#define CFGCHIP3_PLL1_MASTER_LOCK BIT(5)
> >> +#define CFGCHIP3_ASYNC3_CLKSRC BIT(4)
> >> +#define CFGCHIP3_PRUEVTSEL BIT(3)
> >> +#define CFGCHIP3_DIV45PENA BIT(2)
> >> +#define CFGCHIP3_EMA_CLKSRC BIT(1)
> >> +
> >> +/* CFGCHIP4 (McASP0 AMUNTEIN) register bits */
> >> +#define CFGCHIP4_AMUTECLR0 BIT(0)
> >> +
> >> +#endif /* __LINUX_MFD_DA8XX_CFGCHIP_H */
> >
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] mfd: da8xx-cfgchip: New header file for CFGCHIP registers
2016-08-31 11:29 ` Lee Jones
@ 2016-08-31 11:32 ` Kishon Vijay Abraham I
0 siblings, 0 replies; 5+ messages in thread
From: Kishon Vijay Abraham I @ 2016-08-31 11:32 UTC (permalink / raw)
To: Lee Jones; +Cc: david, linux-kernel
On Wednesday 31 August 2016 04:59 PM, Lee Jones wrote:
> On Tue, 30 Aug 2016, Kishon Vijay Abraham I wrote:
>
>> Hi Lee Jones,
>>
>> On Tuesday 30 August 2016 07:52 PM, Lee Jones wrote:
>>> On Wed, 10 Aug 2016, Kishon Vijay Abraham I wrote:
>>>
>>>> From: David Lechner <david@lechnology.com>
>>>>
>>>> Create a new header file for TI DA8XX SoC CFGCHIPx registers.
>>>> This will be used by a number of planned drivers including a new USB
>>>> PHY driver and common clock framework drivers.
>>>>
>>>> The same defines *will* be removed from the platform_data header,
>>>> once all the users start using the new syscon device header.
>>>>
>>>> This also fixes the following compiler error caused due to
>>>> a dependent patch not merged.
>>>> drivers/phy/phy-da8xx-usb.c:19:37:
>>>> fatal error: linux/mfd/da8xx-cfgchip.h: No such file or directory
>>>> #include <linux/mfd/da8xx-cfgchip.h>
>>>>
>>>> Signed-off-by: David Lechner <david@lechnology.com>
>>>> Acked-by: Lee Jones <lee.jones@linaro.org>
>>>> Reported-by: Arnd Bergmann <arnd@arndb.de>
>>>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>>>> ---
>>>> include/linux/mfd/da8xx-cfgchip.h | 153 +++++++++++++++++++++++++++++++++++++
>>>> 1 file changed, 153 insertions(+)
>>>
>>> Applied, thanks.
>>
>> I've already merged this in linux-phy tree since this was causing build
>> breakage. Can you drop this from your tree?
>
> I can, but I may need a pull-request depending on if anything breaks
> in my tree.
sure. This file was used only in the phy driver, so it shouldn't break anything.
Thanks
Kishon
>
>>>> diff --git a/include/linux/mfd/da8xx-cfgchip.h b/include/linux/mfd/da8xx-cfgchip.h
>>>> new file mode 100644
>>>> index 0000000..304985e
>>>> --- /dev/null
>>>> +++ b/include/linux/mfd/da8xx-cfgchip.h
>>>> @@ -0,0 +1,153 @@
>>>> +/*
>>>> + * TI DaVinci DA8xx CHIPCFGx registers for syscon consumers.
>>>> + *
>>>> + * Copyright (C) 2016 David Lechner <david@lechnology.com>
>>>> + *
>>>> + * This program is free software; you can redistribute it and/or modify
>>>> + * it under the terms of the GNU General Public License as published by
>>>> + * the Free Software Foundation; either version 2 of the License, or
>>>> + * (at your option) any later version.
>>>> + *
>>>> + * This program is distributed in the hope that it will be useful,
>>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>>>> + * GNU General Public License for more details.
>>>> + */
>>>> +
>>>> +#ifndef __LINUX_MFD_DA8XX_CFGCHIP_H
>>>> +#define __LINUX_MFD_DA8XX_CFGCHIP_H
>>>> +
>>>> +#include <linux/bitops.h>
>>>> +
>>>> +/* register offset (32-bit registers) */
>>>> +#define CFGCHIP(n) ((n) * 4)
>>>> +
>>>> +/* CFGCHIP0 (PLL0/EDMA3_0) register bits */
>>>> +#define CFGCHIP0_PLL_MASTER_LOCK BIT(4)
>>>> +#define CFGCHIP0_EDMA30TC1DBS(n) ((n) << 2)
>>>> +#define CFGCHIP0_EDMA30TC1DBS_MASK CFGCHIP0_EDMA30TC1DBS(0x3)
>>>> +#define CFGCHIP0_EDMA30TC1DBS_16 CFGCHIP0_EDMA30TC1DBS(0x0)
>>>> +#define CFGCHIP0_EDMA30TC1DBS_32 CFGCHIP0_EDMA30TC1DBS(0x1)
>>>> +#define CFGCHIP0_EDMA30TC1DBS_64 CFGCHIP0_EDMA30TC1DBS(0x2)
>>>> +#define CFGCHIP0_EDMA30TC0DBS(n) ((n) << 0)
>>>> +#define CFGCHIP0_EDMA30TC0DBS_MASK CFGCHIP0_EDMA30TC0DBS(0x3)
>>>> +#define CFGCHIP0_EDMA30TC0DBS_16 CFGCHIP0_EDMA30TC0DBS(0x0)
>>>> +#define CFGCHIP0_EDMA30TC0DBS_32 CFGCHIP0_EDMA30TC0DBS(0x1)
>>>> +#define CFGCHIP0_EDMA30TC0DBS_64 CFGCHIP0_EDMA30TC0DBS(0x2)
>>>> +
>>>> +/* CFGCHIP1 (eCAP/HPI/EDMA3_1/eHRPWM TBCLK/McASP0 AMUTEIN) register bits */
>>>> +#define CFGCHIP1_CAP2SRC(n) ((n) << 27)
>>>> +#define CFGCHIP1_CAP2SRC_MASK CFGCHIP1_CAP2SRC(0x1f)
>>>> +#define CFGCHIP1_CAP2SRC_ECAP_PIN CFGCHIP1_CAP2SRC(0x0)
>>>> +#define CFGCHIP1_CAP2SRC_MCASP0_TX CFGCHIP1_CAP2SRC(0x1)
>>>> +#define CFGCHIP1_CAP2SRC_MCASP0_RX CFGCHIP1_CAP2SRC(0x2)
>>>> +#define CFGCHIP1_CAP2SRC_EMAC_C0_RX_THRESHOLD CFGCHIP1_CAP2SRC(0x7)
>>>> +#define CFGCHIP1_CAP2SRC_EMAC_C0_RX CFGCHIP1_CAP2SRC(0x8)
>>>> +#define CFGCHIP1_CAP2SRC_EMAC_C0_TX CFGCHIP1_CAP2SRC(0x9)
>>>> +#define CFGCHIP1_CAP2SRC_EMAC_C0_MISC CFGCHIP1_CAP2SRC(0xa)
>>>> +#define CFGCHIP1_CAP2SRC_EMAC_C1_RX_THRESHOLD CFGCHIP1_CAP2SRC(0xb)
>>>> +#define CFGCHIP1_CAP2SRC_EMAC_C1_RX CFGCHIP1_CAP2SRC(0xc)
>>>> +#define CFGCHIP1_CAP2SRC_EMAC_C1_TX CFGCHIP1_CAP2SRC(0xd)
>>>> +#define CFGCHIP1_CAP2SRC_EMAC_C1_MISC CFGCHIP1_CAP2SRC(0xe)
>>>> +#define CFGCHIP1_CAP2SRC_EMAC_C2_RX_THRESHOLD CFGCHIP1_CAP2SRC(0xf)
>>>> +#define CFGCHIP1_CAP2SRC_EMAC_C2_RX CFGCHIP1_CAP2SRC(0x10)
>>>> +#define CFGCHIP1_CAP2SRC_EMAC_C2_TX CFGCHIP1_CAP2SRC(0x11)
>>>> +#define CFGCHIP1_CAP2SRC_EMAC_C2_MISC CFGCHIP1_CAP2SRC(0x12)
>>>> +#define CFGCHIP1_CAP1SRC(n) ((n) << 22)
>>>> +#define CFGCHIP1_CAP1SRC_MASK CFGCHIP1_CAP1SRC(0x1f)
>>>> +#define CFGCHIP1_CAP1SRC_ECAP_PIN CFGCHIP1_CAP1SRC(0x0)
>>>> +#define CFGCHIP1_CAP1SRC_MCASP0_TX CFGCHIP1_CAP1SRC(0x1)
>>>> +#define CFGCHIP1_CAP1SRC_MCASP0_RX CFGCHIP1_CAP1SRC(0x2)
>>>> +#define CFGCHIP1_CAP1SRC_EMAC_C0_RX_THRESHOLD CFGCHIP1_CAP1SRC(0x7)
>>>> +#define CFGCHIP1_CAP1SRC_EMAC_C0_RX CFGCHIP1_CAP1SRC(0x8)
>>>> +#define CFGCHIP1_CAP1SRC_EMAC_C0_TX CFGCHIP1_CAP1SRC(0x9)
>>>> +#define CFGCHIP1_CAP1SRC_EMAC_C0_MISC CFGCHIP1_CAP1SRC(0xa)
>>>> +#define CFGCHIP1_CAP1SRC_EMAC_C1_RX_THRESHOLD CFGCHIP1_CAP1SRC(0xb)
>>>> +#define CFGCHIP1_CAP1SRC_EMAC_C1_RX CFGCHIP1_CAP1SRC(0xc)
>>>> +#define CFGCHIP1_CAP1SRC_EMAC_C1_TX CFGCHIP1_CAP1SRC(0xd)
>>>> +#define CFGCHIP1_CAP1SRC_EMAC_C1_MISC CFGCHIP1_CAP1SRC(0xe)
>>>> +#define CFGCHIP1_CAP1SRC_EMAC_C2_RX_THRESHOLD CFGCHIP1_CAP1SRC(0xf)
>>>> +#define CFGCHIP1_CAP1SRC_EMAC_C2_RX CFGCHIP1_CAP1SRC(0x10)
>>>> +#define CFGCHIP1_CAP1SRC_EMAC_C2_TX CFGCHIP1_CAP1SRC(0x11)
>>>> +#define CFGCHIP1_CAP1SRC_EMAC_C2_MISC CFGCHIP1_CAP1SRC(0x12)
>>>> +#define CFGCHIP1_CAP0SRC(n) ((n) << 17)
>>>> +#define CFGCHIP1_CAP0SRC_MASK CFGCHIP1_CAP0SRC(0x1f)
>>>> +#define CFGCHIP1_CAP0SRC_ECAP_PIN CFGCHIP1_CAP0SRC(0x0)
>>>> +#define CFGCHIP1_CAP0SRC_MCASP0_TX CFGCHIP1_CAP0SRC(0x1)
>>>> +#define CFGCHIP1_CAP0SRC_MCASP0_RX CFGCHIP1_CAP0SRC(0x2)
>>>> +#define CFGCHIP1_CAP0SRC_EMAC_C0_RX_THRESHOLD CFGCHIP1_CAP0SRC(0x7)
>>>> +#define CFGCHIP1_CAP0SRC_EMAC_C0_RX CFGCHIP1_CAP0SRC(0x8)
>>>> +#define CFGCHIP1_CAP0SRC_EMAC_C0_TX CFGCHIP1_CAP0SRC(0x9)
>>>> +#define CFGCHIP1_CAP0SRC_EMAC_C0_MISC CFGCHIP1_CAP0SRC(0xa)
>>>> +#define CFGCHIP1_CAP0SRC_EMAC_C1_RX_THRESHOLD CFGCHIP1_CAP0SRC(0xb)
>>>> +#define CFGCHIP1_CAP0SRC_EMAC_C1_RX CFGCHIP1_CAP0SRC(0xc)
>>>> +#define CFGCHIP1_CAP0SRC_EMAC_C1_TX CFGCHIP1_CAP0SRC(0xd)
>>>> +#define CFGCHIP1_CAP0SRC_EMAC_C1_MISC CFGCHIP1_CAP0SRC(0xe)
>>>> +#define CFGCHIP1_CAP0SRC_EMAC_C2_RX_THRESHOLD CFGCHIP1_CAP0SRC(0xf)
>>>> +#define CFGCHIP1_CAP0SRC_EMAC_C2_RX CFGCHIP1_CAP0SRC(0x10)
>>>> +#define CFGCHIP1_CAP0SRC_EMAC_C2_TX CFGCHIP1_CAP0SRC(0x11)
>>>> +#define CFGCHIP1_CAP0SRC_EMAC_C2_MISC CFGCHIP1_CAP0SRC(0x12)
>>>> +#define CFGCHIP1_HPIBYTEAD BIT(16)
>>>> +#define CFGCHIP1_HPIENA BIT(15)
>>>> +#define CFGCHIP0_EDMA31TC0DBS(n) ((n) << 13)
>>>> +#define CFGCHIP0_EDMA31TC0DBS_MASK CFGCHIP0_EDMA31TC0DBS(0x3)
>>>> +#define CFGCHIP0_EDMA31TC0DBS_16 CFGCHIP0_EDMA31TC0DBS(0x0)
>>>> +#define CFGCHIP0_EDMA31TC0DBS_32 CFGCHIP0_EDMA31TC0DBS(0x1)
>>>> +#define CFGCHIP0_EDMA31TC0DBS_64 CFGCHIP0_EDMA31TC0DBS(0x2)
>>>> +#define CFGCHIP1_TBCLKSYNC BIT(12)
>>>> +#define CFGCHIP1_AMUTESEL0(n) ((n) << 0)
>>>> +#define CFGCHIP1_AMUTESEL0_MASK CFGCHIP1_AMUTESEL0(0xf)
>>>> +#define CFGCHIP1_AMUTESEL0_LOW CFGCHIP1_AMUTESEL0(0x0)
>>>> +#define CFGCHIP1_AMUTESEL0_BANK_0 CFGCHIP1_AMUTESEL0(0x1)
>>>> +#define CFGCHIP1_AMUTESEL0_BANK_1 CFGCHIP1_AMUTESEL0(0x2)
>>>> +#define CFGCHIP1_AMUTESEL0_BANK_2 CFGCHIP1_AMUTESEL0(0x3)
>>>> +#define CFGCHIP1_AMUTESEL0_BANK_3 CFGCHIP1_AMUTESEL0(0x4)
>>>> +#define CFGCHIP1_AMUTESEL0_BANK_4 CFGCHIP1_AMUTESEL0(0x5)
>>>> +#define CFGCHIP1_AMUTESEL0_BANK_5 CFGCHIP1_AMUTESEL0(0x6)
>>>> +#define CFGCHIP1_AMUTESEL0_BANK_6 CFGCHIP1_AMUTESEL0(0x7)
>>>> +#define CFGCHIP1_AMUTESEL0_BANK_7 CFGCHIP1_AMUTESEL0(0x8)
>>>> +
>>>> +/* CFGCHIP2 (USB PHY) register bits */
>>>> +#define CFGCHIP2_PHYCLKGD BIT(17)
>>>> +#define CFGCHIP2_VBUSSENSE BIT(16)
>>>> +#define CFGCHIP2_RESET BIT(15)
>>>> +#define CFGCHIP2_OTGMODE(n) ((n) << 13)
>>>> +#define CFGCHIP2_OTGMODE_MASK CFGCHIP2_OTGMODE(0x3)
>>>> +#define CFGCHIP2_OTGMODE_NO_OVERRIDE CFGCHIP2_OTGMODE(0x0)
>>>> +#define CFGCHIP2_OTGMODE_FORCE_HOST CFGCHIP2_OTGMODE(0x1)
>>>> +#define CFGCHIP2_OTGMODE_FORCE_DEVICE CFGCHIP2_OTGMODE(0x2)
>>>> +#define CFGCHIP2_OTGMODE_FORCE_HOST_VBUS_LOW CFGCHIP2_OTGMODE(0x3)
>>>> +#define CFGCHIP2_USB1PHYCLKMUX BIT(12)
>>>> +#define CFGCHIP2_USB2PHYCLKMUX BIT(11)
>>>> +#define CFGCHIP2_PHYPWRDN BIT(10)
>>>> +#define CFGCHIP2_OTGPWRDN BIT(9)
>>>> +#define CFGCHIP2_DATPOL BIT(8)
>>>> +#define CFGCHIP2_USB1SUSPENDM BIT(7)
>>>> +#define CFGCHIP2_PHY_PLLON BIT(6)
>>>> +#define CFGCHIP2_SESENDEN BIT(5)
>>>> +#define CFGCHIP2_VBDTCTEN BIT(4)
>>>> +#define CFGCHIP2_REFFREQ(n) ((n) << 0)
>>>> +#define CFGCHIP2_REFFREQ_MASK CFGCHIP2_REFFREQ(0xf)
>>>> +#define CFGCHIP2_REFFREQ_12MHZ CFGCHIP2_REFFREQ(0x1)
>>>> +#define CFGCHIP2_REFFREQ_24MHZ CFGCHIP2_REFFREQ(0x2)
>>>> +#define CFGCHIP2_REFFREQ_48MHZ CFGCHIP2_REFFREQ(0x3)
>>>> +#define CFGCHIP2_REFFREQ_19_2MHZ CFGCHIP2_REFFREQ(0x4)
>>>> +#define CFGCHIP2_REFFREQ_38_4MHZ CFGCHIP2_REFFREQ(0x5)
>>>> +#define CFGCHIP2_REFFREQ_13MHZ CFGCHIP2_REFFREQ(0x6)
>>>> +#define CFGCHIP2_REFFREQ_26MHZ CFGCHIP2_REFFREQ(0x7)
>>>> +#define CFGCHIP2_REFFREQ_20MHZ CFGCHIP2_REFFREQ(0x8)
>>>> +#define CFGCHIP2_REFFREQ_40MHZ CFGCHIP2_REFFREQ(0x9)
>>>> +
>>>> +/* CFGCHIP3 (EMAC/uPP/PLL1/ASYNC3/PRU/DIV4.5/EMIFA) register bits */
>>>> +#define CFGCHIP3_RMII_SEL BIT(8)
>>>> +#define CFGCHIP3_UPP_TX_CLKSRC BIT(6)
>>>> +#define CFGCHIP3_PLL1_MASTER_LOCK BIT(5)
>>>> +#define CFGCHIP3_ASYNC3_CLKSRC BIT(4)
>>>> +#define CFGCHIP3_PRUEVTSEL BIT(3)
>>>> +#define CFGCHIP3_DIV45PENA BIT(2)
>>>> +#define CFGCHIP3_EMA_CLKSRC BIT(1)
>>>> +
>>>> +/* CFGCHIP4 (McASP0 AMUNTEIN) register bits */
>>>> +#define CFGCHIP4_AMUTECLR0 BIT(0)
>>>> +
>>>> +#endif /* __LINUX_MFD_DA8XX_CFGCHIP_H */
>>>
>
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2016-08-31 11:33 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-08-10 13:19 [PATCH] mfd: da8xx-cfgchip: New header file for CFGCHIP registers Kishon Vijay Abraham I
2016-08-30 14:22 ` Lee Jones
2016-08-30 14:24 ` Kishon Vijay Abraham I
2016-08-31 11:29 ` Lee Jones
2016-08-31 11:32 ` Kishon Vijay Abraham I
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