From: Kumar Gala <galak@codeaurora.org>
To: Gabriel FERNANDEZ <gabriel.fernandez@st.com>
Cc: Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Srinivas Kandagatla <srinivas.kandagatla@gmail.com>,
Maxime Coquelin <maxime.coquelin@st.com>,
Patrice Chotard <patrice.chotard@st.com>,
Russell King <linux@arm.linux.org.uk>,
Bjorn Helgaas <bhelgaas@google.com>,
Mohit Kumar <mohit.kumar@st.com>,
Jingoo Han <jg1.han@samsung.com>,
Lucas Stach <l.stach@pengutronix.de>,
Fabrice Gasnier <fabrice.gasnier@st.com>,
Kishon Vijay Abraham I <kishon@ti.com>,
Andrew Morton <akpm@linux-foundation.org>,
"David S. Miller" <davem@davemloft.net>,
Greg KH <gregkh@linuxfoundation.org>,
Mauro Carvalho Chehab <mchehab@osg.samsung.com>,
Joe Perches <joe@perches.com>, Tejun Heo <tj@kernel.org>,
Arnd Bergmann <arnd@arndb.de>,
Viresh Kumar <viresh.kumar@linaro.org>,
Thierry Reding <treding@nvidia.com>,
Phil Edworthy <phil.edworthy@renesas.com>,
Minghuan Lian <Minghuan.Lian@freescale.com>,
Tanmay Inamdar <tinamdar@apm.com>,
m-karicheri2@ti.com, Sachin Kamat <sachin.kamat@samsung.com>,
Andrew Lunn <andrew@lunn.ch>, Liviu Dudau <liviu.dudau@arm.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, kernel@stlinux.com,
linux-pci@vger.kernel.org, Lee Jones <lee.jones@linaro.org>,
Gabriel Fernandez <gabriel.fernandez@linaro.org>
Subject: Re: [PATCH v2 4/5] PCI: designware: Add disable IO support
Date: Mon, 16 Mar 2015 13:00:51 -0500 [thread overview]
Message-ID: <582D947C-1229-4DD9-BC82-812D1560C49E@codeaurora.org> (raw)
In-Reply-To: <1426515635-9466-5-git-send-email-gabriel.fernandez@linaro.org>
On Mar 16, 2015, at 9:20 AM, Gabriel FERNANDEZ <gabriel.fernandez@st.com> wrote:
> ST sti SoCs PCIe IPs are built around DesignWare IP Core.
> But in these SoCs PCIe IP doesn't support IO.
>
> This patch adds the possibility to disable it through
> a DT property, by creating an empty IO window and by
> removing PCI_COMMAND_IO from the setup register.
>
> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
> ---
> .../devicetree/bindings/pci/designware-pcie.txt | 2 ++
> drivers/pci/host/pcie-designware.c | 24 ++++++++++++++++++++--
> drivers/pci/host/pcie-designware.h | 1 +
> 3 files changed, 25 insertions(+), 2 deletions(-)
Why not just update the code such that if the ranges doesn’t have an IO space rather than introducing a new DT property?
- k
>
> diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt
> index 9f4faa8..40544d4 100644
> --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
> @@ -26,3 +26,5 @@ Optional properties:
> - bus-range: PCI bus numbers covered (it is recommended for new devicetrees to
> specify this property, to keep backwards compatibility a range of 0x00-0xff
> is assumed if not present)
> +- disable_io_support: set this property for PCIe host controller without IO
> + port access
> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> index 1f4ea6f..f9d70f5 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -471,6 +471,9 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
> return -EINVAL;
> }
>
> + pp->disable_io_support = of_property_read_bool(np,
> + "disable_io_support");
> +
> if (IS_ENABLED(CONFIG_PCI_MSI)) {
> if (!pp->ops->msi_host_init) {
> pp->irq_domain = irq_domain_add_linear(pp->dev->of_node,
> @@ -704,6 +707,7 @@ static struct pci_ops dw_pcie_ops = {
> static int dw_pcie_setup(int nr, struct pci_sys_data *sys)
> {
> struct pcie_port *pp;
> + struct resource *res;
>
> pp = sys_to_pcie(sys);
>
> @@ -719,6 +723,18 @@ static int dw_pcie_setup(int nr, struct pci_sys_data *sys)
> pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset);
> pci_add_resource(&sys->resources, &pp->busn);
>
> + if (pp->disable_io_support) {
> + /* This PCIe controller does not support IO, set an empty one */
> + res = devm_kzalloc(pp->dev, sizeof(*res), GFP_KERNEL);
> + if (res) {
> + res->start = 0;
> + res->end = 0;
> + res->name = "PCIe empty IO space";
> + res->flags = IORESOURCE_IO;
> + pci_add_resource(&sys->resources, res);
Do we really need an empty resource? What happens if we just dont have one?
> + }
> + }
> +
> return 1;
> }
>
> @@ -822,8 +838,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
> /* setup command register */
> dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
> val &= 0xffff0000;
> - val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
> - PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
> +
> + if (!pp->disable_io_support)
> + val |= PCI_COMMAND_IO;
> +
> + val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
> +
> dw_pcie_writel_rc(pp, val, PCI_COMMAND);
> }
>
> diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
> index d0bbd27..027045d 100644
> --- a/drivers/pci/host/pcie-designware.h
> +++ b/drivers/pci/host/pcie-designware.h
> @@ -52,6 +52,7 @@ struct pcie_port {
> int msi_irq;
> struct irq_domain *irq_domain;
> unsigned long msi_data;
> + bool disable_io_support;
> DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
> };
>
> --
> 1.9.1
>
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2015-03-16 18:01 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-16 14:20 [PATCH v2 0/5] PCI: st: provide support for dw pcie Gabriel FERNANDEZ
2015-03-16 14:20 ` [PATCH v2 1/5] ARM: STi: Kconfig update for PCIe support Gabriel FERNANDEZ
2015-03-16 14:20 ` [PATCH v2 2/5] PCI: st: Add Device Tree bindings for sti pcie Gabriel FERNANDEZ
2015-03-17 11:42 ` Liviu Dudau
2015-03-30 12:28 ` Gabriel Fernandez
2015-03-16 14:20 ` [PATCH v2 3/5] PCI: st: Provide support for the sti PCIe controller Gabriel FERNANDEZ
2015-03-16 15:11 ` Paul Bolle
2015-03-17 7:53 ` Gabriel Fernandez
2015-03-18 8:49 ` Fabrice Gasnier
2015-03-18 10:35 ` Paul Bolle
2015-03-31 9:11 ` Gabriel Fernandez
2015-04-09 12:43 ` Bjorn Helgaas
2015-03-17 10:35 ` Kishon Vijay Abraham I
2015-03-30 12:41 ` Gabriel Fernandez
2015-03-16 14:20 ` [PATCH v2 4/5] PCI: designware: Add disable IO support Gabriel FERNANDEZ
2015-03-16 17:53 ` Srinivas Kandagatla
2015-03-17 7:49 ` Gabriel Fernandez
2015-03-16 18:00 ` Kumar Gala [this message]
2015-03-16 20:00 ` Arnd Bergmann
2015-03-17 7:41 ` Gabriel Fernandez
2015-03-16 14:20 ` [PATCH v2 5/5] MAINTAINERS: Add pci-st.c to ARCH/STI architecture Gabriel FERNANDEZ
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=582D947C-1229-4DD9-BC82-812D1560C49E@codeaurora.org \
--to=galak@codeaurora.org \
--cc=Minghuan.Lian@freescale.com \
--cc=akpm@linux-foundation.org \
--cc=andrew@lunn.ch \
--cc=arnd@arndb.de \
--cc=bhelgaas@google.com \
--cc=davem@davemloft.net \
--cc=devicetree@vger.kernel.org \
--cc=fabrice.gasnier@st.com \
--cc=gabriel.fernandez@linaro.org \
--cc=gabriel.fernandez@st.com \
--cc=gregkh@linuxfoundation.org \
--cc=ijc+devicetree@hellion.org.uk \
--cc=jg1.han@samsung.com \
--cc=joe@perches.com \
--cc=kernel@stlinux.com \
--cc=kishon@ti.com \
--cc=l.stach@pengutronix.de \
--cc=lee.jones@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux@arm.linux.org.uk \
--cc=liviu.dudau@arm.com \
--cc=m-karicheri2@ti.com \
--cc=mark.rutland@arm.com \
--cc=maxime.coquelin@st.com \
--cc=mchehab@osg.samsung.com \
--cc=mohit.kumar@st.com \
--cc=patrice.chotard@st.com \
--cc=pawel.moll@arm.com \
--cc=phil.edworthy@renesas.com \
--cc=robh+dt@kernel.org \
--cc=sachin.kamat@samsung.com \
--cc=srinivas.kandagatla@gmail.com \
--cc=tinamdar@apm.com \
--cc=tj@kernel.org \
--cc=treding@nvidia.com \
--cc=viresh.kumar@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).