* [PATCH 0/3] Meson8b: add the CPU clock post-dividers
@ 2018-11-16 20:53 Martin Blumenstingl
2018-11-16 20:53 ` [PATCH 1/3] dt-bindings: clock: meson8b: export the CPU post dividers Martin Blumenstingl
` (4 more replies)
0 siblings, 5 replies; 7+ messages in thread
From: Martin Blumenstingl @ 2018-11-16 20:53 UTC (permalink / raw)
To: linux-amlogic, narmstrong, jbrunet
Cc: mturquette, sboyd, linux-clk, linux-arm-kernel, linux-kernel,
Martin Blumenstingl
This is the successor to my previous series "meson8b: add the CPU_DIV16
clock for the ARM TWD" from [0]. I decided to not send this as v2 of
the original series because the PERIPH clock is not the CPU_DIV16 clock.
It's not clear whether a CPU_DIV16 clock exists.
With this series we get all the CPU_CLK post-dividers as listed in the
public S805 datasheet [1] on pages 31 and 32:
- ABP
- PERIPH (used as input for the ARM global timer and ARM TWD timer)
- AXI
- L2 DRAM
Each of these clocks has a register called "..._CLK_DIS" which is
documented as a "just in case" bit:
"Set to 1 to manually disable the [...] clock when changing the mux
selection. Typically this bit is set to 0 since the clock muxes can
switch without glitches."
Since we're not supposed to touch that register we're setting
CLK_IS_CRITICAL for these clocks in the driver.
The result of this is that we can use the PERIPH clock which clocks
the ARM TWD timer. I will send a separate series to add the TWD timer.
[0] http://lists.infradead.org/pipermail/linux-amlogic/2018-July/007890.html
[1] https://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
Martin Blumenstingl (3):
dt-bindings: clock: meson8b: export the CPU post dividers
clk: meson: meson8b: rename cpu_div2/cpu_div3 to
cpu_in_div2/cpu_in_div3
clk: meson: meson8b: add the CPU clock post divider clocks
drivers/clk/meson/meson8b.c | 268 ++++++++++++++++++++++-
drivers/clk/meson/meson8b.h | 17 +-
include/dt-bindings/clock/meson8b-clkc.h | 4 +
3 files changed, 276 insertions(+), 13 deletions(-)
--
2.19.1
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH 1/3] dt-bindings: clock: meson8b: export the CPU post dividers 2018-11-16 20:53 [PATCH 0/3] Meson8b: add the CPU clock post-dividers Martin Blumenstingl @ 2018-11-16 20:53 ` Martin Blumenstingl 2018-11-16 20:53 ` [PATCH 2/3] clk: meson: meson8b: rename cpu_div2/cpu_div3 to cpu_in_div2/cpu_in_div3 Martin Blumenstingl ` (3 subsequent siblings) 4 siblings, 0 replies; 7+ messages in thread From: Martin Blumenstingl @ 2018-11-16 20:53 UTC (permalink / raw) To: linux-amlogic, narmstrong, jbrunet Cc: mturquette, sboyd, linux-clk, linux-arm-kernel, linux-kernel, Martin Blumenstingl There are four CPU clock post dividers: - ABP - PERIPH (used as input for the ARM global timer and ARM TWD timer) - AXI - L2 DRAM Export these so we can use them in .dts files. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> --- include/dt-bindings/clock/meson8b-clkc.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h index a60f47b49231..5fe2923382d0 100644 --- a/include/dt-bindings/clock/meson8b-clkc.h +++ b/include/dt-bindings/clock/meson8b-clkc.h @@ -103,5 +103,9 @@ #define CLKID_MPLL1 94 #define CLKID_MPLL2 95 #define CLKID_NAND_CLK 112 +#define CLKID_ABP 124 +#define CLKID_PERIPH 126 +#define CLKID_AXI 128 +#define CLKID_L2_DRAM 130 #endif /* __MESON8B_CLKC_H */ -- 2.19.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/3] clk: meson: meson8b: rename cpu_div2/cpu_div3 to cpu_in_div2/cpu_in_div3 2018-11-16 20:53 [PATCH 0/3] Meson8b: add the CPU clock post-dividers Martin Blumenstingl 2018-11-16 20:53 ` [PATCH 1/3] dt-bindings: clock: meson8b: export the CPU post dividers Martin Blumenstingl @ 2018-11-16 20:53 ` Martin Blumenstingl 2018-11-16 20:53 ` [PATCH 3/3] clk: meson: meson8b: add the CPU clock post divider clocks Martin Blumenstingl ` (2 subsequent siblings) 4 siblings, 0 replies; 7+ messages in thread From: Martin Blumenstingl @ 2018-11-16 20:53 UTC (permalink / raw) To: linux-amlogic, narmstrong, jbrunet Cc: mturquette, sboyd, linux-clk, linux-arm-kernel, linux-kernel, Martin Blumenstingl The "cpu_div2" and "cpu_div3" take "cpu_in" as input and divide that by 2 or 3. The clock controller can also generate various CPU clock post-dividers (2, 3, 4, 5, 6, 7, 8) which are derived from "cpu_clk". When adding support for these post-dividers our clock naming could be misleading as we have "cpu_div2" as well as "cpu_clk_div2". Rename the existing "cpu_in" dividers so the name of the divider's parent is part of the divider clock's name. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> --- drivers/clk/meson/meson8b.c | 20 ++++++++++---------- drivers/clk/meson/meson8b.h | 4 ++-- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index b3bdc7e05441..010dccc86b5d 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -560,11 +560,11 @@ static struct clk_regmap meson8b_cpu_in_sel = { }, }; -static struct clk_fixed_factor meson8b_cpu_div2 = { +static struct clk_fixed_factor meson8b_cpu_in_div2 = { .mult = 1, .div = 2, .hw.init = &(struct clk_init_data){ - .name = "cpu_div2", + .name = "cpu_in_div2", .ops = &clk_fixed_factor_ops, .parent_names = (const char *[]){ "cpu_in_sel" }, .num_parents = 1, @@ -572,11 +572,11 @@ static struct clk_fixed_factor meson8b_cpu_div2 = { }, }; -static struct clk_fixed_factor meson8b_cpu_div3 = { +static struct clk_fixed_factor meson8b_cpu_in_div3 = { .mult = 1, .div = 3, .hw.init = &(struct clk_init_data){ - .name = "cpu_div3", + .name = "cpu_in_div3", .ops = &clk_fixed_factor_ops, .parent_names = (const char *[]){ "cpu_in_sel" }, .num_parents = 1, @@ -626,12 +626,12 @@ static struct clk_regmap meson8b_cpu_scale_out_sel = { .ops = &clk_regmap_mux_ops, /* * NOTE: We are skipping the parent with value 0x2 (which is - * "cpu_div3") because it results in a duty cycle of 33% which - * makes the system unstable and can result in a lockup of the - * whole system. + * "cpu_in_div3") because it results in a duty cycle of 33% + * which makes the system unstable and can result in a lockup + * of the whole system. */ .parent_names = (const char *[]) { "cpu_in_sel", - "cpu_div2", + "cpu_in_div2", "cpu_scale_div" }, .num_parents = 3, .flags = CLK_SET_RATE_PARENT, @@ -889,8 +889,8 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = { [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw, [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw, [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw, - [CLKID_CPU_DIV2] = &meson8b_cpu_div2.hw, - [CLKID_CPU_DIV3] = &meson8b_cpu_div3.hw, + [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw, + [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw, [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw, [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw, [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw, diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h index 1c6fb180e6a2..9cba34c6cb92 100644 --- a/drivers/clk/meson/meson8b.h +++ b/drivers/clk/meson/meson8b.h @@ -63,8 +63,8 @@ #define CLKID_MPLL1_DIV 97 #define CLKID_MPLL2_DIV 98 #define CLKID_CPU_IN_SEL 99 -#define CLKID_CPU_DIV2 100 -#define CLKID_CPU_DIV3 101 +#define CLKID_CPU_IN_DIV2 100 +#define CLKID_CPU_IN_DIV3 101 #define CLKID_CPU_SCALE_DIV 102 #define CLKID_CPU_SCALE_OUT_SEL 103 #define CLKID_MPLL_PREDIV 104 -- 2.19.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 3/3] clk: meson: meson8b: add the CPU clock post divider clocks 2018-11-16 20:53 [PATCH 0/3] Meson8b: add the CPU clock post-dividers Martin Blumenstingl 2018-11-16 20:53 ` [PATCH 1/3] dt-bindings: clock: meson8b: export the CPU post dividers Martin Blumenstingl 2018-11-16 20:53 ` [PATCH 2/3] clk: meson: meson8b: rename cpu_div2/cpu_div3 to cpu_in_div2/cpu_in_div3 Martin Blumenstingl @ 2018-11-16 20:53 ` Martin Blumenstingl 2018-11-16 20:55 ` [PATCH 0/3] Meson8b: add the CPU clock post-dividers Martin Blumenstingl 2018-11-22 9:05 ` Jerome Brunet 4 siblings, 0 replies; 7+ messages in thread From: Martin Blumenstingl @ 2018-11-16 20:53 UTC (permalink / raw) To: linux-amlogic, narmstrong, jbrunet Cc: mturquette, sboyd, linux-clk, linux-arm-kernel, linux-kernel, Martin Blumenstingl There are four CPU clock post dividers: - ABP - PERIPH (used for the ARM global timer and ARM TWD timer) - AXI - L2 DRAM Each of these clocks consists of two clocks: - a mux to select between "cpu_clk" divided by 2, 3, 4, 5, 6, 7 or 8 - a "_clk_dis" gate (the public S805 datasheet states that this should be set to 1 to disable the clock. the default value is 0. there is also a hint that these are "just in case" bits which is why I set these clocks to CLK_IS_CRITICAL). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> --- drivers/clk/meson/meson8b.c | 248 ++++++++++++++++++++++++++++++++++++ drivers/clk/meson/meson8b.h | 13 +- 2 files changed, 260 insertions(+), 1 deletion(-) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 010dccc86b5d..1b192f823bf8 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -704,6 +704,231 @@ static struct clk_regmap meson8b_nand_clk_gate = { }, }; +static struct clk_fixed_factor meson8b_cpu_clk_div2 = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "cpu_clk_div2", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "cpu_clk" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor meson8b_cpu_clk_div3 = { + .mult = 1, + .div = 3, + .hw.init = &(struct clk_init_data){ + .name = "cpu_clk_div3", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "cpu_clk" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor meson8b_cpu_clk_div4 = { + .mult = 1, + .div = 4, + .hw.init = &(struct clk_init_data){ + .name = "cpu_clk_div4", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "cpu_clk" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor meson8b_cpu_clk_div5 = { + .mult = 1, + .div = 5, + .hw.init = &(struct clk_init_data){ + .name = "cpu_clk_div5", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "cpu_clk" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor meson8b_cpu_clk_div6 = { + .mult = 1, + .div = 6, + .hw.init = &(struct clk_init_data){ + .name = "cpu_clk_div6", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "cpu_clk" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor meson8b_cpu_clk_div7 = { + .mult = 1, + .div = 7, + .hw.init = &(struct clk_init_data){ + .name = "cpu_clk_div7", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "cpu_clk" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor meson8b_cpu_clk_div8 = { + .mult = 1, + .div = 8, + .hw.init = &(struct clk_init_data){ + .name = "cpu_clk_div8", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "cpu_clk" }, + .num_parents = 1, + }, +}; + +static u32 mux_table_abp[] = { 1, 2, 3, 4, 5, 6, 7 }; +static struct clk_regmap meson8b_abp_clk_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_SYS_CPU_CLK_CNTL1, + .mask = 0x7, + .shift = 3, + .table = mux_table_abp, + }, + .hw.init = &(struct clk_init_data){ + .name = "abp_clk_sel", + .ops = &clk_regmap_mux_ops, + .parent_names = (const char *[]){ "cpu_clk_div2", + "cpu_clk_div3", + "cpu_clk_div4", + "cpu_clk_div5", + "cpu_clk_div6", + "cpu_clk_div7", + "cpu_clk_div8", }, + .num_parents = 7, + }, +}; + +static struct clk_regmap meson8b_abp_clk_gate = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_SYS_CPU_CLK_CNTL1, + .bit_idx = 16, + .flags = CLK_GATE_SET_TO_DISABLE, + }, + .hw.init = &(struct clk_init_data){ + .name = "abp_clk_dis", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "abp_clk_sel" }, + .num_parents = 1, + .flags = (CLK_SET_RATE_PARENT | + CLK_IS_CRITICAL), + }, +}; + +static struct clk_regmap meson8b_periph_clk_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_SYS_CPU_CLK_CNTL1, + .mask = 0x7, + .shift = 6, + }, + .hw.init = &(struct clk_init_data){ + .name = "periph_clk_sel", + .ops = &clk_regmap_mux_ops, + .parent_names = (const char *[]){ "cpu_clk_div2", + "cpu_clk_div3", + "cpu_clk_div4", + "cpu_clk_div5", + "cpu_clk_div6", + "cpu_clk_div7", + "cpu_clk_div8", }, + .num_parents = 7, + }, +}; + +static struct clk_regmap meson8b_periph_clk_gate = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_SYS_CPU_CLK_CNTL1, + .bit_idx = 17, + .flags = CLK_GATE_SET_TO_DISABLE, + }, + .hw.init = &(struct clk_init_data){ + .name = "periph_clk_dis", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "periph_clk_sel" }, + .num_parents = 1, + .flags = (CLK_SET_RATE_PARENT | + CLK_IS_CRITICAL), + }, +}; + +static u32 mux_table_axi[] = { 1, 2, 3, 4, 5, 6, 7 }; +static struct clk_regmap meson8b_axi_clk_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_SYS_CPU_CLK_CNTL1, + .mask = 0x7, + .shift = 9, + .table = mux_table_axi, + }, + .hw.init = &(struct clk_init_data){ + .name = "axi_clk_sel", + .ops = &clk_regmap_mux_ops, + .parent_names = (const char *[]){ "cpu_clk_div2", + "cpu_clk_div3", + "cpu_clk_div4", + "cpu_clk_div5", + "cpu_clk_div6", + "cpu_clk_div7", + "cpu_clk_div8", }, + .num_parents = 7, + }, +}; + +static struct clk_regmap meson8b_axi_clk_gate = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_SYS_CPU_CLK_CNTL1, + .bit_idx = 18, + .flags = CLK_GATE_SET_TO_DISABLE, + }, + .hw.init = &(struct clk_init_data){ + .name = "axi_clk_dis", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "axi_clk_sel" }, + .num_parents = 1, + .flags = (CLK_SET_RATE_PARENT | + CLK_IS_CRITICAL), + }, +}; + +static struct clk_regmap meson8b_l2_dram_clk_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_SYS_CPU_CLK_CNTL1, + .mask = 0x7, + .shift = 12, + }, + .hw.init = &(struct clk_init_data){ + .name = "l2_dram_clk_sel", + .ops = &clk_regmap_mux_ops, + .parent_names = (const char *[]){ "cpu_clk_div2", + "cpu_clk_div3", + "cpu_clk_div4", + "cpu_clk_div5", + "cpu_clk_div6", + "cpu_clk_div7", + "cpu_clk_div8", }, + .num_parents = 7, + }, +}; + +static struct clk_regmap meson8b_l2_dram_clk_gate = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_SYS_CPU_CLK_CNTL1, + .bit_idx = 19, + .flags = CLK_GATE_SET_TO_DISABLE, + }, + .hw.init = &(struct clk_init_data){ + .name = "l2_dram_clk_dis", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "l2_dram_clk_sel" }, + .num_parents = 1, + .flags = (CLK_SET_RATE_PARENT | + CLK_IS_CRITICAL), + }, +}; + /* Everything Else (EE) domain gates */ static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0); @@ -905,6 +1130,21 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = { [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw, [CLKID_PLL_VID_DCO] = &meson8b_vid_pll_dco.hw, [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw, + [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw, + [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw, + [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw, + [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw, + [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw, + [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw, + [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw, + [CLKID_ABP_SEL] = &meson8b_abp_clk_sel.hw, + [CLKID_ABP] = &meson8b_abp_clk_gate.hw, + [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw, + [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw, + [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw, + [CLKID_AXI] = &meson8b_axi_clk_gate.hw, + [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw, + [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw, [CLK_NR_CLKS] = NULL, }, .num = CLK_NR_CLKS, @@ -1016,6 +1256,14 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = { &meson8b_fixed_pll_dco, &meson8b_vid_pll_dco, &meson8b_sys_pll_dco, + &meson8b_abp_clk_sel, + &meson8b_abp_clk_gate, + &meson8b_periph_clk_sel, + &meson8b_periph_clk_gate, + &meson8b_axi_clk_sel, + &meson8b_axi_clk_gate, + &meson8b_l2_dram_clk_sel, + &meson8b_l2_dram_clk_gate, }; static const struct meson8b_clk_reset_line { diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h index 9cba34c6cb92..0abb331162ab 100644 --- a/drivers/clk/meson/meson8b.h +++ b/drivers/clk/meson/meson8b.h @@ -78,8 +78,19 @@ #define CLKID_PLL_FIXED_DCO 113 #define CLKID_PLL_VID_DCO 114 #define CLKID_PLL_SYS_DCO 115 +#define CLKID_CPU_CLK_DIV2 116 +#define CLKID_CPU_CLK_DIV3 117 +#define CLKID_CPU_CLK_DIV4 118 +#define CLKID_CPU_CLK_DIV5 119 +#define CLKID_CPU_CLK_DIV6 120 +#define CLKID_CPU_CLK_DIV7 121 +#define CLKID_CPU_CLK_DIV8 122 +#define CLKID_ABP_SEL 123 +#define CLKID_PERIPH_SEL 125 +#define CLKID_AXI_SEL 127 +#define CLKID_L2_DRAM_SEL 129 -#define CLK_NR_CLKS 116 +#define CLK_NR_CLKS 131 /* * include the CLKID and RESETID that have -- 2.19.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 0/3] Meson8b: add the CPU clock post-dividers 2018-11-16 20:53 [PATCH 0/3] Meson8b: add the CPU clock post-dividers Martin Blumenstingl ` (2 preceding siblings ...) 2018-11-16 20:53 ` [PATCH 3/3] clk: meson: meson8b: add the CPU clock post divider clocks Martin Blumenstingl @ 2018-11-16 20:55 ` Martin Blumenstingl 2018-11-22 9:05 ` Jerome Brunet 4 siblings, 0 replies; 7+ messages in thread From: Martin Blumenstingl @ 2018-11-16 20:55 UTC (permalink / raw) To: linux-amlogic, Neil Armstrong, jbrunet Cc: mturquette, sboyd, linux-clk, linux-arm-kernel, linux-kernel On Fri, Nov 16, 2018 at 9:53 PM Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote: > > This is the successor to my previous series "meson8b: add the CPU_DIV16 > clock for the ARM TWD" from [0]. I decided to not send this as v2 of > the original series because the PERIPH clock is not the CPU_DIV16 clock. > It's not clear whether a CPU_DIV16 clock exists. > > With this series we get all the CPU_CLK post-dividers as listed in the > public S805 datasheet [1] on pages 31 and 32: > - ABP > - PERIPH (used as input for the ARM global timer and ARM TWD timer) > - AXI > - L2 DRAM > > Each of these clocks has a register called "..._CLK_DIS" which is > documented as a "just in case" bit: > "Set to 1 to manually disable the [...] clock when changing the mux > selection. Typically this bit is set to 0 since the clock muxes can > switch without glitches." > Since we're not supposed to touch that register we're setting > CLK_IS_CRITICAL for these clocks in the driver. > > The result of this is that we can use the PERIPH clock which clocks > the ARM TWD timer. I will send a separate series to add the TWD timer. > > > [0] http://lists.infradead.org/pipermail/linux-amlogic/2018-July/007890.html > [1] https://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf > > Martin Blumenstingl (3): > dt-bindings: clock: meson8b: export the CPU post dividers > clk: meson: meson8b: rename cpu_div2/cpu_div3 to > cpu_in_div2/cpu_in_div3 > clk: meson: meson8b: add the CPU clock post divider clocks I ran various tests for the PERIPH clock by enabling the TWD timer without specifying a clock. In that case the TWD driver will try to auto-detect the PERIPH clock rate. my results confirm that this implementation is correct: case #1: EC-100 with it's default boot settings: [ 0.000252] smp_twd: clock not found -2 [ 0.000736] Calibrating local timer... 197.86MHz. # cat /sys/kernel/debug/clk/clk_summary enable prepare protect duty clock count count count rate accuracy phase cycle --------------------------------------------------------------------------------------------- ... sys_pll_dco 1 1 0 1584000000 0 0 50000 sys_pll 1 1 0 792000000 0 0 50000 cpu_in_sel 1 1 0 792000000 0 0 50000 cpu_scale_out_sel 1 1 0 792000000 0 0 50000 cpu_clk 4 4 0 792000000 0 0 50000 ... cpu_clk_div4 2 2 0 198000000 0 0 50000 axi_clk_sel 1 1 0 198000000 0 0 50000 axi_clk_dis 1 1 0 198000000 0 0 50000 periph_clk_sel 1 1 0 198000000 0 0 50000 periph_clk_dis 1 1 0 198000000 0 0 50000 ... case #2: switch the parent of the cpu_in_sel clock to xtal: m8b_m201_1G#md.l 0xC110419C 1 c110419c: 000000b1 .... m8b_m201_1G#mw.l 0xC110419C 0xb0 1 m8b_m201_1G#md.l 0xC110419C c110419c: 000000b0 .... [ 0.007005] smp_twd: clock not found -2 [ 0.022680] Calibrating local timer... 5.98MHz. # cat /sys/kernel/debug/clk/clk_summary enable prepare protect duty clock count count count rate accuracy phase cycle --------------------------------------------------------------------------------------------- xtal 4 4 0 24000000 0 0 50000 ... cpu_in_sel 1 1 0 24000000 0 0 50000 cpu_scale_out_sel 1 1 0 24000000 0 0 50000 cpu_clk 4 4 0 24000000 0 0 50000 ... cpu_clk_div4 2 2 0 6000000 0 0 50000 axi_clk_sel 1 1 0 6000000 0 0 50000 axi_clk_dis 1 1 0 6000000 0 0 50000 periph_clk_sel 1 1 0 6000000 0 0 50000 periph_clk_dis 1 1 0 6000000 0 0 50000 ... case #3: set cpu_scale_div to cpu_in_sel/6 and use cpu_scale_div as parent of cpu_scale_out_sel m8b_m201_1G#mw.l 0xC110419C 0x30 1 m8b_m201_1G#md.l 0xC110415C 1 c110415c: 800016a2 .... m8b_m201_1G#mw.l 0xC110415C 0x802016A2 1 m8b_m201_1G#mw.l 0xC110419C 0xbd 1 [ 0.001317] smp_twd: clock not found -2 [ 0.003907] Calibrating local timer... 32.93MHz. # cat /sys/kernel/debug/clk/clk_summary enable prepare protect duty clock count count count rate accuracy phase cycle --------------------------------------------------------------------------------------------- ... sys_pll_dco 1 1 0 1584000000 0 0 50000 sys_pll 1 1 0 792000000 0 0 50000 cpu_in_sel 1 1 0 792000000 0 0 50000 cpu_scale_div 1 1 0 132000000 0 0 50000 cpu_scale_out_sel 1 1 0 132000000 0 0 50000 cpu_clk 4 4 0 132000000 0 0 50000 ... cpu_clk_div4 2 2 0 33000000 0 0 50000 axi_clk_sel 1 1 0 33000000 0 0 50000 axi_clk_dis 1 1 0 33000000 0 0 50000 periph_clk_sel 1 1 0 33000000 0 0 50000 periph_clk_dis 1 1 0 33000000 0 0 50000 ... case #4: set cpu_scale_div to cpu_in_sel/4 and use cpu_scale_div as parent of cpu_scale_out_sel m8b_m201_1G#mw.l 0xC110419C 0x30 1 m8b_m201_1G#md.l 0xC110415C 1 c110415c: 800016a2 .... m8b_m201_1G#mw.l 0xC110415C 0x801016A2 1 m8b_m201_1G#mw.l 0xC110419C 0xbd 1 [ 0.001317] smp_twd: clock not found -2 [ 0.002636] Calibrating local timer... 49.42MHz. # cat /sys/kernel/debug/clk/clk_summary enable prepare protect duty clock count count count rate accuracy phase cycle --------------------------------------------------------------------------------------------- ... sys_pll_dco 1 1 0 1584000000 0 0 50000 sys_pll 1 1 0 792000000 0 0 50000 cpu_in_sel 1 1 0 792000000 0 0 50000 cpu_scale_div 1 1 0 198000000 0 0 50000 cpu_scale_out_sel 1 1 0 198000000 0 0 50000 cpu_clk 4 4 0 198000000 0 0 50000 ... cpu_clk_div4 2 2 0 49500000 0 0 50000 axi_clk_sel 1 1 0 49500000 0 0 50000 axi_clk_dis 1 1 0 49500000 0 0 50000 periph_clk_sel 1 1 0 49500000 0 0 50000 periph_clk_dis 1 1 0 49500000 0 0 50000 ... case #5: set cpu_scale_div to cpu_in_sel/12 and use cpu_scale_div as parent of cpu_scale_out_sel m8b_m201_1G#mw.l 0xC110419C 0x30 1 m8b_m201_1G#md.l 0xC110415C 1 c110415c: 800016a2 .... m8b_m201_1G#mw.l 0xC110415C 0x805016A2 1 m8b_m201_1G#mw.l 0xC110419C 0xbd 1 [ 0.001317] smp_twd: clock not found -2 [ 0.007728] Calibrating local timer... 16.44MHz. # cat /sys/kernel/debug/clk/clk_summary enable prepare protect duty clock count count count rate accuracy phase cycle --------------------------------------------------------------------------------------------- ... sys_pll_dco 1 1 0 1584000000 0 0 50000 sys_pll 1 1 0 792000000 0 0 50000 cpu_in_sel 1 1 0 792000000 0 0 50000 cpu_scale_div 1 1 0 66000000 0 0 50000 cpu_scale_out_sel 1 1 0 66000000 0 0 50000 cpu_clk 4 4 0 66000000 0 0 50000 ... cpu_clk_div4 2 2 0 16500000 0 0 50000 axi_clk_sel 1 1 0 16500000 0 0 50000 axi_clk_dis 1 1 0 16500000 0 0 50000 periph_clk_sel 1 1 0 16500000 0 0 50000 periph_clk_dis 1 1 0 16500000 0 0 50000 ... case #6: use cpu_div2 as parent of cpu_scale_out_sel m8b_m201_1G#mw.l 0xC110419C 0x30 1 m8b_m201_1G#mw.l 0xC110419C 0x34 1 m8b_m201_1G#mw.l 0xC110419C 0xb5 1 [ 0.000534] smp_twd: clock not found -2 [ 0.001487] Calibrating local timer... 98.91MHz. # cat /sys/kernel/debug/clk/clk_summary enable prepare protect duty clock count count count rate accuracy phase cycle --------------------------------------------------------------------------------------------- ... sys_pll_dco 1 1 0 1584000000 0 0 50000 sys_pll 1 1 0 792000000 0 0 50000 cpu_in_sel 1 1 0 792000000 0 0 50000 ... cpu_div2 1 1 0 396000000 0 0 50000 cpu_scale_out_sel 1 1 0 396000000 0 0 50000 cpu_clk 4 4 0 396000000 0 0 50000 ... cpu_clk_div4 2 2 0 99000000 0 0 50000 axi_clk_sel 1 1 0 99000000 0 0 50000 axi_clk_dis 1 1 0 99000000 0 0 50000 periph_clk_sel 1 1 0 99000000 0 0 50000 periph_clk_dis 1 1 0 99000000 0 0 50000 ... case #7: use cpu_div3 as parent of cpu_scale_out_sel m8b_m201_1G#mw.l 0xC110419C 0x30 1 m8b_m201_1G#mw.l 0xC110419C 0x38 1 m8b_m201_1G#mw.l 0xC110419C 0xb9 1 test skipped, the system is not stable with this clock as parent ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 0/3] Meson8b: add the CPU clock post-dividers 2018-11-16 20:53 [PATCH 0/3] Meson8b: add the CPU clock post-dividers Martin Blumenstingl ` (3 preceding siblings ...) 2018-11-16 20:55 ` [PATCH 0/3] Meson8b: add the CPU clock post-dividers Martin Blumenstingl @ 2018-11-22 9:05 ` Jerome Brunet 2018-11-22 21:29 ` Martin Blumenstingl 4 siblings, 1 reply; 7+ messages in thread From: Jerome Brunet @ 2018-11-22 9:05 UTC (permalink / raw) To: Martin Blumenstingl, linux-amlogic, narmstrong Cc: mturquette, sboyd, linux-clk, linux-arm-kernel, linux-kernel On Fri, 2018-11-16 at 21:53 +0100, Martin Blumenstingl wrote: > This is the successor to my previous series "meson8b: add the CPU_DIV16 > clock for the ARM TWD" from [0]. I decided to not send this as v2 of > the original series because the PERIPH clock is not the CPU_DIV16 clock. > It's not clear whether a CPU_DIV16 clock exists. > > With this series we get all the CPU_CLK post-dividers as listed in the > public S805 datasheet [1] on pages 31 and 32: > - ABP > - PERIPH (used as input for the ARM global timer and ARM TWD timer) > - AXI > - L2 DRAM > > Each of these clocks has a register called "..._CLK_DIS" which is > documented as a "just in case" bit: > "Set to 1 to manually disable the [...] clock when changing the mux > selection. Typically this bit is set to 0 since the clock muxes can > switch without glitches." > Since we're not supposed to touch that register we're setting > CLK_IS_CRITICAL for these clocks in the driver. If we are not supposed to touch the register, I'd prefer if you used RO ops instead of using CLK_IS_CRITICAL. > > The result of this is that we can use the PERIPH clock which clocks > the ARM TWD timer. I will send a separate series to add the TWD timer. > > > [0] http://lists.infradead.org/pipermail/linux-amlogic/2018-July/007890.html > [1] > https://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf > > Martin Blumenstingl (3): > dt-bindings: clock: meson8b: export the CPU post dividers > clk: meson: meson8b: rename cpu_div2/cpu_div3 to > cpu_in_div2/cpu_in_div3 > clk: meson: meson8b: add the CPU clock post divider clocks > > drivers/clk/meson/meson8b.c | 268 ++++++++++++++++++++++- > drivers/clk/meson/meson8b.h | 17 +- > include/dt-bindings/clock/meson8b-clkc.h | 4 + > 3 files changed, 276 insertions(+), 13 deletions(-) > With CLK_IS_CRITICAL removed, looks good to me: Acked-by: Jerome Brunet <jbrunet@baylibre.com> ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 0/3] Meson8b: add the CPU clock post-dividers 2018-11-22 9:05 ` Jerome Brunet @ 2018-11-22 21:29 ` Martin Blumenstingl 0 siblings, 0 replies; 7+ messages in thread From: Martin Blumenstingl @ 2018-11-22 21:29 UTC (permalink / raw) To: jbrunet Cc: linux-amlogic, Neil Armstrong, mturquette, sboyd, linux-clk, linux-arm-kernel, linux-kernel Hi Jerome, On Thu, Nov 22, 2018 at 10:05 AM Jerome Brunet <jbrunet@baylibre.com> wrote: > > On Fri, 2018-11-16 at 21:53 +0100, Martin Blumenstingl wrote: > > This is the successor to my previous series "meson8b: add the CPU_DIV16 > > clock for the ARM TWD" from [0]. I decided to not send this as v2 of > > the original series because the PERIPH clock is not the CPU_DIV16 clock. > > It's not clear whether a CPU_DIV16 clock exists. > > > > With this series we get all the CPU_CLK post-dividers as listed in the > > public S805 datasheet [1] on pages 31 and 32: > > - ABP > > - PERIPH (used as input for the ARM global timer and ARM TWD timer) > > - AXI > > - L2 DRAM > > > > Each of these clocks has a register called "..._CLK_DIS" which is > > documented as a "just in case" bit: > > "Set to 1 to manually disable the [...] clock when changing the mux > > selection. Typically this bit is set to 0 since the clock muxes can > > switch without glitches." > > Since we're not supposed to touch that register we're setting > > CLK_IS_CRITICAL for these clocks in the driver. > > If we are not supposed to touch the register, I'd prefer if you used RO ops > instead of using CLK_IS_CRITICAL. that makes sense as other "read-only" clocks are using RO ops as well. I'll add a new patch which introduces clk_regmap_gate_ro_ops as we don't have that yet > > > > The result of this is that we can use the PERIPH clock which clocks > > the ARM TWD timer. I will send a separate series to add the TWD timer. > > > > > > [0] http://lists.infradead.org/pipermail/linux-amlogic/2018-July/007890.html > > [1] > > https://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf > > > > Martin Blumenstingl (3): > > dt-bindings: clock: meson8b: export the CPU post dividers > > clk: meson: meson8b: rename cpu_div2/cpu_div3 to > > cpu_in_div2/cpu_in_div3 > > clk: meson: meson8b: add the CPU clock post divider clocks > > > > drivers/clk/meson/meson8b.c | 268 ++++++++++++++++++++++- > > drivers/clk/meson/meson8b.h | 17 +- > > include/dt-bindings/clock/meson8b-clkc.h | 4 + > > 3 files changed, 276 insertions(+), 13 deletions(-) > > > > With CLK_IS_CRITICAL removed, looks good to me: > > Acked-by: Jerome Brunet <jbrunet@baylibre.com> thanks for reviewing this! Regards Martin ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2018-11-22 21:29 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-11-16 20:53 [PATCH 0/3] Meson8b: add the CPU clock post-dividers Martin Blumenstingl 2018-11-16 20:53 ` [PATCH 1/3] dt-bindings: clock: meson8b: export the CPU post dividers Martin Blumenstingl 2018-11-16 20:53 ` [PATCH 2/3] clk: meson: meson8b: rename cpu_div2/cpu_div3 to cpu_in_div2/cpu_in_div3 Martin Blumenstingl 2018-11-16 20:53 ` [PATCH 3/3] clk: meson: meson8b: add the CPU clock post divider clocks Martin Blumenstingl 2018-11-16 20:55 ` [PATCH 0/3] Meson8b: add the CPU clock post-dividers Martin Blumenstingl 2018-11-22 9:05 ` Jerome Brunet 2018-11-22 21:29 ` Martin Blumenstingl
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).