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* [PATCH] arm64: dts: hisi: add hns-dsaf cpld control for the hip07 SoC
@ 2018-01-18 12:31 Huazhong Tan
  2018-03-02 16:01 ` Wei Xu
  0 siblings, 1 reply; 2+ messages in thread
From: Huazhong Tan @ 2018-01-18 12:31 UTC (permalink / raw)
  To: xuwei5; +Cc: linuxarm, linux-arm-kernel, devicetree, linux-kernel

Add cpld-syscon node to support the cpld control for hns-dsaf
on the hip07 SoC.

Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
---
 arch/arm64/boot/dts/hisilicon/hip07.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
index 2c01a21..4bd6416 100644
--- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
@@ -1127,6 +1127,12 @@
 			reg = <0x0 0xc0000000 0x0 0x10000>;
 		};
 
+		dsa_cpld: dsa_cpld@78000010 {
+			compatible = "syscon";
+			reg = <0x0 0x78000010 0x0 0x100>;
+			reg-io-width = <2>;
+		};
+
 		pcie_subctl: pcie_subctl@a0000000 {
 			compatible = "hisilicon,pcie-sas-subctrl", "syscon";
 			reg = <0x0 0xa0000000 0x0 0x10000>;
@@ -1258,6 +1264,7 @@
 			port@0 {
 				reg = <0>;
 				serdes-syscon = <&serdes_ctrl>;
+				cpld-syscon = <&dsa_cpld 0x0>;
 				port-rst-offset = <0>;
 				port-mode-offset = <0>;
 				mc-mac-mask = [ff f0 00 00 00 00];
@@ -1267,6 +1274,7 @@
 			port@1 {
 				reg = <1>;
 				serdes-syscon= <&serdes_ctrl>;
+				cpld-syscon = <&dsa_cpld 0x4>;
 				port-rst-offset = <1>;
 				port-mode-offset = <1>;
 				mc-mac-mask = [ff f0 00 00 00 00];
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 2+ messages in thread

* Re: [PATCH] arm64: dts: hisi: add hns-dsaf cpld control for the hip07 SoC
  2018-01-18 12:31 [PATCH] arm64: dts: hisi: add hns-dsaf cpld control for the hip07 SoC Huazhong Tan
@ 2018-03-02 16:01 ` Wei Xu
  0 siblings, 0 replies; 2+ messages in thread
From: Wei Xu @ 2018-03-02 16:01 UTC (permalink / raw)
  To: Huazhong Tan; +Cc: linuxarm, linux-arm-kernel, devicetree, linux-kernel

Hi Huazhong,

On 2018/1/18 12:31, Huazhong Tan wrote:
> Add cpld-syscon node to support the cpld control for hns-dsaf
> on the hip07 SoC.
> 
> Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
> ---

Applied into hisilicon dt tree.
Thanks!

BR,
Wei

>  arch/arm64/boot/dts/hisilicon/hip07.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
> index 2c01a21..4bd6416 100644
> --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
> @@ -1127,6 +1127,12 @@
>  			reg = <0x0 0xc0000000 0x0 0x10000>;
>  		};
>  
> +		dsa_cpld: dsa_cpld@78000010 {
> +			compatible = "syscon";
> +			reg = <0x0 0x78000010 0x0 0x100>;
> +			reg-io-width = <2>;
> +		};
> +
>  		pcie_subctl: pcie_subctl@a0000000 {
>  			compatible = "hisilicon,pcie-sas-subctrl", "syscon";
>  			reg = <0x0 0xa0000000 0x0 0x10000>;
> @@ -1258,6 +1264,7 @@
>  			port@0 {
>  				reg = <0>;
>  				serdes-syscon = <&serdes_ctrl>;
> +				cpld-syscon = <&dsa_cpld 0x0>;
>  				port-rst-offset = <0>;
>  				port-mode-offset = <0>;
>  				mc-mac-mask = [ff f0 00 00 00 00];
> @@ -1267,6 +1274,7 @@
>  			port@1 {
>  				reg = <1>;
>  				serdes-syscon= <&serdes_ctrl>;
> +				cpld-syscon = <&dsa_cpld 0x4>;
>  				port-rst-offset = <1>;
>  				port-mode-offset = <1>;
>  				mc-mac-mask = [ff f0 00 00 00 00];
> 

^ permalink raw reply	[flat|nested] 2+ messages in thread

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