* Add support for the X1830 and fix bugs for X1000 v6.
@ 2020-03-22 8:20 周琰杰 (Zhou Yanjie)
2020-03-22 8:20 ` [PATCH v6 0/6] Add support for the X1830 and fix bugs for X1000 周琰杰 (Zhou Yanjie)
` (6 more replies)
0 siblings, 7 replies; 12+ messages in thread
From: 周琰杰 (Zhou Yanjie) @ 2020-03-22 8:20 UTC (permalink / raw)
To: linux-clk
Cc: linux-kernel, devicetree, sboyd, mturquette, robh+dt,
mark.rutland, paul, dongsheng.qiu, yanfei.li, sernia.zhou,
zhenwenjin
v5->v6:
1.Revert "pll_reg" to "reg" to minimize patch as Paul Cercueil's suggest.
2.Add missing part of X1830's CGU.
3.Add missing part of X1000's CGU.
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v6 0/6] Add support for the X1830 and fix bugs for X1000 2020-03-22 8:20 Add support for the X1830 and fix bugs for X1000 v6 周琰杰 (Zhou Yanjie) @ 2020-03-22 8:20 ` 周琰杰 (Zhou Yanjie) 2020-03-22 8:20 ` [PATCH v6 1/6] clk: Ingenic: Remove unnecessary spinlock when reading registers 周琰杰 (Zhou Yanjie) ` (5 subsequent siblings) 6 siblings, 0 replies; 12+ messages in thread From: 周琰杰 (Zhou Yanjie) @ 2020-03-22 8:20 UTC (permalink / raw) To: linux-clk Cc: linux-kernel, devicetree, sboyd, mturquette, robh+dt, mark.rutland, paul, dongsheng.qiu, yanfei.li, sernia.zhou, zhenwenjin v5->v6: 1.Revert "pll_reg" to "reg" to minimize patch as Paul Cercueil's suggest. 2.Add missing part of X1830's CGU. 3.Add missing part of X1000's CGU. 周琰杰 (Zhou Yanjie) (6): clk: Ingenic: Remove unnecessary spinlock when reading registers. clk: Ingenic: Adjust cgu code to make it compatible with X1830. dt-bindings: clock: Add X1830 bindings. clk: Ingenic: Add CGU driver for X1830. dt-bindings: clock: Add and reorder ABI for X1000. clk: X1000: Add FIXDIV for SSI clock of X1000. .../devicetree/bindings/clock/ingenic,cgu.txt | 1 + drivers/clk/ingenic/Kconfig | 10 + drivers/clk/ingenic/Makefile | 1 + drivers/clk/ingenic/cgu.c | 28 +- drivers/clk/ingenic/cgu.h | 4 + drivers/clk/ingenic/jz4725b-cgu.c | 2 + drivers/clk/ingenic/jz4740-cgu.c | 2 + drivers/clk/ingenic/jz4770-cgu.c | 6 +- drivers/clk/ingenic/jz4780-cgu.c | 2 + drivers/clk/ingenic/x1000-cgu.c | 60 +++- drivers/clk/ingenic/x1830-cgu.c | 387 +++++++++++++++++++++ include/dt-bindings/clock/x1000-cgu.h | 62 ++-- include/dt-bindings/clock/x1830-cgu.h | 53 +++ 13 files changed, 569 insertions(+), 49 deletions(-) create mode 100644 drivers/clk/ingenic/x1830-cgu.c create mode 100644 include/dt-bindings/clock/x1830-cgu.h -- 2.7.4 ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v6 1/6] clk: Ingenic: Remove unnecessary spinlock when reading registers. 2020-03-22 8:20 Add support for the X1830 and fix bugs for X1000 v6 周琰杰 (Zhou Yanjie) 2020-03-22 8:20 ` [PATCH v6 0/6] Add support for the X1830 and fix bugs for X1000 周琰杰 (Zhou Yanjie) @ 2020-03-22 8:20 ` 周琰杰 (Zhou Yanjie) 2020-03-22 8:20 ` [PATCH v6 2/6] clk: Ingenic: Adjust cgu code to make it compatible with X1830 周琰杰 (Zhou Yanjie) ` (4 subsequent siblings) 6 siblings, 0 replies; 12+ messages in thread From: 周琰杰 (Zhou Yanjie) @ 2020-03-22 8:20 UTC (permalink / raw) To: linux-clk Cc: linux-kernel, devicetree, sboyd, mturquette, robh+dt, mark.rutland, paul, dongsheng.qiu, yanfei.li, sernia.zhou, zhenwenjin It is not necessary to use spinlock when reading registers, so remove it from cgu.c. Suggested-by: Paul Cercueil <paul@crapouillou.net> Suggested-by: Paul Burton <paulburton@kernel.org> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> --- Notes: v2: New patch. v2->v3: Adjust order from [5/5] in v2 to [1/5] in v3. v3->v4: Remove the spinlock around ingenic_cgu_gate_get(). v4->v5: Rebase on top of kernel 5.6-rc1. v5->v6: No change. drivers/clk/ingenic/cgu.c | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c index 6e96303..ab1302a 100644 --- a/drivers/clk/ingenic/cgu.c +++ b/drivers/clk/ingenic/cgu.c @@ -76,16 +76,13 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) const struct ingenic_cgu_pll_info *pll_info; unsigned m, n, od_enc, od; bool bypass; - unsigned long flags; u32 ctl; clk_info = &cgu->clock_info[ingenic_clk->idx]; BUG_ON(clk_info->type != CGU_CLK_PLL); pll_info = &clk_info->pll; - spin_lock_irqsave(&cgu->lock, flags); ctl = readl(cgu->base + pll_info->reg); - spin_unlock_irqrestore(&cgu->lock, flags); m = (ctl >> pll_info->m_shift) & GENMASK(pll_info->m_bits - 1, 0); m += pll_info->m_offset; @@ -259,12 +256,9 @@ static int ingenic_pll_is_enabled(struct clk_hw *hw) struct ingenic_cgu *cgu = ingenic_clk->cgu; const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; - unsigned long flags; u32 ctl; - spin_lock_irqsave(&cgu->lock, flags); ctl = readl(cgu->base + pll_info->reg); - spin_unlock_irqrestore(&cgu->lock, flags); return !!(ctl & BIT(pll_info->enable_bit)); } @@ -562,16 +556,12 @@ static int ingenic_clk_is_enabled(struct clk_hw *hw) struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); struct ingenic_cgu *cgu = ingenic_clk->cgu; const struct ingenic_cgu_clk_info *clk_info; - unsigned long flags; int enabled = 1; clk_info = &cgu->clock_info[ingenic_clk->idx]; - if (clk_info->type & CGU_CLK_GATE) { - spin_lock_irqsave(&cgu->lock, flags); + if (clk_info->type & CGU_CLK_GATE) enabled = !ingenic_cgu_gate_get(cgu, &clk_info->gate); - spin_unlock_irqrestore(&cgu->lock, flags); - } return enabled; } -- 2.7.4 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v6 2/6] clk: Ingenic: Adjust cgu code to make it compatible with X1830. 2020-03-22 8:20 Add support for the X1830 and fix bugs for X1000 v6 周琰杰 (Zhou Yanjie) 2020-03-22 8:20 ` [PATCH v6 0/6] Add support for the X1830 and fix bugs for X1000 周琰杰 (Zhou Yanjie) 2020-03-22 8:20 ` [PATCH v6 1/6] clk: Ingenic: Remove unnecessary spinlock when reading registers 周琰杰 (Zhou Yanjie) @ 2020-03-22 8:20 ` 周琰杰 (Zhou Yanjie) 2020-03-22 12:25 ` Zhou Yanjie 2020-03-22 8:20 ` [PATCH v6 3/6] dt-bindings: clock: Add X1830 bindings 周琰杰 (Zhou Yanjie) ` (3 subsequent siblings) 6 siblings, 1 reply; 12+ messages in thread From: 周琰杰 (Zhou Yanjie) @ 2020-03-22 8:20 UTC (permalink / raw) To: linux-clk Cc: linux-kernel, devicetree, sboyd, mturquette, robh+dt, mark.rutland, paul, dongsheng.qiu, yanfei.li, sernia.zhou, zhenwenjin The PLL of X1830 Soc from Ingenic has been greatly changed, the bypass control is placed in another register, so now two registers may needed to control the PLL. To this end, the original "reg" was changed to "pll_reg", and a new "bypass_reg" was introduced. In addition, when calculating rate, the PLL of X1830 introduced an extra 2x multiplier, so a new "rate_multiplier" was introduced. And adjust the code in jz47xx-cgu.c and x1000-cgu.c, make it to be compatible with the new cgu code. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> --- Notes: v1->v2: 1.Use two fields (pll_reg & bypass_reg) instead of the 2-values array (reg[2]). 2.Remove the "pll_info->version" and add a "pll_info->rate_multiplier". 3.Fix the coding style and add more detailed commit message. 4.Change my Signed-off-by from "Zhou Yanjie <zhouyanjie@zoho.com>" to "周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>" because the old mailbox is in an unstable state. v2->v3: Adjust order from [1/5] in v2 to [2/5] in v3. v3->v4: Merge [3/5] in v3 into this patch. v4->v5: Rebase on top of kernel 5.6-rc1. v5->v6: Revert "pll_reg" to "reg" to minimize patch as Paul Cercueil's suggest. drivers/clk/ingenic/cgu.c | 16 +++++++++++++--- drivers/clk/ingenic/cgu.h | 4 ++++ drivers/clk/ingenic/jz4725b-cgu.c | 2 ++ drivers/clk/ingenic/jz4740-cgu.c | 2 ++ drivers/clk/ingenic/jz4770-cgu.c | 6 +++++- drivers/clk/ingenic/jz4780-cgu.c | 2 ++ drivers/clk/ingenic/x1000-cgu.c | 4 ++++ 7 files changed, 32 insertions(+), 4 deletions(-) diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c index ab1302a..d7981b6 100644 --- a/drivers/clk/ingenic/cgu.c +++ b/drivers/clk/ingenic/cgu.c @@ -90,6 +90,9 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) n += pll_info->n_offset; od_enc = ctl >> pll_info->od_shift; od_enc &= GENMASK(pll_info->od_bits - 1, 0); + + ctl = readl(cgu->base + pll_info->bypass_reg); + bypass = !pll_info->no_bypass_bit && !!(ctl & BIT(pll_info->bypass_bit)); @@ -103,7 +106,8 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) BUG_ON(od == pll_info->od_max); od++; - return div_u64((u64)parent_rate * m, n * od); + return div_u64((u64)parent_rate * m * pll_info->rate_multiplier, + n * od); } static unsigned long @@ -136,7 +140,8 @@ ingenic_pll_calc(const struct ingenic_cgu_clk_info *clk_info, if (pod) *pod = od; - return div_u64((u64)parent_rate * m, n * od); + return div_u64((u64)parent_rate * m * pll_info->rate_multiplier, + n * od); } static inline const struct ingenic_cgu_clk_info *to_clk_info( @@ -209,9 +214,14 @@ static int ingenic_pll_enable(struct clk_hw *hw) u32 ctl; spin_lock_irqsave(&cgu->lock, flags); - ctl = readl(cgu->base + pll_info->reg); + ctl = readl(cgu->base + pll_info->bypass_reg); ctl &= ~BIT(pll_info->bypass_bit); + + writel(ctl, cgu->base + pll_info->bypass_reg); + + ctl = readl(cgu->base + pll_info->reg); + ctl |= BIT(pll_info->enable_bit); writel(ctl, cgu->base + pll_info->reg); diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h index 0dc8004..2c75ef4 100644 --- a/drivers/clk/ingenic/cgu.h +++ b/drivers/clk/ingenic/cgu.h @@ -17,6 +17,7 @@ /** * struct ingenic_cgu_pll_info - information about a PLL * @reg: the offset of the PLL's control register within the CGU + * @rate_multiplier: the multiplier needed by pll rate calculation * @m_shift: the number of bits to shift the multiplier value by (ie. the * index of the lowest bit of the multiplier value in the PLL's * control register) @@ -37,6 +38,7 @@ * @od_encoding: a pointer to an array mapping post-VCO divider values to * their encoded values in the PLL control register, or -1 for * unsupported values + * @bypass_reg: the offset of the bypass control register within the CGU * @bypass_bit: the index of the bypass bit in the PLL control register * @enable_bit: the index of the enable bit in the PLL control register * @stable_bit: the index of the stable bit in the PLL control register @@ -44,10 +46,12 @@ */ struct ingenic_cgu_pll_info { unsigned reg; + unsigned rate_multiplier; const s8 *od_encoding; u8 m_shift, m_bits, m_offset; u8 n_shift, n_bits, n_offset; u8 od_shift, od_bits, od_max; + unsigned bypass_reg; u8 bypass_bit; u8 enable_bit; u8 stable_bit; diff --git a/drivers/clk/ingenic/jz4725b-cgu.c b/drivers/clk/ingenic/jz4725b-cgu.c index a3b4635..4799627 100644 --- a/drivers/clk/ingenic/jz4725b-cgu.c +++ b/drivers/clk/ingenic/jz4725b-cgu.c @@ -54,6 +54,7 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = { .parents = { JZ4725B_CLK_EXT, -1, -1, -1 }, .pll = { .reg = CGU_REG_CPPCR, + .rate_multiplier = 1, .m_shift = 23, .m_bits = 9, .m_offset = 2, @@ -65,6 +66,7 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = { .od_max = 4, .od_encoding = pll_od_encoding, .stable_bit = 10, + .bypass_reg = CGU_REG_CPPCR, .bypass_bit = 9, .enable_bit = 8, }, diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c index 4f0e92c..16f7e1e 100644 --- a/drivers/clk/ingenic/jz4740-cgu.c +++ b/drivers/clk/ingenic/jz4740-cgu.c @@ -69,6 +69,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { .parents = { JZ4740_CLK_EXT, -1, -1, -1 }, .pll = { .reg = CGU_REG_CPPCR, + .rate_multiplier = 1, .m_shift = 23, .m_bits = 9, .m_offset = 2, @@ -80,6 +81,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { .od_max = 4, .od_encoding = pll_od_encoding, .stable_bit = 10, + .bypass_reg = CGU_REG_CPPCR, .bypass_bit = 9, .enable_bit = 8, }, diff --git a/drivers/clk/ingenic/jz4770-cgu.c b/drivers/clk/ingenic/jz4770-cgu.c index 956dd65..1976008 100644 --- a/drivers/clk/ingenic/jz4770-cgu.c +++ b/drivers/clk/ingenic/jz4770-cgu.c @@ -102,6 +102,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { .parents = { JZ4770_CLK_EXT }, .pll = { .reg = CGU_REG_CPPCR0, + .rate_multiplier = 1, .m_shift = 24, .m_bits = 7, .m_offset = 1, @@ -112,6 +113,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { .od_bits = 2, .od_max = 8, .od_encoding = pll_od_encoding, + .bypass_reg = CGU_REG_CPPCR0, .bypass_bit = 9, .enable_bit = 8, .stable_bit = 10, @@ -124,6 +126,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { .parents = { JZ4770_CLK_EXT }, .pll = { .reg = CGU_REG_CPPCR1, + .rate_multiplier = 1, .m_shift = 24, .m_bits = 7, .m_offset = 1, @@ -134,9 +137,10 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { .od_bits = 2, .od_max = 8, .od_encoding = pll_od_encoding, + .bypass_reg = CGU_REG_CPPCR1, + .no_bypass_bit = true, .enable_bit = 7, .stable_bit = 6, - .no_bypass_bit = true, }, }, diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c index ea905ff..5102432 100644 --- a/drivers/clk/ingenic/jz4780-cgu.c +++ b/drivers/clk/ingenic/jz4780-cgu.c @@ -221,6 +221,7 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = { #define DEF_PLL(name) { \ .reg = CGU_REG_ ## name, \ + .rate_multiplier = 1, \ .m_shift = 19, \ .m_bits = 13, \ .m_offset = 1, \ @@ -232,6 +233,7 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = { .od_max = 16, \ .od_encoding = pll_od_encoding, \ .stable_bit = 6, \ + .bypass_reg = CGU_REG_ ## name, \ .bypass_bit = 1, \ .enable_bit = 0, \ } diff --git a/drivers/clk/ingenic/x1000-cgu.c b/drivers/clk/ingenic/x1000-cgu.c index b22d87b..6f0ec9d 100644 --- a/drivers/clk/ingenic/x1000-cgu.c +++ b/drivers/clk/ingenic/x1000-cgu.c @@ -58,6 +58,7 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { .parents = { X1000_CLK_EXCLK, -1, -1, -1 }, .pll = { .reg = CGU_REG_APLL, + .rate_multiplier = 1, .m_shift = 24, .m_bits = 7, .m_offset = 1, @@ -68,6 +69,7 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { .od_bits = 2, .od_max = 8, .od_encoding = pll_od_encoding, + .bypass_reg = CGU_REG_APLL, .bypass_bit = 9, .enable_bit = 8, .stable_bit = 10, @@ -79,6 +81,7 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { .parents = { X1000_CLK_EXCLK, -1, -1, -1 }, .pll = { .reg = CGU_REG_MPLL, + .rate_multiplier = 1, .m_shift = 24, .m_bits = 7, .m_offset = 1, @@ -89,6 +92,7 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { .od_bits = 2, .od_max = 8, .od_encoding = pll_od_encoding, + .bypass_reg = CGU_REG_MPLL, .bypass_bit = 6, .enable_bit = 7, .stable_bit = 0, -- 2.7.4 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v6 2/6] clk: Ingenic: Adjust cgu code to make it compatible with X1830. 2020-03-22 8:20 ` [PATCH v6 2/6] clk: Ingenic: Adjust cgu code to make it compatible with X1830 周琰杰 (Zhou Yanjie) @ 2020-03-22 12:25 ` Zhou Yanjie 0 siblings, 0 replies; 12+ messages in thread From: Zhou Yanjie @ 2020-03-22 12:25 UTC (permalink / raw) To: Paul Cercueil Cc: linux-clk, linux-kernel, devicetree, sboyd, mturquette, robh+dt, mark.rutland, dongsheng.qiu, yanfei.li, sernia.zhou, zhenwenjin Hi Paul, On 2020年03月22日 20:04, Paul Cercueil wrote: > Hi Zhou, > > Le dim. 22 mars 2020 à 16:20, 周琰杰 (Zhou Yanjie) > <zhouyanjie@wanyeetech.com> a écrit : >> The PLL of X1830 Soc from Ingenic has been greatly changed, >> the bypass control is placed in another register, so now two >> registers may needed to control the PLL. To this end, the >> original "reg" was changed to "pll_reg", and a new "bypass_reg" >> was introduced. In addition, when calculating rate, the PLL of >> X1830 introduced an extra 2x multiplier, so a new "rate_multiplier" >> was introduced. And adjust the code in jz47xx-cgu.c and x1000-cgu.c, >> make it to be compatible with the new cgu code. >> >> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> > > I think you need to update the commit message... > Oops, forgot to update it, I'll update it in next version. Thanks and best regards! > With that fixed, > Reviewed-by: Paul Cercueil <paul@crapouillou.net> > > -Paul > >> --- >> >> Notes: >> v1->v2: >> 1.Use two fields (pll_reg & bypass_reg) instead of the 2-values >> array (reg[2]). >> 2.Remove the "pll_info->version" and add a >> "pll_info->rate_multiplier". >> 3.Fix the coding style and add more detailed commit message. >> 4.Change my Signed-off-by from "Zhou Yanjie <zhouyanjie@zoho.com>" >> to "周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>" because >> the old mailbox is in an unstable state. >> >> v2->v3: >> Adjust order from [1/5] in v2 to [2/5] in v3. >> >> v3->v4: >> Merge [3/5] in v3 into this patch. >> >> v4->v5: >> Rebase on top of kernel 5.6-rc1. >> >> v5->v6: >> Revert "pll_reg" to "reg" to minimize patch as Paul Cercueil's >> suggest. >> >> drivers/clk/ingenic/cgu.c | 16 +++++++++++++--- >> drivers/clk/ingenic/cgu.h | 4 ++++ >> drivers/clk/ingenic/jz4725b-cgu.c | 2 ++ >> drivers/clk/ingenic/jz4740-cgu.c | 2 ++ >> drivers/clk/ingenic/jz4770-cgu.c | 6 +++++- >> drivers/clk/ingenic/jz4780-cgu.c | 2 ++ >> drivers/clk/ingenic/x1000-cgu.c | 4 ++++ >> 7 files changed, 32 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c >> index ab1302a..d7981b6 100644 >> --- a/drivers/clk/ingenic/cgu.c >> +++ b/drivers/clk/ingenic/cgu.c >> @@ -90,6 +90,9 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned >> long parent_rate) >> n += pll_info->n_offset; >> od_enc = ctl >> pll_info->od_shift; >> od_enc &= GENMASK(pll_info->od_bits - 1, 0); >> + >> + ctl = readl(cgu->base + pll_info->bypass_reg); >> + >> bypass = !pll_info->no_bypass_bit && >> !!(ctl & BIT(pll_info->bypass_bit)); >> >> @@ -103,7 +106,8 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, >> unsigned long parent_rate) >> BUG_ON(od == pll_info->od_max); >> od++; >> >> - return div_u64((u64)parent_rate * m, n * od); >> + return div_u64((u64)parent_rate * m * pll_info->rate_multiplier, >> + n * od); >> } >> >> static unsigned long >> @@ -136,7 +140,8 @@ ingenic_pll_calc(const struct >> ingenic_cgu_clk_info *clk_info, >> if (pod) >> *pod = od; >> >> - return div_u64((u64)parent_rate * m, n * od); >> + return div_u64((u64)parent_rate * m * pll_info->rate_multiplier, >> + n * od); >> } >> >> static inline const struct ingenic_cgu_clk_info *to_clk_info( >> @@ -209,9 +214,14 @@ static int ingenic_pll_enable(struct clk_hw *hw) >> u32 ctl; >> >> spin_lock_irqsave(&cgu->lock, flags); >> - ctl = readl(cgu->base + pll_info->reg); >> + ctl = readl(cgu->base + pll_info->bypass_reg); >> >> ctl &= ~BIT(pll_info->bypass_bit); >> + >> + writel(ctl, cgu->base + pll_info->bypass_reg); >> + >> + ctl = readl(cgu->base + pll_info->reg); >> + >> ctl |= BIT(pll_info->enable_bit); >> >> writel(ctl, cgu->base + pll_info->reg); >> diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h >> index 0dc8004..2c75ef4 100644 >> --- a/drivers/clk/ingenic/cgu.h >> +++ b/drivers/clk/ingenic/cgu.h >> @@ -17,6 +17,7 @@ >> /** >> * struct ingenic_cgu_pll_info - information about a PLL >> * @reg: the offset of the PLL's control register within the CGU >> + * @rate_multiplier: the multiplier needed by pll rate calculation >> * @m_shift: the number of bits to shift the multiplier value by >> (ie. the >> * index of the lowest bit of the multiplier value in the >> PLL's >> * control register) >> @@ -37,6 +38,7 @@ >> * @od_encoding: a pointer to an array mapping post-VCO divider >> values to >> * their encoded values in the PLL control register, >> or -1 for >> * unsupported values >> + * @bypass_reg: the offset of the bypass control register within the >> CGU >> * @bypass_bit: the index of the bypass bit in the PLL control register >> * @enable_bit: the index of the enable bit in the PLL control register >> * @stable_bit: the index of the stable bit in the PLL control register >> @@ -44,10 +46,12 @@ >> */ >> struct ingenic_cgu_pll_info { >> unsigned reg; >> + unsigned rate_multiplier; >> const s8 *od_encoding; >> u8 m_shift, m_bits, m_offset; >> u8 n_shift, n_bits, n_offset; >> u8 od_shift, od_bits, od_max; >> + unsigned bypass_reg; >> u8 bypass_bit; >> u8 enable_bit; >> u8 stable_bit; >> diff --git a/drivers/clk/ingenic/jz4725b-cgu.c >> b/drivers/clk/ingenic/jz4725b-cgu.c >> index a3b4635..4799627 100644 >> --- a/drivers/clk/ingenic/jz4725b-cgu.c >> +++ b/drivers/clk/ingenic/jz4725b-cgu.c >> @@ -54,6 +54,7 @@ static const struct ingenic_cgu_clk_info >> jz4725b_cgu_clocks[] = { >> .parents = { JZ4725B_CLK_EXT, -1, -1, -1 }, >> .pll = { >> .reg = CGU_REG_CPPCR, >> + .rate_multiplier = 1, >> .m_shift = 23, >> .m_bits = 9, >> .m_offset = 2, >> @@ -65,6 +66,7 @@ static const struct ingenic_cgu_clk_info >> jz4725b_cgu_clocks[] = { >> .od_max = 4, >> .od_encoding = pll_od_encoding, >> .stable_bit = 10, >> + .bypass_reg = CGU_REG_CPPCR, >> .bypass_bit = 9, >> .enable_bit = 8, >> }, >> diff --git a/drivers/clk/ingenic/jz4740-cgu.c >> b/drivers/clk/ingenic/jz4740-cgu.c >> index 4f0e92c..16f7e1e 100644 >> --- a/drivers/clk/ingenic/jz4740-cgu.c >> +++ b/drivers/clk/ingenic/jz4740-cgu.c >> @@ -69,6 +69,7 @@ static const struct ingenic_cgu_clk_info >> jz4740_cgu_clocks[] = { >> .parents = { JZ4740_CLK_EXT, -1, -1, -1 }, >> .pll = { >> .reg = CGU_REG_CPPCR, >> + .rate_multiplier = 1, >> .m_shift = 23, >> .m_bits = 9, >> .m_offset = 2, >> @@ -80,6 +81,7 @@ static const struct ingenic_cgu_clk_info >> jz4740_cgu_clocks[] = { >> .od_max = 4, >> .od_encoding = pll_od_encoding, >> .stable_bit = 10, >> + .bypass_reg = CGU_REG_CPPCR, >> .bypass_bit = 9, >> .enable_bit = 8, >> }, >> diff --git a/drivers/clk/ingenic/jz4770-cgu.c >> b/drivers/clk/ingenic/jz4770-cgu.c >> index 956dd65..1976008 100644 >> --- a/drivers/clk/ingenic/jz4770-cgu.c >> +++ b/drivers/clk/ingenic/jz4770-cgu.c >> @@ -102,6 +102,7 @@ static const struct ingenic_cgu_clk_info >> jz4770_cgu_clocks[] = { >> .parents = { JZ4770_CLK_EXT }, >> .pll = { >> .reg = CGU_REG_CPPCR0, >> + .rate_multiplier = 1, >> .m_shift = 24, >> .m_bits = 7, >> .m_offset = 1, >> @@ -112,6 +113,7 @@ static const struct ingenic_cgu_clk_info >> jz4770_cgu_clocks[] = { >> .od_bits = 2, >> .od_max = 8, >> .od_encoding = pll_od_encoding, >> + .bypass_reg = CGU_REG_CPPCR0, >> .bypass_bit = 9, >> .enable_bit = 8, >> .stable_bit = 10, >> @@ -124,6 +126,7 @@ static const struct ingenic_cgu_clk_info >> jz4770_cgu_clocks[] = { >> .parents = { JZ4770_CLK_EXT }, >> .pll = { >> .reg = CGU_REG_CPPCR1, >> + .rate_multiplier = 1, >> .m_shift = 24, >> .m_bits = 7, >> .m_offset = 1, >> @@ -134,9 +137,10 @@ static const struct ingenic_cgu_clk_info >> jz4770_cgu_clocks[] = { >> .od_bits = 2, >> .od_max = 8, >> .od_encoding = pll_od_encoding, >> + .bypass_reg = CGU_REG_CPPCR1, >> + .no_bypass_bit = true, >> .enable_bit = 7, >> .stable_bit = 6, >> - .no_bypass_bit = true, >> }, >> }, >> >> diff --git a/drivers/clk/ingenic/jz4780-cgu.c >> b/drivers/clk/ingenic/jz4780-cgu.c >> index ea905ff..5102432 100644 >> --- a/drivers/clk/ingenic/jz4780-cgu.c >> +++ b/drivers/clk/ingenic/jz4780-cgu.c >> @@ -221,6 +221,7 @@ static const struct ingenic_cgu_clk_info >> jz4780_cgu_clocks[] = { >> >> #define DEF_PLL(name) { \ >> .reg = CGU_REG_ ## name, \ >> + .rate_multiplier = 1, \ >> .m_shift = 19, \ >> .m_bits = 13, \ >> .m_offset = 1, \ >> @@ -232,6 +233,7 @@ static const struct ingenic_cgu_clk_info >> jz4780_cgu_clocks[] = { >> .od_max = 16, \ >> .od_encoding = pll_od_encoding, \ >> .stable_bit = 6, \ >> + .bypass_reg = CGU_REG_ ## name, \ >> .bypass_bit = 1, \ >> .enable_bit = 0, \ >> } >> diff --git a/drivers/clk/ingenic/x1000-cgu.c >> b/drivers/clk/ingenic/x1000-cgu.c >> index b22d87b..6f0ec9d 100644 >> --- a/drivers/clk/ingenic/x1000-cgu.c >> +++ b/drivers/clk/ingenic/x1000-cgu.c >> @@ -58,6 +58,7 @@ static const struct ingenic_cgu_clk_info >> x1000_cgu_clocks[] = { >> .parents = { X1000_CLK_EXCLK, -1, -1, -1 }, >> .pll = { >> .reg = CGU_REG_APLL, >> + .rate_multiplier = 1, >> .m_shift = 24, >> .m_bits = 7, >> .m_offset = 1, >> @@ -68,6 +69,7 @@ static const struct ingenic_cgu_clk_info >> x1000_cgu_clocks[] = { >> .od_bits = 2, >> .od_max = 8, >> .od_encoding = pll_od_encoding, >> + .bypass_reg = CGU_REG_APLL, >> .bypass_bit = 9, >> .enable_bit = 8, >> .stable_bit = 10, >> @@ -79,6 +81,7 @@ static const struct ingenic_cgu_clk_info >> x1000_cgu_clocks[] = { >> .parents = { X1000_CLK_EXCLK, -1, -1, -1 }, >> .pll = { >> .reg = CGU_REG_MPLL, >> + .rate_multiplier = 1, >> .m_shift = 24, >> .m_bits = 7, >> .m_offset = 1, >> @@ -89,6 +92,7 @@ static const struct ingenic_cgu_clk_info >> x1000_cgu_clocks[] = { >> .od_bits = 2, >> .od_max = 8, >> .od_encoding = pll_od_encoding, >> + .bypass_reg = CGU_REG_MPLL, >> .bypass_bit = 6, >> .enable_bit = 7, >> .stable_bit = 0, >> -- >> 2.7.4 >> > ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v6 3/6] dt-bindings: clock: Add X1830 bindings. 2020-03-22 8:20 Add support for the X1830 and fix bugs for X1000 v6 周琰杰 (Zhou Yanjie) ` (2 preceding siblings ...) 2020-03-22 8:20 ` [PATCH v6 2/6] clk: Ingenic: Adjust cgu code to make it compatible with X1830 周琰杰 (Zhou Yanjie) @ 2020-03-22 8:20 ` 周琰杰 (Zhou Yanjie) 2020-03-22 8:21 ` [PATCH v6 4/6] clk: Ingenic: Add CGU driver for X1830 周琰杰 (Zhou Yanjie) ` (2 subsequent siblings) 6 siblings, 0 replies; 12+ messages in thread From: 周琰杰 (Zhou Yanjie) @ 2020-03-22 8:20 UTC (permalink / raw) To: linux-clk Cc: linux-kernel, devicetree, sboyd, mturquette, robh+dt, mark.rutland, paul, dongsheng.qiu, yanfei.li, sernia.zhou, zhenwenjin Add the clock bindings for the X1830 Soc from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Rob Herring <robh@kernel.org> --- Notes: v1->v2: Change my Signed-off-by from "Zhou Yanjie <zhouyanjie@zoho.com>" to "周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>" because the old mailbox is in an unstable state. v2->v3: Adjust order from [3/5] in v2 to [4/5] in v3. v3->v4: Adjust order from [4/5] in v3 to [3/4] in v4. v4->v5: Rebase on top of kernel 5.6-rc1. v5->v6: Add missing part of X1830's CGU. .../devicetree/bindings/clock/ingenic,cgu.txt | 1 + include/dt-bindings/clock/x1830-cgu.h | 53 ++++++++++++++++++++++ 2 files changed, 54 insertions(+) create mode 100644 include/dt-bindings/clock/x1830-cgu.h diff --git a/Documentation/devicetree/bindings/clock/ingenic,cgu.txt b/Documentation/devicetree/bindings/clock/ingenic,cgu.txt index 75598e6..74bfc57 100644 --- a/Documentation/devicetree/bindings/clock/ingenic,cgu.txt +++ b/Documentation/devicetree/bindings/clock/ingenic,cgu.txt @@ -12,6 +12,7 @@ Required properties: * ingenic,jz4770-cgu * ingenic,jz4780-cgu * ingenic,x1000-cgu + * ingenic,x1830-cgu - reg : The address & length of the CGU registers. - clocks : List of phandle & clock specifiers for clocks external to the CGU. Two such external clocks should be specified - first the external crystal diff --git a/include/dt-bindings/clock/x1830-cgu.h b/include/dt-bindings/clock/x1830-cgu.h new file mode 100644 index 00000000..f605a7b --- /dev/null +++ b/include/dt-bindings/clock/x1830-cgu.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides clock numbers for the ingenic,x1830-cgu DT binding. + * + * They are roughly ordered as: + * - external clocks + * - PLLs + * - muxes/dividers in the order they appear in the x1830 programmers manual + * - gates in order of their bit in the CLKGR* registers + */ + +#ifndef __DT_BINDINGS_CLOCK_X1830_CGU_H__ +#define __DT_BINDINGS_CLOCK_X1830_CGU_H__ + +#define X1830_CLK_EXCLK 0 +#define X1830_CLK_RTCLK 1 +#define X1830_CLK_APLL 2 +#define X1830_CLK_MPLL 3 +#define X1830_CLK_EPLL 4 +#define X1830_CLK_VPLL 5 +#define X1830_CLK_SCLKA 6 +#define X1830_CLK_CPUMUX 7 +#define X1830_CLK_CPU 8 +#define X1830_CLK_L2CACHE 9 +#define X1830_CLK_AHB0 10 +#define X1830_CLK_AHB2PMUX 11 +#define X1830_CLK_AHB2 12 +#define X1830_CLK_PCLK 13 +#define X1830_CLK_DDR 14 +#define X1830_CLK_MAC 15 +#define X1830_CLK_LCD 16 +#define X1830_CLK_MSCMUX 17 +#define X1830_CLK_MSC0 18 +#define X1830_CLK_MSC1 19 +#define X1830_CLK_SSIPLL 20 +#define X1830_CLK_SSIPLL_DIV2 21 +#define X1830_CLK_SSIMUX 22 +#define X1830_CLK_EMC 23 +#define X1830_CLK_EFUSE 24 +#define X1830_CLK_OTG 25 +#define X1830_CLK_SSI0 26 +#define X1830_CLK_SMB0 27 +#define X1830_CLK_SMB1 28 +#define X1830_CLK_SMB2 29 +#define X1830_CLK_UART0 30 +#define X1830_CLK_UART1 31 +#define X1830_CLK_SSI1 32 +#define X1830_CLK_SFC 33 +#define X1830_CLK_PDMA 34 +#define X1830_CLK_DTRNG 35 +#define X1830_CLK_OST 36 + +#endif /* __DT_BINDINGS_CLOCK_X1830_CGU_H__ */ -- 2.7.4 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v6 4/6] clk: Ingenic: Add CGU driver for X1830. 2020-03-22 8:20 Add support for the X1830 and fix bugs for X1000 v6 周琰杰 (Zhou Yanjie) ` (3 preceding siblings ...) 2020-03-22 8:20 ` [PATCH v6 3/6] dt-bindings: clock: Add X1830 bindings 周琰杰 (Zhou Yanjie) @ 2020-03-22 8:21 ` 周琰杰 (Zhou Yanjie) 2020-03-22 12:30 ` Zhou Yanjie 2020-03-22 8:21 ` [PATCH v6 5/6] dt-bindings: clock: Add and reorder ABI for X1000 周琰杰 (Zhou Yanjie) 2020-03-22 8:21 ` [PATCH v6 6/6] clk: X1000: Add FIXDIV for SSI clock of X1000 周琰杰 (Zhou Yanjie) 6 siblings, 1 reply; 12+ messages in thread From: 周琰杰 (Zhou Yanjie) @ 2020-03-22 8:21 UTC (permalink / raw) To: linux-clk Cc: linux-kernel, devicetree, sboyd, mturquette, robh+dt, mark.rutland, paul, dongsheng.qiu, yanfei.li, sernia.zhou, zhenwenjin Add support for the clocks provided by the CGU in the Ingenic X1830 SoC, making use of the cgu code to do the heavy lifting. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> --- Notes: v1->v2: 1.Use two fields (pll_reg & bypass_reg) instead of the 2-values array (reg[2]). 2.Remove the "pll_info->version" and add a "pll_info->rate_multiplier". 3.Change my Signed-off-by from "Zhou Yanjie <zhouyanjie@zoho.com>" to "周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>" because the old mailbox is in an unstable state. v2->v3: Adjust order from [4/5] in v2 to [5/5] in v3. v3->v4: Adjust order from [5/5] in v3 to [4/4] in v4. v4->v5: Rebase on top of kernel 5.6-rc1. v5->v6: Add missing part of X1830's CGU. drivers/clk/ingenic/Kconfig | 10 ++ drivers/clk/ingenic/Makefile | 1 + drivers/clk/ingenic/x1830-cgu.c | 387 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 398 insertions(+) create mode 100644 drivers/clk/ingenic/x1830-cgu.c diff --git a/drivers/clk/ingenic/Kconfig b/drivers/clk/ingenic/Kconfig index b4555b4..580b0cf 100644 --- a/drivers/clk/ingenic/Kconfig +++ b/drivers/clk/ingenic/Kconfig @@ -55,6 +55,16 @@ config INGENIC_CGU_X1000 If building for a X1000 SoC, you want to say Y here. +config INGENIC_CGU_X1830 + bool "Ingenic X1830 CGU driver" + default MACH_X1830 + select INGENIC_CGU_COMMON + help + Support the clocks provided by the CGU hardware on Ingenic X1830 + and compatible SoCs. + + If building for a X1830 SoC, you want to say Y here. + config INGENIC_TCU_CLK bool "Ingenic JZ47xx TCU clocks driver" default MACH_INGENIC diff --git a/drivers/clk/ingenic/Makefile b/drivers/clk/ingenic/Makefile index 8b1dad9..aaa4bff 100644 --- a/drivers/clk/ingenic/Makefile +++ b/drivers/clk/ingenic/Makefile @@ -5,4 +5,5 @@ obj-$(CONFIG_INGENIC_CGU_JZ4725B) += jz4725b-cgu.o obj-$(CONFIG_INGENIC_CGU_JZ4770) += jz4770-cgu.o obj-$(CONFIG_INGENIC_CGU_JZ4780) += jz4780-cgu.o obj-$(CONFIG_INGENIC_CGU_X1000) += x1000-cgu.o +obj-$(CONFIG_INGENIC_CGU_X1830) += x1830-cgu.o obj-$(CONFIG_INGENIC_TCU_CLK) += tcu.o diff --git a/drivers/clk/ingenic/x1830-cgu.c b/drivers/clk/ingenic/x1830-cgu.c new file mode 100644 index 00000000..0bc927f --- /dev/null +++ b/drivers/clk/ingenic/x1830-cgu.c @@ -0,0 +1,387 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * X1830 SoC CGU driver + * Copyright (c) 2019 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> + */ + +#include <linux/clk-provider.h> +#include <linux/delay.h> +#include <linux/of.h> +#include <dt-bindings/clock/x1830-cgu.h> +#include "cgu.h" +#include "pm.h" + +/* CGU register offsets */ +#define CGU_REG_CPCCR 0x00 +#define CGU_REG_CPPCR 0x0c +#define CGU_REG_APLL 0x10 +#define CGU_REG_MPLL 0x14 +#define CGU_REG_CLKGR0 0x20 +#define CGU_REG_OPCR 0x24 +#define CGU_REG_CLKGR1 0x28 +#define CGU_REG_DDRCDR 0x2c +#define CGU_REG_USBPCR 0x3c +#define CGU_REG_USBRDT 0x40 +#define CGU_REG_USBVBFIL 0x44 +#define CGU_REG_USBPCR1 0x48 +#define CGU_REG_MACCDR 0x54 +#define CGU_REG_EPLL 0x58 +#define CGU_REG_I2SCDR 0x60 +#define CGU_REG_LPCDR 0x64 +#define CGU_REG_MSC0CDR 0x68 +#define CGU_REG_I2SCDR1 0x70 +#define CGU_REG_SSICDR 0x74 +#define CGU_REG_CIMCDR 0x7c +#define CGU_REG_MSC1CDR 0xa4 +#define CGU_REG_CMP_INTR 0xb0 +#define CGU_REG_CMP_INTRE 0xb4 +#define CGU_REG_DRCG 0xd0 +#define CGU_REG_CPCSR 0xd4 +#define CGU_REG_VPLL 0xe0 +#define CGU_REG_MACPHYC 0xe8 + +/* bits within the OPCR register */ +#define OPCR_SPENDN0 BIT(7) +#define OPCR_SPENDN1 BIT(6) + +static struct ingenic_cgu *cgu; + +static const s8 pll_od_encoding[64] = { + 0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3, + -1, -1, -1, -1, -1, -1, -1, 0x4, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, 0x5, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, 0x6, +}; + +static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = { + + /* External clocks */ + + [X1830_CLK_EXCLK] = { "ext", CGU_CLK_EXT }, + [X1830_CLK_RTCLK] = { "rtc", CGU_CLK_EXT }, + + /* PLLs */ + + [X1830_CLK_APLL] = { + "apll", CGU_CLK_PLL, + .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, + .pll = { + .reg = CGU_REG_APLL, + .rate_multiplier = 2, + .m_shift = 20, + .m_bits = 9, + .m_offset = 1, + .n_shift = 14, + .n_bits = 6, + .n_offset = 1, + .od_shift = 11, + .od_bits = 3, + .od_max = 64, + .od_encoding = pll_od_encoding, + .bypass_reg = CGU_REG_CPPCR, + .bypass_bit = 30, + .enable_bit = 0, + .stable_bit = 3, + }, + }, + + [X1830_CLK_MPLL] = { + "mpll", CGU_CLK_PLL, + .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, + .pll = { + .reg = CGU_REG_MPLL, + .rate_multiplier = 2, + .m_shift = 20, + .m_bits = 9, + .m_offset = 1, + .n_shift = 14, + .n_bits = 6, + .n_offset = 1, + .od_shift = 11, + .od_bits = 3, + .od_max = 64, + .od_encoding = pll_od_encoding, + .bypass_reg = CGU_REG_CPPCR, + .bypass_bit = 28, + .enable_bit = 0, + .stable_bit = 3, + }, + }, + + [X1830_CLK_EPLL] = { + "epll", CGU_CLK_PLL, + .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, + .pll = { + .reg = CGU_REG_EPLL, + .rate_multiplier = 2, + .m_shift = 20, + .m_bits = 9, + .m_offset = 1, + .n_shift = 14, + .n_bits = 6, + .n_offset = 1, + .od_shift = 11, + .od_bits = 3, + .od_max = 64, + .od_encoding = pll_od_encoding, + .bypass_reg = CGU_REG_CPPCR, + .bypass_bit = 24, + .enable_bit = 0, + .stable_bit = 3, + }, + }, + + [X1830_CLK_VPLL] = { + "vpll", CGU_CLK_PLL, + .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, + .pll = { + .reg = CGU_REG_VPLL, + .rate_multiplier = 2, + .m_shift = 20, + .m_bits = 9, + .m_offset = 1, + .n_shift = 14, + .n_bits = 6, + .n_offset = 1, + .od_shift = 11, + .od_bits = 3, + .od_max = 64, + .od_encoding = pll_od_encoding, + .bypass_reg = CGU_REG_CPPCR, + .bypass_bit = 26, + .enable_bit = 0, + .stable_bit = 3, + }, + }, + + /* Muxes & dividers */ + + [X1830_CLK_SCLKA] = { + "sclk_a", CGU_CLK_MUX, + .parents = { -1, X1830_CLK_EXCLK, X1830_CLK_APLL, -1 }, + .mux = { CGU_REG_CPCCR, 30, 2 }, + }, + + [X1830_CLK_CPUMUX] = { + "cpu_mux", CGU_CLK_MUX, + .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 }, + .mux = { CGU_REG_CPCCR, 28, 2 }, + }, + + [X1830_CLK_CPU] = { + "cpu", CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { X1830_CLK_CPUMUX, -1, -1, -1 }, + .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 }, + .gate = { CGU_REG_CLKGR1, 15 }, + }, + + [X1830_CLK_L2CACHE] = { + "l2cache", CGU_CLK_DIV, + .parents = { X1830_CLK_CPUMUX, -1, -1, -1 }, + .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 }, + }, + + [X1830_CLK_AHB0] = { + "ahb0", CGU_CLK_MUX | CGU_CLK_DIV, + .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 }, + .mux = { CGU_REG_CPCCR, 26, 2 }, + .div = { CGU_REG_CPCCR, 8, 1, 4, 21, -1, -1 }, + }, + + [X1830_CLK_AHB2PMUX] = { + "ahb2_apb_mux", CGU_CLK_MUX, + .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 }, + .mux = { CGU_REG_CPCCR, 24, 2 }, + }, + + [X1830_CLK_AHB2] = { + "ahb2", CGU_CLK_DIV, + .parents = { X1830_CLK_AHB2PMUX, -1, -1, -1 }, + .div = { CGU_REG_CPCCR, 12, 1, 4, 20, -1, -1 }, + }, + + [X1830_CLK_PCLK] = { + "pclk", CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { X1830_CLK_AHB2PMUX, -1, -1, -1 }, + .div = { CGU_REG_CPCCR, 16, 1, 4, 20, -1, -1 }, + .gate = { CGU_REG_CLKGR1, 14 }, + }, + + [X1830_CLK_DDR] = { + "ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 }, + .mux = { CGU_REG_DDRCDR, 30, 2 }, + .div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 }, + .gate = { CGU_REG_CLKGR0, 31 }, + }, + + [X1830_CLK_MAC] = { + "mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { X1830_CLK_SCLKA, X1830_CLK_MPLL, + X1830_CLK_VPLL, X1830_CLK_EPLL }, + .mux = { CGU_REG_MACCDR, 30, 2 }, + .div = { CGU_REG_MACCDR, 0, 1, 8, 29, 28, 27 }, + .gate = { CGU_REG_CLKGR1, 4 }, + }, + + [X1830_CLK_LCD] = { + "lcd", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { X1830_CLK_SCLKA, X1830_CLK_MPLL, + X1830_CLK_VPLL, X1830_CLK_EPLL }, + .mux = { CGU_REG_LPCDR, 30, 2 }, + .div = { CGU_REG_LPCDR, 0, 1, 8, 28, 27, 26 }, + .gate = { CGU_REG_CLKGR1, 9 }, + }, + + [X1830_CLK_MSCMUX] = { + "msc_mux", CGU_CLK_MUX, + .parents = { X1830_CLK_SCLKA, X1830_CLK_MPLL, + X1830_CLK_VPLL, X1830_CLK_EPLL }, + .mux = { CGU_REG_MSC0CDR, 30, 2 }, + }, + + [X1830_CLK_MSC0] = { + "msc0", CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { X1830_CLK_MSCMUX, -1, -1, -1 }, + .div = { CGU_REG_MSC0CDR, 0, 2, 8, 29, 28, 27 }, + .gate = { CGU_REG_CLKGR0, 4 }, + }, + + [X1830_CLK_MSC1] = { + "msc1", CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { X1830_CLK_MSCMUX, -1, -1, -1 }, + .div = { CGU_REG_MSC1CDR, 0, 2, 8, 29, 28, 27 }, + .gate = { CGU_REG_CLKGR0, 5 }, + }, + + [X1830_CLK_SSIPLL] = { + "ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV, + .parents = { X1830_CLK_SCLKA, X1830_CLK_MPLL, + X1830_CLK_VPLL, X1830_CLK_EPLL }, + .mux = { CGU_REG_SSICDR, 30, 2 }, + .div = { CGU_REG_SSICDR, 0, 1, 8, 28, 27, 26 }, + }, + + [X1830_CLK_SSIPLL_DIV2] = { + "ssi_pll_div2", CGU_CLK_FIXDIV, + .parents = { X1830_CLK_SSIPLL }, + .fixdiv = { 2 }, + }, + + [X1830_CLK_SSIMUX] = { + "ssi_mux", CGU_CLK_MUX, + .parents = { X1830_CLK_EXCLK, X1830_CLK_SSIPLL_DIV2, -1, -1 }, + .mux = { CGU_REG_SSICDR, 29, 1 }, + }, + + /* Gate-only clocks */ + + [X1830_CLK_EMC] = { + "emc", CGU_CLK_GATE, + .parents = { X1830_CLK_AHB2, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR0, 0 }, + }, + + [X1830_CLK_EFUSE] = { + "efuse", CGU_CLK_GATE, + .parents = { X1830_CLK_AHB2, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR0, 1 }, + }, + + [X1830_CLK_OTG] = { + "otg", CGU_CLK_GATE, + .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR0, 3 }, + }, + + [X1830_CLK_SSI0] = { + "ssi0", CGU_CLK_GATE, + .parents = { X1830_CLK_SSIMUX, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR0, 6 }, + }, + + [X1830_CLK_SMB0] = { + "smb0", CGU_CLK_GATE, + .parents = { X1830_CLK_PCLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR0, 7 }, + }, + + [X1830_CLK_SMB1] = { + "smb1", CGU_CLK_GATE, + .parents = { X1830_CLK_PCLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR0, 8 }, + }, + + [X1830_CLK_SMB2] = { + "smb2", CGU_CLK_GATE, + .parents = { X1830_CLK_PCLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR0, 9 }, + }, + + [X1830_CLK_UART0] = { + "uart0", CGU_CLK_GATE, + .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR0, 14 }, + }, + + [X1830_CLK_UART1] = { + "uart1", CGU_CLK_GATE, + .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR0, 15 }, + }, + + [X1830_CLK_SSI1] = { + "ssi1", CGU_CLK_GATE, + .parents = { X1830_CLK_SSIMUX, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR0, 19 }, + }, + + [X1830_CLK_SFC] = { + "sfc", CGU_CLK_GATE, + .parents = { X1830_CLK_SSIPLL, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR0, 20 }, + }, + + [X1830_CLK_PDMA] = { + "pdma", CGU_CLK_GATE, + .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR0, 21 }, + }, + + [X1830_CLK_DTRNG] = { + "dtrng", CGU_CLK_GATE, + .parents = { X1830_CLK_PCLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR1, 1 }, + }, + + [X1830_CLK_OST] = { + "ost", CGU_CLK_GATE, + .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR1, 11 }, + }, +}; + +static void __init x1830_cgu_init(struct device_node *np) +{ + int retval; + + cgu = ingenic_cgu_new(x1830_cgu_clocks, + ARRAY_SIZE(x1830_cgu_clocks), np); + if (!cgu) { + pr_err("%s: failed to initialise CGU\n", __func__); + return; + } + + retval = ingenic_cgu_register_clocks(cgu); + if (retval) { + pr_err("%s: failed to register CGU Clocks\n", __func__); + return; + } + + ingenic_cgu_register_syscore_ops(cgu); +} +CLK_OF_DECLARE_DRIVER(x1830_cgu, "ingenic,x1830-cgu", x1830_cgu_init); -- 2.7.4 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v6 4/6] clk: Ingenic: Add CGU driver for X1830. 2020-03-22 8:21 ` [PATCH v6 4/6] clk: Ingenic: Add CGU driver for X1830 周琰杰 (Zhou Yanjie) @ 2020-03-22 12:30 ` Zhou Yanjie 2020-03-22 12:59 ` Zhou Yanjie 0 siblings, 1 reply; 12+ messages in thread From: Zhou Yanjie @ 2020-03-22 12:30 UTC (permalink / raw) To: Paul Cercueil Cc: linux-clk, linux-kernel, devicetree, sboyd, mturquette, robh+dt, mark.rutland, dongsheng.qiu, yanfei.li, sernia.zhou, zhenwenjin Hi Paul, On 2020年03月22日 20:08, Paul Cercueil wrote: > Hi Zhou, > > Le dim. 22 mars 2020 à 16:21, 周琰杰 (Zhou Yanjie) > <zhouyanjie@wanyeetech.com> a écrit : >> Add support for the clocks provided by the CGU in the Ingenic X1830 >> SoC, making use of the cgu code to do the heavy lifting. >> >> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> >> --- >> >> Notes: >> v1->v2: >> 1.Use two fields (pll_reg & bypass_reg) instead of the 2-values >> array (reg[2]). >> 2.Remove the "pll_info->version" and add a >> "pll_info->rate_multiplier". >> 3.Change my Signed-off-by from "Zhou Yanjie <zhouyanjie@zoho.com>" >> to "周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>" because >> the old mailbox is in an unstable state. >> >> v2->v3: >> Adjust order from [4/5] in v2 to [5/5] in v3. >> >> v3->v4: >> Adjust order from [5/5] in v3 to [4/4] in v4. >> >> v4->v5: >> Rebase on top of kernel 5.6-rc1. >> >> v5->v6: >> Add missing part of X1830's CGU. >> >> drivers/clk/ingenic/Kconfig | 10 ++ >> drivers/clk/ingenic/Makefile | 1 + >> drivers/clk/ingenic/x1830-cgu.c | 387 >> ++++++++++++++++++++++++++++++++++++++++ >> 3 files changed, 398 insertions(+) >> create mode 100644 drivers/clk/ingenic/x1830-cgu.c >> >> diff --git a/drivers/clk/ingenic/Kconfig b/drivers/clk/ingenic/Kconfig >> index b4555b4..580b0cf 100644 >> --- a/drivers/clk/ingenic/Kconfig >> +++ b/drivers/clk/ingenic/Kconfig >> @@ -55,6 +55,16 @@ config INGENIC_CGU_X1000 >> >> If building for a X1000 SoC, you want to say Y here. >> >> +config INGENIC_CGU_X1830 >> + bool "Ingenic X1830 CGU driver" >> + default MACH_X1830 >> + select INGENIC_CGU_COMMON >> + help >> + Support the clocks provided by the CGU hardware on Ingenic X1830 >> + and compatible SoCs. >> + >> + If building for a X1830 SoC, you want to say Y here. >> + >> config INGENIC_TCU_CLK >> bool "Ingenic JZ47xx TCU clocks driver" >> default MACH_INGENIC >> diff --git a/drivers/clk/ingenic/Makefile b/drivers/clk/ingenic/Makefile >> index 8b1dad9..aaa4bff 100644 >> --- a/drivers/clk/ingenic/Makefile >> +++ b/drivers/clk/ingenic/Makefile >> @@ -5,4 +5,5 @@ obj-$(CONFIG_INGENIC_CGU_JZ4725B) += jz4725b-cgu.o >> obj-$(CONFIG_INGENIC_CGU_JZ4770) += jz4770-cgu.o >> obj-$(CONFIG_INGENIC_CGU_JZ4780) += jz4780-cgu.o >> obj-$(CONFIG_INGENIC_CGU_X1000) += x1000-cgu.o >> +obj-$(CONFIG_INGENIC_CGU_X1830) += x1830-cgu.o >> obj-$(CONFIG_INGENIC_TCU_CLK) += tcu.o >> diff --git a/drivers/clk/ingenic/x1830-cgu.c >> b/drivers/clk/ingenic/x1830-cgu.c >> new file mode 100644 >> index 00000000..0bc927f >> --- /dev/null >> +++ b/drivers/clk/ingenic/x1830-cgu.c >> @@ -0,0 +1,387 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * X1830 SoC CGU driver >> + * Copyright (c) 2019 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> >> + */ >> + >> +#include <linux/clk-provider.h> >> +#include <linux/delay.h> >> +#include <linux/of.h> >> +#include <dt-bindings/clock/x1830-cgu.h> > > Please order the includes alphabetically (but with <> ones still > before "" ones, and with a blank line between the two). > Sure, seems the "x1000-cgu.c" also has this problem, I will fix both in next version. >> +#include "cgu.h" >> +#include "pm.h" >> + >> +/* CGU register offsets */ >> +#define CGU_REG_CPCCR 0x00 >> +#define CGU_REG_CPPCR 0x0c >> +#define CGU_REG_APLL 0x10 >> +#define CGU_REG_MPLL 0x14 >> +#define CGU_REG_CLKGR0 0x20 >> +#define CGU_REG_OPCR 0x24 >> +#define CGU_REG_CLKGR1 0x28 >> +#define CGU_REG_DDRCDR 0x2c >> +#define CGU_REG_USBPCR 0x3c >> +#define CGU_REG_USBRDT 0x40 >> +#define CGU_REG_USBVBFIL 0x44 >> +#define CGU_REG_USBPCR1 0x48 >> +#define CGU_REG_MACCDR 0x54 >> +#define CGU_REG_EPLL 0x58 >> +#define CGU_REG_I2SCDR 0x60 >> +#define CGU_REG_LPCDR 0x64 >> +#define CGU_REG_MSC0CDR 0x68 >> +#define CGU_REG_I2SCDR1 0x70 >> +#define CGU_REG_SSICDR 0x74 >> +#define CGU_REG_CIMCDR 0x7c >> +#define CGU_REG_MSC1CDR 0xa4 >> +#define CGU_REG_CMP_INTR 0xb0 >> +#define CGU_REG_CMP_INTRE 0xb4 >> +#define CGU_REG_DRCG 0xd0 >> +#define CGU_REG_CPCSR 0xd4 >> +#define CGU_REG_VPLL 0xe0 >> +#define CGU_REG_MACPHYC 0xe8 >> + >> +/* bits within the OPCR register */ >> +#define OPCR_SPENDN0 BIT(7) >> +#define OPCR_SPENDN1 BIT(6) >> + >> +static struct ingenic_cgu *cgu; > > I don't think you need this global variable at all. > This variable will be used in x1830_cgu_init(), and it is also the same in other cgu drivers of other Ingenic processors, I think we should keep it. Thanks and best regards! > -Paul > >> + >> +static const s8 pll_od_encoding[64] = { >> + 0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3, >> + -1, -1, -1, -1, -1, -1, -1, 0x4, >> + -1, -1, -1, -1, -1, -1, -1, -1, >> + -1, -1, -1, -1, -1, -1, -1, 0x5, >> + -1, -1, -1, -1, -1, -1, -1, -1, >> + -1, -1, -1, -1, -1, -1, -1, -1, >> + -1, -1, -1, -1, -1, -1, -1, -1, >> + -1, -1, -1, -1, -1, -1, -1, 0x6, >> +}; >> + >> +static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = { >> + >> + /* External clocks */ >> + >> + [X1830_CLK_EXCLK] = { "ext", CGU_CLK_EXT }, >> + [X1830_CLK_RTCLK] = { "rtc", CGU_CLK_EXT }, >> + >> + /* PLLs */ >> + >> + [X1830_CLK_APLL] = { >> + "apll", CGU_CLK_PLL, >> + .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, >> + .pll = { >> + .reg = CGU_REG_APLL, >> + .rate_multiplier = 2, >> + .m_shift = 20, >> + .m_bits = 9, >> + .m_offset = 1, >> + .n_shift = 14, >> + .n_bits = 6, >> + .n_offset = 1, >> + .od_shift = 11, >> + .od_bits = 3, >> + .od_max = 64, >> + .od_encoding = pll_od_encoding, >> + .bypass_reg = CGU_REG_CPPCR, >> + .bypass_bit = 30, >> + .enable_bit = 0, >> + .stable_bit = 3, >> + }, >> + }, >> + >> + [X1830_CLK_MPLL] = { >> + "mpll", CGU_CLK_PLL, >> + .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, >> + .pll = { >> + .reg = CGU_REG_MPLL, >> + .rate_multiplier = 2, >> + .m_shift = 20, >> + .m_bits = 9, >> + .m_offset = 1, >> + .n_shift = 14, >> + .n_bits = 6, >> + .n_offset = 1, >> + .od_shift = 11, >> + .od_bits = 3, >> + .od_max = 64, >> + .od_encoding = pll_od_encoding, >> + .bypass_reg = CGU_REG_CPPCR, >> + .bypass_bit = 28, >> + .enable_bit = 0, >> + .stable_bit = 3, >> + }, >> + }, >> + >> + [X1830_CLK_EPLL] = { >> + "epll", CGU_CLK_PLL, >> + .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, >> + .pll = { >> + .reg = CGU_REG_EPLL, >> + .rate_multiplier = 2, >> + .m_shift = 20, >> + .m_bits = 9, >> + .m_offset = 1, >> + .n_shift = 14, >> + .n_bits = 6, >> + .n_offset = 1, >> + .od_shift = 11, >> + .od_bits = 3, >> + .od_max = 64, >> + .od_encoding = pll_od_encoding, >> + .bypass_reg = CGU_REG_CPPCR, >> + .bypass_bit = 24, >> + .enable_bit = 0, >> + .stable_bit = 3, >> + }, >> + }, >> + >> + [X1830_CLK_VPLL] = { >> + "vpll", CGU_CLK_PLL, >> + .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, >> + .pll = { >> + .reg = CGU_REG_VPLL, >> + .rate_multiplier = 2, >> + .m_shift = 20, >> + .m_bits = 9, >> + .m_offset = 1, >> + .n_shift = 14, >> + .n_bits = 6, >> + .n_offset = 1, >> + .od_shift = 11, >> + .od_bits = 3, >> + .od_max = 64, >> + .od_encoding = pll_od_encoding, >> + .bypass_reg = CGU_REG_CPPCR, >> + .bypass_bit = 26, >> + .enable_bit = 0, >> + .stable_bit = 3, >> + }, >> + }, >> + >> + /* Muxes & dividers */ >> + >> + [X1830_CLK_SCLKA] = { >> + "sclk_a", CGU_CLK_MUX, >> + .parents = { -1, X1830_CLK_EXCLK, X1830_CLK_APLL, -1 }, >> + .mux = { CGU_REG_CPCCR, 30, 2 }, >> + }, >> + >> + [X1830_CLK_CPUMUX] = { >> + "cpu_mux", CGU_CLK_MUX, >> + .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 }, >> + .mux = { CGU_REG_CPCCR, 28, 2 }, >> + }, >> + >> + [X1830_CLK_CPU] = { >> + "cpu", CGU_CLK_DIV | CGU_CLK_GATE, >> + .parents = { X1830_CLK_CPUMUX, -1, -1, -1 }, >> + .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 }, >> + .gate = { CGU_REG_CLKGR1, 15 }, >> + }, >> + >> + [X1830_CLK_L2CACHE] = { >> + "l2cache", CGU_CLK_DIV, >> + .parents = { X1830_CLK_CPUMUX, -1, -1, -1 }, >> + .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 }, >> + }, >> + >> + [X1830_CLK_AHB0] = { >> + "ahb0", CGU_CLK_MUX | CGU_CLK_DIV, >> + .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 }, >> + .mux = { CGU_REG_CPCCR, 26, 2 }, >> + .div = { CGU_REG_CPCCR, 8, 1, 4, 21, -1, -1 }, >> + }, >> + >> + [X1830_CLK_AHB2PMUX] = { >> + "ahb2_apb_mux", CGU_CLK_MUX, >> + .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 }, >> + .mux = { CGU_REG_CPCCR, 24, 2 }, >> + }, >> + >> + [X1830_CLK_AHB2] = { >> + "ahb2", CGU_CLK_DIV, >> + .parents = { X1830_CLK_AHB2PMUX, -1, -1, -1 }, >> + .div = { CGU_REG_CPCCR, 12, 1, 4, 20, -1, -1 }, >> + }, >> + >> + [X1830_CLK_PCLK] = { >> + "pclk", CGU_CLK_DIV | CGU_CLK_GATE, >> + .parents = { X1830_CLK_AHB2PMUX, -1, -1, -1 }, >> + .div = { CGU_REG_CPCCR, 16, 1, 4, 20, -1, -1 }, >> + .gate = { CGU_REG_CLKGR1, 14 }, >> + }, >> + >> + [X1830_CLK_DDR] = { >> + "ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, >> + .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 }, >> + .mux = { CGU_REG_DDRCDR, 30, 2 }, >> + .div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 }, >> + .gate = { CGU_REG_CLKGR0, 31 }, >> + }, >> + >> + [X1830_CLK_MAC] = { >> + "mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, >> + .parents = { X1830_CLK_SCLKA, X1830_CLK_MPLL, >> + X1830_CLK_VPLL, X1830_CLK_EPLL }, >> + .mux = { CGU_REG_MACCDR, 30, 2 }, >> + .div = { CGU_REG_MACCDR, 0, 1, 8, 29, 28, 27 }, >> + .gate = { CGU_REG_CLKGR1, 4 }, >> + }, >> + >> + [X1830_CLK_LCD] = { >> + "lcd", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, >> + .parents = { X1830_CLK_SCLKA, X1830_CLK_MPLL, >> + X1830_CLK_VPLL, X1830_CLK_EPLL }, >> + .mux = { CGU_REG_LPCDR, 30, 2 }, >> + .div = { CGU_REG_LPCDR, 0, 1, 8, 28, 27, 26 }, >> + .gate = { CGU_REG_CLKGR1, 9 }, >> + }, >> + >> + [X1830_CLK_MSCMUX] = { >> + "msc_mux", CGU_CLK_MUX, >> + .parents = { X1830_CLK_SCLKA, X1830_CLK_MPLL, >> + X1830_CLK_VPLL, X1830_CLK_EPLL }, >> + .mux = { CGU_REG_MSC0CDR, 30, 2 }, >> + }, >> + >> + [X1830_CLK_MSC0] = { >> + "msc0", CGU_CLK_DIV | CGU_CLK_GATE, >> + .parents = { X1830_CLK_MSCMUX, -1, -1, -1 }, >> + .div = { CGU_REG_MSC0CDR, 0, 2, 8, 29, 28, 27 }, >> + .gate = { CGU_REG_CLKGR0, 4 }, >> + }, >> + >> + [X1830_CLK_MSC1] = { >> + "msc1", CGU_CLK_DIV | CGU_CLK_GATE, >> + .parents = { X1830_CLK_MSCMUX, -1, -1, -1 }, >> + .div = { CGU_REG_MSC1CDR, 0, 2, 8, 29, 28, 27 }, >> + .gate = { CGU_REG_CLKGR0, 5 }, >> + }, >> + >> + [X1830_CLK_SSIPLL] = { >> + "ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV, >> + .parents = { X1830_CLK_SCLKA, X1830_CLK_MPLL, >> + X1830_CLK_VPLL, X1830_CLK_EPLL }, >> + .mux = { CGU_REG_SSICDR, 30, 2 }, >> + .div = { CGU_REG_SSICDR, 0, 1, 8, 28, 27, 26 }, >> + }, >> + >> + [X1830_CLK_SSIPLL_DIV2] = { >> + "ssi_pll_div2", CGU_CLK_FIXDIV, >> + .parents = { X1830_CLK_SSIPLL }, >> + .fixdiv = { 2 }, >> + }, >> + >> + [X1830_CLK_SSIMUX] = { >> + "ssi_mux", CGU_CLK_MUX, >> + .parents = { X1830_CLK_EXCLK, X1830_CLK_SSIPLL_DIV2, -1, -1 }, >> + .mux = { CGU_REG_SSICDR, 29, 1 }, >> + }, >> + >> + /* Gate-only clocks */ >> + >> + [X1830_CLK_EMC] = { >> + "emc", CGU_CLK_GATE, >> + .parents = { X1830_CLK_AHB2, -1, -1, -1 }, >> + .gate = { CGU_REG_CLKGR0, 0 }, >> + }, >> + >> + [X1830_CLK_EFUSE] = { >> + "efuse", CGU_CLK_GATE, >> + .parents = { X1830_CLK_AHB2, -1, -1, -1 }, >> + .gate = { CGU_REG_CLKGR0, 1 }, >> + }, >> + >> + [X1830_CLK_OTG] = { >> + "otg", CGU_CLK_GATE, >> + .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, >> + .gate = { CGU_REG_CLKGR0, 3 }, >> + }, >> + >> + [X1830_CLK_SSI0] = { >> + "ssi0", CGU_CLK_GATE, >> + .parents = { X1830_CLK_SSIMUX, -1, -1, -1 }, >> + .gate = { CGU_REG_CLKGR0, 6 }, >> + }, >> + >> + [X1830_CLK_SMB0] = { >> + "smb0", CGU_CLK_GATE, >> + .parents = { X1830_CLK_PCLK, -1, -1, -1 }, >> + .gate = { CGU_REG_CLKGR0, 7 }, >> + }, >> + >> + [X1830_CLK_SMB1] = { >> + "smb1", CGU_CLK_GATE, >> + .parents = { X1830_CLK_PCLK, -1, -1, -1 }, >> + .gate = { CGU_REG_CLKGR0, 8 }, >> + }, >> + >> + [X1830_CLK_SMB2] = { >> + "smb2", CGU_CLK_GATE, >> + .parents = { X1830_CLK_PCLK, -1, -1, -1 }, >> + .gate = { CGU_REG_CLKGR0, 9 }, >> + }, >> + >> + [X1830_CLK_UART0] = { >> + "uart0", CGU_CLK_GATE, >> + .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, >> + .gate = { CGU_REG_CLKGR0, 14 }, >> + }, >> + >> + [X1830_CLK_UART1] = { >> + "uart1", CGU_CLK_GATE, >> + .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, >> + .gate = { CGU_REG_CLKGR0, 15 }, >> + }, >> + >> + [X1830_CLK_SSI1] = { >> + "ssi1", CGU_CLK_GATE, >> + .parents = { X1830_CLK_SSIMUX, -1, -1, -1 }, >> + .gate = { CGU_REG_CLKGR0, 19 }, >> + }, >> + >> + [X1830_CLK_SFC] = { >> + "sfc", CGU_CLK_GATE, >> + .parents = { X1830_CLK_SSIPLL, -1, -1, -1 }, >> + .gate = { CGU_REG_CLKGR0, 20 }, >> + }, >> + >> + [X1830_CLK_PDMA] = { >> + "pdma", CGU_CLK_GATE, >> + .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, >> + .gate = { CGU_REG_CLKGR0, 21 }, >> + }, >> + >> + [X1830_CLK_DTRNG] = { >> + "dtrng", CGU_CLK_GATE, >> + .parents = { X1830_CLK_PCLK, -1, -1, -1 }, >> + .gate = { CGU_REG_CLKGR1, 1 }, >> + }, >> + >> + [X1830_CLK_OST] = { >> + "ost", CGU_CLK_GATE, >> + .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, >> + .gate = { CGU_REG_CLKGR1, 11 }, >> + }, >> +}; >> + >> +static void __init x1830_cgu_init(struct device_node *np) >> +{ >> + int retval; >> + >> + cgu = ingenic_cgu_new(x1830_cgu_clocks, >> + ARRAY_SIZE(x1830_cgu_clocks), np); >> + if (!cgu) { >> + pr_err("%s: failed to initialise CGU\n", __func__); >> + return; >> + } >> + >> + retval = ingenic_cgu_register_clocks(cgu); >> + if (retval) { >> + pr_err("%s: failed to register CGU Clocks\n", __func__); >> + return; >> + } >> + >> + ingenic_cgu_register_syscore_ops(cgu); >> +} >> +CLK_OF_DECLARE_DRIVER(x1830_cgu, "ingenic,x1830-cgu", x1830_cgu_init); >> -- >> 2.7.4 >> > ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v6 4/6] clk: Ingenic: Add CGU driver for X1830. 2020-03-22 12:30 ` Zhou Yanjie @ 2020-03-22 12:59 ` Zhou Yanjie 0 siblings, 0 replies; 12+ messages in thread From: Zhou Yanjie @ 2020-03-22 12:59 UTC (permalink / raw) To: Paul Cercueil Cc: linux-clk, linux-kernel, devicetree, sboyd, mturquette, robh+dt, mark.rutland, dongsheng.qiu, yanfei.li, sernia.zhou, zhenwenjin Hi Paul, On 2020年03月22日 20:49, Paul Cercueil wrote: > > > Le dim. 22 mars 2020 à 20:30, Zhou Yanjie <zhouyanjie@wanyeetech.com> > a écrit : >> Hi Paul, >> >> On 2020年03月22日 20:08, Paul Cercueil wrote: >>> Hi Zhou, >>> >>> Le dim. 22 mars 2020 à 16:21, 周琰杰 (Zhou Yanjie) >>> \x7f<zhouyanjie@wanyeetech.com> a écrit : >>>> Add support for the clocks provided by the CGU in the Ingenic X1830 >>>> SoC, making use of the cgu code to do the heavy lifting. >>>> >>>> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> >>>> --- >>>> >>>> Notes: >>>> v1->v2: >>>> 1.Use two fields (pll_reg & bypass_reg) instead of the 2-values >>>> array (reg[2]). >>>> 2.Remove the "pll_info->version" and add a >>>> \x7f\x7f"pll_info->rate_multiplier". >>>> 3.Change my Signed-off-by from "Zhou Yanjie <zhouyanjie@zoho.com>" >>>> to "周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>" because >>>> the old mailbox is in an unstable state. >>>> >>>> v2->v3: >>>> Adjust order from [4/5] in v2 to [5/5] in v3. >>>> >>>> v3->v4: >>>> Adjust order from [5/5] in v3 to [4/4] in v4. >>>> >>>> v4->v5: >>>> Rebase on top of kernel 5.6-rc1. >>>> >>>> v5->v6: >>>> Add missing part of X1830's CGU. >>>> >>>> drivers/clk/ingenic/Kconfig | 10 ++ >>>> drivers/clk/ingenic/Makefile | 1 + >>>> drivers/clk/ingenic/x1830-cgu.c | 387 >>>> \x7f\x7f++++++++++++++++++++++++++++++++++++++++ >>>> 3 files changed, 398 insertions(+) >>>> create mode 100644 drivers/clk/ingenic/x1830-cgu.c >>>> >>>> diff --git a/drivers/clk/ingenic/Kconfig b/drivers/clk/ingenic/Kconfig >>>> index b4555b4..580b0cf 100644 >>>> --- a/drivers/clk/ingenic/Kconfig >>>> +++ b/drivers/clk/ingenic/Kconfig >>>> @@ -55,6 +55,16 @@ config INGENIC_CGU_X1000 >>>> >>>> If building for a X1000 SoC, you want to say Y here. >>>> >>>> +config INGENIC_CGU_X1830 >>>> + bool "Ingenic X1830 CGU driver" >>>> + default MACH_X1830 >>>> + select INGENIC_CGU_COMMON >>>> + help >>>> + Support the clocks provided by the CGU hardware on Ingenic >>>> X1830 >>>> + and compatible SoCs. >>>> + >>>> + If building for a X1830 SoC, you want to say Y here. >>>> + >>>> config INGENIC_TCU_CLK >>>> bool "Ingenic JZ47xx TCU clocks driver" >>>> default MACH_INGENIC >>>> diff --git a/drivers/clk/ingenic/Makefile >>>> b/drivers/clk/ingenic/Makefile >>>> index 8b1dad9..aaa4bff 100644 >>>> --- a/drivers/clk/ingenic/Makefile >>>> +++ b/drivers/clk/ingenic/Makefile >>>> @@ -5,4 +5,5 @@ obj-$(CONFIG_INGENIC_CGU_JZ4725B) += jz4725b-cgu.o >>>> obj-$(CONFIG_INGENIC_CGU_JZ4770) += jz4770-cgu.o >>>> obj-$(CONFIG_INGENIC_CGU_JZ4780) += jz4780-cgu.o >>>> obj-$(CONFIG_INGENIC_CGU_X1000) += x1000-cgu.o >>>> +obj-$(CONFIG_INGENIC_CGU_X1830) += x1830-cgu.o >>>> obj-$(CONFIG_INGENIC_TCU_CLK) += tcu.o >>>> diff --git a/drivers/clk/ingenic/x1830-cgu.c >>>> \x7f\x7fb/drivers/clk/ingenic/x1830-cgu.c >>>> new file mode 100644 >>>> index 00000000..0bc927f >>>> --- /dev/null >>>> +++ b/drivers/clk/ingenic/x1830-cgu.c >>>> @@ -0,0 +1,387 @@ >>>> +// SPDX-License-Identifier: GPL-2.0 >>>> +/* >>>> + * X1830 SoC CGU driver >>>> + * Copyright (c) 2019 周琰杰 (Zhou Yanjie) >>>> <zhouyanjie@wanyeetech.com> >>>> + */ >>>> + >>>> +#include <linux/clk-provider.h> >>>> +#include <linux/delay.h> >>>> +#include <linux/of.h> >>>> +#include <dt-bindings/clock/x1830-cgu.h> >>> >>> Please order the includes alphabetically (but with <> ones still >>> \x7fbefore "" ones, and with a blank line between the two). >>> >> >> Sure, seems the "x1000-cgu.c" also has this problem, I will fix both >> in next version. >> >>>> +#include "cgu.h" >>>> +#include "pm.h" >>>> + >>>> +/* CGU register offsets */ >>>> +#define CGU_REG_CPCCR 0x00 >>>> +#define CGU_REG_CPPCR 0x0c >>>> +#define CGU_REG_APLL 0x10 >>>> +#define CGU_REG_MPLL 0x14 >>>> +#define CGU_REG_CLKGR0 0x20 >>>> +#define CGU_REG_OPCR 0x24 >>>> +#define CGU_REG_CLKGR1 0x28 >>>> +#define CGU_REG_DDRCDR 0x2c >>>> +#define CGU_REG_USBPCR 0x3c >>>> +#define CGU_REG_USBRDT 0x40 >>>> +#define CGU_REG_USBVBFIL 0x44 >>>> +#define CGU_REG_USBPCR1 0x48 >>>> +#define CGU_REG_MACCDR 0x54 >>>> +#define CGU_REG_EPLL 0x58 >>>> +#define CGU_REG_I2SCDR 0x60 >>>> +#define CGU_REG_LPCDR 0x64 >>>> +#define CGU_REG_MSC0CDR 0x68 >>>> +#define CGU_REG_I2SCDR1 0x70 >>>> +#define CGU_REG_SSICDR 0x74 >>>> +#define CGU_REG_CIMCDR 0x7c >>>> +#define CGU_REG_MSC1CDR 0xa4 >>>> +#define CGU_REG_CMP_INTR 0xb0 >>>> +#define CGU_REG_CMP_INTRE 0xb4 >>>> +#define CGU_REG_DRCG 0xd0 >>>> +#define CGU_REG_CPCSR 0xd4 >>>> +#define CGU_REG_VPLL 0xe0 >>>> +#define CGU_REG_MACPHYC 0xe8 >>>> + >>>> +/* bits within the OPCR register */ >>>> +#define OPCR_SPENDN0 BIT(7) >>>> +#define OPCR_SPENDN1 BIT(6) >>>> + >>>> +static struct ingenic_cgu *cgu; >>> >>> I don't think you need this global variable at all. >>> >> >> This variable will be used in x1830_cgu_init(), and it is also the >> same in other cgu drivers of other Ingenic processors, I think we >> should keep it. > > The "others do it that way" has never been a valid argument ;) > > It's used only in x1830_cgu_init(), so it should be a local variable > within this function. > Sure, I'll move it into x1830_cgu_init() as a local variable. > -Paul > >> Thanks and best regards! >> >>> -Paul >>> >>>> + >>>> +static const s8 pll_od_encoding[64] = { >>>> + 0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3, >>>> + -1, -1, -1, -1, -1, -1, -1, 0x4, >>>> + -1, -1, -1, -1, -1, -1, -1, -1, >>>> + -1, -1, -1, -1, -1, -1, -1, 0x5, >>>> + -1, -1, -1, -1, -1, -1, -1, -1, >>>> + -1, -1, -1, -1, -1, -1, -1, -1, >>>> + -1, -1, -1, -1, -1, -1, -1, -1, >>>> + -1, -1, -1, -1, -1, -1, -1, 0x6, >>>> +}; >>>> + >>>> +static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = { >>>> + >>>> + /* External clocks */ >>>> + >>>> + [X1830_CLK_EXCLK] = { "ext", CGU_CLK_EXT }, >>>> + [X1830_CLK_RTCLK] = { "rtc", CGU_CLK_EXT }, >>>> + >>>> + /* PLLs */ >>>> + >>>> + [X1830_CLK_APLL] = { >>>> + "apll", CGU_CLK_PLL, >>>> + .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, >>>> + .pll = { >>>> + .reg = CGU_REG_APLL, >>>> + .rate_multiplier = 2, >>>> + .m_shift = 20, >>>> + .m_bits = 9, >>>> + .m_offset = 1, >>>> + .n_shift = 14, >>>> + .n_bits = 6, >>>> + .n_offset = 1, >>>> + .od_shift = 11, >>>> + .od_bits = 3, >>>> + .od_max = 64, >>>> + .od_encoding = pll_od_encoding, >>>> + .bypass_reg = CGU_REG_CPPCR, >>>> + .bypass_bit = 30, >>>> + .enable_bit = 0, >>>> + .stable_bit = 3, >>>> + }, >>>> + }, >>>> + >>>> + [X1830_CLK_MPLL] = { >>>> + "mpll", CGU_CLK_PLL, >>>> + .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, >>>> + .pll = { >>>> + .reg = CGU_REG_MPLL, >>>> + .rate_multiplier = 2, >>>> + .m_shift = 20, >>>> + .m_bits = 9, >>>> + .m_offset = 1, >>>> + .n_shift = 14, >>>> + .n_bits = 6, >>>> + .n_offset = 1, >>>> + .od_shift = 11, >>>> + .od_bits = 3, >>>> + .od_max = 64, >>>> + .od_encoding = pll_od_encoding, >>>> + .bypass_reg = CGU_REG_CPPCR, >>>> + .bypass_bit = 28, >>>> + .enable_bit = 0, >>>> + .stable_bit = 3, >>>> + }, >>>> + }, >>>> + >>>> + [X1830_CLK_EPLL] = { >>>> + "epll", CGU_CLK_PLL, >>>> + .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, >>>> + .pll = { >>>> + .reg = CGU_REG_EPLL, >>>> + .rate_multiplier = 2, >>>> + .m_shift = 20, >>>> + .m_bits = 9, >>>> + .m_offset = 1, >>>> + .n_shift = 14, >>>> + .n_bits = 6, >>>> + .n_offset = 1, >>>> + .od_shift = 11, >>>> + .od_bits = 3, >>>> + .od_max = 64, >>>> + .od_encoding = pll_od_encoding, >>>> + .bypass_reg = CGU_REG_CPPCR, >>>> + .bypass_bit = 24, >>>> + .enable_bit = 0, >>>> + .stable_bit = 3, >>>> + }, >>>> + }, >>>> + >>>> + [X1830_CLK_VPLL] = { >>>> + "vpll", CGU_CLK_PLL, >>>> + .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, >>>> + .pll = { >>>> + .reg = CGU_REG_VPLL, >>>> + .rate_multiplier = 2, >>>> + .m_shift = 20, >>>> + .m_bits = 9, >>>> + .m_offset = 1, >>>> + .n_shift = 14, >>>> + .n_bits = 6, >>>> + .n_offset = 1, >>>> + .od_shift = 11, >>>> + .od_bits = 3, >>>> + .od_max = 64, >>>> + .od_encoding = pll_od_encoding, >>>> + .bypass_reg = CGU_REG_CPPCR, >>>> + .bypass_bit = 26, >>>> + .enable_bit = 0, >>>> + .stable_bit = 3, >>>> + }, >>>> + }, >>>> + >>>> + /* Muxes & dividers */ >>>> + >>>> + [X1830_CLK_SCLKA] = { >>>> + "sclk_a", CGU_CLK_MUX, >>>> + .parents = { -1, X1830_CLK_EXCLK, X1830_CLK_APLL, -1 }, >>>> + .mux = { CGU_REG_CPCCR, 30, 2 }, >>>> + }, >>>> + >>>> + [X1830_CLK_CPUMUX] = { >>>> + "cpu_mux", CGU_CLK_MUX, >>>> + .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 }, >>>> + .mux = { CGU_REG_CPCCR, 28, 2 }, >>>> + }, >>>> + >>>> + [X1830_CLK_CPU] = { >>>> + "cpu", CGU_CLK_DIV | CGU_CLK_GATE, >>>> + .parents = { X1830_CLK_CPUMUX, -1, -1, -1 }, >>>> + .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 }, >>>> + .gate = { CGU_REG_CLKGR1, 15 }, >>>> + }, >>>> + >>>> + [X1830_CLK_L2CACHE] = { >>>> + "l2cache", CGU_CLK_DIV, >>>> + .parents = { X1830_CLK_CPUMUX, -1, -1, -1 }, >>>> + .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 }, >>>> + }, >>>> + >>>> + [X1830_CLK_AHB0] = { >>>> + "ahb0", CGU_CLK_MUX | CGU_CLK_DIV, >>>> + .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 }, >>>> + .mux = { CGU_REG_CPCCR, 26, 2 }, >>>> + .div = { CGU_REG_CPCCR, 8, 1, 4, 21, -1, -1 }, >>>> + }, >>>> + >>>> + [X1830_CLK_AHB2PMUX] = { >>>> + "ahb2_apb_mux", CGU_CLK_MUX, >>>> + .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 }, >>>> + .mux = { CGU_REG_CPCCR, 24, 2 }, >>>> + }, >>>> + >>>> + [X1830_CLK_AHB2] = { >>>> + "ahb2", CGU_CLK_DIV, >>>> + .parents = { X1830_CLK_AHB2PMUX, -1, -1, -1 }, >>>> + .div = { CGU_REG_CPCCR, 12, 1, 4, 20, -1, -1 }, >>>> + }, >>>> + >>>> + [X1830_CLK_PCLK] = { >>>> + "pclk", CGU_CLK_DIV | CGU_CLK_GATE, >>>> + .parents = { X1830_CLK_AHB2PMUX, -1, -1, -1 }, >>>> + .div = { CGU_REG_CPCCR, 16, 1, 4, 20, -1, -1 }, >>>> + .gate = { CGU_REG_CLKGR1, 14 }, >>>> + }, >>>> + >>>> + [X1830_CLK_DDR] = { >>>> + "ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, >>>> + .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 }, >>>> + .mux = { CGU_REG_DDRCDR, 30, 2 }, >>>> + .div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 }, >>>> + .gate = { CGU_REG_CLKGR0, 31 }, >>>> + }, >>>> + >>>> + [X1830_CLK_MAC] = { >>>> + "mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, >>>> + .parents = { X1830_CLK_SCLKA, X1830_CLK_MPLL, >>>> + X1830_CLK_VPLL, X1830_CLK_EPLL }, >>>> + .mux = { CGU_REG_MACCDR, 30, 2 }, >>>> + .div = { CGU_REG_MACCDR, 0, 1, 8, 29, 28, 27 }, >>>> + .gate = { CGU_REG_CLKGR1, 4 }, >>>> + }, >>>> + >>>> + [X1830_CLK_LCD] = { >>>> + "lcd", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, >>>> + .parents = { X1830_CLK_SCLKA, X1830_CLK_MPLL, >>>> + X1830_CLK_VPLL, X1830_CLK_EPLL }, >>>> + .mux = { CGU_REG_LPCDR, 30, 2 }, >>>> + .div = { CGU_REG_LPCDR, 0, 1, 8, 28, 27, 26 }, >>>> + .gate = { CGU_REG_CLKGR1, 9 }, >>>> + }, >>>> + >>>> + [X1830_CLK_MSCMUX] = { >>>> + "msc_mux", CGU_CLK_MUX, >>>> + .parents = { X1830_CLK_SCLKA, X1830_CLK_MPLL, >>>> + X1830_CLK_VPLL, X1830_CLK_EPLL }, >>>> + .mux = { CGU_REG_MSC0CDR, 30, 2 }, >>>> + }, >>>> + >>>> + [X1830_CLK_MSC0] = { >>>> + "msc0", CGU_CLK_DIV | CGU_CLK_GATE, >>>> + .parents = { X1830_CLK_MSCMUX, -1, -1, -1 }, >>>> + .div = { CGU_REG_MSC0CDR, 0, 2, 8, 29, 28, 27 }, >>>> + .gate = { CGU_REG_CLKGR0, 4 }, >>>> + }, >>>> + >>>> + [X1830_CLK_MSC1] = { >>>> + "msc1", CGU_CLK_DIV | CGU_CLK_GATE, >>>> + .parents = { X1830_CLK_MSCMUX, -1, -1, -1 }, >>>> + .div = { CGU_REG_MSC1CDR, 0, 2, 8, 29, 28, 27 }, >>>> + .gate = { CGU_REG_CLKGR0, 5 }, >>>> + }, >>>> + >>>> + [X1830_CLK_SSIPLL] = { >>>> + "ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV, >>>> + .parents = { X1830_CLK_SCLKA, X1830_CLK_MPLL, >>>> + X1830_CLK_VPLL, X1830_CLK_EPLL }, >>>> + .mux = { CGU_REG_SSICDR, 30, 2 }, >>>> + .div = { CGU_REG_SSICDR, 0, 1, 8, 28, 27, 26 }, >>>> + }, >>>> + >>>> + [X1830_CLK_SSIPLL_DIV2] = { >>>> + "ssi_pll_div2", CGU_CLK_FIXDIV, >>>> + .parents = { X1830_CLK_SSIPLL }, >>>> + .fixdiv = { 2 }, >>>> + }, >>>> + >>>> + [X1830_CLK_SSIMUX] = { >>>> + "ssi_mux", CGU_CLK_MUX, >>>> + .parents = { X1830_CLK_EXCLK, X1830_CLK_SSIPLL_DIV2, -1, >>>> -1 }, >>>> + .mux = { CGU_REG_SSICDR, 29, 1 }, >>>> + }, >>>> + >>>> + /* Gate-only clocks */ >>>> + >>>> + [X1830_CLK_EMC] = { >>>> + "emc", CGU_CLK_GATE, >>>> + .parents = { X1830_CLK_AHB2, -1, -1, -1 }, >>>> + .gate = { CGU_REG_CLKGR0, 0 }, >>>> + }, >>>> + >>>> + [X1830_CLK_EFUSE] = { >>>> + "efuse", CGU_CLK_GATE, >>>> + .parents = { X1830_CLK_AHB2, -1, -1, -1 }, >>>> + .gate = { CGU_REG_CLKGR0, 1 }, >>>> + }, >>>> + >>>> + [X1830_CLK_OTG] = { >>>> + "otg", CGU_CLK_GATE, >>>> + .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, >>>> + .gate = { CGU_REG_CLKGR0, 3 }, >>>> + }, >>>> + >>>> + [X1830_CLK_SSI0] = { >>>> + "ssi0", CGU_CLK_GATE, >>>> + .parents = { X1830_CLK_SSIMUX, -1, -1, -1 }, >>>> + .gate = { CGU_REG_CLKGR0, 6 }, >>>> + }, >>>> + >>>> + [X1830_CLK_SMB0] = { >>>> + "smb0", CGU_CLK_GATE, >>>> + .parents = { X1830_CLK_PCLK, -1, -1, -1 }, >>>> + .gate = { CGU_REG_CLKGR0, 7 }, >>>> + }, >>>> + >>>> + [X1830_CLK_SMB1] = { >>>> + "smb1", CGU_CLK_GATE, >>>> + .parents = { X1830_CLK_PCLK, -1, -1, -1 }, >>>> + .gate = { CGU_REG_CLKGR0, 8 }, >>>> + }, >>>> + >>>> + [X1830_CLK_SMB2] = { >>>> + "smb2", CGU_CLK_GATE, >>>> + .parents = { X1830_CLK_PCLK, -1, -1, -1 }, >>>> + .gate = { CGU_REG_CLKGR0, 9 }, >>>> + }, >>>> + >>>> + [X1830_CLK_UART0] = { >>>> + "uart0", CGU_CLK_GATE, >>>> + .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, >>>> + .gate = { CGU_REG_CLKGR0, 14 }, >>>> + }, >>>> + >>>> + [X1830_CLK_UART1] = { >>>> + "uart1", CGU_CLK_GATE, >>>> + .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, >>>> + .gate = { CGU_REG_CLKGR0, 15 }, >>>> + }, >>>> + >>>> + [X1830_CLK_SSI1] = { >>>> + "ssi1", CGU_CLK_GATE, >>>> + .parents = { X1830_CLK_SSIMUX, -1, -1, -1 }, >>>> + .gate = { CGU_REG_CLKGR0, 19 }, >>>> + }, >>>> + >>>> + [X1830_CLK_SFC] = { >>>> + "sfc", CGU_CLK_GATE, >>>> + .parents = { X1830_CLK_SSIPLL, -1, -1, -1 }, >>>> + .gate = { CGU_REG_CLKGR0, 20 }, >>>> + }, >>>> + >>>> + [X1830_CLK_PDMA] = { >>>> + "pdma", CGU_CLK_GATE, >>>> + .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, >>>> + .gate = { CGU_REG_CLKGR0, 21 }, >>>> + }, >>>> + >>>> + [X1830_CLK_DTRNG] = { >>>> + "dtrng", CGU_CLK_GATE, >>>> + .parents = { X1830_CLK_PCLK, -1, -1, -1 }, >>>> + .gate = { CGU_REG_CLKGR1, 1 }, >>>> + }, >>>> + >>>> + [X1830_CLK_OST] = { >>>> + "ost", CGU_CLK_GATE, >>>> + .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, >>>> + .gate = { CGU_REG_CLKGR1, 11 }, >>>> + }, >>>> +}; >>>> + >>>> +static void __init x1830_cgu_init(struct device_node *np) >>>> +{ >>>> + int retval; >>>> + >>>> + cgu = ingenic_cgu_new(x1830_cgu_clocks, >>>> + ARRAY_SIZE(x1830_cgu_clocks), np); >>>> + if (!cgu) { >>>> + pr_err("%s: failed to initialise CGU\n", __func__); >>>> + return; >>>> + } >>>> + >>>> + retval = ingenic_cgu_register_clocks(cgu); >>>> + if (retval) { >>>> + pr_err("%s: failed to register CGU Clocks\n", __func__); >>>> + return; >>>> + } >>>> + >>>> + ingenic_cgu_register_syscore_ops(cgu); >>>> +} >>>> +CLK_OF_DECLARE_DRIVER(x1830_cgu, "ingenic,x1830-cgu", >>>> x1830_cgu_init); >>>> -- >>>> 2.7.4 >>>> >>> >> > ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v6 5/6] dt-bindings: clock: Add and reorder ABI for X1000. 2020-03-22 8:20 Add support for the X1830 and fix bugs for X1000 v6 周琰杰 (Zhou Yanjie) ` (4 preceding siblings ...) 2020-03-22 8:21 ` [PATCH v6 4/6] clk: Ingenic: Add CGU driver for X1830 周琰杰 (Zhou Yanjie) @ 2020-03-22 8:21 ` 周琰杰 (Zhou Yanjie) 2020-03-22 8:21 ` [PATCH v6 6/6] clk: X1000: Add FIXDIV for SSI clock of X1000 周琰杰 (Zhou Yanjie) 6 siblings, 0 replies; 12+ messages in thread From: 周琰杰 (Zhou Yanjie) @ 2020-03-22 8:21 UTC (permalink / raw) To: linux-clk Cc: linux-kernel, devicetree, sboyd, mturquette, robh+dt, mark.rutland, paul, dongsheng.qiu, yanfei.li, sernia.zhou, zhenwenjin 1.The SSI clock of X1000 not like JZ4770 and JZ4780, they are not directly derived from the output of SSIPLL, but from the clock obtained by dividing the frequency by 2. "X1000_CLK_SSIPLL_DIV2" is added for this purpose, it must between "X1000_CLK_SSIPLL" and "X1000_CLK_SSIMUX", otherwise an error will occurs when initializing the clock. These ABIs are only used for X1000, and I'm sure that no other devicetree out there is using these ABIs, so we should be able to reorder them. 2.Clocks of LCD, OTG, EMC, EFUSE, OST are also added. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Acked-by: Rob Herring <robh@kernel.org> --- Notes: v5: New patch. include/dt-bindings/clock/x1000-cgu.h | 62 +++++++++++++++++++---------------- 1 file changed, 34 insertions(+), 28 deletions(-) diff --git a/include/dt-bindings/clock/x1000-cgu.h b/include/dt-bindings/clock/x1000-cgu.h index bbaebaf..ef6ff63 100644 --- a/include/dt-bindings/clock/x1000-cgu.h +++ b/include/dt-bindings/clock/x1000-cgu.h @@ -12,33 +12,39 @@ #ifndef __DT_BINDINGS_CLOCK_X1000_CGU_H__ #define __DT_BINDINGS_CLOCK_X1000_CGU_H__ -#define X1000_CLK_EXCLK 0 -#define X1000_CLK_RTCLK 1 -#define X1000_CLK_APLL 2 -#define X1000_CLK_MPLL 3 -#define X1000_CLK_SCLKA 4 -#define X1000_CLK_CPUMUX 5 -#define X1000_CLK_CPU 6 -#define X1000_CLK_L2CACHE 7 -#define X1000_CLK_AHB0 8 -#define X1000_CLK_AHB2PMUX 9 -#define X1000_CLK_AHB2 10 -#define X1000_CLK_PCLK 11 -#define X1000_CLK_DDR 12 -#define X1000_CLK_MAC 13 -#define X1000_CLK_MSCMUX 14 -#define X1000_CLK_MSC0 15 -#define X1000_CLK_MSC1 16 -#define X1000_CLK_SSIPLL 17 -#define X1000_CLK_SSIMUX 18 -#define X1000_CLK_SFC 19 -#define X1000_CLK_I2C0 20 -#define X1000_CLK_I2C1 21 -#define X1000_CLK_I2C2 22 -#define X1000_CLK_UART0 23 -#define X1000_CLK_UART1 24 -#define X1000_CLK_UART2 25 -#define X1000_CLK_SSI 26 -#define X1000_CLK_PDMA 27 +#define X1000_CLK_EXCLK 0 +#define X1000_CLK_RTCLK 1 +#define X1000_CLK_APLL 2 +#define X1000_CLK_MPLL 3 +#define X1000_CLK_SCLKA 4 +#define X1000_CLK_CPUMUX 5 +#define X1000_CLK_CPU 6 +#define X1000_CLK_L2CACHE 7 +#define X1000_CLK_AHB0 8 +#define X1000_CLK_AHB2PMUX 9 +#define X1000_CLK_AHB2 10 +#define X1000_CLK_PCLK 11 +#define X1000_CLK_DDR 12 +#define X1000_CLK_MAC 13 +#define X1000_CLK_LCD 14 +#define X1000_CLK_MSCMUX 15 +#define X1000_CLK_MSC0 16 +#define X1000_CLK_MSC1 17 +#define X1000_CLK_OTG 18 +#define X1000_CLK_SSIPLL 19 +#define X1000_CLK_SSIPLL_DIV2 20 +#define X1000_CLK_SSIMUX 21 +#define X1000_CLK_EMC 22 +#define X1000_CLK_EFUSE 23 +#define X1000_CLK_SFC 24 +#define X1000_CLK_I2C0 25 +#define X1000_CLK_I2C1 26 +#define X1000_CLK_I2C2 27 +#define X1000_CLK_UART0 28 +#define X1000_CLK_UART1 29 +#define X1000_CLK_UART2 30 +#define X1000_CLK_SSI 31 +#define X1000_CLK_OST 32 +#define X1000_CLK_PDMA 33 #endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */ -- 2.7.4 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v6 6/6] clk: X1000: Add FIXDIV for SSI clock of X1000. 2020-03-22 8:20 Add support for the X1830 and fix bugs for X1000 v6 周琰杰 (Zhou Yanjie) ` (5 preceding siblings ...) 2020-03-22 8:21 ` [PATCH v6 5/6] dt-bindings: clock: Add and reorder ABI for X1000 周琰杰 (Zhou Yanjie) @ 2020-03-22 8:21 ` 周琰杰 (Zhou Yanjie) 2020-03-22 12:43 ` Zhou Yanjie 6 siblings, 1 reply; 12+ messages in thread From: 周琰杰 (Zhou Yanjie) @ 2020-03-22 8:21 UTC (permalink / raw) To: linux-clk Cc: linux-kernel, devicetree, sboyd, mturquette, robh+dt, mark.rutland, paul, dongsheng.qiu, yanfei.li, sernia.zhou, zhenwenjin 1.The SSI clock of X1000 not like JZ4770 and JZ4780, they are not directly derived from the output of SSIPLL, but from the clock obtained by dividing the frequency by 2. "X1000_CLK_SSIPLL_DIV2" is added for this purpose, and ensure that it initialized before "X1000_CLK_SSIMUX" when initializing the clocks. 2.Clocks of LCD, OTG, EMC, EFUSE, OST, and gates of CPU, PCLK are also added. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> --- Notes: v5: New patch. V5->v6: Add missing part of X1000's CGU. drivers/clk/ingenic/x1000-cgu.c | 56 ++++++++++++++++++++++++++++++++++++----- 1 file changed, 50 insertions(+), 6 deletions(-) diff --git a/drivers/clk/ingenic/x1000-cgu.c b/drivers/clk/ingenic/x1000-cgu.c index 6f0ec9d..7e3ef0d 100644 --- a/drivers/clk/ingenic/x1000-cgu.c +++ b/drivers/clk/ingenic/x1000-cgu.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * X1000 SoC CGU driver - * Copyright (c) 2019 Zhou Yanjie <zhouyanjie@zoho.com> + * Copyright (c) 2019 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> */ #include <linux/clk-provider.h> @@ -18,6 +18,7 @@ #define CGU_REG_CLKGR 0x20 #define CGU_REG_OPCR 0x24 #define CGU_REG_DDRCDR 0x2c +#define CGU_REG_USBCDR 0x50 #define CGU_REG_MACCDR 0x54 #define CGU_REG_I2SCDR 0x60 #define CGU_REG_LPCDR 0x64 @@ -114,9 +115,10 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { }, [X1000_CLK_CPU] = { - "cpu", CGU_CLK_DIV, + "cpu", CGU_CLK_DIV | CGU_CLK_GATE, .parents = { X1000_CLK_CPUMUX, -1, -1, -1 }, .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 }, + .gate = { CGU_REG_CLKGR, 30 }, }, [X1000_CLK_L2CACHE] = { @@ -145,9 +147,10 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { }, [X1000_CLK_PCLK] = { - "pclk", CGU_CLK_DIV, + "pclk", CGU_CLK_DIV | CGU_CLK_GATE, .parents = { X1000_CLK_AHB2PMUX, -1, -1, -1 }, .div = { CGU_REG_CPCCR, 16, 1, 4, 20, -1, -1 }, + .gate = { CGU_REG_CLKGR, 28 }, }, [X1000_CLK_DDR] = { @@ -160,12 +163,20 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { [X1000_CLK_MAC] = { "mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, - .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL}, + .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL }, .mux = { CGU_REG_MACCDR, 31, 1 }, .div = { CGU_REG_MACCDR, 0, 1, 8, 29, 28, 27 }, .gate = { CGU_REG_CLKGR, 25 }, }, + [X1000_CLK_LCD] = { + "lcd", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL }, + .mux = { CGU_REG_LPCDR, 31, 1 }, + .div = { CGU_REG_LPCDR, 0, 1, 8, 28, 27, 26 }, + .gate = { CGU_REG_CLKGR, 23 }, + }, + [X1000_CLK_MSCMUX] = { "msc_mux", CGU_CLK_MUX, .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL}, @@ -186,6 +197,15 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { .gate = { CGU_REG_CLKGR, 5 }, }, + [X1000_CLK_OTG] = { + "otg", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, + .parents = { X1000_CLK_EXCLK, -1, + X1000_CLK_APLL, X1000_CLK_MPLL }, + .mux = { CGU_REG_USBCDR, 30, 2 }, + .div = { CGU_REG_USBCDR, 0, 1, 8, 29, 28, 27 }, + .gate = { CGU_REG_CLKGR, 3 }, + }, + [X1000_CLK_SSIPLL] = { "ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV, .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL, -1, -1 }, @@ -193,14 +213,32 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { .div = { CGU_REG_SSICDR, 0, 1, 8, 29, 28, 27 }, }, + [X1000_CLK_SSIPLL_DIV2] = { + "ssi_pll_div2", CGU_CLK_FIXDIV, + .parents = { X1000_CLK_SSIPLL }, + .fixdiv = { 2 }, + }, + [X1000_CLK_SSIMUX] = { "ssi_mux", CGU_CLK_MUX, - .parents = { X1000_CLK_EXCLK, X1000_CLK_SSIPLL, -1, -1 }, + .parents = { X1000_CLK_EXCLK, X1000_CLK_SSIPLL_DIV2, -1, -1 }, .mux = { CGU_REG_SSICDR, 30, 1 }, }, /* Gate-only clocks */ + [X1000_CLK_EMC] = { + "emc", CGU_CLK_GATE, + .parents = { X1000_CLK_AHB2, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 0 }, + }, + + [X1000_CLK_EFUSE] = { + "efuse", CGU_CLK_GATE, + .parents = { X1000_CLK_AHB2, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 1 }, + }, + [X1000_CLK_SFC] = { "sfc", CGU_CLK_GATE, .parents = { X1000_CLK_SSIPLL, -1, -1, -1 }, @@ -249,6 +287,12 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { .gate = { CGU_REG_CLKGR, 19 }, }, + [X1000_CLK_OST] = { + "ost", CGU_CLK_GATE, + .parents = { X1000_CLK_EXCLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 20 }, + }, + [X1000_CLK_PDMA] = { "pdma", CGU_CLK_GATE, .parents = { X1000_CLK_EXCLK, -1, -1, -1 }, @@ -275,4 +319,4 @@ static void __init x1000_cgu_init(struct device_node *np) ingenic_cgu_register_syscore_ops(cgu); } -CLK_OF_DECLARE(x1000_cgu, "ingenic,x1000-cgu", x1000_cgu_init); +CLK_OF_DECLARE_DRIVER(x1000_cgu, "ingenic,x1000-cgu", x1000_cgu_init); -- 2.7.4 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v6 6/6] clk: X1000: Add FIXDIV for SSI clock of X1000. 2020-03-22 8:21 ` [PATCH v6 6/6] clk: X1000: Add FIXDIV for SSI clock of X1000 周琰杰 (Zhou Yanjie) @ 2020-03-22 12:43 ` Zhou Yanjie 0 siblings, 0 replies; 12+ messages in thread From: Zhou Yanjie @ 2020-03-22 12:43 UTC (permalink / raw) To: Paul Cercueil Cc: linux-clk, linux-kernel, devicetree, sboyd, mturquette, robh+dt, mark.rutland, dongsheng.qiu, yanfei.li, sernia.zhou, zhenwenjin Hi Paul, On 2020年03月22日 20:12, Paul Cercueil wrote: > Hi Zhou, > > Le dim. 22 mars 2020 à 16:21, 周琰杰 (Zhou Yanjie) > <zhouyanjie@wanyeetech.com> a écrit : >> 1.The SSI clock of X1000 not like JZ4770 and JZ4780, they are not >> directly derived from the output of SSIPLL, but from the clock >> obtained by dividing the frequency by 2. "X1000_CLK_SSIPLL_DIV2" >> is added for this purpose, and ensure that it initialized before >> "X1000_CLK_SSIMUX" when initializing the clocks. >> 2.Clocks of LCD, OTG, EMC, EFUSE, OST, and gates of CPU, PCLK >> are also added. >> >> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> >> --- >> >> Notes: >> v5: >> New patch. >> >> V5->v6: >> Add missing part of X1000's CGU. >> >> drivers/clk/ingenic/x1000-cgu.c | 56 >> ++++++++++++++++++++++++++++++++++++----- >> 1 file changed, 50 insertions(+), 6 deletions(-) >> >> diff --git a/drivers/clk/ingenic/x1000-cgu.c >> b/drivers/clk/ingenic/x1000-cgu.c >> index 6f0ec9d..7e3ef0d 100644 >> --- a/drivers/clk/ingenic/x1000-cgu.c >> +++ b/drivers/clk/ingenic/x1000-cgu.c >> @@ -1,7 +1,7 @@ >> // SPDX-License-Identifier: GPL-2.0 >> /* >> * X1000 SoC CGU driver >> - * Copyright (c) 2019 Zhou Yanjie <zhouyanjie@zoho.com> >> + * Copyright (c) 2019 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> >> */ >> >> #include <linux/clk-provider.h> >> @@ -18,6 +18,7 @@ >> #define CGU_REG_CLKGR 0x20 >> #define CGU_REG_OPCR 0x24 >> #define CGU_REG_DDRCDR 0x2c >> +#define CGU_REG_USBCDR 0x50 >> #define CGU_REG_MACCDR 0x54 >> #define CGU_REG_I2SCDR 0x60 >> #define CGU_REG_LPCDR 0x64 >> @@ -114,9 +115,10 @@ static const struct ingenic_cgu_clk_info >> x1000_cgu_clocks[] = { >> }, >> >> [X1000_CLK_CPU] = { >> - "cpu", CGU_CLK_DIV, >> + "cpu", CGU_CLK_DIV | CGU_CLK_GATE, >> .parents = { X1000_CLK_CPUMUX, -1, -1, -1 }, >> .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 }, >> + .gate = { CGU_REG_CLKGR, 30 }, >> }, >> >> [X1000_CLK_L2CACHE] = { >> @@ -145,9 +147,10 @@ static const struct ingenic_cgu_clk_info >> x1000_cgu_clocks[] = { >> }, >> >> [X1000_CLK_PCLK] = { >> - "pclk", CGU_CLK_DIV, >> + "pclk", CGU_CLK_DIV | CGU_CLK_GATE, >> .parents = { X1000_CLK_AHB2PMUX, -1, -1, -1 }, >> .div = { CGU_REG_CPCCR, 16, 1, 4, 20, -1, -1 }, >> + .gate = { CGU_REG_CLKGR, 28 }, >> }, >> >> [X1000_CLK_DDR] = { >> @@ -160,12 +163,20 @@ static const struct ingenic_cgu_clk_info >> x1000_cgu_clocks[] = { >> >> [X1000_CLK_MAC] = { >> "mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, >> - .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL}, >> + .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL }, >> .mux = { CGU_REG_MACCDR, 31, 1 }, >> .div = { CGU_REG_MACCDR, 0, 1, 8, 29, 28, 27 }, >> .gate = { CGU_REG_CLKGR, 25 }, >> }, >> >> + [X1000_CLK_LCD] = { >> + "lcd", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, >> + .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL }, >> + .mux = { CGU_REG_LPCDR, 31, 1 }, >> + .div = { CGU_REG_LPCDR, 0, 1, 8, 28, 27, 26 }, >> + .gate = { CGU_REG_CLKGR, 23 }, >> + }, >> + >> [X1000_CLK_MSCMUX] = { >> "msc_mux", CGU_CLK_MUX, >> .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL}, >> @@ -186,6 +197,15 @@ static const struct ingenic_cgu_clk_info >> x1000_cgu_clocks[] = { >> .gate = { CGU_REG_CLKGR, 5 }, >> }, >> >> + [X1000_CLK_OTG] = { >> + "otg", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, >> + .parents = { X1000_CLK_EXCLK, -1, >> + X1000_CLK_APLL, X1000_CLK_MPLL }, >> + .mux = { CGU_REG_USBCDR, 30, 2 }, >> + .div = { CGU_REG_USBCDR, 0, 1, 8, 29, 28, 27 }, >> + .gate = { CGU_REG_CLKGR, 3 }, >> + }, >> + >> [X1000_CLK_SSIPLL] = { >> "ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV, >> .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL, -1, -1 }, >> @@ -193,14 +213,32 @@ static const struct ingenic_cgu_clk_info >> x1000_cgu_clocks[] = { >> .div = { CGU_REG_SSICDR, 0, 1, 8, 29, 28, 27 }, >> }, >> >> + [X1000_CLK_SSIPLL_DIV2] = { >> + "ssi_pll_div2", CGU_CLK_FIXDIV, >> + .parents = { X1000_CLK_SSIPLL }, >> + .fixdiv = { 2 }, >> + }, >> + >> [X1000_CLK_SSIMUX] = { >> "ssi_mux", CGU_CLK_MUX, >> - .parents = { X1000_CLK_EXCLK, X1000_CLK_SSIPLL, -1, -1 }, >> + .parents = { X1000_CLK_EXCLK, X1000_CLK_SSIPLL_DIV2, -1, -1 }, >> .mux = { CGU_REG_SSICDR, 30, 1 }, >> }, >> >> /* Gate-only clocks */ >> >> + [X1000_CLK_EMC] = { >> + "emc", CGU_CLK_GATE, >> + .parents = { X1000_CLK_AHB2, -1, -1, -1 }, >> + .gate = { CGU_REG_CLKGR, 0 }, >> + }, >> + >> + [X1000_CLK_EFUSE] = { >> + "efuse", CGU_CLK_GATE, >> + .parents = { X1000_CLK_AHB2, -1, -1, -1 }, >> + .gate = { CGU_REG_CLKGR, 1 }, >> + }, >> + >> [X1000_CLK_SFC] = { >> "sfc", CGU_CLK_GATE, >> .parents = { X1000_CLK_SSIPLL, -1, -1, -1 }, >> @@ -249,6 +287,12 @@ static const struct ingenic_cgu_clk_info >> x1000_cgu_clocks[] = { >> .gate = { CGU_REG_CLKGR, 19 }, >> }, >> >> + [X1000_CLK_OST] = { >> + "ost", CGU_CLK_GATE, >> + .parents = { X1000_CLK_EXCLK, -1, -1, -1 }, >> + .gate = { CGU_REG_CLKGR, 20 }, >> + }, >> + >> [X1000_CLK_PDMA] = { >> "pdma", CGU_CLK_GATE, >> .parents = { X1000_CLK_EXCLK, -1, -1, -1 }, >> @@ -275,4 +319,4 @@ static void __init x1000_cgu_init(struct >> device_node *np) >> >> ingenic_cgu_register_syscore_ops(cgu); >> } >> -CLK_OF_DECLARE(x1000_cgu, "ingenic,x1000-cgu", x1000_cgu_init); >> +CLK_OF_DECLARE_DRIVER(x1000_cgu, "ingenic,x1000-cgu", x1000_cgu_init); > > This change is not listed in the commit message, so it's not obvious > why it's here. Please explain why it's changed in the commit message. > This should be that when x1000-cgu.c was first submitted the old way was used. In earlier cgu drivers CLK_OF_DECLARE was used here, but other cgu drivers have now been changed to CLK_OF_DECLARE_DRIVER., and this one should also be changed. I will mention this in the commit message in the next version. Thanks and best regards! > Cheers, > -Paul > >> -- >> 2.7.4 >> > ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2020-03-22 13:00 UTC | newest] Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-03-22 8:20 Add support for the X1830 and fix bugs for X1000 v6 周琰杰 (Zhou Yanjie) 2020-03-22 8:20 ` [PATCH v6 0/6] Add support for the X1830 and fix bugs for X1000 周琰杰 (Zhou Yanjie) 2020-03-22 8:20 ` [PATCH v6 1/6] clk: Ingenic: Remove unnecessary spinlock when reading registers 周琰杰 (Zhou Yanjie) 2020-03-22 8:20 ` [PATCH v6 2/6] clk: Ingenic: Adjust cgu code to make it compatible with X1830 周琰杰 (Zhou Yanjie) 2020-03-22 12:25 ` Zhou Yanjie 2020-03-22 8:20 ` [PATCH v6 3/6] dt-bindings: clock: Add X1830 bindings 周琰杰 (Zhou Yanjie) 2020-03-22 8:21 ` [PATCH v6 4/6] clk: Ingenic: Add CGU driver for X1830 周琰杰 (Zhou Yanjie) 2020-03-22 12:30 ` Zhou Yanjie 2020-03-22 12:59 ` Zhou Yanjie 2020-03-22 8:21 ` [PATCH v6 5/6] dt-bindings: clock: Add and reorder ABI for X1000 周琰杰 (Zhou Yanjie) 2020-03-22 8:21 ` [PATCH v6 6/6] clk: X1000: Add FIXDIV for SSI clock of X1000 周琰杰 (Zhou Yanjie) 2020-03-22 12:43 ` Zhou Yanjie
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