[net-next PATCH v2 0/3] net: mdio-ipq4019: fix wrong default MDC rate

[net-next PATCH v2 0/3] net: mdio-ipq4019: fix wrong default MDC rate

[Christian Marangi]

This was a long journey to arrive and discover this problem.

To not waste too much char, there is a race problem with PHY and driver
probe. This was observed with Aquantia PHY firmware loading.

With some hacks the race problem was workarounded but an interesting
thing was notice. It took more than a minute for the firmware to load
via MDIO.

This was strange as the same operation was done by UBoot in at max 5
second and the same data was loaded.

A similar problem was observed on a mtk board that also had an
Aquantia PHY where the load was very slow. It was notice that the cause
was the MDIO bus running at a very low speed and the firmware
was missing a property (present in mtk sdk) that set the right frequency
to the MDIO bus.

It was fun to find that THE VERY SAME PROBLEM is present on IPQ in a
different form. The MDIO apply internally a division to the feed clock
resulting in the bus running at 390KHz instead of 6.25Mhz.

Searching around the web for some documentation and some include and
analyzing the uboot codeflow resulted in the divider being set wrongly
at /256 instead of /16 as the value was actually never set.
Applying the value restore the original load time for the Aquantia PHY.

This series mainly handle this by adding support for the "clock-frequency"
property.

Changes v2:
- Use DIV_ROUND_UP
- Introduce logic to chose a default value for 802.3 spec 2.5MHz

Christian Marangi (3):
  dt-bindings: net: ipq4019-mdio: document now supported clock-frequency
  net: mdio: ipq4019: add support for clock-frequency property
  arm64: dts: qcom: ipq8074: add clock-frequency to MDIO node

 .../bindings/net/qcom,ipq4019-mdio.yaml       |  15 +++
 arch/arm64/boot/dts/qcom/ipq8074.dtsi         |   2 +
 drivers/net/mdio/mdio-ipq4019.c               | 109 +++++++++++++++++-
 3 files changed, 120 insertions(+), 6 deletions(-)

-- 
2.43.0

[net-next PATCH v2 1/3] dt-bindings: net: ipq4019-mdio: document now supported clock-frequency

[Christian Marangi]

Document support for clock-frequency and add details on why this
property is needed and what values are supported.

From internal documentation, while other values are supported, the
correct function of the MDIO bus is not assured hence add only the
suggested supported values to the property enum.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 .../bindings/net/qcom,ipq4019-mdio.yaml           | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml b/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml
index 3407e909e8a7..0029e197a825 100644
--- a/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml
+++ b/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml
@@ -44,6 +44,21 @@ properties:
     items:
       - const: gcc_mdio_ahb_clk
 
+  clock-frequency:
+    description:
+      The MDIO bus clock that must be output by the MDIO bus hardware, if
+      absent, the default hardware values are used.
+
+      MDC rate is feed by an external clock (fixed 100MHz) and is divider
+      internally. The default divider is /256 resulting in the default rate
+      applied of 390KHz.
+
+      To follow 802.3 standard that instruct up to 2.5MHz by default, if
+      this property is not declared and the divider is set to /256, by
+      default 1.5625Mhz is select.
+    enum: [ 390625, 781250, 1562500, 3125000, 6250000, 12500000 ]
+    default: 1562500
+
 required:
   - compatible
   - reg
-- 
2.43.0

[net-next PATCH v2 2/3] net: mdio: ipq4019: add support for clock-frequency property

[Christian Marangi]

The IPQ4019 MDIO internally divide the clock feed by AHB based on the
MDIO_MODE reg. On reset or power up, the default value for the
divider is 0xff that reflect the divider set to /256.

This makes the MDC run at a very low rate, that is, considering AHB is
always fixed to 100Mhz, a value of 390KHz.

This hasn't have been a problem as MDIO wasn't used for time sensitive
operation, it is now that on IPQ807x is usually mounted with PHY that
requires MDIO to load their firmware (example Aquantia PHY).

To handle this problem and permit to set the correct designed MDC
frequency for the SoC add support for the standard "clock-frequency"
property for the MDIO node.

The divider supports value from /1 to /256 and the common value are to
set it to /16 to reflect 6.25Mhz or to /8 on newer platform to reflect
12.5Mhz.

To scan if the requested rate is supported by the divider, loop with
each supported divider and stop when the requested rate match the final
rate with the current divider. An error is returned if the rate doesn't
match any value.

On MDIO reset, the divider is restored to the requested value to prevent
any kind of downclocking caused by the divider reverting to a default
value.

To follow 802.3 spec of 2.5MHz of default value, if divider is set at
/256 and "clock-frequency" is not set in DT, assume nobody set the
divider and try to find the closest MDC rate to 2.5MHz. (in the case of
AHB set to 100MHz, it's 1.5625MHz)

While at is also document other bits of the MDIO_MODE reg to have a
clear idea of what is actually applied there.

Documentation of some BITs is skipped as they are marked as reserved and
their usage is not clear (RES 11:9 GENPHY 16:13 RES1 19:17)

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 drivers/net/mdio/mdio-ipq4019.c | 109 ++++++++++++++++++++++++++++++--
 1 file changed, 103 insertions(+), 6 deletions(-)

diff --git a/drivers/net/mdio/mdio-ipq4019.c b/drivers/net/mdio/mdio-ipq4019.c
index abd8b508ec16..61638f25c184 100644
--- a/drivers/net/mdio/mdio-ipq4019.c
+++ b/drivers/net/mdio/mdio-ipq4019.c
@@ -14,6 +14,20 @@
 #include <linux/clk.h>
 
 #define MDIO_MODE_REG				0x40
+#define   MDIO_MODE_MDC_MODE			BIT(12)
+/* 0 = Clause 22, 1 = Clause 45 */
+#define   MDIO_MODE_C45				BIT(8)
+#define   MDIO_MODE_DIV_MASK			GENMASK(7, 0)
+#define     MDIO_MODE_DIV(x)			FIELD_PREP(MDIO_MODE_DIV_MASK, (x) - 1)
+#define     MDIO_MODE_DIV_1			0x0
+#define     MDIO_MODE_DIV_2			0x1
+#define     MDIO_MODE_DIV_4			0x3
+#define     MDIO_MODE_DIV_8			0x7
+#define     MDIO_MODE_DIV_16			0xf
+#define     MDIO_MODE_DIV_32			0x1f
+#define     MDIO_MODE_DIV_64			0x3f
+#define     MDIO_MODE_DIV_128			0x7f
+#define     MDIO_MODE_DIV_256			0xff
 #define MDIO_ADDR_REG				0x44
 #define MDIO_DATA_WRITE_REG			0x48
 #define MDIO_DATA_READ_REG			0x4c
@@ -26,9 +40,6 @@
 #define MDIO_CMD_ACCESS_CODE_C45_WRITE	1
 #define MDIO_CMD_ACCESS_CODE_C45_READ	2
 
-/* 0 = Clause 22, 1 = Clause 45 */
-#define MDIO_MODE_C45				BIT(8)
-
 #define IPQ4019_MDIO_TIMEOUT	10000
 #define IPQ4019_MDIO_SLEEP		10
 
@@ -41,6 +52,7 @@ struct ipq4019_mdio_data {
 	void __iomem	*membase;
 	void __iomem *eth_ldo_rdy;
 	struct clk *mdio_clk;
+	unsigned int mdc_rate;
 };
 
 static int ipq4019_mdio_wait_busy(struct mii_bus *bus)
@@ -203,6 +215,38 @@ static int ipq4019_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum,
 	return 0;
 }
 
+static int ipq4019_mdio_set_div(struct ipq4019_mdio_data *priv)
+{
+	unsigned long ahb_rate;
+	int div;
+	u32 val;
+
+	/* If we don't have a clock for AHB use the fixed value */
+	ahb_rate = IPQ_MDIO_CLK_RATE;
+	if (priv->mdio_clk)
+		ahb_rate = clk_get_rate(priv->mdio_clk);
+
+	/* MDC rate is ahb_rate/(MDIO_MODE_DIV + 1)
+	 * While supported, internal documentation doesn't
+	 * assure correct functionality of the MDIO bus
+	 * with divider of 1, 2 or 4.
+	 */
+	for (div = 8; div <= 256; div *= 2) {
+		/* The requested rate is supported by the div */
+		if (priv->mdc_rate == DIV_ROUND_UP(ahb_rate, div)) {
+			val = readl(priv->membase + MDIO_MODE_REG);
+			val &= ~MDIO_MODE_DIV_MASK;
+			val |= MDIO_MODE_DIV(div);
+			writel(val, priv->membase + MDIO_MODE_REG);
+
+			return 0;
+		}
+	}
+
+	/* The requested rate is not supported */
+	return -EINVAL;
+}
+
 static int ipq_mdio_reset(struct mii_bus *bus)
 {
 	struct ipq4019_mdio_data *priv = bus->priv;
@@ -225,10 +269,58 @@ static int ipq_mdio_reset(struct mii_bus *bus)
 		return ret;
 
 	ret = clk_prepare_enable(priv->mdio_clk);
-	if (ret == 0)
-		mdelay(10);
+	if (ret)
+		return ret;
 
-	return ret;
+	mdelay(10);
+
+	/* Restore MDC rate */
+	return ipq4019_mdio_set_div(priv);
+}
+
+static void ipq4019_mdio_select_mdc_rate(struct platform_device *pdev,
+					 struct ipq4019_mdio_data *priv)
+{
+	unsigned long ahb_rate;
+	int div;
+	u32 val;
+
+	/* MDC rate defined in DT, we don't have to decide a default value */
+	if (!of_property_read_u32(pdev->dev.of_node, "clock-frequency",
+				  &priv->mdc_rate))
+		return;
+
+	/* If we don't have a clock for AHB use the fixed value */
+	ahb_rate = IPQ_MDIO_CLK_RATE;
+	if (priv->mdio_clk)
+		ahb_rate = clk_get_rate(priv->mdio_clk);
+
+	/* Check what is the current div set */
+	val = readl(priv->membase + MDIO_MODE_REG);
+	div = FIELD_GET(MDIO_MODE_DIV_MASK, val);
+
+	/* div is not set to the default value of /256
+	 * Probably someone changed that (bootloader, other drivers)
+	 * Keep this and doesn't overwrite it.
+	 */
+	if (div != MDIO_MODE_DIV_256) {
+		priv->mdc_rate = DIV_ROUND_UP(ahb_rate, div + 1);
+		return;
+	}
+
+	/* If div is /256 assume nobody have set this value and
+	 * try to find one MDC rate that is close the 802.3 spec of
+	 * 2.5MHz
+	 */
+	for (div = 256; div >= 8; div /= 2) {
+		/* Stop as soon as we found a divider that
+		 * reached the closest value to 2.5MHz
+		 */
+		if (DIV_ROUND_UP(ahb_rate, div) > 2500000)
+			break;
+
+		priv->mdc_rate = DIV_ROUND_UP(ahb_rate, div);
+	}
 }
 
 static int ipq4019_mdio_probe(struct platform_device *pdev)
@@ -252,6 +344,11 @@ static int ipq4019_mdio_probe(struct platform_device *pdev)
 	if (IS_ERR(priv->mdio_clk))
 		return PTR_ERR(priv->mdio_clk);
 
+	ipq4019_mdio_select_mdc_rate(pdev, priv);
+	ret = ipq4019_mdio_set_div(priv);
+	if (ret)
+		return ret;
+
 	/* The platform resource is provided on the chipset IPQ5018 */
 	/* This resource is optional */
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-- 
2.43.0

[net-next PATCH v2 3/3] arm64: dts: qcom: ipq8074: add clock-frequency to MDIO node

[Christian Marangi]

Add clock-frequency to MDIO node to set the MDC rate to 6.25Mhz instead
of using the default value of 390KHz from MDIO default divider.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 2f275c84e566..08ddfeece043 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -264,6 +264,8 @@ mdio: mdio@90000 {
 			clocks = <&gcc GCC_MDIO_AHB_CLK>;
 			clock-names = "gcc_mdio_ahb_clk";
 
+			clock-frequency = <6250000>;
+
 			status = "disabled";
 		};
 
-- 
2.43.0

Re: [net-next PATCH v2 1/3] dt-bindings: net: ipq4019-mdio: document now supported clock-frequency

[Andrew Lunn]

On Tue, Jan 30, 2024 at 01:35:20AM +0100, Christian Marangi wrote:
> Document support for clock-frequency and add details on why this
> property is needed and what values are supported.
> 
> >From internal documentation, while other values are supported, the
> correct function of the MDIO bus is not assured hence add only the
> suggested supported values to the property enum.
> 
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

Re: [net-next PATCH v2 2/3] net: mdio: ipq4019: add support for clock-frequency property

[Andrew Lunn]

On Tue, Jan 30, 2024 at 01:35:21AM +0100, Christian Marangi wrote:
> The IPQ4019 MDIO internally divide the clock feed by AHB based on the
> MDIO_MODE reg. On reset or power up, the default value for the
> divider is 0xff that reflect the divider set to /256.
> 
> This makes the MDC run at a very low rate, that is, considering AHB is
> always fixed to 100Mhz, a value of 390KHz.
> 
> This hasn't have been a problem as MDIO wasn't used for time sensitive
> operation, it is now that on IPQ807x is usually mounted with PHY that
> requires MDIO to load their firmware (example Aquantia PHY).
> 
> To handle this problem and permit to set the correct designed MDC
> frequency for the SoC add support for the standard "clock-frequency"
> property for the MDIO node.
> 
> The divider supports value from /1 to /256 and the common value are to
> set it to /16 to reflect 6.25Mhz or to /8 on newer platform to reflect
> 12.5Mhz.
> 
> To scan if the requested rate is supported by the divider, loop with
> each supported divider and stop when the requested rate match the final
> rate with the current divider. An error is returned if the rate doesn't
> match any value.
> 
> On MDIO reset, the divider is restored to the requested value to prevent
> any kind of downclocking caused by the divider reverting to a default
> value.
> 
> To follow 802.3 spec of 2.5MHz of default value, if divider is set at
> /256 and "clock-frequency" is not set in DT, assume nobody set the
> divider and try to find the closest MDC rate to 2.5MHz. (in the case of
> AHB set to 100MHz, it's 1.5625MHz)
> 
> While at is also document other bits of the MDIO_MODE reg to have a
> clear idea of what is actually applied there.
> 
> Documentation of some BITs is skipped as they are marked as reserved and
> their usage is not clear (RES 11:9 GENPHY 16:13 RES1 19:17)
> 
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> ---
>  drivers/net/mdio/mdio-ipq4019.c | 109 ++++++++++++++++++++++++++++++--
>  1 file changed, 103 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/net/mdio/mdio-ipq4019.c b/drivers/net/mdio/mdio-ipq4019.c
> index abd8b508ec16..61638f25c184 100644
> --- a/drivers/net/mdio/mdio-ipq4019.c
> +++ b/drivers/net/mdio/mdio-ipq4019.c
> @@ -14,6 +14,20 @@
>  #include <linux/clk.h>
>  
>  #define MDIO_MODE_REG				0x40
> +#define   MDIO_MODE_MDC_MODE			BIT(12)
> +/* 0 = Clause 22, 1 = Clause 45 */
> +#define   MDIO_MODE_C45				BIT(8)
> +#define   MDIO_MODE_DIV_MASK			GENMASK(7, 0)
> +#define     MDIO_MODE_DIV(x)			FIELD_PREP(MDIO_MODE_DIV_MASK, (x) - 1)
> +#define     MDIO_MODE_DIV_1			0x0
> +#define     MDIO_MODE_DIV_2			0x1
> +#define     MDIO_MODE_DIV_4			0x3
> +#define     MDIO_MODE_DIV_8			0x7
> +#define     MDIO_MODE_DIV_16			0xf
> +#define     MDIO_MODE_DIV_32			0x1f
> +#define     MDIO_MODE_DIV_64			0x3f
> +#define     MDIO_MODE_DIV_128			0x7f
> +#define     MDIO_MODE_DIV_256			0xff
>  #define MDIO_ADDR_REG				0x44
>  #define MDIO_DATA_WRITE_REG			0x48
>  #define MDIO_DATA_READ_REG			0x4c
> @@ -26,9 +40,6 @@
>  #define MDIO_CMD_ACCESS_CODE_C45_WRITE	1
>  #define MDIO_CMD_ACCESS_CODE_C45_READ	2
>  
> -/* 0 = Clause 22, 1 = Clause 45 */
> -#define MDIO_MODE_C45				BIT(8)
> -
>  #define IPQ4019_MDIO_TIMEOUT	10000
>  #define IPQ4019_MDIO_SLEEP		10
>  
> @@ -41,6 +52,7 @@ struct ipq4019_mdio_data {
>  	void __iomem	*membase;
>  	void __iomem *eth_ldo_rdy;
>  	struct clk *mdio_clk;
> +	unsigned int mdc_rate;
>  };
>  
>  static int ipq4019_mdio_wait_busy(struct mii_bus *bus)
> @@ -203,6 +215,38 @@ static int ipq4019_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum,
>  	return 0;
>  }
>  
> +static int ipq4019_mdio_set_div(struct ipq4019_mdio_data *priv)
> +{
> +	unsigned long ahb_rate;
> +	int div;
> +	u32 val;
> +
> +	/* If we don't have a clock for AHB use the fixed value */
> +	ahb_rate = IPQ_MDIO_CLK_RATE;
> +	if (priv->mdio_clk)
> +		ahb_rate = clk_get_rate(priv->mdio_clk);
> +
> +	/* MDC rate is ahb_rate/(MDIO_MODE_DIV + 1)
> +	 * While supported, internal documentation doesn't
> +	 * assure correct functionality of the MDIO bus
> +	 * with divider of 1, 2 or 4.
> +	 */
> +	for (div = 8; div <= 256; div *= 2) {
> +		/* The requested rate is supported by the div */
> +		if (priv->mdc_rate == DIV_ROUND_UP(ahb_rate, div)) {
> +			val = readl(priv->membase + MDIO_MODE_REG);
> +			val &= ~MDIO_MODE_DIV_MASK;
> +			val |= MDIO_MODE_DIV(div);
> +			writel(val, priv->membase + MDIO_MODE_REG);
> +
> +			return 0;
> +		}
> +	}
> +
> +	/* The requested rate is not supported */
> +	return -EINVAL;
> +}
> +
>  static int ipq_mdio_reset(struct mii_bus *bus)
>  {
>  	struct ipq4019_mdio_data *priv = bus->priv;
> @@ -225,10 +269,58 @@ static int ipq_mdio_reset(struct mii_bus *bus)
>  		return ret;
>  
>  	ret = clk_prepare_enable(priv->mdio_clk);
> -	if (ret == 0)
> -		mdelay(10);
> +	if (ret)
> +		return ret;
>  
> -	return ret;
> +	mdelay(10);
> +
> +	/* Restore MDC rate */
> +	return ipq4019_mdio_set_div(priv);
> +}
> +
> +static void ipq4019_mdio_select_mdc_rate(struct platform_device *pdev,
> +					 struct ipq4019_mdio_data *priv)
> +{
> +	unsigned long ahb_rate;
> +	int div;
> +	u32 val;
> +
> +	/* MDC rate defined in DT, we don't have to decide a default value */
> +	if (!of_property_read_u32(pdev->dev.of_node, "clock-frequency",
> +				  &priv->mdc_rate))
> +		return;
> +
> +	/* If we don't have a clock for AHB use the fixed value */
> +	ahb_rate = IPQ_MDIO_CLK_RATE;
> +	if (priv->mdio_clk)
> +		ahb_rate = clk_get_rate(priv->mdio_clk);
> +
> +	/* Check what is the current div set */
> +	val = readl(priv->membase + MDIO_MODE_REG);
> +	div = FIELD_GET(MDIO_MODE_DIV_MASK, val);
> +
> +	/* div is not set to the default value of /256
> +	 * Probably someone changed that (bootloader, other drivers)
> +	 * Keep this and doesn't overwrite it.

doesn't -> don't 

Otherwise please add my Reviewed-by on the next version.

	Andrew

Re: [net-next PATCH v2 3/3] arm64: dts: qcom: ipq8074: add clock-frequency to MDIO node

[Andrew Lunn]

On Tue, Jan 30, 2024 at 01:35:22AM +0100, Christian Marangi wrote:
> Add clock-frequency to MDIO node to set the MDC rate to 6.25Mhz instead
> of using the default value of 390KHz from MDIO default divider.
> 
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> ---
>  arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> index 2f275c84e566..08ddfeece043 100644
> --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> @@ -264,6 +264,8 @@ mdio: mdio@90000 {
>  			clocks = <&gcc GCC_MDIO_AHB_CLK>;
>  			clock-names = "gcc_mdio_ahb_clk";
>  
> +			clock-frequency = <6250000>;
> +
>  			status = "disabled";

If we merge this via netdev, is a merge conflict likely? Any other
changes expected in this area, given the changes which might happen to
GCC soon, etc?

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

Re: [net-next PATCH v2 3/3] arm64: dts: qcom: ipq8074: add clock-frequency to MDIO node

[Christian Marangi]

On Tue, Jan 30, 2024 at 01:55:28AM +0100, Andrew Lunn wrote:
> On Tue, Jan 30, 2024 at 01:35:22AM +0100, Christian Marangi wrote:
> > Add clock-frequency to MDIO node to set the MDC rate to 6.25Mhz instead
> > of using the default value of 390KHz from MDIO default divider.
> > 
> > Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> > ---
> >  arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> > index 2f275c84e566..08ddfeece043 100644
> > --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> > @@ -264,6 +264,8 @@ mdio: mdio@90000 {
> >  			clocks = <&gcc GCC_MDIO_AHB_CLK>;
> >  			clock-names = "gcc_mdio_ahb_clk";
> >  
> > +			clock-frequency = <6250000>;
> > +
> >  			status = "disabled";
> 
> If we merge this via netdev, is a merge conflict likely? Any other
> changes expected in this area, given the changes which might happen to
> GCC soon, etc?
> 
> Reviewed-by: Andrew Lunn <andrew@lunn.ch>
>

Honestly I don't expect much to change here in the mdio node.

If it's a problem I can submit in a separate patch in linux-msm.

-- 
	Ansuel

Re: [net-next PATCH v2 3/3] arm64: dts: qcom: ipq8074: add clock-frequency to MDIO node

[Jakub Kicinski]

On Tue, 30 Jan 2024 01:57:36 +0100 Christian Marangi wrote:
> > If we merge this via netdev, is a merge conflict likely? Any other
> > changes expected in this area, given the changes which might happen to
> > GCC soon, etc?
> > 
> > Reviewed-by: Andrew Lunn <andrew@lunn.ch>
> 
> Honestly I don't expect much to change here in the mdio node.
> 
> If it's a problem I can submit in a separate patch in linux-msm.

The arch maintainers usually prefer to take the DTS patches,
so if there isn't anything special here we should probably
default to that.

Re: [net-next PATCH v2 3/3] arm64: dts: qcom: ipq8074: add clock-frequency to MDIO node

[Christian Marangi]

On Tue, Jan 30, 2024 at 05:40:41PM -0800, Jakub Kicinski wrote:
> On Tue, 30 Jan 2024 01:57:36 +0100 Christian Marangi wrote:
> > > If we merge this via netdev, is a merge conflict likely? Any other
> > > changes expected in this area, given the changes which might happen to
> > > GCC soon, etc?
> > > 
> > > Reviewed-by: Andrew Lunn <andrew@lunn.ch>
> > 
> > Honestly I don't expect much to change here in the mdio node.
> > 
> > If it's a problem I can submit in a separate patch in linux-msm.
> 
> The arch maintainers usually prefer to take the DTS patches,
> so if there isn't anything special here we should probably
> default to that.

Thanks for the suggestion I sent v3 with the DTS patch dropped and I
sent that patch separately.

-- 
	Ansuel

Re: [net-next PATCH v2 2/3] net: mdio: ipq4019: add support for clock-frequency property

[Jie Luo]

On 1/30/2024 8:35 AM, Christian Marangi wrote:
> +
> +	/* If div is /256 assume nobody have set this value and
> +	 * try to find one MDC rate that is close the 802.3 spec of
> +	 * 2.5MHz
> +	 */
> +	for (div = 256; div >= 8; div /= 2) {
> +		/* Stop as soon as we found a divider that
> +		 * reached the closest value to 2.5MHz
> +		 */
> +		if (DIV_ROUND_UP(ahb_rate, div) > 2500000)
> +			break;

Hi Christian,
Sorry for the delayed review.

The MDIO hardware block supports higher frequency 6.25M and 12.5M,
Would you remove this 2.5MHZ limitation? On the IPQ platform, we
normally use 6.25MHZ.
> +
> +		priv->mdc_rate = DIV_ROUND_UP(ahb_rate, div);
> +	}
>   }

Re: [net-next PATCH v2 2/3] net: mdio: ipq4019: add support for clock-frequency property

[Andrew Lunn]

On Sun, Feb 04, 2024 at 05:59:10PM +0800, Jie Luo wrote:
> 
> 
> On 1/30/2024 8:35 AM, Christian Marangi wrote:
> > +
> > +	/* If div is /256 assume nobody have set this value and
> > +	 * try to find one MDC rate that is close the 802.3 spec of
> > +	 * 2.5MHz
> > +	 */
> > +	for (div = 256; div >= 8; div /= 2) {
> > +		/* Stop as soon as we found a divider that
> > +		 * reached the closest value to 2.5MHz
> > +		 */
> > +		if (DIV_ROUND_UP(ahb_rate, div) > 2500000)
> > +			break;
> 
> Hi Christian,
> Sorry for the delayed review.
> 
> The MDIO hardware block supports higher frequency 6.25M and 12.5M,
> Would you remove this 2.5MHZ limitation? On the IPQ platform, we
> normally use 6.25MHZ.

802.3 says the clock has a maximum of 2.5MHz. So this code is correct.

It is however O.K. to go faster, but since that breaks the standard,
you need each board to indicate it knows all the devices on the bus do
support higher speeds and its O.K. to break the standard. You indicate
this by using the DT property in its .dts file. For an MDIO bus which
is totally internal, you could however put the DT property in the SoC
.dtsi file.

      Andrew

Re: [net-next PATCH v2 2/3] net: mdio: ipq4019: add support for clock-frequency property

[Jie Luo]

On 2/4/2024 11:22 PM, Andrew Lunn wrote:
> On Sun, Feb 04, 2024 at 05:59:10PM +0800, Jie Luo wrote:
>>
>>
>> On 1/30/2024 8:35 AM, Christian Marangi wrote:
>>> +
>>> +	/* If div is /256 assume nobody have set this value and
>>> +	 * try to find one MDC rate that is close the 802.3 spec of
>>> +	 * 2.5MHz
>>> +	 */
>>> +	for (div = 256; div >= 8; div /= 2) {
>>> +		/* Stop as soon as we found a divider that
>>> +		 * reached the closest value to 2.5MHz
>>> +		 */
>>> +		if (DIV_ROUND_UP(ahb_rate, div) > 2500000)
>>> +			break;
>>
>> Hi Christian,
>> Sorry for the delayed review.
>>
>> The MDIO hardware block supports higher frequency 6.25M and 12.5M,
>> Would you remove this 2.5MHZ limitation? On the IPQ platform, we
>> normally use 6.25MHZ.
> 
> 802.3 says the clock has a maximum of 2.5MHz. So this code is correct.
> 
> It is however O.K. to go faster, but since that breaks the standard,
> you need each board to indicate it knows all the devices on the bus do
> support higher speeds and its O.K. to break the standard. You indicate
> this by using the DT property in its .dts file. For an MDIO bus which
> is totally internal, you could however put the DT property in the SoC
> .dtsi file.
> 
>        Andrew

Understand it, Thanks Andrew.