From: Sowjanya Komatineni <skomatineni@nvidia.com>
To: Dmitry Osipenko <digetx@gmail.com>, <thierry.reding@gmail.com>,
<jonathanh@nvidia.com>, <tglx@linutronix.de>,
<jason@lakedaemon.net>, <marc.zyngier@arm.com>,
<linus.walleij@linaro.org>, <stefan@agner.ch>,
<mark.rutland@arm.com>
Cc: <pdeschrijver@nvidia.com>, <pgaikwad@nvidia.com>,
<sboyd@kernel.org>, <linux-clk@vger.kernel.org>,
<linux-gpio@vger.kernel.org>, <jckuo@nvidia.com>,
<josephl@nvidia.com>, <talho@nvidia.com>,
<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<mperttunen@nvidia.com>, <spatra@nvidia.com>,
<robh+dt@kernel.org>, <devicetree@vger.kernel.org>
Subject: Re: [PATCH v7 07/20] clk: tegra: clk-periph: Add save and restore support
Date: Wed, 31 Jul 2019 16:09:53 -0700 [thread overview]
Message-ID: <67cf6c13-688d-0305-61e2-c63c8e8b4729@nvidia.com> (raw)
In-Reply-To: <e796e26e-830c-b1be-e368-c7ff177a61dd@gmail.com>
On 7/31/19 3:44 AM, Dmitry Osipenko wrote:
> 31.07.2019 12:50, Dmitry Osipenko пишет:
>> 31.07.2019 3:20, Sowjanya Komatineni пишет:
>>> This patch implements save and restore context for peripheral fixed
>>> clock ops, peripheral gate clock ops, sdmmc mux clock ops, and
>>> peripheral clock ops.
>>>
>>> During system suspend, core power goes off and looses the settings
>>> of the Tegra CAR controller registers.
>>>
>>> So during suspend entry clock and reset state of peripherals is saved
>>> and on resume they are restored to have clocks back to same rate and
>>> state as before suspend.
>>>
>>> Acked-by: Thierry Reding <treding@nvidia.com>
>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>> ---
>>> drivers/clk/tegra/clk-periph-fixed.c | 33 ++++++++++++++++++++++++++++++++
>>> drivers/clk/tegra/clk-periph-gate.c | 34 +++++++++++++++++++++++++++++++++
>>> drivers/clk/tegra/clk-periph.c | 37 ++++++++++++++++++++++++++++++++++++
>>> drivers/clk/tegra/clk-sdmmc-mux.c | 28 +++++++++++++++++++++++++++
>>> drivers/clk/tegra/clk.h | 6 ++++++
>>> 5 files changed, 138 insertions(+)
>>>
>>> diff --git a/drivers/clk/tegra/clk-periph-fixed.c b/drivers/clk/tegra/clk-periph-fixed.c
>>> index c088e7a280df..21b24530fa00 100644
>>> --- a/drivers/clk/tegra/clk-periph-fixed.c
>>> +++ b/drivers/clk/tegra/clk-periph-fixed.c
>>> @@ -60,11 +60,44 @@ tegra_clk_periph_fixed_recalc_rate(struct clk_hw *hw,
>>> return (unsigned long)rate;
>>> }
>>>
>>> +static int tegra_clk_periph_fixed_save_context(struct clk_hw *hw)
>>> +{
>>> + struct tegra_clk_periph_fixed *fixed = to_tegra_clk_periph_fixed(hw);
>>> + u32 mask = 1 << (fixed->num % 32);
>>> +
>>> + fixed->enb_ctx = readl_relaxed(fixed->base + fixed->regs->enb_reg) &
>>> + mask;
>>> + fixed->rst_ctx = readl_relaxed(fixed->base + fixed->regs->rst_reg) &
>>> + mask;
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static void tegra_clk_periph_fixed_restore_context(struct clk_hw *hw)
>>> +{
>>> + struct tegra_clk_periph_fixed *fixed = to_tegra_clk_periph_fixed(hw);
>>> + u32 mask = 1 << (fixed->num % 32);
>>> +
>>> + if (fixed->enb_ctx)
>>> + writel_relaxed(mask, fixed->base + fixed->regs->enb_set_reg);
>>> + else
>>> + writel_relaxed(mask, fixed->base + fixed->regs->enb_clr_reg);
>>> +
>>> + udelay(2);
>>> +
>>> + if (!fixed->rst_ctx) {
>>> + udelay(5); /* reset propogation delay */
>>> + writel_relaxed(mask, fixed->base + fixed->regs->rst_reg);
>>> + }
>>> +}
>>> +
>>> static const struct clk_ops tegra_clk_periph_fixed_ops = {
>>> .is_enabled = tegra_clk_periph_fixed_is_enabled,
>>> .enable = tegra_clk_periph_fixed_enable,
>>> .disable = tegra_clk_periph_fixed_disable,
>>> .recalc_rate = tegra_clk_periph_fixed_recalc_rate,
>>> + .save_context = tegra_clk_periph_fixed_save_context,
>>> + .restore_context = tegra_clk_periph_fixed_restore_context,
>>> };
>>>
>>> struct clk *tegra_clk_register_periph_fixed(const char *name,
>>> diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c
>>> index 4b31beefc9fc..6ba5b08e0787 100644
>>> --- a/drivers/clk/tegra/clk-periph-gate.c
>>> +++ b/drivers/clk/tegra/clk-periph-gate.c
>>> @@ -25,6 +25,8 @@ static DEFINE_SPINLOCK(periph_ref_lock);
>>>
>>> #define read_rst(gate) \
>>> readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
>>> +#define write_rst_set(val, gate) \
>>> + writel_relaxed(val, gate->clk_base + (gate->regs->rst_set_reg))
>>> #define write_rst_clr(val, gate) \
>>> writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
>>>
>>> @@ -110,10 +112,42 @@ static void clk_periph_disable(struct clk_hw *hw)
>>> spin_unlock_irqrestore(&periph_ref_lock, flags);
>>> }
>>>
>>> +static int clk_periph_gate_save_context(struct clk_hw *hw)
>>> +{
>>> + struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
>>> +
>>> + gate->clk_state_ctx = read_enb(gate) & periph_clk_to_bit(gate);
>>> + gate->rst_state_ctx = read_rst(gate) & periph_clk_to_bit(gate);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static void clk_periph_gate_restore_context(struct clk_hw *hw)
>>> +{
>>> + struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
>>> +
>>> + if (gate->clk_state_ctx)
>>> + write_enb_set(periph_clk_to_bit(gate), gate);
>>> + else
>>> + write_enb_clr(periph_clk_to_bit(gate), gate);
>>> +
>>> + udelay(5);
>>> +
>>> + if (!(gate->flags & TEGRA_PERIPH_NO_RESET) &&
>>> + !(gate->flags & TEGRA_PERIPH_MANUAL_RESET)) {
>>> + if (gate->rst_state_ctx)
>>> + write_rst_set(periph_clk_to_bit(gate), gate);
>>> + else
>>> + write_rst_clr(periph_clk_to_bit(gate), gate);
>>> + }
>>> +}
>>> +
>>> const struct clk_ops tegra_clk_periph_gate_ops = {
>>> .is_enabled = clk_periph_is_enabled,
>>> .enable = clk_periph_enable,
>>> .disable = clk_periph_disable,
>>> + .save_context = clk_periph_gate_save_context,
>>> + .restore_context = clk_periph_gate_restore_context,
>>> };
>>>
>>> struct clk *tegra_clk_register_periph_gate(const char *name,
>>> diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c
>>> index 58437da25156..06fb62955768 100644
>>> --- a/drivers/clk/tegra/clk-periph.c
>>> +++ b/drivers/clk/tegra/clk-periph.c
>>> @@ -99,6 +99,37 @@ static void clk_periph_disable(struct clk_hw *hw)
>>> gate_ops->disable(gate_hw);
>>> }
>>>
>>> +static int clk_periph_save_context(struct clk_hw *hw)
>>> +{
>>> + struct tegra_clk_periph *periph = to_clk_periph(hw);
>>> + const struct clk_ops *gate_ops = periph->gate_ops;
>>> + struct clk_hw *gate_hw = &periph->gate.hw;
>>> +
>>> + if (!(periph->gate.flags & TEGRA_PERIPH_NO_GATE))
>>> + gate_ops->save_context(gate_hw);
>>> +
>>> + periph->parent_ctx = clk_periph_get_parent(hw);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static void clk_periph_restore_context(struct clk_hw *hw)
>>> +{
>>> + struct tegra_clk_periph *periph = to_clk_periph(hw);
>>> + const struct clk_ops *gate_ops = periph->gate_ops;
>>> + struct clk_hw *gate_hw = &periph->gate.hw;
>>> + const struct clk_ops *div_ops = periph->div_ops;
>>> + struct clk_hw *div_hw = &periph->divider.hw;
>>> +
>>> + clk_periph_set_parent(hw, periph->parent_ctx);
>>> +
>>> + if (!(periph->gate.flags & TEGRA_PERIPH_NO_DIV))
>>> + div_ops->restore_context(div_hw);
>> Could you please point to where the divider's save_context() happens?
>> Because I can't see it.
> Ah, I now see that there is no need to save the dividers context because
> clk itself has enough info that is needed for the context's restoring
> (like I pointed in the review to v6).
>
> Looks like you could also implement a new clk_hw_get_parent_index()
> generic helper to get the index instead of storing it manually.
clk_periph_get_parent basically invokes existing clk_mux_ops
get_parent() which is then saved in tegra_clk_periph.
All existing drivers are using directly get_parent() from clk_mux which
actually gets index from the register read.
To have this more generic w.r.t save/restore context point of view,
probably instead of implementing new get_parent_index helper, I think
its better to implement save_context and restore_context to clk_mux_ops
along with creating parent_index field into clk_mux to cache index
during set_parent.
So we just need to invoke mux_ops save_context and restore_context.
next prev parent reply other threads:[~2019-07-31 23:09 UTC|newest]
Thread overview: 67+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-31 0:20 [PATCH v7 00/20] SC7 entry and exit support for Tegra210 Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 01/20] pinctrl: tegra: Add suspend and resume support Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 02/20] pinctrl: tegra210: Add Tegra210 pinctrl pm ops Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 03/20] clk: tegra: divider: Save and restore divider rate Sowjanya Komatineni
2019-07-31 10:49 ` Dmitry Osipenko
2019-07-31 0:20 ` [PATCH v7 04/20] clk: tegra: pllout: Save and restore pllout context Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 05/20] clk: tegra: pll: Save and restore pll context Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 06/20] clk: tegra: Support for OSC context save and restore Sowjanya Komatineni
2019-07-31 11:11 ` Dmitry Osipenko
2019-07-31 21:04 ` Sowjanya Komatineni
2019-08-01 10:53 ` Dmitry Osipenko
2019-08-01 18:06 ` Sowjanya Komatineni
2019-08-01 18:42 ` Dmitry Osipenko
2019-07-31 0:20 ` [PATCH v7 07/20] clk: tegra: clk-periph: Add save and restore support Sowjanya Komatineni
2019-07-31 9:50 ` Dmitry Osipenko
2019-07-31 10:44 ` Dmitry Osipenko
2019-07-31 23:09 ` Sowjanya Komatineni [this message]
2019-08-01 17:58 ` Sowjanya Komatineni
2019-08-01 19:00 ` Dmitry Osipenko
2019-08-01 19:42 ` Sowjanya Komatineni
2019-08-01 20:17 ` Dmitry Osipenko
2019-08-01 20:31 ` Sowjanya Komatineni
2019-08-01 20:54 ` Dmitry Osipenko
2019-08-01 21:30 ` Sowjanya Komatineni
2019-08-01 23:19 ` Sowjanya Komatineni
2019-08-01 23:49 ` Sowjanya Komatineni
2019-08-02 12:38 ` Dmitry Osipenko
2019-08-02 18:33 ` Sowjanya Komatineni
2019-08-02 20:13 ` Dmitry Osipenko
2019-08-02 20:17 ` Dmitry Osipenko
2019-08-02 20:32 ` Sowjanya Komatineni
2019-08-02 21:15 ` Dmitry Osipenko
2019-08-02 21:18 ` Sowjanya Komatineni
2019-08-02 23:51 ` Sowjanya Komatineni
2019-08-03 10:33 ` Dmitry Osipenko
2019-08-03 17:01 ` Sowjanya Komatineni
2019-08-03 23:44 ` Sowjanya Komatineni
2019-08-04 12:24 ` Dmitry Osipenko
2019-08-04 12:31 ` Dmitry Osipenko
2019-08-02 12:32 ` Dmitry Osipenko
2019-08-02 18:43 ` Sowjanya Komatineni
2019-08-02 20:20 ` Dmitry Osipenko
2019-08-02 20:37 ` Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 08/20] clk: tegra: clk-super: Fix to enable PLLP branches to CPU Sowjanya Komatineni
2019-07-31 10:14 ` Dmitry Osipenko
2019-07-31 0:20 ` [PATCH v7 09/20] clk: tegra: clk-super: Add save and restore support Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 10/20] clk: tegra: clk-dfll: Add suspend and resume support Sowjanya Komatineni
2019-07-31 10:12 ` Dmitry Osipenko
2019-07-31 0:20 ` [PATCH v7 11/20] cpufreq: tegra124: " Sowjanya Komatineni
2019-07-31 10:23 ` Dmitry Osipenko
2019-07-31 11:14 ` Dmitry Osipenko
2019-07-31 21:05 ` Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 12/20] clk: tegra210: Use fence_udelay during PLLU init Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 13/20] clk: tegra210: Add suspend and resume support Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 14/20] soc/tegra: pmc: Allow to support more tegras wake Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 15/20] soc/tegra: pmc: Add pmc wake support for tegra210 Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 16/20] arm64: tegra: Enable wake from deep sleep on RTC alarm Sowjanya Komatineni
2019-07-31 11:04 ` Dmitry Osipenko
2019-07-31 21:08 ` Sowjanya Komatineni
2019-08-01 10:43 ` Dmitry Osipenko
2019-08-01 17:56 ` Sowjanya Komatineni
2019-08-01 18:39 ` Dmitry Osipenko
2019-07-31 0:20 ` [PATCH v7 17/20] soc/tegra: pmc: Configure core power request polarity Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 18/20] soc/tegra: pmc: Configure deep sleep control settings Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 19/20] arm64: dts: tegra210-p2180: Jetson TX1 SC7 timings Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 20/20] arm64: dts: tegra210-p3450: Jetson Nano " Sowjanya Komatineni
2019-07-31 21:10 [PATCH v7 00/20] SC7 entry and exit support for Tegra210 Sowjanya Komatineni
2019-07-31 21:10 ` [PATCH v7 07/20] clk: tegra: clk-periph: Add save and restore support Sowjanya Komatineni
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=67cf6c13-688d-0305-61e2-c63c8e8b4729@nvidia.com \
--to=skomatineni@nvidia.com \
--cc=devicetree@vger.kernel.org \
--cc=digetx@gmail.com \
--cc=jason@lakedaemon.net \
--cc=jckuo@nvidia.com \
--cc=jonathanh@nvidia.com \
--cc=josephl@nvidia.com \
--cc=linus.walleij@linaro.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-gpio@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=marc.zyngier@arm.com \
--cc=mark.rutland@arm.com \
--cc=mperttunen@nvidia.com \
--cc=pdeschrijver@nvidia.com \
--cc=pgaikwad@nvidia.com \
--cc=robh+dt@kernel.org \
--cc=sboyd@kernel.org \
--cc=spatra@nvidia.com \
--cc=stefan@agner.ch \
--cc=talho@nvidia.com \
--cc=tglx@linutronix.de \
--cc=thierry.reding@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).