PATCH: Altivec support for RAID-6

PATCH: Altivec support for RAID-6

[H. Peter Anvin]

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This patch adds Altivec support for RAID-6, if appropriately configured 
on the ppc or ppc64 architectures.  Note that it changes the compile 
flags for ppc64 in order to handle -maltivec correctly; this change was 
vetted on the ppc64 mailing list and OK'd by paulus.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>

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Index: raid6/arch/ppc64/Makefile
===================================================================
RCS file: /home/hpa/kernel/bkcvs/linux-2.5/arch/ppc64/Makefile,v
retrieving revision 1.42
diff -u -r1.42 Makefile
--- raid6/arch/ppc64/Makefile	26 Oct 2004 14:53:34 -0000	1.42
+++ raid6/arch/ppc64/Makefile	18 Nov 2004 06:01:37 -0000
@@ -35,7 +35,11 @@
 CFLAGS		+= -msoft-float -pipe -mminimal-toc -mtraceback=none
 
 ifeq ($(CONFIG_POWER4_ONLY),y)
+ifeq ($(CONFIG_ALTIVEC),y)
+	CFLAGS += $(call cc-option,-mcpu=970)
+else
 	CFLAGS += $(call cc-option,-mcpu=power4)
+endif
 else
 	CFLAGS += $(call cc-option,-mtune=power4)
 endif
Index: raid6/drivers/md/Makefile
===================================================================
RCS file: /home/hpa/kernel/bkcvs/linux-2.5/drivers/md/Makefile,v
retrieving revision 1.23
diff -u -r1.23 Makefile
--- raid6/drivers/md/Makefile	11 Nov 2004 21:49:10 -0000	1.23
+++ raid6/drivers/md/Makefile	18 Nov 2004 06:01:38 -0000
@@ -9,6 +9,8 @@
 raid6-objs	:= raid6main.o raid6algos.o raid6recov.o raid6tables.o \
 		   raid6int1.o raid6int2.o raid6int4.o \
 		   raid6int8.o raid6int16.o raid6int32.o \
+		   raid6altivec1.o raid6altivec2.o raid6altivec4.o \
+		   raid6altivec8.o \
 		   raid6mmx.o raid6sse1.o raid6sse2.o
 hostprogs-y	:= mktables
 
@@ -36,6 +38,10 @@
       cmd_unroll = $(PERL) $(srctree)/$(src)/unroll.pl $(UNROLL) \
                    < $< > $@ || ( rm -f $@ && exit 1 )
 
+ifeq ($(CONFIG_ALTIVEC),y)
+altivec_flags := -maltivec -mabi=altivec
+endif
+
 targets += raid6int1.c
 $(obj)/raid6int1.c:   UNROLL := 1
 $(obj)/raid6int1.c:   $(src)/raid6int.uc $(src)/unroll.pl FORCE
@@ -66,6 +72,30 @@
 $(obj)/raid6int32.c:  $(src)/raid6int.uc $(src)/unroll.pl FORCE
 	$(call if_changed,unroll)
 
+CFLAGS_raid6altivec1.o += $(altivec_flags)
+targets += raid6altivec1.c
+$(obj)/raid6altivec1.c:   UNROLL := 1
+$(obj)/raid6altivec1.c:   $(src)/raid6altivec.uc $(src)/unroll.pl FORCE
+	$(call if_changed,unroll)
+
+CFLAGS_raid6altivec2.o += $(altivec_flags)
+targets += raid6altivec2.c
+$(obj)/raid6altivec2.c:   UNROLL := 2
+$(obj)/raid6altivec2.c:   $(src)/raid6altivec.uc $(src)/unroll.pl FORCE
+	$(call if_changed,unroll)
+
+CFLAGS_raid6altivec4.o += $(altivec_flags)
+targets += raid6altivec4.c
+$(obj)/raid6altivec4.c:   UNROLL := 4
+$(obj)/raid6altivec4.c:   $(src)/raid6altivec.uc $(src)/unroll.pl FORCE
+	$(call if_changed,unroll)
+
+CFLAGS_raid6altivec8.o += $(altivec_flags)
+targets += raid6altivec8.c
+$(obj)/raid6altivec8.c:   UNROLL := 8
+$(obj)/raid6altivec8.c:   $(src)/raid6altivec.uc $(src)/unroll.pl FORCE
+	$(call if_changed,unroll)
+
 quiet_cmd_mktable = TABLE   $@
       cmd_mktable = $(obj)/mktables > $@ || ( rm -f $@ && exit 1 )
 
Index: raid6/drivers/md/raid6algos.c
===================================================================
RCS file: /home/hpa/kernel/bkcvs/linux-2.5/drivers/md/raid6algos.c,v
retrieving revision 1.4
diff -u -r1.4 raid6algos.c
--- raid6/drivers/md/raid6algos.c	23 Jan 2004 16:04:36 -0000	1.4
+++ raid6/drivers/md/raid6algos.c	18 Nov 2004 06:01:38 -0000
@@ -37,6 +37,10 @@
 extern const struct raid6_calls raid6_sse2x1;
 extern const struct raid6_calls raid6_sse2x2;
 extern const struct raid6_calls raid6_sse2x4;
+extern const struct raid6_calls raid6_altivec1;
+extern const struct raid6_calls raid6_altivec2;
+extern const struct raid6_calls raid6_altivec4;
+extern const struct raid6_calls raid6_altivec8;
 
 const struct raid6_calls * const raid6_algos[] = {
 	&raid6_intx1,
@@ -60,6 +64,12 @@
 	&raid6_sse2x2,
 	&raid6_sse2x4,
 #endif
+#ifdef CONFIG_ALTIVEC
+	&raid6_altivec1,
+	&raid6_altivec2,
+	&raid6_altivec4,
+	&raid6_altivec8,
+#endif
 	NULL
 };
 
Index: raid6/drivers/md/raid6altivec.uc
===================================================================
RCS file: raid6/drivers/md/raid6altivec.uc
diff -N raid6/drivers/md/raid6altivec.uc
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ raid6/drivers/md/raid6altivec.uc	18 Nov 2004 06:01:38 -0000
@@ -0,0 +1,122 @@
+/* -*- linux-c -*- ------------------------------------------------------- *
+ *
+ *   Copyright 2002-2004 H. Peter Anvin - All Rights Reserved
+ *
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation, Inc., 53 Temple Place Ste 330,
+ *   Bostom MA 02111-1307, USA; either version 2 of the License, or
+ *   (at your option) any later version; incorporated herein by reference.
+ *
+ * ----------------------------------------------------------------------- */
+
+/*
+ * raid6altivec$#.c
+ *
+ * $#-way unrolled portable integer math RAID-6 instruction set
+ *
+ * This file is postprocessed using unroll.pl
+ *
+ * <benh> hpa: in process,
+ * you can just "steal" the vec unit with enable_kernel_altivec() (but
+ * bracked this with preempt_disable/enable or in a lock)
+ */
+
+#include "raid6.h"
+
+#ifdef CONFIG_ALTIVEC
+
+#include <altivec.h>
+#include <asm/system.h>
+#include <asm/cputable.h>
+
+/*
+ * This is the C data type to use
+ */
+
+typedef vector unsigned char unative_t;
+
+#define NBYTES(x) ((vector unsigned char) {x,x,x,x, x,x,x,x, x,x,x,x, x,x,x,x})
+#define NSIZE	sizeof(unative_t)
+
+/*
+ * The SHLBYTE() operation shifts each byte left by 1, *not*
+ * rolling over into the next byte
+ */
+static inline __attribute_const__ unative_t SHLBYTE(unative_t v)
+{
+	return vec_add(v,v);
+}
+
+/*
+ * The MASK() operation returns 0xFF in any byte for which the high
+ * bit is 1, 0x00 for any byte for which the high bit is 0.
+ */
+static inline __attribute_const__ unative_t MASK(unative_t v)
+{
+	unative_t zv = NBYTES(0);
+
+	/* vec_cmpgt returns a vector bool char; thus the need for the cast */
+	return (unative_t)vec_cmpgt(zv, v);
+}
+
+
+/* This is noinline to make damned sure that gcc doesn't move any of the
+   Altivec code around the enable/disable code */
+static void noinline
+raid6_altivec$#_gen_syndrome_real(int disks, size_t bytes, void **ptrs)
+{
+	u8 **dptr = (u8 **)ptrs;
+	u8 *p, *q;
+	int d, z, z0;
+
+	unative_t wd$$, wq$$, wp$$, w1$$, w2$$;
+	unative_t x1d = NBYTES(0x1d);
+
+	z0 = disks - 3;		/* Highest data disk */
+	p = dptr[z0+1];		/* XOR parity */
+	q = dptr[z0+2];		/* RS syndrome */
+
+	for ( d = 0 ; d < bytes ; d += NSIZE*$# ) {
+		wq$$ = wp$$ = *(unative_t *)&dptr[z0][d+$$*NSIZE];
+		for ( z = z0-1 ; z >= 0 ; z-- ) {
+			wd$$ = *(unative_t *)&dptr[z][d+$$*NSIZE];
+			wp$$ = vec_xor(wp$$, wd$$);
+			w2$$ = MASK(wq$$);
+			w1$$ = SHLBYTE(wq$$);
+			w2$$ = vec_and(w2$$, x1d);
+			w1$$ = vec_xor(w1$$, w2$$);
+			wq$$ = vec_xor(w1$$, wd$$);
+		}
+		*(unative_t *)&p[d+NSIZE*$$] = wp$$;
+		*(unative_t *)&q[d+NSIZE*$$] = wq$$;
+	}
+}
+
+static void raid6_altivec$#_gen_syndrome(int disks, size_t bytes, void **ptrs)
+{
+	preempt_disable();
+	enable_kernel_altivec();
+
+	raid6_altivec$#_gen_syndrome_real(disks, bytes, ptrs);
+	
+	preempt_enable();
+}
+
+int raid6_have_altivec(void);
+#if $# == 1
+int raid6_have_altivec(void)
+{
+	/* This assumes either all CPUs have Altivec or none does */
+	return cur_cpu_spec->cpu_features & CPU_FTR_ALTIVEC;
+}
+#endif
+
+const struct raid6_calls raid6_altivec$# = {
+	raid6_altivec$#_gen_syndrome,
+	raid6_have_altivec,
+	"altivecx$#",
+	0
+};
+
+#endif /* CONFIG_ALTIVEC */

Re: PATCH: Altivec support for RAID-6

[Andrew Morton]

"H. Peter Anvin" <hpa@zytor.com> wrote:
>
>   $(obj)/raid6int1.c:   $(src)/raid6int.uc $(src)/unroll.pl FORCE

So we require that raid6int.uc propagate through the system with the x bit
set.

I wonder if it would be safer to stick a $(SHELL) in there?

Re: PATCH: Altivec support for RAID-6

[Andrew Morton]

Andrew Morton <akpm@osdl.org> wrote:
>
> "H. Peter Anvin" <hpa@zytor.com> wrote:
>  >
>  >   $(obj)/raid6int1.c:   $(src)/raid6int.uc $(src)/unroll.pl FORCE
> 
>  So we require that raid6int.uc propagate through the system with the x bit
>  set.

err, I think I misread that.  Ignore.

Re: PATCH: Altivec support for RAID-6

[Antonio Vargas]

On Wed, 17 Nov 2004 22:52:55 -0800, H. Peter Anvin <hpa@zytor.com> wrote:
> This patch adds Altivec support for RAID-6, if appropriately configured
> on the ppc or ppc64 architectures.  Note that it changes the compile
> flags for ppc64 in order to handle -maltivec correctly; this change was
> vetted on the ppc64 mailing list and OK'd by paulus.
> 
> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
> 

hpa, are you aware of any other routines which should benefit from altivec?

-- 
Greetz, Antonio Vargas aka winden of network

Las cosas no son lo que parecen, excepto cuando parecen lo que si son.

Re: PATCH: Altivec support for RAID-6

[H. Peter Anvin]

Followup to:  <69304d1104111812234656a606@mail.gmail.com>
By author:    Antonio Vargas <windenntw@gmail.com>
In newsgroup: linux.dev.kernel
> 
> hpa, are you aware of any other routines which should benefit from altivec?
> 

Presumably the XOR code used by RAID-5, and quite possibly some of the
cryptography stuff.  Unlike most SIMD instruction sets, it should be
possible to write AES using Altivec.

	-hpa

Re: PATCH: Altivec support for RAID-6

[Antonio Vargas]

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On Fri, 19 Nov 2004 13:04:11 +0100, Antonio Vargas <windenntw@gmail.com> wrote:
> On Fri, 19 Nov 2004 05:05:54 +0000 (UTC), H. Peter Anvin <hpa@zytor.com> wrote:
> > Followup to:  <69304d1104111812234656a606@mail.gmail.com>
> > By author:    Antonio Vargas <windenntw@gmail.com>
> > In newsgroup: linux.dev.kernel
> > >
> > > hpa, are you aware of any other routines which should benefit from altivec?
> > >
> >
> > Presumably the XOR code used by RAID-5, and quite possibly some of the
> > cryptography stuff.  Unlike most SIMD instruction sets, it should be
> > possible to write AES using Altivec.
> 
> I'll take a crack at the RAID-5 stuff first then.
> 

Here we go... this file is compile-tested on gcc 3.3 from userspace,
it can serve as an starting point for testing.

Signed-off-by: Antonio Vargas <windenntw@gmail.com>

-- 
Greetz, Antonio Vargas aka winden of network

Las cosas no son lo que parecen, excepto cuando parecen lo que si son.

[-- Attachment #2: xor.h --]
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/*
 * include/asm-ppc/xor.h
 *
 * Altivec optimized RAID-5 checksumming functions.
 * Copyright 2004 Antonio Vargas, windenntw@gmail.com
 *
 * Based on include/asm-generic/xor.h and drivers/md/raid6altivec.uc
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, version 2.
 *
 * You should have received a copy of the GNU General Public License
 * (for example /usr/src/linux/COPYING); if not, write to the Free
 * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#ifdef KERNEL
#include <asm-generic/xor.h>
#endif

#ifdef CONFIG_ALTIVEC

#ifdef KERNEL
#include <altivec.h>
#include <asm/cputable.h>
#include <asm/processor.h>
#include <asm/system.h>
#else
#define prefetch(x)
#define prefetchw(x)
void enable_kernel_altivec(){};
void preempt_enable(){};
void preempt_disable(){};
#endif

typedef vector unsigned char unative_t;

#define BODY\
	long lines = bytes / (4 * sizeof(unative_t)) - 1;\
	int i;\
	preempt_disable();\
	enable_kernel_altivec();\
	PREF(0)\
	do {\
		PREF(4);\
		CALC(0);\
		CALC(1);\
		CALC(2);\
		CALC(3);\
		INC;\
	} while (--lines > 0);\
	for(i = 0 ; i < 4 ; i++)\
		CALC(i);\
	preempt_enable();


#define PREF2(x) prefetchw(p1 + x); prefetch(p2  + x);
#define PREF3(x) PREF2(x) prefetch(p3  + x);
#define PREF4(x) PREF3(x) prefetch(p4  + x);
#define PREF5(x) PREF4(x) prefetch(p5  + x);

#define CALC2(x) p1[x] ^= p2[x]
#define CALC3(x) CALC2(x) ^ p3[x]
#define CALC4(x) CALC3(x) ^ p4[x]
#define CALC5(x) CALC4(x) ^ p5[x]

#define INC2 p1 += 4; p2 += 4;
#define INC3 INC2 p3 += 4;
#define INC4 INC3 p4 += 4;
#define INC5 INC4 p5 += 4;

static void
xor_altivec2(unsigned long bytes, unative_t *p1, unative_t *p2)
{
#undef PREF
#undef CALC
#undef INC
#define PREF(x) PREF2(x)
#define CALC(x) CALC2(x)
#define INC     INC2
	BODY
}

static void
xor_altivec3(unsigned long bytes, unative_t *p1, unative_t *p2, unative_t *p3)
{
#undef PREF
#undef CALC
#undef INC
#define PREF(x) PREF3(x)
#define CALC(x) CALC3(x)
#define INC     INC3
	BODY
}


static void
xor_altivec4(unsigned long bytes, unative_t *p1, unative_t *p2, unative_t *p3, unative_t *p4)
{
#undef PREF
#undef CALC
#undef INC
#define PREF(x) PREF4(x)
#define CALC(x) CALC4(x)
#define INC     INC4
	BODY
}

static void
xor_altivec5(unsigned long bytes, unative_t *p1, unative_t *p2, unative_t *p3, unative_t *p4, unative_t *p5)
{
#undef PREF
#undef CALC
#undef INC
#define PREF(x) PREF5(x)
#define CALC(x) CALC5(x)
#define INC     INC5
	BODY
}

#ifdef KERNEL
static struct xor_block_template xor_block_altivec = {
	.name = "altivec",
	.do_2 = xor_altivec2,
	.do_3 = xor_altivec3,
	.do_4 = xor_altivec4,
	.do_5 = xor_altivec5,
};

#undef  XOR_TRY_TEMPLATES
#define XOR_TRY_TEMPLATES                       \
	do {                                    \
		xor_speed(&xor_block_8regs);    \
		xor_speed(&xor_block_8regs_p);  \
		xor_speed(&xor_block_32regs);   \
		xor_speed(&xor_block_32regs_p); \
		xor_speed(&xor_block_altivec);  \
	} while (0)
#endif

#endif