[PATCH 0/3] Add eFuse region for Qualcomm SoCs

[PATCH 0/3] Add eFuse region for Qualcomm SoCs

[Mukesh Ojha]

This series is dependent on [1] for binding.

[1]
https://lore.kernel.org/lkml/1709662869-10569-1-git-send-email-quic_mojha@quicinc.com/

Mukesh Ojha (3):
  arm64: dts: qcom: sm8450: Add qfprom node
  arm64: dts: qcom: sm8550: Add qfprom node
  arm64: dts: qcom: sm8650: Add qfprom node

 arch/arm64/boot/dts/qcom/sm8450.dtsi | 7 +++++++
 arch/arm64/boot/dts/qcom/sm8550.dtsi | 7 +++++++
 arch/arm64/boot/dts/qcom/sm8650.dtsi | 7 +++++++
 3 files changed, 21 insertions(+)

-- 
2.7.4

[PATCH 1/3] arm64: dts: qcom: sm8450: Add qfprom node

[Mukesh Ojha]

Add the qfprom node for sm8450 SoC.

Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sm8450.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index b86be34a912b..02089a388d03 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -4575,6 +4575,13 @@
 			};
 		};
 
+		qfprom: efuse@221c8000 {
+			compatible = "qcom,sm8450-qfprom", "qcom,qfprom";
+			reg = <0 0x221c8000 0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
+
 		nsp_noc: interconnect@320c0000 {
 			compatible = "qcom,sm8450-nsp-noc";
 			reg = <0 0x320c0000 0 0x10000>;
-- 
2.7.4

[PATCH 2/3] arm64: dts: qcom: sm8550: Add qfprom node

[Mukesh Ojha]

Add the qfprom node for sm8550 SoC

Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sm8550.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 7474cddf7ad3..42130406342d 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -4164,6 +4164,13 @@
 			#clock-cells = <1>;
 		};
 
+		qfprom: efuse@221c8000 {
+			compatible = "qcom,sm8550-qfprom", "qcom,qfprom";
+			reg = <0 0x221c8000 0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
+
 		pmu@24091000 {
 			compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
 			reg = <0 0x24091000 0 0x1000>;
-- 
2.7.4

[PATCH 3/3] arm64: dts: qcom: sm8650: Add qfprom node

[Mukesh Ojha]

Add the qfprom node for sm8650 SoC.

Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sm8650.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index 12ba839f215e..221427bb1b22 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -4674,6 +4674,13 @@
 			#clock-cells = <1>;
 		};
 
+		qfprom: efuse@221c8000 {
+			compatible = "qcom,sm8650-qfprom", "qcom,qfprom";
+			reg = <0 0x221c8000 0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
+
 		pmu@24091000 {
 			compatible = "qcom,sm8650-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
 			reg = <0 0x24091000 0 0x1000>;
-- 
2.7.4

Re: [PATCH 0/3] Add eFuse region for Qualcomm SoCs

[Krzysztof Kozlowski]

On 06/03/2024 13:26, Mukesh Ojha wrote:
> This series is dependent on [1] for binding.
> 

Thanks for linking, that's good and explains a lot, but to clarify: No,
it does not depend. There is no dependency. This can be applied via
Qualcomm SoC.

Best regards,
Krzysztof

Re: [PATCH 1/3] arm64: dts: qcom: sm8450: Add qfprom node

[Konrad Dybcio]

On 3/6/24 13:26, Mukesh Ojha wrote:
> Add the qfprom node for sm8450 SoC.
> 
> Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
> ---
>   arch/arm64/boot/dts/qcom/sm8450.dtsi | 7 +++++++
>   1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> index b86be34a912b..02089a388d03 100644
> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> @@ -4575,6 +4575,13 @@
>   			};
>   		};
>   
> +		qfprom: efuse@221c8000 {
> +			compatible = "qcom,sm8450-qfprom", "qcom,qfprom";
> +			reg = <0 0x221c8000 0 0x1000>;

Is is really only 0x1000-long? Also, is the base you put
here the ECC-corrected part (if that still exists)?

Konrad

Re: [PATCH 1/3] arm64: dts: qcom: sm8450: Add qfprom node

[Mukesh Ojha]

Sorry for the late reply, was on vacation.

On 3/6/2024 9:24 PM, Konrad Dybcio wrote:
> 
> 
> On 3/6/24 13:26, Mukesh Ojha wrote:
>> Add the qfprom node for sm8450 SoC.
>>
>> Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/sm8450.dtsi | 7 +++++++
>>   1 file changed, 7 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi 
>> b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> index b86be34a912b..02089a388d03 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> @@ -4575,6 +4575,13 @@
>>               };
>>           };
>> +        qfprom: efuse@221c8000 {
>> +            compatible = "qcom,sm8450-qfprom", "qcom,qfprom";
>> +            reg = <0 0x221c8000 0 0x1000>;
> 
> Is is really only 0x1000-long? Also, is the base you put
> here the ECC-corrected part (if that still exists)?

No, its not.

Entire fuse space is this.
0x221C0000-0x221Cbfff

ECC corrected range is this 0x221C2000-0x221C3fff and High level OS
does have a access to ECC range however, they are not recommended for
SW usage.

Above mentioned SW range(4) in the patch is  one and only accessible 
range available out of 0-7 SW ranges(0x221C4000-0x221Cbfff with each
size 0x1000) and does not have ECC fuses.

All the downstream use cases are getting fulfilled with this.

-Mukesh

> 
> Konrad

Re: [PATCH 0/3] Add eFuse region for Qualcomm SoCs

[Mukesh Ojha]

On 3/6/2024 8:38 PM, Krzysztof Kozlowski wrote:
> On 06/03/2024 13:26, Mukesh Ojha wrote:
>> This series is dependent on [1] for binding.
>>
> 
> Thanks for linking, that's good and explains a lot, but to clarify: No,
> it does not depend. There is no dependency. This can be applied via
> Qualcomm SoC.

I see, thanks.

-Mukesh

> 
> Best regards,
> Krzysztof
> 

Re: [PATCH 1/3] arm64: dts: qcom: sm8450: Add qfprom node

[Konrad Dybcio]

On 14.03.2024 17:43, Mukesh Ojha wrote:
> Sorry for the late reply, was on vacation.
> 
> On 3/6/2024 9:24 PM, Konrad Dybcio wrote:
>>
>>
>> On 3/6/24 13:26, Mukesh Ojha wrote:
>>> Add the qfprom node for sm8450 SoC.
>>>
>>> Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
>>> ---
>>>   arch/arm64/boot/dts/qcom/sm8450.dtsi | 7 +++++++
>>>   1 file changed, 7 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>>> index b86be34a912b..02089a388d03 100644
>>> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>>> @@ -4575,6 +4575,13 @@
>>>               };
>>>           };
>>> +        qfprom: efuse@221c8000 {
>>> +            compatible = "qcom,sm8450-qfprom", "qcom,qfprom";
>>> +            reg = <0 0x221c8000 0 0x1000>;
>>
>> Is is really only 0x1000-long? Also, is the base you put
>> here the ECC-corrected part (if that still exists)?
> 
> No, its not.
> 
> Entire fuse space is this.
> 0x221C0000-0x221Cbfff
> 
> ECC corrected range is this 0x221C2000-0x221C3fff and High level OS
> does have a access to ECC range however, they are not recommended for
> SW usage.

Are you sure? Bjorn always insisted to use the corrected bit.

The ancient APQ8016 TRM also mentions this:

QFPROM Corrected Region - [...] This region is intended for
functional use of the QFPROM stored data by software.

> 
> Above mentioned SW range(4) in the patch is  one and only accessible range available out of 0-7 SW ranges(0x221C4000-0x221Cbfff with each
> size 0x1000) and does not have ECC fuses.
> 
> All the downstream use cases are getting fulfilled with this.

Right, and I don't quite get why there's an corrected region if
it sits unused.

Konrad

Re: [PATCH 1/3] arm64: dts: qcom: sm8450: Add qfprom node

[Bjorn Andersson]

On Thu, Mar 14, 2024 at 10:13:59PM +0530, Mukesh Ojha wrote:
> Sorry for the late reply, was on vacation.
> 
> On 3/6/2024 9:24 PM, Konrad Dybcio wrote:
> > 
> > 
> > On 3/6/24 13:26, Mukesh Ojha wrote:
> > > Add the qfprom node for sm8450 SoC.
> > > 
> > > Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
> > > ---
> > >   arch/arm64/boot/dts/qcom/sm8450.dtsi | 7 +++++++
> > >   1 file changed, 7 insertions(+)
> > > 
> > > diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> > > b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> > > index b86be34a912b..02089a388d03 100644
> > > --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> > > @@ -4575,6 +4575,13 @@
> > >               };
> > >           };
> > > +        qfprom: efuse@221c8000 {
> > > +            compatible = "qcom,sm8450-qfprom", "qcom,qfprom";
> > > +            reg = <0 0x221c8000 0 0x1000>;
> > 
> > Is is really only 0x1000-long? Also, is the base you put
> > here the ECC-corrected part (if that still exists)?
> 
> No, its not.
> 
> Entire fuse space is this.
> 0x221C0000-0x221Cbfff
> 
> ECC corrected range is this 0x221C2000-0x221C3fff and High level OS

That's 0x2000. Does this then also imply that the ECC-corrected values
are no longer mapped 1:1 with non-corrected, or why do they differ in
size?

> does have a access to ECC range however, they are not recommended for
> SW usage.
> 
> Above mentioned SW range(4) in the patch is  one and only accessible range
> available out of 0-7 SW ranges(0x221C4000-0x221Cbfff with each
> size 0x1000) and does not have ECC fuses.
> 

So you're saying that in contrast to other platforms, the 4th software
range, dedicated for HLOS, does not have a matching ECC-corrected
shadow? If that's the case, then "not recommended for SW usage" sounds
wrong.

> All the downstream use cases are getting fulfilled with this.
> 

You only need ECC if you're unlucky...

Regards,
Bjorn