* [PATCH 01/14] arm64: dts: qcom: sm6115: Add basic soc dtsi
[not found] <20220901072414.1923075-1-iskren.chernev@gmail.com>
@ 2022-09-01 7:24 ` Iskren Chernev
2022-09-01 16:03 ` Krzysztof Kozlowski
2022-09-01 7:24 ` [PATCH 02/14] arm64: dts: qcom: sm6115: Add rpmcc and rpmpd nodes Iskren Chernev
` (12 subsequent siblings)
13 siblings, 1 reply; 35+ messages in thread
From: Iskren Chernev @ 2022-09-01 7:24 UTC (permalink / raw)
To: Bjorn Andersson, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm,
devicetree, Iskren Chernev, Andy Gross, Konrad Dybcio,
Krzysztof Kozlowski, linux-kernel
Add support for Qualcomm SM6115 SoC. This includes bare minimum:
- CPUs
- intc
- timer
- reserved memory
Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
---
arch/arm64/boot/dts/qcom/sm6115.dtsi | 433 +++++++++++++++++++++++++++
1 file changed, 433 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sm6115.dtsi
diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
new file mode 100644
index 000000000000..69d9de540478
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
@@ -0,0 +1,433 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com>
+ */
+
+#include <dt-bindings/clock/qcom,gcc-sm6115.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+
+/ {
+ interrupt-parent = <&intc>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen { };
+
+ clocks {
+ xo_board: xo-board {
+ compatible = "fixed-clock";
+ clock-frequency = <19200000>;
+ #clock-cells = <0>;
+ clock-output-names = "xo_board";
+ };
+
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <32764>;
+ #clock-cells = <0>;
+ clock-output-names = "sleep_clk";
+ };
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "qcom,kryo260";
+ reg = <0x0 0x0>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ L2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+ };
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "qcom,kryo260";
+ reg = <0x0 0x1>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+
+ CPU2: cpu@2 {
+ device_type = "cpu";
+ compatible = "qcom,kryo260";
+ reg = <0x0 0x2>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+
+ CPU3: cpu@3 {
+ device_type = "cpu";
+ compatible = "qcom,kryo260";
+ reg = <0x0 0x3>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+
+ CPU4: cpu@100 {
+ device_type = "cpu";
+ compatible = "qcom,kryo260";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1638>;
+ dynamic-power-coefficient = <282>;
+ next-level-cache = <&L2_1>;
+ L2_1: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+ };
+
+ CPU5: cpu@101 {
+ device_type = "cpu";
+ compatible = "qcom,kryo260";
+ reg = <0x0 0x101>;
+ capacity-dmips-mhz = <1638>;
+ dynamic-power-coefficient = <282>;
+ enable-method = "psci";
+ next-level-cache = <&L2_1>;
+ };
+
+ CPU6: cpu@102 {
+ device_type = "cpu";
+ compatible = "qcom,kryo260";
+ reg = <0x0 0x102>;
+ capacity-dmips-mhz = <1638>;
+ dynamic-power-coefficient = <282>;
+ enable-method = "psci";
+ next-level-cache = <&L2_1>;
+ };
+
+ CPU7: cpu@103 {
+ device_type = "cpu";
+ compatible = "qcom,kryo260";
+ reg = <0x0 0x103>;
+ capacity-dmips-mhz = <1638>;
+ dynamic-power-coefficient = <282>;
+ enable-method = "psci";
+ next-level-cache = <&L2_1>;
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+
+ core1 {
+ cpu = <&CPU1>;
+ };
+
+ core2 {
+ cpu = <&CPU2>;
+ };
+
+ core3 {
+ cpu = <&CPU3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&CPU4>;
+ };
+
+ core1 {
+ cpu = <&CPU5>;
+ };
+
+ core2 {
+ cpu = <&CPU6>;
+ };
+
+ core3 {
+ cpu = <&CPU7>;
+ };
+ };
+ };
+ };
+
+ firmware {
+ scm: scm {
+ compatible = "qcom,scm-sm6115", "qcom,scm";
+ #reset-cells = <1>;
+ };
+ };
+
+ tcsr_mutex: hwlock {
+ compatible = "qcom,tcsr-mutex";
+ syscon = <&tcsr_mutex_regs 0 0x1000>;
+ #hwlock-cells = <1>;
+ };
+
+ memory {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the reg */
+ reg = <0 0 0 0>;
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ hyp_mem: memory@45700000 {
+ reg = <0x0 0x45700000 0x0 0x600000>;
+ no-map;
+ };
+
+ xbl_aop_mem: memory@45e00000 {
+ reg = <0x0 0x45e00000 0x0 0x140000>;
+ no-map;
+ };
+
+ sec_apps_mem: memory@45fff000 {
+ reg = <0x0 0x45fff000 0x0 0x1000>;
+ no-map;
+ };
+
+ smem_mem: memory@46000000 {
+ reg = <0x0 0x46000000 0x0 0x200000>;
+ no-map;
+ };
+
+ cdsp_sec_mem: memory@46200000 {
+ reg = <0x0 0x46200000 0x0 0x1e00000>;
+ no-map;
+ };
+
+ pil_modem_mem: memory@4ab00000 {
+ reg = <0x0 0x4ab00000 0x0 0x6900000>;
+ no-map;
+ };
+
+ pil_video_mem: memory@51400000 {
+ reg = <0x0 0x51400000 0x0 0x500000>;
+ no-map;
+ };
+
+ wlan_msa_mem: memory@51900000 {
+ reg = <0x0 0x51900000 0x0 0x100000>;
+ no-map;
+ };
+
+ pil_cdsp_mem: memory@51a00000 {
+ reg = <0x0 0x51a00000 0x0 0x1e00000>;
+ no-map;
+ };
+
+ pil_adsp_mem: memory@53800000 {
+ reg = <0x0 0x53800000 0x0 0x2800000>;
+ no-map;
+ };
+
+ pil_ipa_fw_mem: memory@56100000 {
+ reg = <0x0 0x56100000 0x0 0x10000>;
+ no-map;
+ };
+
+ pil_ipa_gsi_mem: memory@56110000 {
+ reg = <0x0 0x56110000 0x0 0x5000>;
+ no-map;
+ };
+
+ pil_gpu_mem: memory@56115000 {
+ reg = <0x0 0x56115000 0x0 0x2000>;
+ no-map;
+ };
+
+ cont_splash_memory: memory@5c000000 {
+ reg = <0x0 0x5c000000 0x0 0x00f00000>;
+ no-map;
+ };
+
+ dfps_data_memory: memory@5cf00000 {
+ reg = <0x0 0x5cf00000 0x0 0x0100000>;
+ no-map;
+ };
+
+ removed_mem: memory@60000000 {
+ reg = <0x0 0x60000000 0x0 0x3900000>;
+ no-map;
+ };
+
+ secure_display_memory: memory@f3c00000 {
+ reg = <0x0 0xf3c00000 0x0 0x5c00000>;
+ no-map;
+ };
+
+ dump_mem: memory@f9800000 {
+ reg = <0x0 0xf9800000 0x0 0x800000>;
+ no-map;
+ };
+
+ adsp_mem: memory@fa000000 {
+ reg = <0x0 0xfa000000 0x0 0x800000>;
+ no-map;
+ };
+
+ qseecom_mem: memory@fa800000 {
+ reg = <0x0 0xfa800000 0x0 0x1400000>;
+ no-map;
+ };
+
+ user_contig_mem: memory@fbc00000 {
+ reg = <0x0 0xfbc00000 0x0 0x1000000>;
+ no-map;
+ };
+
+ qseecom_ta_mem: memory@fcc00000 {
+ reg = <0x0 0xfcc00000 0x0 0x1000000>;
+ no-map;
+ };
+
+ linux_cma_mem: memory@fdc00000 {
+ reg = <0x0 0xfdc00000 0x0 0x2000000>;
+ no-map;
+ };
+
+ };
+
+ smem {
+ compatible = "qcom,smem";
+ memory-region = <&smem_mem>;
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
+ hwlocks = <&tcsr_mutex 3>;
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+
+ qfprom@1b40000 {
+ compatible = "qcom,qfprom";
+ reg = <0x1b40000 0x7000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ qusb2_hstx_trim: hstx_trim@25b {
+ reg = <0x25b 0x1>;
+ bits = <1 4>;
+ };
+ };
+
+ tcsr_mutex_regs: syscon@1f40000 {
+ compatible = "syscon";
+ reg = <0x340000 0x20000>;
+ };
+
+ rpm_msg_ram: memory@45f0000 {
+ compatible = "qcom,rpm-msg-ram";
+ reg = <0x45f0000 0x7000>;
+ };
+
+ timer@f120000 {
+ compatible = "arm,armv7-timer-mem";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ reg = <0xf120000 0x1000>;
+ clock-frequency = <19200000>;
+
+ frame@f121000 {
+ frame-number = <0>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xf121000 0x1000>,
+ <0xf122000 0x1000>;
+ };
+
+ frame@f123000 {
+ frame-number = <1>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xf123000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@f124000 {
+ frame-number = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xf124000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@f125000 {
+ frame-number = <3>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xf125000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@f126000 {
+ frame-number = <4>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xf126000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@f127000 {
+ frame-number = <5>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xf127000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@f128000 {
+ frame-number = <6>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xf128000 0x1000>;
+ status = "disabled";
+ };
+ };
+
+ intc: interrupt-controller@f200000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupt-parent = <&intc>;
+ #redistributor-regions = <1>;
+ redistributor-stride = <0x0 0x20000>;
+ reg = <0xf200000 0x10000>,
+ <0xf300000 0x100000>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 1 0xf08>,
+ <GIC_PPI 2 0xf08>,
+ <GIC_PPI 3 0xf08>,
+ <GIC_PPI 0 0xf08>;
+ clock-frequency = <19200000>;
+ };
+};
--
2.37.2
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 02/14] arm64: dts: qcom: sm6115: Add rpmcc and rpmpd nodes
[not found] <20220901072414.1923075-1-iskren.chernev@gmail.com>
2022-09-01 7:24 ` [PATCH 01/14] arm64: dts: qcom: sm6115: Add basic soc dtsi Iskren Chernev
@ 2022-09-01 7:24 ` Iskren Chernev
2022-09-01 7:24 ` [PATCH 03/14] arm64: dts: qcom: sm6115: Add GCC node Iskren Chernev
` (11 subsequent siblings)
13 siblings, 0 replies; 35+ messages in thread
From: Iskren Chernev @ 2022-09-01 7:24 UTC (permalink / raw)
To: Bjorn Andersson, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm,
devicetree, Iskren Chernev, Andy Gross, Konrad Dybcio,
Krzysztof Kozlowski, linux-kernel
The sm6115 uses glink rpm to control some clocks and regulators.
Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
---
arch/arm64/boot/dts/qcom/sm6115.dtsi | 67 ++++++++++++++++++++++++++++
1 file changed, 67 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
index 69d9de540478..7496b3e0ff48 100644
--- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
@@ -315,6 +315,66 @@ linux_cma_mem: memory@fdc00000 {
};
+ rpm-glink {
+ compatible = "qcom,glink-rpm";
+
+ interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
+ mboxes = <&apcs_glb 0>;
+
+ rpm_requests: rpm-requests {
+ compatible = "qcom,rpm-sm6115";
+ qcom,glink-channels = "rpm_requests";
+
+ rpmcc: rpmcc {
+ compatible = "qcom,rpmcc-sm6115";
+ #clock-cells = <1>;
+ };
+
+ rpmpd: power-controller {
+ compatible = "qcom,sm6115-rpmpd";
+ #power-domain-cells = <1>;
+ operating-points-v2 = <&rpmpd_opp_table>;
+
+ rpmpd_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ rpmpd_opp_min_svs: opp1 {
+ opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
+ };
+
+ rpmpd_opp_low_svs: opp2 {
+ opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
+ };
+
+ rpmpd_opp_svs: opp3 {
+ opp-level = <RPM_SMD_LEVEL_SVS>;
+ };
+
+ rpmpd_opp_svs_plus: opp4 {
+ opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
+ };
+
+ rpmpd_opp_nom: opp5 {
+ opp-level = <RPM_SMD_LEVEL_NOM>;
+ };
+
+ rpmpd_opp_nom_plus: opp6 {
+ opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
+ };
+
+ rpmpd_opp_turbo: opp7 {
+ opp-level = <RPM_SMD_LEVEL_TURBO>;
+ };
+
+ rpmpd_opp_turbo_plus: opp8 {
+ opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
+ };
+ };
+ };
+ };
+ };
+
smem {
compatible = "qcom,smem";
memory-region = <&smem_mem>;
@@ -350,6 +410,13 @@ rpm_msg_ram: memory@45f0000 {
reg = <0x45f0000 0x7000>;
};
+ apcs_glb: mailbox@f111000 {
+ compatible = "qcom,sm6115-apcs-hmss-global";
+ reg = <0xf111000 0x1000>;
+
+ #mbox-cells = <1>;
+ };
+
timer@f120000 {
compatible = "arm,armv7-timer-mem";
#address-cells = <1>;
--
2.37.2
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 03/14] arm64: dts: qcom: sm6115: Add GCC node
[not found] <20220901072414.1923075-1-iskren.chernev@gmail.com>
2022-09-01 7:24 ` [PATCH 01/14] arm64: dts: qcom: sm6115: Add basic soc dtsi Iskren Chernev
2022-09-01 7:24 ` [PATCH 02/14] arm64: dts: qcom: sm6115: Add rpmcc and rpmpd nodes Iskren Chernev
@ 2022-09-01 7:24 ` Iskren Chernev
2022-09-01 16:05 ` Krzysztof Kozlowski
2022-09-01 7:24 ` [PATCH 04/14] arm64: dts: qcom: sm6115: Add pinctrl node Iskren Chernev
` (10 subsequent siblings)
13 siblings, 1 reply; 35+ messages in thread
From: Iskren Chernev @ 2022-09-01 7:24 UTC (permalink / raw)
To: Bjorn Andersson, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm,
devicetree, Iskren Chernev, Andy Gross, Konrad Dybcio,
Krzysztof Kozlowski, linux-kernel
Add support for the main clock bundle on the SM6115.
Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
---
arch/arm64/boot/dts/qcom/sm6115.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
index 7496b3e0ff48..5af915e80017 100644
--- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
@@ -388,6 +388,17 @@ soc: soc {
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
+ gcc: clock-controller@1400000 {
+ compatible = "qcom,gcc-sm6115", "syscon";
+ reg = <0x1400000 0x1f0000>;
+ reg-names = "cc_base";
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
+ clock-names = "bi_tcxo", "sleep_clk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
qfprom@1b40000 {
compatible = "qcom,qfprom";
reg = <0x1b40000 0x7000>;
--
2.37.2
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 04/14] arm64: dts: qcom: sm6115: Add pinctrl node
[not found] <20220901072414.1923075-1-iskren.chernev@gmail.com>
` (2 preceding siblings ...)
2022-09-01 7:24 ` [PATCH 03/14] arm64: dts: qcom: sm6115: Add GCC node Iskren Chernev
@ 2022-09-01 7:24 ` Iskren Chernev
2022-09-01 7:24 ` [PATCH 05/14] arm64: dts: qcom: sm6115: Add apps smmu node Iskren Chernev
` (9 subsequent siblings)
13 siblings, 0 replies; 35+ messages in thread
From: Iskren Chernev @ 2022-09-01 7:24 UTC (permalink / raw)
To: Bjorn Andersson, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm,
devicetree, Iskren Chernev, Andy Gross, Konrad Dybcio,
Krzysztof Kozlowski, linux-kernel
Add support for the TLMM on the SM6115.
Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
---
arch/arm64/boot/dts/qcom/sm6115.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
index 5af915e80017..efbc81d2253b 100644
--- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
@@ -388,6 +388,19 @@ soc: soc {
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
+ tlmm: pinctrl@500000 {
+ compatible = "qcom,sm6115-tlmm";
+ reg = <0x500000 0x400000>,
+ <0x900000 0x400000>,
+ <0xd00000 0x400000>;
+ reg-names = "west", "south", "east";
+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ gpio-ranges = <&tlmm 0 0 121>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ };
+
gcc: clock-controller@1400000 {
compatible = "qcom,gcc-sm6115", "syscon";
reg = <0x1400000 0x1f0000>;
--
2.37.2
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 05/14] arm64: dts: qcom: sm6115: Add apps smmu node
[not found] <20220901072414.1923075-1-iskren.chernev@gmail.com>
` (3 preceding siblings ...)
2022-09-01 7:24 ` [PATCH 04/14] arm64: dts: qcom: sm6115: Add pinctrl node Iskren Chernev
@ 2022-09-01 7:24 ` Iskren Chernev
2022-09-01 16:05 ` Krzysztof Kozlowski
2022-09-01 7:24 ` [PATCH 06/14] arm64: dts: qcom: sm6115: Add usb and related phy nodes Iskren Chernev
` (8 subsequent siblings)
13 siblings, 1 reply; 35+ messages in thread
From: Iskren Chernev @ 2022-09-01 7:24 UTC (permalink / raw)
To: Bjorn Andersson, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm,
devicetree, Iskren Chernev, Andy Gross, Konrad Dybcio,
Krzysztof Kozlowski, linux-kernel
Add support for apps smmu (one of the two smmus) present on the SM6115.
Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
---
arch/arm64/boot/dts/qcom/sm6115.dtsi | 73 ++++++++++++++++++++++++++++
1 file changed, 73 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
index efbc81d2253b..a6be8b93a44d 100644
--- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
@@ -434,6 +434,79 @@ rpm_msg_ram: memory@45f0000 {
reg = <0x45f0000 0x7000>;
};
+ apps_smmu: iommu@c600000 {
+ compatible = "qcom,sm6115-smmu-500", "arm,mmu-500";
+ reg = <0xc600000 0x80000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
apcs_glb: mailbox@f111000 {
compatible = "qcom,sm6115-apcs-hmss-global";
reg = <0xf111000 0x1000>;
--
2.37.2
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 06/14] arm64: dts: qcom: sm6115: Add usb and related phy nodes
[not found] <20220901072414.1923075-1-iskren.chernev@gmail.com>
` (4 preceding siblings ...)
2022-09-01 7:24 ` [PATCH 05/14] arm64: dts: qcom: sm6115: Add apps smmu node Iskren Chernev
@ 2022-09-01 7:24 ` Iskren Chernev
2022-09-01 16:06 ` Krzysztof Kozlowski
2022-09-01 7:24 ` [PATCH 07/14] arm64: dts: qcom: sm6115: Add sdhci nodes and related pinctrl Iskren Chernev
` (7 subsequent siblings)
13 siblings, 1 reply; 35+ messages in thread
From: Iskren Chernev @ 2022-09-01 7:24 UTC (permalink / raw)
To: Bjorn Andersson, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm,
devicetree, Iskren Chernev, Andy Gross, Konrad Dybcio,
Krzysztof Kozlowski, linux-kernel
Add support for the USB controller and its HS PHY to SM6115.
Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
---
arch/arm64/boot/dts/qcom/sm6115.dtsi | 62 ++++++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
index a6be8b93a44d..00fd185c87aa 100644
--- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
@@ -412,6 +412,21 @@ gcc: clock-controller@1400000 {
#power-domain-cells = <1>;
};
+ hsusb_phy: phy@1613000 {
+ compatible = "qcom,sm6115-qusb2-phy";
+ reg = <0x1613000 0x180>;
+ #phy-cells = <0>;
+
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&gcc GCC_AHB2PHY_USB_CLK>;
+ clock-names = "ref", "cfg_ahb";
+
+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+ nvmem-cells = <&qusb2_hstx_trim>;
+
+ status = "disabled";
+ };
+
qfprom@1b40000 {
compatible = "qcom,qfprom";
reg = <0x1b40000 0x7000>;
@@ -434,6 +449,53 @@ rpm_msg_ram: memory@45f0000 {
reg = <0x45f0000 0x7000>;
};
+ usb3: usb@4ef8800 {
+ compatible = "qcom,sm6115-dwc3", "qcom,dwc3";
+ reg = <0x04ef8800 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+ <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+ <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
+ clock-names = "cfg_noc", "core", "iface", "mock_utmi",
+ "sleep", "xo";
+
+ assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <66666667>;
+
+ interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hs_phy_irq", "ss_phy_irq";
+
+ resets = <&gcc GCC_USB30_PRIM_BCR>;
+ power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
+ qcom,select-utmi-as-pipe-clk;
+ status = "disabled";
+
+ usb3_dwc3: dwc3@4e00000 {
+ compatible = "snps,dwc3";
+ reg = <0x04e00000 0xcd00>;
+ interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&hsusb_phy>;
+ phy-names = "usb2-phy";
+ iommus = <&apps_smmu 0x120 0x0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ snps,has-lpm-erratum;
+ snps,hird-threshold = /bits/ 8 <0x10>;
+ snps,usb3_lpm_capable;
+ imod-interval-ns = <160>;
+ maximum-speed = "high-speed";
+ dr_mode = "peripheral";
+ };
+ };
+
apps_smmu: iommu@c600000 {
compatible = "qcom,sm6115-smmu-500", "arm,mmu-500";
reg = <0xc600000 0x80000>;
--
2.37.2
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 07/14] arm64: dts: qcom: sm6115: Add sdhci nodes and related pinctrl
[not found] <20220901072414.1923075-1-iskren.chernev@gmail.com>
` (5 preceding siblings ...)
2022-09-01 7:24 ` [PATCH 06/14] arm64: dts: qcom: sm6115: Add usb and related phy nodes Iskren Chernev
@ 2022-09-01 7:24 ` Iskren Chernev
2022-09-01 16:08 ` Krzysztof Kozlowski
2022-09-01 7:24 ` [PATCH 08/14] dt-bindings: ufs: qcom: Add sm6115 binding Iskren Chernev
` (6 subsequent siblings)
13 siblings, 1 reply; 35+ messages in thread
From: Iskren Chernev @ 2022-09-01 7:24 UTC (permalink / raw)
To: Bjorn Andersson, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm,
devicetree, Iskren Chernev, Andy Gross, Konrad Dybcio,
Krzysztof Kozlowski, linux-kernel
Add support for the two sdhci's present on the SM6115 and the related
pinctrl.
Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
---
arch/arm64/boot/dts/qcom/sm6115.dtsi | 171 +++++++++++++++++++++++++++
1 file changed, 171 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
index 00fd185c87aa..cde963c56ac9 100644
--- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
@@ -399,6 +399,110 @@ tlmm: pinctrl@500000 {
gpio-ranges = <&tlmm 0 0 121>;
#gpio-cells = <2>;
interrupt-controller;
+
+ sdc1_state_on: sdc1-on {
+ clk {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+
+ cmd {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ data {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ rclk {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+ };
+
+ sdc1_state_off: sdc1-off {
+ clk {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ cmd {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ data {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ rclk {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+ };
+
+ sdc2_state_on: sdc2-on {
+ clk {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+
+ cmd {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ data {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ sd-cd {
+ pins = "gpio88";
+ function = "gpio";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+ };
+
+ sdc2_state_off: sdc2-off {
+ clk {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ cmd {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ data {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ sd-cd {
+ pins = "gpio88";
+ function = "gpio";
+ bias-disable;
+ drive-strength = <2>;
+ };
+ };
};
gcc: clock-controller@1400000 {
@@ -449,6 +553,73 @@ rpm_msg_ram: memory@45f0000 {
reg = <0x45f0000 0x7000>;
};
+ sdhc_1: sdhci@4744000 {
+ compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0x4744000 0x1000>, <0x4745000 0x1000>, <0x4748000 0x8000>;
+ reg-names = "hc", "cqhci", "ice";
+
+ interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&xo_board>,
+ <&gcc GCC_SDCC1_ICE_CORE_CLK>;
+ clock-names = "iface", "core", "xo", "ice_core_clk";
+
+ pinctrl-0 = <&sdc1_state_on>;
+ pinctrl-1 = <&sdc1_state_off>;
+ pinctrl-names = "default", "sleep";
+
+ bus-width = <8>;
+ non-removable;
+ status = "disabled";
+ };
+
+ sdhc_2: sdhci@4784000 {
+ compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0x04784000 0x1000>;
+ reg-names = "hc";
+
+ interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>,
+ <&xo_board>;
+ clock-names = "iface", "core", "xo";
+
+ pinctrl-0 = <&sdc2_state_on>;
+ pinctrl-1 = <&sdc2_state_off>;
+ pinctrl-names = "default", "sleep";
+
+ power-domains = <&rpmpd SM6115_VDDCX>;
+ operating-points-v2 = <&sdhc2_opp_table>;
+ iommus = <&apps_smmu 0x00a0 0x0>;
+ resets = <&gcc GCC_SDCC2_BCR>;
+
+ bus-width = <4>;
+ qcom,dll-config = <0x0007642c>;
+ qcom,ddr-config = <0x80040868>;
+ status = "disabled";
+
+ sdhc2_opp_table: sdhc2-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmpd_opp_low_svs>;
+ };
+
+ opp-202000000 {
+ opp-hz = /bits/ 64 <202000000>;
+ required-opps = <&rpmpd_opp_nom>;
+ };
+ };
+ };
+
usb3: usb@4ef8800 {
compatible = "qcom,sm6115-dwc3", "qcom,dwc3";
reg = <0x04ef8800 0x400>;
--
2.37.2
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 08/14] dt-bindings: ufs: qcom: Add sm6115 binding
[not found] <20220901072414.1923075-1-iskren.chernev@gmail.com>
` (6 preceding siblings ...)
2022-09-01 7:24 ` [PATCH 07/14] arm64: dts: qcom: sm6115: Add sdhci nodes and related pinctrl Iskren Chernev
@ 2022-09-01 7:24 ` Iskren Chernev
2022-09-01 16:11 ` Krzysztof Kozlowski
2022-09-01 7:24 ` [PATCH 09/14] arm64: dts: qcom: sm6115: Add UFS nodes Iskren Chernev
` (5 subsequent siblings)
13 siblings, 1 reply; 35+ messages in thread
From: Iskren Chernev @ 2022-09-01 7:24 UTC (permalink / raw)
To: Bjorn Andersson, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm,
devicetree, Iskren Chernev, Andy Gross, Konrad Dybcio,
Alim Akhtar, Avri Altman, Bart Van Assche, Krzysztof Kozlowski,
linux-scsi, linux-kernel
Add SM6115 UFS to DT schema.
Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
---
.../devicetree/bindings/ufs/qcom,ufs.yaml | 26 +++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
index f2d6298d926c..7c5f6e2e6d4c 100644
--- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
@@ -28,6 +28,7 @@ properties:
- qcom,msm8998-ufshc
- qcom,sc8280xp-ufshc
- qcom,sdm845-ufshc
+ - qcom,sm6115-ufshc
- qcom,sm6350-ufshc
- qcom,sm8150-ufshc
- qcom,sm8250-ufshc
@@ -178,6 +179,31 @@ allOf:
minItems: 1
maxItems: 1
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sm6115-ufshc
+ then:
+ properties:
+ clocks:
+ minItems: 8
+ maxItems: 8
+ clock-names:
+ items:
+ - const: core_clk
+ - const: bus_aggr_clk
+ - const: iface_clk
+ - const: core_clk_unipro
+ - const: core_clk_ice
+ - const: ref_clk
+ - const: tx_lane0_sync_clk
+ - const: rx_lane0_sync_clk
+ reg:
+ minItems: 1
+ maxItems: 1
+
# TODO: define clock bindings for qcom,msm8994-ufshc
unevaluatedProperties: false
--
2.37.2
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 09/14] arm64: dts: qcom: sm6115: Add UFS nodes
[not found] <20220901072414.1923075-1-iskren.chernev@gmail.com>
` (7 preceding siblings ...)
2022-09-01 7:24 ` [PATCH 08/14] dt-bindings: ufs: qcom: Add sm6115 binding Iskren Chernev
@ 2022-09-01 7:24 ` Iskren Chernev
2022-09-01 16:13 ` Krzysztof Kozlowski
2022-09-01 7:24 ` [PATCH 10/14] arm64: dts: qcom: sm6115: Add SPMI bus node Iskren Chernev
` (4 subsequent siblings)
13 siblings, 1 reply; 35+ messages in thread
From: Iskren Chernev @ 2022-09-01 7:24 UTC (permalink / raw)
To: Bjorn Andersson, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm,
devicetree, Iskren Chernev, Andy Gross, Konrad Dybcio,
Krzysztof Kozlowski, linux-kernel
The SM6115 comes with UFS support, so add the related UFS and UFS PHY
nodes.
Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
---
arch/arm64/boot/dts/qcom/sm6115.dtsi | 70 ++++++++++++++++++++++++++++
1 file changed, 70 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
index cde963c56ac9..491fffff8aa1 100644
--- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
@@ -620,6 +620,76 @@ opp-202000000 {
};
};
+ ufs_mem_hc: ufshc@4804000 {
+ compatible = "qcom,sm6115-ufshc", "qcom,ufshc",
+ "jedec,ufs-2.0";
+ reg = <0x4804000 0x3000>, <0x4810000 0x8000>;
+ reg-names = "std", "ice";
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&ufs_mem_phy_lanes>;
+ phy-names = "ufsphy";
+ lanes-per-direction = <1>;
+ #reset-cells = <1>;
+ resets = <&gcc GCC_UFS_PHY_BCR>;
+ reset-names = "rst";
+
+ power-domains = <&gcc GCC_UFS_PHY_GDSC>;
+ iommus = <&apps_smmu 0x100 0>;
+
+ clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_UFS_PHY_AHB_CLK>,
+ <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+ <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
+ <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;
+ clock-names = "core_clk",
+ "bus_aggr_clk",
+ "iface_clk",
+ "core_clk_unipro",
+ "core_clk_ice",
+ "ref_clk",
+ "tx_lane0_sync_clk",
+ "rx_lane0_sync_clk";
+
+ freq-table-hz = <50000000 200000000>,
+ <0 0>,
+ <0 0>,
+ <37500000 150000000>,
+ <75000000 300000000>,
+ <0 0>,
+ <0 0>,
+ <0 0>;
+
+ non-removable;
+ status = "disabled";
+ };
+
+ ufs_mem_phy: phy@4807000 {
+ compatible = "qcom,sm6115-qmp-ufs-phy";
+ reg = <0x4807000 0x1c4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_UFS_CLKREF_CLK>,
+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+ clock-names = "ref", "ref_aux";
+
+ resets = <&ufs_mem_hc 0>;
+ reset-names = "ufsphy";
+ status = "disabled";
+
+ ufs_mem_phy_lanes: lanes@4807400 {
+ reg = <0x4807400 0x098>,
+ <0x4807600 0x130>,
+ <0x4807c00 0x16c>;
+ #phy-cells = <0>;
+ };
+ };
+
+
usb3: usb@4ef8800 {
compatible = "qcom,sm6115-dwc3", "qcom,dwc3";
reg = <0x04ef8800 0x400>;
--
2.37.2
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 10/14] arm64: dts: qcom: sm6115: Add SPMI bus node
[not found] <20220901072414.1923075-1-iskren.chernev@gmail.com>
` (8 preceding siblings ...)
2022-09-01 7:24 ` [PATCH 09/14] arm64: dts: qcom: sm6115: Add UFS nodes Iskren Chernev
@ 2022-09-01 7:24 ` Iskren Chernev
2022-09-01 16:14 ` Krzysztof Kozlowski
2022-09-01 7:24 ` [PATCH 11/14] dt-bindings: arm: cpus: Add kryo240 compatible Iskren Chernev
` (3 subsequent siblings)
13 siblings, 1 reply; 35+ messages in thread
From: Iskren Chernev @ 2022-09-01 7:24 UTC (permalink / raw)
To: Bjorn Andersson, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm,
devicetree, Iskren Chernev, Andy Gross, Konrad Dybcio,
Krzysztof Kozlowski, linux-kernel
Add support for the SPMI bus on the SM6115.
Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
---
arch/arm64/boot/dts/qcom/sm6115.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
index 491fffff8aa1..d578f8425e36 100644
--- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
@@ -543,6 +543,25 @@ qusb2_hstx_trim: hstx_trim@25b {
};
};
+ spmi_bus: qcom,spmi@1c40000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0x1c40000 0x1100>,
+ <0x1e00000 0x2000000>,
+ <0x3e00000 0x100000>,
+ <0x3f00000 0xa0000>,
+ <0x1c0a000 0x26000>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ cell-index = <0>;
+ };
+
tcsr_mutex_regs: syscon@1f40000 {
compatible = "syscon";
reg = <0x340000 0x20000>;
--
2.37.2
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 11/14] dt-bindings: arm: cpus: Add kryo240 compatible
[not found] <20220901072414.1923075-1-iskren.chernev@gmail.com>
` (9 preceding siblings ...)
2022-09-01 7:24 ` [PATCH 10/14] arm64: dts: qcom: sm6115: Add SPMI bus node Iskren Chernev
@ 2022-09-01 7:24 ` Iskren Chernev
2022-09-01 15:29 ` Vinod Koul
2022-09-01 16:14 ` Krzysztof Kozlowski
2022-09-01 7:24 ` [PATCH 12/14] arm64: dts: qcom: sm4250: Add soc dtsi Iskren Chernev
` (2 subsequent siblings)
13 siblings, 2 replies; 35+ messages in thread
From: Iskren Chernev @ 2022-09-01 7:24 UTC (permalink / raw)
To: Bjorn Andersson, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm,
devicetree, Iskren Chernev, Krzysztof Kozlowski, Vinod Koul,
Robin Murphy, Stephan Gerhold, Luca Weiss, Maxime Ripard,
Bartosz Dudziak, Lorenzo Pieralisi, linux-kernel
Kryo240 is found in SM4250, the slower sibling of the SM6115.
Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
---
Documentation/devicetree/bindings/arm/cpus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
index a07c5bac7c46..5c13b73e4d57 100644
--- a/Documentation/devicetree/bindings/arm/cpus.yaml
+++ b/Documentation/devicetree/bindings/arm/cpus.yaml
@@ -174,6 +174,7 @@ properties:
- nvidia,tegra194-carmel
- qcom,krait
- qcom,kryo
+ - qcom,kryo240
- qcom,kryo250
- qcom,kryo260
- qcom,kryo280
--
2.37.2
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 12/14] arm64: dts: qcom: sm4250: Add soc dtsi
[not found] <20220901072414.1923075-1-iskren.chernev@gmail.com>
` (10 preceding siblings ...)
2022-09-01 7:24 ` [PATCH 11/14] dt-bindings: arm: cpus: Add kryo240 compatible Iskren Chernev
@ 2022-09-01 7:24 ` Iskren Chernev
2022-09-01 7:24 ` [PATCH 13/14] dt-bindings: arm: qcom: Add compatible for oneplus,billie2 phone Iskren Chernev
2022-09-01 7:24 ` [PATCH 14/14] arm64: dts: qcom: sm4250: Add support for oneplus-billie2 Iskren Chernev
13 siblings, 0 replies; 35+ messages in thread
From: Iskren Chernev @ 2022-09-01 7:24 UTC (permalink / raw)
To: Bjorn Andersson, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm,
devicetree, Iskren Chernev, Andy Gross, Konrad Dybcio,
Krzysztof Kozlowski, linux-kernel
The SM4250 is a downclocked version of the SM6115.
Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
---
arch/arm64/boot/dts/qcom/sm4250.dtsi | 38 ++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sm4250.dtsi
diff --git a/arch/arm64/boot/dts/qcom/sm4250.dtsi b/arch/arm64/boot/dts/qcom/sm4250.dtsi
new file mode 100644
index 000000000000..8cadf813e55b
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm4250.dtsi
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com>
+ */
+
+#include "sm6115.dtsi"
+
+&CPU0 {
+ compatible = "qcom,kryo240";
+};
+
+&CPU1 {
+ compatible = "qcom,kryo240";
+};
+
+&CPU2 {
+ compatible = "qcom,kryo240";
+};
+
+&CPU3 {
+ compatible = "qcom,kryo240";
+};
+
+&CPU4 {
+ compatible = "qcom,kryo240";
+};
+
+&CPU5 {
+ compatible = "qcom,kryo240";
+};
+
+&CPU6 {
+ compatible = "qcom,kryo240";
+};
+
+&CPU7 {
+ compatible = "qcom,kryo240";
+};
--
2.37.2
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 13/14] dt-bindings: arm: qcom: Add compatible for oneplus,billie2 phone
[not found] <20220901072414.1923075-1-iskren.chernev@gmail.com>
` (11 preceding siblings ...)
2022-09-01 7:24 ` [PATCH 12/14] arm64: dts: qcom: sm4250: Add soc dtsi Iskren Chernev
@ 2022-09-01 7:24 ` Iskren Chernev
2022-09-01 16:17 ` Krzysztof Kozlowski
2022-09-01 7:24 ` [PATCH 14/14] arm64: dts: qcom: sm4250: Add support for oneplus-billie2 Iskren Chernev
13 siblings, 1 reply; 35+ messages in thread
From: Iskren Chernev @ 2022-09-01 7:24 UTC (permalink / raw)
To: Bjorn Andersson, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm,
devicetree, Iskren Chernev, Andy Gross, Konrad Dybcio,
Krzysztof Kozlowski, linux-kernel
oneplus,billie2 (OnePlus Nord N100) is based on QualComm Snapdragon
SM4250 SoC.
Add support for the same in dt-bindings.
Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
---
Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 19c2f4314741..63cc41cd0119 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -54,6 +54,8 @@ description: |
sdm845
sdx55
sdx65
+ sm4250
+ sm6115
sm6125
sm6350
sm7225
@@ -670,6 +672,11 @@ properties:
- xiaomi,polaris
- const: qcom,sdm845
+ - items:
+ - enum:
+ - oneplus,billie2
+ - const: qcom,sm4250
+
- items:
- enum:
- sony,pdx201
--
2.37.2
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 14/14] arm64: dts: qcom: sm4250: Add support for oneplus-billie2
[not found] <20220901072414.1923075-1-iskren.chernev@gmail.com>
` (12 preceding siblings ...)
2022-09-01 7:24 ` [PATCH 13/14] dt-bindings: arm: qcom: Add compatible for oneplus,billie2 phone Iskren Chernev
@ 2022-09-01 7:24 ` Iskren Chernev
2022-09-01 16:20 ` Krzysztof Kozlowski
13 siblings, 1 reply; 35+ messages in thread
From: Iskren Chernev @ 2022-09-01 7:24 UTC (permalink / raw)
To: Bjorn Andersson, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm,
devicetree, Iskren Chernev, Andy Gross, Konrad Dybcio,
Krzysztof Kozlowski, Kees Cook, Anton Vorontsov, Colin Cross,
Tony Luck, linux-kernel
Add initial support for OnePlus Nord N100, based on SM4250. Currently
working:
- boots
- usb
- buildin flash storage (UFS)
- SD card reader
Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
---
.../boot/dts/qcom/sm4250-oneplus-billie2.dts | 240 ++++++++++++++++++
1 file changed, 240 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts
diff --git a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts
new file mode 100644
index 000000000000..c1cf0288aa5f
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts
@@ -0,0 +1,240 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "sm4250.dtsi"
+
+/ {
+ model = "OnePlus Nord N100";
+ compatible = "oneplus,billie2", "qcom,sm4250";
+
+ /* required for bootloader to select correct board */
+ qcom,msm-id = <0x1a1 0x10000 0x1bc 0x10000>;
+ qcom,board-id = <0x1000b 0x00>;
+
+ aliases {
+ };
+
+ chosen {
+ bootargs = "earlycon=tty0 console=tty0 clk_ignore_unused pd_ignore_unused";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ stdout-path = "framebuffer0";
+
+ framebuffer0: framebuffer@9d400000 {
+ compatible = "simple-framebuffer";
+ reg = <0 0x5c000000 0 (1600 * 720 * 4)>;
+ width = <720>;
+ height = <1600>;
+ stride = <(720 * 4)>;
+ format = "a8r8g8b8";
+ status= "okay";
+ };
+ };
+
+ reserved-memory {
+ mtp_mem: memory@cc300000 {
+ reg = <0x00 0xcc300000 0x00 0xb00000>;
+ no-map;
+ };
+
+ param_mem: memory@cc200000 {
+ reg = <0x00 0xcc200000 0x00 0x100000>;
+ no-map;
+ };
+
+ bootloader_log_mem: memory@5fff7000 {
+ reg = <0x00 0x5fff7000 0x00 0x8000>;
+ no-map;
+ };
+
+ ramoops@cbe00000 {
+ compatible = "ramoops";
+ reg = <0x0 0xcbe00000 0x0 0x400000>;
+ record-size = <0x40000>;
+ pmsg-size = <0x200000>;
+ console-size = <0x40000>;
+ ftrace-size = <0x40000>;
+ };
+ };
+};
+
+&usb3 {
+ status = "okay";
+};
+
+&hsusb_phy {
+ status = "okay";
+ vdd-supply = <&vreg_l4a>;
+ vdda-pll-supply = <&vreg_l12a>;
+ vdda-phy-dpdm-supply = <&vreg_l15a>;
+
+};
+
+&tlmm {
+ gpio-reserved-ranges = <14 4>;
+};
+
+&sdhc_2 {
+ status = "okay";
+ vmmc-supply = <&vreg_l22a>;
+ vqmmc-supply = <&vreg_l5a>;
+
+ cd-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc2_state_on>;
+ pinctrl-1 = <&sdc2_state_off>;
+};
+
+&ufs_mem_hc {
+ status = "okay";
+ vcc-supply = <&vreg_l24a>;
+ vcc-max-microamp = <600000>;
+ vccq2-supply = <&vreg_l11a>;
+ vccq2-max-microamp = <600000>;
+};
+
+&ufs_mem_phy {
+ status = "okay";
+ vdda-phy-supply = <&vreg_l4a>;
+ vdda-pll-supply = <&vreg_l12a>;
+ vddp-ref-clk-supply = <&vreg_l18a>;
+};
+
+&rpm_requests {
+ pm6125-regulators {
+ compatible = "qcom,rpm-pm6125-regulators";
+
+ vreg_s6a: s6 {
+ regulator-min-microvolt = <320000>;
+ regulator-max-microvolt = <1456000>;
+ };
+
+ vreg_s7a: s7 {
+ regulator-min-microvolt = <1280000>;
+ regulator-max-microvolt = <2040000>;
+ };
+
+ vreg_s8a: s8 {
+ regulator-min-microvolt = <1064000>;
+ regulator-max-microvolt = <1304000>;
+ };
+
+ vreg_l1a: l1 {
+ regulator-min-microvolt = <952000>;
+ regulator-max-microvolt = <1152000>;
+ };
+
+ vreg_l4a: l4 {
+ regulator-min-microvolt = <488000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ vreg_l5a: l5 {
+ regulator-min-microvolt = <1648000>;
+ regulator-max-microvolt = <3056000>;
+ };
+
+ vreg_l6a: l6 {
+ regulator-min-microvolt = <576000>;
+ regulator-max-microvolt = <656000>;
+ };
+
+ vreg_l7a: l7 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1304000>;
+ };
+
+ vreg_l8a: l8 {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <728000>;
+ };
+
+ vreg_l9a: l9 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ };
+
+ vreg_l10a: l10 {
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <1904000>;
+ };
+
+ vreg_l11a: l11 {
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <1952000>;
+ };
+
+ vreg_l12a: l12 {
+ regulator-min-microvolt = <1624000>;
+ regulator-max-microvolt = <1984000>;
+ };
+
+ vreg_l13a: l13 {
+ regulator-min-microvolt = <1504000>;
+ regulator-max-microvolt = <1952000>;
+ };
+
+ vreg_l14a: l14 {
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <1904000>;
+ };
+
+ vreg_l15a: l15 {
+ regulator-min-microvolt = <2920000>;
+ regulator-max-microvolt = <3232000>;
+ };
+
+ vreg_l16a: l16 {
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <1904000>;
+ };
+
+ vreg_l17a: l17 {
+ regulator-min-microvolt = <1152000>;
+ regulator-max-microvolt = <1304000>;
+ };
+
+ vreg_l18a: l18 {
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1304000>;
+ };
+
+ vreg_l19a: l19 {
+ regulator-min-microvolt = <1624000>;
+ regulator-max-microvolt = <3304000>;
+ };
+
+ vreg_l20a: l20 {
+ regulator-min-microvolt = <1624000>;
+ regulator-max-microvolt = <3304000>;
+ };
+
+ vreg_l21a: l21 {
+ regulator-min-microvolt = <2400000>;
+ regulator-max-microvolt = <3544000>;
+ };
+
+ vreg_l22a: l22 {
+ regulator-min-microvolt = <2952000>;
+ regulator-max-microvolt = <3304000>;
+ };
+
+ vreg_l23a: l23 {
+ regulator-min-microvolt = <3296000>;
+ regulator-max-microvolt = <3304000>;
+ };
+
+ vreg_l24a: l24 {
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <3544000>;
+ };
+ };
+};
--
2.37.2
^ permalink raw reply related [flat|nested] 35+ messages in thread
* Re: [PATCH 11/14] dt-bindings: arm: cpus: Add kryo240 compatible
2022-09-01 7:24 ` [PATCH 11/14] dt-bindings: arm: cpus: Add kryo240 compatible Iskren Chernev
@ 2022-09-01 15:29 ` Vinod Koul
2022-09-01 16:14 ` Krzysztof Kozlowski
1 sibling, 0 replies; 35+ messages in thread
From: Vinod Koul @ 2022-09-01 15:29 UTC (permalink / raw)
To: Iskren Chernev
Cc: Bjorn Andersson, Rob Herring, phone-devel,
~postmarketos/upstreaming, linux-arm-msm, devicetree,
Krzysztof Kozlowski, Robin Murphy, Stephan Gerhold, Luca Weiss,
Maxime Ripard, Bartosz Dudziak, Lorenzo Pieralisi, linux-kernel
On 01-09-22, 10:24, Iskren Chernev wrote:
> Kryo240 is found in SM4250, the slower sibling of the SM6115.
Reviewed-by: Vinod Koul <vkoul@kernel.org>
--
~Vinod
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 01/14] arm64: dts: qcom: sm6115: Add basic soc dtsi
2022-09-01 7:24 ` [PATCH 01/14] arm64: dts: qcom: sm6115: Add basic soc dtsi Iskren Chernev
@ 2022-09-01 16:03 ` Krzysztof Kozlowski
0 siblings, 0 replies; 35+ messages in thread
From: Krzysztof Kozlowski @ 2022-09-01 16:03 UTC (permalink / raw)
To: Iskren Chernev, Bjorn Andersson, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm,
devicetree, Andy Gross, Konrad Dybcio, Krzysztof Kozlowski,
linux-kernel
On 01/09/2022 10:24, Iskren Chernev wrote:
> Add support for Qualcomm SM6115 SoC. This includes bare minimum:
> - CPUs
> - intc
> - timer
> - reserved memory
>
> Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
> ---
> arch/arm64/boot/dts/qcom/sm6115.dtsi | 433 +++++++++++++++++++++++++++
> 1 file changed, 433 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/sm6115.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
> new file mode 100644
> index 000000000000..69d9de540478
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
> @@ -0,0 +1,433 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com>
> + */
> +
> +#include <dt-bindings/clock/qcom,gcc-sm6115.h>
> +#include <dt-bindings/clock/qcom,rpmcc.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/power/qcom-rpmpd.h>
> +
> +/ {
> + interrupt-parent = <&intc>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + chosen { };
> +
> + clocks {
> + xo_board: xo-board {
> + compatible = "fixed-clock";
> + clock-frequency = <19200000>;
The clocks are outside of the SoC, so usually to denote it the clock
frequencies are at least defined in the board DTS. Move it there.
> + #clock-cells = <0>;
> + clock-output-names = "xo_board";
> + };
> +
> + sleep_clk: sleep-clk {
> + compatible = "fixed-clock";
> + clock-frequency = <32764>;
> + #clock-cells = <0>;
> + clock-output-names = "sleep_clk";
> + };
> + };
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + CPU0: cpu@0 {
> + device_type = "cpu";
> + compatible = "qcom,kryo260";
> + reg = <0x0 0x0>;
> + capacity-dmips-mhz = <1024>;
> + dynamic-power-coefficient = <100>;
> + enable-method = "psci";
> + next-level-cache = <&L2_0>;
> + L2_0: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + };
> + };
> +
> + CPU1: cpu@1 {
> + device_type = "cpu";
> + compatible = "qcom,kryo260";
> + reg = <0x0 0x1>;
> + capacity-dmips-mhz = <1024>;
> + dynamic-power-coefficient = <100>;
> + enable-method = "psci";
> + next-level-cache = <&L2_0>;
> + };
> +
> + CPU2: cpu@2 {
> + device_type = "cpu";
> + compatible = "qcom,kryo260";
> + reg = <0x0 0x2>;
> + capacity-dmips-mhz = <1024>;
> + dynamic-power-coefficient = <100>;
> + enable-method = "psci";
> + next-level-cache = <&L2_0>;
> + };
> +
> + CPU3: cpu@3 {
> + device_type = "cpu";
> + compatible = "qcom,kryo260";
> + reg = <0x0 0x3>;
> + capacity-dmips-mhz = <1024>;
> + dynamic-power-coefficient = <100>;
> + enable-method = "psci";
> + next-level-cache = <&L2_0>;
> + };
> +
> + CPU4: cpu@100 {
> + device_type = "cpu";
> + compatible = "qcom,kryo260";
> + reg = <0x0 0x100>;
> + enable-method = "psci";
> + capacity-dmips-mhz = <1638>;
> + dynamic-power-coefficient = <282>;
> + next-level-cache = <&L2_1>;
> + L2_1: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + };
> + };
> +
> + CPU5: cpu@101 {
> + device_type = "cpu";
> + compatible = "qcom,kryo260";
> + reg = <0x0 0x101>;
> + capacity-dmips-mhz = <1638>;
> + dynamic-power-coefficient = <282>;
> + enable-method = "psci";
> + next-level-cache = <&L2_1>;
> + };
> +
> + CPU6: cpu@102 {
> + device_type = "cpu";
> + compatible = "qcom,kryo260";
> + reg = <0x0 0x102>;
> + capacity-dmips-mhz = <1638>;
> + dynamic-power-coefficient = <282>;
> + enable-method = "psci";
> + next-level-cache = <&L2_1>;
> + };
> +
> + CPU7: cpu@103 {
> + device_type = "cpu";
> + compatible = "qcom,kryo260";
> + reg = <0x0 0x103>;
> + capacity-dmips-mhz = <1638>;
> + dynamic-power-coefficient = <282>;
> + enable-method = "psci";
> + next-level-cache = <&L2_1>;
> + };
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&CPU0>;
> + };
> +
> + core1 {
> + cpu = <&CPU1>;
> + };
> +
> + core2 {
> + cpu = <&CPU2>;
> + };
> +
> + core3 {
> + cpu = <&CPU3>;
> + };
> + };
> +
> + cluster1 {
> + core0 {
> + cpu = <&CPU4>;
> + };
> +
> + core1 {
> + cpu = <&CPU5>;
> + };
> +
> + core2 {
> + cpu = <&CPU6>;
> + };
> +
> + core3 {
> + cpu = <&CPU7>;
> + };
> + };
> + };
> + };
> +
> + firmware {
> + scm: scm {
> + compatible = "qcom,scm-sm6115", "qcom,scm";
> + #reset-cells = <1>;
> + };
> + };
> +
> + tcsr_mutex: hwlock {
> + compatible = "qcom,tcsr-mutex";
> + syscon = <&tcsr_mutex_regs 0 0x1000>;
> + #hwlock-cells = <1>;
> + };
This should be rather MMIO based TCSR mutex.
See:
https://lore.kernel.org/all/20220819083209.50844-1-krzysztof.kozlowski@linaro.org/
> +
> + memory {
> + device_type = "memory";
> + /* We expect the bootloader to fill in the reg */
> + reg = <0 0 0 0>;
> + };
> +
> + pmu {
> + compatible = "arm,armv8-pmuv3";
> + interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + hyp_mem: memory@45700000 {
> + reg = <0x0 0x45700000 0x0 0x600000>;
> + no-map;
> + };
> +
> + xbl_aop_mem: memory@45e00000 {
> + reg = <0x0 0x45e00000 0x0 0x140000>;
> + no-map;
> + };
> +
> + sec_apps_mem: memory@45fff000 {
> + reg = <0x0 0x45fff000 0x0 0x1000>;
> + no-map;
> + };
> +
> + smem_mem: memory@46000000 {
> + reg = <0x0 0x46000000 0x0 0x200000>;
> + no-map;
> + };
> +
> + cdsp_sec_mem: memory@46200000 {
> + reg = <0x0 0x46200000 0x0 0x1e00000>;
> + no-map;
> + };
> +
> + pil_modem_mem: memory@4ab00000 {
> + reg = <0x0 0x4ab00000 0x0 0x6900000>;
> + no-map;
> + };
> +
> + pil_video_mem: memory@51400000 {
> + reg = <0x0 0x51400000 0x0 0x500000>;
> + no-map;
> + };
> +
> + wlan_msa_mem: memory@51900000 {
> + reg = <0x0 0x51900000 0x0 0x100000>;
> + no-map;
> + };
> +
> + pil_cdsp_mem: memory@51a00000 {
> + reg = <0x0 0x51a00000 0x0 0x1e00000>;
> + no-map;
> + };
> +
> + pil_adsp_mem: memory@53800000 {
> + reg = <0x0 0x53800000 0x0 0x2800000>;
> + no-map;
> + };
> +
> + pil_ipa_fw_mem: memory@56100000 {
> + reg = <0x0 0x56100000 0x0 0x10000>;
> + no-map;
> + };
> +
> + pil_ipa_gsi_mem: memory@56110000 {
> + reg = <0x0 0x56110000 0x0 0x5000>;
> + no-map;
> + };
> +
> + pil_gpu_mem: memory@56115000 {
> + reg = <0x0 0x56115000 0x0 0x2000>;
> + no-map;
> + };
> +
> + cont_splash_memory: memory@5c000000 {
> + reg = <0x0 0x5c000000 0x0 0x00f00000>;
> + no-map;
> + };
> +
> + dfps_data_memory: memory@5cf00000 {
> + reg = <0x0 0x5cf00000 0x0 0x0100000>;
> + no-map;
> + };
> +
> + removed_mem: memory@60000000 {
> + reg = <0x0 0x60000000 0x0 0x3900000>;
> + no-map;
> + };
> +
> + secure_display_memory: memory@f3c00000 {
> + reg = <0x0 0xf3c00000 0x0 0x5c00000>;
> + no-map;
> + };
> +
> + dump_mem: memory@f9800000 {
> + reg = <0x0 0xf9800000 0x0 0x800000>;
> + no-map;
> + };
> +
> + adsp_mem: memory@fa000000 {
> + reg = <0x0 0xfa000000 0x0 0x800000>;
> + no-map;
> + };
> +
> + qseecom_mem: memory@fa800000 {
> + reg = <0x0 0xfa800000 0x0 0x1400000>;
> + no-map;
> + };
> +
> + user_contig_mem: memory@fbc00000 {
> + reg = <0x0 0xfbc00000 0x0 0x1000000>;
> + no-map;
> + };
> +
> + qseecom_ta_mem: memory@fcc00000 {
> + reg = <0x0 0xfcc00000 0x0 0x1000000>;
> + no-map;
> + };
> +
> + linux_cma_mem: memory@fdc00000 {
> + reg = <0x0 0xfdc00000 0x0 0x2000000>;
> + no-map;
> + };
> +
> + };
> +
> + smem {
> + compatible = "qcom,smem";
> + memory-region = <&smem_mem>;
> + qcom,rpm-msg-ram = <&rpm_msg_ram>;
> + hwlocks = <&tcsr_mutex 3>;
> + };
> +
> + soc: soc {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0 0xffffffff>;
> +
> + qfprom@1b40000 {
> + compatible = "qcom,qfprom";
Does not look like you tested the DTS against bindings. Please run `make
dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst
for instructions).
> + reg = <0x1b40000 0x7000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + qusb2_hstx_trim: hstx_trim@25b {
No underscores in node names.
> + reg = <0x25b 0x1>;
> + bits = <1 4>;
> + };
> + };
> +
> + tcsr_mutex_regs: syscon@1f40000 {
> + compatible = "syscon";
syscon is not allowed on its own. Use MMIO method (see my other patchset
I linked above)
> + reg = <0x340000 0x20000>;
> + };
> +
> + rpm_msg_ram: memory@45f0000 {
Does not look like you tested the DTS against bindings. Please run `make
dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst
for instructions).
> + compatible = "qcom,rpm-msg-ram";
> + reg = <0x45f0000 0x7000>;
> + };
> +
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 03/14] arm64: dts: qcom: sm6115: Add GCC node
2022-09-01 7:24 ` [PATCH 03/14] arm64: dts: qcom: sm6115: Add GCC node Iskren Chernev
@ 2022-09-01 16:05 ` Krzysztof Kozlowski
0 siblings, 0 replies; 35+ messages in thread
From: Krzysztof Kozlowski @ 2022-09-01 16:05 UTC (permalink / raw)
To: Iskren Chernev, Bjorn Andersson, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm,
devicetree, Andy Gross, Konrad Dybcio, Krzysztof Kozlowski,
linux-kernel
On 01/09/2022 10:24, Iskren Chernev wrote:
> Add support for the main clock bundle on the SM6115.
>
> Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
> ---
> arch/arm64/boot/dts/qcom/sm6115.dtsi | 11 +++++++++++
> 1 file changed, 11 insertions(+)
This needs squashing, because one patchset per device node on first
submission does not make sense.
Please squash all your 1-7, 8-10 patches.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 05/14] arm64: dts: qcom: sm6115: Add apps smmu node
2022-09-01 7:24 ` [PATCH 05/14] arm64: dts: qcom: sm6115: Add apps smmu node Iskren Chernev
@ 2022-09-01 16:05 ` Krzysztof Kozlowski
0 siblings, 0 replies; 35+ messages in thread
From: Krzysztof Kozlowski @ 2022-09-01 16:05 UTC (permalink / raw)
To: Iskren Chernev, Bjorn Andersson, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm,
devicetree, Andy Gross, Konrad Dybcio, Krzysztof Kozlowski,
linux-kernel
On 01/09/2022 10:24, Iskren Chernev wrote:
> Add support for apps smmu (one of the two smmus) present on the SM6115.
>
> Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
> ---
> arch/arm64/boot/dts/qcom/sm6115.dtsi | 73 ++++++++++++++++++++++++++++
> 1 file changed, 73 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
> index efbc81d2253b..a6be8b93a44d 100644
> --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
> @@ -434,6 +434,79 @@ rpm_msg_ram: memory@45f0000 {
> reg = <0x45f0000 0x7000>;
> };
>
> + apps_smmu: iommu@c600000 {
> + compatible = "qcom,sm6115-smmu-500", "arm,mmu-500";
> + reg = <0xc600000 0x80000>;
> + #iommu-cells = <2>;
> + #global-interrupts = <1>;
> +
> + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
One space after =
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 06/14] arm64: dts: qcom: sm6115: Add usb and related phy nodes
2022-09-01 7:24 ` [PATCH 06/14] arm64: dts: qcom: sm6115: Add usb and related phy nodes Iskren Chernev
@ 2022-09-01 16:06 ` Krzysztof Kozlowski
0 siblings, 0 replies; 35+ messages in thread
From: Krzysztof Kozlowski @ 2022-09-01 16:06 UTC (permalink / raw)
To: Iskren Chernev, Bjorn Andersson, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm,
devicetree, Andy Gross, Konrad Dybcio, Krzysztof Kozlowski,
linux-kernel
On 01/09/2022 10:24, Iskren Chernev wrote:
> Add support for the USB controller and its HS PHY to SM6115.
>
> Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
> ---
> arch/arm64/boot/dts/qcom/sm6115.dtsi | 62 ++++++++++++++++++++++++++++
> 1 file changed, 62 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
> index a6be8b93a44d..00fd185c87aa 100644
> --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
> @@ -412,6 +412,21 @@ gcc: clock-controller@1400000 {
> #power-domain-cells = <1>;
> };
>
> + hsusb_phy: phy@1613000 {
> + compatible = "qcom,sm6115-qusb2-phy";
> + reg = <0x1613000 0x180>;
> + #phy-cells = <0>;
> +
> + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
> + <&gcc GCC_AHB2PHY_USB_CLK>;
> + clock-names = "ref", "cfg_ahb";
> +
> + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
> + nvmem-cells = <&qusb2_hstx_trim>;
> +
> + status = "disabled";
> + };
> +
> qfprom@1b40000 {
> compatible = "qcom,qfprom";
> reg = <0x1b40000 0x7000>;
> @@ -434,6 +449,53 @@ rpm_msg_ram: memory@45f0000 {
> reg = <0x45f0000 0x7000>;
> };
>
> + usb3: usb@4ef8800 {
> + compatible = "qcom,sm6115-dwc3", "qcom,dwc3";
> + reg = <0x04ef8800 0x400>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
> + <&gcc GCC_USB30_PRIM_MASTER_CLK>,
> + <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
> + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
> + <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
> + <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
> + clock-names = "cfg_noc", "core", "iface", "mock_utmi",
> + "sleep", "xo";
> +
> + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
> + <&gcc GCC_USB30_PRIM_MASTER_CLK>;
> + assigned-clock-rates = <19200000>, <66666667>;
> +
> + interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hs_phy_irq", "ss_phy_irq";
> +
> + resets = <&gcc GCC_USB30_PRIM_BCR>;
> + power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
> + qcom,select-utmi-as-pipe-clk;
> + status = "disabled";
> +
> + usb3_dwc3: dwc3@4e00000 {
Node name: usb
Does not look like you tested the DTS against bindings. Please run `make
dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst
for instructions).
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 07/14] arm64: dts: qcom: sm6115: Add sdhci nodes and related pinctrl
2022-09-01 7:24 ` [PATCH 07/14] arm64: dts: qcom: sm6115: Add sdhci nodes and related pinctrl Iskren Chernev
@ 2022-09-01 16:08 ` Krzysztof Kozlowski
0 siblings, 0 replies; 35+ messages in thread
From: Krzysztof Kozlowski @ 2022-09-01 16:08 UTC (permalink / raw)
To: Iskren Chernev, Bjorn Andersson, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm,
devicetree, Andy Gross, Konrad Dybcio, Krzysztof Kozlowski,
linux-kernel
On 01/09/2022 10:24, Iskren Chernev wrote:
> Add support for the two sdhci's present on the SM6115 and the related
> pinctrl.
>
>
> gcc: clock-controller@1400000 {
> @@ -449,6 +553,73 @@ rpm_msg_ram: memory@45f0000 {
> reg = <0x45f0000 0x7000>;
> };
>
> + sdhc_1: sdhci@4744000 {
> + compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5";
> + reg = <0x4744000 0x1000>, <0x4745000 0x1000>, <0x4748000 0x8000>;
> + reg-names = "hc", "cqhci", "ice";
> +
> + interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hc_irq", "pwr_irq";
> +
> + clocks = <&gcc GCC_SDCC1_AHB_CLK>,
> + <&gcc GCC_SDCC1_APPS_CLK>,
> + <&xo_board>,
> + <&gcc GCC_SDCC1_ICE_CORE_CLK>;
> + clock-names = "iface", "core", "xo", "ice_core_clk";
Does not look like you tested the DTS against bindings. Please run `make
dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst
for instructions).
> +
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 08/14] dt-bindings: ufs: qcom: Add sm6115 binding
2022-09-01 7:24 ` [PATCH 08/14] dt-bindings: ufs: qcom: Add sm6115 binding Iskren Chernev
@ 2022-09-01 16:11 ` Krzysztof Kozlowski
2022-09-03 16:54 ` Iskren Chernev
0 siblings, 1 reply; 35+ messages in thread
From: Krzysztof Kozlowski @ 2022-09-01 16:11 UTC (permalink / raw)
To: Iskren Chernev, Bjorn Andersson, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm,
devicetree, Andy Gross, Konrad Dybcio, Alim Akhtar, Avri Altman,
Bart Van Assche, Krzysztof Kozlowski, linux-scsi, linux-kernel
On 01/09/2022 10:24, Iskren Chernev wrote:
> Add SM6115 UFS to DT schema.
>
> Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
> ---
> .../devicetree/bindings/ufs/qcom,ufs.yaml | 26 +++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
> index f2d6298d926c..7c5f6e2e6d4c 100644
> --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
> +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
> @@ -28,6 +28,7 @@ properties:
> - qcom,msm8998-ufshc
> - qcom,sc8280xp-ufshc
> - qcom,sdm845-ufshc
> + - qcom,sm6115-ufshc
> - qcom,sm6350-ufshc
> - qcom,sm8150-ufshc
> - qcom,sm8250-ufshc
> @@ -178,6 +179,31 @@ allOf:
> minItems: 1
> maxItems: 1
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,sm6115-ufshc
> + then:
> + properties:
> + clocks:
> + minItems: 8
> + maxItems: 8
> + clock-names:
> + items:
> + - const: core_clk
> + - const: bus_aggr_clk
> + - const: iface_clk
> + - const: core_clk_unipro
> + - const: core_clk_ice
Use existing name and put it in the same place as existing variant - sdm845:
ice_core_clk
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 09/14] arm64: dts: qcom: sm6115: Add UFS nodes
2022-09-01 7:24 ` [PATCH 09/14] arm64: dts: qcom: sm6115: Add UFS nodes Iskren Chernev
@ 2022-09-01 16:13 ` Krzysztof Kozlowski
2022-09-03 17:04 ` Iskren Chernev
0 siblings, 1 reply; 35+ messages in thread
From: Krzysztof Kozlowski @ 2022-09-01 16:13 UTC (permalink / raw)
To: Iskren Chernev, Bjorn Andersson, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm,
devicetree, Andy Gross, Konrad Dybcio, Krzysztof Kozlowski,
linux-kernel
On 01/09/2022 10:24, Iskren Chernev wrote:
> The SM6115 comes with UFS support, so add the related UFS and UFS PHY
> nodes.
>
> Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
> ---
> arch/arm64/boot/dts/qcom/sm6115.dtsi | 70 ++++++++++++++++++++++++++++
> 1 file changed, 70 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
> index cde963c56ac9..491fffff8aa1 100644
> --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
> @@ -620,6 +620,76 @@ opp-202000000 {
> };
> };
>
> + ufs_mem_hc: ufshc@4804000 {
> + compatible = "qcom,sm6115-ufshc", "qcom,ufshc",
> + "jedec,ufs-2.0";
> + reg = <0x4804000 0x3000>, <0x4810000 0x8000>;
> + reg-names = "std", "ice";
I could imagine that testing DTS against existing bindings might miss a
lot, because we have still a lot of errors. But at least I would expect
you test your DTS against your own bindings, which you submit here (and
previously).
You just wrote that ice is not allowed.
> + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&ufs_mem_phy_lanes>;
> + phy-names = "ufsphy";
> + lanes-per-direction = <1>;
> + #reset-cells = <1>;
> + resets = <&gcc GCC_UFS_PHY_BCR>;
> + reset-names = "rst";
> +
> + power-domains = <&gcc GCC_UFS_PHY_GDSC>;
> + iommus = <&apps_smmu 0x100 0>;
> +
> + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
> + <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
> + <&gcc GCC_UFS_PHY_AHB_CLK>,
> + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
> + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
> + <&rpmcc RPM_SMD_XO_CLK_SRC>,
> + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
> + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;
> + clock-names = "core_clk",
> + "bus_aggr_clk",
> + "iface_clk",
> + "core_clk_unipro",
> + "core_clk_ice",
> + "ref_clk",
> + "tx_lane0_sync_clk",
> + "rx_lane0_sync_clk";
> +
> + freq-table-hz = <50000000 200000000>,
> + <0 0>,
> + <0 0>,
> + <37500000 150000000>,
> + <75000000 300000000>,
> + <0 0>,
> + <0 0>,
> + <0 0>;
> +
> + non-removable;
Is it allowed property?
> + status = "disabled";
> + };
> +
> + ufs_mem_phy: phy@4807000 {
> + compatible = "qcom,sm6115-qmp-ufs-phy";
> + reg = <0x4807000 0x1c4>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + clocks = <&gcc GCC_UFS_CLKREF_CLK>,
> + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
> + clock-names = "ref", "ref_aux";
> +
> + resets = <&ufs_mem_hc 0>;
> + reset-names = "ufsphy";
> + status = "disabled";
> +
> + ufs_mem_phy_lanes: lanes@4807400 {
> + reg = <0x4807400 0x098>,
> + <0x4807600 0x130>,
> + <0x4807c00 0x16c>;
> + #phy-cells = <0>;
> + };
> + };
> +
> +
Just one blank line.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 10/14] arm64: dts: qcom: sm6115: Add SPMI bus node
2022-09-01 7:24 ` [PATCH 10/14] arm64: dts: qcom: sm6115: Add SPMI bus node Iskren Chernev
@ 2022-09-01 16:14 ` Krzysztof Kozlowski
0 siblings, 0 replies; 35+ messages in thread
From: Krzysztof Kozlowski @ 2022-09-01 16:14 UTC (permalink / raw)
To: Iskren Chernev, Bjorn Andersson, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm,
devicetree, Andy Gross, Konrad Dybcio, Krzysztof Kozlowski,
linux-kernel
On 01/09/2022 10:24, Iskren Chernev wrote:
> Add support for the SPMI bus on the SM6115.
>
> Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
> ---
> arch/arm64/boot/dts/qcom/sm6115.dtsi | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
> index 491fffff8aa1..d578f8425e36 100644
> --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
> @@ -543,6 +543,25 @@ qusb2_hstx_trim: hstx_trim@25b {
> };
> };
>
> + spmi_bus: qcom,spmi@1c40000 {
Node names should be generic.
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
This is spmi.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 11/14] dt-bindings: arm: cpus: Add kryo240 compatible
2022-09-01 7:24 ` [PATCH 11/14] dt-bindings: arm: cpus: Add kryo240 compatible Iskren Chernev
2022-09-01 15:29 ` Vinod Koul
@ 2022-09-01 16:14 ` Krzysztof Kozlowski
1 sibling, 0 replies; 35+ messages in thread
From: Krzysztof Kozlowski @ 2022-09-01 16:14 UTC (permalink / raw)
To: Iskren Chernev, Bjorn Andersson, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm,
devicetree, Krzysztof Kozlowski, Vinod Koul, Robin Murphy,
Stephan Gerhold, Luca Weiss, Maxime Ripard, Bartosz Dudziak,
Lorenzo Pieralisi, linux-kernel
On 01/09/2022 10:24, Iskren Chernev wrote:
> Kryo240 is found in SM4250, the slower sibling of the SM6115.
>
> Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
> ---
> Documentation/devicetree/bindings/arm/cpus.yaml | 1 +
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 13/14] dt-bindings: arm: qcom: Add compatible for oneplus,billie2 phone
2022-09-01 7:24 ` [PATCH 13/14] dt-bindings: arm: qcom: Add compatible for oneplus,billie2 phone Iskren Chernev
@ 2022-09-01 16:17 ` Krzysztof Kozlowski
0 siblings, 0 replies; 35+ messages in thread
From: Krzysztof Kozlowski @ 2022-09-01 16:17 UTC (permalink / raw)
To: Iskren Chernev, Bjorn Andersson, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm,
devicetree, Andy Gross, Konrad Dybcio, Krzysztof Kozlowski,
linux-kernel
On 01/09/2022 10:24, Iskren Chernev wrote:
> oneplus,billie2 (OnePlus Nord N100) is based on QualComm Snapdragon
> SM4250 SoC.
>
> Add support for the same in dt-bindings.
>
> Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Bjorn,
Can we get top-level schemas merged?
https://lore.kernel.org/all/20220830065744.161163-1-krzysztof.kozlowski@linaro.org/
https://lore.kernel.org/all/20220720073326.19591-1-krzysztof.kozlowski@linaro.org/
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 14/14] arm64: dts: qcom: sm4250: Add support for oneplus-billie2
2022-09-01 7:24 ` [PATCH 14/14] arm64: dts: qcom: sm4250: Add support for oneplus-billie2 Iskren Chernev
@ 2022-09-01 16:20 ` Krzysztof Kozlowski
2022-09-03 12:32 ` Konrad Dybcio
0 siblings, 1 reply; 35+ messages in thread
From: Krzysztof Kozlowski @ 2022-09-01 16:20 UTC (permalink / raw)
To: Iskren Chernev, Bjorn Andersson, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm,
devicetree, Andy Gross, Konrad Dybcio, Krzysztof Kozlowski,
Kees Cook, Anton Vorontsov, Colin Cross, Tony Luck, linux-kernel
On 01/09/2022 10:24, Iskren Chernev wrote:
> Add initial support for OnePlus Nord N100, based on SM4250. Currently
> working:
> - boots
> - usb
> - buildin flash storage (UFS)
> - SD card reader
>
> Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
> ---
> .../boot/dts/qcom/sm4250-oneplus-billie2.dts | 240 ++++++++++++++++++
> 1 file changed, 240 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts
>
> diff --git a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts
> new file mode 100644
> index 000000000000..c1cf0288aa5f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts
> @@ -0,0 +1,240 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com>
> + */
> +
> +/dts-v1/;
> +
> +#include "sm4250.dtsi"
> +
> +/ {
> + model = "OnePlus Nord N100";
> + compatible = "oneplus,billie2", "qcom,sm4250";
> +
> + /* required for bootloader to select correct board */
> + qcom,msm-id = <0x1a1 0x10000 0x1bc 0x10000>;
> + qcom,board-id = <0x1000b 0x00>;
> +
> + aliases {
> + };
> +
> + chosen {
> + bootargs = "earlycon=tty0 console=tty0 clk_ignore_unused pd_ignore_unused";
No bootargs. They are not suitable for wide-use.
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + stdout-path = "framebuffer0";
> +
> + framebuffer0: framebuffer@9d400000 {
> + compatible = "simple-framebuffer";
> + reg = <0 0x5c000000 0 (1600 * 720 * 4)>;
> + width = <720>;
> + height = <1600>;
> + stride = <(720 * 4)>;
> + format = "a8r8g8b8";
> + status= "okay";
No need for status in new nodes.
> + };
> + };
> +
> + reserved-memory {
> + mtp_mem: memory@cc300000 {
> + reg = <0x00 0xcc300000 0x00 0xb00000>;
> + no-map;
> + };
> +
> + param_mem: memory@cc200000 {
> + reg = <0x00 0xcc200000 0x00 0x100000>;
> + no-map;
> + };
> +
> + bootloader_log_mem: memory@5fff7000 {
> + reg = <0x00 0x5fff7000 0x00 0x8000>;
> + no-map;
> + };
> +
> + ramoops@cbe00000 {
> + compatible = "ramoops";
> + reg = <0x0 0xcbe00000 0x0 0x400000>;
> + record-size = <0x40000>;
> + pmsg-size = <0x200000>;
> + console-size = <0x40000>;
> + ftrace-size = <0x40000>;
> + };
> + };
> +};
> +
> +&usb3 {
> + status = "okay";
> +};
> +
> +&hsusb_phy {
> + status = "okay";
Status is the last property. Also in other places.
> + vdd-supply = <&vreg_l4a>;
> + vdda-pll-supply = <&vreg_l12a>;
> + vdda-phy-dpdm-supply = <&vreg_l15a>;
> +
> +};
> +
> +&tlmm {
> + gpio-reserved-ranges = <14 4>;
> +};
> +
> +&sdhc_2 {
> + status = "okay";
> + vmmc-supply = <&vreg_l22a>;
> + vqmmc-supply = <&vreg_l5a>;
> +
> + cd-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>;
> +
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&sdc2_state_on>;
> + pinctrl-1 = <&sdc2_state_off>;
> +};
> +
> +&ufs_mem_hc {
> + status = "okay";
> + vcc-supply = <&vreg_l24a>;
> + vcc-max-microamp = <600000>;
> + vccq2-supply = <&vreg_l11a>;
> + vccq2-max-microamp = <600000>;
> +};
> +
> +&ufs_mem_phy {
> + status = "okay";
> + vdda-phy-supply = <&vreg_l4a>;
> + vdda-pll-supply = <&vreg_l12a>;
> + vddp-ref-clk-supply = <&vreg_l18a>;
> +};
> +
> +&rpm_requests {
> + pm6125-regulators {
regulators
> + compatible = "qcom,rpm-pm6125-regulators";
> +
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 14/14] arm64: dts: qcom: sm4250: Add support for oneplus-billie2
2022-09-01 16:20 ` Krzysztof Kozlowski
@ 2022-09-03 12:32 ` Konrad Dybcio
0 siblings, 0 replies; 35+ messages in thread
From: Konrad Dybcio @ 2022-09-03 12:32 UTC (permalink / raw)
To: Krzysztof Kozlowski, Iskren Chernev, Bjorn Andersson, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm,
devicetree, Andy Gross, Krzysztof Kozlowski, Kees Cook,
Anton Vorontsov, Colin Cross, Tony Luck, linux-kernel
On 1.09.2022 18:20, Krzysztof Kozlowski wrote:
> On 01/09/2022 10:24, Iskren Chernev wrote:
>> Add initial support for OnePlus Nord N100, based on SM4250. Currently
>> working:
>> - boots
>> - usb
>> - buildin flash storage (UFS)
>> - SD card reader
>>
>> Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
>> ---
>> .../boot/dts/qcom/sm4250-oneplus-billie2.dts | 240 ++++++++++++++++++
>> 1 file changed, 240 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts
>> new file mode 100644
>> index 000000000000..c1cf0288aa5f
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts
>> @@ -0,0 +1,240 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com>
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "sm4250.dtsi"
>> +
>> +/ {
>> + model = "OnePlus Nord N100";
>> + compatible = "oneplus,billie2", "qcom,sm4250";
>> +
>> + /* required for bootloader to select correct board */
>> + qcom,msm-id = <0x1a1 0x10000 0x1bc 0x10000>;
>> + qcom,board-id = <0x1000b 0x00>;
>> +
>> + aliases {
>> + };
>> +
>> + chosen {
>> + bootargs = "earlycon=tty0 console=tty0 clk_ignore_unused pd_ignore_unused";
>
> No bootargs. They are not suitable for wide-use.
Agreed, the problem here is probably the framebuffer dying after our clock controllers probe.
One can solve that by adding the relevant clocks/PDs under the framebuffer node like I did
in sm8[123]50 Xperia DTs.
Konrad
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 08/14] dt-bindings: ufs: qcom: Add sm6115 binding
2022-09-01 16:11 ` Krzysztof Kozlowski
@ 2022-09-03 16:54 ` Iskren Chernev
2022-09-04 19:10 ` Krzysztof Kozlowski
0 siblings, 1 reply; 35+ messages in thread
From: Iskren Chernev @ 2022-09-03 16:54 UTC (permalink / raw)
To: Krzysztof Kozlowski, Bjorn Andersson, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm,
devicetree, Andy Gross, Konrad Dybcio, Alim Akhtar, Avri Altman,
Bart Van Assche, Krzysztof Kozlowski, linux-scsi, linux-kernel
On 9/1/22 19:11, Krzysztof Kozlowski wrote:
> On 01/09/2022 10:24, Iskren Chernev wrote:
>> Add SM6115 UFS to DT schema.
>>
>> Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
>> ---
>> .../devicetree/bindings/ufs/qcom,ufs.yaml | 26 +++++++++++++++++++
>> 1 file changed, 26 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
>> index f2d6298d926c..7c5f6e2e6d4c 100644
>> --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
>> +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
>> @@ -28,6 +28,7 @@ properties:
>> - qcom,msm8998-ufshc
>> - qcom,sc8280xp-ufshc
>> - qcom,sdm845-ufshc
>> + - qcom,sm6115-ufshc
>> - qcom,sm6350-ufshc
>> - qcom,sm8150-ufshc
>> - qcom,sm8250-ufshc
>> @@ -178,6 +179,31 @@ allOf:
>> minItems: 1
>> maxItems: 1
>>
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + enum:
>> + - qcom,sm6115-ufshc
>> + then:
>> + properties:
>> + clocks:
>> + minItems: 8
>> + maxItems: 8
>> + clock-names:
>> + items:
>> + - const: core_clk
>> + - const: bus_aggr_clk
>> + - const: iface_clk
>> + - const: core_clk_unipro
>> + - const: core_clk_ice
>
> Use existing name and put it in the same place as existing variant - sdm845:
> ice_core_clk
The only problem with sdm845 bindings is the presence of rx_lane1_sync_clk
clock. I'm guessing I could pass zeros there, because it shouldn't be used. Or
it could be moved to last property and then min/maxItems to guard, but that is
a change to something more-or-less immutable.
> Best regards,
> Krzysztof
Regards,
Iskren
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 09/14] arm64: dts: qcom: sm6115: Add UFS nodes
2022-09-01 16:13 ` Krzysztof Kozlowski
@ 2022-09-03 17:04 ` Iskren Chernev
2022-09-05 10:02 ` Krzysztof Kozlowski
0 siblings, 1 reply; 35+ messages in thread
From: Iskren Chernev @ 2022-09-03 17:04 UTC (permalink / raw)
To: Krzysztof Kozlowski, Bjorn Andersson, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm,
devicetree, Andy Gross, Konrad Dybcio, Krzysztof Kozlowski,
linux-kernel
On 9/1/22 19:13, Krzysztof Kozlowski wrote:
> On 01/09/2022 10:24, Iskren Chernev wrote:
>> The SM6115 comes with UFS support, so add the related UFS and UFS PHY
>> nodes.
>>
>> Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
>> ---
>> arch/arm64/boot/dts/qcom/sm6115.dtsi | 70 ++++++++++++++++++++++++++++
>> 1 file changed, 70 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
>> index cde963c56ac9..491fffff8aa1 100644
>> --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
>> @@ -620,6 +620,76 @@ opp-202000000 {
>> };
>> };
>>
>> + ufs_mem_hc: ufshc@4804000 {
>> + compatible = "qcom,sm6115-ufshc", "qcom,ufshc",
>> + "jedec,ufs-2.0";
>> + reg = <0x4804000 0x3000>, <0x4810000 0x8000>;
>> + reg-names = "std", "ice";
>
> I could imagine that testing DTS against existing bindings might miss a
> lot, because we have still a lot of errors. But at least I would expect
> you test your DTS against your own bindings, which you submit here (and
> previously).
>
> You just wrote that ice is not allowed.
OK, I'm an idiot. I didn't run the bindings checks, not against existing
bindings or my bindings or whatever. It's my fault.
Ice should be allowed, I fixed the bindings in v2.
For the record, running dtbs_checks is a PITA, not only because of the
thousands of warnings in unrelated code, but because it takes forever.
Maybe the docs should be updated with instructions on how to run it on a single
(or a small subset) of DTBs. I had to comment out a lot of Makefile lines to
focus it on mine. It would really help if the binding check works more like
a compiler, not some magic spell hidden in a bunch of Makefiles.
I'll list all remaining issues with description/explanation in v2. The fact
that some bindings break on all DTBs present doesn't help either.
>> + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
>> + phys = <&ufs_mem_phy_lanes>;
>> + phy-names = "ufsphy";
>> + lanes-per-direction = <1>;
>> + #reset-cells = <1>;
>> + resets = <&gcc GCC_UFS_PHY_BCR>;
>> + reset-names = "rst";
>> +
>> + power-domains = <&gcc GCC_UFS_PHY_GDSC>;
>> + iommus = <&apps_smmu 0x100 0>;
>> +
>> + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
>> + <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
>> + <&gcc GCC_UFS_PHY_AHB_CLK>,
>> + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
>> + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
>> + <&rpmcc RPM_SMD_XO_CLK_SRC>,
>> + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
>> + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;
>> + clock-names = "core_clk",
>> + "bus_aggr_clk",
>> + "iface_clk",
>> + "core_clk_unipro",
>> + "core_clk_ice",
>> + "ref_clk",
>> + "tx_lane0_sync_clk",
>> + "rx_lane0_sync_clk";
>> +
>> + freq-table-hz = <50000000 200000000>,
>> + <0 0>,
>> + <0 0>,
>> + <37500000 150000000>,
>> + <75000000 300000000>,
>> + <0 0>,
>> + <0 0>,
>> + <0 0>;
>> +
>> + non-removable;
>
> Is it allowed property?
I dropped it.
>> + status = "disabled";
>> + };
>> +
>> + ufs_mem_phy: phy@4807000 {
>> + compatible = "qcom,sm6115-qmp-ufs-phy";
>> + reg = <0x4807000 0x1c4>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + clocks = <&gcc GCC_UFS_CLKREF_CLK>,
>> + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
>> + clock-names = "ref", "ref_aux";
>> +
>> + resets = <&ufs_mem_hc 0>;
>> + reset-names = "ufsphy";
>> + status = "disabled";
>> +
>> + ufs_mem_phy_lanes: lanes@4807400 {
>> + reg = <0x4807400 0x098>,
>> + <0x4807600 0x130>,
>> + <0x4807c00 0x16c>;
>> + #phy-cells = <0>;
>> + };
>> + };
>> +
>> +
>
> Just one blank line.
>
> Best regards,
> Krzysztof
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 08/14] dt-bindings: ufs: qcom: Add sm6115 binding
2022-09-03 16:54 ` Iskren Chernev
@ 2022-09-04 19:10 ` Krzysztof Kozlowski
2022-09-05 7:29 ` Iskren Chernev
0 siblings, 1 reply; 35+ messages in thread
From: Krzysztof Kozlowski @ 2022-09-04 19:10 UTC (permalink / raw)
To: Iskren Chernev, Bjorn Andersson, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm,
devicetree, Andy Gross, Konrad Dybcio, Alim Akhtar, Avri Altman,
Bart Van Assche, Krzysztof Kozlowski, linux-scsi, linux-kernel
On 03/09/2022 19:54, Iskren Chernev wrote:
>
>
> On 9/1/22 19:11, Krzysztof Kozlowski wrote:
>> On 01/09/2022 10:24, Iskren Chernev wrote:
>>> Add SM6115 UFS to DT schema.
>>>
>>> Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
>>> ---
>>> .../devicetree/bindings/ufs/qcom,ufs.yaml | 26 +++++++++++++++++++
>>> 1 file changed, 26 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
>>> index f2d6298d926c..7c5f6e2e6d4c 100644
>>> --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
>>> +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
>>> @@ -28,6 +28,7 @@ properties:
>>> - qcom,msm8998-ufshc
>>> - qcom,sc8280xp-ufshc
>>> - qcom,sdm845-ufshc
>>> + - qcom,sm6115-ufshc
>>> - qcom,sm6350-ufshc
>>> - qcom,sm8150-ufshc
>>> - qcom,sm8250-ufshc
>>> @@ -178,6 +179,31 @@ allOf:
>>> minItems: 1
>>> maxItems: 1
>>>
>>> + - if:
>>> + properties:
>>> + compatible:
>>> + contains:
>>> + enum:
>>> + - qcom,sm6115-ufshc
>>> + then:
>>> + properties:
>>> + clocks:
>>> + minItems: 8
>>> + maxItems: 8
>>> + clock-names:
>>> + items:
>>> + - const: core_clk
>>> + - const: bus_aggr_clk
>>> + - const: iface_clk
>>> + - const: core_clk_unipro
>>> + - const: core_clk_ice
>>
>> Use existing name and put it in the same place as existing variant - sdm845:
>> ice_core_clk
>
> The only problem with sdm845 bindings is the presence of rx_lane1_sync_clk
> clock. I'm guessing I could pass zeros there, because it shouldn't be used. Or
> it could be moved to last property and then min/maxItems to guard, but that is
> a change to something more-or-less immutable.
I don't understand - what is the problem here. How presence of some
clock affects name of other clock and its place/location in list of clocks?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 08/14] dt-bindings: ufs: qcom: Add sm6115 binding
2022-09-04 19:10 ` Krzysztof Kozlowski
@ 2022-09-05 7:29 ` Iskren Chernev
2022-09-05 10:03 ` Krzysztof Kozlowski
0 siblings, 1 reply; 35+ messages in thread
From: Iskren Chernev @ 2022-09-05 7:29 UTC (permalink / raw)
To: Krzysztof Kozlowski, Bjorn Andersson, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm,
devicetree, Andy Gross, Konrad Dybcio, Alim Akhtar, Avri Altman,
Bart Van Assche, Krzysztof Kozlowski, linux-scsi, linux-kernel
On 9/4/22 22:10, Krzysztof Kozlowski wrote:
> On 03/09/2022 19:54, Iskren Chernev wrote:
>>
>>
>> On 9/1/22 19:11, Krzysztof Kozlowski wrote:
>>> On 01/09/2022 10:24, Iskren Chernev wrote:
>>>> Add SM6115 UFS to DT schema.
>>>>
>>>> Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
>>>> ---
>>>> .../devicetree/bindings/ufs/qcom,ufs.yaml | 26 +++++++++++++++++++
>>>> 1 file changed, 26 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
>>>> index f2d6298d926c..7c5f6e2e6d4c 100644
>>>> --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
>>>> +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
>>>> @@ -28,6 +28,7 @@ properties:
>>>> - qcom,msm8998-ufshc
>>>> - qcom,sc8280xp-ufshc
>>>> - qcom,sdm845-ufshc
>>>> + - qcom,sm6115-ufshc
>>>> - qcom,sm6350-ufshc
>>>> - qcom,sm8150-ufshc
>>>> - qcom,sm8250-ufshc
>>>> @@ -178,6 +179,31 @@ allOf:
>>>> minItems: 1
>>>> maxItems: 1
>>>>
>>>> + - if:
>>>> + properties:
>>>> + compatible:
>>>> + contains:
>>>> + enum:
>>>> + - qcom,sm6115-ufshc
>>>> + then:
>>>> + properties:
>>>> + clocks:
>>>> + minItems: 8
>>>> + maxItems: 8
>>>> + clock-names:
>>>> + items:
>>>> + - const: core_clk
>>>> + - const: bus_aggr_clk
>>>> + - const: iface_clk
>>>> + - const: core_clk_unipro
>>>> + - const: core_clk_ice
>>>
>>> Use existing name and put it in the same place as existing variant - sdm845:
>>> ice_core_clk
>>
>> The only problem with sdm845 bindings is the presence of rx_lane1_sync_clk
>> clock. I'm guessing I could pass zeros there, because it shouldn't be used. Or
>> it could be moved to last property and then min/maxItems to guard, but that is
>> a change to something more-or-less immutable.
>
> I don't understand - what is the problem here. How presence of some
> clock affects name of other clock and its place/location in list of clocks?
qcom,sdm845-ufshc has 9 clocks, one of which is rx_lane1_sync_clk.
qcom,sm6115-ufshc has 8 clocks (all of the ones in sdm845 without
rx_lane1_sync_clk). So if I'm understanding correctly, you want to put the
sm6115 with sdm845, which means re-use the clocks and reg specification from
sdm845, which means sm6115 will "inherit" this rx_lane1_sync_clk, and then
I have to put it in DT (otherwise the schema would complain), and I'm asking if
I can put an empty (i.e <0 0>) value, so schema is satisfied but clock is still
not really passed.
> Best regards,
> Krzysztof
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 09/14] arm64: dts: qcom: sm6115: Add UFS nodes
2022-09-03 17:04 ` Iskren Chernev
@ 2022-09-05 10:02 ` Krzysztof Kozlowski
2022-09-05 10:45 ` Iskren Chernev
0 siblings, 1 reply; 35+ messages in thread
From: Krzysztof Kozlowski @ 2022-09-05 10:02 UTC (permalink / raw)
To: Iskren Chernev, Bjorn Andersson, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm,
devicetree, Andy Gross, Konrad Dybcio, Krzysztof Kozlowski,
linux-kernel
On 03/09/2022 19:04, Iskren Chernev wrote:
>
>
> On 9/1/22 19:13, Krzysztof Kozlowski wrote:
>> On 01/09/2022 10:24, Iskren Chernev wrote:
>>> The SM6115 comes with UFS support, so add the related UFS and UFS PHY
>>> nodes.
>>>
>>> Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
>>> ---
>>> arch/arm64/boot/dts/qcom/sm6115.dtsi | 70 ++++++++++++++++++++++++++++
>>> 1 file changed, 70 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
>>> index cde963c56ac9..491fffff8aa1 100644
>>> --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
>>> @@ -620,6 +620,76 @@ opp-202000000 {
>>> };
>>> };
>>>
>>> + ufs_mem_hc: ufshc@4804000 {
>>> + compatible = "qcom,sm6115-ufshc", "qcom,ufshc",
>>> + "jedec,ufs-2.0";
>>> + reg = <0x4804000 0x3000>, <0x4810000 0x8000>;
>>> + reg-names = "std", "ice";
>>
>> I could imagine that testing DTS against existing bindings might miss a
>> lot, because we have still a lot of errors. But at least I would expect
>> you test your DTS against your own bindings, which you submit here (and
>> previously).
>>
>> You just wrote that ice is not allowed.
>
> OK, I'm an idiot. I didn't run the bindings checks, not against existing
> bindings or my bindings or whatever. It's my fault.
>
> Ice should be allowed, I fixed the bindings in v2.
>
> For the record, running dtbs_checks is a PITA, not only because of the
> thousands of warnings in unrelated code, but because it takes forever.
You can limit it per schema and/or limit it per target, which would
speed up things. Of course it depends on computer you have, but I don't
find it slow on my laptop and I run them a lot...
>
> Maybe the docs should be updated with instructions on how to run it on a single
> (or a small subset) of DTBs. I had to comment out a lot of Makefile lines to
> focus it on mine. It would really help if the binding check works more like
> a compiler, not some magic spell hidden in a bunch of Makefiles.
crosc.... make -j8 DT_SCHEMA_FILES=exynos-srom.yaml CHECK_DTBS=y
qcom/sm8450-hdk.dtb
>
> I'll list all remaining issues with description/explanation in v2. The fact
> that some bindings break on all DTBs present doesn't help either.
We're working on this... It's quite a lot of effort, especially when new
warnings are being added. :)
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 08/14] dt-bindings: ufs: qcom: Add sm6115 binding
2022-09-05 7:29 ` Iskren Chernev
@ 2022-09-05 10:03 ` Krzysztof Kozlowski
0 siblings, 0 replies; 35+ messages in thread
From: Krzysztof Kozlowski @ 2022-09-05 10:03 UTC (permalink / raw)
To: Iskren Chernev, Bjorn Andersson, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm,
devicetree, Andy Gross, Konrad Dybcio, Alim Akhtar, Avri Altman,
Bart Van Assche, Krzysztof Kozlowski, linux-scsi, linux-kernel
On 05/09/2022 09:29, Iskren Chernev wrote:
>
>
> On 9/4/22 22:10, Krzysztof Kozlowski wrote:
>> On 03/09/2022 19:54, Iskren Chernev wrote:
>>>
>>>
>>> On 9/1/22 19:11, Krzysztof Kozlowski wrote:
>>>> On 01/09/2022 10:24, Iskren Chernev wrote:
>>>>> Add SM6115 UFS to DT schema.
>>>>>
>>>>> Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
>>>>> ---
>>>>> .../devicetree/bindings/ufs/qcom,ufs.yaml | 26 +++++++++++++++++++
>>>>> 1 file changed, 26 insertions(+)
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
>>>>> index f2d6298d926c..7c5f6e2e6d4c 100644
>>>>> --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
>>>>> +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
>>>>> @@ -28,6 +28,7 @@ properties:
>>>>> - qcom,msm8998-ufshc
>>>>> - qcom,sc8280xp-ufshc
>>>>> - qcom,sdm845-ufshc
>>>>> + - qcom,sm6115-ufshc
>>>>> - qcom,sm6350-ufshc
>>>>> - qcom,sm8150-ufshc
>>>>> - qcom,sm8250-ufshc
>>>>> @@ -178,6 +179,31 @@ allOf:
>>>>> minItems: 1
>>>>> maxItems: 1
>>>>>
>>>>> + - if:
>>>>> + properties:
>>>>> + compatible:
>>>>> + contains:
>>>>> + enum:
>>>>> + - qcom,sm6115-ufshc
>>>>> + then:
>>>>> + properties:
>>>>> + clocks:
>>>>> + minItems: 8
>>>>> + maxItems: 8
>>>>> + clock-names:
>>>>> + items:
>>>>> + - const: core_clk
>>>>> + - const: bus_aggr_clk
>>>>> + - const: iface_clk
>>>>> + - const: core_clk_unipro
>>>>> + - const: core_clk_ice
>>>>
>>>> Use existing name and put it in the same place as existing variant - sdm845:
>>>> ice_core_clk
>>>
>>> The only problem with sdm845 bindings is the presence of rx_lane1_sync_clk
>>> clock. I'm guessing I could pass zeros there, because it shouldn't be used. Or
>>> it could be moved to last property and then min/maxItems to guard, but that is
>>> a change to something more-or-less immutable.
>>
>> I don't understand - what is the problem here. How presence of some
>> clock affects name of other clock and its place/location in list of clocks?
>
> qcom,sdm845-ufshc has 9 clocks, one of which is rx_lane1_sync_clk.
> qcom,sm6115-ufshc has 8 clocks (all of the ones in sdm845 without
> rx_lane1_sync_clk). So if I'm understanding correctly, you want to put the
> sm6115 with sdm845, which means re-use the clocks and reg specification from
> sdm845, which means sm6115 will "inherit" this rx_lane1_sync_clk, and then
> I have to put it in DT (otherwise the schema would complain), and I'm asking if
> I can put an empty (i.e <0 0>) value, so schema is satisfied but clock is still
> not really passed.
No. I want to use the same order and naming as sdm845 variant, but in
your own/dedicated if:else: entry. Just do not create inconsistencies
when not needed. If inconsistency is needed here (which I think is not),
please explain more.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 09/14] arm64: dts: qcom: sm6115: Add UFS nodes
2022-09-05 10:02 ` Krzysztof Kozlowski
@ 2022-09-05 10:45 ` Iskren Chernev
2022-09-05 10:54 ` Krzysztof Kozlowski
0 siblings, 1 reply; 35+ messages in thread
From: Iskren Chernev @ 2022-09-05 10:45 UTC (permalink / raw)
To: Krzysztof Kozlowski, Bjorn Andersson, Rob Herring
Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm,
devicetree, Andy Gross, Konrad Dybcio, Krzysztof Kozlowski,
linux-kernel
On 9/5/22 13:02, Krzysztof Kozlowski wrote:
> On 03/09/2022 19:04, Iskren Chernev wrote:
>>
>>
>> On 9/1/22 19:13, Krzysztof Kozlowski wrote:
>>> On 01/09/2022 10:24, Iskren Chernev wrote:
>>>> The SM6115 comes with UFS support, so add the related UFS and UFS PHY
>>>> nodes.
>>>>
>>>> Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
>>>> ---
>>>> arch/arm64/boot/dts/qcom/sm6115.dtsi | 70 ++++++++++++++++++++++++++++
>>>> 1 file changed, 70 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
>>>> index cde963c56ac9..491fffff8aa1 100644
>>>> --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
>>>> +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
>>>> @@ -620,6 +620,76 @@ opp-202000000 {
>>>> };
>>>> };
>>>>
>>>> + ufs_mem_hc: ufshc@4804000 {
>>>> + compatible = "qcom,sm6115-ufshc", "qcom,ufshc",
>>>> + "jedec,ufs-2.0";
>>>> + reg = <0x4804000 0x3000>, <0x4810000 0x8000>;
>>>> + reg-names = "std", "ice";
>>>
>>> I could imagine that testing DTS against existing bindings might miss a
>>> lot, because we have still a lot of errors. But at least I would expect
>>> you test your DTS against your own bindings, which you submit here (and
>>> previously).
>>>
>>> You just wrote that ice is not allowed.
>>
>> OK, I'm an idiot. I didn't run the bindings checks, not against existing
>> bindings or my bindings or whatever. It's my fault.
>>
>> Ice should be allowed, I fixed the bindings in v2.
>>
>> For the record, running dtbs_checks is a PITA, not only because of the
>> thousands of warnings in unrelated code, but because it takes forever.
>
> You can limit it per schema and/or limit it per target, which would
> speed up things. Of course it depends on computer you have, but I don't
> find it slow on my laptop and I run them a lot...
For one file it's great. For all files (i.e make dtbs_check) it takes more than
30mins on my 4c/8t intel laptop. About limiting by schema... not really
useful for me (except if I write the schema, but then I use it in one dtb, so
it's easier to limit by dtb).
>>
>> Maybe the docs should be updated with instructions on how to run it on a single
>> (or a small subset) of DTBs. I had to comment out a lot of Makefile lines to
>> focus it on mine. It would really help if the binding check works more like
>> a compiler, not some magic spell hidden in a bunch of Makefiles.
>
> crosc.... make -j8 DT_SCHEMA_FILES=exynos-srom.yaml CHECK_DTBS=y
> qcom/sm8450-hdk.dtb
Aaah, very nice! Thank you!
>>
>> I'll list all remaining issues with description/explanation in v2. The fact
>> that some bindings break on all DTBs present doesn't help either.
>
> We're working on this... It's quite a lot of effort, especially when new
> warnings are being added. :)
I understand. Is there an up-for-grabs list, or any schema fixes are welcome?
> Best regards,
> Krzysztof
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 09/14] arm64: dts: qcom: sm6115: Add UFS nodes
2022-09-05 10:45 ` Iskren Chernev
@ 2022-09-05 10:54 ` Krzysztof Kozlowski
0 siblings, 0 replies; 35+ messages in thread
From: Krzysztof Kozlowski @ 2022-09-05 10:54 UTC (permalink / raw)
To: Iskren Chernev, Bjorn Andersson, Rob Herring, Nicolas Dechesne
Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm,
devicetree, Andy Gross, Konrad Dybcio, Krzysztof Kozlowski,
linux-kernel
On 05/09/2022 12:45, Iskren Chernev wrote:
>
>>>
>>> I'll list all remaining issues with description/explanation in v2. The fact
>>> that some bindings break on all DTBs present doesn't help either.
>>
>> We're working on this... It's quite a lot of effort, especially when new
>> warnings are being added. :)
>
> I understand. Is there an up-for-grabs list, or any schema fixes are welcome?
Any fixes are welcomed, but check if someone did not post it. For
bindings conversion, the easiest is with "dfn:old-schema.txt" on
https://lore.kernel.org/all/.
We have some Linaro internal tracking, but maybe it would be useful to
expose it to avoid duplication of work and to track better what is still
to do/fix.
+Cc Nicolas,
Are we interested in some public tracking not only upstream status but
also actual things to do (like DTS fixes, DT schema conversions)? It
might be quite a lot of effort for us, but if community is engaged, they
would offload us in task tracking system.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 35+ messages in thread
end of thread, other threads:[~2022-09-05 10:55 UTC | newest]
Thread overview: 35+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
[not found] <20220901072414.1923075-1-iskren.chernev@gmail.com>
2022-09-01 7:24 ` [PATCH 01/14] arm64: dts: qcom: sm6115: Add basic soc dtsi Iskren Chernev
2022-09-01 16:03 ` Krzysztof Kozlowski
2022-09-01 7:24 ` [PATCH 02/14] arm64: dts: qcom: sm6115: Add rpmcc and rpmpd nodes Iskren Chernev
2022-09-01 7:24 ` [PATCH 03/14] arm64: dts: qcom: sm6115: Add GCC node Iskren Chernev
2022-09-01 16:05 ` Krzysztof Kozlowski
2022-09-01 7:24 ` [PATCH 04/14] arm64: dts: qcom: sm6115: Add pinctrl node Iskren Chernev
2022-09-01 7:24 ` [PATCH 05/14] arm64: dts: qcom: sm6115: Add apps smmu node Iskren Chernev
2022-09-01 16:05 ` Krzysztof Kozlowski
2022-09-01 7:24 ` [PATCH 06/14] arm64: dts: qcom: sm6115: Add usb and related phy nodes Iskren Chernev
2022-09-01 16:06 ` Krzysztof Kozlowski
2022-09-01 7:24 ` [PATCH 07/14] arm64: dts: qcom: sm6115: Add sdhci nodes and related pinctrl Iskren Chernev
2022-09-01 16:08 ` Krzysztof Kozlowski
2022-09-01 7:24 ` [PATCH 08/14] dt-bindings: ufs: qcom: Add sm6115 binding Iskren Chernev
2022-09-01 16:11 ` Krzysztof Kozlowski
2022-09-03 16:54 ` Iskren Chernev
2022-09-04 19:10 ` Krzysztof Kozlowski
2022-09-05 7:29 ` Iskren Chernev
2022-09-05 10:03 ` Krzysztof Kozlowski
2022-09-01 7:24 ` [PATCH 09/14] arm64: dts: qcom: sm6115: Add UFS nodes Iskren Chernev
2022-09-01 16:13 ` Krzysztof Kozlowski
2022-09-03 17:04 ` Iskren Chernev
2022-09-05 10:02 ` Krzysztof Kozlowski
2022-09-05 10:45 ` Iskren Chernev
2022-09-05 10:54 ` Krzysztof Kozlowski
2022-09-01 7:24 ` [PATCH 10/14] arm64: dts: qcom: sm6115: Add SPMI bus node Iskren Chernev
2022-09-01 16:14 ` Krzysztof Kozlowski
2022-09-01 7:24 ` [PATCH 11/14] dt-bindings: arm: cpus: Add kryo240 compatible Iskren Chernev
2022-09-01 15:29 ` Vinod Koul
2022-09-01 16:14 ` Krzysztof Kozlowski
2022-09-01 7:24 ` [PATCH 12/14] arm64: dts: qcom: sm4250: Add soc dtsi Iskren Chernev
2022-09-01 7:24 ` [PATCH 13/14] dt-bindings: arm: qcom: Add compatible for oneplus,billie2 phone Iskren Chernev
2022-09-01 16:17 ` Krzysztof Kozlowski
2022-09-01 7:24 ` [PATCH 14/14] arm64: dts: qcom: sm4250: Add support for oneplus-billie2 Iskren Chernev
2022-09-01 16:20 ` Krzysztof Kozlowski
2022-09-03 12:32 ` Konrad Dybcio
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).