From: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
To: Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>,
"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
"robin.murphy@arm.com" <robin.murphy@arm.com>
Cc: "mark.rutland@arm.com" <mark.rutland@arm.com>,
"vkilari@codeaurora.org" <vkilari@codeaurora.org>,
"neil.m.leeder@gmail.com" <neil.m.leeder@gmail.com>,
"pabba@codeaurora.org" <pabba@codeaurora.org>,
John Garry <john.garry@huawei.com>,
"will.deacon@arm.com" <will.deacon@arm.com>,
"rruigrok@codeaurora.org" <rruigrok@codeaurora.org>,
Linuxarm <linuxarm@huawei.com>,
"linux-acpi@vger.kernel.org" <linux-acpi@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"Guohanjun (Hanjun Guo)" <guohanjun@huawei.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v3 2/3] perf: add arm64 smmuv3 pmu driver
Date: Wed, 3 Oct 2018 10:46:57 +0100 [thread overview]
Message-ID: <6d51a825-325f-5f78-20da-bf27f208fe37@arm.com> (raw)
In-Reply-To: <5FC3163CFD30C246ABAA99954A238FA838793F4E@FRAEML521-MBX.china.huawei.com>
On 03/10/2018 09:46, Shameerali Kolothum Thodi wrote:
[...]
>>> + /* Verify specified event is supported on this PMU */
>>> + event_id = get_event(event);
>>> + if (((event_id < SMMU_ARCH_MAX_EVENT_ID) &&
>>> + (!test_bit(event_id, smmu_pmu->supported_events))) ||
>>> + (event_id > SMMU_IMPDEF_MAX_EVENT_ID)) {
>>
>>> = ?
>
> I was slightly confused by the spec here as it says,
>
> Performance events are indicated by a numeric ID, in the following ranges:
> • 0x0000 to 0x007F: Architected events
> • 0x0080 to 0xFFFF: IMPLEMENTATION DEFINED events
>
> It looks to me the ids are valid including those limits.
Yes my mistake, I mixed up IMPDEF_MAX_EVENT_ID which is inclusive with
ARCH_MAX_EVENT_ID which isn't, sorry about that
[...]
>>> + dev_err(dev, "Setup irq failed, PMU @%pa\n", &res_0->start);
>>
>> You can probably remove "PMU @%pa" from error and info messages, since
>> the device name already uniquely identifies it:
>> "[ 6.168200] arm-smmu-v3-pmu 2b442000.smmu-pmcg: Registered SMMU
>> PMU
>> @ 0x000000002b442000 using 4 counters"
>
> Interesting. What I have is,
>
> [ 25.669636] arm-smmu-v3-pmu arm-smmu-v3-pmu.6.auto: Registered SMMU
> PMU @ 0x0000000148001000 using 8 counters
>
> Are you using the same patches and is booting using ACPI? IIRC, in the iort
> code it uses the name "arm-smmu-v3-pmu" and AUTO id to register/add the platform
> dev. So not sure, how it is printing the address in your case.
>
> Please check and let me know.
Right, I've been using device tree for my tests, not ACPI. I thought it
was the core platform code that was creating the names. I guess we could
add nicer names to IORT but that's probably for a different series, so
nevermind.
Thanks,
Jean
next prev parent reply other threads:[~2018-10-03 9:47 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-21 15:08 [PATCH v3 0/3] arm64 SMMUv3 PMU driver with IORT support Shameer Kolothum
2018-09-21 15:08 ` [PATCH v3 1/3] acpi: arm64: add iort support for PMCG Shameer Kolothum
2018-10-04 16:43 ` Lorenzo Pieralisi
2018-10-04 17:35 ` Robin Murphy
2018-10-05 11:06 ` Shameerali Kolothum Thodi
2018-09-21 15:08 ` [PATCH v3 2/3] perf: add arm64 smmuv3 pmu driver Shameer Kolothum
2018-10-02 14:11 ` Jean-Philippe Brucker
2018-10-02 16:19 ` Jean-Philippe Brucker
2018-10-02 16:35 ` Robin Murphy
2018-10-03 8:52 ` Shameerali Kolothum Thodi
2018-10-03 8:46 ` Shameerali Kolothum Thodi
2018-10-03 9:46 ` Jean-Philippe Brucker [this message]
2018-10-03 10:21 ` Robin Murphy
2018-10-03 10:37 ` Robin Murphy
2018-10-03 11:28 ` Shameerali Kolothum Thodi
2018-10-03 11:06 ` John Garry
2018-10-11 11:25 ` Robin Murphy
2018-10-11 11:49 ` Shameerali Kolothum Thodi
2018-09-21 15:08 ` [PATCH v3 3/3] perf/smmuv3: Add MSI irq support Shameer Kolothum
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