* [PATCH] platform/x86: intel_pmc_core: Avoid a u32 overflow
@ 2019-02-16 0:19 Rajat Jain
2019-02-21 14:24 ` Andy Shevchenko
2019-02-22 3:40 ` Bhardwaj, Rajneesh
0 siblings, 2 replies; 3+ messages in thread
From: Rajat Jain @ 2019-02-16 0:19 UTC (permalink / raw)
To: Rajneesh Bhardwaj, Vishwanath Somayaji, Darren Hart,
Andy Shevchenko, platform-driver-x86, linux-kernel
Cc: rajatxjain, Rajat Jain
The register (SLP_S0_RES) at offset slp_s0_offset is a 32 bit register.
The pmc_core_adjust_slp_s0_step() could overflow the u32 value while
returning it after adjusting the step. Thus change to u64, this is
already accounted for in debugfs attribute (that wants to output a
64 bit value).
Signed-off-by: Rajat Jain <rajatja@google.com>
---
drivers/platform/x86/intel_pmc_core.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c
index 22dbf115782e..f90f4dd25151 100644
--- a/drivers/platform/x86/intel_pmc_core.c
+++ b/drivers/platform/x86/intel_pmc_core.c
@@ -328,9 +328,9 @@ static inline void pmc_core_reg_write(struct pmc_dev *pmcdev, int
writel(val, pmcdev->regbase + reg_offset);
}
-static inline u32 pmc_core_adjust_slp_s0_step(u32 value)
+static inline u64 pmc_core_adjust_slp_s0_step(u32 value)
{
- return value * SPT_PMC_SLP_S0_RES_COUNTER_STEP;
+ return (u64)value * SPT_PMC_SLP_S0_RES_COUNTER_STEP;
}
static int pmc_core_dev_state_get(void *data, u64 *val)
--
2.21.0.rc0.258.g878e2cd30e-goog
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] platform/x86: intel_pmc_core: Avoid a u32 overflow
2019-02-16 0:19 [PATCH] platform/x86: intel_pmc_core: Avoid a u32 overflow Rajat Jain
@ 2019-02-21 14:24 ` Andy Shevchenko
2019-02-22 3:40 ` Bhardwaj, Rajneesh
1 sibling, 0 replies; 3+ messages in thread
From: Andy Shevchenko @ 2019-02-21 14:24 UTC (permalink / raw)
To: Rajat Jain
Cc: Rajneesh Bhardwaj, Vishwanath Somayaji, Darren Hart,
Andy Shevchenko, Platform Driver, Linux Kernel Mailing List,
Rajat Jain
On Sat, Feb 16, 2019 at 2:19 AM Rajat Jain <rajatja@google.com> wrote:
>
> The register (SLP_S0_RES) at offset slp_s0_offset is a 32 bit register.
> The pmc_core_adjust_slp_s0_step() could overflow the u32 value while
> returning it after adjusting the step. Thus change to u64, this is
> already accounted for in debugfs attribute (that wants to output a
> 64 bit value).
>
Pushed to my review and testing queue, thanks!
> Signed-off-by: Rajat Jain <rajatja@google.com>
> ---
> drivers/platform/x86/intel_pmc_core.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c
> index 22dbf115782e..f90f4dd25151 100644
> --- a/drivers/platform/x86/intel_pmc_core.c
> +++ b/drivers/platform/x86/intel_pmc_core.c
> @@ -328,9 +328,9 @@ static inline void pmc_core_reg_write(struct pmc_dev *pmcdev, int
> writel(val, pmcdev->regbase + reg_offset);
> }
>
> -static inline u32 pmc_core_adjust_slp_s0_step(u32 value)
> +static inline u64 pmc_core_adjust_slp_s0_step(u32 value)
> {
> - return value * SPT_PMC_SLP_S0_RES_COUNTER_STEP;
> + return (u64)value * SPT_PMC_SLP_S0_RES_COUNTER_STEP;
> }
>
> static int pmc_core_dev_state_get(void *data, u64 *val)
> --
> 2.21.0.rc0.258.g878e2cd30e-goog
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] platform/x86: intel_pmc_core: Avoid a u32 overflow
2019-02-16 0:19 [PATCH] platform/x86: intel_pmc_core: Avoid a u32 overflow Rajat Jain
2019-02-21 14:24 ` Andy Shevchenko
@ 2019-02-22 3:40 ` Bhardwaj, Rajneesh
1 sibling, 0 replies; 3+ messages in thread
From: Bhardwaj, Rajneesh @ 2019-02-22 3:40 UTC (permalink / raw)
To: Rajat Jain, Rajneesh Bhardwaj, Vishwanath Somayaji, Darren Hart,
Andy Shevchenko, platform-driver-x86, linux-kernel
Cc: rajatxjain
On 16-Feb-19 5:49 AM, Rajat Jain wrote:
> The register (SLP_S0_RES) at offset slp_s0_offset is a 32 bit register.
> The pmc_core_adjust_slp_s0_step() could overflow the u32 value while
> returning it after adjusting the step. Thus change to u64, this is
> already accounted for in debugfs attribute (that wants to output a
> 64 bit value).
>
> Signed-off-by: Rajat Jain <rajatja@google.com>
Acked-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com>
> ---
> drivers/platform/x86/intel_pmc_core.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c
> index 22dbf115782e..f90f4dd25151 100644
> --- a/drivers/platform/x86/intel_pmc_core.c
> +++ b/drivers/platform/x86/intel_pmc_core.c
> @@ -328,9 +328,9 @@ static inline void pmc_core_reg_write(struct pmc_dev *pmcdev, int
> writel(val, pmcdev->regbase + reg_offset);
> }
>
> -static inline u32 pmc_core_adjust_slp_s0_step(u32 value)
> +static inline u64 pmc_core_adjust_slp_s0_step(u32 value)
> {
> - return value * SPT_PMC_SLP_S0_RES_COUNTER_STEP;
> + return (u64)value * SPT_PMC_SLP_S0_RES_COUNTER_STEP;
> }
>
> static int pmc_core_dev_state_get(void *data, u64 *val)
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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