[PATCH] arm64/sysreg: Add register fields for ID_AA64DFR1_EL1

[PATCH] arm64/sysreg: Add register fields for ID_AA64DFR1_EL1

[Anshuman Khandual]

This adds register fields for ID_AA64DFR1_EL1 as per the definitions based
on DDI0601 2023-12.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
 arch/arm64/tools/sysreg | 28 +++++++++++++++++++++++++++-
 1 file changed, 27 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 94692abfeeb9..1cd06edfad3b 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -1253,7 +1253,33 @@ EndEnum
 EndSysreg
 
 Sysreg	ID_AA64DFR1_EL1	3	0	0	5	1
-Res0	63:0
+Field	63:56	ABL_CMPs
+Field	55:52	DPFZS
+UnsignedEnum	51:48	EBEP
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+UnsignedEnum	47:44	ITE
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+UnsignedEnum	43:40	ABLE
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+UnsignedEnum	39:36	PMICNTR
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+UnsignedEnum	35:32	SPMU
+	0b0000	NI
+	0b0001	IMP
+	0b0010	IMP_SPMZR
+EndEnum
+Field	31:24	CTX_CMPs
+Field	23:16	WRPs
+Field	15:8	BRPs
+Field	7:0	SYSPMUID
 EndSysreg
 
 Sysreg	ID_AA64AFR0_EL1	3	0	0	5	4
-- 
2.25.1

Re: [PATCH] arm64/sysreg: Add register fields for ID_AA64DFR1_EL1

[Mark Brown]

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On Thu, Feb 15, 2024 at 12:24:54PM +0530, Anshuman Khandual wrote:

>  Sysreg	ID_AA64DFR1_EL1	3	0	0	5	1
> -Res0	63:0
> +Field	63:56	ABL_CMPs
> +Field	55:52	DPFZS

This is documented in the architecture as an enumeration, though I'm not
immediately seeing what values to use.

Otherwise this looks good.

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Re: [PATCH] arm64/sysreg: Add register fields for ID_AA64DFR1_EL1

[Anshuman Khandual]

On 2/15/24 18:34, Mark Brown wrote:
> On Thu, Feb 15, 2024 at 12:24:54PM +0530, Anshuman Khandual wrote:
> 
>>  Sysreg	ID_AA64DFR1_EL1	3	0	0	5	1
>> -Res0	63:0
>> +Field	63:56	ABL_CMPs
>> +Field	55:52	DPFZS
> 
> This is documented in the architecture as an enumeration, though I'm not
> immediately seeing what values to use.

Just wondering - would something like the following make sense. Because
0b0000 signifies that the cycle counter would just ignore PMCR_EL0.FZS,
where as it gets frozen with 0b0001.

UnsignedEnum   55:52   DPFZS
       0b0000  IGNR
       0b0001  FRZN
EndEnum

> 
> Otherwise this looks good.

Re: [PATCH] arm64/sysreg: Add register fields for ID_AA64DFR1_EL1

[Mark Brown]

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On Sun, Feb 18, 2024 at 06:04:34AM +0530, Anshuman Khandual wrote:

> Just wondering - would something like the following make sense. Because
> 0b0000 signifies that the cycle counter would just ignore PMCR_EL0.FZS,
> where as it gets frozen with 0b0001.

> UnsignedEnum   55:52   DPFZS
>        0b0000  IGNR
>        0b0001  FRZN
> EndEnum

LGTM.

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