[PATCH v1 0/6] Add display driver for MT8188 VDOSYS1

[PATCH v1 0/6] Add display driver for MT8188 VDOSYS1

[Hsiao Chien Sung]

[PATCH v1 1/6] dt-bindings: display/mediatek: mt8188: Add documentations
[PATCH v1 2/6] dt-bindings: reset: mt8188: Add reset control bits for VDOSYS1
[PATCH v1 3/6] soc: mediatek: mt8188: Support VDOSYS1 in mtk-mmsys
[PATCH v1 4/6] drm/mediatek: mt8188: Modify display driver for VDOSYS1
[PATCH v1 5/6] soc: mediatek: mt8188: Support VDOSYS1 PADDING in mtk-mmsys
[PATCH v1 6/6] drm/mediatek: mt8188: Add VDOSYS1 PADDING driver

Hsiao Chien Sung (6):
  dt-bindings: display/mediatek: mt8188: Add documentations for VDOSYS1
  dt-bindings: reset: mt8188: Add reset control bits for VDOSYS1
  soc: mediatek: mt8188: Support VDOSYS1 in mtk-mmsys
  drm/mediatek: mt8188: Modify display driver for VDOSYS1
  soc: mediatek: mt8188: Support VDOSYS1 PADDING in mtk-mmsys
  drm/mediatek: mt8188: Add VDOSYS1 PADDING driver

 .../bindings/arm/mediatek/mediatek,mmsys.yaml |   1 +
 .../display/mediatek/mediatek,ethdr.yaml      |   5 +-
 .../display/mediatek/mediatek,mdp-rdma.yaml   |   5 +-
 .../display/mediatek/mediatek,merge.yaml      |   1 +
 .../display/mediatek/mediatek,padding.yaml    |  80 ++++++++++
 drivers/gpu/drm/mediatek/Makefile             |   1 +
 drivers/gpu/drm/mediatek/mtk_disp_drv.h       |   3 +
 drivers/gpu/drm/mediatek/mtk_disp_merge.c     |   3 +-
 .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c   | 143 +++++++++++------
 drivers/gpu/drm/mediatek/mtk_disp_padding.c   | 134 ++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h   |   1 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c        |  29 +++-
 drivers/gpu/drm/mediatek/mtk_drm_drv.h        |   2 +-
 drivers/gpu/drm/mediatek/mtk_ethdr.c          |   1 +
 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c       |   1 +
 drivers/soc/mediatek/mt8188-mmsys.h           | 149 ++++++++++++++++++
 drivers/soc/mediatek/mtk-mmsys.c              |  13 ++
 drivers/soc/mediatek/mtk-mmsys.h              |   1 +
 drivers/soc/mediatek/mtk-mutex.c              |  51 ++++++
 include/dt-bindings/reset/mt8188-resets.h     |  12 ++
 include/linux/soc/mediatek/mtk-mmsys.h        |   8 +
 21 files changed, 589 insertions(+), 55 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_padding.c

--
2.18.0

[PATCH v1 1/6] dt-bindings: display/mediatek: mt8188: Add documentations for VDOSYS1

[Hsiao Chien Sung]

Add device tree documentations for MT8188 VDOSYS1.

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 .../bindings/arm/mediatek/mediatek,mmsys.yaml |  1 +
 .../display/mediatek/mediatek,ethdr.yaml      |  5 +-
 .../display/mediatek/mediatek,mdp-rdma.yaml   |  5 +-
 .../display/mediatek/mediatek,merge.yaml      |  1 +
 .../display/mediatek/mediatek,padding.yaml    | 80 +++++++++++++++++++
 5 files changed, 90 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index 536f5a5ebd24..642fa2e4736e 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -32,6 +32,7 @@ properties:
               - mediatek,mt8183-mmsys
               - mediatek,mt8186-mmsys
               - mediatek,mt8188-vdosys0
+              - mediatek,mt8188-vdosys1
               - mediatek,mt8192-mmsys
               - mediatek,mt8195-vdosys1
               - mediatek,mt8195-vppsys0
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
index 801fa66ae615..e3f740ab0564 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
@@ -23,7 +23,10 @@ description:

 properties:
   compatible:
-    const: mediatek,mt8195-disp-ethdr
+    oneOf:
+      - enum:
+        - mediatek,mt8188-disp-ethdr
+        - mediatek,mt8195-disp-ethdr

   reg:
     maxItems: 7
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
index dd12e2ff685c..07c345fa9178 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
@@ -21,7 +21,10 @@ description:

 properties:
   compatible:
-    const: mediatek,mt8195-vdo1-rdma
+    oneOf:
+      - enum:
+        - mediatek,mt8188-vdo1-rdma
+        - mediatek,mt8195-vdo1-rdma

   reg:
     maxItems: 1
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
index 2f8e2f4dc3b8..600f1b4608f8 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
@@ -23,6 +23,7 @@ properties:
     oneOf:
       - enum:
           - mediatek,mt8173-disp-merge
+          - mediatek,mt8188-disp-merge
           - mediatek,mt8195-disp-merge

   reg:
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml
new file mode 100644
index 000000000000..8a9e74cbf6dc
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,padding.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek PADDING
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description:
+  MediaTek PADDING provides ability to VDOSYS1 to fill pixels to
+  width and height of a layer with a specified color.
+  Since MIXER in VDOSYS1 requires the width of a layer to be 2-pixel-align, or
+  4-pixel-align when ETHDR is enabled, we need PADDING to deal with odd width.
+  Please notice that even if the PADDING is in bypass mode,
+  settings in the registers must be cleared to 0, otherwise
+  undeinfed behaviors could happen.
+
+properties:
+  compatible:
+    const: mediatek,mt8188-vdo1-padding
+
+  reg:
+    maxItems: 1
+
+  power-domains:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: RDMA Clock
+
+  mediatek,gce-client-reg:
+    description:
+      The register of display function block to be set by gce. There are 4 arguments,
+      such as gce node, subsys id, offset and register size. The subsys id that is
+      mapping to the register of display function blocks is defined in the gce header
+      include/dt-bindings/gce/<chip>-gce.h of each chips.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    items:
+      items:
+        - description: phandle of GCE
+        - description: GCE subsys id
+        - description: register offset
+        - description: register size
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - power-domains
+  - clocks
+  - mediatek,gce-client-reg
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/mt8188-clk.h>
+    #include <dt-bindings/power/mt8188-power.h>
+    #include <dt-bindings/gce/mt8188-gce.h>
+    #include <dt-bindings/memory/mt8188-memory-port.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        vdo1_padding0: vdo1_padding0@1c11d000 {
+            compatible = "mediatek,mt8188-vdo1-padding";
+            reg = <0 0x1c11d000 0 0x1000>;
+            clocks = <&vdosys1 CLK_VDO1_PADDING0>;
+            power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
+            mediatek,gce-client-reg =
+                <&gce0 SUBSYS_1c11XXXX 0xd000 0x1000>;
+        };
+    };
--
2.18.0

[PATCH v1 2/6] dt-bindings: reset: mt8188: Add reset control bits for VDOSYS1

[Hsiao Chien Sung]

Add reset control bits for  MT8188 VDOSYS1.

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 include/dt-bindings/reset/mt8188-resets.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/include/dt-bindings/reset/mt8188-resets.h b/include/dt-bindings/reset/mt8188-resets.h
index 377cdfda82a9..439a9a25ca19 100644
--- a/include/dt-bindings/reset/mt8188-resets.h
+++ b/include/dt-bindings/reset/mt8188-resets.h
@@ -33,4 +33,16 @@

 #define MT8188_TOPRGU_SW_RST_NUM               24

+/* VDOSYS1 */
+#define MT8188_VDO1_RST_MERGE0_DL_ASYNC         9
+#define MT8188_VDO1_RST_MERGE1_DL_ASYNC         10
+#define MT8188_VDO1_RST_MERGE2_DL_ASYNC         11
+#define MT8188_VDO1_RST_MERGE3_DL_ASYNC         32
+#define MT8188_VDO1_RST_MERGE4_DL_ASYNC         33
+#define MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC    64
+#define MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC    65
+#define MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC     66
+#define MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC    80
+#define MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC    81
+
 #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */
--
2.18.0

[PATCH v1 3/6] soc: mediatek: mt8188: Support VDOSYS1 in mtk-mmsys

[Hsiao Chien Sung]

- Add register definitions for MT8188
- Add VDOSYS1 routing table
- Update MUTEX definitions accordingly
- Set VSYNC length from 0x40 (default) to 1 since ETHDR is bypassed

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 drivers/soc/mediatek/mt8188-mmsys.h | 149 ++++++++++++++++++++++++++++
 drivers/soc/mediatek/mtk-mmsys.c    |  13 +++
 drivers/soc/mediatek/mtk-mmsys.h    |   1 +
 drivers/soc/mediatek/mtk-mutex.c    |  35 +++++++
 4 files changed, 198 insertions(+)

diff --git a/drivers/soc/mediatek/mt8188-mmsys.h b/drivers/soc/mediatek/mt8188-mmsys.h
index 448cc3761b43..1b313b979ea1 100644
--- a/drivers/soc/mediatek/mt8188-mmsys.h
+++ b/drivers/soc/mediatek/mt8188-mmsys.h
@@ -67,6 +67,79 @@
 #define MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE		BIT(18)
 #define MT8188_SOUT_DSC_WRAP0_OUT_TO_DISP_WDMA0		BIT(19)

+#define MT8188_VDO1_SW0_RST_B					0x1d0
+#define MT8188_VDO1_HDR_TOP_CFG					0xd00
+#define MT8188_VDO1_MIXER_IN1_ALPHA				0xd30
+#define MT8188_VDO1_MIXER_IN1_PAD				0xd40
+#define MT8188_VDO1_MERGE0_ASYNC_CFG_WD				0xe30
+#define MT8188_VDO1_HDRBE_ASYNC_CFG_WD				0xe70
+
+#define MT8188_VDO1_VPP_MERGE0_P0_SEL_IN			0xf04
+#define MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0			1
+
+#define MT8188_VDO1_VPP_MERGE0_P1_SEL_IN			0xf08
+#define MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1			1
+
+#define MT8188_VDO1_DISP_DPI1_SEL_IN				0xf10
+#define MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT			0
+
+#define MT8188_VDO1_DISP_DP_INTF0_SEL_IN			0xf14
+#define MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT		0
+
+#define MT8188_VDO1_MERGE4_SOUT_SEL				0xf18
+#define MT8188_MERGE4_SOUT_TO_DPI1_SEL					BIT(2)
+#define MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL				BIT(3)
+
+#define MT8188_VDO1_MIXER_IN1_SEL_IN				0xf24
+#define MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT			1
+
+#define MT8188_VDO1_MIXER_IN2_SEL_IN				0xf28
+#define MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT			1
+
+#define MT8188_VDO1_MIXER_IN3_SEL_IN				0xf2c
+#define MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT			1
+
+#define MT8188_VDO1_MIXER_IN4_SEL_IN				0xf30
+#define MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT			1
+
+#define MT8188_VDO1_MIXER_OUT_SOUT_SEL				0xf34
+#define MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL				1
+
+#define MT8188_VDO1_VPP_MERGE1_P0_SEL_IN			0xf3c
+#define MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2			1
+
+#define MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL			0xf40
+#define MT8188_SOUT_TO_MIXER_IN1_SEL					1
+
+#define MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL			0xf44
+#define MT8188_SOUT_TO_MIXER_IN2_SEL					1
+
+#define MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL			0xf48
+#define MT8188_SOUT_TO_MIXER_IN3_SEL					1
+
+#define MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL			0xf4c
+#define MT8188_SOUT_TO_MIXER_IN4_SEL					1
+
+#define MT8188_VDO1_MERGE4_ASYNC_SEL_IN				0xf50
+#define MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT			1
+
+#define MT8188_VDO1_MIXER_IN1_SOUT_SEL				0xf58
+#define MT8188_MIXER_IN1_SOUT_TO_DISP_MIXER				0
+
+#define MT8188_VDO1_MIXER_IN2_SOUT_SEL				0xf5c
+#define MT8188_MIXER_IN2_SOUT_TO_DISP_MIXER				0
+
+#define MT8188_VDO1_MIXER_IN3_SOUT_SEL				0xf60
+#define MT8188_MIXER_IN3_SOUT_TO_DISP_MIXER				0
+
+#define MT8188_VDO1_MIXER_IN4_SOUT_SEL				0xf64
+#define MT8188_MIXER_IN4_SOUT_TO_DISP_MIXER				0
+
+#define MT8188_VDO1_MIXER_SOUT_SEL_IN				0xf68
+#define MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER			0
+
+#define MT8188_VDO1_MIXER_VSYNC_LEN				0xd5c
+
 static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = {
 	{
 		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
@@ -146,4 +219,80 @@ static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = {
 	},
 };

+static const struct mtk_mmsys_routes mmsys_mt8188_vdo1_routing_table[] = {
+	{
+		DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1,
+		MT8188_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
+		MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
+	}, {
+		DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1,
+		MT8188_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
+		MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
+	}, {
+		DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2,
+		MT8188_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
+		MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
+	}, {
+		DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
+		MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
+		MT8188_SOUT_TO_MIXER_IN1_SEL
+	}, {
+		DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
+		MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
+		MT8188_SOUT_TO_MIXER_IN2_SEL
+	}, {
+		DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
+		MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
+		MT8188_SOUT_TO_MIXER_IN3_SEL
+	}, {
+		DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
+		MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
+		MT8188_SOUT_TO_MIXER_IN4_SEL
+	}, {
+		DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
+		MT8188_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
+		MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL
+	}, {
+		DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
+		MT8188_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
+		MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
+	}, {
+		DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
+		MT8188_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
+		MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
+	}, {
+		DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
+		MT8188_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
+		MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
+	}, {
+		DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
+		MT8188_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
+		MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
+	}, {
+		DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
+		MT8188_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
+		MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
+	}, {
+		DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
+		MT8188_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
+		MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
+	}, {
+		DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
+		MT8188_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
+		MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
+	}, {
+		DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
+		MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
+		MT8188_MERGE4_SOUT_TO_DPI1_SEL
+	}, {
+		DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
+		MT8188_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
+		MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
+	}, {
+		DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
+		MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0),
+		MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL
+	}
+};
+
 #endif /* __SOC_MEDIATEK_MT8188_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 9619faa796e8..b1e4695a0a93 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -89,6 +89,15 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
 	.num_routes = ARRAY_SIZE(mmsys_mt8188_routing_table),
 };

+static const struct mtk_mmsys_driver_data mt8188_vdosys1_driver_data = {
+	.clk_driver = "clk-mt8188-vdo1",
+	.routes = mmsys_mt8188_vdo1_routing_table,
+	.num_routes = ARRAY_SIZE(mmsys_mt8188_vdo1_routing_table),
+	.sw0_rst_offset = MT8188_VDO1_SW0_RST_B,
+	.num_resets = 96,
+	.vsync_len = 1,
+};
+
 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
 	.clk_driver = "clk-mt8192-mm",
 	.routes = mmsys_mt8192_routing_table,
@@ -213,6 +222,9 @@ void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16
 			      alpha_sel << (19 + idx), cmdq_pkt);
 	mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4,
 			      GENMASK(31, 16) | GENMASK(1, 0), biwidth << 16 | mode, cmdq_pkt);
+	if (mmsys->data->vsync_len)
+		mtk_mmsys_update_bits(mmsys, MT8188_VDO1_MIXER_VSYNC_LEN, ~0,
+				      mmsys->data->vsync_len, cmdq_pkt);
 }
 EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_config);

@@ -431,6 +443,7 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
 	{ .compatible = "mediatek,mt8183-mmsys", .data = &mt8183_mmsys_driver_data },
 	{ .compatible = "mediatek,mt8186-mmsys", .data = &mt8186_mmsys_driver_data },
 	{ .compatible = "mediatek,mt8188-vdosys0", .data = &mt8188_vdosys0_driver_data },
+	{ .compatible = "mediatek,mt8188-vdosys1", .data = &mt8188_vdosys1_driver_data },
 	{ .compatible = "mediatek,mt8192-mmsys", .data = &mt8192_mmsys_driver_data },
 	/* "mediatek,mt8195-mmsys" compatible is deprecated */
 	{ .compatible = "mediatek,mt8195-mmsys", .data = &mt8195_vdosys0_driver_data },
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 6725403d2e3a..b9cc1d9e46fa 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -93,6 +93,7 @@ struct mtk_mmsys_driver_data {
 	const u16 sw0_rst_offset;
 	const u32 num_resets;
 	const bool is_vppsys;
+	const u8 vsync_len;
 };

 /*
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 26f3d9a41496..11dda20eb462 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -134,6 +134,22 @@
 #define MT8188_MUTEX_MOD_DISP_POSTMASK0		24
 #define MT8188_MUTEX_MOD2_DISP_PWM0		33

+#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA0	0
+#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA1	1
+#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA2	2
+#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA3	3
+#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA4	4
+#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA5	5
+#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA6	6
+#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA7	7
+#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE0	20
+#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE1	21
+#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE2	22
+#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE3	23
+#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE4	24
+#define MT8188_MUTEX_MOD_DISP1_DISP_MIXER	30
+#define MT8188_MUTEX_MOD_DISP1_DP_INTF1		39
+
 #define MT8195_MUTEX_MOD_DISP_OVL0		0
 #define MT8195_MUTEX_MOD_DISP_WDMA0		1
 #define MT8195_MUTEX_MOD_DISP_RDMA0		2
@@ -265,6 +281,7 @@
 #define MT8183_MUTEX_SOF_DPI0			2
 #define MT8188_MUTEX_SOF_DSI0			1
 #define MT8188_MUTEX_SOF_DP_INTF0		3
+#define MT8188_MUTEX_SOF_DP_INTF1		4
 #define MT8195_MUTEX_SOF_DSI0			1
 #define MT8195_MUTEX_SOF_DSI1			2
 #define MT8195_MUTEX_SOF_DP_INTF0		3
@@ -276,6 +293,7 @@
 #define MT8183_MUTEX_EOF_DPI0			(MT8183_MUTEX_SOF_DPI0 << 6)
 #define MT8188_MUTEX_EOF_DSI0			(MT8188_MUTEX_SOF_DSI0 << 7)
 #define MT8188_MUTEX_EOF_DP_INTF0		(MT8188_MUTEX_SOF_DP_INTF0 << 7)
+#define MT8188_MUTEX_EOF_DP_INTF1		(MT8188_MUTEX_SOF_DP_INTF1 << 7)
 #define MT8195_MUTEX_EOF_DSI0			(MT8195_MUTEX_SOF_DSI0 << 7)
 #define MT8195_MUTEX_EOF_DSI1			(MT8195_MUTEX_SOF_DSI1 << 7)
 #define MT8195_MUTEX_EOF_DP_INTF0		(MT8195_MUTEX_SOF_DP_INTF0 << 7)
@@ -446,6 +464,21 @@ static const unsigned int mt8188_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_DSI0] = MT8188_MUTEX_MOD_DISP_DSI0,
 	[DDP_COMPONENT_PWM0] = MT8188_MUTEX_MOD2_DISP_PWM0,
 	[DDP_COMPONENT_DP_INTF0] = MT8188_MUTEX_MOD_DISP_DP_INTF0,
+	[DDP_COMPONENT_MDP_RDMA0] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA0,
+	[DDP_COMPONENT_MDP_RDMA1] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA1,
+	[DDP_COMPONENT_MDP_RDMA2] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA2,
+	[DDP_COMPONENT_MDP_RDMA3] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA3,
+	[DDP_COMPONENT_MDP_RDMA4] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA4,
+	[DDP_COMPONENT_MDP_RDMA5] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA5,
+	[DDP_COMPONENT_MDP_RDMA6] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA6,
+	[DDP_COMPONENT_MDP_RDMA7] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA7,
+	[DDP_COMPONENT_MERGE1] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE0,
+	[DDP_COMPONENT_MERGE2] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE1,
+	[DDP_COMPONENT_MERGE3] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE2,
+	[DDP_COMPONENT_MERGE4] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE3,
+	[DDP_COMPONENT_ETHDR_MIXER] = MT8188_MUTEX_MOD_DISP1_DISP_MIXER,
+	[DDP_COMPONENT_MERGE5] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE4,
+	[DDP_COMPONENT_DP_INTF1] = MT8188_MUTEX_MOD_DISP1_DP_INTF1,
 };

 static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
@@ -606,6 +639,8 @@ static const unsigned int mt8188_mutex_sof[DDP_MUTEX_SOF_MAX] = {
 		MT8188_MUTEX_SOF_DSI0 | MT8188_MUTEX_EOF_DSI0,
 	[MUTEX_SOF_DP_INTF0] =
 		MT8188_MUTEX_SOF_DP_INTF0 | MT8188_MUTEX_EOF_DP_INTF0,
+	[MUTEX_SOF_DP_INTF1] =
+		MT8188_MUTEX_SOF_DP_INTF1 | MT8188_MUTEX_EOF_DP_INTF1,
 };

 static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
--
2.18.0

[PATCH v1 4/6] drm/mediatek: mt8188: Modify display driver for VDOSYS1

[Hsiao Chien Sung]

- Modify MUTEX and component preparation logic for better compatibility
- Adjust display module probe sequence to avoid probe deferral

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_disp_merge.c     |   3 +-
 .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c   | 100 ++++++++++--------
 drivers/gpu/drm/mediatek/mtk_drm_drv.c        |  28 ++++-
 drivers/gpu/drm/mediatek/mtk_ethdr.c          |   1 +
 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c       |   1 +
 5 files changed, 84 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
index 6428b6203ffe..2a30e41c246f 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
@@ -104,7 +104,7 @@ void mtk_merge_stop_cmdq(struct device *dev, struct cmdq_pkt *cmdq_pkt)
 	mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
 		      DISP_REG_MERGE_CTRL);

-	if (priv->async_clk)
+	if (!cmdq_pkt && priv->async_clk)
 		reset_control_reset(priv->reset_ctl);
 }

@@ -303,6 +303,7 @@ static int mtk_disp_merge_remove(struct platform_device *pdev)
 }

 static const struct of_device_id mtk_disp_merge_driver_dt_match[] = {
+	{ .compatible = "mediatek,mt8188-disp-merge", },
 	{ .compatible = "mediatek,mt8195-disp-merge", },
 	{},
 };
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
index c0a38f5217ee..e1d8d4765af8 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
@@ -51,6 +51,7 @@ enum mtk_ovl_adaptor_comp_id {

 struct ovl_adaptor_comp_match {
 	enum mtk_ovl_adaptor_comp_type type;
+	enum mtk_ddp_comp_id comp_id;
 	int alias_id;
 };

@@ -67,19 +68,19 @@ static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
 };

 static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {
-	[OVL_ADAPTOR_MDP_RDMA0]	= { OVL_ADAPTOR_TYPE_RDMA, 0 },
-	[OVL_ADAPTOR_MDP_RDMA1]	= { OVL_ADAPTOR_TYPE_RDMA, 1 },
-	[OVL_ADAPTOR_MDP_RDMA2]	= { OVL_ADAPTOR_TYPE_RDMA, 2 },
-	[OVL_ADAPTOR_MDP_RDMA3]	= { OVL_ADAPTOR_TYPE_RDMA, 3 },
-	[OVL_ADAPTOR_MDP_RDMA4]	= { OVL_ADAPTOR_TYPE_RDMA, 4 },
-	[OVL_ADAPTOR_MDP_RDMA5]	= { OVL_ADAPTOR_TYPE_RDMA, 5 },
-	[OVL_ADAPTOR_MDP_RDMA6]	= { OVL_ADAPTOR_TYPE_RDMA, 6 },
-	[OVL_ADAPTOR_MDP_RDMA7]	= { OVL_ADAPTOR_TYPE_RDMA, 7 },
-	[OVL_ADAPTOR_MERGE0]	= { OVL_ADAPTOR_TYPE_MERGE, 1 },
-	[OVL_ADAPTOR_MERGE1]	= { OVL_ADAPTOR_TYPE_MERGE, 2 },
-	[OVL_ADAPTOR_MERGE2]	= { OVL_ADAPTOR_TYPE_MERGE, 3 },
-	[OVL_ADAPTOR_MERGE3]	= { OVL_ADAPTOR_TYPE_MERGE, 4 },
-	[OVL_ADAPTOR_ETHDR0]	= { OVL_ADAPTOR_TYPE_ETHDR, 0 },
+	[OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA0, 0 },
+	[OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA1, 1 },
+	[OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA2, 2 },
+	[OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA3, 3 },
+	[OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA4, 4 },
+	[OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA5, 5 },
+	[OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA6, 6 },
+	[OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA7, 7 },
+	[OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE1, 1 },
+	[OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, 2 },
+	[OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, 3 },
+	[OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE4, 4 },
+	[OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, DDP_COMPONENT_ETHDR_MIXER, 0 },
 };

 void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
@@ -192,6 +193,8 @@ int mtk_ovl_adaptor_clk_enable(struct device *dev)

 	for (i = 0; i < OVL_ADAPTOR_MERGE0; i++) {
 		comp = ovl_adaptor->ovl_adaptor_comp[i];
+		if (!comp)
+			continue;
 		ret = pm_runtime_get_sync(comp);
 		if (ret < 0) {
 			dev_err(dev, "Failed to enable power domain %d, err %d\n", i, ret);
@@ -201,7 +204,8 @@ int mtk_ovl_adaptor_clk_enable(struct device *dev)

 	for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
 		comp = ovl_adaptor->ovl_adaptor_comp[i];
-
+		if (!comp)
+			continue;
 		if (i < OVL_ADAPTOR_MERGE0)
 			ret = mtk_mdp_rdma_clk_enable(comp);
 		else if (i < OVL_ADAPTOR_ETHDR0)
@@ -219,6 +223,8 @@ int mtk_ovl_adaptor_clk_enable(struct device *dev)
 clk_err:
 	while (--i >= 0) {
 		comp = ovl_adaptor->ovl_adaptor_comp[i];
+		if (!comp)
+			continue;
 		if (i < OVL_ADAPTOR_MERGE0)
 			mtk_mdp_rdma_clk_disable(comp);
 		else if (i < OVL_ADAPTOR_ETHDR0)
@@ -229,8 +235,12 @@ int mtk_ovl_adaptor_clk_enable(struct device *dev)
 	i = OVL_ADAPTOR_MERGE0;

 pwr_err:
-	while (--i >= 0)
-		pm_runtime_put(ovl_adaptor->ovl_adaptor_comp[i]);
+	while (--i >= 0) {
+		comp = ovl_adaptor->ovl_adaptor_comp[i];
+		if (!comp)
+			continue;
+		pm_runtime_put(comp);
+	}

 	return ret;
 }
@@ -243,7 +253,8 @@ void mtk_ovl_adaptor_clk_disable(struct device *dev)

 	for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
 		comp = ovl_adaptor->ovl_adaptor_comp[i];
-
+		if (!comp)
+			continue;
 		if (i < OVL_ADAPTOR_MERGE0) {
 			mtk_mdp_rdma_clk_disable(comp);
 			pm_runtime_put(comp);
@@ -313,36 +324,26 @@ size_t mtk_ovl_adaptor_get_num_formats(struct device *dev)

 void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex *mutex)
 {
-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA0);
-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA1);
-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA2);
-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA3);
-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA4);
-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA5);
-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA6);
-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA7);
-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE1);
-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE2);
-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE3);
-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE4);
-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
+	struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+	int i;
+
+	for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
+		if (!ovl_adaptor->ovl_adaptor_comp[i])
+			continue;
+		mtk_mutex_add_comp(mutex, comp_matches[i].comp_id);
+	}
 }

 void mtk_ovl_adaptor_remove_comp(struct device *dev, struct mtk_mutex *mutex)
 {
-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA0);
-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA1);
-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA2);
-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA3);
-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA4);
-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA5);
-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA6);
-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA7);
-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE1);
-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE2);
-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE3);
-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE4);
-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
+	struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+	int i;
+
+	for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
+		if (!ovl_adaptor->ovl_adaptor_comp[i])
+			continue;
+		mtk_mutex_remove_comp(mutex, comp_matches[i].comp_id);
+	}
 }

 void mtk_ovl_adaptor_connect(struct device *dev, struct device *mmsys_dev, unsigned int next)
@@ -386,6 +387,15 @@ static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node *node,

 static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
 	{
+		.compatible = "mediatek,mt8188-vdo1-rdma",
+		.data = (void *)OVL_ADAPTOR_TYPE_RDMA,
+	}, {
+		.compatible = "mediatek,mt8188-disp-merge",
+		.data = (void *)OVL_ADAPTOR_TYPE_MERGE,
+	}, {
+		.compatible = "mediatek,mt8188-disp-ethdr",
+		.data = (void *)OVL_ADAPTOR_TYPE_ETHDR,
+	}, {
 		.compatible = "mediatek,mt8195-vdo1-rdma",
 		.data = (void *)OVL_ADAPTOR_TYPE_RDMA,
 	}, {
@@ -466,6 +476,9 @@ static int mtk_disp_ovl_adaptor_comp_bind(struct device *dev, struct device *mas
 static void mtk_disp_ovl_adaptor_comp_unbind(struct device *dev, struct device *master,
 					     void *data)
 {
+	struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
+
+	priv->children_bound = false;
 }

 static const struct component_ops mtk_disp_ovl_adaptor_comp_ops = {
@@ -483,6 +496,7 @@ static int mtk_disp_ovl_adaptor_master_bind(struct device *dev)
 		return dev_err_probe(dev, ret, "component_bind_all failed!\n");

 	priv->children_bound = true;
+
 	return 0;
 }

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 6dcb4ba2466c..87dadd129c22 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -188,6 +188,12 @@ static const unsigned int mt8188_mtk_ddp_main[] = {
 	DDP_COMPONENT_DP_INTF0,
 };

+static const unsigned int mt8188_mtk_ddp_ext[] = {
+	DDP_COMPONENT_DRM_OVL_ADAPTOR,
+	DDP_COMPONENT_MERGE5,
+	DDP_COMPONENT_DP_INTF1,
+};
+
 static const unsigned int mt8192_mtk_ddp_main[] = {
 	DDP_COMPONENT_OVL0,
 	DDP_COMPONENT_OVL_2L0,
@@ -287,6 +293,14 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
 static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
 	.main_path = mt8188_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt8188_mtk_ddp_main),
+	.mmsys_dev_num = 2,
+};
+
+static const struct mtk_mmsys_driver_data mt8188_vdosys1_driver_data = {
+	.ext_path = mt8188_mtk_ddp_ext,
+	.ext_len = ARRAY_SIZE(mt8188_mtk_ddp_ext),
+	.mmsys_id = 1,
+	.mmsys_dev_num = 2,
 };

 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
@@ -327,6 +341,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
 	  .data = &mt8186_mmsys_driver_data},
 	{ .compatible = "mediatek,mt8188-vdosys0",
 	  .data = &mt8188_vdosys0_driver_data},
+	{ .compatible = "mediatek,mt8188-vdosys1",
+	  .data = &mt8188_vdosys1_driver_data},
 	{ .compatible = "mediatek,mt8192-mmsys",
 	  .data = &mt8192_mmsys_driver_data},
 	{ .compatible = "mediatek,mt8195-mmsys",
@@ -682,6 +698,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_GAMMA, },
 	{ .compatible = "mediatek,mt8183-disp-gamma",
 	  .data = (void *)MTK_DISP_GAMMA, },
+	{ .compatible = "mediatek,mt8188-disp-merge",
+	  .data = (void *)MTK_DISP_MERGE },
 	{ .compatible = "mediatek,mt8195-disp-merge",
 	  .data = (void *)MTK_DISP_MERGE },
 	{ .compatible = "mediatek,mt2701-disp-mutex",
@@ -965,15 +983,15 @@ static struct platform_driver * const mtk_drm_drivers[] = {
 	&mtk_disp_ccorr_driver,
 	&mtk_disp_color_driver,
 	&mtk_disp_gamma_driver,
+	&mtk_disp_rdma_driver,
+	&mtk_mdp_rdma_driver,
 	&mtk_disp_merge_driver,
-	&mtk_disp_ovl_adaptor_driver,
+	&mtk_ethdr_driver,
 	&mtk_disp_ovl_driver,
-	&mtk_disp_rdma_driver,
+	&mtk_disp_ovl_adaptor_driver,
+	&mtk_dsi_driver,
 	&mtk_dpi_driver,
 	&mtk_drm_platform_driver,
-	&mtk_dsi_driver,
-	&mtk_ethdr_driver,
-	&mtk_mdp_rdma_driver,
 };

 static int __init mtk_drm_init(void)
diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
index 73dc4da3ba3b..b5a6b67f2db9 100644
--- a/drivers/gpu/drm/mediatek/mtk_ethdr.c
+++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
@@ -353,6 +353,7 @@ static int mtk_ethdr_remove(struct platform_device *pdev)
 }

 static const struct of_device_id mtk_ethdr_driver_dt_match[] = {
+	{ .compatible = "mediatek,mt8188-disp-ethdr"},
 	{ .compatible = "mediatek,mt8195-disp-ethdr"},
 	{},
 };
diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
index e06db6e56b5f..06d5c9abb515 100644
--- a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
@@ -323,6 +323,7 @@ static int mtk_mdp_rdma_remove(struct platform_device *pdev)
 }

 static const struct of_device_id mtk_mdp_rdma_driver_dt_match[] = {
+	{ .compatible = "mediatek,mt8188-vdo1-rdma", },
 	{ .compatible = "mediatek,mt8195-vdo1-rdma", },
 	{},
 };
--
2.18.0

[PATCH v1 5/6] soc: mediatek: mt8188: Support VDOSYS1 PADDING in mtk-mmsys

[Hsiao Chien Sung]

- Add PADDING components
- Add MUTEX definitions for PADDING

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 drivers/soc/mediatek/mtk-mutex.c       | 16 ++++++++++++++++
 include/linux/soc/mediatek/mtk-mmsys.h |  8 ++++++++
 2 files changed, 24 insertions(+)

diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 11dda20eb462..39fe9650b7a2 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -142,6 +142,14 @@
 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA5	5
 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA6	6
 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA7	7
+#define MT8188_MUTEX_MOD_DISP1_PADDING0		8
+#define MT8188_MUTEX_MOD_DISP1_PADDING1		9
+#define MT8188_MUTEX_MOD_DISP1_PADDING2		10
+#define MT8188_MUTEX_MOD_DISP1_PADDING3		11
+#define MT8188_MUTEX_MOD_DISP1_PADDING4		12
+#define MT8188_MUTEX_MOD_DISP1_PADDING5		13
+#define MT8188_MUTEX_MOD_DISP1_PADDING6		14
+#define MT8188_MUTEX_MOD_DISP1_PADDING7		15
 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE0	20
 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE1	21
 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE2	22
@@ -472,6 +480,14 @@ static const unsigned int mt8188_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_MDP_RDMA5] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA5,
 	[DDP_COMPONENT_MDP_RDMA6] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA6,
 	[DDP_COMPONENT_MDP_RDMA7] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA7,
+	[DDP_COMPONENT_DISP_PADDING0] = MT8188_MUTEX_MOD_DISP1_PADDING0,
+	[DDP_COMPONENT_DISP_PADDING1] = MT8188_MUTEX_MOD_DISP1_PADDING1,
+	[DDP_COMPONENT_DISP_PADDING2] = MT8188_MUTEX_MOD_DISP1_PADDING2,
+	[DDP_COMPONENT_DISP_PADDING3] = MT8188_MUTEX_MOD_DISP1_PADDING3,
+	[DDP_COMPONENT_DISP_PADDING4] = MT8188_MUTEX_MOD_DISP1_PADDING4,
+	[DDP_COMPONENT_DISP_PADDING5] = MT8188_MUTEX_MOD_DISP1_PADDING5,
+	[DDP_COMPONENT_DISP_PADDING6] = MT8188_MUTEX_MOD_DISP1_PADDING6,
+	[DDP_COMPONENT_DISP_PADDING7] = MT8188_MUTEX_MOD_DISP1_PADDING7,
 	[DDP_COMPONENT_MERGE1] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE0,
 	[DDP_COMPONENT_MERGE2] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE1,
 	[DDP_COMPONENT_MERGE3] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE2,
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 37544ea6286d..63a599d6dd90 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -50,6 +50,14 @@ enum mtk_ddp_comp_id {
 	DDP_COMPONENT_MDP_RDMA5,
 	DDP_COMPONENT_MDP_RDMA6,
 	DDP_COMPONENT_MDP_RDMA7,
+	DDP_COMPONENT_DISP_PADDING0,
+	DDP_COMPONENT_DISP_PADDING1,
+	DDP_COMPONENT_DISP_PADDING2,
+	DDP_COMPONENT_DISP_PADDING3,
+	DDP_COMPONENT_DISP_PADDING4,
+	DDP_COMPONENT_DISP_PADDING5,
+	DDP_COMPONENT_DISP_PADDING6,
+	DDP_COMPONENT_DISP_PADDING7,
 	DDP_COMPONENT_MERGE0,
 	DDP_COMPONENT_MERGE1,
 	DDP_COMPONENT_MERGE2,
--
2.18.0

[PATCH v1 6/6] drm/mediatek: mt8188: Add VDOSYS1 PADDING driver

[Hsiao Chien Sung]

Add VDOSYS1 PADDING driver.

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 drivers/gpu/drm/mediatek/Makefile             |   1 +
 drivers/gpu/drm/mediatek/mtk_disp_drv.h       |   3 +
 .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c   |  43 +++++-
 drivers/gpu/drm/mediatek/mtk_disp_padding.c   | 134 ++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h   |   1 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c        |   1 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.h        |   2 +-
 7 files changed, 181 insertions(+), 4 deletions(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_padding.c

diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index d4d193f60271..753b7cb264d6 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -7,6 +7,7 @@ mediatek-drm-y := mtk_disp_aal.o \
 		  mtk_disp_merge.o \
 		  mtk_disp_ovl.o \
 		  mtk_disp_ovl_adaptor.o \
+		  mtk_disp_padding.o \
 		  mtk_disp_rdma.o \
 		  mtk_drm_crtc.o \
 		  mtk_drm_ddp_comp.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 2254038519e1..7200519a2670 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -157,4 +157,7 @@ void mtk_mdp_rdma_config(struct device *dev, struct mtk_mdp_rdma_cfg *cfg,
 const u32 *mtk_mdp_rdma_get_formats(struct device *dev);
 size_t mtk_mdp_rdma_get_num_formats(struct device *dev);

+int mtk_disp_padding_clk_enable(struct device *dev);
+void mtk_disp_padding_clk_disable(struct device *dev);
+void mtk_disp_padding_config(struct device *dev, struct cmdq_pkt *cmdq_pkt);
 #endif
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
index e1d8d4765af8..5f775144e8c1 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
@@ -27,6 +27,7 @@

 enum mtk_ovl_adaptor_comp_type {
 	OVL_ADAPTOR_TYPE_RDMA = 0,
+	OVL_ADAPTOR_TYPE_PADDING,
 	OVL_ADAPTOR_TYPE_MERGE,
 	OVL_ADAPTOR_TYPE_ETHDR,
 	OVL_ADAPTOR_TYPE_NUM,
@@ -41,6 +42,14 @@ enum mtk_ovl_adaptor_comp_id {
 	OVL_ADAPTOR_MDP_RDMA5,
 	OVL_ADAPTOR_MDP_RDMA6,
 	OVL_ADAPTOR_MDP_RDMA7,
+	OVL_ADAPTOR_DISP_PADDING0,
+	OVL_ADAPTOR_DISP_PADDING1,
+	OVL_ADAPTOR_DISP_PADDING2,
+	OVL_ADAPTOR_DISP_PADDING3,
+	OVL_ADAPTOR_DISP_PADDING4,
+	OVL_ADAPTOR_DISP_PADDING5,
+	OVL_ADAPTOR_DISP_PADDING6,
+	OVL_ADAPTOR_DISP_PADDING7,
 	OVL_ADAPTOR_MERGE0,
 	OVL_ADAPTOR_MERGE1,
 	OVL_ADAPTOR_MERGE2,
@@ -63,6 +72,7 @@ struct mtk_disp_ovl_adaptor {

 static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
 	[OVL_ADAPTOR_TYPE_RDMA]		= "vdo1-rdma",
+	[OVL_ADAPTOR_TYPE_PADDING]	= "vdo1-padding",
 	[OVL_ADAPTOR_TYPE_MERGE]	= "merge",
 	[OVL_ADAPTOR_TYPE_ETHDR]	= "ethdr",
 };
@@ -76,6 +86,14 @@ static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {
 	[OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA5, 5 },
 	[OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA6, 6 },
 	[OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA7, 7 },
+	[OVL_ADAPTOR_DISP_PADDING0] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_DISP_PADDING0, 0 },
+	[OVL_ADAPTOR_DISP_PADDING1] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_DISP_PADDING1, 1 },
+	[OVL_ADAPTOR_DISP_PADDING2] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_DISP_PADDING2, 2 },
+	[OVL_ADAPTOR_DISP_PADDING3] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_DISP_PADDING3, 3 },
+	[OVL_ADAPTOR_DISP_PADDING4] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_DISP_PADDING4, 4 },
+	[OVL_ADAPTOR_DISP_PADDING5] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_DISP_PADDING5, 5 },
+	[OVL_ADAPTOR_DISP_PADDING6] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_DISP_PADDING6, 6 },
+	[OVL_ADAPTOR_DISP_PADDING7] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_DISP_PADDING7, 7 },
 	[OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE1, 1 },
 	[OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, 2 },
 	[OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, 3 },
@@ -92,6 +110,8 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
 	struct mtk_mdp_rdma_cfg rdma_config = {0};
 	struct device *rdma_l;
 	struct device *rdma_r;
+	struct device *padding_l;
+	struct device *padding_r;
 	struct device *merge;
 	struct device *ethdr;
 	const struct drm_format_info *fmt_info = drm_format_info(pending->format);
@@ -108,6 +128,8 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,

 	rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx];
 	rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx + 1];
+	padding_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_DISP_PADDING0 + 2 * idx];
+	padding_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_DISP_PADDING0 + 2 * idx + 1];
 	merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx];
 	ethdr = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0];

@@ -143,10 +165,15 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
 	rdma_config.color_encoding = pending->color_encoding;
 	mtk_mdp_rdma_config(rdma_l, &rdma_config, cmdq_pkt);

+	if (padding_l)
+		mtk_disp_padding_config(padding_l, cmdq_pkt);
+
 	if (use_dual_pipe) {
 		rdma_config.x_left = l_w;
 		rdma_config.width = r_w;
 		mtk_mdp_rdma_config(rdma_r, &rdma_config, cmdq_pkt);
+		if (padding_r)
+			mtk_disp_padding_config(padding_r, cmdq_pkt);
 	}

 	mtk_merge_start_cmdq(merge, cmdq_pkt);
@@ -206,8 +233,10 @@ int mtk_ovl_adaptor_clk_enable(struct device *dev)
 		comp = ovl_adaptor->ovl_adaptor_comp[i];
 		if (!comp)
 			continue;
-		if (i < OVL_ADAPTOR_MERGE0)
+		if (i < OVL_ADAPTOR_DISP_PADDING0)
 			ret = mtk_mdp_rdma_clk_enable(comp);
+		else if (i < OVL_ADAPTOR_MERGE0)
+			ret = mtk_disp_padding_clk_enable(comp);
 		else if (i < OVL_ADAPTOR_ETHDR0)
 			ret = mtk_merge_clk_enable(comp);
 		else
@@ -225,8 +254,10 @@ int mtk_ovl_adaptor_clk_enable(struct device *dev)
 		comp = ovl_adaptor->ovl_adaptor_comp[i];
 		if (!comp)
 			continue;
-		if (i < OVL_ADAPTOR_MERGE0)
+		if (i < OVL_ADAPTOR_DISP_PADDING0)
 			mtk_mdp_rdma_clk_disable(comp);
+		else if (i < OVL_ADAPTOR_MERGE0)
+			mtk_disp_padding_clk_disable(comp);
 		else if (i < OVL_ADAPTOR_ETHDR0)
 			mtk_merge_clk_disable(comp);
 		else
@@ -255,9 +286,12 @@ void mtk_ovl_adaptor_clk_disable(struct device *dev)
 		comp = ovl_adaptor->ovl_adaptor_comp[i];
 		if (!comp)
 			continue;
-		if (i < OVL_ADAPTOR_MERGE0) {
+		if (i < OVL_ADAPTOR_DISP_PADDING0) {
 			mtk_mdp_rdma_clk_disable(comp);
 			pm_runtime_put(comp);
+		} else if (i < OVL_ADAPTOR_MERGE0) {
+			mtk_disp_padding_clk_disable(comp);
+			pm_runtime_put(comp);
 		} else if (i < OVL_ADAPTOR_ETHDR0) {
 			mtk_merge_clk_disable(comp);
 		} else {
@@ -389,6 +423,9 @@ static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
 	{
 		.compatible = "mediatek,mt8188-vdo1-rdma",
 		.data = (void *)OVL_ADAPTOR_TYPE_RDMA,
+	}, {
+		.compatible = "mediatek,mt8188-vdo1-padding",
+		.data = (void *)OVL_ADAPTOR_TYPE_PADDING,
 	}, {
 		.compatible = "mediatek,mt8188-disp-merge",
 		.data = (void *)OVL_ADAPTOR_TYPE_MERGE,
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_padding.c b/drivers/gpu/drm/mediatek/mtk_disp_padding.c
new file mode 100644
index 000000000000..5722aa57d628
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_padding.c
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_disp_drv.h"
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+
+/*
+ * struct mtk_disp_padding - DISP_RDMA driver structure
+ * @data: local driver data
+ */
+struct mtk_disp_padding {
+	struct clk		*clk;
+	void __iomem		*regs;
+	struct cmdq_client_reg	cmdq_reg;
+};
+
+static int mtk_disp_padding_bind(struct device *dev, struct device *master,
+				 void *data)
+{
+	return 0;
+}
+
+static void mtk_disp_padding_unbind(struct device *dev, struct device *master,
+				    void *data)
+{
+}
+
+static const struct component_ops mtk_disp_padding_component_ops = {
+	.bind	= mtk_disp_padding_bind,
+	.unbind = mtk_disp_padding_unbind,
+};
+
+static int mtk_disp_padding_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct mtk_disp_padding *priv;
+	struct resource *res;
+	int ret;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(priv->clk)) {
+		dev_err(dev, "failed to get clk\n");
+		return PTR_ERR(priv->clk);
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	priv->regs = devm_ioremap_resource(dev, res);
+	if (IS_ERR(priv->regs)) {
+		dev_err(dev, "failed to do ioremap\n");
+		return PTR_ERR(priv->regs);
+	}
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+	ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
+	if (ret) {
+		dev_err(dev, "failed to get gce client reg\n");
+		return ret;
+	}
+#endif
+
+	platform_set_drvdata(pdev, priv);
+
+	pm_runtime_enable(dev);
+
+	ret = component_add(dev, &mtk_disp_padding_component_ops);
+	if (ret) {
+		pm_runtime_disable(dev);
+		dev_err(dev, "failed to add component: %d\n", ret);
+	}
+
+	return ret;
+}
+
+static int mtk_disp_padding_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &mtk_disp_padding_component_ops);
+	pm_runtime_disable(&pdev->dev);
+	return 0;
+}
+
+static const struct of_device_id mtk_disp_padding_driver_dt_match[] = {
+	{ .compatible = "mediatek,mt8188-vdo1-padding" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, mtk_disp_padding_driver_dt_match);
+
+struct platform_driver mtk_disp_padding_driver = {
+	.probe		= mtk_disp_padding_probe,
+	.remove		= mtk_disp_padding_remove,
+	.driver		= {
+		.name	= "mediatek-disp-padding",
+		.owner	= THIS_MODULE,
+		.of_match_table = mtk_disp_padding_driver_dt_match,
+	},
+};
+
+int mtk_disp_padding_clk_enable(struct device *dev)
+{
+	struct mtk_disp_padding *padding = dev_get_drvdata(dev);
+
+	return clk_prepare_enable(padding->clk);
+}
+
+void mtk_disp_padding_clk_disable(struct device *dev)
+{
+	struct mtk_disp_padding *padding = dev_get_drvdata(dev);
+
+	clk_disable_unprepare(padding->clk);
+}
+
+void mtk_disp_padding_config(struct device *dev, struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_disp_padding *padding = dev_get_drvdata(dev);
+
+	// bypass padding
+	mtk_ddp_write_mask(cmdq_pkt,
+			   0b11, &padding->cmdq_reg, padding->regs, 0, 0b11);
+}
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index febcaeef16a1..d8145a99fb94 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -32,6 +32,7 @@ enum mtk_ddp_comp_type {
 	MTK_DISP_OVL,
 	MTK_DISP_OVL_2L,
 	MTK_DISP_OVL_ADAPTOR,
+	MTK_DISP_PADDING,
 	MTK_DISP_POSTMASK,
 	MTK_DISP_PWM,
 	MTK_DISP_RDMA,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 87dadd129c22..1c912bf43c35 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -985,6 +985,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
 	&mtk_disp_gamma_driver,
 	&mtk_disp_rdma_driver,
 	&mtk_mdp_rdma_driver,
+	&mtk_disp_padding_driver,
 	&mtk_disp_merge_driver,
 	&mtk_ethdr_driver,
 	&mtk_disp_ovl_driver,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index eb2fd45941f0..cb89d2c30019 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -64,5 +64,5 @@ extern struct platform_driver mtk_dpi_driver;
 extern struct platform_driver mtk_dsi_driver;
 extern struct platform_driver mtk_ethdr_driver;
 extern struct platform_driver mtk_mdp_rdma_driver;
-
+extern struct platform_driver mtk_disp_padding_driver;
 #endif /* MTK_DRM_DRV_H */
--
2.18.0

Re: [PATCH v1 1/6] dt-bindings: display/mediatek: mt8188: Add documentations for VDOSYS1

[Rob Herring]

On Wed, 07 Jun 2023 14:11:16 +0800, Hsiao Chien Sung wrote:
> Add device tree documentations for MT8188 VDOSYS1.
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
>  .../bindings/arm/mediatek/mediatek,mmsys.yaml |  1 +
>  .../display/mediatek/mediatek,ethdr.yaml      |  5 +-
>  .../display/mediatek/mediatek,mdp-rdma.yaml   |  5 +-
>  .../display/mediatek/mediatek,merge.yaml      |  1 +
>  .../display/mediatek/mediatek,padding.yaml    | 80 +++++++++++++++++++
>  5 files changed, 90 insertions(+), 2 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:
./Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml:28:9: [warning] wrong indentation: expected 10 but found 8 (indentation)
./Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml:26:9: [warning] wrong indentation: expected 10 but found 8 (indentation)

dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/display/mediatek/mediatek,padding.example.dts:19:18: fatal error: dt-bindings/clock/mt8188-clk.h: No such file or directory
   19 |         #include <dt-bindings/clock/mt8188-clk.h>
      |                  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:419: Documentation/devicetree/bindings/display/mediatek/mediatek,padding.example.dtb] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1512: dt_binding_check] Error 2

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230607061121.6732-2-shawn.sung@mediatek.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

Re: [PATCH v1 4/6] drm/mediatek: mt8188: Modify display driver for VDOSYS1

[AngeloGioacchino Del Regno]

Il 07/06/23 08:11, Hsiao Chien Sung ha scritto:
> - Modify MUTEX and component preparation logic for better compatibility
> - Adjust display module probe sequence to avoid probe deferral

Please split this in two commits, one modifying mutex/component preparation
logic, and one optimizing the probe sequence.

Also, you're adding MT8188 compatible strings without mentioning that anywhere.

Thanks,
Angelo

> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
>   drivers/gpu/drm/mediatek/mtk_disp_merge.c     |   3 +-
>   .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c   | 100 ++++++++++--------
>   drivers/gpu/drm/mediatek/mtk_drm_drv.c        |  28 ++++-
>   drivers/gpu/drm/mediatek/mtk_ethdr.c          |   1 +
>   drivers/gpu/drm/mediatek/mtk_mdp_rdma.c       |   1 +
>   5 files changed, 84 insertions(+), 49 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> index 6428b6203ffe..2a30e41c246f 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> @@ -104,7 +104,7 @@ void mtk_merge_stop_cmdq(struct device *dev, struct cmdq_pkt *cmdq_pkt)
>   	mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
>   		      DISP_REG_MERGE_CTRL);
> 
> -	if (priv->async_clk)
> +	if (!cmdq_pkt && priv->async_clk)
>   		reset_control_reset(priv->reset_ctl);
>   }
> 
> @@ -303,6 +303,7 @@ static int mtk_disp_merge_remove(struct platform_device *pdev)
>   }
> 
>   static const struct of_device_id mtk_disp_merge_driver_dt_match[] = {
> +	{ .compatible = "mediatek,mt8188-disp-merge", },
>   	{ .compatible = "mediatek,mt8195-disp-merge", },
>   	{},
>   };
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> index c0a38f5217ee..e1d8d4765af8 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> @@ -51,6 +51,7 @@ enum mtk_ovl_adaptor_comp_id {
> 
>   struct ovl_adaptor_comp_match {
>   	enum mtk_ovl_adaptor_comp_type type;
> +	enum mtk_ddp_comp_id comp_id;
>   	int alias_id;
>   };
> 
> @@ -67,19 +68,19 @@ static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
>   };
> 
>   static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {
> -	[OVL_ADAPTOR_MDP_RDMA0]	= { OVL_ADAPTOR_TYPE_RDMA, 0 },
> -	[OVL_ADAPTOR_MDP_RDMA1]	= { OVL_ADAPTOR_TYPE_RDMA, 1 },
> -	[OVL_ADAPTOR_MDP_RDMA2]	= { OVL_ADAPTOR_TYPE_RDMA, 2 },
> -	[OVL_ADAPTOR_MDP_RDMA3]	= { OVL_ADAPTOR_TYPE_RDMA, 3 },
> -	[OVL_ADAPTOR_MDP_RDMA4]	= { OVL_ADAPTOR_TYPE_RDMA, 4 },
> -	[OVL_ADAPTOR_MDP_RDMA5]	= { OVL_ADAPTOR_TYPE_RDMA, 5 },
> -	[OVL_ADAPTOR_MDP_RDMA6]	= { OVL_ADAPTOR_TYPE_RDMA, 6 },
> -	[OVL_ADAPTOR_MDP_RDMA7]	= { OVL_ADAPTOR_TYPE_RDMA, 7 },
> -	[OVL_ADAPTOR_MERGE0]	= { OVL_ADAPTOR_TYPE_MERGE, 1 },
> -	[OVL_ADAPTOR_MERGE1]	= { OVL_ADAPTOR_TYPE_MERGE, 2 },
> -	[OVL_ADAPTOR_MERGE2]	= { OVL_ADAPTOR_TYPE_MERGE, 3 },
> -	[OVL_ADAPTOR_MERGE3]	= { OVL_ADAPTOR_TYPE_MERGE, 4 },
> -	[OVL_ADAPTOR_ETHDR0]	= { OVL_ADAPTOR_TYPE_ETHDR, 0 },
> +	[OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA0, 0 },
> +	[OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA1, 1 },
> +	[OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA2, 2 },
> +	[OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA3, 3 },
> +	[OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA4, 4 },
> +	[OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA5, 5 },
> +	[OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA6, 6 },
> +	[OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA7, 7 },
> +	[OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE1, 1 },
> +	[OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, 2 },
> +	[OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, 3 },
> +	[OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE4, 4 },
> +	[OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, DDP_COMPONENT_ETHDR_MIXER, 0 },
>   };
> 
>   void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
> @@ -192,6 +193,8 @@ int mtk_ovl_adaptor_clk_enable(struct device *dev)
> 
>   	for (i = 0; i < OVL_ADAPTOR_MERGE0; i++) {
>   		comp = ovl_adaptor->ovl_adaptor_comp[i];
> +		if (!comp)
> +			continue;
>   		ret = pm_runtime_get_sync(comp);
>   		if (ret < 0) {
>   			dev_err(dev, "Failed to enable power domain %d, err %d\n", i, ret);
> @@ -201,7 +204,8 @@ int mtk_ovl_adaptor_clk_enable(struct device *dev)
> 
>   	for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
>   		comp = ovl_adaptor->ovl_adaptor_comp[i];
> -
> +		if (!comp)
> +			continue;
>   		if (i < OVL_ADAPTOR_MERGE0)
>   			ret = mtk_mdp_rdma_clk_enable(comp);
>   		else if (i < OVL_ADAPTOR_ETHDR0)
> @@ -219,6 +223,8 @@ int mtk_ovl_adaptor_clk_enable(struct device *dev)
>   clk_err:
>   	while (--i >= 0) {
>   		comp = ovl_adaptor->ovl_adaptor_comp[i];
> +		if (!comp)
> +			continue;
>   		if (i < OVL_ADAPTOR_MERGE0)
>   			mtk_mdp_rdma_clk_disable(comp);
>   		else if (i < OVL_ADAPTOR_ETHDR0)
> @@ -229,8 +235,12 @@ int mtk_ovl_adaptor_clk_enable(struct device *dev)
>   	i = OVL_ADAPTOR_MERGE0;
> 
>   pwr_err:
> -	while (--i >= 0)
> -		pm_runtime_put(ovl_adaptor->ovl_adaptor_comp[i]);
> +	while (--i >= 0) {
> +		comp = ovl_adaptor->ovl_adaptor_comp[i];
> +		if (!comp)
> +			continue;
> +		pm_runtime_put(comp);
> +	}
> 
>   	return ret;
>   }
> @@ -243,7 +253,8 @@ void mtk_ovl_adaptor_clk_disable(struct device *dev)
> 
>   	for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
>   		comp = ovl_adaptor->ovl_adaptor_comp[i];
> -
> +		if (!comp)
> +			continue;
>   		if (i < OVL_ADAPTOR_MERGE0) {
>   			mtk_mdp_rdma_clk_disable(comp);
>   			pm_runtime_put(comp);
> @@ -313,36 +324,26 @@ size_t mtk_ovl_adaptor_get_num_formats(struct device *dev)
> 
>   void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex *mutex)
>   {
> -	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA0);
> -	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA1);
> -	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA2);
> -	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA3);
> -	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA4);
> -	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA5);
> -	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA6);
> -	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA7);
> -	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE1);
> -	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE2);
> -	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE3);
> -	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE4);
> -	mtk_mutex_add_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
> +	struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> +	int i;
> +
> +	for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
> +		if (!ovl_adaptor->ovl_adaptor_comp[i])
> +			continue;
> +		mtk_mutex_add_comp(mutex, comp_matches[i].comp_id);
> +	}
>   }
> 
>   void mtk_ovl_adaptor_remove_comp(struct device *dev, struct mtk_mutex *mutex)
>   {
> -	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA0);
> -	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA1);
> -	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA2);
> -	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA3);
> -	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA4);
> -	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA5);
> -	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA6);
> -	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA7);
> -	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE1);
> -	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE2);
> -	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE3);
> -	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE4);
> -	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
> +	struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> +	int i;
> +
> +	for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
> +		if (!ovl_adaptor->ovl_adaptor_comp[i])
> +			continue;
> +		mtk_mutex_remove_comp(mutex, comp_matches[i].comp_id);
> +	}
>   }
> 
>   void mtk_ovl_adaptor_connect(struct device *dev, struct device *mmsys_dev, unsigned int next)
> @@ -386,6 +387,15 @@ static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node *node,
> 
>   static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
>   	{
> +		.compatible = "mediatek,mt8188-vdo1-rdma",
> +		.data = (void *)OVL_ADAPTOR_TYPE_RDMA,
> +	}, {
> +		.compatible = "mediatek,mt8188-disp-merge",
> +		.data = (void *)OVL_ADAPTOR_TYPE_MERGE,
> +	}, {
> +		.compatible = "mediatek,mt8188-disp-ethdr",
> +		.data = (void *)OVL_ADAPTOR_TYPE_ETHDR,
> +	}, {
>   		.compatible = "mediatek,mt8195-vdo1-rdma",
>   		.data = (void *)OVL_ADAPTOR_TYPE_RDMA,
>   	}, {
> @@ -466,6 +476,9 @@ static int mtk_disp_ovl_adaptor_comp_bind(struct device *dev, struct device *mas
>   static void mtk_disp_ovl_adaptor_comp_unbind(struct device *dev, struct device *master,
>   					     void *data)
>   {
> +	struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
> +
> +	priv->children_bound = false;
>   }
> 
>   static const struct component_ops mtk_disp_ovl_adaptor_comp_ops = {
> @@ -483,6 +496,7 @@ static int mtk_disp_ovl_adaptor_master_bind(struct device *dev)
>   		return dev_err_probe(dev, ret, "component_bind_all failed!\n");
> 
>   	priv->children_bound = true;
> +
>   	return 0;
>   }
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 6dcb4ba2466c..87dadd129c22 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -188,6 +188,12 @@ static const unsigned int mt8188_mtk_ddp_main[] = {
>   	DDP_COMPONENT_DP_INTF0,
>   };
> 
> +static const unsigned int mt8188_mtk_ddp_ext[] = {
> +	DDP_COMPONENT_DRM_OVL_ADAPTOR,
> +	DDP_COMPONENT_MERGE5,
> +	DDP_COMPONENT_DP_INTF1,
> +};
> +
>   static const unsigned int mt8192_mtk_ddp_main[] = {
>   	DDP_COMPONENT_OVL0,
>   	DDP_COMPONENT_OVL_2L0,
> @@ -287,6 +293,14 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
>   static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
>   	.main_path = mt8188_mtk_ddp_main,
>   	.main_len = ARRAY_SIZE(mt8188_mtk_ddp_main),
> +	.mmsys_dev_num = 2,
> +};
> +
> +static const struct mtk_mmsys_driver_data mt8188_vdosys1_driver_data = {
> +	.ext_path = mt8188_mtk_ddp_ext,
> +	.ext_len = ARRAY_SIZE(mt8188_mtk_ddp_ext),
> +	.mmsys_id = 1,
> +	.mmsys_dev_num = 2,
>   };
> 
>   static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
> @@ -327,6 +341,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
>   	  .data = &mt8186_mmsys_driver_data},
>   	{ .compatible = "mediatek,mt8188-vdosys0",
>   	  .data = &mt8188_vdosys0_driver_data},
> +	{ .compatible = "mediatek,mt8188-vdosys1",
> +	  .data = &mt8188_vdosys1_driver_data},
>   	{ .compatible = "mediatek,mt8192-mmsys",
>   	  .data = &mt8192_mmsys_driver_data},
>   	{ .compatible = "mediatek,mt8195-mmsys",
> @@ -682,6 +698,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>   	  .data = (void *)MTK_DISP_GAMMA, },
>   	{ .compatible = "mediatek,mt8183-disp-gamma",
>   	  .data = (void *)MTK_DISP_GAMMA, },
> +	{ .compatible = "mediatek,mt8188-disp-merge",
> +	  .data = (void *)MTK_DISP_MERGE },
>   	{ .compatible = "mediatek,mt8195-disp-merge",
>   	  .data = (void *)MTK_DISP_MERGE },
>   	{ .compatible = "mediatek,mt2701-disp-mutex",
> @@ -965,15 +983,15 @@ static struct platform_driver * const mtk_drm_drivers[] = {
>   	&mtk_disp_ccorr_driver,
>   	&mtk_disp_color_driver,
>   	&mtk_disp_gamma_driver,
> +	&mtk_disp_rdma_driver,
> +	&mtk_mdp_rdma_driver,
>   	&mtk_disp_merge_driver,
> -	&mtk_disp_ovl_adaptor_driver,
> +	&mtk_ethdr_driver,
>   	&mtk_disp_ovl_driver,
> -	&mtk_disp_rdma_driver,
> +	&mtk_disp_ovl_adaptor_driver,
> +	&mtk_dsi_driver,
>   	&mtk_dpi_driver,
>   	&mtk_drm_platform_driver,
> -	&mtk_dsi_driver,
> -	&mtk_ethdr_driver,
> -	&mtk_mdp_rdma_driver,
>   };
> 
>   static int __init mtk_drm_init(void)
> diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> index 73dc4da3ba3b..b5a6b67f2db9 100644
> --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c
> +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> @@ -353,6 +353,7 @@ static int mtk_ethdr_remove(struct platform_device *pdev)
>   }
> 
>   static const struct of_device_id mtk_ethdr_driver_dt_match[] = {
> +	{ .compatible = "mediatek,mt8188-disp-ethdr"},
>   	{ .compatible = "mediatek,mt8195-disp-ethdr"},
>   	{},
>   };
> diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> index e06db6e56b5f..06d5c9abb515 100644
> --- a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> @@ -323,6 +323,7 @@ static int mtk_mdp_rdma_remove(struct platform_device *pdev)
>   }
> 
>   static const struct of_device_id mtk_mdp_rdma_driver_dt_match[] = {
> +	{ .compatible = "mediatek,mt8188-vdo1-rdma", },
>   	{ .compatible = "mediatek,mt8195-vdo1-rdma", },
>   	{},
>   };
> --
> 2.18.0
> 

Re: [PATCH v1 1/6] dt-bindings: display/mediatek: mt8188: Add documentations for VDOSYS1

[Krzysztof Kozlowski]

On 07/06/2023 08:11, Hsiao Chien Sung wrote:
> Add device tree documentations for MT8188 VDOSYS1.

It does not look like you tested the bindings, at least after quick
look. Please run `make dt_binding_check` (see
Documentation/devicetree/bindings/writing-schema.rst for instructions).
Maybe you need to update your dtschema and yamllint.

> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml
> new file mode 100644
> index 000000000000..8a9e74cbf6dc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml
> @@ -0,0 +1,80 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,padding.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek PADDING
> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description:
> +  MediaTek PADDING provides ability to VDOSYS1 to fill pixels to
> +  width and height of a layer with a specified color.
> +  Since MIXER in VDOSYS1 requires the width of a layer to be 2-pixel-align, or
> +  4-pixel-align when ETHDR is enabled, we need PADDING to deal with odd width.
> +  Please notice that even if the PADDING is in bypass mode,
> +  settings in the registers must be cleared to 0, otherwise
> +  undeinfed behaviors could happen.

Typo, undefined

> +



> +required:
> +  - compatible
> +  - reg
> +  - power-domains
> +  - clocks
> +  - mediatek,gce-client-reg
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/clock/mt8188-clk.h>
> +    #include <dt-bindings/power/mt8188-power.h>
> +    #include <dt-bindings/gce/mt8188-gce.h>
> +    #include <dt-bindings/memory/mt8188-memory-port.h>
> +
> +    soc {
> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +
> +        vdo1_padding0: vdo1_padding0@1c11d000 {

No underscores in node names.

Node names should be generic. See also explanation and list of examples
in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation

> +            compatible = "mediatek,mt8188-vdo1-padding";
> +            reg = <0 0x1c11d000 0 0x1000>;
> +            clocks = <&vdosys1 CLK_VDO1_PADDING0>;
> +            power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
> +            mediatek,gce-client-reg =
> +                <&gce0 SUBSYS_1c11XXXX 0xd000 0x1000>;

Wrong wrapping. It's one line. Properties should not be wrapped after '='.


Best regards,
Krzysztof

Re: [PATCH v1 2/6] dt-bindings: reset: mt8188: Add reset control bits for VDOSYS1

[Krzysztof Kozlowski]

On 07/06/2023 08:11, Hsiao Chien Sung wrote:
> Add reset control bits for  MT8188 VDOSYS1.

Double space -> one space.

> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
>  include/dt-bindings/reset/mt8188-resets.h | 12 ++++++++++++

This should be squashed with patch adding compatible.


>  1 file changed, 12 insertions(+)
> 
> diff --git a/include/dt-bindings/reset/mt8188-resets.h b/include/dt-bindings/reset/mt8188-resets.h
> index 377cdfda82a9..439a9a25ca19 100644
> --- a/include/dt-bindings/reset/mt8188-resets.h
> +++ b/include/dt-bindings/reset/mt8188-resets.h
> @@ -33,4 +33,16 @@
> 
>  #define MT8188_TOPRGU_SW_RST_NUM               24
> 
> +/* VDOSYS1 */
> +#define MT8188_VDO1_RST_MERGE0_DL_ASYNC         9

Indices start from 0.

> +#define MT8188_VDO1_RST_MERGE1_DL_ASYNC         10
> +#define MT8188_VDO1_RST_MERGE2_DL_ASYNC         11
> +#define MT8188_VDO1_RST_MERGE3_DL_ASYNC         32

... and are continuous.

Commit explains here nothing that it is for existing reset, so you got
such review.

Best regards,
Krzysztof

Re: [PATCH v1 6/6] drm/mediatek: mt8188: Add VDOSYS1 PADDING driver

[AngeloGioacchino Del Regno]

Il 07/06/23 08:11, Hsiao Chien Sung ha scritto:
> Add VDOSYS1 PADDING driver.

Please expand on the commit description, say what PADDING does, what is it for.

> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
>   drivers/gpu/drm/mediatek/Makefile             |   1 +
>   drivers/gpu/drm/mediatek/mtk_disp_drv.h       |   3 +
>   .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c   |  43 +++++-
>   drivers/gpu/drm/mediatek/mtk_disp_padding.c   | 134 ++++++++++++++++++
>   drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h   |   1 +
>   drivers/gpu/drm/mediatek/mtk_drm_drv.c        |   1 +
>   drivers/gpu/drm/mediatek/mtk_drm_drv.h        |   2 +-
>   7 files changed, 181 insertions(+), 4 deletions(-)
>   create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_padding.c
> 
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index d4d193f60271..753b7cb264d6 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -7,6 +7,7 @@ mediatek-drm-y := mtk_disp_aal.o \
>   		  mtk_disp_merge.o \
>   		  mtk_disp_ovl.o \
>   		  mtk_disp_ovl_adaptor.o \
> +		  mtk_disp_padding.o \
>   		  mtk_disp_rdma.o \
>   		  mtk_drm_crtc.o \
>   		  mtk_drm_ddp_comp.o \
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index 2254038519e1..7200519a2670 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -157,4 +157,7 @@ void mtk_mdp_rdma_config(struct device *dev, struct mtk_mdp_rdma_cfg *cfg,
>   const u32 *mtk_mdp_rdma_get_formats(struct device *dev);
>   size_t mtk_mdp_rdma_get_num_formats(struct device *dev);
> 
> +int mtk_disp_padding_clk_enable(struct device *dev);
> +void mtk_disp_padding_clk_disable(struct device *dev);
> +void mtk_disp_padding_config(struct device *dev, struct cmdq_pkt *cmdq_pkt);
>   #endif
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> index e1d8d4765af8..5f775144e8c1 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> @@ -27,6 +27,7 @@
> 
>   enum mtk_ovl_adaptor_comp_type {
>   	OVL_ADAPTOR_TYPE_RDMA = 0,
> +	OVL_ADAPTOR_TYPE_PADDING,
>   	OVL_ADAPTOR_TYPE_MERGE,
>   	OVL_ADAPTOR_TYPE_ETHDR,
>   	OVL_ADAPTOR_TYPE_NUM,
> @@ -41,6 +42,14 @@ enum mtk_ovl_adaptor_comp_id {
>   	OVL_ADAPTOR_MDP_RDMA5,
>   	OVL_ADAPTOR_MDP_RDMA6,
>   	OVL_ADAPTOR_MDP_RDMA7,
> +	OVL_ADAPTOR_DISP_PADDING0,
> +	OVL_ADAPTOR_DISP_PADDING1,
> +	OVL_ADAPTOR_DISP_PADDING2,
> +	OVL_ADAPTOR_DISP_PADDING3,
> +	OVL_ADAPTOR_DISP_PADDING4,
> +	OVL_ADAPTOR_DISP_PADDING5,
> +	OVL_ADAPTOR_DISP_PADDING6,
> +	OVL_ADAPTOR_DISP_PADDING7,
>   	OVL_ADAPTOR_MERGE0,
>   	OVL_ADAPTOR_MERGE1,
>   	OVL_ADAPTOR_MERGE2,
> @@ -63,6 +72,7 @@ struct mtk_disp_ovl_adaptor {
> 
>   static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
>   	[OVL_ADAPTOR_TYPE_RDMA]		= "vdo1-rdma",
> +	[OVL_ADAPTOR_TYPE_PADDING]	= "vdo1-padding",
>   	[OVL_ADAPTOR_TYPE_MERGE]	= "merge",
>   	[OVL_ADAPTOR_TYPE_ETHDR]	= "ethdr",
>   };
> @@ -76,6 +86,14 @@ static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {
>   	[OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA5, 5 },
>   	[OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA6, 6 },
>   	[OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA7, 7 },
> +	[OVL_ADAPTOR_DISP_PADDING0] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_DISP_PADDING0, 0 },
> +	[OVL_ADAPTOR_DISP_PADDING1] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_DISP_PADDING1, 1 },
> +	[OVL_ADAPTOR_DISP_PADDING2] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_DISP_PADDING2, 2 },
> +	[OVL_ADAPTOR_DISP_PADDING3] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_DISP_PADDING3, 3 },
> +	[OVL_ADAPTOR_DISP_PADDING4] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_DISP_PADDING4, 4 },
> +	[OVL_ADAPTOR_DISP_PADDING5] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_DISP_PADDING5, 5 },
> +	[OVL_ADAPTOR_DISP_PADDING6] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_DISP_PADDING6, 6 },
> +	[OVL_ADAPTOR_DISP_PADDING7] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_DISP_PADDING7, 7 },
>   	[OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE1, 1 },
>   	[OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, 2 },
>   	[OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, 3 },
> @@ -92,6 +110,8 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
>   	struct mtk_mdp_rdma_cfg rdma_config = {0};
>   	struct device *rdma_l;
>   	struct device *rdma_r;
> +	struct device *padding_l;
> +	struct device *padding_r;
>   	struct device *merge;
>   	struct device *ethdr;
>   	const struct drm_format_info *fmt_info = drm_format_info(pending->format);
> @@ -108,6 +128,8 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
> 
>   	rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx];
>   	rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx + 1];
> +	padding_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_DISP_PADDING0 + 2 * idx];
> +	padding_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_DISP_PADDING0 + 2 * idx + 1];
>   	merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx];
>   	ethdr = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0];
> 
> @@ -143,10 +165,15 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
>   	rdma_config.color_encoding = pending->color_encoding;
>   	mtk_mdp_rdma_config(rdma_l, &rdma_config, cmdq_pkt);
> 
> +	if (padding_l)
> +		mtk_disp_padding_config(padding_l, cmdq_pkt);
> +
>   	if (use_dual_pipe) {
>   		rdma_config.x_left = l_w;
>   		rdma_config.width = r_w;
>   		mtk_mdp_rdma_config(rdma_r, &rdma_config, cmdq_pkt);
> +		if (padding_r)
> +			mtk_disp_padding_config(padding_r, cmdq_pkt);
>   	}
> 
>   	mtk_merge_start_cmdq(merge, cmdq_pkt);
> @@ -206,8 +233,10 @@ int mtk_ovl_adaptor_clk_enable(struct device *dev)
>   		comp = ovl_adaptor->ovl_adaptor_comp[i];
>   		if (!comp)
>   			continue;
> -		if (i < OVL_ADAPTOR_MERGE0)
> +		if (i < OVL_ADAPTOR_DISP_PADDING0)
>   			ret = mtk_mdp_rdma_clk_enable(comp);
> +		else if (i < OVL_ADAPTOR_MERGE0)
> +			ret = mtk_disp_padding_clk_enable(comp);
>   		else if (i < OVL_ADAPTOR_ETHDR0)
>   			ret = mtk_merge_clk_enable(comp);
>   		else
> @@ -225,8 +254,10 @@ int mtk_ovl_adaptor_clk_enable(struct device *dev)
>   		comp = ovl_adaptor->ovl_adaptor_comp[i];
>   		if (!comp)
>   			continue;
> -		if (i < OVL_ADAPTOR_MERGE0)
> +		if (i < OVL_ADAPTOR_DISP_PADDING0)
>   			mtk_mdp_rdma_clk_disable(comp);
> +		else if (i < OVL_ADAPTOR_MERGE0)
> +			mtk_disp_padding_clk_disable(comp);
>   		else if (i < OVL_ADAPTOR_ETHDR0)
>   			mtk_merge_clk_disable(comp);
>   		else
> @@ -255,9 +286,12 @@ void mtk_ovl_adaptor_clk_disable(struct device *dev)
>   		comp = ovl_adaptor->ovl_adaptor_comp[i];
>   		if (!comp)
>   			continue;
> -		if (i < OVL_ADAPTOR_MERGE0) {
> +		if (i < OVL_ADAPTOR_DISP_PADDING0) {

Now we're counting three branches. I'd say that a switch() would be a better
fit at this point.

>   			mtk_mdp_rdma_clk_disable(comp);
>   			pm_runtime_put(comp);
> +		} else if (i < OVL_ADAPTOR_MERGE0) {
> +			mtk_disp_padding_clk_disable(comp);
> +			pm_runtime_put(comp);
>   		} else if (i < OVL_ADAPTOR_ETHDR0) {
>   			mtk_merge_clk_disable(comp);
>   		} else {
> @@ -389,6 +423,9 @@ static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
>   	{
>   		.compatible = "mediatek,mt8188-vdo1-rdma",
>   		.data = (void *)OVL_ADAPTOR_TYPE_RDMA,
> +	}, {
> +		.compatible = "mediatek,mt8188-vdo1-padding",
> +		.data = (void *)OVL_ADAPTOR_TYPE_PADDING,
>   	}, {
>   		.compatible = "mediatek,mt8188-disp-merge",
>   		.data = (void *)OVL_ADAPTOR_TYPE_MERGE,
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_padding.c b/drivers/gpu/drm/mediatek/mtk_disp_padding.c
> new file mode 100644
> index 000000000000..5722aa57d628
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_padding.c
> @@ -0,0 +1,134 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2022 MediaTek Inc.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/of_irq.h>

I don't see any interrupt parsing action here, why are you including of_irq.h?

> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_disp_drv.h"
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +
> +/*

For kerneldoc, this should be:

/**

> + * struct mtk_disp_padding - DISP_RDMA driver structure

Also, this is not the DISP_RDMA driver structure

> + * @data: local driver data

...and there's no @data member, plus, you're not documenting other members.

> + */
> +struct mtk_disp_padding {
> +	struct clk		*clk;
> +	void __iomem		*regs;
> +	struct cmdq_client_reg	cmdq_reg;
> +};
> +
> +static int mtk_disp_padding_bind(struct device *dev, struct device *master,
> +				 void *data)
> +{
> +	return 0;
> +}
> +
> +static void mtk_disp_padding_unbind(struct device *dev, struct device *master,
> +				    void *data)
> +{
> +}
> +
> +static const struct component_ops mtk_disp_padding_component_ops = {
> +	.bind	= mtk_disp_padding_bind,
> +	.unbind = mtk_disp_padding_unbind,
> +};
> +
> +static int mtk_disp_padding_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct mtk_disp_padding *priv;
> +	struct resource *res;
> +	int ret;
> +
> +	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> +	if (!priv)
> +		return -ENOMEM;
> +
> +	priv->clk = devm_clk_get(dev, NULL);
> +	if (IS_ERR(priv->clk)) {
> +		dev_err(dev, "failed to get clk\n");
> +		return PTR_ERR(priv->clk);
> +	}
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	priv->regs = devm_ioremap_resource(dev, res);

priv->regs = devm_platform_get_and_ioremap_resource(pdev, 0, res);

> +	if (IS_ERR(priv->regs)) {
> +		dev_err(dev, "failed to do ioremap\n");
> +		return PTR_ERR(priv->regs);
> +	}
> +
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> +	ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
> +	if (ret) {
> +		dev_err(dev, "failed to get gce client reg\n");
> +		return ret;
> +	}
> +#endif
> +
> +	platform_set_drvdata(pdev, priv);
> +
> +	pm_runtime_enable(dev);

	ret = devm_pm_runtime_enable(dev);
	if (ret)
		return ret;

> +
> +	ret = component_add(dev, &mtk_disp_padding_component_ops);
> +	if (ret) {
> +		pm_runtime_disable(dev);
> +		dev_err(dev, "failed to add component: %d\n", ret);

	return dev_err_probe( .... )

> +	}
> +
> +	return ret;

return 0;

> +}
> +
> +static int mtk_disp_padding_remove(struct platform_device *pdev)
> +{
> +	component_del(&pdev->dev, &mtk_disp_padding_component_ops);
> +	pm_runtime_disable(&pdev->dev);

If you use devm_pm_runtime_enable, you don't have to call pm_runtime_disable here.

> +	return 0;
> +}
> +
> +static const struct of_device_id mtk_disp_padding_driver_dt_match[] = {
> +	{ .compatible = "mediatek,mt8188-vdo1-padding" },
> +	{},

	{ /* sentinel */ }
}

> +};
> +MODULE_DEVICE_TABLE(of, mtk_disp_padding_driver_dt_match);
> +
> +struct platform_driver mtk_disp_padding_driver = {
> +	.probe		= mtk_disp_padding_probe,
> +	.remove		= mtk_disp_padding_remove,
> +	.driver		= {
> +		.name	= "mediatek-disp-padding",
> +		.owner	= THIS_MODULE,
> +		.of_match_table = mtk_disp_padding_driver_dt_match,
> +	},
> +};
> +
> +int mtk_disp_padding_clk_enable(struct device *dev)
> +{
> +	struct mtk_disp_padding *padding = dev_get_drvdata(dev);
> +
> +	return clk_prepare_enable(padding->clk);
> +}
> +
> +void mtk_disp_padding_clk_disable(struct device *dev)
> +{
> +	struct mtk_disp_padding *padding = dev_get_drvdata(dev);
> +
> +	clk_disable_unprepare(padding->clk);
> +}
> +
> +void mtk_disp_padding_config(struct device *dev, struct cmdq_pkt *cmdq_pkt)
> +{
> +	struct mtk_disp_padding *padding = dev_get_drvdata(dev);
> +
> +	// bypass padding

C-style comments please.

> +	mtk_ddp_write_mask(cmdq_pkt,
> +			   0b11, &padding->cmdq_reg, padding->regs, 0, 0b11);

Please add definitions and use GENMASK().

> +}

Move those functions before the probe function please.

Regards,
Angelo

Re: [PATCH v1 2/6] dt-bindings: reset: mt8188: Add reset control bits for VDOSYS1

[AngeloGioacchino Del Regno]

Il 07/06/23 08:11, Hsiao Chien Sung ha scritto:
> Add reset control bits for  MT8188 VDOSYS1.
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Re: [PATCH v1 2/6] dt-bindings: reset: mt8188: Add reset control bits for VDOSYS1

[AngeloGioacchino Del Regno]

Il 07/06/23 08:11, Hsiao Chien Sung ha scritto:
> Add reset control bits for  MT8188 VDOSYS1.
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
>   include/dt-bindings/reset/mt8188-resets.h | 12 ++++++++++++
>   1 file changed, 12 insertions(+)
> 
> diff --git a/include/dt-bindings/reset/mt8188-resets.h b/include/dt-bindings/reset/mt8188-resets.h
> index 377cdfda82a9..439a9a25ca19 100644
> --- a/include/dt-bindings/reset/mt8188-resets.h
> +++ b/include/dt-bindings/reset/mt8188-resets.h
> @@ -33,4 +33,16 @@
> 
>   #define MT8188_TOPRGU_SW_RST_NUM               24
> 
> +/* VDOSYS1 */
> +#define MT8188_VDO1_RST_MERGE0_DL_ASYNC         9

Sorry, I've just noticed that there's no index 0 in previous definitions: this
is wrong, it must start from 0 and must be sequential.

Re: [PATCH v1 2/6] dt-bindings: reset: mt8188: Add reset control bits for VDOSYS1

[Shawn Sung (宋孝謙)]

Hi AngeloGioacchino,

Should I use enum instead of #define if reset ID must starts from 0?

Thanks,
Hsiao Chien Sung

On Wed, 2023-06-07 at 09:51 +0200, AngeloGioacchino Del Regno wrote:
>  	 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>  
> Il 07/06/23 08:11, Hsiao Chien Sung ha scritto:
> > Add reset control bits for  MT8188 VDOSYS1.
> > 
> > Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> > ---
> >   include/dt-bindings/reset/mt8188-resets.h | 12 ++++++++++++
> >   1 file changed, 12 insertions(+)
> > 
> > diff --git a/include/dt-bindings/reset/mt8188-resets.h
> b/include/dt-bindings/reset/mt8188-resets.h
> > index 377cdfda82a9..439a9a25ca19 100644
> > --- a/include/dt-bindings/reset/mt8188-resets.h
> > +++ b/include/dt-bindings/reset/mt8188-resets.h
> > @@ -33,4 +33,16 @@
> > 
> >   #define MT8188_TOPRGU_SW_RST_NUM               24
> > 
> > +/* VDOSYS1 */
> > +#define MT8188_VDO1_RST_MERGE0_DL_ASYNC         9
> 
> Sorry, I've just noticed that there's no index 0 in previous
> definitions: this
> is wrong, it must start from 0 and must be sequential.
> 
> 

Re: [PATCH v1 2/6] dt-bindings: reset: mt8188: Add reset control bits for VDOSYS1

[Shawn Sung (宋孝謙)]

Hi Krzysztof,

Got it, I'll squash this commit with the one adds compatible, and
commit another patch to modify mmsys reset control to handle the new
rule of indexing.

Thanks,
Hsiao Chien Sung

On Wed, 2023-06-07 at 09:27 +0200, Krzysztof Kozlowski wrote:
>  	 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>  
> On 07/06/2023 08:11, Hsiao Chien Sung wrote:
> > Add reset control bits for  MT8188 VDOSYS1.
> 
> Double space -> one space.
> 
> > 
> > Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> > ---
> >  include/dt-bindings/reset/mt8188-resets.h | 12 ++++++++++++
> 
> This should be squashed with patch adding compatible.
> 
> 
> >  1 file changed, 12 insertions(+)
> > 
> > diff --git a/include/dt-bindings/reset/mt8188-resets.h
> b/include/dt-bindings/reset/mt8188-resets.h
> > index 377cdfda82a9..439a9a25ca19 100644
> > --- a/include/dt-bindings/reset/mt8188-resets.h
> > +++ b/include/dt-bindings/reset/mt8188-resets.h
> > @@ -33,4 +33,16 @@
> > 
> >  #define MT8188_TOPRGU_SW_RST_NUM               24
> > 
> > +/* VDOSYS1 */
> > +#define MT8188_VDO1_RST_MERGE0_DL_ASYNC         9
> 
> Indices start from 0.
> 
> > +#define MT8188_VDO1_RST_MERGE1_DL_ASYNC         10
> > +#define MT8188_VDO1_RST_MERGE2_DL_ASYNC         11
> > +#define MT8188_VDO1_RST_MERGE3_DL_ASYNC         32
> 
> ... and are continuous.
> 
> Commit explains here nothing that it is for existing reset, so you
> got
> such review.
> 
> Best regards,
> Krzysztof
> 

Re: [PATCH v1 1/6] dt-bindings: display/mediatek: mt8188: Add documentations for VDOSYS1

[Shawn Sung (宋孝謙)]

Hi Krzysztof,

Sorry, I missed this step in my SOP.
Will follow the instruction below to check again,
thank you for the information.

Best regards,
Hsiao Chien Sung

On Wed, 2023-06-07 at 09:26 +0200, Krzysztof Kozlowski wrote:
>  	 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>  
> On 07/06/2023 08:11, Hsiao Chien Sung wrote:
> > Add device tree documentations for MT8188 VDOSYS1.
> 
> It does not look like you tested the bindings, at least after quick
> look. Please run `make dt_binding_check` (see
> Documentation/devicetree/bindings/writing-schema.rst for
> instructions).
> Maybe you need to update your dtschema and yamllint.
> 
> > diff --git
> a/Documentation/devicetree/bindings/display/mediatek/mediatek,padding
> .yaml
> b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding
> .yaml
> > new file mode 100644
> > index 000000000000..8a9e74cbf6dc
> > --- /dev/null
> > +++
> b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding
> .yaml
> > @@ -0,0 +1,80 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: 
> http://devicetree.org/schemas/display/mediatek/mediatek,padding.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: MediaTek PADDING
> > +
> > +maintainers:
> > +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > +  - Philipp Zabel <p.zabel@pengutronix.de>
> > +
> > +description:
> > +  MediaTek PADDING provides ability to VDOSYS1 to fill pixels to
> > +  width and height of a layer with a specified color.
> > +  Since MIXER in VDOSYS1 requires the width of a layer to be 2-
> pixel-align, or
> > +  4-pixel-align when ETHDR is enabled, we need PADDING to deal
> with odd width.
> > +  Please notice that even if the PADDING is in bypass mode,
> > +  settings in the registers must be cleared to 0, otherwise
> > +  undeinfed behaviors could happen.
> 
> Typo, undefined
> 
> > +
> 
> 
> 
> > +required:
> > +  - compatible
> > +  - reg
> > +  - power-domains
> > +  - clocks
> > +  - mediatek,gce-client-reg
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +    #include <dt-bindings/clock/mt8188-clk.h>
> > +    #include <dt-bindings/power/mt8188-power.h>
> > +    #include <dt-bindings/gce/mt8188-gce.h>
> > +    #include <dt-bindings/memory/mt8188-memory-port.h>
> > +
> > +    soc {
> > +        #address-cells = <2>;
> > +        #size-cells = <2>;
> > +
> > +        vdo1_padding0: vdo1_padding0@1c11d000 {
> 
> No underscores in node names.
> 
> Node names should be generic. See also explanation and list of
> examples
> in DT specification:
> 
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
> 
> > +            compatible = "mediatek,mt8188-vdo1-padding";
> > +            reg = <0 0x1c11d000 0 0x1000>;
> > +            clocks = <&vdosys1 CLK_VDO1_PADDING0>;
> > +            power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
> > +            mediatek,gce-client-reg =
> > +                <&gce0 SUBSYS_1c11XXXX 0xd000 0x1000>;
> 
> Wrong wrapping. It's one line. Properties should not be wrapped after
> '='.
> 
> 
> Best regards,
> Krzysztof
> 

Re: [PATCH v1 2/6] dt-bindings: reset: mt8188: Add reset control bits for VDOSYS1

[Shawn Sung (宋孝謙)]

Update:

It seems device tree doesn't accept enum.
I'll use #define here.

On Thu, 2023-06-08 at 11:01 +0800, shawn.sung wrote:
> Hi AngeloGioacchino,
> 
> Should I use enum instead of #define if reset ID must starts from 0?
> 
> Thanks,
> Hsiao Chien Sung
> 
> On Wed, 2023-06-07 at 09:51 +0200, AngeloGioacchino Del Regno wrote:
> >  	 
> > External email : Please do not click links or open attachments
> > until
> > you have verified the sender or the content.
> >  
> > Il 07/06/23 08:11, Hsiao Chien Sung ha scritto:
> > > Add reset control bits for  MT8188 VDOSYS1.
> > > 
> > > Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> > > ---
> > >   include/dt-bindings/reset/mt8188-resets.h | 12 ++++++++++++
> > >   1 file changed, 12 insertions(+)
> > > 
> > > diff --git a/include/dt-bindings/reset/mt8188-resets.h
> > 
> > b/include/dt-bindings/reset/mt8188-resets.h
> > > index 377cdfda82a9..439a9a25ca19 100644
> > > --- a/include/dt-bindings/reset/mt8188-resets.h
> > > +++ b/include/dt-bindings/reset/mt8188-resets.h
> > > @@ -33,4 +33,16 @@
> > > 
> > >   #define MT8188_TOPRGU_SW_RST_NUM               24
> > > 
> > > +/* VDOSYS1 */
> > > +#define MT8188_VDO1_RST_MERGE0_DL_ASYNC         9
> > 
> > Sorry, I've just noticed that there's no index 0 in previous
> > definitions: this
> > is wrong, it must start from 0 and must be sequential.
> > 
> > 

Re: [PATCH v1 2/6] dt-bindings: reset: mt8188: Add reset control bits for VDOSYS1

[Krzysztof Kozlowski]

On 08/06/2023 05:01, Shawn Sung (宋孝謙) wrote:
> Hi AngeloGioacchino,
> 
> Should I use enum instead of #define if reset ID must starts from 0?

Open existing bindings (there are many, many files) which will give you
the answer. It will be faster than asking us and you will learn something.

Best regards,
Krzysztof

Re: [PATCH v1 1/6] dt-bindings: display/mediatek: mt8188: Add documentations for VDOSYS1

[Chun-Kuang Hu]

Hi, Hsiao-chien:

Separate mmsys part to another patch because it would go through
different maintainer's tree.

Separate padding part to another patch because it's a new device.

Regards,
Chun-Kuang.

Hsiao Chien Sung <shawn.sung@mediatek.com> 於 2023年6月7日 週三 下午2:11寫道：
>
> Add device tree documentations for MT8188 VDOSYS1.
>
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
>  .../bindings/arm/mediatek/mediatek,mmsys.yaml |  1 +
>  .../display/mediatek/mediatek,ethdr.yaml      |  5 +-
>  .../display/mediatek/mediatek,mdp-rdma.yaml   |  5 +-
>  .../display/mediatek/mediatek,merge.yaml      |  1 +
>  .../display/mediatek/mediatek,padding.yaml    | 80 +++++++++++++++++++
>  5 files changed, 90 insertions(+), 2 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> index 536f5a5ebd24..642fa2e4736e 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> @@ -32,6 +32,7 @@ properties:
>                - mediatek,mt8183-mmsys
>                - mediatek,mt8186-mmsys
>                - mediatek,mt8188-vdosys0
> +              - mediatek,mt8188-vdosys1
>                - mediatek,mt8192-mmsys
>                - mediatek,mt8195-vdosys1
>                - mediatek,mt8195-vppsys0
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
> index 801fa66ae615..e3f740ab0564 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
> @@ -23,7 +23,10 @@ description:
>
>  properties:
>    compatible:
> -    const: mediatek,mt8195-disp-ethdr
> +    oneOf:
> +      - enum:
> +        - mediatek,mt8188-disp-ethdr
> +        - mediatek,mt8195-disp-ethdr
>
>    reg:
>      maxItems: 7
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
> index dd12e2ff685c..07c345fa9178 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
> @@ -21,7 +21,10 @@ description:
>
>  properties:
>    compatible:
> -    const: mediatek,mt8195-vdo1-rdma
> +    oneOf:
> +      - enum:
> +        - mediatek,mt8188-vdo1-rdma
> +        - mediatek,mt8195-vdo1-rdma
>
>    reg:
>      maxItems: 1
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> index 2f8e2f4dc3b8..600f1b4608f8 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> @@ -23,6 +23,7 @@ properties:
>      oneOf:
>        - enum:
>            - mediatek,mt8173-disp-merge
> +          - mediatek,mt8188-disp-merge
>            - mediatek,mt8195-disp-merge
>
>    reg:
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml
> new file mode 100644
> index 000000000000..8a9e74cbf6dc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml
> @@ -0,0 +1,80 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,padding.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek PADDING
> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description:
> +  MediaTek PADDING provides ability to VDOSYS1 to fill pixels to
> +  width and height of a layer with a specified color.
> +  Since MIXER in VDOSYS1 requires the width of a layer to be 2-pixel-align, or
> +  4-pixel-align when ETHDR is enabled, we need PADDING to deal with odd width.
> +  Please notice that even if the PADDING is in bypass mode,
> +  settings in the registers must be cleared to 0, otherwise
> +  undeinfed behaviors could happen.
> +
> +properties:
> +  compatible:
> +    const: mediatek,mt8188-vdo1-padding
> +
> +  reg:
> +    maxItems: 1
> +
> +  power-domains:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: RDMA Clock
> +
> +  mediatek,gce-client-reg:
> +    description:
> +      The register of display function block to be set by gce. There are 4 arguments,
> +      such as gce node, subsys id, offset and register size. The subsys id that is
> +      mapping to the register of display function blocks is defined in the gce header
> +      include/dt-bindings/gce/<chip>-gce.h of each chips.
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    items:
> +      items:
> +        - description: phandle of GCE
> +        - description: GCE subsys id
> +        - description: register offset
> +        - description: register size
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - power-domains
> +  - clocks
> +  - mediatek,gce-client-reg
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/clock/mt8188-clk.h>
> +    #include <dt-bindings/power/mt8188-power.h>
> +    #include <dt-bindings/gce/mt8188-gce.h>
> +    #include <dt-bindings/memory/mt8188-memory-port.h>
> +
> +    soc {
> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +
> +        vdo1_padding0: vdo1_padding0@1c11d000 {
> +            compatible = "mediatek,mt8188-vdo1-padding";
> +            reg = <0 0x1c11d000 0 0x1000>;
> +            clocks = <&vdosys1 CLK_VDO1_PADDING0>;
> +            power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
> +            mediatek,gce-client-reg =
> +                <&gce0 SUBSYS_1c11XXXX 0xd000 0x1000>;
> +        };
> +    };
> --
> 2.18.0
>

Re: [PATCH v1 4/6] drm/mediatek: mt8188: Modify display driver for VDOSYS1

[Chun-Kuang Hu]

Hi, Hsiao-chien:

Hsiao Chien Sung <shawn.sung@mediatek.com> 於 2023年6月7日 週三 下午2:11寫道：
>
> - Modify MUTEX and component preparation logic for better compatibility
> - Adjust display module probe sequence to avoid probe deferral
>
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_disp_merge.c     |   3 +-
>  .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c   | 100 ++++++++++--------
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c        |  28 ++++-
>  drivers/gpu/drm/mediatek/mtk_ethdr.c          |   1 +
>  drivers/gpu/drm/mediatek/mtk_mdp_rdma.c       |   1 +
>  5 files changed, 84 insertions(+), 49 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> index 6428b6203ffe..2a30e41c246f 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> @@ -104,7 +104,7 @@ void mtk_merge_stop_cmdq(struct device *dev, struct cmdq_pkt *cmdq_pkt)
>         mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
>                       DISP_REG_MERGE_CTRL);
>
> -       if (priv->async_clk)
> +       if (!cmdq_pkt && priv->async_clk)

This is related to neither preparation logic nor probe sequence,
separate this to another patch.

>                 reset_control_reset(priv->reset_ctl);
>  }
>
> @@ -303,6 +303,7 @@ static int mtk_disp_merge_remove(struct platform_device *pdev)
>  }
>
>  static const struct of_device_id mtk_disp_merge_driver_dt_match[] = {
> +       { .compatible = "mediatek,mt8188-disp-merge", },

This is related to neither preparation logic nor probe sequence,
separate this to another patch.

>         { .compatible = "mediatek,mt8195-disp-merge", },
>         {},
>  };
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> index c0a38f5217ee..e1d8d4765af8 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> @@ -51,6 +51,7 @@ enum mtk_ovl_adaptor_comp_id {
>
>  struct ovl_adaptor_comp_match {
>         enum mtk_ovl_adaptor_comp_type type;
> +       enum mtk_ddp_comp_id comp_id;
>         int alias_id;
>  };
>
> @@ -67,19 +68,19 @@ static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
>  };
>
>  static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {
> -       [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, 0 },
> -       [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, 1 },
> -       [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, 2 },
> -       [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, 3 },
> -       [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, 4 },
> -       [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, 5 },
> -       [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, 6 },
> -       [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, 7 },
> -       [OVL_ADAPTOR_MERGE0]    = { OVL_ADAPTOR_TYPE_MERGE, 1 },
> -       [OVL_ADAPTOR_MERGE1]    = { OVL_ADAPTOR_TYPE_MERGE, 2 },
> -       [OVL_ADAPTOR_MERGE2]    = { OVL_ADAPTOR_TYPE_MERGE, 3 },
> -       [OVL_ADAPTOR_MERGE3]    = { OVL_ADAPTOR_TYPE_MERGE, 4 },
> -       [OVL_ADAPTOR_ETHDR0]    = { OVL_ADAPTOR_TYPE_ETHDR, 0 },
> +       [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA0, 0 },
> +       [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA1, 1 },
> +       [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA2, 2 },
> +       [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA3, 3 },
> +       [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA4, 4 },
> +       [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA5, 5 },
> +       [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA6, 6 },
> +       [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, DDP_COMPONENT_MDP_RDMA7, 7 },
> +       [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE1, 1 },
> +       [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, 2 },
> +       [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, 3 },
> +       [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE4, 4 },
> +       [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, DDP_COMPONENT_ETHDR_MIXER, 0 },
>  };
>
>  void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
> @@ -192,6 +193,8 @@ int mtk_ovl_adaptor_clk_enable(struct device *dev)
>
>         for (i = 0; i < OVL_ADAPTOR_MERGE0; i++) {
>                 comp = ovl_adaptor->ovl_adaptor_comp[i];
> +               if (!comp)
> +                       continue;
>                 ret = pm_runtime_get_sync(comp);
>                 if (ret < 0) {
>                         dev_err(dev, "Failed to enable power domain %d, err %d\n", i, ret);
> @@ -201,7 +204,8 @@ int mtk_ovl_adaptor_clk_enable(struct device *dev)
>
>         for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
>                 comp = ovl_adaptor->ovl_adaptor_comp[i];
> -
> +               if (!comp)
> +                       continue;
>                 if (i < OVL_ADAPTOR_MERGE0)
>                         ret = mtk_mdp_rdma_clk_enable(comp);
>                 else if (i < OVL_ADAPTOR_ETHDR0)
> @@ -219,6 +223,8 @@ int mtk_ovl_adaptor_clk_enable(struct device *dev)
>  clk_err:
>         while (--i >= 0) {
>                 comp = ovl_adaptor->ovl_adaptor_comp[i];
> +               if (!comp)
> +                       continue;
>                 if (i < OVL_ADAPTOR_MERGE0)
>                         mtk_mdp_rdma_clk_disable(comp);
>                 else if (i < OVL_ADAPTOR_ETHDR0)
> @@ -229,8 +235,12 @@ int mtk_ovl_adaptor_clk_enable(struct device *dev)
>         i = OVL_ADAPTOR_MERGE0;
>
>  pwr_err:
> -       while (--i >= 0)
> -               pm_runtime_put(ovl_adaptor->ovl_adaptor_comp[i]);
> +       while (--i >= 0) {
> +               comp = ovl_adaptor->ovl_adaptor_comp[i];
> +               if (!comp)
> +                       continue;
> +               pm_runtime_put(comp);
> +       }
>
>         return ret;
>  }
> @@ -243,7 +253,8 @@ void mtk_ovl_adaptor_clk_disable(struct device *dev)
>
>         for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
>                 comp = ovl_adaptor->ovl_adaptor_comp[i];
> -
> +               if (!comp)
> +                       continue;
>                 if (i < OVL_ADAPTOR_MERGE0) {
>                         mtk_mdp_rdma_clk_disable(comp);
>                         pm_runtime_put(comp);
> @@ -313,36 +324,26 @@ size_t mtk_ovl_adaptor_get_num_formats(struct device *dev)
>
>  void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex *mutex)
>  {
> -       mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA0);
> -       mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA1);
> -       mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA2);
> -       mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA3);
> -       mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA4);
> -       mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA5);
> -       mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA6);
> -       mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA7);
> -       mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE1);
> -       mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE2);
> -       mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE3);
> -       mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE4);
> -       mtk_mutex_add_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
> +       struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> +       int i;
> +
> +       for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
> +               if (!ovl_adaptor->ovl_adaptor_comp[i])
> +                       continue;
> +               mtk_mutex_add_comp(mutex, comp_matches[i].comp_id);
> +       }
>  }
>
>  void mtk_ovl_adaptor_remove_comp(struct device *dev, struct mtk_mutex *mutex)
>  {
> -       mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA0);
> -       mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA1);
> -       mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA2);
> -       mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA3);
> -       mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA4);
> -       mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA5);
> -       mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA6);
> -       mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA7);
> -       mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE1);
> -       mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE2);
> -       mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE3);
> -       mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE4);
> -       mtk_mutex_remove_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
> +       struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> +       int i;
> +
> +       for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
> +               if (!ovl_adaptor->ovl_adaptor_comp[i])
> +                       continue;
> +               mtk_mutex_remove_comp(mutex, comp_matches[i].comp_id);
> +       }
>  }
>
>  void mtk_ovl_adaptor_connect(struct device *dev, struct device *mmsys_dev, unsigned int next)
> @@ -386,6 +387,15 @@ static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node *node,
>
>  static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
>         {
> +               .compatible = "mediatek,mt8188-vdo1-rdma",
> +               .data = (void *)OVL_ADAPTOR_TYPE_RDMA,
> +       }, {
> +               .compatible = "mediatek,mt8188-disp-merge",
> +               .data = (void *)OVL_ADAPTOR_TYPE_MERGE,
> +       }, {
> +               .compatible = "mediatek,mt8188-disp-ethdr",
> +               .data = (void *)OVL_ADAPTOR_TYPE_ETHDR,
> +       }, {

This is related to neither preparation logic nor probe sequence,
separate this to another patch.

>                 .compatible = "mediatek,mt8195-vdo1-rdma",
>                 .data = (void *)OVL_ADAPTOR_TYPE_RDMA,
>         }, {
> @@ -466,6 +476,9 @@ static int mtk_disp_ovl_adaptor_comp_bind(struct device *dev, struct device *mas
>  static void mtk_disp_ovl_adaptor_comp_unbind(struct device *dev, struct device *master,
>                                              void *data)
>  {
> +       struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
> +
> +       priv->children_bound = false;
>  }
>
>  static const struct component_ops mtk_disp_ovl_adaptor_comp_ops = {
> @@ -483,6 +496,7 @@ static int mtk_disp_ovl_adaptor_master_bind(struct device *dev)
>                 return dev_err_probe(dev, ret, "component_bind_all failed!\n");
>
>         priv->children_bound = true;
> +

This is related to neither preparation logic nor probe sequence,
separate this to another patch.

>         return 0;
>  }
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 6dcb4ba2466c..87dadd129c22 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -188,6 +188,12 @@ static const unsigned int mt8188_mtk_ddp_main[] = {
>         DDP_COMPONENT_DP_INTF0,
>  };
>
> +static const unsigned int mt8188_mtk_ddp_ext[] = {
> +       DDP_COMPONENT_DRM_OVL_ADAPTOR,
> +       DDP_COMPONENT_MERGE5,
> +       DDP_COMPONENT_DP_INTF1,
> +};
> +
>  static const unsigned int mt8192_mtk_ddp_main[] = {
>         DDP_COMPONENT_OVL0,
>         DDP_COMPONENT_OVL_2L0,
> @@ -287,6 +293,14 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
>  static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
>         .main_path = mt8188_mtk_ddp_main,
>         .main_len = ARRAY_SIZE(mt8188_mtk_ddp_main),
> +       .mmsys_dev_num = 2,
> +};
> +
> +static const struct mtk_mmsys_driver_data mt8188_vdosys1_driver_data = {
> +       .ext_path = mt8188_mtk_ddp_ext,
> +       .ext_len = ARRAY_SIZE(mt8188_mtk_ddp_ext),
> +       .mmsys_id = 1,
> +       .mmsys_dev_num = 2,

This is related to neither preparation logic nor probe sequence,
separate this to another patch.

>  };
>
>  static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
> @@ -327,6 +341,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
>           .data = &mt8186_mmsys_driver_data},
>         { .compatible = "mediatek,mt8188-vdosys0",
>           .data = &mt8188_vdosys0_driver_data},
> +       { .compatible = "mediatek,mt8188-vdosys1",
> +         .data = &mt8188_vdosys1_driver_data},

This is related to neither preparation logic nor probe sequence,
separate this to another patch.

>         { .compatible = "mediatek,mt8192-mmsys",
>           .data = &mt8192_mmsys_driver_data},
>         { .compatible = "mediatek,mt8195-mmsys",
> @@ -682,6 +698,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>           .data = (void *)MTK_DISP_GAMMA, },
>         { .compatible = "mediatek,mt8183-disp-gamma",
>           .data = (void *)MTK_DISP_GAMMA, },
> +       { .compatible = "mediatek,mt8188-disp-merge",
> +         .data = (void *)MTK_DISP_MERGE },

This is related to neither preparation logic nor probe sequence,
separate this to another patch.

>         { .compatible = "mediatek,mt8195-disp-merge",
>           .data = (void *)MTK_DISP_MERGE },
>         { .compatible = "mediatek,mt2701-disp-mutex",
> @@ -965,15 +983,15 @@ static struct platform_driver * const mtk_drm_drivers[] = {
>         &mtk_disp_ccorr_driver,
>         &mtk_disp_color_driver,
>         &mtk_disp_gamma_driver,
> +       &mtk_disp_rdma_driver,
> +       &mtk_mdp_rdma_driver,
>         &mtk_disp_merge_driver,
> -       &mtk_disp_ovl_adaptor_driver,
> +       &mtk_ethdr_driver,
>         &mtk_disp_ovl_driver,
> -       &mtk_disp_rdma_driver,
> +       &mtk_disp_ovl_adaptor_driver,
> +       &mtk_dsi_driver,
>         &mtk_dpi_driver,
>         &mtk_drm_platform_driver,
> -       &mtk_dsi_driver,
> -       &mtk_ethdr_driver,
> -       &mtk_mdp_rdma_driver,

Why change the order?

>  };
>
>  static int __init mtk_drm_init(void)
> diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> index 73dc4da3ba3b..b5a6b67f2db9 100644
> --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c
> +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> @@ -353,6 +353,7 @@ static int mtk_ethdr_remove(struct platform_device *pdev)
>  }
>
>  static const struct of_device_id mtk_ethdr_driver_dt_match[] = {
> +       { .compatible = "mediatek,mt8188-disp-ethdr"},

This is related to neither preparation logic nor probe sequence,
separate this to another patch.

>         { .compatible = "mediatek,mt8195-disp-ethdr"},
>         {},
>  };
> diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> index e06db6e56b5f..06d5c9abb515 100644
> --- a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> @@ -323,6 +323,7 @@ static int mtk_mdp_rdma_remove(struct platform_device *pdev)
>  }
>
>  static const struct of_device_id mtk_mdp_rdma_driver_dt_match[] = {
> +       { .compatible = "mediatek,mt8188-vdo1-rdma", },

This is related to neither preparation logic nor probe sequence,
separate this to another patch.

Regards,
Chun-Kuang.

>         { .compatible = "mediatek,mt8195-vdo1-rdma", },
>         {},
>  };
> --
> 2.18.0
>

Re: [PATCH v1 4/6] drm/mediatek: mt8188: Modify display driver for VDOSYS1

[CK Hu (胡俊光)]

Hi, Hsiao chien:

On Wed, 2023-06-07 at 14:11 +0800, Hsiao Chien Sung wrote:
> - Modify MUTEX and component preparation logic for better
> compatibility
> - Adjust display module probe sequence to avoid probe deferral

Probe deferral is normal in Linux driver, why to avoid it?
Is new sequence only optimized for mt8188? If so, I think it's not
necessary to do this only for one SoC.

Regards,
CK

> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_disp_merge.c     |   3 +-
>  .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c   | 100 ++++++++++----
> ----
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c        |  28 ++++-
>  drivers/gpu/drm/mediatek/mtk_ethdr.c          |   1 +
>  drivers/gpu/drm/mediatek/mtk_mdp_rdma.c       |   1 +
>  5 files changed, 84 insertions(+), 49 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> index 6428b6203ffe..2a30e41c246f 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> @@ -104,7 +104,7 @@ void mtk_merge_stop_cmdq(struct device *dev,
> struct cmdq_pkt *cmdq_pkt)
>  	mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
>  		      DISP_REG_MERGE_CTRL);
> 
> -	if (priv->async_clk)
> +	if (!cmdq_pkt && priv->async_clk)
>  		reset_control_reset(priv->reset_ctl);
>  }
> 
> @@ -303,6 +303,7 @@ static int mtk_disp_merge_remove(struct
> platform_device *pdev)
>  }
> 
>  static const struct of_device_id mtk_disp_merge_driver_dt_match[] =
> {
> +	{ .compatible = "mediatek,mt8188-disp-merge", },
>  	{ .compatible = "mediatek,mt8195-disp-merge", },
>  	{},
>  };
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> index c0a38f5217ee..e1d8d4765af8 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> @@ -51,6 +51,7 @@ enum mtk_ovl_adaptor_comp_id {
> 
>  struct ovl_adaptor_comp_match {
>  	enum mtk_ovl_adaptor_comp_type type;
> +	enum mtk_ddp_comp_id comp_id;
>  	int alias_id;
>  };
> 
> @@ -67,19 +68,19 @@ static const char * const
> private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
>  };
> 
>  static const struct ovl_adaptor_comp_match
> comp_matches[OVL_ADAPTOR_ID_MAX] = {
> -	[OVL_ADAPTOR_MDP_RDMA0]	= { OVL_ADAPTOR_TYPE_RDMA, 0 },
> -	[OVL_ADAPTOR_MDP_RDMA1]	= { OVL_ADAPTOR_TYPE_RDMA, 1 },
> -	[OVL_ADAPTOR_MDP_RDMA2]	= { OVL_ADAPTOR_TYPE_RDMA, 2 },
> -	[OVL_ADAPTOR_MDP_RDMA3]	= { OVL_ADAPTOR_TYPE_RDMA, 3 },
> -	[OVL_ADAPTOR_MDP_RDMA4]	= { OVL_ADAPTOR_TYPE_RDMA, 4 },
> -	[OVL_ADAPTOR_MDP_RDMA5]	= { OVL_ADAPTOR_TYPE_RDMA, 5 },
> -	[OVL_ADAPTOR_MDP_RDMA6]	= { OVL_ADAPTOR_TYPE_RDMA, 6 },
> -	[OVL_ADAPTOR_MDP_RDMA7]	= { OVL_ADAPTOR_TYPE_RDMA, 7 },
> -	[OVL_ADAPTOR_MERGE0]	= { OVL_ADAPTOR_TYPE_MERGE, 1 },
> -	[OVL_ADAPTOR_MERGE1]	= { OVL_ADAPTOR_TYPE_MERGE, 2 },
> -	[OVL_ADAPTOR_MERGE2]	= { OVL_ADAPTOR_TYPE_MERGE, 3 },
> -	[OVL_ADAPTOR_MERGE3]	= { OVL_ADAPTOR_TYPE_MERGE, 4 },
> -	[OVL_ADAPTOR_ETHDR0]	= { OVL_ADAPTOR_TYPE_ETHDR, 0 },
> +	[OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA,
> DDP_COMPONENT_MDP_RDMA0, 0 },
> +	[OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA,
> DDP_COMPONENT_MDP_RDMA1, 1 },
> +	[OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA,
> DDP_COMPONENT_MDP_RDMA2, 2 },
> +	[OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA,
> DDP_COMPONENT_MDP_RDMA3, 3 },
> +	[OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA,
> DDP_COMPONENT_MDP_RDMA4, 4 },
> +	[OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA,
> DDP_COMPONENT_MDP_RDMA5, 5 },
> +	[OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA,
> DDP_COMPONENT_MDP_RDMA6, 6 },
> +	[OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA,
> DDP_COMPONENT_MDP_RDMA7, 7 },
> +	[OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE,
> DDP_COMPONENT_MERGE1, 1 },
> +	[OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE,
> DDP_COMPONENT_MERGE2, 2 },
> +	[OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE,
> DDP_COMPONENT_MERGE3, 3 },
> +	[OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE,
> DDP_COMPONENT_MERGE4, 4 },
> +	[OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR,
> DDP_COMPONENT_ETHDR_MIXER, 0 },
>  };
> 
>  void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int
> idx,
> @@ -192,6 +193,8 @@ int mtk_ovl_adaptor_clk_enable(struct device
> *dev)
> 
>  	for (i = 0; i < OVL_ADAPTOR_MERGE0; i++) {
>  		comp = ovl_adaptor->ovl_adaptor_comp[i];
> +		if (!comp)
> +			continue;
>  		ret = pm_runtime_get_sync(comp);
>  		if (ret < 0) {
>  			dev_err(dev, "Failed to enable power domain %d,
> err %d\n", i, ret);
> @@ -201,7 +204,8 @@ int mtk_ovl_adaptor_clk_enable(struct device
> *dev)
> 
>  	for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
>  		comp = ovl_adaptor->ovl_adaptor_comp[i];
> -
> +		if (!comp)
> +			continue;
>  		if (i < OVL_ADAPTOR_MERGE0)
>  			ret = mtk_mdp_rdma_clk_enable(comp);
>  		else if (i < OVL_ADAPTOR_ETHDR0)
> @@ -219,6 +223,8 @@ int mtk_ovl_adaptor_clk_enable(struct device
> *dev)
>  clk_err:
>  	while (--i >= 0) {
>  		comp = ovl_adaptor->ovl_adaptor_comp[i];
> +		if (!comp)
> +			continue;
>  		if (i < OVL_ADAPTOR_MERGE0)
>  			mtk_mdp_rdma_clk_disable(comp);
>  		else if (i < OVL_ADAPTOR_ETHDR0)
> @@ -229,8 +235,12 @@ int mtk_ovl_adaptor_clk_enable(struct device
> *dev)
>  	i = OVL_ADAPTOR_MERGE0;
> 
>  pwr_err:
> -	while (--i >= 0)
> -		pm_runtime_put(ovl_adaptor->ovl_adaptor_comp[i]);
> +	while (--i >= 0) {
> +		comp = ovl_adaptor->ovl_adaptor_comp[i];
> +		if (!comp)
> +			continue;
> +		pm_runtime_put(comp);
> +	}
> 
>  	return ret;
>  }
> @@ -243,7 +253,8 @@ void mtk_ovl_adaptor_clk_disable(struct device
> *dev)
> 
>  	for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
>  		comp = ovl_adaptor->ovl_adaptor_comp[i];
> -
> +		if (!comp)
> +			continue;
>  		if (i < OVL_ADAPTOR_MERGE0) {
>  			mtk_mdp_rdma_clk_disable(comp);
>  			pm_runtime_put(comp);
> @@ -313,36 +324,26 @@ size_t mtk_ovl_adaptor_get_num_formats(struct
> device *dev)
> 
>  void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex
> *mutex)
>  {
> -	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA0);
> -	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA1);
> -	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA2);
> -	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA3);
> -	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA4);
> -	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA5);
> -	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA6);
> -	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA7);
> -	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE1);
> -	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE2);
> -	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE3);
> -	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE4);
> -	mtk_mutex_add_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
> +	struct mtk_disp_ovl_adaptor *ovl_adaptor =
> dev_get_drvdata(dev);
> +	int i;
> +
> +	for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
> +		if (!ovl_adaptor->ovl_adaptor_comp[i])
> +			continue;
> +		mtk_mutex_add_comp(mutex, comp_matches[i].comp_id);
> +	}
>  }
> 
>  void mtk_ovl_adaptor_remove_comp(struct device *dev, struct
> mtk_mutex *mutex)
>  {
> -	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA0);
> -	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA1);
> -	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA2);
> -	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA3);
> -	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA4);
> -	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA5);
> -	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA6);
> -	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA7);
> -	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE1);
> -	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE2);
> -	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE3);
> -	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE4);
> -	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
> +	struct mtk_disp_ovl_adaptor *ovl_adaptor =
> dev_get_drvdata(dev);
> +	int i;
> +
> +	for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
> +		if (!ovl_adaptor->ovl_adaptor_comp[i])
> +			continue;
> +		mtk_mutex_remove_comp(mutex, comp_matches[i].comp_id);
> +	}
>  }
> 
>  void mtk_ovl_adaptor_connect(struct device *dev, struct device
> *mmsys_dev, unsigned int next)
> @@ -386,6 +387,15 @@ static int ovl_adaptor_comp_get_id(struct device
> *dev, struct device_node *node,
> 
>  static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
>  	{
> +		.compatible = "mediatek,mt8188-vdo1-rdma",
> +		.data = (void *)OVL_ADAPTOR_TYPE_RDMA,
> +	}, {
> +		.compatible = "mediatek,mt8188-disp-merge",
> +		.data = (void *)OVL_ADAPTOR_TYPE_MERGE,
> +	}, {
> +		.compatible = "mediatek,mt8188-disp-ethdr",
> +		.data = (void *)OVL_ADAPTOR_TYPE_ETHDR,
> +	}, {
>  		.compatible = "mediatek,mt8195-vdo1-rdma",
>  		.data = (void *)OVL_ADAPTOR_TYPE_RDMA,
>  	}, {
> @@ -466,6 +476,9 @@ static int mtk_disp_ovl_adaptor_comp_bind(struct
> device *dev, struct device *mas
>  static void mtk_disp_ovl_adaptor_comp_unbind(struct device *dev,
> struct device *master,
>  					     void *data)
>  {
> +	struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
> +
> +	priv->children_bound = false;
>  }
> 
>  static const struct component_ops mtk_disp_ovl_adaptor_comp_ops = {
> @@ -483,6 +496,7 @@ static int
> mtk_disp_ovl_adaptor_master_bind(struct device *dev)
>  		return dev_err_probe(dev, ret, "component_bind_all
> failed!\n");
> 
>  	priv->children_bound = true;
> +
>  	return 0;
>  }
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 6dcb4ba2466c..87dadd129c22 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -188,6 +188,12 @@ static const unsigned int mt8188_mtk_ddp_main[]
> = {
>  	DDP_COMPONENT_DP_INTF0,
>  };
> 
> +static const unsigned int mt8188_mtk_ddp_ext[] = {
> +	DDP_COMPONENT_DRM_OVL_ADAPTOR,
> +	DDP_COMPONENT_MERGE5,
> +	DDP_COMPONENT_DP_INTF1,
> +};
> +
>  static const unsigned int mt8192_mtk_ddp_main[] = {
>  	DDP_COMPONENT_OVL0,
>  	DDP_COMPONENT_OVL_2L0,
> @@ -287,6 +293,14 @@ static const struct mtk_mmsys_driver_data
> mt8186_mmsys_driver_data = {
>  static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data
> = {
>  	.main_path = mt8188_mtk_ddp_main,
>  	.main_len = ARRAY_SIZE(mt8188_mtk_ddp_main),
> +	.mmsys_dev_num = 2,
> +};
> +
> +static const struct mtk_mmsys_driver_data mt8188_vdosys1_driver_data
> = {
> +	.ext_path = mt8188_mtk_ddp_ext,
> +	.ext_len = ARRAY_SIZE(mt8188_mtk_ddp_ext),
> +	.mmsys_id = 1,
> +	.mmsys_dev_num = 2,
>  };
> 
>  static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data =
> {
> @@ -327,6 +341,8 @@ static const struct of_device_id mtk_drm_of_ids[]
> = {
>  	  .data = &mt8186_mmsys_driver_data},
>  	{ .compatible = "mediatek,mt8188-vdosys0",
>  	  .data = &mt8188_vdosys0_driver_data},
> +	{ .compatible = "mediatek,mt8188-vdosys1",
> +	  .data = &mt8188_vdosys1_driver_data},
>  	{ .compatible = "mediatek,mt8192-mmsys",
>  	  .data = &mt8192_mmsys_driver_data},
>  	{ .compatible = "mediatek,mt8195-mmsys",
> @@ -682,6 +698,8 @@ static const struct of_device_id
> mtk_ddp_comp_dt_ids[] = {
>  	  .data = (void *)MTK_DISP_GAMMA, },
>  	{ .compatible = "mediatek,mt8183-disp-gamma",
>  	  .data = (void *)MTK_DISP_GAMMA, },
> +	{ .compatible = "mediatek,mt8188-disp-merge",
> +	  .data = (void *)MTK_DISP_MERGE },
>  	{ .compatible = "mediatek,mt8195-disp-merge",
>  	  .data = (void *)MTK_DISP_MERGE },
>  	{ .compatible = "mediatek,mt2701-disp-mutex",
> @@ -965,15 +983,15 @@ static struct platform_driver * const
> mtk_drm_drivers[] = {
>  	&mtk_disp_ccorr_driver,
>  	&mtk_disp_color_driver,
>  	&mtk_disp_gamma_driver,
> +	&mtk_disp_rdma_driver,
> +	&mtk_mdp_rdma_driver,
>  	&mtk_disp_merge_driver,
> -	&mtk_disp_ovl_adaptor_driver,
> +	&mtk_ethdr_driver,
>  	&mtk_disp_ovl_driver,
> -	&mtk_disp_rdma_driver,
> +	&mtk_disp_ovl_adaptor_driver,
> +	&mtk_dsi_driver,
>  	&mtk_dpi_driver,
>  	&mtk_drm_platform_driver,
> -	&mtk_dsi_driver,
> -	&mtk_ethdr_driver,
> -	&mtk_mdp_rdma_driver,
>  };
> 
>  static int __init mtk_drm_init(void)
> diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c
> b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> index 73dc4da3ba3b..b5a6b67f2db9 100644
> --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c
> +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> @@ -353,6 +353,7 @@ static int mtk_ethdr_remove(struct
> platform_device *pdev)
>  }
> 
>  static const struct of_device_id mtk_ethdr_driver_dt_match[] = {
> +	{ .compatible = "mediatek,mt8188-disp-ethdr"},
>  	{ .compatible = "mediatek,mt8195-disp-ethdr"},
>  	{},
>  };
> diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> index e06db6e56b5f..06d5c9abb515 100644
> --- a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> @@ -323,6 +323,7 @@ static int mtk_mdp_rdma_remove(struct
> platform_device *pdev)
>  }
> 
>  static const struct of_device_id mtk_mdp_rdma_driver_dt_match[] = {
> +	{ .compatible = "mediatek,mt8188-vdo1-rdma", },
>  	{ .compatible = "mediatek,mt8195-vdo1-rdma", },
>  	{},
>  };
> --
> 2.18.0
> 
>