[PATCH v2 0/7] MSM8976 PLL,RPMPD and DTS changes

[PATCH v2 0/7] MSM8976 PLL,RPMPD and DTS changes

[Adam Skladowski]

This patch series fixes introduce support for msm8976 pll,
also brings some adjustments and fixes domains setup and few dts nitpicks.

Changes since v1
================
1. Fixed few styling issues
2. Changed compatibles for plls
3. Added fixes: tag to first patch

Adam Skladowski (7):
  drivers: soc: qcom: rpmpd: Fix MSM8976 power domains setup
  clk: qcom: clk-hfpll: Configure l_val in init when required
  clk: qcom: hfpll: Allow matching pdata
  dt-bindings: clock: qcom,hfpll: Document MSM8976 compatibles
  clk: qcom: hfpll: Add MSM8976 PLL data
  arm64: dts: qcom: msm8976: Split lpass region
  arm64: dts: qcom: msm8976: Fix smsm ipc bit shifts

 .../devicetree/bindings/clock/qcom,hfpll.txt  |  3 +
 arch/arm64/boot/dts/qcom/msm8976.dtsi         | 11 +++-
 drivers/clk/qcom/clk-hfpll.c                  |  4 ++
 drivers/clk/qcom/clk-hfpll.h                  |  1 +
 drivers/clk/qcom/hfpll.c                      | 59 ++++++++++++++++++-
 drivers/soc/qcom/rpmpd.c                      | 27 ++++-----
 6 files changed, 83 insertions(+), 22 deletions(-)

-- 
2.25.1

[PATCH v2 1/7] drivers: soc: qcom: rpmpd: Fix MSM8976 power domains setup

[Adam Skladowski]

Downstream kernel parses resource names based on pm8950-rpm-regulator.dtsi
in such file qcom,resource-name takes three values: smpa,ldoa and clk0.
First appearance of RWSC/RWSM point to msm-4.4 kernel
which is way newer than what this platform was shipped with (msm-3.10).
For the max_state downstream code limit value to TURBO inside dts
with only one turbo_high being placed in msm-thermal bindings.
One of effects of requesting TURBO_HIGH vote is rebooting of device
which happens during voting inside WCNSS/IRIS,
this behavior was observed on LeEco S2 smartphone.
Fix regulator setup and drop unused resources.

Fixes: b1d522443b4b ("soc: qcom: rpmpd: Add rpm power domains for msm8976")
Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
---
 drivers/soc/qcom/rpmpd.c | 27 ++++++++++-----------------
 1 file changed, 10 insertions(+), 17 deletions(-)

diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c
index 3135dd1dafe0..59caa4e7b99a 100644
--- a/drivers/soc/qcom/rpmpd.c
+++ b/drivers/soc/qcom/rpmpd.c
@@ -166,13 +166,6 @@ static struct rpmpd cx_rwcx0_vfl = {
 	.key = KEY_FLOOR_LEVEL,
 };
 
-static struct rpmpd cx_rwsc2_vfl = {
-	.pd = { .name = "cx_vfl", },
-	.res_type = RPMPD_RWSC,
-	.res_id = 2,
-	.key = KEY_FLOOR_LEVEL,
-};
-
 static struct rpmpd cx_s1a_vfc = {
 	.pd = { .name = "cx_vfc", },
 	.res_type = RPMPD_SMPA,
@@ -329,6 +322,13 @@ static struct rpmpd mx_s6a_lvl_ao = {
 	.key = KEY_LEVEL,
 };
 
+static struct rpmpd mx_s6a_vfl = {
+	.pd = { .name = "mx_vfl", },
+	.res_type = RPMPD_SMPA,
+	.res_id = 6,
+	.key = KEY_FLOOR_LEVEL,
+};
+
 static struct rpmpd mx_s7a_lvl_ao;
 static struct rpmpd mx_s7a_lvl = {
 	.pd = { .name = "mx", },
@@ -361,13 +361,6 @@ static struct rpmpd mx_rwmx0_vfl = {
 	.key = KEY_FLOOR_LEVEL,
 };
 
-static struct rpmpd mx_rwsm6_vfl = {
-	.pd = { .name = "mx_vfl", },
-	.res_type = RPMPD_RWSM,
-	.res_id = 6,
-	.key = KEY_FLOOR_LEVEL,
-};
-
 /* MD */
 static struct rpmpd md_s1a_corner_ao;
 static struct rpmpd md_s1a_corner = {
@@ -591,16 +584,16 @@ static const struct rpmpd_desc msm8953_desc = {
 static struct rpmpd *msm8976_rpmpds[] = {
 	[MSM8976_VDDCX] =	&cx_s2a_lvl,
 	[MSM8976_VDDCX_AO] =	&cx_s2a_lvl_ao,
-	[MSM8976_VDDCX_VFL] =	&cx_rwsc2_vfl,
+	[MSM8976_VDDCX_VFL] =	&cx_s2a_vfl,
 	[MSM8976_VDDMX] =	&mx_s6a_lvl,
 	[MSM8976_VDDMX_AO] =	&mx_s6a_lvl_ao,
-	[MSM8976_VDDMX_VFL] =	&mx_rwsm6_vfl,
+	[MSM8976_VDDMX_VFL] =	&mx_s6a_vfl,
 };
 
 static const struct rpmpd_desc msm8976_desc = {
 	.rpmpds = msm8976_rpmpds,
 	.num_pds = ARRAY_SIZE(msm8976_rpmpds),
-	.max_state = RPM_SMD_LEVEL_TURBO_HIGH,
+	.max_state = RPM_SMD_LEVEL_TURBO,
 };
 
 static struct rpmpd *msm8994_rpmpds[] = {
-- 
2.25.1

[PATCH v2 2/7] clk: qcom: clk-hfpll: Configure l_val in init when required

[Adam Skladowski]

Add support for pre-configuring default frequency multiplier,
this appears to be required on some platforms like MSM8976.
Without configuring L_VAL device reboots when trying to bring PLL up.

Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
---
 drivers/clk/qcom/clk-hfpll.c | 4 ++++
 drivers/clk/qcom/clk-hfpll.h | 1 +
 2 files changed, 5 insertions(+)

diff --git a/drivers/clk/qcom/clk-hfpll.c b/drivers/clk/qcom/clk-hfpll.c
index 86f728dc69e5..705352aff067 100644
--- a/drivers/clk/qcom/clk-hfpll.c
+++ b/drivers/clk/qcom/clk-hfpll.c
@@ -44,6 +44,10 @@ static void __clk_hfpll_init_once(struct clk_hw *hw)
 		regmap_write(regmap, hd->user_reg, regval);
 	}
 
+	/* Write L_VAL from conf if it exist */
+	if (hd->l_val)
+		regmap_write(regmap, hd->l_reg, hd->l_val);
+
 	if (hd->droop_reg)
 		regmap_write(regmap, hd->droop_reg, hd->droop_val);
 
diff --git a/drivers/clk/qcom/clk-hfpll.h b/drivers/clk/qcom/clk-hfpll.h
index 2a57b2fb2f2f..27b9effcb3fd 100644
--- a/drivers/clk/qcom/clk-hfpll.h
+++ b/drivers/clk/qcom/clk-hfpll.h
@@ -18,6 +18,7 @@ struct hfpll_data {
 	u32 status_reg;
 	u8  lock_bit;
 
+	u32 l_val;
 	u32 droop_val;
 	u32 config_val;
 	u32 user_val;
-- 
2.25.1

[PATCH v2 3/7] clk: qcom: hfpll: Allow matching pdata

[Adam Skladowski]

HFPLL driver can be used to drive PLLs also on different SoCs like MSM8976
On MSM8976 each PLL gets it own different configuration,
add matching pdata to driver to support multiple configurations.

Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
---
 drivers/clk/qcom/hfpll.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/qcom/hfpll.c b/drivers/clk/qcom/hfpll.c
index f4d78003d189..ec18bc8f0089 100644
--- a/drivers/clk/qcom/hfpll.c
+++ b/drivers/clk/qcom/hfpll.c
@@ -6,6 +6,7 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/of.h>
+#include <linux/of_device.h>
 #include <linux/clk.h>
 #include <linux/clk-provider.h>
 #include <linux/regmap.h>
@@ -32,7 +33,7 @@ static const struct hfpll_data hdata = {
 };
 
 static const struct of_device_id qcom_hfpll_match_table[] = {
-	{ .compatible = "qcom,hfpll" },
+	{ .compatible = "qcom,hfpll", &hdata },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, qcom_hfpll_match_table);
@@ -83,7 +84,7 @@ static int qcom_hfpll_probe(struct platform_device *pdev)
 
 	init.parent_data = &pdata;
 
-	h->d = &hdata;
+	h->d = of_device_get_match_data(&pdev->dev);
 	h->clkr.hw.init = &init;
 	spin_lock_init(&h->lock);
 
-- 
2.25.1

[PATCH v2 4/7] dt-bindings: clock: qcom,hfpll: Document MSM8976 compatibles

[Adam Skladowski]

Document MSM8976 HFPLL compatibles.

Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
---
 Documentation/devicetree/bindings/clock/qcom,hfpll.txt | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,hfpll.txt b/Documentation/devicetree/bindings/clock/qcom,hfpll.txt
index ec02a024424c..5769cbbe76be 100644
--- a/Documentation/devicetree/bindings/clock/qcom,hfpll.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,hfpll.txt
@@ -12,6 +12,9 @@ PROPERTIES
                         "qcom,hfpll-apq8064", "qcom,hfpll"
                         "qcom,hfpll-msm8974", "qcom,hfpll"
                         "qcom,hfpll-msm8960", "qcom,hfpll"
+                        "qcom,msm8976-hfpll-a53", "qcom,hfpll"
+                        "qcom,msm8976-hfpll-a72", "qcom,hfpll"
+                        "qcom,msm8976-hfpll-cci", "qcom,hfpll"
 
 - reg:
 	Usage: required
-- 
2.25.1

[PATCH v2 5/7] clk: qcom: hfpll: Add MSM8976 PLL data

[Adam Skladowski]

Add PLL configuration for MSM8976 SoC, this SoC offers 3 HFPLL.
Small cluster offers two presets for 652-902Mhz range and 902Mhz-1.47Ghz.
For simplicity only add second range as smaller frequencies can be obtained
via apcs divider or safe parent this also saves us
a hassle of reconfiguring VCO bit and config_val.
A72 and CCI cluster only use single frequency range with their
outputs/post_dividers/vco_bits being static.

Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
---
 drivers/clk/qcom/hfpll.c | 54 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 54 insertions(+)

diff --git a/drivers/clk/qcom/hfpll.c b/drivers/clk/qcom/hfpll.c
index ec18bc8f0089..7a67b1457605 100644
--- a/drivers/clk/qcom/hfpll.c
+++ b/drivers/clk/qcom/hfpll.c
@@ -32,8 +32,62 @@ static const struct hfpll_data hdata = {
 	.max_rate = 2900000000UL,
 };
 
+static const struct hfpll_data msm8976_a53 = {
+	.mode_reg = 0x00,
+	.l_reg = 0x04,
+	.m_reg = 0x08,
+	.n_reg = 0x0c,
+	.user_reg = 0x10,
+	.config_reg = 0x14,
+	.config_val = 0x341600,
+	.status_reg = 0x1c,
+	.lock_bit = 16,
+
+	.l_val = 0x35,
+	.user_val = 0x109,
+	.min_rate = 902400000UL,
+	.max_rate = 1478400000UL,
+};
+
+static const struct hfpll_data msm8976_a72 = {
+	.mode_reg = 0x00,
+	.l_reg = 0x04,
+	.m_reg = 0x08,
+	.n_reg = 0x0c,
+	.user_reg = 0x10,
+	.config_reg = 0x14,
+	.config_val = 0x4e0405d,
+	.status_reg = 0x1c,
+	.lock_bit = 16,
+
+	.l_val = 0x3e,
+	.user_val = 0x100109,
+	.min_rate = 940800000UL,
+	.max_rate = 1843200000UL,
+};
+
+static const struct hfpll_data msm8976_cci = {
+	.mode_reg = 0x00,
+	.l_reg = 0x04,
+	.m_reg = 0x08,
+	.n_reg = 0x0c,
+	.user_reg = 0x10,
+	.config_reg = 0x14,
+	.config_val = 0x141400,
+	.status_reg = 0x1c,
+	.lock_bit = 16,
+
+	.l_val = 0x20,
+	.user_val = 0x100109,
+	.min_rate = 556800000UL,
+	.max_rate = 902400000UL,
+};
+
 static const struct of_device_id qcom_hfpll_match_table[] = {
 	{ .compatible = "qcom,hfpll", &hdata },
+	{ .compatible = "qcom,msm8976-hfpll-a53", &msm8976_a53 },
+	{ .compatible = "qcom,msm8976-hfpll-a72", &msm8976_a72 },
+	{ .compatible = "qcom,msm8976-hfpll-cci", &msm8976_cci },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, qcom_hfpll_match_table);
-- 
2.25.1

[PATCH v2 6/7] arm64: dts: qcom: msm8976: Split lpass region

[Adam Skladowski]

Some devices like Sony Loire uses Broadcom module over sdc3 however others
utilize qcom WCNSS, split shared region based on downstream pil-tz loader.

Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
---
 arch/arm64/boot/dts/qcom/msm8976.dtsi | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi
index ab76806317a7..7385d5edec04 100644
--- a/arch/arm64/boot/dts/qcom/msm8976.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi
@@ -338,7 +338,12 @@ mpss_mem: mpss@86c00000 {
 		};
 
 		lpass_mem: lpass@8c200000 {
-			reg = <0x0 0x8c200000 0x0 0x1800000>;
+			reg = <0x0 0x8c200000 0x0 0x1000000>;
+			no-map;
+		};
+
+		wcnss_fw_mem: wcnss@8d200000 {
+			reg = <0x0 0x8d200000 0x0 0x800000>;
 			no-map;
 		};
 
-- 
2.25.1

[PATCH v2 7/7] arm64: dts: qcom: msm8976: Fix smsm ipc bit shifts

[Adam Skladowski]

Update bits to match downstream irq-bitmask values.

Fixes: 0484d3ce0902 ("arm64: dts: qcom: Add DTS for MSM8976 and MSM8956 SoCs")
Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
---
 arch/arm64/boot/dts/qcom/msm8976.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi
index 7385d5edec04..5537ec049451 100644
--- a/arch/arm64/boot/dts/qcom/msm8976.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi
@@ -433,9 +433,9 @@ smsm {
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		qcom,ipc-1 = <&apcs 8 12>;
+		qcom,ipc-1 = <&apcs 8 13>;
 		qcom,ipc-2 = <&apcs 8 9>;
-		qcom,ipc-3 = <&apcs 8 18>;
+		qcom,ipc-3 = <&apcs 8 19>;
 
 		apps_smsm: apps@0 {
 			reg = <0>;
-- 
2.25.1

Re: [PATCH v2 4/7] dt-bindings: clock: qcom,hfpll: Document MSM8976 compatibles

[Krzysztof Kozlowski]

On 23/07/2023 18:08, Adam Skladowski wrote:
> Document MSM8976 HFPLL compatibles.
> 
> Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
> ---
>  Documentation/devicetree/bindings/clock/qcom,hfpll.txt | 3 +++
>  1 file changed, 3 insertions(+)


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v2 2/7] clk: qcom: clk-hfpll: Configure l_val in init when required

[Konrad Dybcio]

On 23.07.2023 18:08, Adam Skladowski wrote:
> Add support for pre-configuring default frequency multiplier,
> this appears to be required on some platforms like MSM8976.
> Without configuring L_VAL device reboots when trying to bring PLL up.
> 
> Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad

Re: [PATCH v2 3/7] clk: qcom: hfpll: Allow matching pdata

[Konrad Dybcio]

On 23.07.2023 18:08, Adam Skladowski wrote:
> HFPLL driver can be used to drive PLLs also on different SoCs like MSM8976
> On MSM8976 each PLL gets it own different configuration,
> add matching pdata to driver to support multiple configurations.
> 
> Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
> ---
>  drivers/clk/qcom/hfpll.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/qcom/hfpll.c b/drivers/clk/qcom/hfpll.c
> index f4d78003d189..ec18bc8f0089 100644
> --- a/drivers/clk/qcom/hfpll.c
> +++ b/drivers/clk/qcom/hfpll.c
> @@ -6,6 +6,7 @@
>  #include <linux/module.h>
>  #include <linux/platform_device.h>
>  #include <linux/of.h>
> +#include <linux/of_device.h>
>  #include <linux/clk.h>
>  #include <linux/clk-provider.h>
>  #include <linux/regmap.h>
> @@ -32,7 +33,7 @@ static const struct hfpll_data hdata = {
>  };
>  
>  static const struct of_device_id qcom_hfpll_match_table[] = {
> -	{ .compatible = "qcom,hfpll" },
> +	{ .compatible = "qcom,hfpll", &hdata },
As Angelo pointed out the last time around, ".data = " is missing

Konrad

Re: [PATCH v2 1/7] drivers: soc: qcom: rpmpd: Fix MSM8976 power domains setup

[Dmitry Baryshkov]

On 23/07/2023 19:08, Adam Skladowski wrote:
> Downstream kernel parses resource names based on pm8950-rpm-regulator.dtsi
> in such file qcom,resource-name takes three values: smpa,ldoa and clk0.
> First appearance of RWSC/RWSM point to msm-4.4 kernel
> which is way newer than what this platform was shipped with (msm-3.10).
> For the max_state downstream code limit value to TURBO inside dts
> with only one turbo_high being placed in msm-thermal bindings.
> One of effects of requesting TURBO_HIGH vote is rebooting of device
> which happens during voting inside WCNSS/IRIS,
> this behavior was observed on LeEco S2 smartphone.
> Fix regulator setup and drop unused resources.
> 
> Fixes: b1d522443b4b ("soc: qcom: rpmpd: Add rpm power domains for msm8976")
> Signed-off-by: Adam Skladowski <a39.skl@gmail.com>

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-- 
With best wishes
Dmitry

Re: [PATCH v2 0/7] MSM8976 PLL,RPMPD and DTS changes

[Dmitry Baryshkov]

On 23/07/2023 19:08, Adam Skladowski wrote:
> This patch series fixes introduce support for msm8976 pll,
> also brings some adjustments and fixes domains setup and few dts nitpicks.

Could you please extend the series with the DT patches utilizing the 
HFPLL? You can keep them disabled via the status property if they are 
not expected to be used yet.

> 
> Changes since v1
> ================
> 1. Fixed few styling issues
> 2. Changed compatibles for plls
> 3. Added fixes: tag to first patch
> 
> Adam Skladowski (7):
>    drivers: soc: qcom: rpmpd: Fix MSM8976 power domains setup
>    clk: qcom: clk-hfpll: Configure l_val in init when required
>    clk: qcom: hfpll: Allow matching pdata
>    dt-bindings: clock: qcom,hfpll: Document MSM8976 compatibles
>    clk: qcom: hfpll: Add MSM8976 PLL data
>    arm64: dts: qcom: msm8976: Split lpass region
>    arm64: dts: qcom: msm8976: Fix smsm ipc bit shifts
> 
>   .../devicetree/bindings/clock/qcom,hfpll.txt  |  3 +
>   arch/arm64/boot/dts/qcom/msm8976.dtsi         | 11 +++-
>   drivers/clk/qcom/clk-hfpll.c                  |  4 ++
>   drivers/clk/qcom/clk-hfpll.h                  |  1 +
>   drivers/clk/qcom/hfpll.c                      | 59 ++++++++++++++++++-
>   drivers/soc/qcom/rpmpd.c                      | 27 ++++-----
>   6 files changed, 83 insertions(+), 22 deletions(-)
> 

-- 
With best wishes
Dmitry

Re: [PATCH v2 5/7] clk: qcom: hfpll: Add MSM8976 PLL data

[Konrad Dybcio]

On 23.07.2023 18:08, Adam Skladowski wrote:
> Add PLL configuration for MSM8976 SoC, this SoC offers 3 HFPLL.
> Small cluster offers two presets for 652-902Mhz range and 902Mhz-1.47Ghz.
> For simplicity only add second range as smaller frequencies can be obtained
> via apcs divider or safe parent this also saves us
> a hassle of reconfiguring VCO bit and config_val.
> A72 and CCI cluster only use single frequency range with their
> outputs/post_dividers/vco_bits being static.
> 
> Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
> ---
[...]

> +static const struct hfpll_data msm8976_a72 = {
> +	.mode_reg = 0x00,
> +	.l_reg = 0x04,
> +	.m_reg = 0x08,
> +	.n_reg = 0x0c,
> +	.user_reg = 0x10,
> +	.config_reg = 0x14,
> +	.config_val = 0x4e0405d,
> +	.status_reg = 0x1c,
> +	.lock_bit = 16,
> +
> +	.l_val = 0x3e,
> +	.user_val = 0x100109,
> +	.min_rate = 940800000UL,
> +	.max_rate = 1843200000UL,
2016000000?

[...]

>  static const struct of_device_id qcom_hfpll_match_table[] = {
>  	{ .compatible = "qcom,hfpll", &hdata },
> +	{ .compatible = "qcom,msm8976-hfpll-a53", &msm8976_a53 },
> +	{ .compatible = "qcom,msm8976-hfpll-a72", &msm8976_a72 },
> +	{ .compatible = "qcom,msm8976-hfpll-cci", &msm8976_cci },
.data = is missing

Konrad

Re: [PATCH v2 6/7] arm64: dts: qcom: msm8976: Split lpass region

[Konrad Dybcio]

On 23.07.2023 18:08, Adam Skladowski wrote:
> Some devices like Sony Loire uses Broadcom module over sdc3 however others
> utilize qcom WCNSS, split shared region based on downstream pil-tz loader.
> 
> Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
> ---
Looks like 0x1800000 is the generic configuration:

https://git.codelinaro.org/clo/la/kernel/msm-3.10/-/blob/LA.BR.1.3.7.c26-05300-8976.0/arch/arm/boot/dts/qcom/msm8976.dtsi#L93-98

Konrad

Re: [PATCH v2 6/7] arm64: dts: qcom: msm8976: Split lpass region

[Adam Skladowski]

On 25.07.2023 10:44, Konrad Dybcio wrote:
> On 23.07.2023 18:08, Adam Skladowski wrote:
>> Some devices like Sony Loire uses Broadcom module over sdc3 however others
>> utilize qcom WCNSS, split shared region based on downstream pil-tz loader.
>>
>> Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
>> ---
> Looks like 0x1800000 is the generic configuration:
>
> https://git.codelinaro.org/clo/la/kernel/msm-3.10/-/blob/LA.BR.1.3.7.c26-05300-8976.0/arch/arm/boot/dts/qcom/msm8976.dtsi#L93-98
>
> Konrad

Yes, indeed however as you probably noticed this region isn't called lpass rather reloc.

Downstream sometimes tends to define pools of memory where loader will do its own job.

If you read later wcnss/lpass both point to same shared memory which im not sure without reworks will work with mainline.

On top it's not really that it will even hurt Loire at the end, if you browse around internet you can easily find gists
from Pavel which have logs of pil-tz loading of lpass:

https://gist.github.com/bartcubbins/c2ff215f39fe2b3ed5d3f8444bcec83b#file-gistfile1-txt-L1289

As you can see even on loire where region is bigger it only loads first 0x1000000.
Do we really need to complicate things just for everyone else for sake of not ending with one platform having to adjust
or even not(it probably wouldn't even make a difference for loader as it will fit anyway)

On the ending note i apologize if this msg gets broken formatting first time using thunderbird
and after redesign im unable to find most options mentioned in guide.
.

Re: [PATCH v2 5/7] clk: qcom: hfpll: Add MSM8976 PLL data

[Adam Skladowski]

On 25.07.2023 10:02, Konrad Dybcio wrote:
> On 23.07.2023 18:08, Adam Skladowski wrote:
>> Add PLL configuration for MSM8976 SoC, this SoC offers 3 HFPLL.
>> Small cluster offers two presets for 652-902Mhz range and 902Mhz-1.47Ghz.
>> For simplicity only add second range as smaller frequencies can be obtained
>> via apcs divider or safe parent this also saves us
>> a hassle of reconfiguring VCO bit and config_val.
>> A72 and CCI cluster only use single frequency range with their
>> outputs/post_dividers/vco_bits being static.
>>
>> Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
>> ---
> [...]
>
>> +static const struct hfpll_data msm8976_a72 = {
>> +	.mode_reg = 0x00,
>> +	.l_reg = 0x04,
>> +	.m_reg = 0x08,
>> +	.n_reg = 0x0c,
>> +	.user_reg = 0x10,
>> +	.config_reg = 0x14,
>> +	.config_val = 0x4e0405d,
>> +	.status_reg = 0x1c,
>> +	.lock_bit = 16,
>> +
>> +	.l_val = 0x3e,
>> +	.user_val = 0x100109,
>> +	.min_rate = 940800000UL,
>> +	.max_rate = 1843200000UL,
> 2016000000?

We are using msm kernel as base not SODP ports.

https://android.googlesource.com/kernel/msm/+/android-lego-6.0.1_r0.2/drivers/clk/qcom/clock-cpu-8976.c
https://android.googlesource.com/kernel/msm.git/+/android-msm-lego-3.10-marshmallow-dr/arch/arm/boot/dts/qcom/msm8976.dtsi#349

> [...]
>>  static const struct of_device_id qcom_hfpll_match_table[] = {
>>  	{ .compatible = "qcom,hfpll", &hdata },
>> +	{ .compatible = "qcom,msm8976-hfpll-a53", &msm8976_a53 },
>> +	{ .compatible = "qcom,msm8976-hfpll-a72", &msm8976_a72 },
>> +	{ .compatible = "qcom,msm8976-hfpll-cci", &msm8976_cci },
> .data = is missing
>
> Konrad

Seems like i took "inspiration" from also not great code, albeit it does work somehow when printing inside init, will fix in v3 

Thanks Angelo/Konrad