From: Anshuman Khandual <anshuman.khandual@arm.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>,
linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, maz@kernel.org,
catalin.marinas@arm.com, mark.rutland@arm.com,
james.morse@arm.com, leo.yan@linaro.org, mike.leach@linaro.org,
mathieu.poirier@linaro.org, will@kernel.org,
lcherian@marvell.com, coresight@lists.linaro.org
Subject: Re: [PATCH v2 02/17] coresight: trbe: Add infrastructure for Errata handling
Date: Wed, 22 Sep 2021 12:17:43 +0530 [thread overview]
Message-ID: <7384656b-2777-d5d5-0c5a-d30ee6dde20a@arm.com> (raw)
In-Reply-To: <20210921134121.2423546-3-suzuki.poulose@arm.com>
On 9/21/21 7:11 PM, Suzuki K Poulose wrote:
> Add a minimal infrastructure to keep track of the errata
> affecting the given TRBE instance. Given that we have
> heterogeneous CPUs, we have to manage the list per-TRBE
> instance to be able to apply the work around as needed.
>
> We rely on the arm64 errata framework for the actual
> description and the discovery of a given erratum, to
> keep the Erratum work around at a central place and
> benefit from the code and the advertisement from the
> kernel. We use a local mapping of the erratum to
> avoid bloating up the individual TRBE structures.
> i.e, each arm64 TRBE erratum bit is assigned a new number
> within the driver to track. Each trbe instance updates
> the list of affected erratum at probe time on the CPU.
> This makes sure that we can easily access the list of
> errata on a given TRBE instance without much overhead.
>
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Cc: Leo Yan <leo.yan@linaro.org>
> Cc: Anshuman Khandual <anshuman.khandual@arm.com>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
> Changes since v1:
> - Flip the order of args for trbe_has_erratum()
> - Move erratum detection further down in the sequence
> ---
> drivers/hwtracing/coresight/coresight-trbe.c | 49 ++++++++++++++++++++
> 1 file changed, 49 insertions(+)
>
> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
> index e3d73751d568..63f7edd5fd1f 100644
> --- a/drivers/hwtracing/coresight/coresight-trbe.c
> +++ b/drivers/hwtracing/coresight/coresight-trbe.c
> @@ -16,6 +16,8 @@
> #define pr_fmt(fmt) DRVNAME ": " fmt
>
> #include <asm/barrier.h>
> +#include <asm/cputype.h>
> +
> #include "coresight-self-hosted-trace.h"
> #include "coresight-trbe.h"
>
> @@ -65,6 +67,35 @@ struct trbe_buf {
> struct trbe_cpudata *cpudata;
> };
>
> +/*
> + * TRBE erratum list
> + *
> + * We rely on the corresponding cpucaps to be defined for a given
> + * TRBE erratum. We map the given cpucap into a TRBE internal number
> + * to make the tracking of the errata lean.
> + *
> + * This helps in :
> + * - Not duplicating the detection logic
> + * - Streamlined detection of erratum across the system
> + *
> + * Since the erratum work arounds could be applied individually
> + * per TRBE instance, we keep track of the list of errata that
> + * affects the given instance of the TRBE.
> + */
> +#define TRBE_ERRATA_MAX 0
> +
> +static unsigned long trbe_errata_cpucaps[TRBE_ERRATA_MAX] = {
> +};
Hence TRBE_ERRATA_MAX needs to be updated manually here when new
TRBE specific erratums get added to the cpucap list. Hence lets
add a comment indicating that the TRBE_ERRATA_MAX needs explicit
syncing with changes to cpucap list.
> +
> +/*
> + * struct trbe_cpudata: TRBE instance specific data
> + * @trbe_flag - TRBE dirty/access flag support
> + * @tbre_align - Actual TRBE alignment required for TRBPTR_EL1.
> + * @cpu - CPU this TRBE belongs to.
> + * @mode - Mode of current operation. (perf/disabled)
> + * @drvdata - TRBE specific drvdata
> + * @errata - Bit map for the errata on this TRBE.
> + */
> struct trbe_cpudata {
> bool trbe_flag;
> u64 trbe_align;
> @@ -72,6 +103,7 @@ struct trbe_cpudata {
> enum cs_mode mode;
> struct trbe_buf *buf;
> struct trbe_drvdata *drvdata;
> + DECLARE_BITMAP(errata, TRBE_ERRATA_MAX);
> };
>
> struct trbe_drvdata {
> @@ -84,6 +116,21 @@ struct trbe_drvdata {
> struct platform_device *pdev;
> };
>
> +static void trbe_check_errata(struct trbe_cpudata *cpudata)
> +{
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(trbe_errata_cpucaps); i++) {
> + if (this_cpu_has_cap(trbe_errata_cpucaps[i]))
> + set_bit(i, cpudata->errata);
> + }
> +}
> +
> +static inline bool trbe_has_erratum(struct trbe_cpudata *cpudata, int i)
> +{
> + return (i < TRBE_ERRATA_MAX) && test_bit(i, cpudata->errata);
> +}
> +
> static int trbe_alloc_node(struct perf_event *event)
> {
> if (event->cpu == -1)
> @@ -926,6 +973,8 @@ static void arm_trbe_probe_cpu(void *info)
> pr_err("Unsupported alignment on cpu %d\n", cpu);
> goto cpu_clear;
> }
> +
> + trbe_check_errata(cpudata);
This could be moved further down just before the 'return' statement.
Lets not interrupt cpudata init sequence, rather run all the errata
detection right at the end.
> cpudata->trbe_flag = get_trbe_flag_update(trbidr);
> cpudata->cpu = cpu;
> cpudata->drvdata = drvdata;
>
next prev parent reply other threads:[~2021-09-22 6:46 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-21 13:41 [PATCH v2 00/17] arm64: Self-hosted trace related errata workarounds Suzuki K Poulose
2021-09-21 13:41 ` [PATCH v2 01/17] coresight: trbe: Fix incorrect access of the sink specific data Suzuki K Poulose
2021-09-22 5:41 ` Anshuman Khandual
2021-09-30 17:57 ` Mathieu Poirier
2021-09-21 13:41 ` [PATCH v2 02/17] coresight: trbe: Add infrastructure for Errata handling Suzuki K Poulose
2021-09-22 6:47 ` Anshuman Khandual [this message]
2021-10-05 16:46 ` Mathieu Poirier
2021-09-21 13:41 ` [PATCH v2 03/17] coresight: trbe: Add a helper to calculate the trace generated Suzuki K Poulose
2021-09-30 17:54 ` Mathieu Poirier
2021-10-01 8:36 ` Suzuki K Poulose
2021-10-01 15:15 ` Mathieu Poirier
2021-10-01 15:22 ` Suzuki K Poulose
2021-09-21 13:41 ` [PATCH v2 04/17] coresight: trbe: Add a helper to pad a given buffer area Suzuki K Poulose
2021-09-21 13:41 ` [PATCH v2 05/17] coresight: trbe: Decouple buffer base from the hardware base Suzuki K Poulose
2021-09-21 13:41 ` [PATCH v2 06/17] coresight: trbe: Allow driver to choose a different alignment Suzuki K Poulose
2021-09-21 13:41 ` [PATCH v2 07/17] arm64: Add Neoverse-N2, Cortex-A710 CPU part definition Suzuki K Poulose
2021-09-22 6:57 ` Anshuman Khandual
2021-09-21 13:41 ` [PATCH v2 08/17] arm64: Add erratum detection for TRBE overwrite in FILL mode Suzuki K Poulose
2021-09-21 13:41 ` [PATCH v2 09/17] coresight: trbe: Workaround TRBE errata " Suzuki K Poulose
2021-09-23 6:13 ` Anshuman Khandual
2021-09-28 10:40 ` Suzuki K Poulose
2021-10-01 4:21 ` Anshuman Khandual
2021-10-01 17:15 ` Mathieu Poirier
2021-10-04 8:46 ` Suzuki K Poulose
2021-10-04 16:47 ` Mathieu Poirier
2021-09-21 13:41 ` [PATCH v2 10/17] arm64: Enable workaround for TRBE " Suzuki K Poulose
2021-09-22 7:23 ` Anshuman Khandual
2021-09-22 8:11 ` Suzuki K Poulose
2021-10-01 4:35 ` Anshuman Khandual
2021-10-07 16:09 ` Catalin Marinas
2021-09-21 13:41 ` [PATCH v2 11/17] arm64: errata: Add workaround for TSB flush failures Suzuki K Poulose
2021-09-22 7:39 ` Anshuman Khandual
2021-09-22 12:03 ` Suzuki K Poulose
2021-10-01 4:38 ` Anshuman Khandual
2021-10-07 16:10 ` Catalin Marinas
2021-09-21 13:41 ` [PATCH v2 12/17] coresight: trbe: Add a helper to fetch cpudata from perf handle Suzuki K Poulose
2021-09-22 7:59 ` Anshuman Khandual
2021-10-04 17:42 ` Mathieu Poirier
2021-10-05 22:35 ` Suzuki K Poulose
2021-10-06 17:15 ` Mathieu Poirier
2021-10-07 9:18 ` Suzuki K Poulose
2021-09-21 13:41 ` [PATCH v2 13/17] coresight: trbe: Add a helper to determine the minimum buffer size Suzuki K Poulose
2021-09-22 9:51 ` Anshuman Khandual
2021-09-21 13:41 ` [PATCH v2 14/17] coresight: trbe: Make sure we have enough space Suzuki K Poulose
2021-09-22 9:58 ` Anshuman Khandual
2021-09-22 10:16 ` Suzuki K Poulose
2021-10-01 4:40 ` Anshuman Khandual
2021-09-21 13:41 ` [PATCH v2 15/17] arm64: Add erratum detection for TRBE write to out-of-range Suzuki K Poulose
2021-09-22 10:59 ` Anshuman Khandual
2021-10-07 16:10 ` Catalin Marinas
2021-09-21 13:41 ` [PATCH v2 16/17] coresight: trbe: Work around write to out of range Suzuki K Poulose
2021-09-23 3:15 ` Anshuman Khandual
2021-09-28 10:32 ` Suzuki K Poulose
2021-10-01 4:56 ` Anshuman Khandual
2021-09-21 13:41 ` [PATCH v2 17/17] arm64: Advertise TRBE erratum workaround for write to out-of-range address Suzuki K Poulose
2021-09-22 11:03 ` Anshuman Khandual
2021-10-07 16:11 ` Catalin Marinas
2021-10-05 17:04 ` [PATCH v2 00/17] arm64: Self-hosted trace related errata workarounds Mathieu Poirier
2021-10-08 7:32 ` Will Deacon
2021-10-08 9:25 ` Suzuki K Poulose
2021-10-08 9:52 ` Will Deacon
2021-10-08 9:57 ` Suzuki K Poulose
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