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From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, maz@kernel.org,
	catalin.marinas@arm.com, mark.rutland@arm.com,
	james.morse@arm.com, anshuman.khandual@arm.com,
	leo.yan@linaro.org, mike.leach@linaro.org, will@kernel.org,
	lcherian@marvell.com, coresight@lists.linaro.org
Subject: Re: [PATCH v2 12/17] coresight: trbe: Add a helper to fetch cpudata from perf handle
Date: Thu, 7 Oct 2021 10:18:42 +0100	[thread overview]
Message-ID: <8cecf6d2-f1ff-5b9c-7969-24124a00944e@arm.com> (raw)
In-Reply-To: <20211006171536.GA3373323@p14s>

On 06/10/2021 18:15, Mathieu Poirier wrote:
> On Tue, Oct 05, 2021 at 11:35:13PM +0100, Suzuki K Poulose wrote:
>> Hi Mathieu
>>
>> On 04/10/2021 18:42, Mathieu Poirier wrote:
>>> On Tue, Sep 21, 2021 at 02:41:16PM +0100, Suzuki K Poulose wrote:
>>>> Add a helper to get the CPU specific data for TRBE instance, from
>>>> a given perf handle. This also adds extra checks to make sure that
>>>> the event associated with the handle is "bound" to the CPU and is
>>>> active on the TRBE.
>>>>
>>>> Cc: Anshuman Khandual <anshuman.khandual@arm.com>
>>>> Cc: Mike Leach <mike.leach@linaro.org>
>>>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>>>> Cc: Leo Yan <leo.yan@linaro.org>
>>>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>>>> ---
>>>>    drivers/hwtracing/coresight/coresight-trbe.c | 12 ++++++++++--
>>>>    1 file changed, 10 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
>>>> index 983dd5039e52..797d978f9fa7 100644
>>>> --- a/drivers/hwtracing/coresight/coresight-trbe.c
>>>> +++ b/drivers/hwtracing/coresight/coresight-trbe.c
>>>> @@ -268,6 +268,15 @@ static unsigned long trbe_snapshot_offset(struct perf_output_handle *handle)
>>>>    	return buf->nr_pages * PAGE_SIZE;
>>>>    }
>>>> +static inline struct trbe_cpudata *
>>>> +trbe_handle_to_cpudata(struct perf_output_handle *handle)
>>>> +{
>>>> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
>>>> +
>>>> +	BUG_ON(!buf || !buf->cpudata);
>>>> +	return buf->cpudata;
>>>> +}
>>>> +
>>>>    /*
>>>>     * TRBE Limit Calculation
>>>>     *
>>>> @@ -533,8 +542,7 @@ static enum trbe_fault_action trbe_get_fault_act(struct perf_output_handle *hand
>>>>    {
>>>>    	int ec = get_trbe_ec(trbsr);
>>>>    	int bsc = get_trbe_bsc(trbsr);
>>>> -	struct trbe_buf *buf = etm_perf_sink_config(handle);
>>>> -	struct trbe_cpudata *cpudata = buf->cpudata;
>>>> +	struct trbe_cpudata *cpudata = trbe_handle_to_cpudata(handle);
>>>
>>> There is two other places where this pattern is present:  is_perf_trbe() and
>>> __trbe_normal_offset().
>>
>> I skipped them, as they have to get access to the "trbe_buf" anyways.
>> So the step by step, made sense. But I could replace them too to make it
>> transparent.
>>
>> What do you think ?
> 
> Humm...  I don't think there is a right way or a wrong way here.  If we move
> forward with this patchset we have two ways of getting to buf->cpudata.  One
> using trbe_handle_to_cpudata() and another one as laid out in is_perf_trbe() and
> __trbe_normal_offset(), each with an equal number of occurences (2 for each).
> 
> I am usually not fond of small functions like trbe_handle_to_cpudata() and to me
> keeping the current heuristic in trbe_get_fault_act() would have been just fine.

There is another user introduced in the work around patch. But, yes, I
agree, we could open code it, rather than having it inconsistent across
the driver.

> I agree with the argument that trbe_handle_to_cpudata() provides more checks but
> is it really worth it if they aren't done everywhere?
> 
> In short I would get rid of trbe_handle_to_cpudata() entirely and live without
> the extra checks... But I'm not strongly opinionated on this either.

Ok, I will remove this then. Thanks for the feedback.

Suzuki

  reply	other threads:[~2021-10-07  9:18 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-21 13:41 [PATCH v2 00/17] arm64: Self-hosted trace related errata workarounds Suzuki K Poulose
2021-09-21 13:41 ` [PATCH v2 01/17] coresight: trbe: Fix incorrect access of the sink specific data Suzuki K Poulose
2021-09-22  5:41   ` Anshuman Khandual
2021-09-30 17:57   ` Mathieu Poirier
2021-09-21 13:41 ` [PATCH v2 02/17] coresight: trbe: Add infrastructure for Errata handling Suzuki K Poulose
2021-09-22  6:47   ` Anshuman Khandual
2021-10-05 16:46   ` Mathieu Poirier
2021-09-21 13:41 ` [PATCH v2 03/17] coresight: trbe: Add a helper to calculate the trace generated Suzuki K Poulose
2021-09-30 17:54   ` Mathieu Poirier
2021-10-01  8:36     ` Suzuki K Poulose
2021-10-01 15:15       ` Mathieu Poirier
2021-10-01 15:22         ` Suzuki K Poulose
2021-09-21 13:41 ` [PATCH v2 04/17] coresight: trbe: Add a helper to pad a given buffer area Suzuki K Poulose
2021-09-21 13:41 ` [PATCH v2 05/17] coresight: trbe: Decouple buffer base from the hardware base Suzuki K Poulose
2021-09-21 13:41 ` [PATCH v2 06/17] coresight: trbe: Allow driver to choose a different alignment Suzuki K Poulose
2021-09-21 13:41 ` [PATCH v2 07/17] arm64: Add Neoverse-N2, Cortex-A710 CPU part definition Suzuki K Poulose
2021-09-22  6:57   ` Anshuman Khandual
2021-09-21 13:41 ` [PATCH v2 08/17] arm64: Add erratum detection for TRBE overwrite in FILL mode Suzuki K Poulose
2021-09-21 13:41 ` [PATCH v2 09/17] coresight: trbe: Workaround TRBE errata " Suzuki K Poulose
2021-09-23  6:13   ` Anshuman Khandual
2021-09-28 10:40     ` Suzuki K Poulose
2021-10-01  4:21       ` Anshuman Khandual
2021-10-01 17:15   ` Mathieu Poirier
2021-10-04  8:46     ` Suzuki K Poulose
2021-10-04 16:47       ` Mathieu Poirier
2021-09-21 13:41 ` [PATCH v2 10/17] arm64: Enable workaround for TRBE " Suzuki K Poulose
2021-09-22  7:23   ` Anshuman Khandual
2021-09-22  8:11     ` Suzuki K Poulose
2021-10-01  4:35       ` Anshuman Khandual
2021-10-07 16:09   ` Catalin Marinas
2021-09-21 13:41 ` [PATCH v2 11/17] arm64: errata: Add workaround for TSB flush failures Suzuki K Poulose
2021-09-22  7:39   ` Anshuman Khandual
2021-09-22 12:03     ` Suzuki K Poulose
2021-10-01  4:38       ` Anshuman Khandual
2021-10-07 16:10   ` Catalin Marinas
2021-09-21 13:41 ` [PATCH v2 12/17] coresight: trbe: Add a helper to fetch cpudata from perf handle Suzuki K Poulose
2021-09-22  7:59   ` Anshuman Khandual
2021-10-04 17:42   ` Mathieu Poirier
2021-10-05 22:35     ` Suzuki K Poulose
2021-10-06 17:15       ` Mathieu Poirier
2021-10-07  9:18         ` Suzuki K Poulose [this message]
2021-09-21 13:41 ` [PATCH v2 13/17] coresight: trbe: Add a helper to determine the minimum buffer size Suzuki K Poulose
2021-09-22  9:51   ` Anshuman Khandual
2021-09-21 13:41 ` [PATCH v2 14/17] coresight: trbe: Make sure we have enough space Suzuki K Poulose
2021-09-22  9:58   ` Anshuman Khandual
2021-09-22 10:16     ` Suzuki K Poulose
2021-10-01  4:40       ` Anshuman Khandual
2021-09-21 13:41 ` [PATCH v2 15/17] arm64: Add erratum detection for TRBE write to out-of-range Suzuki K Poulose
2021-09-22 10:59   ` Anshuman Khandual
2021-10-07 16:10   ` Catalin Marinas
2021-09-21 13:41 ` [PATCH v2 16/17] coresight: trbe: Work around write to out of range Suzuki K Poulose
2021-09-23  3:15   ` Anshuman Khandual
2021-09-28 10:32     ` Suzuki K Poulose
2021-10-01  4:56       ` Anshuman Khandual
2021-09-21 13:41 ` [PATCH v2 17/17] arm64: Advertise TRBE erratum workaround for write to out-of-range address Suzuki K Poulose
2021-09-22 11:03   ` Anshuman Khandual
2021-10-07 16:11   ` Catalin Marinas
2021-10-05 17:04 ` [PATCH v2 00/17] arm64: Self-hosted trace related errata workarounds Mathieu Poirier
2021-10-08  7:32 ` Will Deacon
2021-10-08  9:25   ` Suzuki K Poulose
2021-10-08  9:52     ` Will Deacon
2021-10-08  9:57       ` Suzuki K Poulose

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