* [PATCH v3 0/3] Add Global Clock controller (GCC) driver for SC7180
@ 2019-09-18 9:50 Taniya Das
2019-09-18 9:50 ` [PATCH v3 1/3] clk: qcom: rcg: update the DFS macro for RCG Taniya Das
` (2 more replies)
0 siblings, 3 replies; 25+ messages in thread
From: Taniya Das @ 2019-09-18 9:50 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette , robh+dt
Cc: David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, devicetree, Taniya Das
[v3]
* Remove old documentation and fix comments for binding.
* Cleanup few CRITICAL clocks and add comments for the CRITICAL clocks.
* Add reference clocks for UFS & USB.
[v2]
* Update the DFS macro for RCG to reflect the hw init similar to clock
name.
* Update the Documentation binding of GCC to YAML schemas.
* Add comments for CRITICAL clocks, remove PLL forward declarations and
unwanted comments/prints.
[v1]
* Add driver support for Global Clock controller for SC7180 and also
update device tree bindings for the various clocks supported in the
clock controller.
Taniya Das (3):
clk: qcom: rcg: update the DFS macro for RCG
dt-bindings: clk: qcom: Add YAML schemas for the GCC clock bindings
clk: qcom: Add Global Clock controller (GCC) driver for SC7180
.../devicetree/bindings/clock/qcom,gcc.txt | 94 -
.../devicetree/bindings/clock/qcom,gcc.yaml | 157 +
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk-rcg.h | 2 +-
drivers/clk/qcom/gcc-sc7180.c | 2515 +++++++++++++++++
drivers/clk/qcom/gcc-sdm845.c | 96 +-
include/dt-bindings/clock/qcom,gcc-sc7180.h | 155 +
8 files changed, 2886 insertions(+), 143 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc.txt
create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc.yaml
create mode 100644 drivers/clk/qcom/gcc-sc7180.c
create mode 100644 include/dt-bindings/clock/qcom,gcc-sc7180.h
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the Linux Foundation.
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v3 1/3] clk: qcom: rcg: update the DFS macro for RCG
2019-09-18 9:50 [PATCH v3 0/3] Add Global Clock controller (GCC) driver for SC7180 Taniya Das
@ 2019-09-18 9:50 ` Taniya Das
2019-09-18 9:50 ` [PATCH v3 2/3] dt-bindings: clk: qcom: Add YAML schemas for the GCC clock bindings Taniya Das
2019-09-18 9:50 ` [PATCH v3 3/3] clk: qcom: Add Global Clock controller (GCC) driver for SC7180 Taniya Das
2 siblings, 0 replies; 25+ messages in thread
From: Taniya Das @ 2019-09-18 9:50 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette , robh+dt
Cc: David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, devicetree, Taniya Das
Update the init data name for each of the dynamic frequency switch
controlled clock associated with the RCG clock name, so that it can be
generated as per the hardware plan. Thus update the macro accordingly.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
---
drivers/clk/qcom/clk-rcg.h | 2 +-
drivers/clk/qcom/gcc-sdm845.c | 96 +++++++++++++++++------------------
2 files changed, 49 insertions(+), 49 deletions(-)
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index c25b57c3cbc8..78358b81d249 100644
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -168,7 +168,7 @@ struct clk_rcg_dfs_data {
};
#define DEFINE_RCG_DFS(r) \
- { .rcg = &r##_src, .init = &r##_init }
+ { .rcg = &r, .init = &r##_init }
extern int qcom_cc_register_rcg_dfs(struct regmap *regmap,
const struct clk_rcg_dfs_data *rcgs,
diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index 95be125c3bdd..d2142fe46a8e 100644
--- a/drivers/clk/qcom/gcc-sdm845.c
+++ b/drivers/clk/qcom/gcc-sdm845.c
@@ -408,7 +408,7 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
{ }
};
-static struct clk_init_data gcc_qupv3_wrap0_s0_clk_init = {
+static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
.name = "gcc_qupv3_wrap0_s0_clk_src",
.parent_names = gcc_parent_names_0,
.num_parents = 4,
@@ -421,10 +421,10 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
- .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_init,
+ .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
};
-static struct clk_init_data gcc_qupv3_wrap0_s1_clk_init = {
+static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
.name = "gcc_qupv3_wrap0_s1_clk_src",
.parent_names = gcc_parent_names_0,
.num_parents = 4,
@@ -437,10 +437,10 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
- .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_init,
+ .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
};
-static struct clk_init_data gcc_qupv3_wrap0_s2_clk_init = {
+static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
.name = "gcc_qupv3_wrap0_s2_clk_src",
.parent_names = gcc_parent_names_0,
.num_parents = 4,
@@ -453,10 +453,10 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
- .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_init,
+ .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
};
-static struct clk_init_data gcc_qupv3_wrap0_s3_clk_init = {
+static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
.name = "gcc_qupv3_wrap0_s3_clk_src",
.parent_names = gcc_parent_names_0,
.num_parents = 4,
@@ -469,10 +469,10 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
- .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_init,
+ .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
};
-static struct clk_init_data gcc_qupv3_wrap0_s4_clk_init = {
+static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
.name = "gcc_qupv3_wrap0_s4_clk_src",
.parent_names = gcc_parent_names_0,
.num_parents = 4,
@@ -485,10 +485,10 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
- .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_init,
+ .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
};
-static struct clk_init_data gcc_qupv3_wrap0_s5_clk_init = {
+static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
.name = "gcc_qupv3_wrap0_s5_clk_src",
.parent_names = gcc_parent_names_0,
.num_parents = 4,
@@ -501,10 +501,10 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
- .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_init,
+ .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
};
-static struct clk_init_data gcc_qupv3_wrap0_s6_clk_init = {
+static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
.name = "gcc_qupv3_wrap0_s6_clk_src",
.parent_names = gcc_parent_names_0,
.num_parents = 4,
@@ -517,10 +517,10 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
- .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_init,
+ .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
};
-static struct clk_init_data gcc_qupv3_wrap0_s7_clk_init = {
+static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
.name = "gcc_qupv3_wrap0_s7_clk_src",
.parent_names = gcc_parent_names_0,
.num_parents = 4,
@@ -533,10 +533,10 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
- .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_init,
+ .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
};
-static struct clk_init_data gcc_qupv3_wrap1_s0_clk_init = {
+static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
.name = "gcc_qupv3_wrap1_s0_clk_src",
.parent_names = gcc_parent_names_0,
.num_parents = 4,
@@ -549,10 +549,10 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
- .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_init,
+ .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
};
-static struct clk_init_data gcc_qupv3_wrap1_s1_clk_init = {
+static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
.name = "gcc_qupv3_wrap1_s1_clk_src",
.parent_names = gcc_parent_names_0,
.num_parents = 4,
@@ -565,10 +565,10 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
- .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_init,
+ .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
};
-static struct clk_init_data gcc_qupv3_wrap1_s2_clk_init = {
+static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
.name = "gcc_qupv3_wrap1_s2_clk_src",
.parent_names = gcc_parent_names_0,
.num_parents = 4,
@@ -581,10 +581,10 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
- .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_init,
+ .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
};
-static struct clk_init_data gcc_qupv3_wrap1_s3_clk_init = {
+static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
.name = "gcc_qupv3_wrap1_s3_clk_src",
.parent_names = gcc_parent_names_0,
.num_parents = 4,
@@ -597,10 +597,10 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
- .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_init,
+ .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
};
-static struct clk_init_data gcc_qupv3_wrap1_s4_clk_init = {
+static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
.name = "gcc_qupv3_wrap1_s4_clk_src",
.parent_names = gcc_parent_names_0,
.num_parents = 4,
@@ -613,10 +613,10 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
- .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_init,
+ .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
};
-static struct clk_init_data gcc_qupv3_wrap1_s5_clk_init = {
+static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
.name = "gcc_qupv3_wrap1_s5_clk_src",
.parent_names = gcc_parent_names_0,
.num_parents = 4,
@@ -629,10 +629,10 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
- .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_init,
+ .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
};
-static struct clk_init_data gcc_qupv3_wrap1_s6_clk_init = {
+static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
.name = "gcc_qupv3_wrap1_s6_clk_src",
.parent_names = gcc_parent_names_0,
.num_parents = 4,
@@ -645,10 +645,10 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
- .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_init,
+ .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
};
-static struct clk_init_data gcc_qupv3_wrap1_s7_clk_init = {
+static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
.name = "gcc_qupv3_wrap1_s7_clk_src",
.parent_names = gcc_parent_names_0,
.num_parents = 4,
@@ -661,7 +661,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
- .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_init,
+ .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
@@ -3577,22 +3577,22 @@ static const struct of_device_id gcc_sdm845_match_table[] = {
MODULE_DEVICE_TABLE(of, gcc_sdm845_match_table);
static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
- DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk),
- DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk),
- DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk),
- DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk),
- DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk),
- DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk),
- DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk),
- DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk),
- DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk),
- DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk),
- DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk),
- DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk),
- DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk),
- DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk),
- DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk),
- DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src),
};
static int gcc_sdm845_probe(struct platform_device *pdev)
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the Linux Foundation.
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 2/3] dt-bindings: clk: qcom: Add YAML schemas for the GCC clock bindings
2019-09-18 9:50 [PATCH v3 0/3] Add Global Clock controller (GCC) driver for SC7180 Taniya Das
2019-09-18 9:50 ` [PATCH v3 1/3] clk: qcom: rcg: update the DFS macro for RCG Taniya Das
@ 2019-09-18 9:50 ` Taniya Das
2019-09-18 17:52 ` Matthias Kaehlcke
` (2 more replies)
2019-09-18 9:50 ` [PATCH v3 3/3] clk: qcom: Add Global Clock controller (GCC) driver for SC7180 Taniya Das
2 siblings, 3 replies; 25+ messages in thread
From: Taniya Das @ 2019-09-18 9:50 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette , robh+dt
Cc: David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, devicetree, Taniya Das
The GCC clock provider have a bunch of generic properties that
are needed in a device tree. Add a YAML schemas for those. Also update
the compatible for SC7180 along with example for clocks & clock-names.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
---
.../devicetree/bindings/clock/qcom,gcc.txt | 94 -----------
.../devicetree/bindings/clock/qcom,gcc.yaml | 157 ++++++++++++++++++
include/dt-bindings/clock/qcom,gcc-sc7180.h | 155 +++++++++++++++++
3 files changed, 312 insertions(+), 94 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc.txt
create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc.yaml
create mode 100644 include/dt-bindings/clock/qcom,gcc-sc7180.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
deleted file mode 100644
index d14362ad4132..000000000000
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ /dev/null
@@ -1,94 +0,0 @@
-Qualcomm Global Clock & Reset Controller Binding
-------------------------------------------------
-
-Required properties :
-- compatible : shall contain only one of the following:
-
- "qcom,gcc-apq8064"
- "qcom,gcc-apq8084"
- "qcom,gcc-ipq8064"
- "qcom,gcc-ipq4019"
- "qcom,gcc-ipq8074"
- "qcom,gcc-msm8660"
- "qcom,gcc-msm8916"
- "qcom,gcc-msm8960"
- "qcom,gcc-msm8974"
- "qcom,gcc-msm8974pro"
- "qcom,gcc-msm8974pro-ac"
- "qcom,gcc-msm8994"
- "qcom,gcc-msm8996"
- "qcom,gcc-msm8998"
- "qcom,gcc-mdm9615"
- "qcom,gcc-qcs404"
- "qcom,gcc-sdm630"
- "qcom,gcc-sdm660"
- "qcom,gcc-sdm845"
- "qcom,gcc-sm8150"
-
-- reg : shall contain base register location and length
-- #clock-cells : shall contain 1
-- #reset-cells : shall contain 1
-
-Optional properties :
-- #power-domain-cells : shall contain 1
-- Qualcomm TSENS (thermal sensor device) on some devices can
-be part of GCC and hence the TSENS properties can also be
-part of the GCC/clock-controller node.
-For more details on the TSENS properties please refer
-Documentation/devicetree/bindings/thermal/qcom-tsens.txt
-- protected-clocks : Protected clock specifier list as per common clock
- binding.
-
-For SM8150 only:
- - clocks: a list of phandles and clock-specifier pairs,
- one for each entry in clock-names.
- - clock-names: "bi_tcxo" (required)
- "sleep_clk" (optional)
- "aud_ref_clock" (optional)
-
-Example:
- clock-controller@900000 {
- compatible = "qcom,gcc-msm8960";
- reg = <0x900000 0x4000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
- };
-
-Example of GCC with TSENS properties:
- clock-controller@900000 {
- compatible = "qcom,gcc-apq8064";
- reg = <0x00900000 0x4000>;
- nvmem-cells = <&tsens_calib>, <&tsens_backup>;
- nvmem-cell-names = "calib", "calib_backup";
- #clock-cells = <1>;
- #reset-cells = <1>;
- #thermal-sensor-cells = <1>;
- };
-
-Example of GCC with protected-clocks properties:
- clock-controller@100000 {
- compatible = "qcom,gcc-sdm845";
- reg = <0x100000 0x1f0000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
- protected-clocks = <GCC_QSPI_CORE_CLK>,
- <GCC_QSPI_CORE_CLK_SRC>,
- <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
- <GCC_LPASS_Q6_AXI_CLK>,
- <GCC_LPASS_SWAY_CLK>;
- };
-
-Example of GCC with clocks
- gcc: clock-controller@100000 {
- compatible = "qcom,gcc-sm8150";
- reg = <0x00100000 0x1f0000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
- clock-names = "bi_tcxo",
- "sleep_clk";
- clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
- <&sleep_clk>;
- };
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
new file mode 100644
index 000000000000..056a7977c458
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
@@ -0,0 +1,157 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,gcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller Binding
+
+maintainers:
+ - Stephen Boyd <sboyd@kernel.org>
+
+properties:
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+ reg:
+ maxItems: 1
+
+ compatible :
+ enum:
+ - qcom,gcc-apq8064
+ - qcom,gcc-apq8084
+ - qcom,gcc-ipq8064
+ - qcom,gcc-ipq4019
+ - qcom,gcc-ipq8074
+ - qcom,gcc-msm8660
+ - qcom,gcc-msm8916
+ - qcom,gcc-msm8960
+ - qcom,gcc-msm8974
+ - qcom,gcc-msm8974pro
+ - qcom,gcc-msm8974pro-ac
+ - qcom,gcc-msm8994
+ - qcom,gcc-msm8996
+ - qcom,gcc-msm8998
+ - qcom,gcc-mdm9615
+ - qcom,gcc-qcs404
+ - qcom,gcc-sdm630
+ - qcom,gcc-sdm660
+ - qcom,gcc-sdm845
+ - qcom,gcc-sm8150
+ - qcom,gcc-sc7180
+
+ clocks:
+ minItems: 1
+ maxItems: 3
+ items:
+ - description: Board XO source
+ - description: Board active XO source
+ - description: Sleep clock source(optional)
+
+ clock-names:
+ minItems: 1
+ maxItems: 3
+ items:
+ - const: bi_tcxo
+ - const: bi_tcxo_ao
+ - const: sleep_clk
+
+ nvmem-cells:
+ minItems: 1
+ maxItems: 2
+ description:
+ Qualcomm TSENS (thermal sensor device) on some devices can
+ be part of GCC and hence the TSENS properties can also be part
+ of the GCC/clock-controller node.
+ For more details on the TSENS properties please refer
+ Documentation/devicetree/bindings/thermal/qcom-tsens.txt
+
+ nvmem-cell-names:
+ minItems: 1
+ maxItems: 2
+ description:
+ Names for each nvmem-cells specified.
+ items:
+ - const: calib
+ - const: calib_backup
+
+ "#thermal-sensor-cells":
+ const: 1
+
+ "#power-domain-cells":
+ const: 1
+
+ protected-clocks:
+ description:
+ Protected clock specifier list as per common clock binding
+
+required:
+ - "#clock-cells"
+ - "#reset-cells"
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+examples:
+ - |
+ // Example:
+ clock-controller@900000 {
+ compatible = "qcom,gcc-msm8960";
+ reg = <0x900000 0x4000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+
+ - |
+ // Example of GCC with TSENS properties:
+ clock-controller@900000 {
+ compatible = "qcom,gcc-apq8064";
+ reg = <0x00900000 0x4000>;
+ nvmem-cells = <&tsens_calib>, <&tsens_backup>;
+ nvmem-cell-names = "calib", "calib_backup";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ - |
+ //Example of GCC with protected-clocks properties:
+ clock-controller@100000 {
+ compatible = "qcom,gcc-sdm845";
+ reg = <0x100000 0x1f0000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ protected-clocks = <187>, <188>, <189>, <190>, <191>;
+ };
+
+ - |
+ //Example of GCC with clock node properties for SM8150:
+ clock-controller@100000 {
+ compatible = "qcom,gcc-sm8150";
+ reg = <0x00100000 0x1f0000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ clocks = <&rpmhcc 0>, <&rpmhcc 1>, <&sleep_clk>;
+ clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
+ };
+
+ - |
+ //Example of GCC with clock nodes properties:
+ clock-controller@100000 {
+ compatible = "qcom,gcc-sc7180";
+ reg = <0x100000 0x1f0000>;
+ clocks = <&rpmhcc 0>, <&rpmhcc 1>;
+ clock-names = "bi_tcxo", "bi_tcxo_ao";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/include/dt-bindings/clock/qcom,gcc-sc7180.h b/include/dt-bindings/clock/qcom,gcc-sc7180.h
new file mode 100644
index 000000000000..d76b061f6a4e
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-sc7180.h
@@ -0,0 +1,155 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SC7180_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_SC7180_H
+
+/* GCC clocks */
+#define GCC_GPLL0_MAIN_DIV_CDIV 0
+#define GPLL0 1
+#define GPLL0_OUT_EVEN 2
+#define GPLL1 3
+#define GPLL4 4
+#define GPLL6 5
+#define GPLL7 6
+#define GCC_AGGRE_UFS_PHY_AXI_CLK 7
+#define GCC_AGGRE_USB3_PRIM_AXI_CLK 8
+#define GCC_BOOT_ROM_AHB_CLK 9
+#define GCC_CAMERA_AHB_CLK 10
+#define GCC_CAMERA_HF_AXI_CLK 11
+#define GCC_CAMERA_THROTTLE_HF_AXI_CLK 12
+#define GCC_CAMERA_XO_CLK 13
+#define GCC_CE1_AHB_CLK 14
+#define GCC_CE1_AXI_CLK 15
+#define GCC_CE1_CLK 16
+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 17
+#define GCC_CPUSS_AHB_CLK 18
+#define GCC_CPUSS_AHB_CLK_SRC 19
+#define GCC_CPUSS_GNOC_CLK 20
+#define GCC_CPUSS_RBCPR_CLK 21
+#define GCC_DDRSS_GPU_AXI_CLK 22
+#define GCC_DISP_AHB_CLK 23
+#define GCC_DISP_GPLL0_CLK_SRC 24
+#define GCC_DISP_GPLL0_DIV_CLK_SRC 25
+#define GCC_DISP_HF_AXI_CLK 26
+#define GCC_DISP_THROTTLE_HF_AXI_CLK 27
+#define GCC_DISP_XO_CLK 28
+#define GCC_GP1_CLK 29
+#define GCC_GP1_CLK_SRC 30
+#define GCC_GP2_CLK 31
+#define GCC_GP2_CLK_SRC 32
+#define GCC_GP3_CLK 33
+#define GCC_GP3_CLK_SRC 34
+#define GCC_GPU_CFG_AHB_CLK 35
+#define GCC_GPU_GPLL0_CLK_SRC 36
+#define GCC_GPU_GPLL0_DIV_CLK_SRC 37
+#define GCC_GPU_MEMNOC_GFX_CLK 38
+#define GCC_GPU_SNOC_DVM_GFX_CLK 39
+#define GCC_NPU_AXI_CLK 40
+#define GCC_NPU_BWMON_AXI_CLK 41
+#define GCC_NPU_BWMON_DMA_CFG_AHB_CLK 42
+#define GCC_NPU_BWMON_DSP_CFG_AHB_CLK 43
+#define GCC_NPU_CFG_AHB_CLK 44
+#define GCC_NPU_DMA_CLK 45
+#define GCC_NPU_GPLL0_CLK_SRC 46
+#define GCC_NPU_GPLL0_DIV_CLK_SRC 47
+#define GCC_PDM2_CLK 48
+#define GCC_PDM2_CLK_SRC 49
+#define GCC_PDM_AHB_CLK 50
+#define GCC_PDM_XO4_CLK 51
+#define GCC_PRNG_AHB_CLK 52
+#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 53
+#define GCC_QSPI_CORE_CLK 54
+#define GCC_QSPI_CORE_CLK_SRC 55
+#define GCC_QUPV3_WRAP0_CORE_2X_CLK 56
+#define GCC_QUPV3_WRAP0_CORE_CLK 57
+#define GCC_QUPV3_WRAP0_S0_CLK 58
+#define GCC_QUPV3_WRAP0_S0_CLK_SRC 59
+#define GCC_QUPV3_WRAP0_S1_CLK 60
+#define GCC_QUPV3_WRAP0_S1_CLK_SRC 61
+#define GCC_QUPV3_WRAP0_S2_CLK 62
+#define GCC_QUPV3_WRAP0_S2_CLK_SRC 63
+#define GCC_QUPV3_WRAP0_S3_CLK 64
+#define GCC_QUPV3_WRAP0_S3_CLK_SRC 65
+#define GCC_QUPV3_WRAP0_S4_CLK 66
+#define GCC_QUPV3_WRAP0_S4_CLK_SRC 67
+#define GCC_QUPV3_WRAP0_S5_CLK 68
+#define GCC_QUPV3_WRAP0_S5_CLK_SRC 69
+#define GCC_QUPV3_WRAP1_CORE_2X_CLK 70
+#define GCC_QUPV3_WRAP1_CORE_CLK 71
+#define GCC_QUPV3_WRAP1_S0_CLK 72
+#define GCC_QUPV3_WRAP1_S0_CLK_SRC 73
+#define GCC_QUPV3_WRAP1_S1_CLK 74
+#define GCC_QUPV3_WRAP1_S1_CLK_SRC 75
+#define GCC_QUPV3_WRAP1_S2_CLK 76
+#define GCC_QUPV3_WRAP1_S2_CLK_SRC 77
+#define GCC_QUPV3_WRAP1_S3_CLK 78
+#define GCC_QUPV3_WRAP1_S3_CLK_SRC 79
+#define GCC_QUPV3_WRAP1_S4_CLK 80
+#define GCC_QUPV3_WRAP1_S4_CLK_SRC 81
+#define GCC_QUPV3_WRAP1_S5_CLK 82
+#define GCC_QUPV3_WRAP1_S5_CLK_SRC 83
+#define GCC_QUPV3_WRAP_0_M_AHB_CLK 84
+#define GCC_QUPV3_WRAP_0_S_AHB_CLK 85
+#define GCC_QUPV3_WRAP_1_M_AHB_CLK 86
+#define GCC_QUPV3_WRAP_1_S_AHB_CLK 87
+#define GCC_SDCC1_AHB_CLK 88
+#define GCC_SDCC1_APPS_CLK 89
+#define GCC_SDCC1_APPS_CLK_SRC 90
+#define GCC_SDCC1_ICE_CORE_CLK 91
+#define GCC_SDCC1_ICE_CORE_CLK_SRC 92
+#define GCC_SDCC2_AHB_CLK 93
+#define GCC_SDCC2_APPS_CLK 94
+#define GCC_SDCC2_APPS_CLK_SRC 95
+#define GCC_SYS_NOC_CPUSS_AHB_CLK 96
+#define GCC_UFS_MEM_CLKREF_CLK 97
+#define GCC_UFS_PHY_AHB_CLK 98
+#define GCC_UFS_PHY_AXI_CLK 99
+#define GCC_UFS_PHY_AXI_CLK_SRC 100
+#define GCC_UFS_PHY_ICE_CORE_CLK 101
+#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 102
+#define GCC_UFS_PHY_PHY_AUX_CLK 103
+#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 104
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 105
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 106
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK 107
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 108
+#define GCC_USB30_PRIM_MASTER_CLK 109
+#define GCC_USB30_PRIM_MASTER_CLK_SRC 110
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK 111
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 112
+#define GCC_USB30_PRIM_SLEEP_CLK 113
+#define GCC_USB3_PRIM_CLKREF_CLK 114
+#define GCC_USB3_PRIM_PHY_AUX_CLK 115
+#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 116
+#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 117
+#define GCC_USB3_PRIM_PHY_PIPE_CLK 118
+#define GCC_USB_PHY_CFG_AHB2PHY_CLK 119
+#define GCC_VIDEO_AHB_CLK 120
+#define GCC_VIDEO_AXI_CLK 121
+#define GCC_VIDEO_GPLL0_DIV_CLK_SRC 122
+#define GCC_VIDEO_THROTTLE_AXI_CLK 123
+#define GCC_VIDEO_XO_CLK 124
+
+/* GCC resets */
+#define GCC_QUSB2PHY_PRIM_BCR 0
+#define GCC_QUSB2PHY_SEC_BCR 1
+#define GCC_UFS_PHY_BCR 2
+#define GCC_USB30_PRIM_BCR 3
+#define GCC_USB3_DP_PHY_PRIM_BCR 4
+#define GCC_USB3_DP_PHY_SEC_BCR 5
+#define GCC_USB3_PHY_PRIM_BCR 6
+#define GCC_USB3_PHY_SEC_BCR 7
+#define GCC_USB3PHY_PHY_PRIM_BCR 8
+#define GCC_USB3PHY_PHY_SEC_BCR 9
+#define GCC_USB_PHY_CFG_AHB2PHY_BCR 10
+
+/* GCC GDSCRs */
+#define UFS_PHY_GDSC 0
+#define USB30_PRIM_GDSC 1
+#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 2
+#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 3
+
+#endif
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the Linux Foundation.
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 3/3] clk: qcom: Add Global Clock controller (GCC) driver for SC7180
2019-09-18 9:50 [PATCH v3 0/3] Add Global Clock controller (GCC) driver for SC7180 Taniya Das
2019-09-18 9:50 ` [PATCH v3 1/3] clk: qcom: rcg: update the DFS macro for RCG Taniya Das
2019-09-18 9:50 ` [PATCH v3 2/3] dt-bindings: clk: qcom: Add YAML schemas for the GCC clock bindings Taniya Das
@ 2019-09-18 9:50 ` Taniya Das
2019-09-19 11:08 ` Rajendra Nayak
[not found] ` <20190918213946.DC03521924@mail.kernel.org>
2 siblings, 2 replies; 25+ messages in thread
From: Taniya Das @ 2019-09-18 9:50 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette , robh+dt
Cc: David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, devicetree, Taniya Das
Add support for the global clock controller found on SC7180
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
---
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gcc-sc7180.c | 2515 +++++++++++++++++++++++++++++++++
3 files changed, 2525 insertions(+)
create mode 100644 drivers/clk/qcom/gcc-sc7180.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 32dbb4f09492..91706d88eeeb 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -227,6 +227,15 @@ config QCS_GCC_404
Say Y if you want to use multimedia devices or peripheral
devices such as UART, SPI, I2C, USB, SD/eMMC, PCIe etc.
+config SC_GCC_7180
+ tristate "SC7180 Global Clock Controller"
+ select QCOM_GDSC
+ depends on COMMON_CLK_QCOM
+ help
+ Support for the global clock controller on SC7180 devices.
+ Say Y if you want to use peripheral devices such as UART, SPI,
+ I2C, USB, UFS, SDCC, etc.
+
config SDM_CAMCC_845
tristate "SDM845 Camera Clock Controller"
select SDM_GCC_845
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 4a813b4055d0..6fb356a0bbf5 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -43,6 +43,7 @@ obj-$(CONFIG_QCOM_CLK_RPMH) += clk-rpmh.o
obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
obj-$(CONFIG_QCS_GCC_404) += gcc-qcs404.o
obj-$(CONFIG_QCS_TURING_404) += turingcc-qcs404.o
+obj-$(CONFIG_SC_GCC_7180) += gcc-sc7180.o
obj-$(CONFIG_SDM_CAMCC_845) += camcc-sdm845.o
obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o
obj-$(CONFIG_SDM_GCC_660) += gcc-sdm660.o
diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c
new file mode 100644
index 000000000000..d47865d5408f
--- /dev/null
+++ b/drivers/clk/qcom/gcc-sc7180.c
@@ -0,0 +1,2515 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,gcc-sc7180.h>
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "common.h"
+#include "gdsc.h"
+#include "reset.h"
+
+#define GCC_MMSS_MISC 0x09ffc
+#define GCC_NPU_MISC 0x4d110
+#define GCC_GPU_MISC 0x71028
+
+enum {
+ P_BI_TCXO,
+ P_CORE_BI_PLL_TEST_SE,
+ P_GPLL0_OUT_EVEN,
+ P_GPLL0_OUT_MAIN,
+ P_GPLL1_OUT_MAIN,
+ P_GPLL4_OUT_MAIN,
+ P_GPLL6_OUT_MAIN,
+ P_GPLL7_OUT_MAIN,
+ P_SLEEP_CLK,
+};
+
+static struct clk_alpha_pll gpll0 = {
+ .offset = 0x0,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
+ .clkr = {
+ .enable_reg = 0x52010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll0",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "bi_tcxo",
+ .name = "bi_tcxo",
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_fixed_fabia_ops,
+ },
+ },
+};
+
+static const struct clk_div_table post_div_table_gpll0_out_even[] = {
+ { 0x1, 2 },
+ { }
+};
+
+static struct clk_alpha_pll_postdiv gpll0_out_even = {
+ .offset = 0x0,
+ .post_div_shift = 8,
+ .post_div_table = post_div_table_gpll0_out_even,
+ .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll0_out_even",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gpll0.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_fabia_ops,
+ },
+};
+
+static struct clk_fixed_factor gcc_pll0_main_div_cdiv = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pll0_main_div_cdiv",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gpll0.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+static struct clk_alpha_pll gpll1 = {
+ .offset = 0x01000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
+ .clkr = {
+ .enable_reg = 0x52010,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll1",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "bi_tcxo",
+ .name = "bi_tcxo",
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_fixed_fabia_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll gpll4 = {
+ .offset = 0x76000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
+ .clkr = {
+ .enable_reg = 0x52010,
+ .enable_mask = BIT(4),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll4",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "bi_tcxo",
+ .name = "bi_tcxo",
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_fixed_fabia_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll gpll6 = {
+ .offset = 0x13000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
+ .clkr = {
+ .enable_reg = 0x52010,
+ .enable_mask = BIT(6),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll6",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "bi_tcxo",
+ .name = "bi_tcxo",
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_fixed_fabia_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll gpll7 = {
+ .offset = 0x27000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
+ .clkr = {
+ .enable_reg = 0x52010,
+ .enable_mask = BIT(7),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll7",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "bi_tcxo",
+ .name = "bi_tcxo",
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_fixed_fabia_ops,
+ },
+ },
+};
+
+static const struct parent_map gcc_parent_map_0[] = {
+ { P_BI_TCXO, 0 },
+ { P_GPLL0_OUT_MAIN, 1 },
+ { P_GPLL0_OUT_EVEN, 6 },
+ { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const struct clk_parent_data gcc_parent_data_0[] = {
+ { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll0_out_even.clkr.hw },
+ { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
+};
+
+static const struct clk_parent_data gcc_parent_data_0_ao[] = {
+ { .fw_name = "bi_tcxo_ao", .name = "bi_tcxo_ao" },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll0_out_even.clkr.hw },
+ { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
+};
+
+static const struct parent_map gcc_parent_map_1[] = {
+ { P_BI_TCXO, 0 },
+ { P_GPLL0_OUT_MAIN, 1 },
+ { P_GPLL6_OUT_MAIN, 2 },
+ { P_GPLL0_OUT_EVEN, 6 },
+ { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const struct clk_parent_data gcc_parent_data_1[] = {
+ { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll6.clkr.hw },
+ { .hw = &gpll0_out_even.clkr.hw },
+ { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
+};
+
+static const struct parent_map gcc_parent_map_2[] = {
+ { P_BI_TCXO, 0 },
+ { P_GPLL0_OUT_MAIN, 1 },
+ { P_GPLL1_OUT_MAIN, 4 },
+ { P_GPLL4_OUT_MAIN, 5 },
+ { P_GPLL0_OUT_EVEN, 6 },
+ { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const struct clk_parent_data gcc_parent_data_2[] = {
+ { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll1.clkr.hw },
+ { .hw = &gpll4.clkr.hw },
+ { .hw = &gpll0_out_even.clkr.hw },
+ { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
+};
+
+static const struct parent_map gcc_parent_map_3[] = {
+ { P_BI_TCXO, 0 },
+ { P_GPLL0_OUT_MAIN, 1 },
+ { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const struct clk_parent_data gcc_parent_data_3[] = {
+ { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
+ { .hw = &gpll0.clkr.hw },
+ { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
+};
+
+static const struct parent_map gcc_parent_map_4[] = {
+ { P_BI_TCXO, 0 },
+ { P_GPLL0_OUT_MAIN, 1 },
+ { P_SLEEP_CLK, 5 },
+ { P_GPLL0_OUT_EVEN, 6 },
+ { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const struct clk_parent_data gcc_parent_data_4[] = {
+ { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
+ { .hw = &gpll0.clkr.hw },
+ { .fw_name = "sleep_clk", .name = "sleep_clk" },
+ { .hw = &gpll0_out_even.clkr.hw },
+ { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
+};
+
+static const struct parent_map gcc_parent_map_5[] = {
+ { P_BI_TCXO, 0 },
+ { P_GPLL0_OUT_MAIN, 1 },
+ { P_GPLL7_OUT_MAIN, 3 },
+ { P_GPLL0_OUT_EVEN, 6 },
+ { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const struct clk_parent_data gcc_parent_data_5[] = {
+ { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll7.clkr.hw },
+ { .hw = &gpll0_out_even.clkr.hw },
+ { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
+};
+
+static const struct parent_map gcc_parent_map_6[] = {
+ { P_BI_TCXO, 0 },
+ { P_GPLL0_OUT_MAIN, 1 },
+ { P_SLEEP_CLK, 5 },
+ { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const struct clk_parent_data gcc_parent_data_6[] = {
+ { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
+ { .hw = &gpll0.clkr.hw },
+ { .fw_name = "sleep_clk", .name = "sleep_clk" },
+ { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
+};
+
+static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
+ .cmd_rcgr = 0x48014,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gcc_cpuss_ahb_clk_src",
+ .parent_data = gcc_parent_data_0_ao,
+ .num_parents = 4,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
+ F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
+ F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
+ F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_gp1_clk_src = {
+ .cmd_rcgr = 0x64004,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_4,
+ .freq_tbl = ftbl_gcc_gp1_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gcc_gp1_clk_src",
+ .parent_data = gcc_parent_data_4,
+ .num_parents = 5,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_gp2_clk_src = {
+ .cmd_rcgr = 0x65004,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_4,
+ .freq_tbl = ftbl_gcc_gp1_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gcc_gp2_clk_src",
+ .parent_data = gcc_parent_data_4,
+ .num_parents = 5,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_gp3_clk_src = {
+ .cmd_rcgr = 0x66004,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_4,
+ .freq_tbl = ftbl_gcc_gp1_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gcc_gp3_clk_src",
+ .parent_data = gcc_parent_data_4,
+ .num_parents = 5,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_pdm2_clk_src = {
+ .cmd_rcgr = 0x33010,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_pdm2_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gcc_pdm2_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
+ F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
+ F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
+ F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_qspi_core_clk_src = {
+ .cmd_rcgr = 0x4b00c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_2,
+ .freq_tbl = ftbl_gcc_qspi_core_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gcc_qspi_core_clk_src",
+ .parent_data = gcc_parent_data_2,
+ .num_parents = 6,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
+ F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
+ F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
+ F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
+ F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
+ F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
+ F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
+ F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
+ F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
+ F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
+ F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
+ F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
+ F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
+ F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
+ F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0),
+ { }
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
+ .name = "gcc_qupv3_wrap0_s0_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
+ .cmd_rcgr = 0x17034,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+ .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
+ .name = "gcc_qupv3_wrap0_s1_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
+ .cmd_rcgr = 0x17164,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+ .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
+ .name = "gcc_qupv3_wrap0_s2_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
+ .cmd_rcgr = 0x17294,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+ .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
+ .name = "gcc_qupv3_wrap0_s3_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
+ .cmd_rcgr = 0x173c4,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+ .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
+ .name = "gcc_qupv3_wrap0_s4_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
+ .cmd_rcgr = 0x174f4,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+ .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
+ .name = "gcc_qupv3_wrap0_s5_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
+ .cmd_rcgr = 0x17624,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+ .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
+ .name = "gcc_qupv3_wrap1_s0_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
+ .cmd_rcgr = 0x18018,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+ .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
+ .name = "gcc_qupv3_wrap1_s1_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
+ .cmd_rcgr = 0x18148,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+ .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
+ .name = "gcc_qupv3_wrap1_s2_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
+ .cmd_rcgr = 0x18278,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+ .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
+ .name = "gcc_qupv3_wrap1_s3_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
+ .cmd_rcgr = 0x183a8,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+ .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
+ .name = "gcc_qupv3_wrap1_s4_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
+ .cmd_rcgr = 0x184d8,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+ .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
+ .name = "gcc_qupv3_wrap1_s5_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
+ .cmd_rcgr = 0x18608,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+ .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
+};
+
+
+static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
+ F(144000, P_BI_TCXO, 16, 3, 25),
+ F(400000, P_BI_TCXO, 12, 1, 4),
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3),
+ F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2),
+ F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
+ F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
+ F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
+ F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
+ .cmd_rcgr = 0x12028,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_1,
+ .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc1_apps_clk_src",
+ .parent_data = gcc_parent_data_1,
+ .num_parents = 5,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
+ F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
+ F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
+ F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
+ F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
+ .cmd_rcgr = 0x12010,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc1_ice_core_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
+ F(400000, P_BI_TCXO, 12, 1, 4),
+ F(9600000, P_BI_TCXO, 2, 0, 0),
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
+ F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
+ F(202000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
+ .cmd_rcgr = 0x1400c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_5,
+ .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc2_apps_clk_src",
+ .parent_data = gcc_parent_data_5,
+ .num_parents = 5,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
+ F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
+ F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
+ F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
+ F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
+ F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
+ .cmd_rcgr = 0x77020,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_phy_axi_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
+ F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
+ F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
+ F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
+ F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
+ .cmd_rcgr = 0x77048,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_phy_ice_core_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
+ F(9600000, P_BI_TCXO, 2, 0, 0),
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
+ .cmd_rcgr = 0x77098,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_3,
+ .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_phy_phy_aux_clk_src",
+ .parent_data = gcc_parent_data_3,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
+ F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
+ F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
+ F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
+ .cmd_rcgr = 0x77060,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_phy_unipro_core_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
+ F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
+ F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
+ F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
+ F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
+ .cmd_rcgr = 0xf01c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gcc_usb30_prim_master_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
+ .cmd_rcgr = 0xf034,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gcc_usb30_prim_mock_utmi_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_usb3_prim_phy_aux_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
+ .cmd_rcgr = 0xf060,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_6,
+ .freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gcc_usb3_prim_phy_aux_clk_src",
+ .parent_data = gcc_parent_data_6,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
+ .halt_reg = 0x82024,
+ .halt_check = BRANCH_HALT_DELAY,
+ .hwcg_reg = 0x82024,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x82024,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_aggre_ufs_phy_axi_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
+ .halt_reg = 0x8201c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x8201c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_aggre_usb3_prim_axi_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_boot_rom_ahb_clk = {
+ .halt_reg = 0x38004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x38004,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x52000,
+ .enable_mask = BIT(10),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_boot_rom_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_camera_ahb_clk = {
+ .halt_reg = 0xb008,
+ .halt_check = BRANCH_HALT,
+ .hwcg_reg = 0xb008,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0xb008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_camera_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_camera_hf_axi_clk = {
+ .halt_reg = 0xb020,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xb020,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_camera_hf_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_camera_throttle_hf_axi_clk = {
+ .halt_reg = 0xb080,
+ .halt_check = BRANCH_HALT,
+ .hwcg_reg = 0xb080,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0xb080,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_camera_throttle_hf_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_camera_xo_clk = {
+ .halt_reg = 0xb02c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xb02c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_camera_xo_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ce1_ahb_clk = {
+ .halt_reg = 0x4100c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x4100c,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x52000,
+ .enable_mask = BIT(3),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ce1_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ce1_axi_clk = {
+ .halt_reg = 0x41008,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52000,
+ .enable_mask = BIT(4),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ce1_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ce1_clk = {
+ .halt_reg = 0x41004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52000,
+ .enable_mask = BIT(5),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ce1_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
+ .halt_reg = 0x502c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x502c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_cfg_noc_usb3_prim_axi_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+/* For CPUSS functionality the AHB clock needs to be left enabled */
+static struct clk_branch gcc_cpuss_ahb_clk = {
+ .halt_reg = 0x48000,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52000,
+ .enable_mask = BIT(21),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_cpuss_ahb_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gcc_cpuss_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+/* For CPUSS functionality the GNOC clock needs to be left enabled */
+static struct clk_branch gcc_cpuss_gnoc_clk = {
+ .halt_reg = 0x48004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x48004,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x52000,
+ .enable_mask = BIT(22),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_cpuss_gnoc_clk",
+ .flags = CLK_IS_CRITICAL,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_cpuss_rbcpr_clk = {
+ .halt_reg = 0x48008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x48008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_cpuss_rbcpr_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ddrss_gpu_axi_clk = {
+ .halt_reg = 0x4452c,
+ .halt_check = BRANCH_VOTED,
+ .clkr = {
+ .enable_reg = 0x4452c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ddrss_gpu_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+/* Leave the clock ON for parent config_noc_clk to be kept enabled */
+static struct clk_branch gcc_disp_ahb_clk = {
+ .halt_reg = 0xb00c,
+ .halt_check = BRANCH_HALT,
+ .hwcg_reg = 0xb00c,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0xb00c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_disp_ahb_clk",
+ .flags = CLK_IS_CRITICAL,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_disp_gpll0_clk_src = {
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x52000,
+ .enable_mask = BIT(18),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_disp_gpll0_clk_src",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gpll0.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_disp_gpll0_div_clk_src = {
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x52000,
+ .enable_mask = BIT(19),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_disp_gpll0_div_clk_src",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gcc_pll0_main_div_cdiv.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_disp_hf_axi_clk = {
+ .halt_reg = 0xb024,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xb024,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_disp_hf_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_disp_throttle_hf_axi_clk = {
+ .halt_reg = 0xb084,
+ .halt_check = BRANCH_HALT,
+ .hwcg_reg = 0xb084,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0xb084,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_disp_throttle_hf_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_disp_xo_clk = {
+ .halt_reg = 0xb030,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xb030,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_disp_xo_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp1_clk = {
+ .halt_reg = 0x64000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x64000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gp1_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gcc_gp1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp2_clk = {
+ .halt_reg = 0x65000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x65000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gp2_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gcc_gp2_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp3_clk = {
+ .halt_reg = 0x66000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x66000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gp3_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gcc_gp3_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+/* Leave the clock ON for parent config_noc_clk to be kept enabled */
+static struct clk_branch gcc_gpu_cfg_ahb_clk = {
+ .halt_reg = 0x71004,
+ .halt_check = BRANCH_HALT,
+ .hwcg_reg = 0x71004,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x71004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gpu_cfg_ahb_clk",
+ .flags = CLK_IS_CRITICAL,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gpu_gpll0_clk_src = {
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x52000,
+ .enable_mask = BIT(15),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gpu_gpll0_clk_src",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gpll0.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x52000,
+ .enable_mask = BIT(16),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gpu_gpll0_div_clk_src",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gcc_pll0_main_div_cdiv.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
+ .halt_reg = 0x7100c,
+ .halt_check = BRANCH_VOTED,
+ .clkr = {
+ .enable_reg = 0x7100c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gpu_memnoc_gfx_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
+ .halt_reg = 0x71018,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x71018,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gpu_snoc_dvm_gfx_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_npu_axi_clk = {
+ .halt_reg = 0x4d008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4d008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_npu_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_npu_bwmon_axi_clk = {
+ .halt_reg = 0x73008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x73008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_npu_bwmon_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_npu_bwmon_dma_cfg_ahb_clk = {
+ .halt_reg = 0x73018,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x73018,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_npu_bwmon_dma_cfg_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_npu_bwmon_dsp_cfg_ahb_clk = {
+ .halt_reg = 0x7301c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x7301c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_npu_bwmon_dsp_cfg_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_npu_cfg_ahb_clk = {
+ .halt_reg = 0x4d004,
+ .halt_check = BRANCH_HALT,
+ .hwcg_reg = 0x4d004,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x4d004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_npu_cfg_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_npu_dma_clk = {
+ .halt_reg = 0x4d1a0,
+ .halt_check = BRANCH_HALT,
+ .hwcg_reg = 0x4d1a0,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x4d1a0,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_npu_dma_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_npu_gpll0_clk_src = {
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x52000,
+ .enable_mask = BIT(25),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_npu_gpll0_clk_src",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gpll0.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_npu_gpll0_div_clk_src = {
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x52000,
+ .enable_mask = BIT(26),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_npu_gpll0_div_clk_src",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gcc_pll0_main_div_cdiv.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pdm2_clk = {
+ .halt_reg = 0x3300c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x3300c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pdm2_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gcc_pdm2_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pdm_ahb_clk = {
+ .halt_reg = 0x33004,
+ .halt_check = BRANCH_HALT,
+ .hwcg_reg = 0x33004,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x33004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pdm_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pdm_xo4_clk = {
+ .halt_reg = 0x33008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x33008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pdm_xo4_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_prng_ahb_clk = {
+ .halt_reg = 0x34004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x34004,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x52000,
+ .enable_mask = BIT(13),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_prng_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
+ .halt_reg = 0x4b004,
+ .halt_check = BRANCH_HALT,
+ .hwcg_reg = 0x4b004,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x4b004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qspi_cnoc_periph_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qspi_core_clk = {
+ .halt_reg = 0x4b008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4b008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qspi_core_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gcc_qspi_core_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
+ .halt_reg = 0x17014,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52008,
+ .enable_mask = BIT(9),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qupv3_wrap0_core_2x_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_core_clk = {
+ .halt_reg = 0x1700c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52008,
+ .enable_mask = BIT(8),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qupv3_wrap0_core_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
+ .halt_reg = 0x17030,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52008,
+ .enable_mask = BIT(10),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qupv3_wrap0_s0_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
+ .halt_reg = 0x17160,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52008,
+ .enable_mask = BIT(11),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qupv3_wrap0_s1_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
+ .halt_reg = 0x17290,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52008,
+ .enable_mask = BIT(12),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qupv3_wrap0_s2_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
+ .halt_reg = 0x173c0,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52008,
+ .enable_mask = BIT(13),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qupv3_wrap0_s3_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
+ .halt_reg = 0x174f0,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52008,
+ .enable_mask = BIT(14),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qupv3_wrap0_s4_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
+ .halt_reg = 0x17620,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52008,
+ .enable_mask = BIT(15),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qupv3_wrap0_s5_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
+ .halt_reg = 0x18004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52008,
+ .enable_mask = BIT(18),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qupv3_wrap1_core_2x_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap1_core_clk = {
+ .halt_reg = 0x18008,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52008,
+ .enable_mask = BIT(19),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qupv3_wrap1_core_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
+ .halt_reg = 0x18014,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52008,
+ .enable_mask = BIT(22),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qupv3_wrap1_s0_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
+ .halt_reg = 0x18144,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52008,
+ .enable_mask = BIT(23),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qupv3_wrap1_s1_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
+ .halt_reg = 0x18274,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52008,
+ .enable_mask = BIT(24),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qupv3_wrap1_s2_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
+ .halt_reg = 0x183a4,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52008,
+ .enable_mask = BIT(25),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qupv3_wrap1_s3_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
+ .halt_reg = 0x184d4,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52008,
+ .enable_mask = BIT(26),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qupv3_wrap1_s4_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
+ .halt_reg = 0x18604,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52008,
+ .enable_mask = BIT(27),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qupv3_wrap1_s5_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
+ .halt_reg = 0x17004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52008,
+ .enable_mask = BIT(6),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qupv3_wrap_0_m_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
+ .halt_reg = 0x17008,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x17008,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x52008,
+ .enable_mask = BIT(7),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qupv3_wrap_0_s_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
+ .halt_reg = 0x1800c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52008,
+ .enable_mask = BIT(20),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qupv3_wrap_1_m_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
+ .halt_reg = 0x18010,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x18010,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x52008,
+ .enable_mask = BIT(21),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qupv3_wrap_1_s_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc1_ahb_clk = {
+ .halt_reg = 0x12008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x12008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc1_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc1_apps_clk = {
+ .halt_reg = 0x1200c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1200c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc1_apps_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gcc_sdcc1_apps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc1_ice_core_clk = {
+ .halt_reg = 0x12040,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x12040,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc1_ice_core_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gcc_sdcc1_ice_core_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc2_ahb_clk = {
+ .halt_reg = 0x14008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x14008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc2_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc2_apps_clk = {
+ .halt_reg = 0x14004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x14004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc2_apps_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gcc_sdcc2_apps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+/* For CPUSS functionality the SYS NOC clock needs to be left enabled */
+static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
+ .halt_reg = 0x4144,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sys_noc_cpuss_ahb_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gcc_cpuss_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_mem_clkref_clk = {
+ .halt_reg = 0x8c000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x8c000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_mem_clkref_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_phy_ahb_clk = {
+ .halt_reg = 0x77014,
+ .halt_check = BRANCH_HALT,
+ .hwcg_reg = 0x77014,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x77014,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_phy_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_phy_axi_clk = {
+ .halt_reg = 0x77038,
+ .halt_check = BRANCH_HALT,
+ .hwcg_reg = 0x77038,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x77038,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_phy_axi_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_phy_ice_core_clk = {
+ .halt_reg = 0x77090,
+ .halt_check = BRANCH_HALT,
+ .hwcg_reg = 0x77090,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x77090,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_phy_ice_core_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
+ .halt_reg = 0x77094,
+ .halt_check = BRANCH_HALT,
+ .hwcg_reg = 0x77094,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x77094,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_phy_phy_aux_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
+ .halt_reg = 0x7701c,
+ .halt_check = BRANCH_HALT_SKIP,
+ .clkr = {
+ .enable_reg = 0x7701c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_phy_rx_symbol_0_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
+ .halt_reg = 0x77018,
+ .halt_check = BRANCH_HALT_SKIP,
+ .clkr = {
+ .enable_reg = 0x77018,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_phy_tx_symbol_0_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
+ .halt_reg = 0x7708c,
+ .halt_check = BRANCH_HALT,
+ .hwcg_reg = 0x7708c,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x7708c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_phy_unipro_core_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb30_prim_master_clk = {
+ .halt_reg = 0xf010,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xf010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb30_prim_master_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
+ .halt_reg = 0xf018,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xf018,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb30_prim_mock_utmi_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw =
+ &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb30_prim_sleep_clk = {
+ .halt_reg = 0xf014,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xf014,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb30_prim_sleep_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb3_prim_clkref_clk = {
+ .halt_reg = 0x8c010,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x8c010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb3_prim_clkref_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
+ .halt_reg = 0xf050,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xf050,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb3_prim_phy_aux_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
+ .halt_reg = 0xf054,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xf054,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb3_prim_phy_com_aux_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
+ .halt_reg = 0xf058,
+ .halt_check = BRANCH_HALT_SKIP,
+ .clkr = {
+ .enable_reg = 0xf058,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb3_prim_phy_pipe_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
+ .halt_reg = 0x6a004,
+ .halt_check = BRANCH_HALT,
+ .hwcg_reg = 0x6a004,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x6a004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb_phy_cfg_ahb2phy_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+/* Leave the clock ON for parent config_noc_clk to be kept enabled */
+static struct clk_branch gcc_video_ahb_clk = {
+ .halt_reg = 0xb004,
+ .halt_check = BRANCH_HALT,
+ .hwcg_reg = 0xb004,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0xb004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_video_ahb_clk",
+ .flags = CLK_IS_CRITICAL,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_video_axi_clk = {
+ .halt_reg = 0xb01c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xb01c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_video_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_video_gpll0_div_clk_src = {
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x52000,
+ .enable_mask = BIT(20),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_video_gpll0_div_clk_src",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = &gcc_pll0_main_div_cdiv.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_video_throttle_axi_clk = {
+ .halt_reg = 0xb07c,
+ .halt_check = BRANCH_HALT,
+ .hwcg_reg = 0xb07c,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0xb07c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_video_throttle_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_video_xo_clk = {
+ .halt_reg = 0xb028,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xb028,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_video_xo_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct gdsc ufs_phy_gdsc = {
+ .gdscr = 0x77004,
+ .pd = {
+ .name = "ufs_phy_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc usb30_prim_gdsc = {
+ .gdscr = 0x0f004,
+ .pd = {
+ .name = "usb30_prim_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
+ .gdscr = 0x7d040,
+ .pd = {
+ .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON | VOTABLE,
+};
+
+static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = {
+ .gdscr = 0x7d044,
+ .pd = {
+ .name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON | VOTABLE,
+};
+
+static struct gdsc *gcc_sc7180_gdscs[] = {
+ [UFS_PHY_GDSC] = &ufs_phy_gdsc,
+ [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
+ [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] =
+ &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
+ [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] =
+ &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc,
+};
+
+
+static struct clk_hw *gcc_sc7180_hws[] = {
+ [GCC_GPLL0_MAIN_DIV_CDIV] = &gcc_pll0_main_div_cdiv.hw,
+};
+
+static struct clk_regmap *gcc_sc7180_clocks[] = {
+ [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
+ [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
+ [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
+ [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
+ [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
+ [GCC_CAMERA_THROTTLE_HF_AXI_CLK] = &gcc_camera_throttle_hf_axi_clk.clkr,
+ [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
+ [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
+ [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
+ [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
+ [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
+ [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
+ [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
+ [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
+ [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
+ [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
+ [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
+ [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
+ [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
+ [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
+ [GCC_DISP_THROTTLE_HF_AXI_CLK] = &gcc_disp_throttle_hf_axi_clk.clkr,
+ [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
+ [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
+ [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
+ [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
+ [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
+ [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
+ [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
+ [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
+ [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
+ [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
+ [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
+ [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
+ [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,
+ [GCC_NPU_BWMON_AXI_CLK] = &gcc_npu_bwmon_axi_clk.clkr,
+ [GCC_NPU_BWMON_DMA_CFG_AHB_CLK] = &gcc_npu_bwmon_dma_cfg_ahb_clk.clkr,
+ [GCC_NPU_BWMON_DSP_CFG_AHB_CLK] = &gcc_npu_bwmon_dsp_cfg_ahb_clk.clkr,
+ [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr,
+ [GCC_NPU_DMA_CLK] = &gcc_npu_dma_clk.clkr,
+ [GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr,
+ [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr,
+ [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
+ [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
+ [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
+ [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
+ [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
+ [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
+ [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
+ [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
+ [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
+ [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
+ [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
+ [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
+ [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
+ [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
+ [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
+ [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
+ [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
+ [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
+ [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
+ [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
+ [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
+ [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
+ [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
+ [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
+ [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
+ [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
+ [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
+ [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
+ [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
+ [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
+ [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
+ [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
+ [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
+ [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
+ [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
+ [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
+ [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
+ [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
+ [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
+ [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
+ [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
+ [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
+ [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
+ [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
+ [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
+ [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
+ [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
+ [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
+ [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
+ [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
+ [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
+ [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
+ [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
+ [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
+ [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
+ [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
+ [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
+ [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
+ [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
+ [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
+ [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
+ &gcc_ufs_phy_unipro_core_clk_src.clkr,
+ [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
+ [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
+ [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
+ [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
+ &gcc_usb30_prim_mock_utmi_clk_src.clkr,
+ [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
+ [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
+ [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
+ [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
+ [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
+ [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
+ [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
+ [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
+ [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr,
+ [GCC_VIDEO_GPLL0_DIV_CLK_SRC] = &gcc_video_gpll0_div_clk_src.clkr,
+ [GCC_VIDEO_THROTTLE_AXI_CLK] = &gcc_video_throttle_axi_clk.clkr,
+ [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
+ [GPLL0] = &gpll0.clkr,
+ [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
+ [GPLL6] = &gpll6.clkr,
+ [GPLL7] = &gpll7.clkr,
+ [GPLL4] = &gpll4.clkr,
+ [GPLL1] = &gpll1.clkr,
+};
+
+static const struct qcom_reset_map gcc_sc7180_resets[] = {
+ [GCC_QUSB2PHY_PRIM_BCR] = { 0x26000 },
+ [GCC_QUSB2PHY_SEC_BCR] = { 0x26004 },
+ [GCC_UFS_PHY_BCR] = { 0x77000 },
+ [GCC_USB30_PRIM_BCR] = { 0xf000 },
+ [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
+ [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
+ [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
+ [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
+ [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
+ [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
+ [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
+};
+
+static struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
+ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
+};
+
+static const struct regmap_config gcc_sc7180_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x18208c,
+ .fast_io = true,
+};
+
+static const struct qcom_cc_desc gcc_sc7180_desc = {
+ .config = &gcc_sc7180_regmap_config,
+ .clk_hws = gcc_sc7180_hws,
+ .num_clk_hws = ARRAY_SIZE(gcc_sc7180_hws),
+ .clks = gcc_sc7180_clocks,
+ .num_clks = ARRAY_SIZE(gcc_sc7180_clocks),
+ .resets = gcc_sc7180_resets,
+ .num_resets = ARRAY_SIZE(gcc_sc7180_resets),
+ .gdscs = gcc_sc7180_gdscs,
+ .num_gdscs = ARRAY_SIZE(gcc_sc7180_gdscs),
+};
+
+static const struct of_device_id gcc_sc7180_match_table[] = {
+ { .compatible = "qcom,gcc-sc7180" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, gcc_sc7180_match_table);
+
+static int gcc_sc7180_probe(struct platform_device *pdev)
+{
+ struct regmap *regmap;
+ int ret;
+
+ regmap = qcom_cc_map(pdev, &gcc_sc7180_desc);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ /*
+ * Disable the GPLL0 active input to MM blocks, NPU
+ * and GPU via MISC registers.
+ */
+ regmap_update_bits(regmap, GCC_MMSS_MISC, 0x3, 0x3);
+ regmap_update_bits(regmap, GCC_NPU_MISC, 0x3, 0x3);
+ regmap_update_bits(regmap, GCC_GPU_MISC, 0x3, 0x3);
+
+ ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
+ ARRAY_SIZE(gcc_dfs_clocks));
+ if (ret)
+ return ret;
+
+ return qcom_cc_really_probe(pdev, &gcc_sc7180_desc, regmap);
+}
+
+static struct platform_driver gcc_sc7180_driver = {
+ .probe = gcc_sc7180_probe,
+ .driver = {
+ .name = "gcc-sc7180",
+ .of_match_table = gcc_sc7180_match_table,
+ },
+};
+
+static int __init gcc_sc7180_init(void)
+{
+ return platform_driver_register(&gcc_sc7180_driver);
+}
+subsys_initcall(gcc_sc7180_init);
+
+static void __exit gcc_sc7180_exit(void)
+{
+ platform_driver_unregister(&gcc_sc7180_driver);
+}
+module_exit(gcc_sc7180_exit);
+
+MODULE_DESCRIPTION("QTI GCC SC7180 Driver");
+MODULE_LICENSE("GPL v2");
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the Linux Foundation.
^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: clk: qcom: Add YAML schemas for the GCC clock bindings
2019-09-18 9:50 ` [PATCH v3 2/3] dt-bindings: clk: qcom: Add YAML schemas for the GCC clock bindings Taniya Das
@ 2019-09-18 17:52 ` Matthias Kaehlcke
2019-09-23 6:33 ` Taniya Das
2019-09-27 17:27 ` Rob Herring
[not found] ` <20190918212614.448FC20882@mail.kernel.org>
2 siblings, 1 reply; 25+ messages in thread
From: Matthias Kaehlcke @ 2019-09-18 17:52 UTC (permalink / raw)
To: Taniya Das
Cc: Stephen Boyd, Michael Turquette ,
robh+dt, David Brown, Rajendra Nayak, linux-arm-msm, linux-soc,
linux-clk, linux-kernel, devicetree
Hi Taniya,
not a full review, just a couple of things I noticed, comments inline.
On Wed, Sep 18, 2019 at 03:20:17PM +0530, Taniya Das wrote:
> The GCC clock provider have a bunch of generic properties that
> are needed in a device tree. Add a YAML schemas for those. Also update
> the compatible for SC7180 along with example for clocks & clock-names.
I would suggest to split this in two:
1. conversion to YAML
2. add SC7180 header and example
> Signed-off-by: Taniya Das <tdas@codeaurora.org>
> ---
> .../devicetree/bindings/clock/qcom,gcc.txt | 94 -----------
> .../devicetree/bindings/clock/qcom,gcc.yaml | 157 ++++++++++++++++++
> include/dt-bindings/clock/qcom,gcc-sc7180.h | 155 +++++++++++++++++
> 3 files changed, 312 insertions(+), 94 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc.txt
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc.yaml
> create mode 100644 include/dt-bindings/clock/qcom,gcc-sc7180.h
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
> deleted file mode 100644
> index d14362ad4132..000000000000
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
> +++ /dev/null
> @@ -1,94 +0,0 @@
> -Qualcomm Global Clock & Reset Controller Binding
> -------------------------------------------------
> -
> -Required properties :
> -- compatible : shall contain only one of the following:
> -
> - "qcom,gcc-apq8064"
> - "qcom,gcc-apq8084"
> - "qcom,gcc-ipq8064"
> - "qcom,gcc-ipq4019"
> - "qcom,gcc-ipq8074"
> - "qcom,gcc-msm8660"
> - "qcom,gcc-msm8916"
> - "qcom,gcc-msm8960"
> - "qcom,gcc-msm8974"
> - "qcom,gcc-msm8974pro"
> - "qcom,gcc-msm8974pro-ac"
> - "qcom,gcc-msm8994"
> - "qcom,gcc-msm8996"
> - "qcom,gcc-msm8998"
> - "qcom,gcc-mdm9615"
> - "qcom,gcc-qcs404"
> - "qcom,gcc-sdm630"
> - "qcom,gcc-sdm660"
> - "qcom,gcc-sdm845"
> - "qcom,gcc-sm8150"
> -
> -- reg : shall contain base register location and length
> -- #clock-cells : shall contain 1
> -- #reset-cells : shall contain 1
> -
> -Optional properties :
> -- #power-domain-cells : shall contain 1
> -- Qualcomm TSENS (thermal sensor device) on some devices can
> -be part of GCC and hence the TSENS properties can also be
> -part of the GCC/clock-controller node.
> -For more details on the TSENS properties please refer
> -Documentation/devicetree/bindings/thermal/qcom-tsens.txt
> -- protected-clocks : Protected clock specifier list as per common clock
> - binding.
> -
> -For SM8150 only:
> - - clocks: a list of phandles and clock-specifier pairs,
> - one for each entry in clock-names.
> - - clock-names: "bi_tcxo" (required)
> - "sleep_clk" (optional)
> - "aud_ref_clock" (optional)
> -
> -Example:
> - clock-controller@900000 {
> - compatible = "qcom,gcc-msm8960";
> - reg = <0x900000 0x4000>;
> - #clock-cells = <1>;
> - #reset-cells = <1>;
> - #power-domain-cells = <1>;
> - };
> -
> -Example of GCC with TSENS properties:
> - clock-controller@900000 {
> - compatible = "qcom,gcc-apq8064";
> - reg = <0x00900000 0x4000>;
> - nvmem-cells = <&tsens_calib>, <&tsens_backup>;
> - nvmem-cell-names = "calib", "calib_backup";
> - #clock-cells = <1>;
> - #reset-cells = <1>;
> - #thermal-sensor-cells = <1>;
> - };
> -
> -Example of GCC with protected-clocks properties:
> - clock-controller@100000 {
> - compatible = "qcom,gcc-sdm845";
> - reg = <0x100000 0x1f0000>;
> - #clock-cells = <1>;
> - #reset-cells = <1>;
> - #power-domain-cells = <1>;
> - protected-clocks = <GCC_QSPI_CORE_CLK>,
> - <GCC_QSPI_CORE_CLK_SRC>,
> - <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
> - <GCC_LPASS_Q6_AXI_CLK>,
> - <GCC_LPASS_SWAY_CLK>;
> - };
> -
> -Example of GCC with clocks
> - gcc: clock-controller@100000 {
> - compatible = "qcom,gcc-sm8150";
> - reg = <0x00100000 0x1f0000>;
> - #clock-cells = <1>;
> - #reset-cells = <1>;
> - #power-domain-cells = <1>;
> - clock-names = "bi_tcxo",
> - "sleep_clk";
> - clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
> - <&sleep_clk>;
> - };
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
> new file mode 100644
> index 000000000000..056a7977c458
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
> @@ -0,0 +1,157 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,gcc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Global Clock & Reset Controller Binding
> +
> +maintainers:
> + - Stephen Boyd <sboyd@kernel.org>
> +
> +properties:
> + "#clock-cells":
> + const: 1
> +
> + "#reset-cells":
> + const: 1
> +
> + reg:
> + maxItems: 1
> +
> + compatible :
> + enum:
> + - qcom,gcc-apq8064
> + - qcom,gcc-apq8084
> + - qcom,gcc-ipq8064
> + - qcom,gcc-ipq4019
> + - qcom,gcc-ipq8074
> + - qcom,gcc-msm8660
> + - qcom,gcc-msm8916
> + - qcom,gcc-msm8960
> + - qcom,gcc-msm8974
> + - qcom,gcc-msm8974pro
> + - qcom,gcc-msm8974pro-ac
> + - qcom,gcc-msm8994
> + - qcom,gcc-msm8996
> + - qcom,gcc-msm8998
> + - qcom,gcc-mdm9615
> + - qcom,gcc-qcs404
> + - qcom,gcc-sdm630
> + - qcom,gcc-sdm660
> + - qcom,gcc-sdm845
> + - qcom,gcc-sm8150
> + - qcom,gcc-sc7180
> +
> + clocks:
> + minItems: 1
> + maxItems: 3
> + items:
> + - description: Board XO source
> + - description: Board active XO source
> + - description: Sleep clock source(optional)
> +
> + clock-names:
> + minItems: 1
> + maxItems: 3
> + items:
> + - const: bi_tcxo
> + - const: bi_tcxo_ao
> + - const: sleep_clk
> +
> + nvmem-cells:
> + minItems: 1
> + maxItems: 2
> + description:
> + Qualcomm TSENS (thermal sensor device) on some devices can
> + be part of GCC and hence the TSENS properties can also be part
> + of the GCC/clock-controller node.
> + For more details on the TSENS properties please refer
> + Documentation/devicetree/bindings/thermal/qcom-tsens.txt
> +
> + nvmem-cell-names:
> + minItems: 1
> + maxItems: 2
> + description:
> + Names for each nvmem-cells specified.
> + items:
> + - const: calib
> + - const: calib_backup
> +
> + "#thermal-sensor-cells":
> + const: 1
> +
> + "#power-domain-cells":
> + const: 1
> +
> + protected-clocks:
> + description:
> + Protected clock specifier list as per common clock binding
> +
> +required:
> + - "#clock-cells"
> + - "#reset-cells"
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> +
> +examples:
> + - |
> + // Example:
> + clock-controller@900000 {
> + compatible = "qcom,gcc-msm8960";
> + reg = <0x900000 0x4000>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> +
> +
> + - |
> + // Example of GCC with TSENS properties:
> + clock-controller@900000 {
> + compatible = "qcom,gcc-apq8064";
> + reg = <0x00900000 0x4000>;
> + nvmem-cells = <&tsens_calib>, <&tsens_backup>;
> + nvmem-cell-names = "calib", "calib_backup";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #thermal-sensor-cells = <1>;
> + };
> +
> + - |
> + //Example of GCC with protected-clocks properties:
> + clock-controller@100000 {
> + compatible = "qcom,gcc-sdm845";
> + reg = <0x100000 0x1f0000>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + protected-clocks = <187>, <188>, <189>, <190>, <191>;
> + };
> +
> + - |
> + //Example of GCC with clock node properties for SM8150:
> + clock-controller@100000 {
> + compatible = "qcom,gcc-sm8150";
> + reg = <0x00100000 0x1f0000>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + clocks = <&rpmhcc 0>, <&rpmhcc 1>, <&sleep_clk>;
> + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
> + };
> +
> + - |
> + //Example of GCC with clock nodes properties:
add "for SC7180"
> + clock-controller@100000 {
> + compatible = "qcom,gcc-sc7180";
> + reg = <0x100000 0x1f0000>;
> + clocks = <&rpmhcc 0>, <&rpmhcc 1>;
IIUC the ids correspond to GCC_GPLL0_MAIN_DIV_CDIV and GPLL0. If
that is correct I guess the intention is to use the constants in the
DT?
> + clock-names = "bi_tcxo", "bi_tcxo_ao";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> +...
> diff --git a/include/dt-bindings/clock/qcom,gcc-sc7180.h b/include/dt-bindings/clock/qcom,gcc-sc7180.h
> new file mode 100644
> index 000000000000..d76b061f6a4e
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,gcc-sc7180.h
> @@ -0,0 +1,155 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SC7180_H
> +#define _DT_BINDINGS_CLK_QCOM_GCC_SC7180_H
> +
> +/* GCC clocks */
> +#define GCC_GPLL0_MAIN_DIV_CDIV 0
> +#define GPLL0 1
> +#define GPLL0_OUT_EVEN 2
> +#define GPLL1 3
> +#define GPLL4 4
> +#define GPLL6 5
> +#define GPLL7 6
> +#define GCC_AGGRE_UFS_PHY_AXI_CLK 7
> +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 8
> +#define GCC_BOOT_ROM_AHB_CLK 9
> +#define GCC_CAMERA_AHB_CLK 10
> +#define GCC_CAMERA_HF_AXI_CLK 11
> +#define GCC_CAMERA_THROTTLE_HF_AXI_CLK 12
> +#define GCC_CAMERA_XO_CLK 13
> +#define GCC_CE1_AHB_CLK 14
> +#define GCC_CE1_AXI_CLK 15
> +#define GCC_CE1_CLK 16
> +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 17
> +#define GCC_CPUSS_AHB_CLK 18
> +#define GCC_CPUSS_AHB_CLK_SRC 19
> +#define GCC_CPUSS_GNOC_CLK 20
> +#define GCC_CPUSS_RBCPR_CLK 21
> +#define GCC_DDRSS_GPU_AXI_CLK 22
> +#define GCC_DISP_AHB_CLK 23
> +#define GCC_DISP_GPLL0_CLK_SRC 24
> +#define GCC_DISP_GPLL0_DIV_CLK_SRC 25
> +#define GCC_DISP_HF_AXI_CLK 26
> +#define GCC_DISP_THROTTLE_HF_AXI_CLK 27
> +#define GCC_DISP_XO_CLK 28
> +#define GCC_GP1_CLK 29
> +#define GCC_GP1_CLK_SRC 30
> +#define GCC_GP2_CLK 31
> +#define GCC_GP2_CLK_SRC 32
> +#define GCC_GP3_CLK 33
> +#define GCC_GP3_CLK_SRC 34
> +#define GCC_GPU_CFG_AHB_CLK 35
> +#define GCC_GPU_GPLL0_CLK_SRC 36
> +#define GCC_GPU_GPLL0_DIV_CLK_SRC 37
> +#define GCC_GPU_MEMNOC_GFX_CLK 38
> +#define GCC_GPU_SNOC_DVM_GFX_CLK 39
> +#define GCC_NPU_AXI_CLK 40
> +#define GCC_NPU_BWMON_AXI_CLK 41
> +#define GCC_NPU_BWMON_DMA_CFG_AHB_CLK 42
> +#define GCC_NPU_BWMON_DSP_CFG_AHB_CLK 43
> +#define GCC_NPU_CFG_AHB_CLK 44
> +#define GCC_NPU_DMA_CLK 45
> +#define GCC_NPU_GPLL0_CLK_SRC 46
> +#define GCC_NPU_GPLL0_DIV_CLK_SRC 47
> +#define GCC_PDM2_CLK 48
> +#define GCC_PDM2_CLK_SRC 49
> +#define GCC_PDM_AHB_CLK 50
> +#define GCC_PDM_XO4_CLK 51
> +#define GCC_PRNG_AHB_CLK 52
> +#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 53
> +#define GCC_QSPI_CORE_CLK 54
> +#define GCC_QSPI_CORE_CLK_SRC 55
> +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 56
> +#define GCC_QUPV3_WRAP0_CORE_CLK 57
> +#define GCC_QUPV3_WRAP0_S0_CLK 58
> +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 59
> +#define GCC_QUPV3_WRAP0_S1_CLK 60
> +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 61
> +#define GCC_QUPV3_WRAP0_S2_CLK 62
> +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 63
> +#define GCC_QUPV3_WRAP0_S3_CLK 64
> +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 65
> +#define GCC_QUPV3_WRAP0_S4_CLK 66
> +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 67
> +#define GCC_QUPV3_WRAP0_S5_CLK 68
> +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 69
> +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 70
> +#define GCC_QUPV3_WRAP1_CORE_CLK 71
> +#define GCC_QUPV3_WRAP1_S0_CLK 72
> +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 73
> +#define GCC_QUPV3_WRAP1_S1_CLK 74
> +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 75
> +#define GCC_QUPV3_WRAP1_S2_CLK 76
> +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 77
> +#define GCC_QUPV3_WRAP1_S3_CLK 78
> +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 79
> +#define GCC_QUPV3_WRAP1_S4_CLK 80
> +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 81
> +#define GCC_QUPV3_WRAP1_S5_CLK 82
> +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 83
> +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 84
> +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 85
> +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 86
> +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 87
> +#define GCC_SDCC1_AHB_CLK 88
> +#define GCC_SDCC1_APPS_CLK 89
> +#define GCC_SDCC1_APPS_CLK_SRC 90
> +#define GCC_SDCC1_ICE_CORE_CLK 91
> +#define GCC_SDCC1_ICE_CORE_CLK_SRC 92
> +#define GCC_SDCC2_AHB_CLK 93
> +#define GCC_SDCC2_APPS_CLK 94
> +#define GCC_SDCC2_APPS_CLK_SRC 95
> +#define GCC_SYS_NOC_CPUSS_AHB_CLK 96
> +#define GCC_UFS_MEM_CLKREF_CLK 97
> +#define GCC_UFS_PHY_AHB_CLK 98
> +#define GCC_UFS_PHY_AXI_CLK 99
> +#define GCC_UFS_PHY_AXI_CLK_SRC 100
> +#define GCC_UFS_PHY_ICE_CORE_CLK 101
> +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 102
> +#define GCC_UFS_PHY_PHY_AUX_CLK 103
> +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 104
> +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 105
> +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 106
> +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 107
> +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 108
> +#define GCC_USB30_PRIM_MASTER_CLK 109
> +#define GCC_USB30_PRIM_MASTER_CLK_SRC 110
> +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 111
> +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 112
> +#define GCC_USB30_PRIM_SLEEP_CLK 113
> +#define GCC_USB3_PRIM_CLKREF_CLK 114
> +#define GCC_USB3_PRIM_PHY_AUX_CLK 115
> +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 116
> +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 117
> +#define GCC_USB3_PRIM_PHY_PIPE_CLK 118
> +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 119
> +#define GCC_VIDEO_AHB_CLK 120
> +#define GCC_VIDEO_AXI_CLK 121
> +#define GCC_VIDEO_GPLL0_DIV_CLK_SRC 122
> +#define GCC_VIDEO_THROTTLE_AXI_CLK 123
> +#define GCC_VIDEO_XO_CLK 124
> +
> +/* GCC resets */
> +#define GCC_QUSB2PHY_PRIM_BCR 0
> +#define GCC_QUSB2PHY_SEC_BCR 1
> +#define GCC_UFS_PHY_BCR 2
> +#define GCC_USB30_PRIM_BCR 3
> +#define GCC_USB3_DP_PHY_PRIM_BCR 4
> +#define GCC_USB3_DP_PHY_SEC_BCR 5
> +#define GCC_USB3_PHY_PRIM_BCR 6
> +#define GCC_USB3_PHY_SEC_BCR 7
> +#define GCC_USB3PHY_PHY_PRIM_BCR 8
> +#define GCC_USB3PHY_PHY_SEC_BCR 9
> +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 10
> +
> +/* GCC GDSCRs */
> +#define UFS_PHY_GDSC 0
> +#define USB30_PRIM_GDSC 1
> +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 2
> +#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 3
> +
> +#endif
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 3/3] clk: qcom: Add Global Clock controller (GCC) driver for SC7180
2019-09-18 9:50 ` [PATCH v3 3/3] clk: qcom: Add Global Clock controller (GCC) driver for SC7180 Taniya Das
@ 2019-09-19 11:08 ` Rajendra Nayak
2019-09-20 4:00 ` Taniya Das
[not found] ` <20190918213946.DC03521924@mail.kernel.org>
1 sibling, 1 reply; 25+ messages in thread
From: Rajendra Nayak @ 2019-09-19 11:08 UTC (permalink / raw)
To: Taniya Das, Stephen Boyd, Michael Turquette, robh+dt
Cc: David Brown, linux-arm-msm, linux-soc, linux-clk, linux-kernel,
devicetree
[]..
> +static struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
> + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
> + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
> + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
> + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
> + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
> + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
> + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
> + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
> + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
> + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
> + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
> + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
> +};
this fails to build..
In file included from drivers/clk/qcom/gcc-sc7180.c:17:0:
drivers/clk/qcom/gcc-sc7180.c:2429:17: error: ‘gcc_qupv3_wrap0_s0_clk_src_src’ undeclared here (not in a function)
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
^
drivers/clk/qcom/clk-rcg.h:171:12: note: in definition of macro ‘DEFINE_RCG_DFS’
{ .rcg = &r##_src, .init = &r##_init }
^
drivers/clk/qcom/gcc-sc7180.c:2430:17: error: ‘gcc_qupv3_wrap0_s1_clk_src_src’ undeclared here (not in a function)
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
^
drivers/clk/qcom/clk-rcg.h:171:12: note: in definition of macro ‘DEFINE_RCG_DFS’
{ .rcg = &r##_src, .init = &r##_init }
^
Perhaps you should drop _src here and in the clk_init_data names.
> +
> +static const struct regmap_config gcc_sc7180_regmap_config = {
> + .reg_bits = 32,
> + .reg_stride = 4,
> + .val_bits = 32,
> + .max_register = 0x18208c,
> + .fast_io = true,
> +};
> +
> +static const struct qcom_cc_desc gcc_sc7180_desc = {
> + .config = &gcc_sc7180_regmap_config,
> + .clk_hws = gcc_sc7180_hws,
> + .num_clk_hws = ARRAY_SIZE(gcc_sc7180_hws),
> + .clks = gcc_sc7180_clocks,
> + .num_clks = ARRAY_SIZE(gcc_sc7180_clocks),
> + .resets = gcc_sc7180_resets,
> + .num_resets = ARRAY_SIZE(gcc_sc7180_resets),
> + .gdscs = gcc_sc7180_gdscs,
> + .num_gdscs = ARRAY_SIZE(gcc_sc7180_gdscs),
> +};
> +
> +static const struct of_device_id gcc_sc7180_match_table[] = {
> + { .compatible = "qcom,gcc-sc7180" },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, gcc_sc7180_match_table);
> +
> +static int gcc_sc7180_probe(struct platform_device *pdev)
> +{
> + struct regmap *regmap;
> + int ret;
> +
> + regmap = qcom_cc_map(pdev, &gcc_sc7180_desc);
> + if (IS_ERR(regmap))
> + return PTR_ERR(regmap);
> +
> + /*
> + * Disable the GPLL0 active input to MM blocks, NPU
> + * and GPU via MISC registers.
> + */
> + regmap_update_bits(regmap, GCC_MMSS_MISC, 0x3, 0x3);
> + regmap_update_bits(regmap, GCC_NPU_MISC, 0x3, 0x3);
> + regmap_update_bits(regmap, GCC_GPU_MISC, 0x3, 0x3);
> +
> + ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
> + ARRAY_SIZE(gcc_dfs_clocks));
> + if (ret)
> + return ret;
> +
> + return qcom_cc_really_probe(pdev, &gcc_sc7180_desc, regmap);
> +}
> +
> +static struct platform_driver gcc_sc7180_driver = {
> + .probe = gcc_sc7180_probe,
> + .driver = {
> + .name = "gcc-sc7180",
> + .of_match_table = gcc_sc7180_match_table,
> + },
> +};
> +
> +static int __init gcc_sc7180_init(void)
> +{
> + return platform_driver_register(&gcc_sc7180_driver);
> +}
> +subsys_initcall(gcc_sc7180_init);
> +
> +static void __exit gcc_sc7180_exit(void)
> +{
> + platform_driver_unregister(&gcc_sc7180_driver);
> +}
> +module_exit(gcc_sc7180_exit);
> +
> +MODULE_DESCRIPTION("QTI GCC SC7180 Driver");
> +MODULE_LICENSE("GPL v2");
> --
> Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
> of the Code Aurora Forum, hosted by the Linux Foundation.
>
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 3/3] clk: qcom: Add Global Clock controller (GCC) driver for SC7180
2019-09-19 11:08 ` Rajendra Nayak
@ 2019-09-20 4:00 ` Taniya Das
2019-09-20 4:44 ` Rajendra Nayak
0 siblings, 1 reply; 25+ messages in thread
From: Taniya Das @ 2019-09-20 4:00 UTC (permalink / raw)
To: Rajendra Nayak, Stephen Boyd, Michael Turquette, robh+dt
Cc: David Brown, linux-arm-msm, linux-soc, linux-clk, linux-kernel,
devicetree
Hi Rajendra,
Please pick the patch in the series :
https://patchwork.kernel.org/patch/11150013/
On 9/19/2019 4:38 PM, Rajendra Nayak wrote:
> []..
>
>> +static struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
>> + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
>> + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
>> + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
>> + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
>> + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
>> + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
>> + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
>> + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
>> + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
>> + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
>> + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
>> + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
>> +};
>
> this fails to build..
>
> In file included from drivers/clk/qcom/gcc-sc7180.c:17:0:
> drivers/clk/qcom/gcc-sc7180.c:2429:17: error:
> ‘gcc_qupv3_wrap0_s0_clk_src_src’ undeclared here (not in a function)
> DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
> ^
> drivers/clk/qcom/clk-rcg.h:171:12: note: in definition of macro
> ‘DEFINE_RCG_DFS’
> { .rcg = &r##_src, .init = &r##_init }
> ^
> drivers/clk/qcom/gcc-sc7180.c:2430:17: error:
> ‘gcc_qupv3_wrap0_s1_clk_src_src’ undeclared here (not in a function)
> DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
> ^
> drivers/clk/qcom/clk-rcg.h:171:12: note: in definition of macro
> ‘DEFINE_RCG_DFS’
> { .rcg = &r##_src, .init = &r##_init }
> ^
> Perhaps you should drop _src here and in the clk_init_data names.
>
>> +
>> +static const struct regmap_config gcc_sc7180_regmap_config = {
>> + .reg_bits = 32,
>> + .reg_stride = 4,
>> + .val_bits = 32,
>> + .max_register = 0x18208c,
>> + .fast_io = true,
>> +};
>> +
>> +static const struct qcom_cc_desc gcc_sc7180_desc = {
>> + .config = &gcc_sc7180_regmap_config,
>> + .clk_hws = gcc_sc7180_hws,
>> + .num_clk_hws = ARRAY_SIZE(gcc_sc7180_hws),
>> + .clks = gcc_sc7180_clocks,
>> + .num_clks = ARRAY_SIZE(gcc_sc7180_clocks),
>> + .resets = gcc_sc7180_resets,
>> + .num_resets = ARRAY_SIZE(gcc_sc7180_resets),
>> + .gdscs = gcc_sc7180_gdscs,
>> + .num_gdscs = ARRAY_SIZE(gcc_sc7180_gdscs),
>> +};
>> +
>> +static const struct of_device_id gcc_sc7180_match_table[] = {
>> + { .compatible = "qcom,gcc-sc7180" },
>> + { }
>> +};
>> +MODULE_DEVICE_TABLE(of, gcc_sc7180_match_table);
>> +
>> +static int gcc_sc7180_probe(struct platform_device *pdev)
>> +{
>> + struct regmap *regmap;
>> + int ret;
>> +
>> + regmap = qcom_cc_map(pdev, &gcc_sc7180_desc);
>> + if (IS_ERR(regmap))
>> + return PTR_ERR(regmap);
>> +
>> + /*
>> + * Disable the GPLL0 active input to MM blocks, NPU
>> + * and GPU via MISC registers.
>> + */
>> + regmap_update_bits(regmap, GCC_MMSS_MISC, 0x3, 0x3);
>> + regmap_update_bits(regmap, GCC_NPU_MISC, 0x3, 0x3);
>> + regmap_update_bits(regmap, GCC_GPU_MISC, 0x3, 0x3);
>> +
>> + ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
>> + ARRAY_SIZE(gcc_dfs_clocks));
>> + if (ret)
>> + return ret;
>> +
>> + return qcom_cc_really_probe(pdev, &gcc_sc7180_desc, regmap);
>> +}
>> +
>> +static struct platform_driver gcc_sc7180_driver = {
>> + .probe = gcc_sc7180_probe,
>> + .driver = {
>> + .name = "gcc-sc7180",
>> + .of_match_table = gcc_sc7180_match_table,
>> + },
>> +};
>> +
>> +static int __init gcc_sc7180_init(void)
>> +{
>> + return platform_driver_register(&gcc_sc7180_driver);
>> +}
>> +subsys_initcall(gcc_sc7180_init);
>> +
>> +static void __exit gcc_sc7180_exit(void)
>> +{
>> + platform_driver_unregister(&gcc_sc7180_driver);
>> +}
>> +module_exit(gcc_sc7180_exit);
>> +
>> +MODULE_DESCRIPTION("QTI GCC SC7180 Driver");
>> +MODULE_LICENSE("GPL v2");
>> --
>> Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
>> of the Code Aurora Forum, hosted by the Linux Foundation.
>>
>
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.
--
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 3/3] clk: qcom: Add Global Clock controller (GCC) driver for SC7180
2019-09-20 4:00 ` Taniya Das
@ 2019-09-20 4:44 ` Rajendra Nayak
0 siblings, 0 replies; 25+ messages in thread
From: Rajendra Nayak @ 2019-09-20 4:44 UTC (permalink / raw)
To: Taniya Das, Stephen Boyd, Michael Turquette, robh+dt
Cc: David Brown, linux-arm-msm, linux-soc, linux-clk, linux-kernel,
devicetree
On 9/20/2019 9:30 AM, Taniya Das wrote:
> Hi Rajendra,
>
> Please pick the patch in the series : https://patchwork.kernel.org/patch/11150013/
ah, right, not sure how I missed the PATCH 1/3 in the series.
Sorry about the noise.
>
> On 9/19/2019 4:38 PM, Rajendra Nayak wrote:
>> []..
>>
>>> +static struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
>>> + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
>>> + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
>>> + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
>>> + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
>>> + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
>>> + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
>>> + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
>>> + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
>>> + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
>>> + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
>>> + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
>>> + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
>>> +};
>>
>> this fails to build..
>>
>> In file included from drivers/clk/qcom/gcc-sc7180.c:17:0:
>> drivers/clk/qcom/gcc-sc7180.c:2429:17: error: ‘gcc_qupv3_wrap0_s0_clk_src_src’ undeclared here (not in a function)
>> DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
>> ^
>> drivers/clk/qcom/clk-rcg.h:171:12: note: in definition of macro ‘DEFINE_RCG_DFS’
>> { .rcg = &r##_src, .init = &r##_init }
>> ^
>> drivers/clk/qcom/gcc-sc7180.c:2430:17: error: ‘gcc_qupv3_wrap0_s1_clk_src_src’ undeclared here (not in a function)
>> DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
>> ^
>> drivers/clk/qcom/clk-rcg.h:171:12: note: in definition of macro ‘DEFINE_RCG_DFS’
>> { .rcg = &r##_src, .init = &r##_init }
>> ^
>> Perhaps you should drop _src here and in the clk_init_data names.
>>
>>> +
>>> +static const struct regmap_config gcc_sc7180_regmap_config = {
>>> + .reg_bits = 32,
>>> + .reg_stride = 4,
>>> + .val_bits = 32,
>>> + .max_register = 0x18208c,
>>> + .fast_io = true,
>>> +};
>>> +
>>> +static const struct qcom_cc_desc gcc_sc7180_desc = {
>>> + .config = &gcc_sc7180_regmap_config,
>>> + .clk_hws = gcc_sc7180_hws,
>>> + .num_clk_hws = ARRAY_SIZE(gcc_sc7180_hws),
>>> + .clks = gcc_sc7180_clocks,
>>> + .num_clks = ARRAY_SIZE(gcc_sc7180_clocks),
>>> + .resets = gcc_sc7180_resets,
>>> + .num_resets = ARRAY_SIZE(gcc_sc7180_resets),
>>> + .gdscs = gcc_sc7180_gdscs,
>>> + .num_gdscs = ARRAY_SIZE(gcc_sc7180_gdscs),
>>> +};
>>> +
>>> +static const struct of_device_id gcc_sc7180_match_table[] = {
>>> + { .compatible = "qcom,gcc-sc7180" },
>>> + { }
>>> +};
>>> +MODULE_DEVICE_TABLE(of, gcc_sc7180_match_table);
>>> +
>>> +static int gcc_sc7180_probe(struct platform_device *pdev)
>>> +{
>>> + struct regmap *regmap;
>>> + int ret;
>>> +
>>> + regmap = qcom_cc_map(pdev, &gcc_sc7180_desc);
>>> + if (IS_ERR(regmap))
>>> + return PTR_ERR(regmap);
>>> +
>>> + /*
>>> + * Disable the GPLL0 active input to MM blocks, NPU
>>> + * and GPU via MISC registers.
>>> + */
>>> + regmap_update_bits(regmap, GCC_MMSS_MISC, 0x3, 0x3);
>>> + regmap_update_bits(regmap, GCC_NPU_MISC, 0x3, 0x3);
>>> + regmap_update_bits(regmap, GCC_GPU_MISC, 0x3, 0x3);
>>> +
>>> + ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
>>> + ARRAY_SIZE(gcc_dfs_clocks));
>>> + if (ret)
>>> + return ret;
>>> +
>>> + return qcom_cc_really_probe(pdev, &gcc_sc7180_desc, regmap);
>>> +}
>>> +
>>> +static struct platform_driver gcc_sc7180_driver = {
>>> + .probe = gcc_sc7180_probe,
>>> + .driver = {
>>> + .name = "gcc-sc7180",
>>> + .of_match_table = gcc_sc7180_match_table,
>>> + },
>>> +};
>>> +
>>> +static int __init gcc_sc7180_init(void)
>>> +{
>>> + return platform_driver_register(&gcc_sc7180_driver);
>>> +}
>>> +subsys_initcall(gcc_sc7180_init);
>>> +
>>> +static void __exit gcc_sc7180_exit(void)
>>> +{
>>> + platform_driver_unregister(&gcc_sc7180_driver);
>>> +}
>>> +module_exit(gcc_sc7180_exit);
>>> +
>>> +MODULE_DESCRIPTION("QTI GCC SC7180 Driver");
>>> +MODULE_LICENSE("GPL v2");
>>> --
>>> Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
>>> of the Code Aurora Forum, hosted by the Linux Foundation.
>>>
>>
>
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: clk: qcom: Add YAML schemas for the GCC clock bindings
2019-09-18 17:52 ` Matthias Kaehlcke
@ 2019-09-23 6:33 ` Taniya Das
0 siblings, 0 replies; 25+ messages in thread
From: Taniya Das @ 2019-09-23 6:33 UTC (permalink / raw)
To: Matthias Kaehlcke
Cc: Stephen Boyd, Michael Turquette, robh+dt, David Brown,
Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, devicetree
Hi Matthias,
Thank you for your review.
On 9/18/2019 11:22 PM, Matthias Kaehlcke wrote:
> Hi Taniya,
>
> not a full review, just a couple of things I noticed, comments inline.
>
> On Wed, Sep 18, 2019 at 03:20:17PM +0530, Taniya Das wrote:
>> The GCC clock provider have a bunch of generic properties that
>> are needed in a device tree. Add a YAML schemas for those. Also update
>> the compatible for SC7180 along with example for clocks & clock-names.
>
> I would suggest to split this in two:
>
> 1. conversion to YAML
> 2. add SC7180 header and example
>
I will split the patch.
>> Signed-off-by: Taniya Das <tdas@codeaurora.org>
>> ---
>> .../devicetree/bindings/clock/qcom,gcc.txt | 94 -----------
>> .../devicetree/bindings/clock/qcom,gcc.yaml | 157 ++++++++++++++++++
>> include/dt-bindings/clock/qcom,gcc-sc7180.h | 155 +++++++++++++++++
>> 3 files changed, 312 insertions(+), 94 deletions(-)
>> delete mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc.txt
>> create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc.yaml
>> create mode 100644 include/dt-bindings/clock/qcom,gcc-sc7180.h
>>
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
>> deleted file mode 100644
>> index d14362ad4132..000000000000
>> --- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
>> +++ /dev/null
>> @@ -1,94 +0,0 @@
>> -Qualcomm Global Clock & Reset Controller Binding
>> -------------------------------------------------
>> -
>> -Required properties :
>> -- compatible : shall contain only one of the following:
>> -
>> - "qcom,gcc-apq8064"
>> - "qcom,gcc-apq8084"
>> - "qcom,gcc-ipq8064"
>> - "qcom,gcc-ipq4019"
>> - "qcom,gcc-ipq8074"
>> - "qcom,gcc-msm8660"
>> - "qcom,gcc-msm8916"
>> - "qcom,gcc-msm8960"
>> - "qcom,gcc-msm8974"
>> - "qcom,gcc-msm8974pro"
>> - "qcom,gcc-msm8974pro-ac"
>> - "qcom,gcc-msm8994"
>> - "qcom,gcc-msm8996"
>> - "qcom,gcc-msm8998"
>> - "qcom,gcc-mdm9615"
>> - "qcom,gcc-qcs404"
>> - "qcom,gcc-sdm630"
>> - "qcom,gcc-sdm660"
>> - "qcom,gcc-sdm845"
>> - "qcom,gcc-sm8150"
>> -
>> -- reg : shall contain base register location and length
>> -- #clock-cells : shall contain 1
>> -- #reset-cells : shall contain 1
>> -
>> -Optional properties :
>> -- #power-domain-cells : shall contain 1
>> -- Qualcomm TSENS (thermal sensor device) on some devices can
>> -be part of GCC and hence the TSENS properties can also be
>> -part of the GCC/clock-controller node.
>> -For more details on the TSENS properties please refer
>> -Documentation/devicetree/bindings/thermal/qcom-tsens.txt
>> -- protected-clocks : Protected clock specifier list as per common clock
>> - binding.
>> -
>> -For SM8150 only:
>> - - clocks: a list of phandles and clock-specifier pairs,
>> - one for each entry in clock-names.
>> - - clock-names: "bi_tcxo" (required)
>> - "sleep_clk" (optional)
>> - "aud_ref_clock" (optional)
>> -
>> -Example:
>> - clock-controller@900000 {
>> - compatible = "qcom,gcc-msm8960";
>> - reg = <0x900000 0x4000>;
>> - #clock-cells = <1>;
>> - #reset-cells = <1>;
>> - #power-domain-cells = <1>;
>> - };
>> -
>> -Example of GCC with TSENS properties:
>> - clock-controller@900000 {
>> - compatible = "qcom,gcc-apq8064";
>> - reg = <0x00900000 0x4000>;
>> - nvmem-cells = <&tsens_calib>, <&tsens_backup>;
>> - nvmem-cell-names = "calib", "calib_backup";
>> - #clock-cells = <1>;
>> - #reset-cells = <1>;
>> - #thermal-sensor-cells = <1>;
>> - };
>> -
>> -Example of GCC with protected-clocks properties:
>> - clock-controller@100000 {
>> - compatible = "qcom,gcc-sdm845";
>> - reg = <0x100000 0x1f0000>;
>> - #clock-cells = <1>;
>> - #reset-cells = <1>;
>> - #power-domain-cells = <1>;
>> - protected-clocks = <GCC_QSPI_CORE_CLK>,
>> - <GCC_QSPI_CORE_CLK_SRC>,
>> - <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
>> - <GCC_LPASS_Q6_AXI_CLK>,
>> - <GCC_LPASS_SWAY_CLK>;
>> - };
>> -
>> -Example of GCC with clocks
>> - gcc: clock-controller@100000 {
>> - compatible = "qcom,gcc-sm8150";
>> - reg = <0x00100000 0x1f0000>;
>> - #clock-cells = <1>;
>> - #reset-cells = <1>;
>> - #power-domain-cells = <1>;
>> - clock-names = "bi_tcxo",
>> - "sleep_clk";
>> - clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
>> - <&sleep_clk>;
>> - };
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
>> new file mode 100644
>> index 000000000000..056a7977c458
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
>> @@ -0,0 +1,157 @@
>> +# SPDX-License-Identifier: GPL-2.0
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/qcom,gcc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm Global Clock & Reset Controller Binding
>> +
>> +maintainers:
>> + - Stephen Boyd <sboyd@kernel.org>
>> +
>> +properties:
>> + "#clock-cells":
>> + const: 1
>> +
>> + "#reset-cells":
>> + const: 1
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + compatible :
>> + enum:
>> + - qcom,gcc-apq8064
>> + - qcom,gcc-apq8084
>> + - qcom,gcc-ipq8064
>> + - qcom,gcc-ipq4019
>> + - qcom,gcc-ipq8074
>> + - qcom,gcc-msm8660
>> + - qcom,gcc-msm8916
>> + - qcom,gcc-msm8960
>> + - qcom,gcc-msm8974
>> + - qcom,gcc-msm8974pro
>> + - qcom,gcc-msm8974pro-ac
>> + - qcom,gcc-msm8994
>> + - qcom,gcc-msm8996
>> + - qcom,gcc-msm8998
>> + - qcom,gcc-mdm9615
>> + - qcom,gcc-qcs404
>> + - qcom,gcc-sdm630
>> + - qcom,gcc-sdm660
>> + - qcom,gcc-sdm845
>> + - qcom,gcc-sm8150
>> + - qcom,gcc-sc7180
>> +
>> + clocks:
>> + minItems: 1
>> + maxItems: 3
>> + items:
>> + - description: Board XO source
>> + - description: Board active XO source
>> + - description: Sleep clock source(optional)
>> +
>> + clock-names:
>> + minItems: 1
>> + maxItems: 3
>> + items:
>> + - const: bi_tcxo
>> + - const: bi_tcxo_ao
>> + - const: sleep_clk
>> +
>> + nvmem-cells:
>> + minItems: 1
>> + maxItems: 2
>> + description:
>> + Qualcomm TSENS (thermal sensor device) on some devices can
>> + be part of GCC and hence the TSENS properties can also be part
>> + of the GCC/clock-controller node.
>> + For more details on the TSENS properties please refer
>> + Documentation/devicetree/bindings/thermal/qcom-tsens.txt
>> +
>> + nvmem-cell-names:
>> + minItems: 1
>> + maxItems: 2
>> + description:
>> + Names for each nvmem-cells specified.
>> + items:
>> + - const: calib
>> + - const: calib_backup
>> +
>> + "#thermal-sensor-cells":
>> + const: 1
>> +
>> + "#power-domain-cells":
>> + const: 1
>> +
>> + protected-clocks:
>> + description:
>> + Protected clock specifier list as per common clock binding
>> +
>> +required:
>> + - "#clock-cells"
>> + - "#reset-cells"
>> + - compatible
>> + - reg
>> + - clocks
>> + - clock-names
>> +
>> +examples:
>> + - |
>> + // Example:
>> + clock-controller@900000 {
>> + compatible = "qcom,gcc-msm8960";
>> + reg = <0x900000 0x4000>;
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + #power-domain-cells = <1>;
>> + };
>> +
>> +
>> + - |
>> + // Example of GCC with TSENS properties:
>> + clock-controller@900000 {
>> + compatible = "qcom,gcc-apq8064";
>> + reg = <0x00900000 0x4000>;
>> + nvmem-cells = <&tsens_calib>, <&tsens_backup>;
>> + nvmem-cell-names = "calib", "calib_backup";
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + #thermal-sensor-cells = <1>;
>> + };
>> +
>> + - |
>> + //Example of GCC with protected-clocks properties:
>> + clock-controller@100000 {
>> + compatible = "qcom,gcc-sdm845";
>> + reg = <0x100000 0x1f0000>;
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + #power-domain-cells = <1>;
>> + protected-clocks = <187>, <188>, <189>, <190>, <191>;
>> + };
>> +
>> + - |
>> + //Example of GCC with clock node properties for SM8150:
>> + clock-controller@100000 {
>> + compatible = "qcom,gcc-sm8150";
>> + reg = <0x00100000 0x1f0000>;
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + #power-domain-cells = <1>;
>> + clocks = <&rpmhcc 0>, <&rpmhcc 1>, <&sleep_clk>;
>> + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
>> + };
>> +
>> + - |
>> + //Example of GCC with clock nodes properties:
>
> add "for SC7180"
>
>> + clock-controller@100000 {
>> + compatible = "qcom,gcc-sc7180";
>> + reg = <0x100000 0x1f0000>;
>> + clocks = <&rpmhcc 0>, <&rpmhcc 1>;
>
> IIUC the ids correspond to GCC_GPLL0_MAIN_DIV_CDIV and GPLL0. If
> that is correct I guess the intention is to use the constants in the
> DT?
>
>> + clock-names = "bi_tcxo", "bi_tcxo_ao";
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + #power-domain-cells = <1>;
>> + };
>> +...
>> diff --git a/include/dt-bindings/clock/qcom,gcc-sc7180.h b/include/dt-bindings/clock/qcom,gcc-sc7180.h
>> new file mode 100644
>> index 000000000000..d76b061f6a4e
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/qcom,gcc-sc7180.h
>> @@ -0,0 +1,155 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/*
>> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
>> + */
>> +
>> +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SC7180_H
>> +#define _DT_BINDINGS_CLK_QCOM_GCC_SC7180_H
>> +
>> +/* GCC clocks */
>> +#define GCC_GPLL0_MAIN_DIV_CDIV 0
>> +#define GPLL0 1
>> +#define GPLL0_OUT_EVEN 2
>> +#define GPLL1 3
>> +#define GPLL4 4
>> +#define GPLL6 5
>> +#define GPLL7 6
>> +#define GCC_AGGRE_UFS_PHY_AXI_CLK 7
>> +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 8
>> +#define GCC_BOOT_ROM_AHB_CLK 9
>> +#define GCC_CAMERA_AHB_CLK 10
>> +#define GCC_CAMERA_HF_AXI_CLK 11
>> +#define GCC_CAMERA_THROTTLE_HF_AXI_CLK 12
>> +#define GCC_CAMERA_XO_CLK 13
>> +#define GCC_CE1_AHB_CLK 14
>> +#define GCC_CE1_AXI_CLK 15
>> +#define GCC_CE1_CLK 16
>> +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 17
>> +#define GCC_CPUSS_AHB_CLK 18
>> +#define GCC_CPUSS_AHB_CLK_SRC 19
>> +#define GCC_CPUSS_GNOC_CLK 20
>> +#define GCC_CPUSS_RBCPR_CLK 21
>> +#define GCC_DDRSS_GPU_AXI_CLK 22
>> +#define GCC_DISP_AHB_CLK 23
>> +#define GCC_DISP_GPLL0_CLK_SRC 24
>> +#define GCC_DISP_GPLL0_DIV_CLK_SRC 25
>> +#define GCC_DISP_HF_AXI_CLK 26
>> +#define GCC_DISP_THROTTLE_HF_AXI_CLK 27
>> +#define GCC_DISP_XO_CLK 28
>> +#define GCC_GP1_CLK 29
>> +#define GCC_GP1_CLK_SRC 30
>> +#define GCC_GP2_CLK 31
>> +#define GCC_GP2_CLK_SRC 32
>> +#define GCC_GP3_CLK 33
>> +#define GCC_GP3_CLK_SRC 34
>> +#define GCC_GPU_CFG_AHB_CLK 35
>> +#define GCC_GPU_GPLL0_CLK_SRC 36
>> +#define GCC_GPU_GPLL0_DIV_CLK_SRC 37
>> +#define GCC_GPU_MEMNOC_GFX_CLK 38
>> +#define GCC_GPU_SNOC_DVM_GFX_CLK 39
>> +#define GCC_NPU_AXI_CLK 40
>> +#define GCC_NPU_BWMON_AXI_CLK 41
>> +#define GCC_NPU_BWMON_DMA_CFG_AHB_CLK 42
>> +#define GCC_NPU_BWMON_DSP_CFG_AHB_CLK 43
>> +#define GCC_NPU_CFG_AHB_CLK 44
>> +#define GCC_NPU_DMA_CLK 45
>> +#define GCC_NPU_GPLL0_CLK_SRC 46
>> +#define GCC_NPU_GPLL0_DIV_CLK_SRC 47
>> +#define GCC_PDM2_CLK 48
>> +#define GCC_PDM2_CLK_SRC 49
>> +#define GCC_PDM_AHB_CLK 50
>> +#define GCC_PDM_XO4_CLK 51
>> +#define GCC_PRNG_AHB_CLK 52
>> +#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 53
>> +#define GCC_QSPI_CORE_CLK 54
>> +#define GCC_QSPI_CORE_CLK_SRC 55
>> +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 56
>> +#define GCC_QUPV3_WRAP0_CORE_CLK 57
>> +#define GCC_QUPV3_WRAP0_S0_CLK 58
>> +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 59
>> +#define GCC_QUPV3_WRAP0_S1_CLK 60
>> +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 61
>> +#define GCC_QUPV3_WRAP0_S2_CLK 62
>> +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 63
>> +#define GCC_QUPV3_WRAP0_S3_CLK 64
>> +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 65
>> +#define GCC_QUPV3_WRAP0_S4_CLK 66
>> +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 67
>> +#define GCC_QUPV3_WRAP0_S5_CLK 68
>> +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 69
>> +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 70
>> +#define GCC_QUPV3_WRAP1_CORE_CLK 71
>> +#define GCC_QUPV3_WRAP1_S0_CLK 72
>> +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 73
>> +#define GCC_QUPV3_WRAP1_S1_CLK 74
>> +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 75
>> +#define GCC_QUPV3_WRAP1_S2_CLK 76
>> +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 77
>> +#define GCC_QUPV3_WRAP1_S3_CLK 78
>> +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 79
>> +#define GCC_QUPV3_WRAP1_S4_CLK 80
>> +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 81
>> +#define GCC_QUPV3_WRAP1_S5_CLK 82
>> +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 83
>> +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 84
>> +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 85
>> +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 86
>> +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 87
>> +#define GCC_SDCC1_AHB_CLK 88
>> +#define GCC_SDCC1_APPS_CLK 89
>> +#define GCC_SDCC1_APPS_CLK_SRC 90
>> +#define GCC_SDCC1_ICE_CORE_CLK 91
>> +#define GCC_SDCC1_ICE_CORE_CLK_SRC 92
>> +#define GCC_SDCC2_AHB_CLK 93
>> +#define GCC_SDCC2_APPS_CLK 94
>> +#define GCC_SDCC2_APPS_CLK_SRC 95
>> +#define GCC_SYS_NOC_CPUSS_AHB_CLK 96
>> +#define GCC_UFS_MEM_CLKREF_CLK 97
>> +#define GCC_UFS_PHY_AHB_CLK 98
>> +#define GCC_UFS_PHY_AXI_CLK 99
>> +#define GCC_UFS_PHY_AXI_CLK_SRC 100
>> +#define GCC_UFS_PHY_ICE_CORE_CLK 101
>> +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 102
>> +#define GCC_UFS_PHY_PHY_AUX_CLK 103
>> +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 104
>> +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 105
>> +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 106
>> +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 107
>> +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 108
>> +#define GCC_USB30_PRIM_MASTER_CLK 109
>> +#define GCC_USB30_PRIM_MASTER_CLK_SRC 110
>> +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 111
>> +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 112
>> +#define GCC_USB30_PRIM_SLEEP_CLK 113
>> +#define GCC_USB3_PRIM_CLKREF_CLK 114
>> +#define GCC_USB3_PRIM_PHY_AUX_CLK 115
>> +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 116
>> +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 117
>> +#define GCC_USB3_PRIM_PHY_PIPE_CLK 118
>> +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 119
>> +#define GCC_VIDEO_AHB_CLK 120
>> +#define GCC_VIDEO_AXI_CLK 121
>> +#define GCC_VIDEO_GPLL0_DIV_CLK_SRC 122
>> +#define GCC_VIDEO_THROTTLE_AXI_CLK 123
>> +#define GCC_VIDEO_XO_CLK 124
>> +
>> +/* GCC resets */
>> +#define GCC_QUSB2PHY_PRIM_BCR 0
>> +#define GCC_QUSB2PHY_SEC_BCR 1
>> +#define GCC_UFS_PHY_BCR 2
>> +#define GCC_USB30_PRIM_BCR 3
>> +#define GCC_USB3_DP_PHY_PRIM_BCR 4
>> +#define GCC_USB3_DP_PHY_SEC_BCR 5
>> +#define GCC_USB3_PHY_PRIM_BCR 6
>> +#define GCC_USB3_PHY_SEC_BCR 7
>> +#define GCC_USB3PHY_PHY_PRIM_BCR 8
>> +#define GCC_USB3PHY_PHY_SEC_BCR 9
>> +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 10
>> +
>> +/* GCC GDSCRs */
>> +#define UFS_PHY_GDSC 0
>> +#define USB30_PRIM_GDSC 1
>> +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 2
>> +#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 3
>> +
>> +#endif
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.
--
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 3/3] clk: qcom: Add Global Clock controller (GCC) driver for SC7180
[not found] ` <20190918213946.DC03521924@mail.kernel.org>
@ 2019-09-23 8:01 ` Taniya Das
2019-09-24 23:12 ` Stephen Boyd
0 siblings, 1 reply; 25+ messages in thread
From: Taniya Das @ 2019-09-23 8:01 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette, robh+dt
Cc: David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, devicetree
Hi Stephen,
Thanks for your comments.
On 9/19/2019 3:09 AM, Stephen Boyd wrote:
> Quoting Taniya Das (2019-09-18 02:50:18)
>> diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c
>> new file mode 100644
>> index 000000000000..d47865d5408f
>> --- /dev/null
>> +++ b/drivers/clk/qcom/gcc-sc7180.c
>> @@ -0,0 +1,2515 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
>> + */
>> +
>> +#include <linux/err.h>
>> +#include <linux/kernel.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/of_device.h>
>> +#include <linux/regmap.h>
>
> include clk-provider.h
>
will add this header.
Currently the <drivers/clk/qcom/clk-regmap.h> already includes it.
>> +
>> +#include <dt-bindings/clock/qcom,gcc-sc7180.h>
>> +
>> +#include "clk-alpha-pll.h"
>> +#include "clk-branch.h"
>> +#include "clk-rcg.h"
>> +#include "clk-regmap.h"
>> +#include "common.h"
>> +#include "gdsc.h"
>> +#include "reset.h"
>> +
>> +#define GCC_MMSS_MISC 0x09ffc
>> +#define GCC_NPU_MISC 0x4d110
>> +#define GCC_GPU_MISC 0x71028
>> +
>> +enum {
>> + P_BI_TCXO,
>> + P_CORE_BI_PLL_TEST_SE,
>> + P_GPLL0_OUT_EVEN,
>> + P_GPLL0_OUT_MAIN,
>> + P_GPLL1_OUT_MAIN,
>> + P_GPLL4_OUT_MAIN,
>> + P_GPLL6_OUT_MAIN,
>> + P_GPLL7_OUT_MAIN,
>> + P_SLEEP_CLK,
>> +};
>> +
>> +static struct clk_alpha_pll gpll0 = {
>> + .offset = 0x0,
>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
>> + .clkr = {
>> + .enable_reg = 0x52010,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gpll0",
>> + .parent_data = &(const struct clk_parent_data){
>> + .fw_name = "bi_tcxo",
>> + .name = "bi_tcxo",
>> + },
>> + .num_parents = 1,
>> + .ops = &clk_alpha_pll_fixed_fabia_ops,
>> + },
>> + },
>> +};
>> +
>> +static const struct clk_div_table post_div_table_gpll0_out_even[] = {
>> + { 0x1, 2 },
>> + { }
>> +};
>> +
>> +static struct clk_alpha_pll_postdiv gpll0_out_even = {
>> + .offset = 0x0,
>> + .post_div_shift = 8,
>> + .post_div_table = post_div_table_gpll0_out_even,
>> + .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even),
>> + .width = 4,
>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gpll0_out_even",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gpll0.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .ops = &clk_alpha_pll_postdiv_fabia_ops,
>> + },
>> +};
>> +
>> +static struct clk_fixed_factor gcc_pll0_main_div_cdiv = {
>> + .mult = 1,
>> + .div = 2,
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_pll0_main_div_cdiv",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gpll0.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .ops = &clk_fixed_factor_ops,
>> + },
>> +};
>> +
>> +static struct clk_alpha_pll gpll1 = {
>> + .offset = 0x01000,
>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
>> + .clkr = {
>> + .enable_reg = 0x52010,
>> + .enable_mask = BIT(1),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gpll1",
>> + .parent_data = &(const struct clk_parent_data){
>> + .fw_name = "bi_tcxo",
>> + .name = "bi_tcxo",
>> + },
>> + .num_parents = 1,
>> + .ops = &clk_alpha_pll_fixed_fabia_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_alpha_pll gpll4 = {
>> + .offset = 0x76000,
>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
>> + .clkr = {
>> + .enable_reg = 0x52010,
>> + .enable_mask = BIT(4),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gpll4",
>> + .parent_data = &(const struct clk_parent_data){
>> + .fw_name = "bi_tcxo",
>> + .name = "bi_tcxo",
>> + },
>> + .num_parents = 1,
>> + .ops = &clk_alpha_pll_fixed_fabia_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_alpha_pll gpll6 = {
>> + .offset = 0x13000,
>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
>> + .clkr = {
>> + .enable_reg = 0x52010,
>> + .enable_mask = BIT(6),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gpll6",
>> + .parent_data = &(const struct clk_parent_data){
>> + .fw_name = "bi_tcxo",
>> + .name = "bi_tcxo",
>> + },
>> + .num_parents = 1,
>> + .ops = &clk_alpha_pll_fixed_fabia_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_alpha_pll gpll7 = {
>> + .offset = 0x27000,
>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
>> + .clkr = {
>> + .enable_reg = 0x52010,
>> + .enable_mask = BIT(7),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gpll7",
>> + .parent_data = &(const struct clk_parent_data){
>> + .fw_name = "bi_tcxo",
>> + .name = "bi_tcxo",
>> + },
>> + .num_parents = 1,
>> + .ops = &clk_alpha_pll_fixed_fabia_ops,
>> + },
>> + },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_0[] = {
>> + { P_BI_TCXO, 0 },
>> + { P_GPLL0_OUT_MAIN, 1 },
>> + { P_GPLL0_OUT_EVEN, 6 },
>> + { P_CORE_BI_PLL_TEST_SE, 7 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_0[] = {
>> + { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
>> + { .hw = &gpll0.clkr.hw },
>> + { .hw = &gpll0_out_even.clkr.hw },
>> + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_0_ao[] = {
>> + { .fw_name = "bi_tcxo_ao", .name = "bi_tcxo_ao" },
>> + { .hw = &gpll0.clkr.hw },
>> + { .hw = &gpll0_out_even.clkr.hw },
>> + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_1[] = {
>> + { P_BI_TCXO, 0 },
>> + { P_GPLL0_OUT_MAIN, 1 },
>> + { P_GPLL6_OUT_MAIN, 2 },
>> + { P_GPLL0_OUT_EVEN, 6 },
>> + { P_CORE_BI_PLL_TEST_SE, 7 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_1[] = {
>> + { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
>> + { .hw = &gpll0.clkr.hw },
>> + { .hw = &gpll6.clkr.hw },
>> + { .hw = &gpll0_out_even.clkr.hw },
>> + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_2[] = {
>> + { P_BI_TCXO, 0 },
>> + { P_GPLL0_OUT_MAIN, 1 },
>> + { P_GPLL1_OUT_MAIN, 4 },
>> + { P_GPLL4_OUT_MAIN, 5 },
>> + { P_GPLL0_OUT_EVEN, 6 },
>> + { P_CORE_BI_PLL_TEST_SE, 7 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_2[] = {
>> + { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
>> + { .hw = &gpll0.clkr.hw },
>> + { .hw = &gpll1.clkr.hw },
>> + { .hw = &gpll4.clkr.hw },
>> + { .hw = &gpll0_out_even.clkr.hw },
>> + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_3[] = {
>> + { P_BI_TCXO, 0 },
>> + { P_GPLL0_OUT_MAIN, 1 },
>> + { P_CORE_BI_PLL_TEST_SE, 7 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_3[] = {
>> + { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
>> + { .hw = &gpll0.clkr.hw },
>> + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_4[] = {
>> + { P_BI_TCXO, 0 },
>> + { P_GPLL0_OUT_MAIN, 1 },
>> + { P_SLEEP_CLK, 5 },
>> + { P_GPLL0_OUT_EVEN, 6 },
>> + { P_CORE_BI_PLL_TEST_SE, 7 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_4[] = {
>> + { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
>> + { .hw = &gpll0.clkr.hw },
>> + { .fw_name = "sleep_clk", .name = "sleep_clk" },
>> + { .hw = &gpll0_out_even.clkr.hw },
>> + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_5[] = {
>> + { P_BI_TCXO, 0 },
>> + { P_GPLL0_OUT_MAIN, 1 },
>> + { P_GPLL7_OUT_MAIN, 3 },
>> + { P_GPLL0_OUT_EVEN, 6 },
>> + { P_CORE_BI_PLL_TEST_SE, 7 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_5[] = {
>> + { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
>> + { .hw = &gpll0.clkr.hw },
>> + { .hw = &gpll7.clkr.hw },
>> + { .hw = &gpll0_out_even.clkr.hw },
>> + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_6[] = {
>> + { P_BI_TCXO, 0 },
>> + { P_GPLL0_OUT_MAIN, 1 },
>> + { P_SLEEP_CLK, 5 },
>> + { P_CORE_BI_PLL_TEST_SE, 7 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_6[] = {
>> + { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
>> + { .hw = &gpll0.clkr.hw },
>> + { .fw_name = "sleep_clk", .name = "sleep_clk" },
>> + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
>> + F(19200000, P_BI_TCXO, 1, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
>> + .cmd_rcgr = 0x48014,
>> + .mnd_width = 0,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_cpuss_ahb_clk_src",
>> + .parent_data = gcc_parent_data_0_ao,
>> + .num_parents = 4,
>> + .flags = CLK_SET_RATE_PARENT,
>
> Is this supposed to have CLK_SET_RATE_PARENT set? The only parent is XO
> that's fixed rate.
>
This will be removed.
>> + .ops = &clk_rcg2_ops,
>> + },
>
> Weird tab here.
>
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
>> + F(19200000, P_BI_TCXO, 1, 0, 0),
>> + F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
>> + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
>> + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
>> + F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_gp1_clk_src = {
>> + .cmd_rcgr = 0x64004,
>> + .mnd_width = 8,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_4,
>> + .freq_tbl = ftbl_gcc_gp1_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_gp1_clk_src",
>> + .parent_data = gcc_parent_data_4,
>> + .num_parents = 5,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 gcc_gp2_clk_src = {
>> + .cmd_rcgr = 0x65004,
>> + .mnd_width = 8,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_4,
>> + .freq_tbl = ftbl_gcc_gp1_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_gp2_clk_src",
>> + .parent_data = gcc_parent_data_4,
>> + .num_parents = 5,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 gcc_gp3_clk_src = {
>> + .cmd_rcgr = 0x66004,
>> + .mnd_width = 8,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_4,
>> + .freq_tbl = ftbl_gcc_gp1_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_gp3_clk_src",
>> + .parent_data = gcc_parent_data_4,
>> + .num_parents = 5,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
>> + F(19200000, P_BI_TCXO, 1, 0, 0),
>> + F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_pdm2_clk_src = {
>> + .cmd_rcgr = 0x33010,
>> + .mnd_width = 0,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_pdm2_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_pdm2_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = 4,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
>> + F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
>> + F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
>> + F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_qspi_core_clk_src = {
>> + .cmd_rcgr = 0x4b00c,
>> + .mnd_width = 0,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_2,
>> + .freq_tbl = ftbl_gcc_qspi_core_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_qspi_core_clk_src",
>> + .parent_data = gcc_parent_data_2,
>> + .num_parents = 6,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
>> + F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
>> + F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
>> + F(19200000, P_BI_TCXO, 1, 0, 0),
>> + F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
>> + F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
>> + F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
>> + F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
>> + F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
>> + F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
>> + F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
>> + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
>> + F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
>> + F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
>> + F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
>> + F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
>> + F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
>> + .name = "gcc_qupv3_wrap0_s0_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = 4,
>> + .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
>> + .cmd_rcgr = 0x17034,
>> + .mnd_width = 16,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
>> + .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
>> + .name = "gcc_qupv3_wrap0_s1_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = 4,
>> + .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
>> + .cmd_rcgr = 0x17164,
>> + .mnd_width = 16,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
>> + .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
>> + .name = "gcc_qupv3_wrap0_s2_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = 4,
>> + .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
>> + .cmd_rcgr = 0x17294,
>> + .mnd_width = 16,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
>> + .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
>> + .name = "gcc_qupv3_wrap0_s3_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = 4,
>> + .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
>> + .cmd_rcgr = 0x173c4,
>> + .mnd_width = 16,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
>> + .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
>> + .name = "gcc_qupv3_wrap0_s4_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = 4,
>> + .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
>> + .cmd_rcgr = 0x174f4,
>> + .mnd_width = 16,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
>> + .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
>> + .name = "gcc_qupv3_wrap0_s5_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = 4,
>> + .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
>> + .cmd_rcgr = 0x17624,
>> + .mnd_width = 16,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
>> + .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
>> + .name = "gcc_qupv3_wrap1_s0_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = 4,
>> + .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
>> + .cmd_rcgr = 0x18018,
>> + .mnd_width = 16,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
>> + .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
>> + .name = "gcc_qupv3_wrap1_s1_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = 4,
>> + .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
>> + .cmd_rcgr = 0x18148,
>> + .mnd_width = 16,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
>> + .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
>> + .name = "gcc_qupv3_wrap1_s2_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = 4,
>> + .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
>> + .cmd_rcgr = 0x18278,
>> + .mnd_width = 16,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
>> + .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
>> + .name = "gcc_qupv3_wrap1_s3_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = 4,
>> + .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
>> + .cmd_rcgr = 0x183a8,
>> + .mnd_width = 16,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
>> + .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
>> + .name = "gcc_qupv3_wrap1_s4_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = 4,
>> + .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
>> + .cmd_rcgr = 0x184d8,
>> + .mnd_width = 16,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
>> + .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
>> + .name = "gcc_qupv3_wrap1_s5_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = 4,
>> + .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
>> + .cmd_rcgr = 0x18608,
>> + .mnd_width = 16,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
>> + .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
>> +};
>> +
>> +
>> +static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
>> + F(144000, P_BI_TCXO, 16, 3, 25),
>> + F(400000, P_BI_TCXO, 12, 1, 4),
>> + F(19200000, P_BI_TCXO, 1, 0, 0),
>> + F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3),
>> + F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2),
>> + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
>> + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
>> + F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
>> + F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
>> + .cmd_rcgr = 0x12028,
>> + .mnd_width = 8,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_1,
>> + .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_sdcc1_apps_clk_src",
>> + .parent_data = gcc_parent_data_1,
>> + .num_parents = 5,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
>> + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
>> + F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
>> + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
>> + F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
>> + .cmd_rcgr = 0x12010,
>> + .mnd_width = 0,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_sdcc1_ice_core_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = 4,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
>> + F(400000, P_BI_TCXO, 12, 1, 4),
>> + F(9600000, P_BI_TCXO, 2, 0, 0),
>> + F(19200000, P_BI_TCXO, 1, 0, 0),
>> + F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
>> + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
>> + F(202000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
>> + .cmd_rcgr = 0x1400c,
>> + .mnd_width = 8,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_5,
>> + .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_sdcc2_apps_clk_src",
>> + .parent_data = gcc_parent_data_5,
>> + .num_parents = 5,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
>> + F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
>> + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
>> + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
>> + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
>> + F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
>> + .cmd_rcgr = 0x77020,
>> + .mnd_width = 8,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_ufs_phy_axi_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = 4,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
>> + F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
>> + F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
>> + F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
>> + F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
>> + .cmd_rcgr = 0x77048,
>> + .mnd_width = 0,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_ufs_phy_ice_core_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = 4,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
>> + F(9600000, P_BI_TCXO, 2, 0, 0),
>> + F(19200000, P_BI_TCXO, 1, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
>> + .cmd_rcgr = 0x77098,
>> + .mnd_width = 0,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_3,
>> + .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_ufs_phy_phy_aux_clk_src",
>> + .parent_data = gcc_parent_data_3,
>> + .num_parents = 3,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
>> + F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
>> + F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
>> + F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
>> + .cmd_rcgr = 0x77060,
>> + .mnd_width = 0,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_ufs_phy_unipro_core_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = 4,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
>> + F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
>> + F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
>> + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
>> + F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
>> + .cmd_rcgr = 0xf01c,
>> + .mnd_width = 8,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_usb30_prim_master_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = 4,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
>> + F(19200000, P_BI_TCXO, 1, 0, 0),
>> + F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
>> + .cmd_rcgr = 0xf034,
>> + .mnd_width = 0,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_usb30_prim_mock_utmi_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = 4,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_usb3_prim_phy_aux_clk_src[] = {
>> + F(19200000, P_BI_TCXO, 1, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
>> + .cmd_rcgr = 0xf060,
>> + .mnd_width = 0,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_6,
>> + .freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_usb3_prim_phy_aux_clk_src",
>> + .parent_data = gcc_parent_data_6,
>> + .num_parents = 4,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
>> + .halt_reg = 0x82024,
>> + .halt_check = BRANCH_HALT_DELAY,
>> + .hwcg_reg = 0x82024,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x82024,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_aggre_ufs_phy_axi_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
>> + .halt_reg = 0x8201c,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0x8201c,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_aggre_usb3_prim_axi_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_boot_rom_ahb_clk = {
>> + .halt_reg = 0x38004,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x38004,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x52000,
>> + .enable_mask = BIT(10),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_boot_rom_ahb_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_camera_ahb_clk = {
>> + .halt_reg = 0xb008,
>> + .halt_check = BRANCH_HALT,
>> + .hwcg_reg = 0xb008,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0xb008,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_camera_ahb_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_camera_hf_axi_clk = {
>> + .halt_reg = 0xb020,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0xb020,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_camera_hf_axi_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_camera_throttle_hf_axi_clk = {
>> + .halt_reg = 0xb080,
>> + .halt_check = BRANCH_HALT,
>> + .hwcg_reg = 0xb080,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0xb080,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_camera_throttle_hf_axi_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_camera_xo_clk = {
>> + .halt_reg = 0xb02c,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0xb02c,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_camera_xo_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_ce1_ahb_clk = {
>> + .halt_reg = 0x4100c,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x4100c,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x52000,
>> + .enable_mask = BIT(3),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_ce1_ahb_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_ce1_axi_clk = {
>> + .halt_reg = 0x41008,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52000,
>> + .enable_mask = BIT(4),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_ce1_axi_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_ce1_clk = {
>> + .halt_reg = 0x41004,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52000,
>> + .enable_mask = BIT(5),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_ce1_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
>> + .halt_reg = 0x502c,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0x502c,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_cfg_noc_usb3_prim_axi_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +/* For CPUSS functionality the AHB clock needs to be left enabled */
>> +static struct clk_branch gcc_cpuss_ahb_clk = {
>> + .halt_reg = 0x48000,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52000,
>> + .enable_mask = BIT(21),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_cpuss_ahb_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_cpuss_ahb_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +/* For CPUSS functionality the GNOC clock needs to be left enabled */
>> +static struct clk_branch gcc_cpuss_gnoc_clk = {
>> + .halt_reg = 0x48004,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x48004,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x52000,
>> + .enable_mask = BIT(22),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_cpuss_gnoc_clk",
>> + .flags = CLK_IS_CRITICAL,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_cpuss_rbcpr_clk = {
>> + .halt_reg = 0x48008,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0x48008,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_cpuss_rbcpr_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_ddrss_gpu_axi_clk = {
>> + .halt_reg = 0x4452c,
>> + .halt_check = BRANCH_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x4452c,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_ddrss_gpu_axi_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +/* Leave the clock ON for parent config_noc_clk to be kept enabled */
>> +static struct clk_branch gcc_disp_ahb_clk = {
>> + .halt_reg = 0xb00c,
>> + .halt_check = BRANCH_HALT,
>> + .hwcg_reg = 0xb00c,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0xb00c,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_disp_ahb_clk",
>> + .flags = CLK_IS_CRITICAL,
>
> Does this assume the display is left enabled out of the bootloader? Why
> is this critical to system operation? Maybe it is really
> CLK_IGNORE_UNUSED?
>
This clock is not kept enabled by bootloader. But leaving this ON for
clients on config noc.
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_disp_gpll0_clk_src = {
>> + .halt_check = BRANCH_HALT_DELAY,
>> + .clkr = {
>> + .enable_reg = 0x52000,
>> + .enable_mask = BIT(18),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_disp_gpll0_clk_src",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gpll0.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_disp_gpll0_div_clk_src = {
>> + .halt_check = BRANCH_HALT_DELAY,
>> + .clkr = {
>> + .enable_reg = 0x52000,
>> + .enable_mask = BIT(19),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_disp_gpll0_div_clk_src",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_pll0_main_div_cdiv.hw,
>> + },
>> + .num_parents = 1,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_disp_hf_axi_clk = {
>> + .halt_reg = 0xb024,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0xb024,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_disp_hf_axi_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_disp_throttle_hf_axi_clk = {
>> + .halt_reg = 0xb084,
>> + .halt_check = BRANCH_HALT,
>> + .hwcg_reg = 0xb084,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0xb084,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_disp_throttle_hf_axi_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_disp_xo_clk = {
>> + .halt_reg = 0xb030,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0xb030,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_disp_xo_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_gp1_clk = {
>> + .halt_reg = 0x64000,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0x64000,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_gp1_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_gp1_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_gp2_clk = {
>> + .halt_reg = 0x65000,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0x65000,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_gp2_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_gp2_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_gp3_clk = {
>> + .halt_reg = 0x66000,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0x66000,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_gp3_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_gp3_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +/* Leave the clock ON for parent config_noc_clk to be kept enabled */
>> +static struct clk_branch gcc_gpu_cfg_ahb_clk = {
>> + .halt_reg = 0x71004,
>> + .halt_check = BRANCH_HALT,
>> + .hwcg_reg = 0x71004,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x71004,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_gpu_cfg_ahb_clk",
>> + .flags = CLK_IS_CRITICAL,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_gpu_gpll0_clk_src = {
>> + .halt_check = BRANCH_HALT_DELAY,
>> + .clkr = {
>> + .enable_reg = 0x52000,
>> + .enable_mask = BIT(15),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_gpu_gpll0_clk_src",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gpll0.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
>> + .halt_check = BRANCH_HALT_DELAY,
>> + .clkr = {
>> + .enable_reg = 0x52000,
>> + .enable_mask = BIT(16),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_gpu_gpll0_div_clk_src",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_pll0_main_div_cdiv.hw,
>> + },
>> + .num_parents = 1,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
>> + .halt_reg = 0x7100c,
>> + .halt_check = BRANCH_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x7100c,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_gpu_memnoc_gfx_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
>> + .halt_reg = 0x71018,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0x71018,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_gpu_snoc_dvm_gfx_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_npu_axi_clk = {
>> + .halt_reg = 0x4d008,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0x4d008,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_npu_axi_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_npu_bwmon_axi_clk = {
>> + .halt_reg = 0x73008,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0x73008,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_npu_bwmon_axi_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_npu_bwmon_dma_cfg_ahb_clk = {
>> + .halt_reg = 0x73018,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0x73018,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_npu_bwmon_dma_cfg_ahb_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_npu_bwmon_dsp_cfg_ahb_clk = {
>> + .halt_reg = 0x7301c,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0x7301c,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_npu_bwmon_dsp_cfg_ahb_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_npu_cfg_ahb_clk = {
>> + .halt_reg = 0x4d004,
>> + .halt_check = BRANCH_HALT,
>> + .hwcg_reg = 0x4d004,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x4d004,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_npu_cfg_ahb_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_npu_dma_clk = {
>> + .halt_reg = 0x4d1a0,
>> + .halt_check = BRANCH_HALT,
>> + .hwcg_reg = 0x4d1a0,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x4d1a0,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_npu_dma_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_npu_gpll0_clk_src = {
>> + .halt_check = BRANCH_HALT_DELAY,
>> + .clkr = {
>> + .enable_reg = 0x52000,
>> + .enable_mask = BIT(25),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_npu_gpll0_clk_src",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gpll0.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_npu_gpll0_div_clk_src = {
>> + .halt_check = BRANCH_HALT_DELAY,
>> + .clkr = {
>> + .enable_reg = 0x52000,
>> + .enable_mask = BIT(26),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_npu_gpll0_div_clk_src",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_pll0_main_div_cdiv.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_pdm2_clk = {
>> + .halt_reg = 0x3300c,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0x3300c,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_pdm2_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_pdm2_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_pdm_ahb_clk = {
>> + .halt_reg = 0x33004,
>> + .halt_check = BRANCH_HALT,
>> + .hwcg_reg = 0x33004,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x33004,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_pdm_ahb_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_pdm_xo4_clk = {
>> + .halt_reg = 0x33008,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0x33008,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_pdm_xo4_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_prng_ahb_clk = {
>> + .halt_reg = 0x34004,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x34004,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x52000,
>> + .enable_mask = BIT(13),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_prng_ahb_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
>> + .halt_reg = 0x4b004,
>> + .halt_check = BRANCH_HALT,
>> + .hwcg_reg = 0x4b004,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x4b004,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qspi_cnoc_periph_ahb_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qspi_core_clk = {
>> + .halt_reg = 0x4b008,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0x4b008,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qspi_core_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_qspi_core_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
>> + .halt_reg = 0x17014,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(9),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap0_core_2x_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap0_core_clk = {
>> + .halt_reg = 0x1700c,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(8),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap0_core_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
>> + .halt_reg = 0x17030,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(10),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap0_s0_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
>> + .halt_reg = 0x17160,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(11),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap0_s1_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
>> + .halt_reg = 0x17290,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(12),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap0_s2_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
>> + .halt_reg = 0x173c0,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(13),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap0_s3_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
>> + .halt_reg = 0x174f0,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(14),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap0_s4_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
>> + .halt_reg = 0x17620,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(15),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap0_s5_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
>> + .halt_reg = 0x18004,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(18),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap1_core_2x_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap1_core_clk = {
>> + .halt_reg = 0x18008,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(19),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap1_core_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
>> + .halt_reg = 0x18014,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(22),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap1_s0_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
>> + .halt_reg = 0x18144,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(23),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap1_s1_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
>> + .halt_reg = 0x18274,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(24),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap1_s2_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
>> + .halt_reg = 0x183a4,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(25),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap1_s3_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
>> + .halt_reg = 0x184d4,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(26),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap1_s4_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
>> + .halt_reg = 0x18604,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(27),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap1_s5_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
>> + .halt_reg = 0x17004,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(6),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap_0_m_ahb_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
>> + .halt_reg = 0x17008,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x17008,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(7),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap_0_s_ahb_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
>> + .halt_reg = 0x1800c,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(20),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap_1_m_ahb_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
>> + .halt_reg = 0x18010,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x18010,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(21),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap_1_s_ahb_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_sdcc1_ahb_clk = {
>> + .halt_reg = 0x12008,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0x12008,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_sdcc1_ahb_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_sdcc1_apps_clk = {
>> + .halt_reg = 0x1200c,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0x1200c,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_sdcc1_apps_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_sdcc1_apps_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_sdcc1_ice_core_clk = {
>> + .halt_reg = 0x12040,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0x12040,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_sdcc1_ice_core_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_sdcc1_ice_core_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_sdcc2_ahb_clk = {
>> + .halt_reg = 0x14008,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0x14008,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_sdcc2_ahb_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_sdcc2_apps_clk = {
>> + .halt_reg = 0x14004,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0x14004,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_sdcc2_apps_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_sdcc2_apps_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +/* For CPUSS functionality the SYS NOC clock needs to be left enabled */
>> +static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
>> + .halt_reg = 0x4144,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52000,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_sys_noc_cpuss_ahb_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_cpuss_ahb_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_ufs_mem_clkref_clk = {
>> + .halt_reg = 0x8c000,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0x8c000,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_ufs_mem_clkref_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_ufs_phy_ahb_clk = {
>> + .halt_reg = 0x77014,
>> + .halt_check = BRANCH_HALT,
>> + .hwcg_reg = 0x77014,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x77014,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_ufs_phy_ahb_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_ufs_phy_axi_clk = {
>> + .halt_reg = 0x77038,
>> + .halt_check = BRANCH_HALT,
>> + .hwcg_reg = 0x77038,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x77038,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_ufs_phy_axi_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_ufs_phy_ice_core_clk = {
>> + .halt_reg = 0x77090,
>> + .halt_check = BRANCH_HALT,
>> + .hwcg_reg = 0x77090,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x77090,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_ufs_phy_ice_core_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
>> + .halt_reg = 0x77094,
>> + .halt_check = BRANCH_HALT,
>> + .hwcg_reg = 0x77094,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x77094,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_ufs_phy_phy_aux_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
>> + .halt_reg = 0x7701c,
>> + .halt_check = BRANCH_HALT_SKIP,
>
> Again, nobody has fixed the UFS driver to not need to do this halt skip
> check for these clks? It's been over a year.
>
The UFS_PHY_RX/TX clocks could be left enabled due to certain HW boot
configuration and thus during the late initcall of clk_disable there
could be warnings of "clock stuck ON" in the dmesg. That is the reason
also to use the BRANCH_HALT_SKIP flag.
I would also check internally for the UFS driver fix you are referring here.
>> + .clkr = {
>> + .enable_reg = 0x7701c,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_ufs_phy_rx_symbol_0_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
>> + .halt_reg = 0x77018,
>> + .halt_check = BRANCH_HALT_SKIP,
>> + .clkr = {
>> + .enable_reg = 0x77018,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_ufs_phy_tx_symbol_0_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
>> + .halt_reg = 0x7708c,
>> + .halt_check = BRANCH_HALT,
>> + .hwcg_reg = 0x7708c,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x7708c,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_ufs_phy_unipro_core_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_usb30_prim_master_clk = {
>> + .halt_reg = 0xf010,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0xf010,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_usb30_prim_master_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
>> + .halt_reg = 0xf018,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0xf018,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_usb30_prim_mock_utmi_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw =
>> + &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_usb30_prim_sleep_clk = {
>> + .halt_reg = 0xf014,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0xf014,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_usb30_prim_sleep_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_usb3_prim_clkref_clk = {
>> + .halt_reg = 0x8c010,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0x8c010,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_usb3_prim_clkref_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
>> + .halt_reg = 0xf050,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0xf050,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_usb3_prim_phy_aux_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
>> + .halt_reg = 0xf054,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0xf054,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_usb3_prim_phy_com_aux_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
>> + .halt_reg = 0xf058,
>> + .halt_check = BRANCH_HALT_SKIP,
>
> Why does this need halt_skip?
This is required as the source is external PHY, so we want to not check
for HALT.
>
>> + .clkr = {
>> + .enable_reg = 0xf058,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_usb3_prim_phy_pipe_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
>> + .halt_reg = 0x6a004,
>> + .halt_check = BRANCH_HALT,
>> + .hwcg_reg = 0x6a004,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x6a004,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_usb_phy_cfg_ahb2phy_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +/* Leave the clock ON for parent config_noc_clk to be kept enabled */
>
> There's no parent though... So I guess this means it keeps it enabled
> implicitly in hardware?
>
These are not left enabled, but want to leave them enabled for clients
on config NOC.
>> +static struct clk_branch gcc_video_ahb_clk = {
>> + .halt_reg = 0xb004,
>> + .halt_check = BRANCH_HALT,
>> + .hwcg_reg = 0xb004,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0xb004,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_video_ahb_clk",
>> + .flags = CLK_IS_CRITICAL,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
> [..]
>> +
>> +static const struct qcom_reset_map gcc_sc7180_resets[] = {
>> + [GCC_QUSB2PHY_PRIM_BCR] = { 0x26000 },
>> + [GCC_QUSB2PHY_SEC_BCR] = { 0x26004 },
>> + [GCC_UFS_PHY_BCR] = { 0x77000 },
>> + [GCC_USB30_PRIM_BCR] = { 0xf000 },
>> + [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
>> + [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
>> + [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
>> + [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
>> + [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
>> + [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
>> + [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
>> +};
>> +
>> +static struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
>
> const?
>
Will take care of this too.
>> + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
>> + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
>> + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
>> + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
>> + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
>> + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
>> + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
>> + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
>> + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
>> + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
>> + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
>> + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
>> +};
>> +
>> +static const struct regmap_config gcc_sc7180_regmap_config = {
>> + .reg_bits = 32,
>> + .reg_stride = 4,
>> + .val_bits = 32,
>> + .max_register = 0x18208c,
>> + .fast_io = true,
>> +};
>> +
>> +static const struct qcom_cc_desc gcc_sc7180_desc = {
>> + .config = &gcc_sc7180_regmap_config,
>> + .clk_hws = gcc_sc7180_hws,
>> + .num_clk_hws = ARRAY_SIZE(gcc_sc7180_hws),
>> + .clks = gcc_sc7180_clocks,
>> + .num_clks = ARRAY_SIZE(gcc_sc7180_clocks),
>> + .resets = gcc_sc7180_resets,
>> + .num_resets = ARRAY_SIZE(gcc_sc7180_resets),
>> + .gdscs = gcc_sc7180_gdscs,
>> + .num_gdscs = ARRAY_SIZE(gcc_sc7180_gdscs),
>> +};
>> +
>> +static const struct of_device_id gcc_sc7180_match_table[] = {
>> + { .compatible = "qcom,gcc-sc7180" },
>> + { }
>> +};
>> +MODULE_DEVICE_TABLE(of, gcc_sc7180_match_table);
>> +
>> +static int gcc_sc7180_probe(struct platform_device *pdev)
>> +{
>> + struct regmap *regmap;
>> + int ret;
>> +
>> + regmap = qcom_cc_map(pdev, &gcc_sc7180_desc);
>> + if (IS_ERR(regmap))
>> + return PTR_ERR(regmap);
>> +
>> + /*
>> + * Disable the GPLL0 active input to MM blocks, NPU
>> + * and GPU via MISC registers.
>> + */
>> + regmap_update_bits(regmap, GCC_MMSS_MISC, 0x3, 0x3);
>> + regmap_update_bits(regmap, GCC_NPU_MISC, 0x3, 0x3);
>> + regmap_update_bits(regmap, GCC_GPU_MISC, 0x3, 0x3);
>> +
>> + ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
>> + ARRAY_SIZE(gcc_dfs_clocks));
>> + if (ret)
>> + return ret;
>> +
>> + return qcom_cc_really_probe(pdev, &gcc_sc7180_desc, regmap);
>> +}
>> +
>> +static struct platform_driver gcc_sc7180_driver = {
>> + .probe = gcc_sc7180_probe,
>> + .driver = {
>> + .name = "gcc-sc7180",
>> + .of_match_table = gcc_sc7180_match_table,
>> + },
>> +};
>> +
>> +static int __init gcc_sc7180_init(void)
>> +{
>> + return platform_driver_register(&gcc_sc7180_driver);
>> +}
>> +subsys_initcall(gcc_sc7180_init);
>
> Make this core_initcall because Amit has done that for other drivers.
>
Will move it to core_initcall().
>> +
>> +static void __exit gcc_sc7180_exit(void)
>> +{
>> + platform_driver_unregister(&gcc_sc7180_driver);
>> +}
>> +module_exit(gcc_sc7180_exit);
>> +
>> +MODULE_DESCRIPTION("QTI GCC SC7180 Driver");
>> +MODULE_LICENSE("GPL v2");
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.
--
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 3/3] clk: qcom: Add Global Clock controller (GCC) driver for SC7180
2019-09-23 8:01 ` Taniya Das
@ 2019-09-24 23:12 ` Stephen Boyd
2019-09-25 11:20 ` Taniya Das
0 siblings, 1 reply; 25+ messages in thread
From: Stephen Boyd @ 2019-09-24 23:12 UTC (permalink / raw)
To: Michael Turquette, Taniya Das, robh+dt
Cc: David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, devicetree
Quoting Taniya Das (2019-09-23 01:01:11)
> Hi Stephen,
>
> Thanks for your comments.
>
> On 9/19/2019 3:09 AM, Stephen Boyd wrote:
> > Quoting Taniya Das (2019-09-18 02:50:18)
> >> diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c
> >> new file mode 100644
> >> index 000000000000..d47865d5408f
> >> --- /dev/null
> >> +++ b/drivers/clk/qcom/gcc-sc7180.c
> >> @@ -0,0 +1,2515 @@
> >> +// SPDX-License-Identifier: GPL-2.0
> >> +/*
> >> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
> >> + */
> >> +
> >> +#include <linux/err.h>
> >> +#include <linux/kernel.h>
> >> +#include <linux/module.h>
> >> +#include <linux/of.h>
> >> +#include <linux/of_device.h>
> >> +#include <linux/regmap.h>
> >
> > include clk-provider.h
> >
>
> will add this header.
> Currently the <drivers/clk/qcom/clk-regmap.h> already includes it.
Yes but it should be included in any clk-provider drivers too.
> >> +
> >> +/* Leave the clock ON for parent config_noc_clk to be kept enabled */
> >> +static struct clk_branch gcc_disp_ahb_clk = {
> >> + .halt_reg = 0xb00c,
> >> + .halt_check = BRANCH_HALT,
> >> + .hwcg_reg = 0xb00c,
> >> + .hwcg_bit = 1,
> >> + .clkr = {
> >> + .enable_reg = 0xb00c,
> >> + .enable_mask = BIT(0),
> >> + .hw.init = &(struct clk_init_data){
> >> + .name = "gcc_disp_ahb_clk",
> >> + .flags = CLK_IS_CRITICAL,
> >
> > Does this assume the display is left enabled out of the bootloader? Why
> > is this critical to system operation? Maybe it is really
> > CLK_IGNORE_UNUSED?
> >
>
> This clock is not kept enabled by bootloader. But leaving this ON for
> clients on config noc.
Please see below comment for the other critical clk with no parent.
>
> >> + .ops = &clk_branch2_ops,
> >> + },
> >> + },
> >> +};
> >> +
[...]
> >> +static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
> >> + .halt_reg = 0x77094,
> >> + .halt_check = BRANCH_HALT,
> >> + .hwcg_reg = 0x77094,
> >> + .hwcg_bit = 1,
> >> + .clkr = {
> >> + .enable_reg = 0x77094,
> >> + .enable_mask = BIT(0),
> >> + .hw.init = &(struct clk_init_data){
> >> + .name = "gcc_ufs_phy_phy_aux_clk",
> >> + .parent_data = &(const struct clk_parent_data){
> >> + .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
> >> + },
> >> + .num_parents = 1,
> >> + .flags = CLK_SET_RATE_PARENT,
> >> + .ops = &clk_branch2_ops,
> >> + },
> >> + },
> >> +};
> >> +
> >> +static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
> >> + .halt_reg = 0x7701c,
> >> + .halt_check = BRANCH_HALT_SKIP,
> >
> > Again, nobody has fixed the UFS driver to not need to do this halt skip
> > check for these clks? It's been over a year.
> >
>
> The UFS_PHY_RX/TX clocks could be left enabled due to certain HW boot
> configuration and thus during the late initcall of clk_disable there
> could be warnings of "clock stuck ON" in the dmesg. That is the reason
> also to use the BRANCH_HALT_SKIP flag.
Oh that's bad. Why do the clks stay on when we try to turn them off?
>
> I would also check internally for the UFS driver fix you are referring here.
Sure. I keep asking but nothing is done :(
>
> >> + .clkr = {
> >> + .enable_reg = 0x7701c,
> >> + .enable_mask = BIT(0),
> >> + .hw.init = &(struct clk_init_data){
> >> + .name = "gcc_ufs_phy_rx_symbol_0_clk",
> >> + .ops = &clk_branch2_ops,
> >> + },
> >> + },
> >> +};
> >> +
[...]
> >> +
> >> +static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
> >> + .halt_reg = 0xf058,
> >> + .halt_check = BRANCH_HALT_SKIP,
> >
> > Why does this need halt_skip?
>
> This is required as the source is external PHY, so we want to not check
> for HALT.
This doesn't really answer my question. If the source is an external phy
then it should be listed as a clock in the DT binding and the parent
should be specified here. Unless something doesn't work because of that?
>
> >
> >> + .clkr = {
> >> + .enable_reg = 0xf058,
> >> + .enable_mask = BIT(0),
> >> + .hw.init = &(struct clk_init_data){
> >> + .name = "gcc_usb3_prim_phy_pipe_clk",
> >> + .ops = &clk_branch2_ops,
> >> + },
> >> + },
> >> +};
> >> +
> >> +static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
> >> + .halt_reg = 0x6a004,
> >> + .halt_check = BRANCH_HALT,
> >> + .hwcg_reg = 0x6a004,
> >> + .hwcg_bit = 1,
> >> + .clkr = {
> >> + .enable_reg = 0x6a004,
> >> + .enable_mask = BIT(0),
> >> + .hw.init = &(struct clk_init_data){
> >> + .name = "gcc_usb_phy_cfg_ahb2phy_clk",
> >> + .ops = &clk_branch2_ops,
> >> + },
> >> + },
> >> +};
> >> +
> >> +/* Leave the clock ON for parent config_noc_clk to be kept enabled */
> >
> > There's no parent though... So I guess this means it keeps it enabled
> > implicitly in hardware?
> >
>
> These are not left enabled, but want to leave them enabled for clients
> on config NOC.
Sure. It just doesn't make sense to create clk structures and expose
them in the kernel when we just want to turn the bits on and leave them
on forever. Why not just do some register writes in probe for this
driver? Doesn't that work just as well and use less memory?
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 3/3] clk: qcom: Add Global Clock controller (GCC) driver for SC7180
2019-09-24 23:12 ` Stephen Boyd
@ 2019-09-25 11:20 ` Taniya Das
2019-09-25 13:03 ` Stephen Boyd
0 siblings, 1 reply; 25+ messages in thread
From: Taniya Das @ 2019-09-25 11:20 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette, robh+dt
Cc: David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, devicetree
Hi Stephen,
Please find my comments.
On 9/25/2019 4:42 AM, Stephen Boyd wrote:
> Quoting Taniya Das (2019-09-23 01:01:11)
>> Hi Stephen,
>>
>> Thanks for your comments.
>>
>> On 9/19/2019 3:09 AM, Stephen Boyd wrote:
>>> Quoting Taniya Das (2019-09-18 02:50:18)
>>>> diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c
>>>> new file mode 100644
>>>> index 000000000000..d47865d5408f
>>>> --- /dev/null
>>>> +++ b/drivers/clk/qcom/gcc-sc7180.c
>>>> @@ -0,0 +1,2515 @@
>>>> +// SPDX-License-Identifier: GPL-2.0
>>>> +/*
>>>> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
>>>> + */
>>>> +
>>>> +#include <linux/err.h>
>>>> +#include <linux/kernel.h>
>>>> +#include <linux/module.h>
>>>> +#include <linux/of.h>
>>>> +#include <linux/of_device.h>
>>>> +#include <linux/regmap.h>
>>>
>>> include clk-provider.h
>>>
>>
>> will add this header.
>> Currently the <drivers/clk/qcom/clk-regmap.h> already includes it.
>
> Yes but it should be included in any clk-provider drivers too.
>
>>>> +
>>>> +/* Leave the clock ON for parent config_noc_clk to be kept enabled */
>>>> +static struct clk_branch gcc_disp_ahb_clk = {
>>>> + .halt_reg = 0xb00c,
>>>> + .halt_check = BRANCH_HALT,
>>>> + .hwcg_reg = 0xb00c,
>>>> + .hwcg_bit = 1,
>>>> + .clkr = {
>>>> + .enable_reg = 0xb00c,
>>>> + .enable_mask = BIT(0),
>>>> + .hw.init = &(struct clk_init_data){
>>>> + .name = "gcc_disp_ahb_clk",
>>>> + .flags = CLK_IS_CRITICAL,
>>>
>>> Does this assume the display is left enabled out of the bootloader? Why
>>> is this critical to system operation? Maybe it is really
>>> CLK_IGNORE_UNUSED?
>>>
>>
>> This clock is not kept enabled by bootloader. But leaving this ON for
>> clients on config noc.
>
> Please see below comment for the other critical clk with no parent.
>
>>
>>>> + .ops = &clk_branch2_ops,
>>>> + },
>>>> + },
>>>> +};
>>>> +
> [...]
>>>> +static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
>>>> + .halt_reg = 0x77094,
>>>> + .halt_check = BRANCH_HALT,
>>>> + .hwcg_reg = 0x77094,
>>>> + .hwcg_bit = 1,
>>>> + .clkr = {
>>>> + .enable_reg = 0x77094,
>>>> + .enable_mask = BIT(0),
>>>> + .hw.init = &(struct clk_init_data){
>>>> + .name = "gcc_ufs_phy_phy_aux_clk",
>>>> + .parent_data = &(const struct clk_parent_data){
>>>> + .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
>>>> + },
>>>> + .num_parents = 1,
>>>> + .flags = CLK_SET_RATE_PARENT,
>>>> + .ops = &clk_branch2_ops,
>>>> + },
>>>> + },
>>>> +};
>>>> +
>>>> +static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
>>>> + .halt_reg = 0x7701c,
>>>> + .halt_check = BRANCH_HALT_SKIP,
>>>
>>> Again, nobody has fixed the UFS driver to not need to do this halt skip
>>> check for these clks? It's been over a year.
>>>
>>
>> The UFS_PHY_RX/TX clocks could be left enabled due to certain HW boot
>> configuration and thus during the late initcall of clk_disable there
>> could be warnings of "clock stuck ON" in the dmesg. That is the reason
>> also to use the BRANCH_HALT_SKIP flag.
>
> Oh that's bad. Why do the clks stay on when we try to turn them off?
>
Those could be due to the configuration selected by HW and SW cannot
override them, so traditionally we have never polled for CLK_OFF for
these clocks.
>>
>> I would also check internally for the UFS driver fix you are referring here.
>
> Sure. I keep asking but nothing is done :(
>
>>
>>>> + .clkr = {
>>>> + .enable_reg = 0x7701c,
>>>> + .enable_mask = BIT(0),
>>>> + .hw.init = &(struct clk_init_data){
>>>> + .name = "gcc_ufs_phy_rx_symbol_0_clk",
>>>> + .ops = &clk_branch2_ops,
>>>> + },
>>>> + },
>>>> +};
>>>> +
> [...]
>>>> +
>>>> +static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
>>>> + .halt_reg = 0xf058,
>>>> + .halt_check = BRANCH_HALT_SKIP,
>>>
>>> Why does this need halt_skip?
>>
>> This is required as the source is external PHY, so we want to not check
>> for HALT.
>
> This doesn't really answer my question. If the source is an external phy
> then it should be listed as a clock in the DT binding and the parent
> should be specified here. Unless something doesn't work because of that?
>
The USB phy is managed by the USB driver and clock driver is not aware
if USB driver models the phy as a clock. Thus we do want to keep a
dependency on the parent and not poll for CLK_ENABLE.
>>
>>>
>>>> + .clkr = {
>>>> + .enable_reg = 0xf058,
>>>> + .enable_mask = BIT(0),
>>>> + .hw.init = &(struct clk_init_data){
>>>> + .name = "gcc_usb3_prim_phy_pipe_clk",
>>>> + .ops = &clk_branch2_ops,
>>>> + },
>>>> + },
>>>> +};
>>>> +
>>>> +static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
>>>> + .halt_reg = 0x6a004,
>>>> + .halt_check = BRANCH_HALT,
>>>> + .hwcg_reg = 0x6a004,
>>>> + .hwcg_bit = 1,
>>>> + .clkr = {
>>>> + .enable_reg = 0x6a004,
>>>> + .enable_mask = BIT(0),
>>>> + .hw.init = &(struct clk_init_data){
>>>> + .name = "gcc_usb_phy_cfg_ahb2phy_clk",
>>>> + .ops = &clk_branch2_ops,
>>>> + },
>>>> + },
>>>> +};
>>>> +
>>>> +/* Leave the clock ON for parent config_noc_clk to be kept enabled */
>>>
>>> There's no parent though... So I guess this means it keeps it enabled
>>> implicitly in hardware?
>>>
>>
>> These are not left enabled, but want to leave them enabled for clients
>> on config NOC.
>
> Sure. It just doesn't make sense to create clk structures and expose
> them in the kernel when we just want to turn the bits on and leave them
> on forever. Why not just do some register writes in probe for this
> driver? Doesn't that work just as well and use less memory?
>
Even if I write these registers during probe, the late init check
'clk_core_is_enabled' would return true and would be turned OFF, that is
the reason for marking them CRITICAL.
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.
--
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 3/3] clk: qcom: Add Global Clock controller (GCC) driver for SC7180
2019-09-25 11:20 ` Taniya Das
@ 2019-09-25 13:03 ` Stephen Boyd
2019-09-27 7:37 ` Taniya Das
0 siblings, 1 reply; 25+ messages in thread
From: Stephen Boyd @ 2019-09-25 13:03 UTC (permalink / raw)
To: Michael Turquette, Taniya Das, robh+dt
Cc: David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, devicetree
Quoting Taniya Das (2019-09-25 04:20:07)
> Hi Stephen,
>
> Please find my comments.
>
> On 9/25/2019 4:42 AM, Stephen Boyd wrote:
> > Quoting Taniya Das (2019-09-23 01:01:11)
> >> Hi Stephen,
> >>
> >> Thanks for your comments.
> >>
> >> On 9/19/2019 3:09 AM, Stephen Boyd wrote:
> >>> Quoting Taniya Das (2019-09-18 02:50:18)
> >>>> diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c
> >>>> new file mode 100644
> >>>> index 000000000000..d47865d5408f
> >>>> --- /dev/null
> >>>> +++ b/drivers/clk/qcom/gcc-sc7180.c
> >>>> + .ops = &clk_branch2_ops,
> >>>> + },
> >>>> + },
> >>>> +};
> >>>> +
> > [...]
> >>>> +static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
> >>>> + .halt_reg = 0x77094,
> >>>> + .halt_check = BRANCH_HALT,
> >>>> + .hwcg_reg = 0x77094,
> >>>> + .hwcg_bit = 1,
> >>>> + .clkr = {
> >>>> + .enable_reg = 0x77094,
> >>>> + .enable_mask = BIT(0),
> >>>> + .hw.init = &(struct clk_init_data){
> >>>> + .name = "gcc_ufs_phy_phy_aux_clk",
> >>>> + .parent_data = &(const struct clk_parent_data){
> >>>> + .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
> >>>> + },
> >>>> + .num_parents = 1,
> >>>> + .flags = CLK_SET_RATE_PARENT,
> >>>> + .ops = &clk_branch2_ops,
> >>>> + },
> >>>> + },
> >>>> +};
> >>>> +
> >>>> +static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
> >>>> + .halt_reg = 0x7701c,
> >>>> + .halt_check = BRANCH_HALT_SKIP,
> >>>
> >>> Again, nobody has fixed the UFS driver to not need to do this halt skip
> >>> check for these clks? It's been over a year.
> >>>
> >>
> >> The UFS_PHY_RX/TX clocks could be left enabled due to certain HW boot
> >> configuration and thus during the late initcall of clk_disable there
> >> could be warnings of "clock stuck ON" in the dmesg. That is the reason
> >> also to use the BRANCH_HALT_SKIP flag.
> >
> > Oh that's bad. Why do the clks stay on when we try to turn them off?
> >
>
> Those could be due to the configuration selected by HW and SW cannot
> override them, so traditionally we have never polled for CLK_OFF for
> these clocks.
Is that the case or just a guess?
>
> >>
> >> I would also check internally for the UFS driver fix you are referring here.
> >
> > Sure. I keep asking but nothing is done :(
> >
> >>
> >>>> + .clkr = {
> >>>> + .enable_reg = 0x7701c,
> >>>> + .enable_mask = BIT(0),
> >>>> + .hw.init = &(struct clk_init_data){
> >>>> + .name = "gcc_ufs_phy_rx_symbol_0_clk",
> >>>> + .ops = &clk_branch2_ops,
> >>>> + },
> >>>> + },
> >>>> +};
> >>>> +
> > [...]
> >>>> +
> >>>> +static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
> >>>> + .halt_reg = 0xf058,
> >>>> + .halt_check = BRANCH_HALT_SKIP,
> >>>
> >>> Why does this need halt_skip?
> >>
> >> This is required as the source is external PHY, so we want to not check
> >> for HALT.
> >
> > This doesn't really answer my question. If the source is an external phy
> > then it should be listed as a clock in the DT binding and the parent
> > should be specified here. Unless something doesn't work because of that?
> >
>
> The USB phy is managed by the USB driver and clock driver is not aware
> if USB driver models the phy as a clock. Thus we do want to keep a
> dependency on the parent and not poll for CLK_ENABLE.
The clk driver should be aware of the USB driver modeling the phy as a
clk. We do that for other phys so what is the difference here?
>
> >>
> >>>
> >>>> + .clkr = {
> >>>> + .enable_reg = 0xf058,
> >>>> + .enable_mask = BIT(0),
> >>>> + .hw.init = &(struct clk_init_data){
> >>>> + .name = "gcc_usb3_prim_phy_pipe_clk",
> >>>> + .ops = &clk_branch2_ops,
> >>>> + },
> >>>> + },
> >>>> +};
> >>>> +
> >>>> +static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
> >>>> + .halt_reg = 0x6a004,
> >>>> + .halt_check = BRANCH_HALT,
> >>>> + .hwcg_reg = 0x6a004,
> >>>> + .hwcg_bit = 1,
> >>>> + .clkr = {
> >>>> + .enable_reg = 0x6a004,
> >>>> + .enable_mask = BIT(0),
> >>>> + .hw.init = &(struct clk_init_data){
> >>>> + .name = "gcc_usb_phy_cfg_ahb2phy_clk",
> >>>> + .ops = &clk_branch2_ops,
> >>>> + },
> >>>> + },
> >>>> +};
> >>>> +
> >>>> +/* Leave the clock ON for parent config_noc_clk to be kept enabled */
> >>>
> >>> There's no parent though... So I guess this means it keeps it enabled
> >>> implicitly in hardware?
> >>>
> >>
> >> These are not left enabled, but want to leave them enabled for clients
> >> on config NOC.
> >
> > Sure. It just doesn't make sense to create clk structures and expose
> > them in the kernel when we just want to turn the bits on and leave them
> > on forever. Why not just do some register writes in probe for this
> > driver? Doesn't that work just as well and use less memory?
> >
>
> Even if I write these registers during probe, the late init check
> 'clk_core_is_enabled' would return true and would be turned OFF, that is
> the reason for marking them CRITICAL.
>
That wouldn't happen if the clks weren't registered though, no?
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 3/3] clk: qcom: Add Global Clock controller (GCC) driver for SC7180
2019-09-25 13:03 ` Stephen Boyd
@ 2019-09-27 7:37 ` Taniya Das
2019-10-01 14:38 ` Stephen Boyd
0 siblings, 1 reply; 25+ messages in thread
From: Taniya Das @ 2019-09-27 7:37 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette, robh+dt
Cc: David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, devicetree
Hi Stephen,
On 9/25/2019 6:33 PM, Stephen Boyd wrote:
> Quoting Taniya Das (2019-09-25 04:20:07)
>> Hi Stephen,
>>
>> Please find my comments.
>>
>> On 9/25/2019 4:42 AM, Stephen Boyd wrote:
>>> Quoting Taniya Das (2019-09-23 01:01:11)
>>>> Hi Stephen,
>>>>
>>>> Thanks for your comments.
>>>>
>>>> On 9/19/2019 3:09 AM, Stephen Boyd wrote:
>>>>> Quoting Taniya Das (2019-09-18 02:50:18)
>>>>>> diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c
>>>>>> new file mode 100644
>>>>>> index 000000000000..d47865d5408f
>>>>>> --- /dev/null
>>>>>> +++ b/drivers/clk/qcom/gcc-sc7180.c
>>>>>> + .ops = &clk_branch2_ops,
>>>>>> + },
>>>>>> + },
>>>>>> +};
>>>>>> +
>>> [...]
>>>>>> +static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
>>>>>> + .halt_reg = 0x77094,
>>>>>> + .halt_check = BRANCH_HALT,
>>>>>> + .hwcg_reg = 0x77094,
>>>>>> + .hwcg_bit = 1,
>>>>>> + .clkr = {
>>>>>> + .enable_reg = 0x77094,
>>>>>> + .enable_mask = BIT(0),
>>>>>> + .hw.init = &(struct clk_init_data){
>>>>>> + .name = "gcc_ufs_phy_phy_aux_clk",
>>>>>> + .parent_data = &(const struct clk_parent_data){
>>>>>> + .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
>>>>>> + },
>>>>>> + .num_parents = 1,
>>>>>> + .flags = CLK_SET_RATE_PARENT,
>>>>>> + .ops = &clk_branch2_ops,
>>>>>> + },
>>>>>> + },
>>>>>> +};
>>>>>> +
>>>>>> +static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
>>>>>> + .halt_reg = 0x7701c,
>>>>>> + .halt_check = BRANCH_HALT_SKIP,
>>>>>
>>>>> Again, nobody has fixed the UFS driver to not need to do this halt skip
>>>>> check for these clks? It's been over a year.
>>>>>
>>>>
>>>> The UFS_PHY_RX/TX clocks could be left enabled due to certain HW boot
>>>> configuration and thus during the late initcall of clk_disable there
>>>> could be warnings of "clock stuck ON" in the dmesg. That is the reason
>>>> also to use the BRANCH_HALT_SKIP flag.
>>>
>>> Oh that's bad. Why do the clks stay on when we try to turn them off?
>>>
>>
>> Those could be due to the configuration selected by HW and SW cannot
>> override them, so traditionally we have never polled for CLK_OFF for
>> these clocks.
>
> Is that the case or just a guess?
>
This is the behavior :).
>>
>>>>
>>>> I would also check internally for the UFS driver fix you are referring here.
>>>
>>> Sure. I keep asking but nothing is done :(
>>>
>>>>
>>>>>> + .clkr = {
>>>>>> + .enable_reg = 0x7701c,
>>>>>> + .enable_mask = BIT(0),
>>>>>> + .hw.init = &(struct clk_init_data){
>>>>>> + .name = "gcc_ufs_phy_rx_symbol_0_clk",
>>>>>> + .ops = &clk_branch2_ops,
>>>>>> + },
>>>>>> + },
>>>>>> +};
>>>>>> +
>>> [...]
>>>>>> +
>>>>>> +static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
>>>>>> + .halt_reg = 0xf058,
>>>>>> + .halt_check = BRANCH_HALT_SKIP,
>>>>>
>>>>> Why does this need halt_skip?
>>>>
>>>> This is required as the source is external PHY, so we want to not check
>>>> for HALT.
>>>
>>> This doesn't really answer my question. If the source is an external phy
>>> then it should be listed as a clock in the DT binding and the parent
>>> should be specified here. Unless something doesn't work because of that?
>>>
>>
>> The USB phy is managed by the USB driver and clock driver is not aware
>> if USB driver models the phy as a clock. Thus we do want to keep a
>> dependency on the parent and not poll for CLK_ENABLE.
>
> The clk driver should be aware of the USB driver modeling the phy as a
> clk. We do that for other phys so what is the difference here?
>
Let me check with the USB team, but could we keep them for now?
>>
>>>>
>>>>>
>>>>>> + .clkr = {
>>>>>> + .enable_reg = 0xf058,
>>>>>> + .enable_mask = BIT(0),
>>>>>> + .hw.init = &(struct clk_init_data){
>>>>>> + .name = "gcc_usb3_prim_phy_pipe_clk",
>>>>>> + .ops = &clk_branch2_ops,
>>>>>> + },
>>>>>> + },
>>>>>> +};
>>>>>> +
>>>>>> +static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
>>>>>> + .halt_reg = 0x6a004,
>>>>>> + .halt_check = BRANCH_HALT,
>>>>>> + .hwcg_reg = 0x6a004,
>>>>>> + .hwcg_bit = 1,
>>>>>> + .clkr = {
>>>>>> + .enable_reg = 0x6a004,
>>>>>> + .enable_mask = BIT(0),
>>>>>> + .hw.init = &(struct clk_init_data){
>>>>>> + .name = "gcc_usb_phy_cfg_ahb2phy_clk",
>>>>>> + .ops = &clk_branch2_ops,
>>>>>> + },
>>>>>> + },
>>>>>> +};
>>>>>> +
>>>>>> +/* Leave the clock ON for parent config_noc_clk to be kept enabled */
>>>>>
>>>>> There's no parent though... So I guess this means it keeps it enabled
>>>>> implicitly in hardware?
>>>>>
>>>>
>>>> These are not left enabled, but want to leave them enabled for clients
>>>> on config NOC.
>>>
>>> Sure. It just doesn't make sense to create clk structures and expose
>>> them in the kernel when we just want to turn the bits on and leave them
>>> on forever. Why not just do some register writes in probe for this
>>> driver? Doesn't that work just as well and use less memory?
>>>
>>
>> Even if I write these registers during probe, the late init check
>> 'clk_core_is_enabled' would return true and would be turned OFF, that is
>> the reason for marking them CRITICAL.
>>
>
> That wouldn't happen if the clks weren't registered though, no?
>
I want to keep these clock CRITICAL and registered for now, but we
should be able to revisit/clean them up later.
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.
--
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: clk: qcom: Add YAML schemas for the GCC clock bindings
2019-09-18 9:50 ` [PATCH v3 2/3] dt-bindings: clk: qcom: Add YAML schemas for the GCC clock bindings Taniya Das
2019-09-18 17:52 ` Matthias Kaehlcke
@ 2019-09-27 17:27 ` Rob Herring
2019-10-14 10:16 ` Taniya Das
[not found] ` <20190918212614.448FC20882@mail.kernel.org>
2 siblings, 1 reply; 25+ messages in thread
From: Rob Herring @ 2019-09-27 17:27 UTC (permalink / raw)
To: Taniya Das
Cc: Stephen Boyd, Michael Turquette ,
David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, devicetree
On Wed, Sep 18, 2019 at 03:20:17PM +0530, Taniya Das wrote:
> The GCC clock provider have a bunch of generic properties that
> are needed in a device tree. Add a YAML schemas for those. Also update
> the compatible for SC7180 along with example for clocks & clock-names.
I'm fine fixing errors in the conversion, but adding a new chip should
be separate patch.
>
> Signed-off-by: Taniya Das <tdas@codeaurora.org>
> ---
> .../devicetree/bindings/clock/qcom,gcc.txt | 94 -----------
> .../devicetree/bindings/clock/qcom,gcc.yaml | 157 ++++++++++++++++++
> include/dt-bindings/clock/qcom,gcc-sc7180.h | 155 +++++++++++++++++
> 3 files changed, 312 insertions(+), 94 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc.txt
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc.yaml
> create mode 100644 include/dt-bindings/clock/qcom,gcc-sc7180.h
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
> deleted file mode 100644
> index d14362ad4132..000000000000
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
> +++ /dev/null
> @@ -1,94 +0,0 @@
> -Qualcomm Global Clock & Reset Controller Binding
> -------------------------------------------------
> -
> -Required properties :
> -- compatible : shall contain only one of the following:
> -
> - "qcom,gcc-apq8064"
> - "qcom,gcc-apq8084"
> - "qcom,gcc-ipq8064"
> - "qcom,gcc-ipq4019"
> - "qcom,gcc-ipq8074"
> - "qcom,gcc-msm8660"
> - "qcom,gcc-msm8916"
> - "qcom,gcc-msm8960"
> - "qcom,gcc-msm8974"
> - "qcom,gcc-msm8974pro"
> - "qcom,gcc-msm8974pro-ac"
> - "qcom,gcc-msm8994"
> - "qcom,gcc-msm8996"
> - "qcom,gcc-msm8998"
> - "qcom,gcc-mdm9615"
> - "qcom,gcc-qcs404"
> - "qcom,gcc-sdm630"
> - "qcom,gcc-sdm660"
> - "qcom,gcc-sdm845"
> - "qcom,gcc-sm8150"
> -
> -- reg : shall contain base register location and length
> -- #clock-cells : shall contain 1
> -- #reset-cells : shall contain 1
> -
> -Optional properties :
> -- #power-domain-cells : shall contain 1
> -- Qualcomm TSENS (thermal sensor device) on some devices can
> -be part of GCC and hence the TSENS properties can also be
> -part of the GCC/clock-controller node.
> -For more details on the TSENS properties please refer
> -Documentation/devicetree/bindings/thermal/qcom-tsens.txt
> -- protected-clocks : Protected clock specifier list as per common clock
> - binding.
> -
> -For SM8150 only:
> - - clocks: a list of phandles and clock-specifier pairs,
> - one for each entry in clock-names.
> - - clock-names: "bi_tcxo" (required)
> - "sleep_clk" (optional)
> - "aud_ref_clock" (optional)
> -
> -Example:
> - clock-controller@900000 {
> - compatible = "qcom,gcc-msm8960";
> - reg = <0x900000 0x4000>;
> - #clock-cells = <1>;
> - #reset-cells = <1>;
> - #power-domain-cells = <1>;
> - };
> -
> -Example of GCC with TSENS properties:
> - clock-controller@900000 {
> - compatible = "qcom,gcc-apq8064";
> - reg = <0x00900000 0x4000>;
> - nvmem-cells = <&tsens_calib>, <&tsens_backup>;
> - nvmem-cell-names = "calib", "calib_backup";
> - #clock-cells = <1>;
> - #reset-cells = <1>;
> - #thermal-sensor-cells = <1>;
> - };
> -
> -Example of GCC with protected-clocks properties:
> - clock-controller@100000 {
> - compatible = "qcom,gcc-sdm845";
> - reg = <0x100000 0x1f0000>;
> - #clock-cells = <1>;
> - #reset-cells = <1>;
> - #power-domain-cells = <1>;
> - protected-clocks = <GCC_QSPI_CORE_CLK>,
> - <GCC_QSPI_CORE_CLK_SRC>,
> - <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
> - <GCC_LPASS_Q6_AXI_CLK>,
> - <GCC_LPASS_SWAY_CLK>;
> - };
> -
> -Example of GCC with clocks
> - gcc: clock-controller@100000 {
> - compatible = "qcom,gcc-sm8150";
> - reg = <0x00100000 0x1f0000>;
> - #clock-cells = <1>;
> - #reset-cells = <1>;
> - #power-domain-cells = <1>;
> - clock-names = "bi_tcxo",
> - "sleep_clk";
> - clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
> - <&sleep_clk>;
> - };
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
> new file mode 100644
> index 000000000000..056a7977c458
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
> @@ -0,0 +1,157 @@
> +# SPDX-License-Identifier: GPL-2.0
As all the authors where QCom on the old file, can you relicense to
(GPL-2.0-only OR BSD-2-Clause)?
And please, can all of Qcom and the Linaro QCom landing team get aligned
on this.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,gcc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Global Clock & Reset Controller Binding
> +
> +maintainers:
> + - Stephen Boyd <sboyd@kernel.org>
> +
> +properties:
> + "#clock-cells":
> + const: 1
> +
> + "#reset-cells":
> + const: 1
> +
> + reg:
> + maxItems: 1
> +
> + compatible :
> + enum:
> + - qcom,gcc-apq8064
> + - qcom,gcc-apq8084
> + - qcom,gcc-ipq8064
> + - qcom,gcc-ipq4019
> + - qcom,gcc-ipq8074
> + - qcom,gcc-msm8660
> + - qcom,gcc-msm8916
> + - qcom,gcc-msm8960
> + - qcom,gcc-msm8974
> + - qcom,gcc-msm8974pro
> + - qcom,gcc-msm8974pro-ac
> + - qcom,gcc-msm8994
> + - qcom,gcc-msm8996
> + - qcom,gcc-msm8998
> + - qcom,gcc-mdm9615
> + - qcom,gcc-qcs404
> + - qcom,gcc-sdm630
> + - qcom,gcc-sdm660
> + - qcom,gcc-sdm845
> + - qcom,gcc-sm8150
> + - qcom,gcc-sc7180
> +
> + clocks:
> + minItems: 1
> + maxItems: 3
> + items:
> + - description: Board XO source
> + - description: Board active XO source
> + - description: Sleep clock source(optional)
> +
> + clock-names:
> + minItems: 1
> + maxItems: 3
> + items:
> + - const: bi_tcxo
> + - const: bi_tcxo_ao
> + - const: sleep_clk
> +
> + nvmem-cells:
> + minItems: 1
> + maxItems: 2
> + description:
> + Qualcomm TSENS (thermal sensor device) on some devices can
> + be part of GCC and hence the TSENS properties can also be part
> + of the GCC/clock-controller node.
> + For more details on the TSENS properties please refer
> + Documentation/devicetree/bindings/thermal/qcom-tsens.txt
> +
> + nvmem-cell-names:
> + minItems: 1
> + maxItems: 2
> + description:
> + Names for each nvmem-cells specified.
> + items:
> + - const: calib
> + - const: calib_backup
> +
> + "#thermal-sensor-cells":
> + const: 1
>
> + "#power-domain-cells":
> + const: 1
> +
> + protected-clocks:
> + description:
> + Protected clock specifier list as per common clock binding
> +
> +required:
> + - "#clock-cells"
> + - "#reset-cells"
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> +
> +examples:
> + - |
> + // Example:
> + clock-controller@900000 {
> + compatible = "qcom,gcc-msm8960";
> + reg = <0x900000 0x4000>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
Does this pass 'make dt_binding_check' as 'clocks' is required.
> + };
> +
> +
> + - |
> + // Example of GCC with TSENS properties:
> + clock-controller@900000 {
> + compatible = "qcom,gcc-apq8064";
> + reg = <0x00900000 0x4000>;
> + nvmem-cells = <&tsens_calib>, <&tsens_backup>;
> + nvmem-cell-names = "calib", "calib_backup";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #thermal-sensor-cells = <1>;
> + };
> +
> + - |
> + //Example of GCC with protected-clocks properties:
> + clock-controller@100000 {
> + compatible = "qcom,gcc-sdm845";
> + reg = <0x100000 0x1f0000>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + protected-clocks = <187>, <188>, <189>, <190>, <191>;
> + };
> +
> + - |
> + //Example of GCC with clock node properties for SM8150:
> + clock-controller@100000 {
> + compatible = "qcom,gcc-sm8150";
> + reg = <0x00100000 0x1f0000>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + clocks = <&rpmhcc 0>, <&rpmhcc 1>, <&sleep_clk>;
> + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
> + };
> +
> + - |
> + //Example of GCC with clock nodes properties:
> + clock-controller@100000 {
> + compatible = "qcom,gcc-sc7180";
> + reg = <0x100000 0x1f0000>;
> + clocks = <&rpmhcc 0>, <&rpmhcc 1>;
> + clock-names = "bi_tcxo", "bi_tcxo_ao";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> +...
> diff --git a/include/dt-bindings/clock/qcom,gcc-sc7180.h b/include/dt-bindings/clock/qcom,gcc-sc7180.h
> new file mode 100644
> index 000000000000..d76b061f6a4e
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,gcc-sc7180.h
> @@ -0,0 +1,155 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SC7180_H
> +#define _DT_BINDINGS_CLK_QCOM_GCC_SC7180_H
> +
> +/* GCC clocks */
> +#define GCC_GPLL0_MAIN_DIV_CDIV 0
> +#define GPLL0 1
> +#define GPLL0_OUT_EVEN 2
> +#define GPLL1 3
> +#define GPLL4 4
> +#define GPLL6 5
> +#define GPLL7 6
> +#define GCC_AGGRE_UFS_PHY_AXI_CLK 7
> +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 8
> +#define GCC_BOOT_ROM_AHB_CLK 9
> +#define GCC_CAMERA_AHB_CLK 10
> +#define GCC_CAMERA_HF_AXI_CLK 11
> +#define GCC_CAMERA_THROTTLE_HF_AXI_CLK 12
> +#define GCC_CAMERA_XO_CLK 13
> +#define GCC_CE1_AHB_CLK 14
> +#define GCC_CE1_AXI_CLK 15
> +#define GCC_CE1_CLK 16
> +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 17
> +#define GCC_CPUSS_AHB_CLK 18
> +#define GCC_CPUSS_AHB_CLK_SRC 19
> +#define GCC_CPUSS_GNOC_CLK 20
> +#define GCC_CPUSS_RBCPR_CLK 21
> +#define GCC_DDRSS_GPU_AXI_CLK 22
> +#define GCC_DISP_AHB_CLK 23
> +#define GCC_DISP_GPLL0_CLK_SRC 24
> +#define GCC_DISP_GPLL0_DIV_CLK_SRC 25
> +#define GCC_DISP_HF_AXI_CLK 26
> +#define GCC_DISP_THROTTLE_HF_AXI_CLK 27
> +#define GCC_DISP_XO_CLK 28
> +#define GCC_GP1_CLK 29
> +#define GCC_GP1_CLK_SRC 30
> +#define GCC_GP2_CLK 31
> +#define GCC_GP2_CLK_SRC 32
> +#define GCC_GP3_CLK 33
> +#define GCC_GP3_CLK_SRC 34
> +#define GCC_GPU_CFG_AHB_CLK 35
> +#define GCC_GPU_GPLL0_CLK_SRC 36
> +#define GCC_GPU_GPLL0_DIV_CLK_SRC 37
> +#define GCC_GPU_MEMNOC_GFX_CLK 38
> +#define GCC_GPU_SNOC_DVM_GFX_CLK 39
> +#define GCC_NPU_AXI_CLK 40
> +#define GCC_NPU_BWMON_AXI_CLK 41
> +#define GCC_NPU_BWMON_DMA_CFG_AHB_CLK 42
> +#define GCC_NPU_BWMON_DSP_CFG_AHB_CLK 43
> +#define GCC_NPU_CFG_AHB_CLK 44
> +#define GCC_NPU_DMA_CLK 45
> +#define GCC_NPU_GPLL0_CLK_SRC 46
> +#define GCC_NPU_GPLL0_DIV_CLK_SRC 47
> +#define GCC_PDM2_CLK 48
> +#define GCC_PDM2_CLK_SRC 49
> +#define GCC_PDM_AHB_CLK 50
> +#define GCC_PDM_XO4_CLK 51
> +#define GCC_PRNG_AHB_CLK 52
> +#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 53
> +#define GCC_QSPI_CORE_CLK 54
> +#define GCC_QSPI_CORE_CLK_SRC 55
> +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 56
> +#define GCC_QUPV3_WRAP0_CORE_CLK 57
> +#define GCC_QUPV3_WRAP0_S0_CLK 58
> +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 59
> +#define GCC_QUPV3_WRAP0_S1_CLK 60
> +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 61
> +#define GCC_QUPV3_WRAP0_S2_CLK 62
> +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 63
> +#define GCC_QUPV3_WRAP0_S3_CLK 64
> +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 65
> +#define GCC_QUPV3_WRAP0_S4_CLK 66
> +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 67
> +#define GCC_QUPV3_WRAP0_S5_CLK 68
> +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 69
> +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 70
> +#define GCC_QUPV3_WRAP1_CORE_CLK 71
> +#define GCC_QUPV3_WRAP1_S0_CLK 72
> +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 73
> +#define GCC_QUPV3_WRAP1_S1_CLK 74
> +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 75
> +#define GCC_QUPV3_WRAP1_S2_CLK 76
> +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 77
> +#define GCC_QUPV3_WRAP1_S3_CLK 78
> +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 79
> +#define GCC_QUPV3_WRAP1_S4_CLK 80
> +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 81
> +#define GCC_QUPV3_WRAP1_S5_CLK 82
> +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 83
> +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 84
> +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 85
> +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 86
> +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 87
> +#define GCC_SDCC1_AHB_CLK 88
> +#define GCC_SDCC1_APPS_CLK 89
> +#define GCC_SDCC1_APPS_CLK_SRC 90
> +#define GCC_SDCC1_ICE_CORE_CLK 91
> +#define GCC_SDCC1_ICE_CORE_CLK_SRC 92
> +#define GCC_SDCC2_AHB_CLK 93
> +#define GCC_SDCC2_APPS_CLK 94
> +#define GCC_SDCC2_APPS_CLK_SRC 95
> +#define GCC_SYS_NOC_CPUSS_AHB_CLK 96
> +#define GCC_UFS_MEM_CLKREF_CLK 97
> +#define GCC_UFS_PHY_AHB_CLK 98
> +#define GCC_UFS_PHY_AXI_CLK 99
> +#define GCC_UFS_PHY_AXI_CLK_SRC 100
> +#define GCC_UFS_PHY_ICE_CORE_CLK 101
> +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 102
> +#define GCC_UFS_PHY_PHY_AUX_CLK 103
> +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 104
> +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 105
> +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 106
> +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 107
> +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 108
> +#define GCC_USB30_PRIM_MASTER_CLK 109
> +#define GCC_USB30_PRIM_MASTER_CLK_SRC 110
> +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 111
> +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 112
> +#define GCC_USB30_PRIM_SLEEP_CLK 113
> +#define GCC_USB3_PRIM_CLKREF_CLK 114
> +#define GCC_USB3_PRIM_PHY_AUX_CLK 115
> +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 116
> +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 117
> +#define GCC_USB3_PRIM_PHY_PIPE_CLK 118
> +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 119
> +#define GCC_VIDEO_AHB_CLK 120
> +#define GCC_VIDEO_AXI_CLK 121
> +#define GCC_VIDEO_GPLL0_DIV_CLK_SRC 122
> +#define GCC_VIDEO_THROTTLE_AXI_CLK 123
> +#define GCC_VIDEO_XO_CLK 124
> +
> +/* GCC resets */
> +#define GCC_QUSB2PHY_PRIM_BCR 0
> +#define GCC_QUSB2PHY_SEC_BCR 1
> +#define GCC_UFS_PHY_BCR 2
> +#define GCC_USB30_PRIM_BCR 3
> +#define GCC_USB3_DP_PHY_PRIM_BCR 4
> +#define GCC_USB3_DP_PHY_SEC_BCR 5
> +#define GCC_USB3_PHY_PRIM_BCR 6
> +#define GCC_USB3_PHY_SEC_BCR 7
> +#define GCC_USB3PHY_PHY_PRIM_BCR 8
> +#define GCC_USB3PHY_PHY_SEC_BCR 9
> +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 10
> +
> +/* GCC GDSCRs */
> +#define UFS_PHY_GDSC 0
> +#define USB30_PRIM_GDSC 1
> +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 2
> +#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 3
> +
> +#endif
> --
> Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
> of the Code Aurora Forum, hosted by the Linux Foundation.
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 3/3] clk: qcom: Add Global Clock controller (GCC) driver for SC7180
2019-09-27 7:37 ` Taniya Das
@ 2019-10-01 14:38 ` Stephen Boyd
2019-10-03 10:31 ` Taniya Das
0 siblings, 1 reply; 25+ messages in thread
From: Stephen Boyd @ 2019-10-01 14:38 UTC (permalink / raw)
To: Michael Turquette, Taniya Das, robh+dt
Cc: David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, devicetree
Quoting Taniya Das (2019-09-27 00:37:57)
> Hi Stephen,
>
> On 9/25/2019 6:33 PM, Stephen Boyd wrote:
> > Quoting Taniya Das (2019-09-25 04:20:07)
> >> Hi Stephen,
> >>
> >> Please find my comments.
> >>
> >> On 9/25/2019 4:42 AM, Stephen Boyd wrote:
> >>> Quoting Taniya Das (2019-09-23 01:01:11)
> >>>> Hi Stephen,
> >>>>
> >>>> Thanks for your comments.
> >>>>
> >>>> On 9/19/2019 3:09 AM, Stephen Boyd wrote:
> >>>>> Quoting Taniya Das (2019-09-18 02:50:18)
> >>>>>> diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c
> >>>>>> new file mode 100644
> >>>>>> index 000000000000..d47865d5408f
> >>>>>> --- /dev/null
> >>>>>> +++ b/drivers/clk/qcom/gcc-sc7180.c
> >>>>>> + .ops = &clk_branch2_ops,
> >>>>>> + },
> >>>>>> + },
> >>>>>> +};
> >>>>>> +
> >>> [...]
> >>>>>> +static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
> >>>>>> + .halt_reg = 0x77094,
> >>>>>> + .halt_check = BRANCH_HALT,
> >>>>>> + .hwcg_reg = 0x77094,
> >>>>>> + .hwcg_bit = 1,
> >>>>>> + .clkr = {
> >>>>>> + .enable_reg = 0x77094,
> >>>>>> + .enable_mask = BIT(0),
> >>>>>> + .hw.init = &(struct clk_init_data){
> >>>>>> + .name = "gcc_ufs_phy_phy_aux_clk",
> >>>>>> + .parent_data = &(const struct clk_parent_data){
> >>>>>> + .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
> >>>>>> + },
> >>>>>> + .num_parents = 1,
> >>>>>> + .flags = CLK_SET_RATE_PARENT,
> >>>>>> + .ops = &clk_branch2_ops,
> >>>>>> + },
> >>>>>> + },
> >>>>>> +};
> >>>>>> +
> >>>>>> +static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
> >>>>>> + .halt_reg = 0x7701c,
> >>>>>> + .halt_check = BRANCH_HALT_SKIP,
> >>>>>
> >>>>> Again, nobody has fixed the UFS driver to not need to do this halt skip
> >>>>> check for these clks? It's been over a year.
> >>>>>
> >>>>
> >>>> The UFS_PHY_RX/TX clocks could be left enabled due to certain HW boot
> >>>> configuration and thus during the late initcall of clk_disable there
> >>>> could be warnings of "clock stuck ON" in the dmesg. That is the reason
> >>>> also to use the BRANCH_HALT_SKIP flag.
> >>>
> >>> Oh that's bad. Why do the clks stay on when we try to turn them off?
> >>>
> >>
> >> Those could be due to the configuration selected by HW and SW cannot
> >> override them, so traditionally we have never polled for CLK_OFF for
> >> these clocks.
> >
> > Is that the case or just a guess?
> >
>
> This is the behavior :).
Ok. It's the same as sdm845 so I guess it's OK.
>
> >>
> >>>>
> >>>> I would also check internally for the UFS driver fix you are referring here.
> >>>
> >>> Sure. I keep asking but nothing is done :(
> >>>
> >>>>
> >>>>>> + .clkr = {
> >>>>>> + .enable_reg = 0x7701c,
> >>>>>> + .enable_mask = BIT(0),
> >>>>>> + .hw.init = &(struct clk_init_data){
> >>>>>> + .name = "gcc_ufs_phy_rx_symbol_0_clk",
> >>>>>> + .ops = &clk_branch2_ops,
> >>>>>> + },
> >>>>>> + },
> >>>>>> +};
> >>>>>> +
> >>> [...]
> >>>>>> +
> >>>>>> +static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
> >>>>>> + .halt_reg = 0xf058,
> >>>>>> + .halt_check = BRANCH_HALT_SKIP,
> >>>>>
> >>>>> Why does this need halt_skip?
> >>>>
> >>>> This is required as the source is external PHY, so we want to not check
> >>>> for HALT.
> >>>
> >>> This doesn't really answer my question. If the source is an external phy
> >>> then it should be listed as a clock in the DT binding and the parent
> >>> should be specified here. Unless something doesn't work because of that?
> >>>
> >>
> >> The USB phy is managed by the USB driver and clock driver is not aware
> >> if USB driver models the phy as a clock. Thus we do want to keep a
> >> dependency on the parent and not poll for CLK_ENABLE.
> >
> > The clk driver should be aware of the USB driver modeling the phy as a
> > clk. We do that for other phys so what is the difference here?
> >
>
> Let me check with the USB team, but could we keep them for now?
Ok. It's also the same as sdm845 so I guess it's OK. Would be nice to
properly model it though so we can be certain the clk is actually
enabled.
>
> >>
> >>>>
> >>>>>
> >>>>>> + .clkr = {
> >>>>>> + .enable_reg = 0xf058,
> >>>>>> + .enable_mask = BIT(0),
> >>>>>> + .hw.init = &(struct clk_init_data){
> >>>>>> + .name = "gcc_usb3_prim_phy_pipe_clk",
> >>>>>> + .ops = &clk_branch2_ops,
> >>>>>> + },
> >>>>>> + },
> >>>>>> +};
> >>>>>> +
> >>>>>> +static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
> >>>>>> + .halt_reg = 0x6a004,
> >>>>>> + .halt_check = BRANCH_HALT,
> >>>>>> + .hwcg_reg = 0x6a004,
> >>>>>> + .hwcg_bit = 1,
> >>>>>> + .clkr = {
> >>>>>> + .enable_reg = 0x6a004,
> >>>>>> + .enable_mask = BIT(0),
> >>>>>> + .hw.init = &(struct clk_init_data){
> >>>>>> + .name = "gcc_usb_phy_cfg_ahb2phy_clk",
> >>>>>> + .ops = &clk_branch2_ops,
> >>>>>> + },
> >>>>>> + },
> >>>>>> +};
> >>>>>> +
> >>>>>> +/* Leave the clock ON for parent config_noc_clk to be kept enabled */
> >>>>>
> >>>>> There's no parent though... So I guess this means it keeps it enabled
> >>>>> implicitly in hardware?
> >>>>>
> >>>>
> >>>> These are not left enabled, but want to leave them enabled for clients
> >>>> on config NOC.
> >>>
> >>> Sure. It just doesn't make sense to create clk structures and expose
> >>> them in the kernel when we just want to turn the bits on and leave them
> >>> on forever. Why not just do some register writes in probe for this
> >>> driver? Doesn't that work just as well and use less memory?
> >>>
> >>
> >> Even if I write these registers during probe, the late init check
> >> 'clk_core_is_enabled' would return true and would be turned OFF, that is
> >> the reason for marking them CRITICAL.
> >>
> >
> > That wouldn't happen if the clks weren't registered though, no?
> >
>
> I want to keep these clock CRITICAL and registered for now, but we
> should be able to revisit/clean them up later.
>
Why do you want to keep them critical and registered? I'm suggesting
that any clk that is marked critical and doesn't have a parent should
instead become a register write in probe to turn the clk on.
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 3/3] clk: qcom: Add Global Clock controller (GCC) driver for SC7180
2019-10-01 14:38 ` Stephen Boyd
@ 2019-10-03 10:31 ` Taniya Das
2019-10-03 16:01 ` Stephen Boyd
0 siblings, 1 reply; 25+ messages in thread
From: Taniya Das @ 2019-10-03 10:31 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette, robh+dt
Cc: David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, devicetree
Hi Stephen,
On 10/1/2019 8:08 PM, Stephen Boyd wrote:
> Quoting Taniya Das (2019-09-27 00:37:57)
>> Hi Stephen,
>>
>> On 9/25/2019 6:33 PM, Stephen Boyd wrote:
>>> Quoting Taniya Das (2019-09-25 04:20:07)
>>>> Hi Stephen,
>>>>
>>>> Please find my comments.
>>>>
>>>> On 9/25/2019 4:42 AM, Stephen Boyd wrote:
>>>>> Quoting Taniya Das (2019-09-23 01:01:11)
>>>>>> Hi Stephen,
>>>>>>
>>>>>> Thanks for your comments.
>>>>>>
>>>>>> On 9/19/2019 3:09 AM, Stephen Boyd wrote:
>>>>>>> Quoting Taniya Das (2019-09-18 02:50:18)
>>>>>>>> diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c
>>>>>>>> new file mode 100644
>>>>>>>> index 000000000000..d47865d5408f
>>>>>>>> --- /dev/null
>>>>>>>> +++ b/drivers/clk/qcom/gcc-sc7180.c
>>>>>>>> + .ops = &clk_branch2_ops,
>>>>>>>> + },
>>>>>>>> + },
>>>>>>>> +};
>>>>>>>> +
>>>>> [...]
>>>>>>>> +static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
>>>>>>>> + .halt_reg = 0x77094,
>>>>>>>> + .halt_check = BRANCH_HALT,
>>>>>>>> + .hwcg_reg = 0x77094,
>>>>>>>> + .hwcg_bit = 1,
>>>>>>>> + .clkr = {
>>>>>>>> + .enable_reg = 0x77094,
>>>>>>>> + .enable_mask = BIT(0),
>>>>>>>> + .hw.init = &(struct clk_init_data){
>>>>>>>> + .name = "gcc_ufs_phy_phy_aux_clk",
>>>>>>>> + .parent_data = &(const struct clk_parent_data){
>>>>>>>> + .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
>>>>>>>> + },
>>>>>>>> + .num_parents = 1,
>>>>>>>> + .flags = CLK_SET_RATE_PARENT,
>>>>>>>> + .ops = &clk_branch2_ops,
>>>>>>>> + },
>>>>>>>> + },
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
>>>>>>>> + .halt_reg = 0x7701c,
>>>>>>>> + .halt_check = BRANCH_HALT_SKIP,
>>>>>>>
>>>>>>> Again, nobody has fixed the UFS driver to not need to do this halt skip
>>>>>>> check for these clks? It's been over a year.
>>>>>>>
>>>>>>
>>>>>> The UFS_PHY_RX/TX clocks could be left enabled due to certain HW boot
>>>>>> configuration and thus during the late initcall of clk_disable there
>>>>>> could be warnings of "clock stuck ON" in the dmesg. That is the reason
>>>>>> also to use the BRANCH_HALT_SKIP flag.
>>>>>
>>>>> Oh that's bad. Why do the clks stay on when we try to turn them off?
>>>>>
>>>>
>>>> Those could be due to the configuration selected by HW and SW cannot
>>>> override them, so traditionally we have never polled for CLK_OFF for
>>>> these clocks.
>>>
>>> Is that the case or just a guess?
>>>
>>
>> This is the behavior :).
>
> Ok. It's the same as sdm845 so I guess it's OK.
>
Thanks.
>>
>>>>
>>>>>>
>>>>>> I would also check internally for the UFS driver fix you are referring here.
>>>>>
>>>>> Sure. I keep asking but nothing is done :(
>>>>>
>>>>>>
>>>>>>>> + .clkr = {
>>>>>>>> + .enable_reg = 0x7701c,
>>>>>>>> + .enable_mask = BIT(0),
>>>>>>>> + .hw.init = &(struct clk_init_data){
>>>>>>>> + .name = "gcc_ufs_phy_rx_symbol_0_clk",
>>>>>>>> + .ops = &clk_branch2_ops,
>>>>>>>> + },
>>>>>>>> + },
>>>>>>>> +};
>>>>>>>> +
>>>>> [...]
>>>>>>>> +
>>>>>>>> +static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
>>>>>>>> + .halt_reg = 0xf058,
>>>>>>>> + .halt_check = BRANCH_HALT_SKIP,
>>>>>>>
>>>>>>> Why does this need halt_skip?
>>>>>>
>>>>>> This is required as the source is external PHY, so we want to not check
>>>>>> for HALT.
>>>>>
>>>>> This doesn't really answer my question. If the source is an external phy
>>>>> then it should be listed as a clock in the DT binding and the parent
>>>>> should be specified here. Unless something doesn't work because of that?
>>>>>
>>>>
>>>> The USB phy is managed by the USB driver and clock driver is not aware
>>>> if USB driver models the phy as a clock. Thus we do want to keep a
>>>> dependency on the parent and not poll for CLK_ENABLE.
>>>
>>> The clk driver should be aware of the USB driver modeling the phy as a
>>> clk. We do that for other phys so what is the difference here?
>>>
>>
>> Let me check with the USB team, but could we keep them for now?
>
> Ok. It's also the same as sdm845 so I guess it's OK. Would be nice to
> properly model it though so we can be certain the clk is actually
> enabled.
>
I am going to follow it up and close on this.
>>
>>>>
>>>>>>
>>>>>>>
>>>>>>>> + .clkr = {
>>>>>>>> + .enable_reg = 0xf058,
>>>>>>>> + .enable_mask = BIT(0),
>>>>>>>> + .hw.init = &(struct clk_init_data){
>>>>>>>> + .name = "gcc_usb3_prim_phy_pipe_clk",
>>>>>>>> + .ops = &clk_branch2_ops,
>>>>>>>> + },
>>>>>>>> + },
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
>>>>>>>> + .halt_reg = 0x6a004,
>>>>>>>> + .halt_check = BRANCH_HALT,
>>>>>>>> + .hwcg_reg = 0x6a004,
>>>>>>>> + .hwcg_bit = 1,
>>>>>>>> + .clkr = {
>>>>>>>> + .enable_reg = 0x6a004,
>>>>>>>> + .enable_mask = BIT(0),
>>>>>>>> + .hw.init = &(struct clk_init_data){
>>>>>>>> + .name = "gcc_usb_phy_cfg_ahb2phy_clk",
>>>>>>>> + .ops = &clk_branch2_ops,
>>>>>>>> + },
>>>>>>>> + },
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +/* Leave the clock ON for parent config_noc_clk to be kept enabled */
>>>>>>>
>>>>>>> There's no parent though... So I guess this means it keeps it enabled
>>>>>>> implicitly in hardware?
>>>>>>>
>>>>>>
>>>>>> These are not left enabled, but want to leave them enabled for clients
>>>>>> on config NOC.
>>>>>
>>>>> Sure. It just doesn't make sense to create clk structures and expose
>>>>> them in the kernel when we just want to turn the bits on and leave them
>>>>> on forever. Why not just do some register writes in probe for this
>>>>> driver? Doesn't that work just as well and use less memory?
>>>>>
>>>>
>>>> Even if I write these registers during probe, the late init check
>>>> 'clk_core_is_enabled' would return true and would be turned OFF, that is
>>>> the reason for marking them CRITICAL.
>>>>
>>>
>>> That wouldn't happen if the clks weren't registered though, no?
>>>
>>
>> I want to keep these clock CRITICAL and registered for now, but we
>> should be able to revisit/clean them up later.
>>
>
> Why do you want to keep them critical and registered? I'm suggesting
> that any clk that is marked critical and doesn't have a parent should
> instead become a register write in probe to turn the clk on.
>
Sure, let me do a one-time enable from probe for the clocks which
doesn't have a parent.
But I would now have to educate the clients of these clocks to remove
using them.
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.
--
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 3/3] clk: qcom: Add Global Clock controller (GCC) driver for SC7180
2019-10-03 10:31 ` Taniya Das
@ 2019-10-03 16:01 ` Stephen Boyd
2019-10-04 17:39 ` Taniya Das
0 siblings, 1 reply; 25+ messages in thread
From: Stephen Boyd @ 2019-10-03 16:01 UTC (permalink / raw)
To: Michael Turquette, Taniya Das, robh+dt
Cc: David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, devicetree
Quoting Taniya Das (2019-10-03 03:31:15)
> Hi Stephen,
>
> On 10/1/2019 8:08 PM, Stephen Boyd wrote:
> >
> > Why do you want to keep them critical and registered? I'm suggesting
> > that any clk that is marked critical and doesn't have a parent should
> > instead become a register write in probe to turn the clk on.
> >
> Sure, let me do a one-time enable from probe for the clocks which
> doesn't have a parent.
> But I would now have to educate the clients of these clocks to remove
> using them.
>
If anyone is using these clks we can return NULL from the provider for
the specifier so that we indicate there isn't support for them in the
kernel. At least I hope that code path still works given all the recent
changes to clk_get().
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 3/3] clk: qcom: Add Global Clock controller (GCC) driver for SC7180
2019-10-03 16:01 ` Stephen Boyd
@ 2019-10-04 17:39 ` Taniya Das
2019-10-04 23:20 ` Stephen Boyd
0 siblings, 1 reply; 25+ messages in thread
From: Taniya Das @ 2019-10-04 17:39 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette, robh+dt
Cc: David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, devicetree
Hi Stephen,
On 10/3/2019 9:31 PM, Stephen Boyd wrote:
> Quoting Taniya Das (2019-10-03 03:31:15)
>> Hi Stephen,
>>
>> On 10/1/2019 8:08 PM, Stephen Boyd wrote:
>>>
>>> Why do you want to keep them critical and registered? I'm suggesting
>>> that any clk that is marked critical and doesn't have a parent should
>>> instead become a register write in probe to turn the clk on.
>>>
>> Sure, let me do a one-time enable from probe for the clocks which
>> doesn't have a parent.
>> But I would now have to educate the clients of these clocks to remove
>> using them.
>>
>
> If anyone is using these clks we can return NULL from the provider for
> the specifier so that we indicate there isn't support for them in the
> kernel. At least I hope that code path still works given all the recent
> changes to clk_get().
>
Could you please confirm if you are referring to update the below?
--- a/drivers/clk/qcom/common.c
+++ b/drivers/clk/qcom/common.c
@@ -218,7 +218,7 @@ static struct clk_hw *qcom_cc_clk_hw_get(struct
of_phandle_args *clkspec,
return ERR_PTR(-EINVAL);
}
- return cc->rclks[idx] ? &cc->rclks[idx]->hw : ERR_PTR(-ENOENT);
+ return cc->rclks[idx] ? &cc->rclks[idx]->hw : NULL;
}
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.
--
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 3/3] clk: qcom: Add Global Clock controller (GCC) driver for SC7180
2019-10-04 17:39 ` Taniya Das
@ 2019-10-04 23:20 ` Stephen Boyd
2019-10-09 9:19 ` Taniya Das
0 siblings, 1 reply; 25+ messages in thread
From: Stephen Boyd @ 2019-10-04 23:20 UTC (permalink / raw)
To: Michael Turquette, Taniya Das, robh+dt
Cc: David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, devicetree
Quoting Taniya Das (2019-10-04 10:39:31)
> Hi Stephen,
>
> On 10/3/2019 9:31 PM, Stephen Boyd wrote:
> > Quoting Taniya Das (2019-10-03 03:31:15)
> >> Hi Stephen,
> >>
> >> On 10/1/2019 8:08 PM, Stephen Boyd wrote:
> >>>
> >>> Why do you want to keep them critical and registered? I'm suggesting
> >>> that any clk that is marked critical and doesn't have a parent should
> >>> instead become a register write in probe to turn the clk on.
> >>>
> >> Sure, let me do a one-time enable from probe for the clocks which
> >> doesn't have a parent.
> >> But I would now have to educate the clients of these clocks to remove
> >> using them.
> >>
> >
> > If anyone is using these clks we can return NULL from the provider for
> > the specifier so that we indicate there isn't support for them in the
> > kernel. At least I hope that code path still works given all the recent
> > changes to clk_get().
> >
>
> Could you please confirm if you are referring to update the below?
I wasn't suggesting that explicitly but sure. Something like this would
be necessary to make clk_get() pass back a NULL pointer to the caller.
Does everything keep working with this change?
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 3/3] clk: qcom: Add Global Clock controller (GCC) driver for SC7180
2019-10-04 23:20 ` Stephen Boyd
@ 2019-10-09 9:19 ` Taniya Das
2019-10-10 4:16 ` Stephen Boyd
0 siblings, 1 reply; 25+ messages in thread
From: Taniya Das @ 2019-10-09 9:19 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette, robh+dt
Cc: David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, devicetree
Hi Stephen,
On 10/5/2019 4:50 AM, Stephen Boyd wrote:
> Quoting Taniya Das (2019-10-04 10:39:31)
>> Hi Stephen,
>>
>> On 10/3/2019 9:31 PM, Stephen Boyd wrote:
>>> Quoting Taniya Das (2019-10-03 03:31:15)
>>>> Hi Stephen,
>>>>
>>>> On 10/1/2019 8:08 PM, Stephen Boyd wrote:
>>>>>
>>>>> Why do you want to keep them critical and registered? I'm suggesting
>>>>> that any clk that is marked critical and doesn't have a parent should
>>>>> instead become a register write in probe to turn the clk on.
>>>>>
>>>> Sure, let me do a one-time enable from probe for the clocks which
>>>> doesn't have a parent.
>>>> But I would now have to educate the clients of these clocks to remove
>>>> using them.
>>>>
>>>
>>> If anyone is using these clks we can return NULL from the provider for
>>> the specifier so that we indicate there isn't support for them in the
>>> kernel. At least I hope that code path still works given all the recent
>>> changes to clk_get().
>>>
>>
>> Could you please confirm if you are referring to update the below?
>
> I wasn't suggesting that explicitly but sure. Something like this would
> be necessary to make clk_get() pass back a NULL pointer to the caller.
> Does everything keep working with this change?
>
Even if I pass back NULL, I don't see it working. Please suggest how to
take it forward.
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.
--
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 3/3] clk: qcom: Add Global Clock controller (GCC) driver for SC7180
2019-10-09 9:19 ` Taniya Das
@ 2019-10-10 4:16 ` Stephen Boyd
2019-10-11 10:28 ` Taniya Das
0 siblings, 1 reply; 25+ messages in thread
From: Stephen Boyd @ 2019-10-10 4:16 UTC (permalink / raw)
To: Michael Turquette, Taniya Das, robh+dt
Cc: David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, devicetree
Quoting Taniya Das (2019-10-09 02:19:39)
> Hi Stephen,
>
> On 10/5/2019 4:50 AM, Stephen Boyd wrote:
> > Quoting Taniya Das (2019-10-04 10:39:31)
> >>
> >> Could you please confirm if you are referring to update the below?
> >
> > I wasn't suggesting that explicitly but sure. Something like this would
> > be necessary to make clk_get() pass back a NULL pointer to the caller.
> > Does everything keep working with this change?
> >
>
> Even if I pass back NULL, I don't see it working. Please suggest how to
> take it forward.
>
Why doesn't it work?
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 3/3] clk: qcom: Add Global Clock controller (GCC) driver for SC7180
2019-10-10 4:16 ` Stephen Boyd
@ 2019-10-11 10:28 ` Taniya Das
0 siblings, 0 replies; 25+ messages in thread
From: Taniya Das @ 2019-10-11 10:28 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette, robh+dt
Cc: David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, devicetree
Hi Stephen,
On 10/10/2019 9:46 AM, Stephen Boyd wrote:
> Quoting Taniya Das (2019-10-09 02:19:39)
>> Hi Stephen,
>>
>> On 10/5/2019 4:50 AM, Stephen Boyd wrote:
>>> Quoting Taniya Das (2019-10-04 10:39:31)
>>>>
>>>> Could you please confirm if you are referring to update the below?
>>>
>>> I wasn't suggesting that explicitly but sure. Something like this would
>>> be necessary to make clk_get() pass back a NULL pointer to the caller.
>>> Does everything keep working with this change?
>>>
>>
>> Even if I pass back NULL, I don't see it working. Please suggest how to
>> take it forward.
>>
>
> Why doesn't it work?
>
My bad, I messed up with the kernel and my testing was showing failures.
Have tested it on SC7180 & Cheza and it works as expected.
I will submit the changes in common.c to return NULL.
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.
--
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: clk: qcom: Add YAML schemas for the GCC clock bindings
2019-09-27 17:27 ` Rob Herring
@ 2019-10-14 10:16 ` Taniya Das
0 siblings, 0 replies; 25+ messages in thread
From: Taniya Das @ 2019-10-14 10:16 UTC (permalink / raw)
To: Rob Herring
Cc: Stephen Boyd, Michael Turquette, David Brown, Rajendra Nayak,
linux-arm-msm, linux-soc, linux-clk, linux-kernel, devicetree
Hi Rob,
Thanks for your comments.
On 9/27/2019 10:57 PM, Rob Herring wrote:
> On Wed, Sep 18, 2019 at 03:20:17PM +0530, Taniya Das wrote:
>> The GCC clock provider have a bunch of generic properties that
>> are needed in a device tree. Add a YAML schemas for those. Also update
>> the compatible for SC7180 along with example for clocks & clock-names.
>
> I'm fine fixing errors in the conversion, but adding a new chip should
> be separate patch.
>
Sure, will take care of splitting the patch.
>>
>> Signed-off-by: Taniya Das <tdas@codeaurora.org>
>> ---
>> .../devicetree/bindings/clock/qcom,gcc.txt | 94 -----------
>> .../devicetree/bindings/clock/qcom,gcc.yaml | 157 ++++++++++++++++++
>> include/dt-bindings/clock/qcom,gcc-sc7180.h | 155 +++++++++++++++++
>> 3 files changed, 312 insertions(+), 94 deletions(-)
>> delete mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc.txt
>> create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc.yaml
>> create mode 100644 include/dt-bindings/clock/qcom,gcc-sc7180.h
>>
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
>> deleted file mode 100644
>> index d14362ad4132..000000000000
>> --- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
>> +++ /dev/null
>> @@ -1,94 +0,0 @@
>> -Qualcomm Global Clock & Reset Controller Binding
>> -------------------------------------------------
>> -
>> -Required properties :
>> -- compatible : shall contain only one of the following:
>> -
>> - "qcom,gcc-apq8064"
>> - "qcom,gcc-apq8084"
>> - "qcom,gcc-ipq8064"
>> - "qcom,gcc-ipq4019"
>> - "qcom,gcc-ipq8074"
>> - "qcom,gcc-msm8660"
>> - "qcom,gcc-msm8916"
>> - "qcom,gcc-msm8960"
>> - "qcom,gcc-msm8974"
>> - "qcom,gcc-msm8974pro"
>> - "qcom,gcc-msm8974pro-ac"
>> - "qcom,gcc-msm8994"
>> - "qcom,gcc-msm8996"
>> - "qcom,gcc-msm8998"
>> - "qcom,gcc-mdm9615"
>> - "qcom,gcc-qcs404"
>> - "qcom,gcc-sdm630"
>> - "qcom,gcc-sdm660"
>> - "qcom,gcc-sdm845"
>> - "qcom,gcc-sm8150"
>> -
>> -- reg : shall contain base register location and length
>> -- #clock-cells : shall contain 1
>> -- #reset-cells : shall contain 1
>> -
>> -Optional properties :
>> -- #power-domain-cells : shall contain 1
>> -- Qualcomm TSENS (thermal sensor device) on some devices can
>> -be part of GCC and hence the TSENS properties can also be
>> -part of the GCC/clock-controller node.
>> -For more details on the TSENS properties please refer
>> -Documentation/devicetree/bindings/thermal/qcom-tsens.txt
>> -- protected-clocks : Protected clock specifier list as per common clock
>> - binding.
>> -
>> -For SM8150 only:
>> - - clocks: a list of phandles and clock-specifier pairs,
>> - one for each entry in clock-names.
>> - - clock-names: "bi_tcxo" (required)
>> - "sleep_clk" (optional)
>> - "aud_ref_clock" (optional)
>> -
>> -Example:
>> - clock-controller@900000 {
>> - compatible = "qcom,gcc-msm8960";
>> - reg = <0x900000 0x4000>;
>> - #clock-cells = <1>;
>> - #reset-cells = <1>;
>> - #power-domain-cells = <1>;
>> - };
>> -
>> -Example of GCC with TSENS properties:
>> - clock-controller@900000 {
>> - compatible = "qcom,gcc-apq8064";
>> - reg = <0x00900000 0x4000>;
>> - nvmem-cells = <&tsens_calib>, <&tsens_backup>;
>> - nvmem-cell-names = "calib", "calib_backup";
>> - #clock-cells = <1>;
>> - #reset-cells = <1>;
>> - #thermal-sensor-cells = <1>;
>> - };
>> -
>> -Example of GCC with protected-clocks properties:
>> - clock-controller@100000 {
>> - compatible = "qcom,gcc-sdm845";
>> - reg = <0x100000 0x1f0000>;
>> - #clock-cells = <1>;
>> - #reset-cells = <1>;
>> - #power-domain-cells = <1>;
>> - protected-clocks = <GCC_QSPI_CORE_CLK>,
>> - <GCC_QSPI_CORE_CLK_SRC>,
>> - <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
>> - <GCC_LPASS_Q6_AXI_CLK>,
>> - <GCC_LPASS_SWAY_CLK>;
>> - };
>> -
>> -Example of GCC with clocks
>> - gcc: clock-controller@100000 {
>> - compatible = "qcom,gcc-sm8150";
>> - reg = <0x00100000 0x1f0000>;
>> - #clock-cells = <1>;
>> - #reset-cells = <1>;
>> - #power-domain-cells = <1>;
>> - clock-names = "bi_tcxo",
>> - "sleep_clk";
>> - clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
>> - <&sleep_clk>;
>> - };
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
>> new file mode 100644
>> index 000000000000..056a7977c458
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
>> @@ -0,0 +1,157 @@
>> +# SPDX-License-Identifier: GPL-2.0
>
> As all the authors where QCom on the old file, can you relicense to
> (GPL-2.0-only OR BSD-2-Clause)?
>
I will submit the new file with the GPL-2.0-only license and will also
relicense the old files to use the GPL-2.0-only.
> And please, can all of Qcom and the Linaro QCom landing team get aligned
> on this.
>
Will work out internally.
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/qcom,gcc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm Global Clock & Reset Controller Binding
>> +
>> +maintainers:
>> + - Stephen Boyd <sboyd@kernel.org>
>> +
>> +properties:
>> + "#clock-cells":
>> + const: 1
>> +
>> + "#reset-cells":
>> + const: 1
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + compatible :
>> + enum:
>> + - qcom,gcc-apq8064
>> + - qcom,gcc-apq8084
>> + - qcom,gcc-ipq8064
>> + - qcom,gcc-ipq4019
>> + - qcom,gcc-ipq8074
>> + - qcom,gcc-msm8660
>> + - qcom,gcc-msm8916
>> + - qcom,gcc-msm8960
>> + - qcom,gcc-msm8974
>> + - qcom,gcc-msm8974pro
>> + - qcom,gcc-msm8974pro-ac
>> + - qcom,gcc-msm8994
>> + - qcom,gcc-msm8996
>> + - qcom,gcc-msm8998
>> + - qcom,gcc-mdm9615
>> + - qcom,gcc-qcs404
>> + - qcom,gcc-sdm630
>> + - qcom,gcc-sdm660
>> + - qcom,gcc-sdm845
>> + - qcom,gcc-sm8150
>> + - qcom,gcc-sc7180
>> +
>> + clocks:
>> + minItems: 1
>> + maxItems: 3
>> + items:
>> + - description: Board XO source
>> + - description: Board active XO source
>> + - description: Sleep clock source(optional)
>> +
>> + clock-names:
>> + minItems: 1
>> + maxItems: 3
>> + items:
>> + - const: bi_tcxo
>> + - const: bi_tcxo_ao
>> + - const: sleep_clk
>> +
>> + nvmem-cells:
>> + minItems: 1
>> + maxItems: 2
>> + description:
>> + Qualcomm TSENS (thermal sensor device) on some devices can
>> + be part of GCC and hence the TSENS properties can also be part
>> + of the GCC/clock-controller node.
>> + For more details on the TSENS properties please refer
>> + Documentation/devicetree/bindings/thermal/qcom-tsens.txt
>> +
>> + nvmem-cell-names:
>> + minItems: 1
>> + maxItems: 2
>> + description:
>> + Names for each nvmem-cells specified.
>> + items:
>> + - const: calib
>> + - const: calib_backup
>> +
>> + "#thermal-sensor-cells":
>> + const: 1
>>
>> + "#power-domain-cells":
>> + const: 1
>> +
>> + protected-clocks:
>> + description:
>> + Protected clock specifier list as per common clock binding
>> +
>> +required:
>> + - "#clock-cells"
>> + - "#reset-cells"
>> + - compatible
>> + - reg
>> + - clocks
>> + - clock-names
>> +
>> +examples:
>> + - |
>> + // Example:
>> + clock-controller@900000 {
>> + compatible = "qcom,gcc-msm8960";
>> + reg = <0x900000 0x4000>;
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + #power-domain-cells = <1>;
>
> Does this pass 'make dt_binding_check' as 'clocks' is required.
>
I will fix it in the next patch.
>> + };
>> +
>> +
>> + - |
>> + // Example of GCC with TSENS properties:
>> + clock-controller@900000 {
>> + compatible = "qcom,gcc-apq8064";
>> + reg = <0x00900000 0x4000>;
>> + nvmem-cells = <&tsens_calib>, <&tsens_backup>;
>> + nvmem-cell-names = "calib", "calib_backup";
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + #thermal-sensor-cells = <1>;
>> + };
>> +
>> + - |
>> + //Example of GCC with protected-clocks properties:
>> + clock-controller@100000 {
>> + compatible = "qcom,gcc-sdm845";
>> + reg = <0x100000 0x1f0000>;
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + #power-domain-cells = <1>;
>> + protected-clocks = <187>, <188>, <189>, <190>, <191>;
>> + };
>> +
>> + - |
>> + //Example of GCC with clock node properties for SM8150:
>> + clock-controller@100000 {
>> + compatible = "qcom,gcc-sm8150";
>> + reg = <0x00100000 0x1f0000>;
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + #power-domain-cells = <1>;
>> + clocks = <&rpmhcc 0>, <&rpmhcc 1>, <&sleep_clk>;
>> + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
>> + };
>> +
>> + - |
>> + //Example of GCC with clock nodes properties:
>> + clock-controller@100000 {
>> + compatible = "qcom,gcc-sc7180";
>> + reg = <0x100000 0x1f0000>;
>> + clocks = <&rpmhcc 0>, <&rpmhcc 1>;
>> + clock-names = "bi_tcxo", "bi_tcxo_ao";
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + #power-domain-cells = <1>;
>> + };
>> +...
>> diff --git a/include/dt-bindings/clock/qcom,gcc-sc7180.h b/include/dt-bindings/clock/qcom,gcc-sc7180.h
>> new file mode 100644
>> index 000000000000..d76b061f6a4e
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/qcom,gcc-sc7180.h
>> @@ -0,0 +1,155 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/*
>> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
>> + */
>> +
>> +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SC7180_H
>> +#define _DT_BINDINGS_CLK_QCOM_GCC_SC7180_H
>> +
>> +/* GCC clocks */
>> +#define GCC_GPLL0_MAIN_DIV_CDIV 0
>> +#define GPLL0 1
>> +#define GPLL0_OUT_EVEN 2
>> +#define GPLL1 3
>> +#define GPLL4 4
>> +#define GPLL6 5
>> +#define GPLL7 6
>> +#define GCC_AGGRE_UFS_PHY_AXI_CLK 7
>> +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 8
>> +#define GCC_BOOT_ROM_AHB_CLK 9
>> +#define GCC_CAMERA_AHB_CLK 10
>> +#define GCC_CAMERA_HF_AXI_CLK 11
>> +#define GCC_CAMERA_THROTTLE_HF_AXI_CLK 12
>> +#define GCC_CAMERA_XO_CLK 13
>> +#define GCC_CE1_AHB_CLK 14
>> +#define GCC_CE1_AXI_CLK 15
>> +#define GCC_CE1_CLK 16
>> +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 17
>> +#define GCC_CPUSS_AHB_CLK 18
>> +#define GCC_CPUSS_AHB_CLK_SRC 19
>> +#define GCC_CPUSS_GNOC_CLK 20
>> +#define GCC_CPUSS_RBCPR_CLK 21
>> +#define GCC_DDRSS_GPU_AXI_CLK 22
>> +#define GCC_DISP_AHB_CLK 23
>> +#define GCC_DISP_GPLL0_CLK_SRC 24
>> +#define GCC_DISP_GPLL0_DIV_CLK_SRC 25
>> +#define GCC_DISP_HF_AXI_CLK 26
>> +#define GCC_DISP_THROTTLE_HF_AXI_CLK 27
>> +#define GCC_DISP_XO_CLK 28
>> +#define GCC_GP1_CLK 29
>> +#define GCC_GP1_CLK_SRC 30
>> +#define GCC_GP2_CLK 31
>> +#define GCC_GP2_CLK_SRC 32
>> +#define GCC_GP3_CLK 33
>> +#define GCC_GP3_CLK_SRC 34
>> +#define GCC_GPU_CFG_AHB_CLK 35
>> +#define GCC_GPU_GPLL0_CLK_SRC 36
>> +#define GCC_GPU_GPLL0_DIV_CLK_SRC 37
>> +#define GCC_GPU_MEMNOC_GFX_CLK 38
>> +#define GCC_GPU_SNOC_DVM_GFX_CLK 39
>> +#define GCC_NPU_AXI_CLK 40
>> +#define GCC_NPU_BWMON_AXI_CLK 41
>> +#define GCC_NPU_BWMON_DMA_CFG_AHB_CLK 42
>> +#define GCC_NPU_BWMON_DSP_CFG_AHB_CLK 43
>> +#define GCC_NPU_CFG_AHB_CLK 44
>> +#define GCC_NPU_DMA_CLK 45
>> +#define GCC_NPU_GPLL0_CLK_SRC 46
>> +#define GCC_NPU_GPLL0_DIV_CLK_SRC 47
>> +#define GCC_PDM2_CLK 48
>> +#define GCC_PDM2_CLK_SRC 49
>> +#define GCC_PDM_AHB_CLK 50
>> +#define GCC_PDM_XO4_CLK 51
>> +#define GCC_PRNG_AHB_CLK 52
>> +#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 53
>> +#define GCC_QSPI_CORE_CLK 54
>> +#define GCC_QSPI_CORE_CLK_SRC 55
>> +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 56
>> +#define GCC_QUPV3_WRAP0_CORE_CLK 57
>> +#define GCC_QUPV3_WRAP0_S0_CLK 58
>> +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 59
>> +#define GCC_QUPV3_WRAP0_S1_CLK 60
>> +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 61
>> +#define GCC_QUPV3_WRAP0_S2_CLK 62
>> +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 63
>> +#define GCC_QUPV3_WRAP0_S3_CLK 64
>> +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 65
>> +#define GCC_QUPV3_WRAP0_S4_CLK 66
>> +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 67
>> +#define GCC_QUPV3_WRAP0_S5_CLK 68
>> +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 69
>> +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 70
>> +#define GCC_QUPV3_WRAP1_CORE_CLK 71
>> +#define GCC_QUPV3_WRAP1_S0_CLK 72
>> +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 73
>> +#define GCC_QUPV3_WRAP1_S1_CLK 74
>> +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 75
>> +#define GCC_QUPV3_WRAP1_S2_CLK 76
>> +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 77
>> +#define GCC_QUPV3_WRAP1_S3_CLK 78
>> +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 79
>> +#define GCC_QUPV3_WRAP1_S4_CLK 80
>> +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 81
>> +#define GCC_QUPV3_WRAP1_S5_CLK 82
>> +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 83
>> +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 84
>> +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 85
>> +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 86
>> +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 87
>> +#define GCC_SDCC1_AHB_CLK 88
>> +#define GCC_SDCC1_APPS_CLK 89
>> +#define GCC_SDCC1_APPS_CLK_SRC 90
>> +#define GCC_SDCC1_ICE_CORE_CLK 91
>> +#define GCC_SDCC1_ICE_CORE_CLK_SRC 92
>> +#define GCC_SDCC2_AHB_CLK 93
>> +#define GCC_SDCC2_APPS_CLK 94
>> +#define GCC_SDCC2_APPS_CLK_SRC 95
>> +#define GCC_SYS_NOC_CPUSS_AHB_CLK 96
>> +#define GCC_UFS_MEM_CLKREF_CLK 97
>> +#define GCC_UFS_PHY_AHB_CLK 98
>> +#define GCC_UFS_PHY_AXI_CLK 99
>> +#define GCC_UFS_PHY_AXI_CLK_SRC 100
>> +#define GCC_UFS_PHY_ICE_CORE_CLK 101
>> +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 102
>> +#define GCC_UFS_PHY_PHY_AUX_CLK 103
>> +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 104
>> +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 105
>> +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 106
>> +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 107
>> +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 108
>> +#define GCC_USB30_PRIM_MASTER_CLK 109
>> +#define GCC_USB30_PRIM_MASTER_CLK_SRC 110
>> +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 111
>> +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 112
>> +#define GCC_USB30_PRIM_SLEEP_CLK 113
>> +#define GCC_USB3_PRIM_CLKREF_CLK 114
>> +#define GCC_USB3_PRIM_PHY_AUX_CLK 115
>> +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 116
>> +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 117
>> +#define GCC_USB3_PRIM_PHY_PIPE_CLK 118
>> +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 119
>> +#define GCC_VIDEO_AHB_CLK 120
>> +#define GCC_VIDEO_AXI_CLK 121
>> +#define GCC_VIDEO_GPLL0_DIV_CLK_SRC 122
>> +#define GCC_VIDEO_THROTTLE_AXI_CLK 123
>> +#define GCC_VIDEO_XO_CLK 124
>> +
>> +/* GCC resets */
>> +#define GCC_QUSB2PHY_PRIM_BCR 0
>> +#define GCC_QUSB2PHY_SEC_BCR 1
>> +#define GCC_UFS_PHY_BCR 2
>> +#define GCC_USB30_PRIM_BCR 3
>> +#define GCC_USB3_DP_PHY_PRIM_BCR 4
>> +#define GCC_USB3_DP_PHY_SEC_BCR 5
>> +#define GCC_USB3_PHY_PRIM_BCR 6
>> +#define GCC_USB3_PHY_SEC_BCR 7
>> +#define GCC_USB3PHY_PHY_PRIM_BCR 8
>> +#define GCC_USB3PHY_PHY_SEC_BCR 9
>> +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 10
>> +
>> +/* GCC GDSCRs */
>> +#define UFS_PHY_GDSC 0
>> +#define USB30_PRIM_GDSC 1
>> +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 2
>> +#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 3
>> +
>> +#endif
>> --
>> Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
>> of the Code Aurora Forum, hosted by the Linux Foundation.
>>
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.
--
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: clk: qcom: Add YAML schemas for the GCC clock bindings
[not found] ` <20190918212614.448FC20882@mail.kernel.org>
@ 2019-10-14 10:17 ` Taniya Das
0 siblings, 0 replies; 25+ messages in thread
From: Taniya Das @ 2019-10-14 10:17 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette, robh+dt
Cc: David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, devicetree
Hi Stephen,
Thanks for your review.
On 9/19/2019 2:56 AM, Stephen Boyd wrote:
> Quoting Taniya Das (2019-09-18 02:50:17)
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
>> new file mode 100644
>> index 000000000000..056a7977c458
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
>> @@ -0,0 +1,157 @@
>> +# SPDX-License-Identifier: GPL-2.0
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/qcom,gcc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm Global Clock & Reset Controller Binding
>> +
>> +maintainers:
>> + - Stephen Boyd <sboyd@kernel.org>
>
> Why am I the maintainer? Shouldn't this be you?
>
>> +
>> +properties:
>> + "#clock-cells":
>> + const: 1
>> +
>> + "#reset-cells":
>> + const: 1
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + compatible :
>> + enum:
>> + - qcom,gcc-apq8064
>> + - qcom,gcc-apq8084
>> + - qcom,gcc-ipq8064
>> + - qcom,gcc-ipq4019
>> + - qcom,gcc-ipq8074
>> + - qcom,gcc-msm8660
>> + - qcom,gcc-msm8916
>> + - qcom,gcc-msm8960
>> + - qcom,gcc-msm8974
>> + - qcom,gcc-msm8974pro
>> + - qcom,gcc-msm8974pro-ac
>> + - qcom,gcc-msm8994
>> + - qcom,gcc-msm8996
>> + - qcom,gcc-msm8998
>> + - qcom,gcc-mdm9615
>> + - qcom,gcc-qcs404
>> + - qcom,gcc-sdm630
>> + - qcom,gcc-sdm660
>> + - qcom,gcc-sdm845
>> + - qcom,gcc-sm8150
>> + - qcom,gcc-sc7180
>> +
>> + clocks:
>> + minItems: 1
>> + maxItems: 3
>> + items:
>> + - description: Board XO source
>> + - description: Board active XO source
>> + - description: Sleep clock source(optional)
>
> Why is sleep clk optional?
>
Will remove optional.
>> +
>> + clock-names:
>> + minItems: 1
>> + maxItems: 3
>> + items:
>> + - const: bi_tcxo
>> + - const: bi_tcxo_ao
>> + - const: sleep_clk
>> +
>> + nvmem-cells:
>> + minItems: 1
>> + maxItems: 2
>> + description:
>> + Qualcomm TSENS (thermal sensor device) on some devices can
>
> Can this be restricted to certain compatible strings where this is the
> case? I'd like to be able to confirm that the compatibles that expect to
> see the nvmem actually have it.
>
I will add this in the next patch.
>> + be part of GCC and hence the TSENS properties can also be part
>> + of the GCC/clock-controller node.
>> + For more details on the TSENS properties please refer
>> + Documentation/devicetree/bindings/thermal/qcom-tsens.txt
>> +
>> + nvmem-cell-names:
>> + minItems: 1
>> + maxItems: 2
>> + description:
>> + Names for each nvmem-cells specified.
>> + items:
>> + - const: calib
>> + - const: calib_backup
>> +
>> + "#thermal-sensor-cells":
>> + const: 1
>
> Same for this one.
>
>> +
>> + "#power-domain-cells":
>> + const: 1
>> +
>> + protected-clocks:
>> + description:
>> + Protected clock specifier list as per common clock binding
>> +
>> +required:
>> + - "#clock-cells"
>> + - "#reset-cells"
>> + - compatible
>> + - reg
>> + - clocks
>> + - clock-names
>> +
>> +examples:
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.
--
^ permalink raw reply [flat|nested] 25+ messages in thread
end of thread, other threads:[~2019-10-14 10:18 UTC | newest]
Thread overview: 25+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-09-18 9:50 [PATCH v3 0/3] Add Global Clock controller (GCC) driver for SC7180 Taniya Das
2019-09-18 9:50 ` [PATCH v3 1/3] clk: qcom: rcg: update the DFS macro for RCG Taniya Das
2019-09-18 9:50 ` [PATCH v3 2/3] dt-bindings: clk: qcom: Add YAML schemas for the GCC clock bindings Taniya Das
2019-09-18 17:52 ` Matthias Kaehlcke
2019-09-23 6:33 ` Taniya Das
2019-09-27 17:27 ` Rob Herring
2019-10-14 10:16 ` Taniya Das
[not found] ` <20190918212614.448FC20882@mail.kernel.org>
2019-10-14 10:17 ` Taniya Das
2019-09-18 9:50 ` [PATCH v3 3/3] clk: qcom: Add Global Clock controller (GCC) driver for SC7180 Taniya Das
2019-09-19 11:08 ` Rajendra Nayak
2019-09-20 4:00 ` Taniya Das
2019-09-20 4:44 ` Rajendra Nayak
[not found] ` <20190918213946.DC03521924@mail.kernel.org>
2019-09-23 8:01 ` Taniya Das
2019-09-24 23:12 ` Stephen Boyd
2019-09-25 11:20 ` Taniya Das
2019-09-25 13:03 ` Stephen Boyd
2019-09-27 7:37 ` Taniya Das
2019-10-01 14:38 ` Stephen Boyd
2019-10-03 10:31 ` Taniya Das
2019-10-03 16:01 ` Stephen Boyd
2019-10-04 17:39 ` Taniya Das
2019-10-04 23:20 ` Stephen Boyd
2019-10-09 9:19 ` Taniya Das
2019-10-10 4:16 ` Stephen Boyd
2019-10-11 10:28 ` Taniya Das
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