* [PATCH v3] arm64: dts: qcom: Add msm8916 CoreSight components
@ 2015-05-11 8:31 Ivan T. Ivanov
2015-05-11 19:21 ` Mathieu Poirier
0 siblings, 1 reply; 6+ messages in thread
From: Ivan T. Ivanov @ 2015-05-11 8:31 UTC (permalink / raw)
To: Mathieu Poirier, Kumar Gala
Cc: Pratik Patel, Catalin Marinas, Will Deacon, Rob Herring,
Pawel Moll, Mark Rutland, Ian Campbell, devicetree,
linux-arm-kernel, linux-kernel, linux-arm-msm
Add initial set of CoreSight components found on Qualcomm's 8x16 chipset.
Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
---
Changes since v2 [1]:
* Added "1x" to "qcom,coresight-replicator" compatible string, to match what
devicetree bindings documentations says.
[1] http://www.spinics.net/lists/devicetree/msg77768.html
arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi | 254 ++++++++++++++++++++++++
1 file changed, 254 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi
diff --git a/arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi b/arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi
new file mode 100644
index 0000000..900f1f4
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi
@@ -0,0 +1,254 @@
+/*
+ * Copyright (c) 2013 - 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+&soc {
+
+ tpiu@820000 {
+ compatible = "arm,coresight-tpiu", "arm,primecell";
+ reg = <0x820000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ port {
+ tpiu_in: endpoint {
+ slave-mode;
+ remote-endpoint = <&replicator_out1>;
+ };
+ };
+ };
+
+ funnel@821000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0x821000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /*
+ * Not described input ports:
+ * 0 - connected to Resource and Power Manger CPU ETM
+ * 1 - not-connected
+ * 2 - connected to Modem CPU ETM
+ * 3 - not-connected
+ * 5 - not-connected
+ * 6 - connected trought funnel to Wireless CPU ETM
+ * 7 - connected to STM component
+ */
+ port@4 {
+ reg = <4>;
+ funnel0_in4: endpoint {
+ slave-mode;
+ remote-endpoint = <&funnel1_out>;
+ };
+ };
+ port@8 {
+ reg = <0>;
+ funnel0_out: endpoint {
+ remote-endpoint = <&etf_in>;
+ };
+ };
+ };
+ };
+
+ replicator@824000 {
+ compatible = "qcom,coresight-replicator1x", "arm,primecell";
+ reg = <0x824000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ replicator_out0: endpoint {
+ remote-endpoint = <&etr_in>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ replicator_out1: endpoint {
+ remote-endpoint = <&tpiu_in>;
+ };
+ };
+ port@2 {
+ reg = <0>;
+ replicator_in: endpoint {
+ slave-mode;
+ remote-endpoint = <&etf_out>;
+ };
+ };
+ };
+ };
+
+ etf@825000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x825000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ etf_out: endpoint {
+ slave-mode;
+ remote-endpoint = <&funnel0_out>;
+ };
+ };
+ port@1 {
+ reg = <0>;
+ etf_in: endpoint {
+ remote-endpoint = <&replicator_in>;
+ };
+ };
+ };
+ };
+
+ etr@826000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x826000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ port {
+ etr_in: endpoint {
+ slave-mode;
+ remote-endpoint = <&replicator_out0>;
+ };
+ };
+ };
+
+ funnel@841000 { /* APSS funnel only 4 inputs are used */
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0x841000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel1_in0: endpoint {
+ slave-mode;
+ remote-endpoint = <&etm0_out>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ funnel1_in1: endpoint {
+ slave-mode;
+ remote-endpoint = <&etm1_out>;
+ };
+ };
+ port@2 {
+ reg = <2>;
+ funnel1_in2: endpoint {
+ slave-mode;
+ remote-endpoint = <&etm2_out>;
+ };
+ };
+ port@3 {
+ reg = <3>;
+ funnel1_in3: endpoint {
+ slave-mode;
+ remote-endpoint = <&etm3_out>;
+ };
+ };
+ port@4 {
+ reg = <0>;
+ funnel1_out: endpoint {
+ remote-endpoint = <&funnel0_in4>;
+ };
+ };
+ };
+ };
+
+ etm@85c000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x85c000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ cpu = <&CPU0>;
+
+ port {
+ etm0_out: endpoint {
+ remote-endpoint = <&funnel1_in0>;
+ };
+ };
+ };
+
+ etm@85d000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x85d000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ cpu = <&CPU1>;
+
+ port {
+ etm1_out: endpoint {
+ remote-endpoint = <&funnel1_in1>;
+ };
+ };
+ };
+
+ etm@85e000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x85e000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ cpu = <&CPU2>;
+
+ port {
+ etm2_out: endpoint {
+ remote-endpoint = <&funnel1_in2>;
+ };
+ };
+ };
+
+ etm@85f000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x85f000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ cpu = <&CPU3>;
+
+ port {
+ etm3_out: endpoint {
+ remote-endpoint = <&funnel1_in3>;
+ };
+ };
+ };
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v3] arm64: dts: qcom: Add msm8916 CoreSight components
2015-05-11 8:31 [PATCH v3] arm64: dts: qcom: Add msm8916 CoreSight components Ivan T. Ivanov
@ 2015-05-11 19:21 ` Mathieu Poirier
2015-05-18 18:52 ` Kumar Gala
0 siblings, 1 reply; 6+ messages in thread
From: Mathieu Poirier @ 2015-05-11 19:21 UTC (permalink / raw)
To: Ivan T. Ivanov
Cc: Kumar Gala, Pratik Patel, Catalin Marinas, Will Deacon,
Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, devicetree,
linux-arm-kernel, linux-kernel, linux-arm-msm
On 11 May 2015 at 02:31, Ivan T. Ivanov <ivan.ivanov@linaro.org> wrote:
> Add initial set of CoreSight components found on Qualcomm's 8x16 chipset.
>
> Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
> ---
>
> Changes since v2 [1]:
> * Added "1x" to "qcom,coresight-replicator" compatible string, to match what
> devicetree bindings documentations says.
>
> [1] http://www.spinics.net/lists/devicetree/msg77768.html
>
> arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi | 254 ++++++++++++++++++++++++
> 1 file changed, 254 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi b/arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi
> new file mode 100644
> index 0000000..900f1f4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi
> @@ -0,0 +1,254 @@
> +/*
> + * Copyright (c) 2013 - 2015, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +&soc {
> +
> + tpiu@820000 {
> + compatible = "arm,coresight-tpiu", "arm,primecell";
> + reg = <0x820000 0x1000>;
> +
> + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + port {
> + tpiu_in: endpoint {
> + slave-mode;
> + remote-endpoint = <&replicator_out1>;
> + };
> + };
> + };
> +
> + funnel@821000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0x821000 0x1000>;
> +
> + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /*
> + * Not described input ports:
> + * 0 - connected to Resource and Power Manger CPU ETM
> + * 1 - not-connected
> + * 2 - connected to Modem CPU ETM
> + * 3 - not-connected
> + * 5 - not-connected
> + * 6 - connected trought funnel to Wireless CPU ETM
> + * 7 - connected to STM component
> + */
> + port@4 {
> + reg = <4>;
> + funnel0_in4: endpoint {
> + slave-mode;
> + remote-endpoint = <&funnel1_out>;
> + };
> + };
> + port@8 {
> + reg = <0>;
> + funnel0_out: endpoint {
> + remote-endpoint = <&etf_in>;
> + };
> + };
> + };
> + };
> +
> + replicator@824000 {
> + compatible = "qcom,coresight-replicator1x", "arm,primecell";
> + reg = <0x824000 0x1000>;
> +
> + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + replicator_out0: endpoint {
> + remote-endpoint = <&etr_in>;
> + };
> + };
> + port@1 {
> + reg = <1>;
> + replicator_out1: endpoint {
> + remote-endpoint = <&tpiu_in>;
> + };
> + };
> + port@2 {
> + reg = <0>;
> + replicator_in: endpoint {
> + slave-mode;
> + remote-endpoint = <&etf_out>;
> + };
> + };
> + };
> + };
> +
> + etf@825000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0x825000 0x1000>;
> +
> + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + etf_out: endpoint {
> + slave-mode;
> + remote-endpoint = <&funnel0_out>;
> + };
> + };
> + port@1 {
> + reg = <0>;
> + etf_in: endpoint {
> + remote-endpoint = <&replicator_in>;
> + };
> + };
> + };
> + };
> +
> + etr@826000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0x826000 0x1000>;
> +
> + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + port {
> + etr_in: endpoint {
> + slave-mode;
> + remote-endpoint = <&replicator_out0>;
> + };
> + };
> + };
> +
> + funnel@841000 { /* APSS funnel only 4 inputs are used */
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0x841000 0x1000>;
> +
> + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + funnel1_in0: endpoint {
> + slave-mode;
> + remote-endpoint = <&etm0_out>;
> + };
> + };
> + port@1 {
> + reg = <1>;
> + funnel1_in1: endpoint {
> + slave-mode;
> + remote-endpoint = <&etm1_out>;
> + };
> + };
> + port@2 {
> + reg = <2>;
> + funnel1_in2: endpoint {
> + slave-mode;
> + remote-endpoint = <&etm2_out>;
> + };
> + };
> + port@3 {
> + reg = <3>;
> + funnel1_in3: endpoint {
> + slave-mode;
> + remote-endpoint = <&etm3_out>;
> + };
> + };
> + port@4 {
> + reg = <0>;
> + funnel1_out: endpoint {
> + remote-endpoint = <&funnel0_in4>;
> + };
> + };
> + };
> + };
> +
> + etm@85c000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0x85c000 0x1000>;
> +
> + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + cpu = <&CPU0>;
> +
> + port {
> + etm0_out: endpoint {
> + remote-endpoint = <&funnel1_in0>;
> + };
> + };
> + };
> +
> + etm@85d000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0x85d000 0x1000>;
> +
> + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + cpu = <&CPU1>;
> +
> + port {
> + etm1_out: endpoint {
> + remote-endpoint = <&funnel1_in1>;
> + };
> + };
> + };
> +
> + etm@85e000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0x85e000 0x1000>;
> +
> + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + cpu = <&CPU2>;
> +
> + port {
> + etm2_out: endpoint {
> + remote-endpoint = <&funnel1_in2>;
> + };
> + };
> + };
> +
> + etm@85f000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0x85f000 0x1000>;
> +
> + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + cpu = <&CPU3>;
> +
> + port {
> + etm3_out: endpoint {
> + remote-endpoint = <&funnel1_in3>;
> + };
> + };
> + };
> +};
> --
> 1.9.1
>
Kumar, I'm happy with this DT specification for Coresight. Since I'm
taking the driver it would likely make more sense for this to go
through my tree. Could you please have a look and give me your ack?
Thanks,
Mathieu
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH v3] arm64: dts: qcom: Add msm8916 CoreSight components
2015-05-11 19:21 ` Mathieu Poirier
@ 2015-05-18 18:52 ` Kumar Gala
2015-05-19 7:03 ` Ivan T. Ivanov
0 siblings, 1 reply; 6+ messages in thread
From: Kumar Gala @ 2015-05-18 18:52 UTC (permalink / raw)
To: Mathieu Poirier
Cc: Ivan T. Ivanov, Pratik Patel, Catalin Marinas, Will Deacon,
Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, devicetree,
linux-arm-kernel, linux-kernel, linux-arm-msm
> On May 11, 2015, at 2:21 PM, Mathieu Poirier <mathieu.poirier@linaro.org> wrote:
>
> On 11 May 2015 at 02:31, Ivan T. Ivanov <ivan.ivanov@linaro.org> wrote:
>> Add initial set of CoreSight components found on Qualcomm's 8x16 chipset.
>>
>> Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
>> ---
>>
>> Changes since v2 [1]:
>> * Added "1x" to "qcom,coresight-replicator" compatible string, to match what
>> devicetree bindings documentations says.
>>
>> [1] http://www.spinics.net/lists/devicetree/msg77768.html
>>
>> arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi | 254 ++++++++++++++++++++++++
>> 1 file changed, 254 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi b/arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi
>> new file mode 100644
>> index 0000000..900f1f4
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi
>> @@ -0,0 +1,254 @@
>> +/*
>> + * Copyright (c) 2013 - 2015, The Linux Foundation. All rights reserved.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 and
>> + * only version 2 as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +&soc {
>> +
>> + tpiu@820000 {
>> + compatible = "arm,coresight-tpiu", "arm,primecell";
>> + reg = <0x820000 0x1000>;
>> +
>> + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
>> + clock-names = "apb_pclk", "atclk";
>> +
>> + port {
>> + tpiu_in: endpoint {
>> + slave-mode;
>> + remote-endpoint = <&replicator_out1>;
>> + };
>> + };
>> + };
>> +
>> + funnel@821000 {
>> + compatible = "arm,coresight-funnel", "arm,primecell";
>> + reg = <0x821000 0x1000>;
>> +
>> + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
>> + clock-names = "apb_pclk", "atclk";
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + /*
>> + * Not described input ports:
>> + * 0 - connected to Resource and Power Manger CPU ETM
>> + * 1 - not-connected
>> + * 2 - connected to Modem CPU ETM
>> + * 3 - not-connected
>> + * 5 - not-connected
>> + * 6 - connected trought funnel to Wireless CPU ETM
>> + * 7 - connected to STM component
>> + */
>> + port@4 {
>> + reg = <4>;
>> + funnel0_in4: endpoint {
>> + slave-mode;
>> + remote-endpoint = <&funnel1_out>;
>> + };
>> + };
>> + port@8 {
>> + reg = <0>;
>> + funnel0_out: endpoint {
>> + remote-endpoint = <&etf_in>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + replicator@824000 {
>> + compatible = "qcom,coresight-replicator1x", "arm,primecell";
>> + reg = <0x824000 0x1000>;
>> +
>> + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
>> + clock-names = "apb_pclk", "atclk";
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> + replicator_out0: endpoint {
>> + remote-endpoint = <&etr_in>;
>> + };
>> + };
>> + port@1 {
>> + reg = <1>;
>> + replicator_out1: endpoint {
>> + remote-endpoint = <&tpiu_in>;
>> + };
>> + };
>> + port@2 {
>> + reg = <0>;
>> + replicator_in: endpoint {
>> + slave-mode;
>> + remote-endpoint = <&etf_out>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + etf@825000 {
>> + compatible = "arm,coresight-tmc", "arm,primecell";
>> + reg = <0x825000 0x1000>;
>> +
>> + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
>> + clock-names = "apb_pclk", "atclk";
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> + etf_out: endpoint {
>> + slave-mode;
>> + remote-endpoint = <&funnel0_out>;
>> + };
>> + };
>> + port@1 {
>> + reg = <0>;
>> + etf_in: endpoint {
>> + remote-endpoint = <&replicator_in>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + etr@826000 {
>> + compatible = "arm,coresight-tmc", "arm,primecell";
>> + reg = <0x826000 0x1000>;
>> +
>> + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
>> + clock-names = "apb_pclk", "atclk";
>> +
>> + port {
>> + etr_in: endpoint {
>> + slave-mode;
>> + remote-endpoint = <&replicator_out0>;
>> + };
>> + };
>> + };
>> +
>> + funnel@841000 { /* APSS funnel only 4 inputs are used */
>> + compatible = "arm,coresight-funnel", "arm,primecell";
>> + reg = <0x841000 0x1000>;
>> +
>> + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
>> + clock-names = "apb_pclk", "atclk";
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> + funnel1_in0: endpoint {
>> + slave-mode;
>> + remote-endpoint = <&etm0_out>;
>> + };
>> + };
>> + port@1 {
>> + reg = <1>;
>> + funnel1_in1: endpoint {
>> + slave-mode;
>> + remote-endpoint = <&etm1_out>;
>> + };
>> + };
>> + port@2 {
>> + reg = <2>;
>> + funnel1_in2: endpoint {
>> + slave-mode;
>> + remote-endpoint = <&etm2_out>;
>> + };
>> + };
>> + port@3 {
>> + reg = <3>;
>> + funnel1_in3: endpoint {
>> + slave-mode;
>> + remote-endpoint = <&etm3_out>;
>> + };
>> + };
>> + port@4 {
>> + reg = <0>;
>> + funnel1_out: endpoint {
>> + remote-endpoint = <&funnel0_in4>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + etm@85c000 {
>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>> + reg = <0x85c000 0x1000>;
>> +
>> + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
>> + clock-names = "apb_pclk", "atclk";
>> +
>> + cpu = <&CPU0>;
>> +
>> + port {
>> + etm0_out: endpoint {
>> + remote-endpoint = <&funnel1_in0>;
>> + };
>> + };
>> + };
>> +
>> + etm@85d000 {
>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>> + reg = <0x85d000 0x1000>;
>> +
>> + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
>> + clock-names = "apb_pclk", "atclk";
>> +
>> + cpu = <&CPU1>;
>> +
>> + port {
>> + etm1_out: endpoint {
>> + remote-endpoint = <&funnel1_in1>;
>> + };
>> + };
>> + };
>> +
>> + etm@85e000 {
>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>> + reg = <0x85e000 0x1000>;
>> +
>> + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
>> + clock-names = "apb_pclk", "atclk";
>> +
>> + cpu = <&CPU2>;
>> +
>> + port {
>> + etm2_out: endpoint {
>> + remote-endpoint = <&funnel1_in2>;
>> + };
>> + };
>> + };
>> +
>> + etm@85f000 {
>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>> + reg = <0x85f000 0x1000>;
>> +
>> + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
>> + clock-names = "apb_pclk", "atclk";
>> +
>> + cpu = <&CPU3>;
>> +
>> + port {
>> + etm3_out: endpoint {
>> + remote-endpoint = <&funnel1_in3>;
>> + };
>> + };
>> + };
>> +};
>> --
>> 1.9.1
>>
>
> Kumar, I'm happy with this DT specification for Coresight. Since I'm
> taking the driver it would likely make more sense for this to go
> through my tree. Could you please have a look and give me your ack?
It looks ok, however I don’t see us including this file anywhere, so that’s my only concern.
- k
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH v3] arm64: dts: qcom: Add msm8916 CoreSight components
2015-05-18 18:52 ` Kumar Gala
@ 2015-05-19 7:03 ` Ivan T. Ivanov
2015-05-19 13:52 ` Mathieu Poirier
0 siblings, 1 reply; 6+ messages in thread
From: Ivan T. Ivanov @ 2015-05-19 7:03 UTC (permalink / raw)
To: Kumar Gala
Cc: Mathieu Poirier, Pratik Patel, Catalin Marinas, Will Deacon,
Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, devicetree,
linux-arm-kernel, linux-kernel, linux-arm-msm
On Mon, 2015-05-18 at 13:52 -0500, Kumar Gala wrote:
> >
> > On May 11, 2015, at 2:21 PM, Mathieu Poirier poirier@linaro.org> wrote:
> >
> > On 11 May 2015 at 02:31, Ivan T. Ivanov ivanov@linaro.org> wrote:
> > > Add initial set of CoreSight components found on Qualcomm's 8x16 chipset.
> >
> >
> > Kumar, I'm happy with this DT specification for Coresight. Since I'm
> > taking the driver it would likely make more sense for this to go
> > through my tree. Could you please have a look and give me your ack?
>
> It looks ok, however I don’t see us including this file anywhere, so that’s my only concern.
>
True. The reason is that 'rpmcc' driver is still in testing phase
and it is not upstreamed. Once it is ready, I will include this file
where is appropriate.
Regards,
Ivan
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v3] arm64: dts: qcom: Add msm8916 CoreSight components
2015-05-19 7:03 ` Ivan T. Ivanov
@ 2015-05-19 13:52 ` Mathieu Poirier
2015-05-19 14:02 ` Ivan T. Ivanov
0 siblings, 1 reply; 6+ messages in thread
From: Mathieu Poirier @ 2015-05-19 13:52 UTC (permalink / raw)
To: Ivan T. Ivanov
Cc: Kumar Gala, Pratik Patel, Catalin Marinas, Will Deacon,
Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, devicetree,
linux-arm-kernel, linux-kernel, linux-arm-msm
On 19 May 2015 at 01:03, Ivan T. Ivanov <ivan.ivanov@linaro.org> wrote:
>
> On Mon, 2015-05-18 at 13:52 -0500, Kumar Gala wrote:
>> >
>> > On May 11, 2015, at 2:21 PM, Mathieu Poirier poirier@linaro.org> wrote:
>> >
>> > On 11 May 2015 at 02:31, Ivan T. Ivanov ivanov@linaro.org> wrote:
>> > > Add initial set of CoreSight components found on Qualcomm's 8x16 chipset.
>> >
>
>> >
>> > Kumar, I'm happy with this DT specification for Coresight. Since I'm
>> > taking the driver it would likely make more sense for this to go
>> > through my tree. Could you please have a look and give me your ack?
>>
>> It looks ok, however I don’t see us including this file anywhere, so that’s my only concern.
>>
>
> True. The reason is that 'rpmcc' driver is still in testing phase
> and it is not upstreamed. Once it is ready, I will include this file
> where is appropriate.
>
> Regards,
> Ivan
Very well - as such I won't take the DT patch right away. Please
re-submit when all the components are ready.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v3] arm64: dts: qcom: Add msm8916 CoreSight components
2015-05-19 13:52 ` Mathieu Poirier
@ 2015-05-19 14:02 ` Ivan T. Ivanov
0 siblings, 0 replies; 6+ messages in thread
From: Ivan T. Ivanov @ 2015-05-19 14:02 UTC (permalink / raw)
To: Mathieu Poirier
Cc: Kumar Gala, Pratik Patel, Catalin Marinas, Will Deacon,
Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, devicetree,
linux-arm-kernel, linux-kernel, linux-arm-msm
On Tue, 2015-05-19 at 07:52 -0600, Mathieu Poirier wrote:
> On 19 May 2015 at 01:03, Ivan T. Ivanov ivanov@linaro.org> wrote:
> > On Mon, 2015-05-18 at 13:52 -0500, Kumar Gala wrote:
> > > > On May 11, 2015, at 2:21 PM, Mathieu Poirier poirier@linaro.org> wrote:
> > > >
> > > > On 11 May 2015 at 02:31, Ivan T. Ivanov ivanov@linaro.org> wrote:
> > > > > Add initial set of CoreSight components found on Qualcomm's 8x16 chipset.
> > > >
> >
> > > > Kumar, I'm happy with this DT specification for Coresight. Since I'm
> > > > taking the driver it would likely make more sense for this to go
> > > > through my tree. Could you please have a look and give me your ack?
> > >
> > > It looks ok, however I don’t see us including this file anywhere, so that’s my only concern.
> > >
> >
> > True. The reason is that 'rpmcc' driver is still in testing phase
> > and it is not upstreamed. Once it is ready, I will include this file
> > where is appropriate.
> >
> > Regards,
> > Ivan
>
> Very well - as such I won't take the DT patch right away. Please
> re-submit when all the components are ready.
Eeh, I was hoping to include this file to main msm8916.dtsi,
not to resend it, but I'm оk either way.
Regards,
Ivan
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2015-05-19 14:02 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-05-11 8:31 [PATCH v3] arm64: dts: qcom: Add msm8916 CoreSight components Ivan T. Ivanov
2015-05-11 19:21 ` Mathieu Poirier
2015-05-18 18:52 ` Kumar Gala
2015-05-19 7:03 ` Ivan T. Ivanov
2015-05-19 13:52 ` Mathieu Poirier
2015-05-19 14:02 ` Ivan T. Ivanov
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