From: "Saripalli, RK" <rsaripal@amd.com>
To: linux-kernel@vger.kernel.org, x86@kernel.org, tglx@linutronix.de,
mingo@redhat.com, bp@alien8.de, hpa@zytor.com
Cc: bsd@redhat.com
Subject: Re: [v6 0/1] Introduce support for PSF control.
Date: Thu, 17 Jun 2021 15:47:45 -0500 [thread overview]
Message-ID: <7b952b4c-de69-080b-477c-44d2f973fea6@amd.com> (raw)
In-Reply-To: <20210517220059.6452-1-rsaripal@amd.com>
On 5/17/2021 5:00 PM, Ramakrishna Saripalli wrote:
> From: Ramakrishna Saripalli <rk.saripalli@amd.com>
>
> Predictive Store Forwarding:
> AMD Zen3 processors feature a new technology called
> Predictive Store Forwarding (PSF).
>
> https://www.amd.com/system/files/documents/security-analysis-predictive-store-forwarding.pdf
>
> PSF is a hardware-based micro-architectural optimization designed
> to improve the performance of code execution by predicting address
> dependencies between loads and stores.
>
> How PSF works:
>
> It is very common for a CPU to execute a load instruction to an address
> that was recently written by a store. Modern CPUs implement a technique
> known as Store-To-Load-Forwarding (STLF) to improve performance in such
> cases. With STLF, data from the store is forwarded directly to the load
> without having to wait for it to be written to memory. In a typical CPU,
> STLF occurs after the address of both the load and store are calculated
> and determined to match.
>
> PSF expands on this by speculating on the relationship between loads and
> stores without waiting for the address calculation to complete. With PSF,
> the CPU learns over time the relationship between loads and stores.
> If STLF typically occurs between a particular store and load, the CPU will
> remember this.
>
> In typical code, PSF provides a performance benefit by speculating on
> the load result and allowing later instructions to begin execution
> sooner than they otherwise would be able to.
>
> Causes of Incorrect PSF:
>
> Incorrect PSF predictions can occur due to two reasons.
>
> First, it is possible that the store/load pair had a dependency for a
> while but later stops having a dependency. This can occur if the address
> of either the store or load changes during the execution of the program.
>
> The second source of incorrect PSF predictions can occur if there is an
> alias in the PSF predictor structure. The PSF predictor tracks
> store-load pairs based on portions of their RIP. It is possible that a
> store-load pair which does have a dependency may alias in the predictor
> with another store-load pair which does not.
>
> This can result in incorrect speculation when the second store/load pair
> is executed.
>
> Security Analysis:
>
> Previous research has shown that when CPUs speculate on non-architectural
> paths it can lead to the potential of side channel attacks.
> In particular, programs that implement isolation, also known as
> ‘sandboxing’, entirely in software may need to be concerned with incorrect
> CPU speculation as they can occur due to bad PSF predictions.
>
> Because PSF speculation is limited to the current program context,
> the impact of bad PSF speculation is very similar to that of
> Speculative Store Bypass (Spectre v4)
>
> Predictive Store Forwarding controls:
> There are two hardware control bits which influence the PSF feature:
> - MSR 48h bit 2 – Speculative Store Bypass (SSBD)
> - MSR 48h bit 7 – Predictive Store Forwarding Disable (PSFD)
>
> The PSF feature is disabled if either of these bits are set. These bits
> are controllable on a per-thread basis in an SMT system. By default, both
> SSBD and PSFD are 0 meaning that the speculation features are enabled.
>
> While the SSBD bit disables PSF and speculative store bypass, PSFD only
> disables PSF.
>
> PSFD may be desirable for software which is concerned with the
> speculative behavior of PSF but desires a smaller performance impact than
> setting SSBD.
>
> Support for PSFD is indicated in CPUID Fn8000_0008 EBX[28].
> All processors that support PSF will also support PSFD.
>
> ChangeLogs:
> V6->V5:
> Moved PSF control code to arch/x86/kernel/cpu/bugs.c
> PSF mitigation is similar to spec_control_bypass mitigation.
> PSF mitigation has only ON and OFF controls.
> Kernel parameter changed to predictive_store_fwd_disable.
> V5->V4:
> Replaced rdmsrl and wrmsrl for setting SPEC_CTRL_PSFD with
> a single call to msr_set_bit.
> Removed temporary variable to read and write the MSR
> V4->V3:
> Write to MSR_IA32_SPEC_CTRL properly
> Read MSR, modify PSFD bit based on kernel parameter and
> write back to MSR.
>
> Changes made in psf_cmdline() and check_bugs().
> V3->V2:
> Set the X86_FEATURE_SPEC_CTRL_MSR cap in boot cpu caps.
> Fix kernel documentation for the kernel parameter.
> Rename PSF to a control instead of mitigation.
>
> V1->V2:
> - Smashed multiple commits into one commit.
> - Rename PSF to a control instead of mitigation.
>
> V1:
> - Initial patchset.
> - Kernel parameter controls enable and disable of PSF.
>
>
>
Gentle ping. Any more concerns or feedback with this patch series?.
Thanks,
RK
>
> Ramakrishna Saripalli (1):
> x86/bugs: Implement mitigation for Predictive Store Forwarding
>
> .../admin-guide/kernel-parameters.txt | 5 +
> arch/x86/include/asm/cpufeatures.h | 1 +
> arch/x86/include/asm/msr-index.h | 2 +
> arch/x86/include/asm/nospec-branch.h | 6 ++
> arch/x86/kernel/cpu/bugs.c | 94 +++++++++++++++++++
> 5 files changed, 108 insertions(+)
>
>
> base-commit: 0e16f466004d7f04296b9676a712a32a12367d1f
>
prev parent reply other threads:[~2021-06-17 20:47 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-17 22:00 [v6 0/1] Introduce support for PSF control Ramakrishna Saripalli
2021-05-17 22:00 ` [v6 1/1] x86/bugs: Implement mitigation for Predictive Store Forwarding Ramakrishna Saripalli
2021-05-18 2:55 ` Randy Dunlap
2021-05-18 12:27 ` Saripalli, RK
2021-05-18 20:35 ` Pawan Gupta
2021-05-19 5:38 ` Pawan Gupta
2021-05-19 13:19 ` Saripalli, RK
2021-05-19 5:50 ` Pawan Gupta
2021-09-01 20:20 ` [v6 1/1] x86/bugs: Implement mitigation for Predictive Store Babu Moger
2021-09-01 20:30 ` Babu Moger
2021-09-01 20:35 ` Babu Moger
2021-09-02 17:35 ` Pawan Gupta
2021-08-12 23:44 ` [v6 1/1] x86/bugs: Implement mitigation for Predictive Store Forwarding Josh Poimboeuf
2021-09-02 18:16 ` [v6 1/1] x86/bugs: Implement mitigation for Predictive Store Babu Moger
2021-09-03 0:07 ` Josh Poimboeuf
[not found] ` <dca004cf-bacc-1a1f-56d6-c06e8bec167a@amd.com>
2021-09-04 17:23 ` Josh Poimboeuf
2021-09-07 23:15 ` Babu Moger
2021-09-08 18:20 ` Josh Poimboeuf
2021-09-10 16:08 ` Babu Moger
2021-09-09 16:20 ` Bandan Das
2021-06-17 20:47 ` Saripalli, RK [this message]
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