* Re: [PATCH] arm64: dts: apple: Add t8103 L1/L2 cache properties and nodes
[not found] <20221206-asahi-soc-t8103-cache-v1-0-577c5ca2360f@jannau.net>
@ 2022-12-07 4:29 ` Hector Martin
0 siblings, 0 replies; only message in thread
From: Hector Martin @ 2022-12-07 4:29 UTC (permalink / raw)
To: Janne Grunau, Sven Peter, Alyssa Rosenzweig, Rob Herring,
Krzysztof Kozlowski
Cc: asahi, linux-arm-kernel, devicetree, linux-kernel
On 07/12/2022 07.38, Janne Grunau wrote:
> The t8103 CPU nodes are missing the cache hierarchy information. The
> cache hierarchy on Arm can not be detected and needs to be described in
> DT. The OS scheduler can make use of this information for scheduling
> decisions.
>
> The cache size information is based on various articles about the
> processors. There's also an L3 system level cache (SLC). It's not
> described here because SLCs typically have some MMIO interface which
> would need to be described.
>
> Based on Rob Herring's patch adding cache properties and nodes for
> t600x.
>
> Link: https://lore.kernel.org/asahi/20221122220619.659174-1-robh@kernel.org/
>
> Signed-off-by: Janne Grunau <j@jannau.net>
Acked-by: Hector Martin <marcan@marcan.st>
Thanks! Applied to asahi-soc/dt.
- Hector
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2022-12-07 4:29 ` [PATCH] arm64: dts: apple: Add t8103 L1/L2 cache properties and nodes Hector Martin
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