[PATCH v2 1/7] dt-bindings: phy: mediatek,tphy: add support type of SGMII

[PATCH v2 1/7] dt-bindings: phy: mediatek,tphy: add support type of SGMII

[Chunfeng Yun]

Add support ethernet SGMII, forgot to update type supported.

Fixes: c01608b3b46b ("dt-bindings: phy: mediatek: tphy: support type switch by pericfg")
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: add acked-by Rob
---
 Documentation/devicetree/bindings/phy/mediatek,tphy.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
index b3e409988c17..848edfb1f677 100644
--- a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
+++ b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
@@ -163,6 +163,7 @@ patternProperties:
                 - PHY_TYPE_USB3
                 - PHY_TYPE_PCIE
                 - PHY_TYPE_SATA
+                - PHY_TYPE_SGMII
 
       nvmem-cells:
         items:
-- 
2.18.0

[PATCH v2 2/7] dt-bindings: phy: mediatek,tphy: add property to set pre-emphasis

[Chunfeng Yun]

Add a property to set usb2 phy's pre-emphasis, which used to widen eye
opening and boost eye swing.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: Add more description suggested by Krzysztof
---
 .../devicetree/bindings/phy/mediatek,tphy.yaml         | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
index 848edfb1f677..e0754fb44451 100644
--- a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
+++ b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
@@ -219,6 +219,16 @@ patternProperties:
         minimum: 1
         maximum: 15
 
+      mediatek,pre-emphasis:
+        description:
+          The level of pre-emphasis which used to widen the eye opening and
+          boost eye swing, the unit step is about 4.16% increment; e.g. the
+          level 1 means amplitude increases about 4.16%, the level 2 is about
+          8.3% etc. (U2 phy)
+        $ref: /schemas/types.yaml#/definitions/uint32
+        minimum: 1
+        maximum: 3
+
       mediatek,bc12:
         description:
           Specify the flag to enable BC1.2 if support it
-- 
2.18.0

[PATCH v2 3/7] phy: phy-mtk-tphy: add property to set pre-emphasis

[Chunfeng Yun]

Add a property to set usb2 phy's pre-emphasis, it's disabled by default
on some SoCs.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: no changes
---
 drivers/phy/mediatek/phy-mtk-tphy.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c
index 8ee7682b8e93..986fde0f63a0 100644
--- a/drivers/phy/mediatek/phy-mtk-tphy.c
+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
@@ -72,6 +72,8 @@
 #define PA5_RG_U2_HS_100U_U3_EN	BIT(11)
 
 #define U3P_USBPHYACR6		0x018
+#define PA6_RG_U2_PRE_EMP		GENMASK(31, 30)
+#define PA6_RG_U2_PRE_EMP_VAL(x)	((0x3 & (x)) << 30)
 #define PA6_RG_U2_BC11_SW_EN		BIT(23)
 #define PA6_RG_U2_OTG_VBUSCMP_EN	BIT(20)
 #define PA6_RG_U2_DISCTH		GENMASK(7, 4)
@@ -370,6 +372,7 @@ struct mtk_phy_instance {
 	int eye_term;
 	int intr;
 	int discth;
+	int pre_emphasis;
 	bool bc12_en;
 };
 
@@ -841,10 +844,13 @@ static void phy_parse_property(struct mtk_tphy *tphy,
 				 &instance->intr);
 	device_property_read_u32(dev, "mediatek,discth",
 				 &instance->discth);
+	device_property_read_u32(dev, "mediatek,pre-emphasis",
+				 &instance->pre_emphasis);
 	dev_dbg(dev, "bc12:%d, src:%d, vrt:%d, term:%d, intr:%d, disc:%d\n",
 		instance->bc12_en, instance->eye_src,
 		instance->eye_vrt, instance->eye_term,
 		instance->intr, instance->discth);
+	dev_dbg(dev, "pre-emp:%d\n", instance->pre_emphasis);
 }
 
 static void u2_phy_props_set(struct mtk_tphy *tphy,
@@ -875,6 +881,10 @@ static void u2_phy_props_set(struct mtk_tphy *tphy,
 	if (instance->discth)
 		mtk_phy_update_bits(com + U3P_USBPHYACR6, PA6_RG_U2_DISCTH,
 				    PA6_RG_U2_DISCTH_VAL(instance->discth));
+
+	if (instance->pre_emphasis)
+		mtk_phy_update_bits(com + U3P_USBPHYACR6, PA6_RG_U2_PRE_EMP,
+				    PA6_RG_U2_PRE_EMP_VAL(instance->pre_emphasis));
 }
 
 /* type switch for usb3/pcie/sgmii/sata */
-- 
2.18.0

[PATCH v2 4/7] phy: phy-mtk-tphy: disable hardware efuse when set INTR

[Chunfeng Yun]

INTR's value is able autoload from hardware efuse by default, when
software tries to update its value, should disable hardware efuse
firstly.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: no changes
---
 drivers/phy/mediatek/phy-mtk-tphy.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c
index 986fde0f63a0..7f40b8b052bd 100644
--- a/drivers/phy/mediatek/phy-mtk-tphy.c
+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
@@ -874,9 +874,14 @@ static void u2_phy_props_set(struct mtk_tphy *tphy,
 		mtk_phy_update_bits(com + U3P_USBPHYACR1, PA1_RG_TERM_SEL,
 				    PA1_RG_TERM_SEL_VAL(instance->eye_term));
 
-	if (instance->intr)
+	if (instance->intr) {
+		if (u2_banks->misc)
+			mtk_phy_set_bits(u2_banks->misc + U3P_MISC_REG1,
+					 MR1_EFUSE_AUTO_LOAD_DIS);
+
 		mtk_phy_update_bits(com + U3P_USBPHYACR1, PA1_RG_INTR_CAL,
 				    PA1_RG_INTR_CAL_VAL(instance->intr));
+	}
 
 	if (instance->discth)
 		mtk_phy_update_bits(com + U3P_USBPHYACR6, PA6_RG_U2_DISCTH,
-- 
2.18.0

[PATCH v2 5/7] phy: phy-mtk-tphy: disable gpio mode for all usb2 phys

[Chunfeng Yun]

Disable DP/DM's GPIO mode for all usb2 phy, not only for the first
usb2 phy which usually supports dual-role mode.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: no changes
---
 drivers/phy/mediatek/phy-mtk-tphy.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c
index 7f40b8b052bd..79920c066e59 100644
--- a/drivers/phy/mediatek/phy-mtk-tphy.c
+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
@@ -532,8 +532,7 @@ static void u2_phy_instance_init(struct mtk_tphy *tphy,
 	/* disable switch 100uA current to SSUSB */
 	mtk_phy_clear_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HS_100U_U3_EN);
 
-	if (!index)
-		mtk_phy_clear_bits(com + U3P_U2PHYACR4, P2C_U2_GPIO_CTR_MSK);
+	mtk_phy_clear_bits(com + U3P_U2PHYACR4, P2C_U2_GPIO_CTR_MSK);
 
 	if (tphy->pdata->avoid_rx_sen_degradation) {
 		if (!index) {
-- 
2.18.0

[PATCH v2 6/7] phy: phy-mtk-tphy: set utmi 0 register in init() ops

[Chunfeng Yun]

No need repeat to clear utmi 0 register in ->power_on() and
->power_off(), just do it in ->init()

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: no changes
---
 drivers/phy/mediatek/phy-mtk-tphy.c | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c
index 79920c066e59..e0f227a0d3cc 100644
--- a/drivers/phy/mediatek/phy-mtk-tphy.c
+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
@@ -522,8 +522,8 @@ static void u2_phy_instance_init(struct mtk_tphy *tphy,
 	/* switch to USB function, and enable usb pll */
 	mtk_phy_clear_bits(com + U3P_U2PHYDTM0, P2C_FORCE_UART_EN | P2C_FORCE_SUSPENDM);
 
-	mtk_phy_update_bits(com + U3P_U2PHYDTM0, P2C_RG_XCVRSEL | P2C_RG_DATAIN,
-			    P2C_RG_XCVRSEL_VAL(1) | P2C_RG_DATAIN_VAL(0));
+	mtk_phy_clear_bits(com + U3P_U2PHYDTM0,
+			   P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK);
 
 	mtk_phy_clear_bits(com + U3P_U2PHYDTM1, P2C_RG_UART_EN);
 
@@ -565,9 +565,6 @@ static void u2_phy_instance_power_on(struct mtk_tphy *tphy,
 	void __iomem *com = u2_banks->com;
 	u32 index = instance->index;
 
-	mtk_phy_clear_bits(com + U3P_U2PHYDTM0,
-			   P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK);
-
 	/* OTG Enable */
 	mtk_phy_set_bits(com + U3P_USBPHYACR6, PA6_RG_U2_OTG_VBUSCMP_EN);
 
@@ -590,8 +587,6 @@ static void u2_phy_instance_power_off(struct mtk_tphy *tphy,
 	void __iomem *com = u2_banks->com;
 	u32 index = instance->index;
 
-	mtk_phy_clear_bits(com + U3P_U2PHYDTM0, P2C_RG_XCVRSEL | P2C_RG_DATAIN);
-
 	/* OTG Disable */
 	mtk_phy_clear_bits(com + U3P_USBPHYACR6, PA6_RG_U2_OTG_VBUSCMP_EN);
 
-- 
2.18.0

[PATCH v2 7/7] phy: phy-mtk-tphy: fix the phy type setting issue

[Chunfeng Yun]

The PHY type is not set if the index is non zero, prepare type
value according to the index, like as mask value.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: no changes
---
 drivers/phy/mediatek/phy-mtk-tphy.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c
index e0f227a0d3cc..cc10298bc70d 100644
--- a/drivers/phy/mediatek/phy-mtk-tphy.c
+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
@@ -915,7 +915,7 @@ static int phy_type_syscon_get(struct mtk_phy_instance *instance,
 static int phy_type_set(struct mtk_phy_instance *instance)
 {
 	int type;
-	u32 mask;
+	u32 offset;
 
 	if (!instance->type_sw)
 		return 0;
@@ -938,8 +938,9 @@ static int phy_type_set(struct mtk_phy_instance *instance)
 		return 0;
 	}
 
-	mask = RG_PHY_SW_TYPE << (instance->type_sw_index * BITS_PER_BYTE);
-	regmap_update_bits(instance->type_sw, instance->type_sw_reg, mask, type);
+	offset = instance->type_sw_index * BITS_PER_BYTE;
+	regmap_update_bits(instance->type_sw, instance->type_sw_reg,
+			   RG_PHY_SW_TYPE << offset, type << offset);
 
 	return 0;
 }
-- 
2.18.0

Re: [PATCH v2 2/7] dt-bindings: phy: mediatek,tphy: add property to set pre-emphasis

[Krzysztof Kozlowski]

On 29/08/2022 11:08, Chunfeng Yun wrote:
> Add a property to set usb2 phy's pre-emphasis, which used to widen eye
> opening and boost eye swing.
> 
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> v2: Add more description suggested by Krzysztof
> ---
>  .../devicetree/bindings/phy/mediatek,tphy.yaml         | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
> index 848edfb1f677..e0754fb44451 100644
> --- a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
> +++ b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
> @@ -219,6 +219,16 @@ patternProperties:
>          minimum: 1
>          maximum: 15
>  
> +      mediatek,pre-emphasis:
> +        description:
> +          The level of pre-emphasis which used to widen the eye opening and
> +          boost eye swing, the unit step is about 4.16% increment; e.g. the
> +          level 1 means amplitude increases about 4.16%, the level 2 is about
> +          8.3% etc. (U2 phy)
> +        $ref: /schemas/types.yaml#/definitions/uint32

As I proposed - use instead common units. Since only three values are
allowed - make it an enum. These bindings are expected to be
usable/applicable on several devices, so units, not register values
which can change between devices, are the proper and reliable way to
describe a feature.


Best regards,
Krzysztof

Re: [PATCH v2 2/7] dt-bindings: phy: mediatek,tphy: add property to set pre-emphasis

[Chunfeng Yun]

On Tue, 2022-08-30 at 20:38 +0300, Krzysztof Kozlowski wrote:
> On 29/08/2022 11:08, Chunfeng Yun wrote:
> > Add a property to set usb2 phy's pre-emphasis, which used to widen
> > eye
> > opening and boost eye swing.
> > 
> > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> > ---
> > v2: Add more description suggested by Krzysztof
> > ---
> >  .../devicetree/bindings/phy/mediatek,tphy.yaml         | 10
> > ++++++++++
> >  1 file changed, 10 insertions(+)
> > 
> > diff --git
> > a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
> > b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
> > index 848edfb1f677..e0754fb44451 100644
> > --- a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
> > +++ b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
> > @@ -219,6 +219,16 @@ patternProperties:
> >          minimum: 1
> >          maximum: 15
> >  
> > +      mediatek,pre-emphasis:
> > +        description:
> > +          The level of pre-emphasis which used to widen the eye
> > opening and
> > +          boost eye swing, the unit step is about 4.16% increment;
> > e.g. the
> > +          level 1 means amplitude increases about 4.16%, the level
> > 2 is about
> > +          8.3% etc. (U2 phy)
> > +        $ref: /schemas/types.yaml#/definitions/uint32
> 
> As I proposed - use instead common units. 
As explained before, no units for these value.

> Since only three values are
> allowed - make it an enum. 
Ok,

> These bindings are expected to be
> usable/applicable on several devices, so units, not register values
> which can change between devices, are the proper and reliable way to
> describe a feature.
I prefer to use exact level values, but not the inexact values with
units (e.g. -percent, -microvolt).

Thanks a lot

> 
> 
> Best regards,
> Krzysztof

Re: [PATCH v2 2/7] dt-bindings: phy: mediatek,tphy: add property to set pre-emphasis

[Krzysztof Kozlowski]

On 31/08/2022 06:14, Chunfeng Yun wrote:
>> These bindings are expected to be
>> usable/applicable on several devices, so units, not register values
>> which can change between devices, are the proper and reliable way to
>> describe a feature.
> I prefer to use exact level values, but not the inexact values with
> units (e.g. -percent, -microvolt).

What stops you from using exact values - bp?

Best regards,
Krzysztof

Re: [PATCH v2 3/7] phy: phy-mtk-tphy: add property to set pre-emphasis

[AngeloGioacchino Del Regno]

Il 29/08/22 10:08, Chunfeng Yun ha scritto:
> Add a property to set usb2 phy's pre-emphasis, it's disabled by default
> on some SoCs.
> 
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> v2: no changes
> ---
>   drivers/phy/mediatek/phy-mtk-tphy.c | 10 ++++++++++
>   1 file changed, 10 insertions(+)
> 
> diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c
> index 8ee7682b8e93..986fde0f63a0 100644
> --- a/drivers/phy/mediatek/phy-mtk-tphy.c
> +++ b/drivers/phy/mediatek/phy-mtk-tphy.c
> @@ -72,6 +72,8 @@
>   #define PA5_RG_U2_HS_100U_U3_EN	BIT(11)
>   
>   #define U3P_USBPHYACR6		0x018
> +#define PA6_RG_U2_PRE_EMP		GENMASK(31, 30)
> +#define PA6_RG_U2_PRE_EMP_VAL(x)	((0x3 & (x)) << 30)

Hello Chunfeng,

can you please clarify which SoC is this change referred to?

If I'm not missing anything, there may be a register layout conflict between
one version and the other for T-PHYs, for which, it may be a good idea to add
a PHY version check before allowing to write settings that are supported only
on a specific IP...

Regards,
Angelo

Re: [PATCH v2 4/7] phy: phy-mtk-tphy: disable hardware efuse when set INTR

[AngeloGioacchino Del Regno]

Il 29/08/22 10:08, Chunfeng Yun ha scritto:
> INTR's value is able autoload from hardware efuse by default, when
> software tries to update its value, should disable hardware efuse
> firstly.
> 
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Re: [PATCH v2 7/7] phy: phy-mtk-tphy: fix the phy type setting issue

[AngeloGioacchino Del Regno]

Il 29/08/22 10:08, Chunfeng Yun ha scritto:
> The PHY type is not set if the index is non zero, prepare type
> value according to the index, like as mask value.
> 
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>

I agree with this change and I'd be happy to give you my R-b tag, but this
commit clearly needs to be backported, so you need a Fixes tag, or a Cc to stable.

Thanks,
Angelo

> ---
> v2: no changes
> ---
>   drivers/phy/mediatek/phy-mtk-tphy.c | 7 ++++---
>   1 file changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c
> index e0f227a0d3cc..cc10298bc70d 100644
> --- a/drivers/phy/mediatek/phy-mtk-tphy.c
> +++ b/drivers/phy/mediatek/phy-mtk-tphy.c
> @@ -915,7 +915,7 @@ static int phy_type_syscon_get(struct mtk_phy_instance *instance,
>   static int phy_type_set(struct mtk_phy_instance *instance)
>   {
>   	int type;
> -	u32 mask;
> +	u32 offset;
>   
>   	if (!instance->type_sw)
>   		return 0;
> @@ -938,8 +938,9 @@ static int phy_type_set(struct mtk_phy_instance *instance)
>   		return 0;
>   	}
>   
> -	mask = RG_PHY_SW_TYPE << (instance->type_sw_index * BITS_PER_BYTE);
> -	regmap_update_bits(instance->type_sw, instance->type_sw_reg, mask, type);
> +	offset = instance->type_sw_index * BITS_PER_BYTE;
> +	regmap_update_bits(instance->type_sw, instance->type_sw_reg,
> +			   RG_PHY_SW_TYPE << offset, type << offset);
>   
>   	return 0;
>   }
> 

Re: [PATCH v2 7/7] phy: phy-mtk-tphy: fix the phy type setting issue

[Chunfeng Yun]

On Wed, 2022-08-31 at 10:31 +0200, AngeloGioacchino Del Regno wrote:
> Il 29/08/22 10:08, Chunfeng Yun ha scritto:
> > The PHY type is not set if the index is non zero, prepare type
> > value according to the index, like as mask value.
> > 
> > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> 
> I agree with this change and I'd be happy to give you my R-b tag, but
> this
> commit clearly needs to be backported, so you need a Fixes tag, or a
> Cc to stable.
A good point, will add it in next version, thanks a lot

> 
> Thanks,
> Angelo
> 
> > ---
> > v2: no changes
> > ---
> >   drivers/phy/mediatek/phy-mtk-tphy.c | 7 ++++---
> >   1 file changed, 4 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c
> > b/drivers/phy/mediatek/phy-mtk-tphy.c
> > index e0f227a0d3cc..cc10298bc70d 100644
> > --- a/drivers/phy/mediatek/phy-mtk-tphy.c
> > +++ b/drivers/phy/mediatek/phy-mtk-tphy.c
> > @@ -915,7 +915,7 @@ static int phy_type_syscon_get(struct
> > mtk_phy_instance *instance,
> >   static int phy_type_set(struct mtk_phy_instance *instance)
> >   {
> >   	int type;
> > -	u32 mask;
> > +	u32 offset;
> >   
> >   	if (!instance->type_sw)
> >   		return 0;
> > @@ -938,8 +938,9 @@ static int phy_type_set(struct mtk_phy_instance
> > *instance)
> >   		return 0;
> >   	}
> >   
> > -	mask = RG_PHY_SW_TYPE << (instance->type_sw_index *
> > BITS_PER_BYTE);
> > -	regmap_update_bits(instance->type_sw, instance->type_sw_reg,
> > mask, type);
> > +	offset = instance->type_sw_index * BITS_PER_BYTE;
> > +	regmap_update_bits(instance->type_sw, instance->type_sw_reg,
> > +			   RG_PHY_SW_TYPE << offset, type << offset);
> >   
> >   	return 0;
> >   }
> > 
> 
> 

Re: [PATCH v2 3/7] phy: phy-mtk-tphy: add property to set pre-emphasis

[Chunfeng Yun]

On Wed, 2022-08-31 at 10:14 +0200, AngeloGioacchino Del Regno wrote:
> Il 29/08/22 10:08, Chunfeng Yun ha scritto:
> > Add a property to set usb2 phy's pre-emphasis, it's disabled by
> > default
> > on some SoCs.
> > 
> > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> > ---
> > v2: no changes
> > ---
> >   drivers/phy/mediatek/phy-mtk-tphy.c | 10 ++++++++++
> >   1 file changed, 10 insertions(+)
> > 
> > diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c
> > b/drivers/phy/mediatek/phy-mtk-tphy.c
> > index 8ee7682b8e93..986fde0f63a0 100644
> > --- a/drivers/phy/mediatek/phy-mtk-tphy.c
> > +++ b/drivers/phy/mediatek/phy-mtk-tphy.c
> > @@ -72,6 +72,8 @@
> >   #define PA5_RG_U2_HS_100U_U3_EN	BIT(11)
> >   
> >   #define U3P_USBPHYACR6		0x018
> > +#define PA6_RG_U2_PRE_EMP		GENMASK(31, 30)
> > +#define PA6_RG_U2_PRE_EMP_VAL(x)	((0x3 & (x)) << 30)
> 
> Hello Chunfeng,
> 
> can you please clarify which SoC is this change referred to?
These bits are reserved before using 12nm process.

> 
> If I'm not missing anything, there may be a register layout conflict 
As I know these reserved bits are not used before, but now used to tune
pre-emphasis after supporting 12nm or 5nm process.

> between
> one version and the other for T-PHYs, for which, it may be a good
> idea to add
> a PHY version check before allowing to write settings that are
> supported only
> on a specific IP...
Do you know which SoC used bits, I can confirm it with our DE.

Thanks a lot

> 
> Regards,
> Angelo
> 

Re: [PATCH v2 3/7] phy: phy-mtk-tphy: add property to set pre-emphasis

[AngeloGioacchino Del Regno]

Il 08/09/22 03:39, Chunfeng Yun ha scritto:
> On Wed, 2022-08-31 at 10:14 +0200, AngeloGioacchino Del Regno wrote:
>> Il 29/08/22 10:08, Chunfeng Yun ha scritto:
>>> Add a property to set usb2 phy's pre-emphasis, it's disabled by
>>> default
>>> on some SoCs.
>>>
>>> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
>>> ---
>>> v2: no changes
>>> ---
>>>    drivers/phy/mediatek/phy-mtk-tphy.c | 10 ++++++++++
>>>    1 file changed, 10 insertions(+)
>>>
>>> diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c
>>> b/drivers/phy/mediatek/phy-mtk-tphy.c
>>> index 8ee7682b8e93..986fde0f63a0 100644
>>> --- a/drivers/phy/mediatek/phy-mtk-tphy.c
>>> +++ b/drivers/phy/mediatek/phy-mtk-tphy.c
>>> @@ -72,6 +72,8 @@
>>>    #define PA5_RG_U2_HS_100U_U3_EN	BIT(11)
>>>    
>>>    #define U3P_USBPHYACR6		0x018
>>> +#define PA6_RG_U2_PRE_EMP		GENMASK(31, 30)
>>> +#define PA6_RG_U2_PRE_EMP_VAL(x)	((0x3 & (x)) << 30)
>>
>> Hello Chunfeng,
>>
>> can you please clarify which SoC is this change referred to?
> These bits are reserved before using 12nm process.
> 
>>
>> If I'm not missing anything, there may be a register layout conflict
> As I know these reserved bits are not used before, but now used to tune
> pre-emphasis after supporting 12nm or 5nm process.
> 
>> between
>> one version and the other for T-PHYs, for which, it may be a good
>> idea to add
>> a PHY version check before allowing to write settings that are
>> supported only
>> on a specific IP...
> Do you know which SoC used bits, I can confirm it with our DE.
> 

MT8195, MT8186 (and others), RG_USB20_PHY_REV is marked as bit 31:24.

Regards,
Angelo

Re: [PATCH v2 2/7] dt-bindings: phy: mediatek,tphy: add property to set pre-emphasis

[Chunfeng Yun]

On Wed, 2022-08-31 at 09:02 +0300, Krzysztof Kozlowski wrote:
> On 31/08/2022 06:14, Chunfeng Yun wrote:
> > > These bindings are expected to be
> > > usable/applicable on several devices, so units, not register
> > > values
> > > which can change between devices, are the proper and reliable way
> > > to
> > > describe a feature.
> > 
> > I prefer to use exact level values, but not the inexact values with
> > units (e.g. -percent, -microvolt).
> 
> What stops you from using exact values - bp?
See reply for the first series, thanks

> 
> Best regards,
> Krzysztof

Re: [PATCH v2 2/7] dt-bindings: phy: mediatek,tphy: add property to set pre-emphasis

[Krzysztof Kozlowski]

On 09/09/2022 05:07, Chunfeng Yun wrote:
> On Wed, 2022-08-31 at 09:02 +0300, Krzysztof Kozlowski wrote:
>> On 31/08/2022 06:14, Chunfeng Yun wrote:
>>>> These bindings are expected to be
>>>> usable/applicable on several devices, so units, not register
>>>> values
>>>> which can change between devices, are the proper and reliable way
>>>> to
>>>> describe a feature.
>>>
>>> I prefer to use exact level values, but not the inexact values with
>>> units (e.g. -percent, -microvolt).
>>
>> What stops you from using exact values - bp?
> See reply for the first series, thanks

Not in my inbox anymore.


Best regards,
Krzysztof

Re: [PATCH v2 2/7] dt-bindings: phy: mediatek,tphy: add property to set pre-emphasis

[Krzysztof Kozlowski]

On 29/08/2022 10:08, Chunfeng Yun wrote:
> Add a property to set usb2 phy's pre-emphasis, which used to widen eye
> opening and boost eye swing.
> 
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> v2: Add more description suggested by Krzysztof
> ---
>  .../devicetree/bindings/phy/mediatek,tphy.yaml         | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

Re: [PATCH v2 3/7] phy: phy-mtk-tphy: add property to set pre-emphasis

[Chunfeng Yun]

On Thu, 2022-09-08 at 10:05 +0200, AngeloGioacchino Del Regno wrote:
> Il 08/09/22 03:39, Chunfeng Yun ha scritto:
> > On Wed, 2022-08-31 at 10:14 +0200, AngeloGioacchino Del Regno
> > wrote:
> > > Il 29/08/22 10:08, Chunfeng Yun ha scritto:
> > > > Add a property to set usb2 phy's pre-emphasis, it's disabled by
> > > > default
> > > > on some SoCs.
> > > > 
> > > > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> > > > ---
> > > > v2: no changes
> > > > ---
> > > >    drivers/phy/mediatek/phy-mtk-tphy.c | 10 ++++++++++
> > > >    1 file changed, 10 insertions(+)
> > > > 
> > > > diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c
> > > > b/drivers/phy/mediatek/phy-mtk-tphy.c
> > > > index 8ee7682b8e93..986fde0f63a0 100644
> > > > --- a/drivers/phy/mediatek/phy-mtk-tphy.c
> > > > +++ b/drivers/phy/mediatek/phy-mtk-tphy.c
> > > > @@ -72,6 +72,8 @@
> > > >    #define PA5_RG_U2_HS_100U_U3_EN	BIT(11)
> > > >    
> > > >    #define U3P_USBPHYACR6		0x018
> > > > +#define PA6_RG_U2_PRE_EMP		GENMASK(31, 30)
> > > > +#define PA6_RG_U2_PRE_EMP_VAL(x)	((0x3 & (x)) << 30)
> > > 
> > > Hello Chunfeng,
> > > 
> > > can you please clarify which SoC is this change referred to?
> > 
> > These bits are reserved before using 12nm process.
> > 
> > > 
> > > If I'm not missing anything, there may be a register layout
> > > conflict
> > 
> > As I know these reserved bits are not used before, but now used to
> > tune
> > pre-emphasis after supporting 12nm or 5nm process.
> > 
> > > between
> > > one version and the other for T-PHYs, for which, it may be a good
> > > idea to add
> > > a PHY version check before allowing to write settings that are
> > > supported only
> > > on a specific IP...
> > 
> > Do you know which SoC used bits, I can confirm it with our DE.
> > 
> 
> MT8195, MT8186 (and others), RG_USB20_PHY_REV is marked as bit 31:24.
Sorry, there is something wrong, the register map is not updated;

> 
> Regards,
> Angelo
>