* [PATCH 01/10] dt-bindings: display/msm: dsi-controller-main: Add SM6350
[not found] <20230211122656.1479141-1-konrad.dybcio@linaro.org>
@ 2023-02-11 12:26 ` Konrad Dybcio
2023-02-14 23:57 ` Rob Herring
2023-02-11 12:26 ` [PATCH 02/10] dt-bindings: display/msm: dsi-controller-main: Add SM6375 Konrad Dybcio
` (8 subsequent siblings)
9 siblings, 1 reply; 36+ messages in thread
From: Konrad Dybcio @ 2023-02-11 12:26 UTC (permalink / raw)
To: linux-arm-msm, andersson, agross, krzysztof.kozlowski
Cc: marijn.suijten, Konrad Dybcio, Rob Clark, Abhinav Kumar,
Dmitry Baryshkov, Sean Paul, David Airlie, Daniel Vetter,
Rob Herring, Krzysztof Kozlowski, Krishna Manikandan, dri-devel,
freedreno, devicetree, linux-kernel
Add the DSI host found on SM6350.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
.../devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
index f195530ae964..2f946bb9fe24 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
@@ -26,6 +26,7 @@ properties:
- qcom,sdm660-dsi-ctrl
- qcom,sdm845-dsi-ctrl
- qcom,sm6115-dsi-ctrl
+ - qcom,sm6350-dsi-ctrl
- qcom,sm8150-dsi-ctrl
- qcom,sm8250-dsi-ctrl
- qcom,sm8350-dsi-ctrl
@@ -286,6 +287,7 @@ allOf:
contains:
enum:
- qcom,msm8998-dsi-ctrl
+ - qcom,sm6350-dsi-ctrl
then:
properties:
clocks:
--
2.39.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 02/10] dt-bindings: display/msm: dsi-controller-main: Add SM6375
[not found] <20230211122656.1479141-1-konrad.dybcio@linaro.org>
2023-02-11 12:26 ` [PATCH 01/10] dt-bindings: display/msm: dsi-controller-main: Add SM6350 Konrad Dybcio
@ 2023-02-11 12:26 ` Konrad Dybcio
2023-02-14 23:57 ` Rob Herring
2023-02-11 12:26 ` [PATCH 03/10] dt-bindings: display/msm: Add SM6350 DPU & MDSS Konrad Dybcio
` (7 subsequent siblings)
9 siblings, 1 reply; 36+ messages in thread
From: Konrad Dybcio @ 2023-02-11 12:26 UTC (permalink / raw)
To: linux-arm-msm, andersson, agross, krzysztof.kozlowski
Cc: marijn.suijten, Konrad Dybcio, Rob Clark, Abhinav Kumar,
Dmitry Baryshkov, Sean Paul, David Airlie, Daniel Vetter,
Rob Herring, Krzysztof Kozlowski, Krishna Manikandan, dri-devel,
freedreno, devicetree, linux-kernel
Add the DSI host found on SM6375.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
.../devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
index 2f946bb9fe24..41cdb631d305 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
@@ -27,6 +27,7 @@ properties:
- qcom,sdm845-dsi-ctrl
- qcom,sm6115-dsi-ctrl
- qcom,sm6350-dsi-ctrl
+ - qcom,sm6375-dsi-ctrl
- qcom,sm8150-dsi-ctrl
- qcom,sm8250-dsi-ctrl
- qcom,sm8350-dsi-ctrl
@@ -355,6 +356,7 @@ allOf:
enum:
- qcom,sdm845-dsi-ctrl
- qcom,sm6115-dsi-ctrl
+ - qcom,sm6375-dsi-ctrl
then:
properties:
clocks:
--
2.39.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 03/10] dt-bindings: display/msm: Add SM6350 DPU & MDSS
[not found] <20230211122656.1479141-1-konrad.dybcio@linaro.org>
2023-02-11 12:26 ` [PATCH 01/10] dt-bindings: display/msm: dsi-controller-main: Add SM6350 Konrad Dybcio
2023-02-11 12:26 ` [PATCH 02/10] dt-bindings: display/msm: dsi-controller-main: Add SM6375 Konrad Dybcio
@ 2023-02-11 12:26 ` Konrad Dybcio
2023-02-11 16:33 ` Dmitry Baryshkov
2023-02-13 15:09 ` Rob Herring
2023-02-11 12:26 ` [PATCH 04/10] dt-bindings: display/msm: Add SM6375 " Konrad Dybcio
` (6 subsequent siblings)
9 siblings, 2 replies; 36+ messages in thread
From: Konrad Dybcio @ 2023-02-11 12:26 UTC (permalink / raw)
To: linux-arm-msm, andersson, agross, krzysztof.kozlowski
Cc: marijn.suijten, Konrad Dybcio, Rob Clark, Abhinav Kumar,
Dmitry Baryshkov, Sean Paul, David Airlie, Daniel Vetter,
Rob Herring, Krzysztof Kozlowski, Krishna Manikandan, dri-devel,
freedreno, devicetree, linux-kernel
Document 6350 DPU and MDSS.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
.../bindings/display/msm/qcom,sm6350-dpu.yaml | 94 ++++++++
.../display/msm/qcom,sm6350-mdss.yaml | 213 ++++++++++++++++++
2 files changed, 307 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml
create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml
new file mode 100644
index 000000000000..979fcf81afc9
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml
@@ -0,0 +1,94 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm6350-dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display DPU dt properties for SM6350 target
+
+maintainers:
+ - Konrad Dybcio <konrad.dybcio@linaro.org>
+
+$ref: /schemas/display/msm/dpu-common.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: qcom,sm6350-dpu
+
+ reg:
+ items:
+ - description: Address offset and size for mdp register set
+ - description: Address offset and size for vbif register set
+
+ reg-names:
+ items:
+ - const: mdp
+ - const: vbif
+
+ clocks:
+ items:
+ - description: Display axi clock
+ - description: Display ahb clock
+ - description: Display rot clock
+ - description: Display lut clock
+ - description: Display core clock
+ - description: Display vsync clock
+
+ clock-names:
+ items:
+ - const: bus
+ - const: iface
+ - const: rot
+ - const: lut
+ - const: core
+ - const: vsync
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,dispcc-sm6350.h>
+ #include <dt-bindings/clock/qcom,gcc-sm6350.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ display-controller@ae01000 {
+ compatible = "qcom,sm6350-dpu";
+ reg = <0x0ae01000 0x8f000>,
+ <0x0aeb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_ROT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus", "iface", "rot", "lut", "core",
+ "vsync";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+ power-domains = <&rpmhpd SM6350_CX>;
+ operating-points-v2 = <&mdp_opp_table>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml
new file mode 100644
index 000000000000..4fda5205494e
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml
@@ -0,0 +1,213 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm6350-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM6350 Display MDSS
+
+maintainers:
+ - Krishna Manikandan <quic_mkrishn@quicinc.com>
+
+description:
+ SM6350 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
+ like DPU display controller, DSI and DP interfaces etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: qcom,sm6350-mdss
+
+ clocks:
+ items:
+ - description: Display AHB clock from gcc
+ - description: Display AXI clock from gcc
+ - description: Display core clock
+
+ clock-names:
+ items:
+ - const: iface
+ - const: bus
+ - const: core
+
+ iommus:
+ maxItems: 1
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ maxItems: 2
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ const: qcom,sm6350-dpu
+
+ "^dsi@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ - const: qcom,sm6350-dsi-ctrl
+ - const: qcom,mdss-dsi-ctrl
+
+ "^phy@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ const: qcom,dsi-phy-10nm
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,dispcc-sm6350.h>
+ #include <dt-bindings/clock/qcom,gcc-sm6350.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ display-subsystem@ae00000 {
+ compatible = "qcom,sm6350-mdss";
+ reg = <0x0ae00000 0x1000>;
+ reg-names = "mdss";
+
+ power-domains = <&dispcc MDSS_GDSC>;
+
+ clocks = <&gcc GCC_DISP_AHB_CLK>,
+ <&gcc GCC_DISP_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "bus", "core";
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_smmu 0x800 0x2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ display-controller@ae01000 {
+ compatible = "qcom,sm6350-dpu";
+ reg = <0x0ae01000 0x8f000>,
+ <0x0aeb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_ROT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus", "iface", "rot", "lut", "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
+ <&dispcc DISP_CC_MDSS_ROT_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>;
+ assigned-clock-rates = <300000000>,
+ <19200000>,
+ <19200000>,
+ <19200000>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmhpd SM6350_CX>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf2_out: endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
+ };
+ };
+
+ dsi@ae94000 {
+ compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+ reg = <0x0ae94000 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmhpd SM6350_MX>;
+
+ phys = <&dsi0_phy>;
+ phy-names = "dsi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_out: endpoint {
+ };
+ };
+ };
+ };
+
+ dsi0_phy: phy@ae94400 {
+ compatible = "qcom,dsi-phy-10nm";
+ reg = <0x0ae94400 0x200>,
+ <0x0ae94600 0x280>,
+ <0x0ae94a00 0x1e0>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+ };
+ };
+...
--
2.39.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 04/10] dt-bindings: display/msm: Add SM6375 DPU & MDSS
[not found] <20230211122656.1479141-1-konrad.dybcio@linaro.org>
` (2 preceding siblings ...)
2023-02-11 12:26 ` [PATCH 03/10] dt-bindings: display/msm: Add SM6350 DPU & MDSS Konrad Dybcio
@ 2023-02-11 12:26 ` Konrad Dybcio
2023-02-13 15:09 ` Rob Herring
2023-02-11 12:26 ` [PATCH 05/10] drm/msm/dpu: Allow variable SSPP/INTF_BLK size Konrad Dybcio
` (5 subsequent siblings)
9 siblings, 1 reply; 36+ messages in thread
From: Konrad Dybcio @ 2023-02-11 12:26 UTC (permalink / raw)
To: linux-arm-msm, andersson, agross, krzysztof.kozlowski
Cc: marijn.suijten, Konrad Dybcio, Rob Clark, Abhinav Kumar,
Dmitry Baryshkov, Sean Paul, David Airlie, Daniel Vetter,
Rob Herring, Krzysztof Kozlowski, dri-devel, freedreno,
devicetree, linux-kernel
Document SM6375 DPU and MDSS.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
.../bindings/display/msm/qcom,sm6375-dpu.yaml | 106 +++++++++
.../display/msm/qcom,sm6375-mdss.yaml | 216 ++++++++++++++++++
2 files changed, 322 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm6375-dpu.yaml
create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6375-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-dpu.yaml
new file mode 100644
index 000000000000..76dc5a7efebf
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-dpu.yaml
@@ -0,0 +1,106 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm6375-dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display DPU dt properties for SM6375 target
+
+maintainers:
+ - Konrad Dybcio <konrad.dybcio@linaro.org>
+
+$ref: /schemas/display/msm/dpu-common.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: qcom,sm6375-dpu
+
+ reg:
+ items:
+ - description: Address offset and size for mdp register set
+ - description: Address offset and size for vbif register set
+
+ reg-names:
+ items:
+ - const: mdp
+ - const: vbif
+
+ clocks:
+ items:
+ - description: Display iface clock
+ - description: Display bus clock
+ - description: Display core clock
+ - description: Display lut clock
+ - description: Display rot clock
+ - description: Display vsync clock
+ - description: Display throttle clock
+
+ clock-names:
+ items:
+ - const: iface
+ - const: bus
+ - const: core
+ - const: lut
+ - const: rot
+ - const: vsync
+ - const: throttle
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,sm6375-gcc.h>
+ #include <dt-bindings/clock/qcom,sm6375-dispcc.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ display-controller@ae01000 {
+ compatible = "qcom,sm6375-dpu";
+ reg = <0x05e01000 0x8e030>,
+ <0x05eb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_ROT_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
+ <&gcc GCC_DISP_THROTTLE_CORE_CLK>;
+ clock-names = "iface",
+ "bus",
+ "core",
+ "lut",
+ "rot",
+ "vsync",
+ "throttle";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmpd SM6375_VDDCX>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml
new file mode 100644
index 000000000000..fb56971ea2a1
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml
@@ -0,0 +1,216 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm6375-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM6375 Display MDSS
+
+maintainers:
+ - Konrad Dybcio <konrad.dybcio@linaro.org>
+
+description:
+ SM6375 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
+ like DPU display controller, DSI and DP interfaces etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: qcom,sm6375-mdss
+
+ clocks:
+ items:
+ - description: Display AHB clock from gcc
+ - description: Display AHB clock
+ - description: Display core clock
+
+ clock-names:
+ items:
+ - const: iface
+ - const: ahb
+ - const: core
+
+ iommus:
+ maxItems: 1
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ maxItems: 2
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ const: qcom,sm6375-dpu
+
+ "^dsi@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ items:
+ - const: qcom,sm6375-dsi-ctrl
+ - const: qcom,mdss-dsi-ctrl
+
+ "^phy@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ const: qcom,sm6375-dsi-phy-7nm
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmcc.h>
+ #include <dt-bindings/clock/qcom,sm6375-gcc.h>
+ #include <dt-bindings/clock/qcom,sm6375-dispcc.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ display-subsystem@5e00000 {
+ compatible = "qcom,sm6375-mdss";
+ reg = <0x05e00000 0x1000>;
+ reg-names = "mdss";
+
+ power-domains = <&dispcc MDSS_GDSC>;
+
+ clocks = <&gcc GCC_DISP_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "ahb", "core";
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_smmu 0x820 0x2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ display-controller@5e01000 {
+ compatible = "qcom,sm6375-dpu";
+ reg = <0x05e01000 0x8e030>,
+ <0x05eb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_ROT_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
+ <&gcc GCC_DISP_THROTTLE_CORE_CLK>;
+ clock-names = "iface",
+ "bus",
+ "core",
+ "lut",
+ "rot",
+ "vsync",
+ "throttle";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmpd SM6375_VDDCX>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf2_out: endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
+ };
+ };
+
+ dsi@5e94000 {
+ compatible = "qcom,sm6375-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+ reg = <0x05e94000 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmpd SM6375_VDDMX>;
+
+ phys = <&mdss_dsi0_phy>;
+ phy-names = "dsi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_out: endpoint {
+ };
+ };
+ };
+ };
+
+ mdss_dsi0_phy: phy@5e94400 {
+ compatible = "qcom,sm6375-dsi-phy-7nm";
+ reg = <0x05e94400 0x200>,
+ <0x05e94600 0x280>,
+ <0x05e94900 0x264>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "iface", "ref";
+ };
+ };
+...
--
2.39.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 05/10] drm/msm/dpu: Allow variable SSPP/INTF_BLK size
[not found] <20230211122656.1479141-1-konrad.dybcio@linaro.org>
` (3 preceding siblings ...)
2023-02-11 12:26 ` [PATCH 04/10] dt-bindings: display/msm: Add SM6375 " Konrad Dybcio
@ 2023-02-11 12:26 ` Konrad Dybcio
2023-02-11 17:00 ` Dmitry Baryshkov
2023-02-13 11:12 ` Marijn Suijten
2023-02-11 12:26 ` [PATCH 06/10] drm/msm/dpu: Add SM6350 support Konrad Dybcio
` (4 subsequent siblings)
9 siblings, 2 replies; 36+ messages in thread
From: Konrad Dybcio @ 2023-02-11 12:26 UTC (permalink / raw)
To: linux-arm-msm, andersson, agross, krzysztof.kozlowski
Cc: marijn.suijten, Konrad Dybcio, Rob Clark, Abhinav Kumar,
Dmitry Baryshkov, Sean Paul, David Airlie, Daniel Vetter,
Robert Foss, AngeloGioacchino Del Regno, dri-devel, freedreno,
linux-kernel
These blocks are of variable length on different SoCs. Set the
correct values where I was able to retrieve it from downstream
DTs and leave the old defaults (0x1c8 for sspp and 0x280 for
intf) otherwise.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 242 +++++++++---------
1 file changed, 121 insertions(+), 121 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 802050118345..d9ef1e133c1e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -1167,11 +1167,11 @@ static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK("9", 2);
static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK("10", 3);
static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11", 4);
-#define SSPP_BLK(_name, _id, _base, _features, \
+#define SSPP_BLK(_name, _id, _base, _len, _features, \
_sblk, _xinid, _type, _clkctrl) \
{ \
.name = _name, .id = _id, \
- .base = _base, .len = 0x1c8, \
+ .base = _base, .len = _len, \
.features = _features, \
.sblk = &_sblk, \
.xin_id = _xinid, \
@@ -1180,40 +1180,40 @@ static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11", 4);
}
static const struct dpu_sspp_cfg msm8998_sspp[] = {
- SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_MSM8998_MASK,
+ SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x184, VIG_MSM8998_MASK,
msm8998_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
- SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_MSM8998_MASK,
+ SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x184, VIG_MSM8998_MASK,
msm8998_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
- SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_MSM8998_MASK,
+ SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x184, VIG_MSM8998_MASK,
msm8998_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
- SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_MSM8998_MASK,
+ SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x184, VIG_MSM8998_MASK,
msm8998_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
- SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_MSM8998_MASK,
+ SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x184, DMA_MSM8998_MASK,
sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
- SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_MSM8998_MASK,
+ SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x184, DMA_MSM8998_MASK,
sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
- SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_MSM8998_MASK,
+ SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x184, DMA_CURSOR_MSM8998_MASK,
sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
- SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_MSM8998_MASK,
+ SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x184, DMA_CURSOR_MSM8998_MASK,
sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
};
static const struct dpu_sspp_cfg sdm845_sspp[] = {
- SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SDM845_MASK,
+ SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1c8, VIG_SDM845_MASK,
sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
- SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SDM845_MASK,
+ SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1c8, VIG_SDM845_MASK,
sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
- SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SDM845_MASK,
+ SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1c8, VIG_SDM845_MASK,
sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
- SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SDM845_MASK,
+ SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1c8, VIG_SDM845_MASK,
sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
- SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
+ SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1c8, DMA_SDM845_MASK,
sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
- SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK,
+ SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1c8, DMA_SDM845_MASK,
sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
- SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
+ SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1c8, DMA_CURSOR_SDM845_MASK,
sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
- SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK,
+ SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1c8, DMA_CURSOR_SDM845_MASK,
sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
};
@@ -1224,13 +1224,13 @@ static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 =
_VIG_SBLK_ROT("0", 4, DPU_SSPP_SCALER_QSEED4, &dpu_rot_sc7280_cfg_v2);
static const struct dpu_sspp_cfg sc7180_sspp[] = {
- SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK,
+ SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1c8, VIG_SC7180_MASK,
sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
- SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
+ SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1c8, DMA_SDM845_MASK,
sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
- SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_CURSOR_SDM845_MASK,
+ SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1c8, DMA_CURSOR_SDM845_MASK,
sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
- SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
+ SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1c8, DMA_CURSOR_SDM845_MASK,
sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
};
@@ -1238,9 +1238,9 @@ static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 =
_VIG_SBLK("0", 2, DPU_SSPP_SCALER_QSEED3LITE);
static const struct dpu_sspp_cfg sm6115_sspp[] = {
- SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SM8250_MASK,
+ SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SM8250_MASK,
sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
- SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
+ SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
};
@@ -1254,21 +1254,21 @@ static const struct dpu_sspp_sub_blks sm8250_vig_sblk_3 =
_VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3LITE);
static const struct dpu_sspp_cfg sm8250_sspp[] = {
- SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SM8250_MASK,
+ SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SM8250_MASK,
sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
- SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SM8250_MASK,
+ SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f8, VIG_SM8250_MASK,
sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
- SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SM8250_MASK,
+ SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f8, VIG_SM8250_MASK,
sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
- SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SM8250_MASK,
+ SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f8, VIG_SM8250_MASK,
sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
- SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
+ SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
- SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK,
+ SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_SDM845_MASK,
sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
- SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
+ SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
- SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK,
+ SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f8, DMA_CURSOR_SDM845_MASK,
sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
};
@@ -1282,21 +1282,21 @@ static const struct dpu_sspp_sub_blks sm8450_vig_sblk_3 =
_VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3LITE);
static const struct dpu_sspp_cfg sm8450_sspp[] = {
- SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK,
- sm8450_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
- SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SC7180_MASK,
- sm8450_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
- SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SC7180_MASK,
+ SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x328, VIG_SC7180_MASK,
+ sm8450_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
+ SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x328, VIG_SC7180_MASK,
+ sm8450_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
+ SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x328, VIG_SC7180_MASK,
sm8450_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
- SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SC7180_MASK,
- sm8450_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
- SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
+ SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x328, VIG_SC7180_MASK,
+ sm8450_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
+ SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x328, DMA_SDM845_MASK,
sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
- SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK,
+ SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x328, DMA_SDM845_MASK,
sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
- SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
+ SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x328, DMA_CURSOR_SDM845_MASK,
sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
- SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK,
+ SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x328, DMA_CURSOR_SDM845_MASK,
sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
};
@@ -1312,36 +1312,36 @@ static const struct dpu_sspp_sub_blks sm8550_dma_sblk_4 = _DMA_SBLK("12", 5);
static const struct dpu_sspp_sub_blks sd8550_dma_sblk_5 = _DMA_SBLK("13", 6);
static const struct dpu_sspp_cfg sm8550_sspp[] = {
- SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK,
- sm8550_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
- SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SC7180_MASK,
- sm8550_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
- SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SC7180_MASK,
+ SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x344, VIG_SC7180_MASK,
+ sm8550_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
+ SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x344, VIG_SC7180_MASK,
+ sm8550_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
+ SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x344, VIG_SC7180_MASK,
sm8550_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
- SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SC7180_MASK,
- sm8550_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
- SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
+ SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x344, VIG_SC7180_MASK,
+ sm8550_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
+ SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x344, DMA_SDM845_MASK,
sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
- SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK,
+ SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x344, DMA_SDM845_MASK,
sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
- SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_SDM845_MASK,
+ SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x344, DMA_SDM845_MASK,
sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
- SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_SDM845_MASK,
+ SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x344, DMA_SDM845_MASK,
sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
- SSPP_BLK("sspp_12", SSPP_DMA4, 0x2c000, DMA_CURSOR_SDM845_MASK,
+ SSPP_BLK("sspp_12", SSPP_DMA4, 0x2c000, 0x344, DMA_CURSOR_SDM845_MASK,
sm8550_dma_sblk_4, 14, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
- SSPP_BLK("sspp_13", SSPP_DMA5, 0x2e000, DMA_CURSOR_SDM845_MASK,
+ SSPP_BLK("sspp_13", SSPP_DMA5, 0x2e000, 0x344, DMA_CURSOR_SDM845_MASK,
sd8550_dma_sblk_5, 15, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
};
static const struct dpu_sspp_cfg sc7280_sspp[] = {
- SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7280_MASK,
+ SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1c8, VIG_SC7280_MASK,
sc7280_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
- SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
+ SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1c8, DMA_SDM845_MASK,
sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
- SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_CURSOR_SDM845_MASK,
+ SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1c8, DMA_CURSOR_SDM845_MASK,
sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
- SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
+ SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1c8, DMA_CURSOR_SDM845_MASK,
sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
};
@@ -1355,21 +1355,21 @@ static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_3 =
_VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3LITE);
static const struct dpu_sspp_cfg sc8280xp_sspp[] = {
- SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SM8250_MASK,
- sc8280xp_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
- SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SM8250_MASK,
- sc8280xp_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
- SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SM8250_MASK,
+ SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x280, VIG_SM8250_MASK,
+ sc8280xp_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
+ SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x280, VIG_SM8250_MASK,
+ sc8280xp_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
+ SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x280, VIG_SM8250_MASK,
sc8280xp_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
- SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SM8250_MASK,
- sc8280xp_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
- SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
+ SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x280, VIG_SM8250_MASK,
+ sc8280xp_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
+ SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x280, DMA_SDM845_MASK,
sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
- SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK,
+ SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x280, DMA_SDM845_MASK,
sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
- SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
+ SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x280, DMA_CURSOR_SDM845_MASK,
sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
- SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK,
+ SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x280, DMA_CURSOR_SDM845_MASK,
sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
};
@@ -1390,9 +1390,9 @@ static const struct dpu_sspp_sub_blks qcm2290_vig_sblk_0 = _VIG_SBLK_NOSCALE("0"
static const struct dpu_sspp_sub_blks qcm2290_dma_sblk_0 = _DMA_SBLK("8", 1);
static const struct dpu_sspp_cfg qcm2290_sspp[] = {
- SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_QCM2290_MASK,
+ SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_QCM2290_MASK,
qcm2290_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
- SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
+ SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
qcm2290_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
};
@@ -1848,10 +1848,10 @@ static struct dpu_dsc_cfg sm8150_dsc[] = {
/*************************************************************
* INTF sub blocks config
*************************************************************/
-#define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \
+#define INTF_BLK(_name, _id, _base, _len, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \
{\
.name = _name, .id = _id, \
- .base = _base, .len = 0x280, \
+ .base = _base, .len = _len, \
.features = _features, \
.type = _type, \
.controller_id = _ctrl_id, \
@@ -1861,85 +1861,85 @@ static struct dpu_dsc_cfg sm8150_dsc[] = {
}
static const struct dpu_intf_cfg msm8998_intf[] = {
- INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
- INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
- INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
- INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_HDMI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
+ INTF_BLK("intf_0", INTF_0, 0x6A000, 0x268, INTF_DP, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
+ INTF_BLK("intf_1", INTF_1, 0x6A800, 0x268, INTF_DSI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
+ INTF_BLK("intf_2", INTF_2, 0x6B000, 0x268, INTF_DSI, 1, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
+ INTF_BLK("intf_3", INTF_3, 0x6B800, 0x268, INTF_HDMI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
};
static const struct dpu_intf_cfg sdm845_intf[] = {
- INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
- INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
- INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
- INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
+ INTF_BLK("intf_0", INTF_0, 0x6A000, 0x280, INTF_DP, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
+ INTF_BLK("intf_1", INTF_1, 0x6A800, 0x280, INTF_DSI, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
+ INTF_BLK("intf_2", INTF_2, 0x6B000, 0x280, INTF_DSI, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
+ INTF_BLK("intf_3", INTF_3, 0x6B800, 0x280, INTF_DP, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
};
static const struct dpu_intf_cfg sc7180_intf[] = {
- INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
- INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
+ INTF_BLK("intf_0", INTF_0, 0x6A000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
+ INTF_BLK("intf_1", INTF_1, 0x6A800, 0x280, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
};
static const struct dpu_intf_cfg sm8150_intf[] = {
- INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
- INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
- INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
- INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
+ INTF_BLK("intf_0", INTF_0, 0x6A000, 0x280, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
+ INTF_BLK("intf_1", INTF_1, 0x6A800, 0x280, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
+ INTF_BLK("intf_2", INTF_2, 0x6B000, 0x280, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
+ INTF_BLK("intf_3", INTF_3, 0x6B800, 0x280, INTF_DP, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
};
static const struct dpu_intf_cfg sc7280_intf[] = {
- INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
- INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
- INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
+ INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
+ INTF_BLK("intf_1", INTF_1, 0x35000, 0x280, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
+ INTF_BLK("intf_5", INTF_5, 0x39000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
};
static const struct dpu_intf_cfg sm8350_intf[] = {
- INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
- INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
- INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
- INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
+ INTF_BLK("intf_0", INTF_0, 0x34000, 0x2c4, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
+ INTF_BLK("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
+ INTF_BLK("intf_2", INTF_2, 0x36000, 0x2c4, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
+ INTF_BLK("intf_3", INTF_3, 0x37000, 0x2c4, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
};
static const struct dpu_intf_cfg sc8180x_intf[] = {
- INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
- INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
- INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
+ INTF_BLK("intf_0", INTF_0, 0x6A000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
+ INTF_BLK("intf_1", INTF_1, 0x6A800, 0x280, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
+ INTF_BLK("intf_2", INTF_2, 0x6B000, 0x280, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
/* INTF_3 is for MST, wired to INTF_DP 0 and 1, use dummy index until this is supported */
- INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 999, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
- INTF_BLK("intf_4", INTF_4, 0x6C000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 20, 21),
- INTF_BLK("intf_5", INTF_5, 0x6C800, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
+ INTF_BLK("intf_3", INTF_3, 0x6B800, 0x280, INTF_DP, 999, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
+ INTF_BLK("intf_4", INTF_4, 0x6C000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 20, 21),
+ INTF_BLK("intf_5", INTF_5, 0x6C800, 0x280, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
};
/* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for now */
static const struct dpu_intf_cfg sc8280xp_intf[] = {
- INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
- INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
- INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
- INTF_BLK("intf_3", INTF_3, 0x37000, INTF_NONE, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
- INTF_BLK("intf_4", INTF_4, 0x38000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 20, 21),
- INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, MSM_DP_CONTROLLER_3, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
- INTF_BLK("intf_6", INTF_6, 0x3a000, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 16, 17),
- INTF_BLK("intf_7", INTF_7, 0x3b000, INTF_NONE, MSM_DP_CONTROLLER_2, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 18, 19),
- INTF_BLK("intf_8", INTF_8, 0x3c000, INTF_NONE, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 12, 13),
+ INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
+ INTF_BLK("intf_1", INTF_1, 0x35000, 0x280, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
+ INTF_BLK("intf_2", INTF_2, 0x36000, 0x280, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
+ INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_NONE, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
+ INTF_BLK("intf_4", INTF_4, 0x38000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 20, 21),
+ INTF_BLK("intf_5", INTF_5, 0x39000, 0x280, INTF_DP, MSM_DP_CONTROLLER_3, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
+ INTF_BLK("intf_6", INTF_6, 0x3a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 16, 17),
+ INTF_BLK("intf_7", INTF_7, 0x3b000, 0x280, INTF_NONE, MSM_DP_CONTROLLER_2, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 18, 19),
+ INTF_BLK("intf_8", INTF_8, 0x3c000, 0x280, INTF_NONE, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 12, 13),
};
static const struct dpu_intf_cfg qcm2290_intf[] = {
- INTF_BLK("intf_0", INTF_0, 0x00000, INTF_NONE, 0, 0, 0, 0, 0, 0),
- INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
+ INTF_BLK("intf_0", INTF_0, 0x00000, 0x2b8, INTF_NONE, 0, 0, 0, 0, 0, 0),
+ INTF_BLK("intf_1", INTF_1, 0x6A800, 0x2b8, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
};
static const struct dpu_intf_cfg sm8450_intf[] = {
- INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
- INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
- INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
- INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
+ INTF_BLK("intf_0", INTF_0, 0x34000, 0x2c4, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
+ INTF_BLK("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
+ INTF_BLK("intf_2", INTF_2, 0x36000, 0x2c4, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
+ INTF_BLK("intf_3", INTF_3, 0x37000, 0x2c4, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
};
static const struct dpu_intf_cfg sm8550_intf[] = {
- INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
+ INTF_BLK("intf_0", INTF_0, 0x34000, 0x300, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
/* TODO TE sub-blocks for intf1 & intf2 */
- INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
- INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
- INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
+ INTF_BLK("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
+ INTF_BLK("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
+ INTF_BLK("intf_3", INTF_3, 0x37000, 0x300, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
};
/*************************************************************
--
2.39.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 06/10] drm/msm/dpu: Add SM6350 support
[not found] <20230211122656.1479141-1-konrad.dybcio@linaro.org>
` (4 preceding siblings ...)
2023-02-11 12:26 ` [PATCH 05/10] drm/msm/dpu: Allow variable SSPP/INTF_BLK size Konrad Dybcio
@ 2023-02-11 12:26 ` Konrad Dybcio
2023-02-11 16:32 ` Dmitry Baryshkov
2023-02-11 12:26 ` [PATCH 07/10] drm/msm/dpu: Add SM6375 support Konrad Dybcio
` (3 subsequent siblings)
9 siblings, 1 reply; 36+ messages in thread
From: Konrad Dybcio @ 2023-02-11 12:26 UTC (permalink / raw)
To: linux-arm-msm, andersson, agross, krzysztof.kozlowski
Cc: marijn.suijten, Konrad Dybcio, Konrad Dybcio, Rob Clark,
Abhinav Kumar, Dmitry Baryshkov, Sean Paul, David Airlie,
Daniel Vetter, Robert Foss, AngeloGioacchino Del Regno,
Vinod Koul, Vinod Polimera, Stephen Boyd, Liu Shixin, dri-devel,
freedreno, linux-kernel
Add SM6350 support to the DPU1 driver to enable display output.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 187 ++++++++++++++++++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
drivers/gpu/drm/msm/msm_mdss.c | 2 +
4 files changed, 193 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index d9ef1e133c1e..ba0bc795e5ff 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -364,6 +364,25 @@ static const struct dpu_caps sm6115_dpu_caps = {
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
};
+static const struct dpu_caps sm6350_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0x7,
+ .qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
+ .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
+ .ubwc_version = DPU_HW_UBWC_VER_20,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ /*
+ * There is *NO* 3DMERGE hw, but we *need* to set this property to true,
+ * because SM6350 includes newer hardware that requires a different reset
+ * sequence and it is executed based on this confusingly named variable..
+ */
+ .has_3d_merge = true,
+ .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
static const struct dpu_caps sm8150_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
@@ -554,6 +573,25 @@ static const struct dpu_mdp_cfg sc7180_mdp[] = {
},
};
+static const struct dpu_mdp_cfg sm6350_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0x0, .len = 0x494,
+ .features = 0,
+ .highest_bank_bit = 0x1,
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
+ .reg_off = 0x2ac, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
+ .reg_off = 0x2ac, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
+ .reg_off = 0x2b4, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
+ .reg_off = 0x2c4, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
+ .reg_off = 0x2bc, .bit_off = 20},
+ },
+};
+
static const struct dpu_mdp_cfg sc8180x_mdp[] = {
{
.name = "top_0", .id = MDP_TOP,
@@ -888,6 +926,33 @@ static const struct dpu_ctl_cfg sc8280xp_ctl[] = {
},
};
+static const struct dpu_ctl_cfg sm6350_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ },
+ {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x1200, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ },
+ {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x1400, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ },
+ {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x1600, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ },
+};
+
static const struct dpu_ctl_cfg sm8150_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
@@ -1244,6 +1309,20 @@ static const struct dpu_sspp_cfg sm6115_sspp[] = {
sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
};
+static const struct dpu_sspp_sub_blks sm6350_vig_sblk_0 =
+ _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED3LITE);
+
+static const struct dpu_sspp_cfg sm6350_sspp[] = {
+ SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SM8250_MASK,
+ sm6350_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
+ SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
+ sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
+ SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
+ sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
+ SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
+ sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
+};
+
static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 =
_VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE);
static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 =
@@ -1491,6 +1570,13 @@ static const struct dpu_lm_cfg sc8280xp_lm[] = {
LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
};
+static const struct dpu_lm_cfg sm6350_lm[] = {
+ LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
+ &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
+ LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
+ &sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
+};
+
/* SM8150 */
static const struct dpu_lm_cfg sm8150_lm[] = {
@@ -1572,6 +1658,11 @@ static const struct dpu_dspp_cfg sc7180_dspp[] = {
&sc7180_dspp_sblk),
};
+static const struct dpu_dspp_cfg sm6350_dspp[] = {
+ DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
+ &sm8150_dspp_sblk),
+};
+
static const struct dpu_dspp_cfg sm8150_dspp[] = {
DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
&sm8150_dspp_sblk),
@@ -1674,6 +1765,15 @@ static struct dpu_pingpong_cfg sc8280xp_pp[] = {
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), -1),
};
+static struct dpu_pingpong_cfg sm6350_pp[] = {
+ PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
+ PP_BLK("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
+};
+
static const struct dpu_pingpong_cfg sm8150_pp[] = {
PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk_te,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
@@ -1879,6 +1979,11 @@ static const struct dpu_intf_cfg sc7180_intf[] = {
INTF_BLK("intf_1", INTF_1, 0x6A800, 0x280, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
};
+static const struct dpu_intf_cfg sm6350_intf[] = {
+ INTF_BLK("intf_0", INTF_0, 0x6a000, 0x2c0, INTF_DP, 0, 35, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
+ INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 35, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
+};
+
static const struct dpu_intf_cfg sm8150_intf[] = {
INTF_BLK("intf_0", INTF_0, 0x6A000, 0x280, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
INTF_BLK("intf_1", INTF_1, 0x6A800, 0x280, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
@@ -2039,6 +2144,25 @@ static const struct dpu_vbif_cfg sdm845_vbif[] = {
},
};
+static const struct dpu_vbif_cfg sm6350_vbif[] = {
+ {
+ .name = "vbif_0", .id = VBIF_RT,
+ .base = 0, .len = 0x1044,
+ .features = BIT(DPU_VBIF_QOS_REMAP),
+ .xin_halt_timeout = 0x4000,
+ .qos_rt_tbl = {
+ .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
+ .priority_lvl = sdm845_rt_pri_lvl,
+ },
+ .qos_nrt_tbl = {
+ .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
+ .priority_lvl = sdm845_nrt_pri_lvl,
+ },
+ .memtype_count = 14,
+ .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
+ },
+};
+
static const struct dpu_reg_dma_cfg sc8280xp_regdma = {
.base = 0x0,
.version = 0x00020000,
@@ -2128,6 +2252,11 @@ static const struct dpu_qos_lut_entry sc7180_qos_linear[] = {
{.fl = 0, .lut = 0x0011222222335777},
};
+static const struct dpu_qos_lut_entry sm6350_qos_linear[] = {
+ {.fl = 0, .lut = 0x0011223344556677 },
+ {.fl = 0, .lut = 0x0011223445566777 },
+};
+
static const struct dpu_qos_lut_entry sm8150_qos_linear[] = {
{.fl = 0, .lut = 0x0011222222223357 },
};
@@ -2153,6 +2282,11 @@ static const struct dpu_qos_lut_entry sc7180_qos_macrotile[] = {
{.fl = 0, .lut = 0x0011223344556677},
};
+static const struct dpu_qos_lut_entry sm6350_qos_macrotile[] = {
+ {.fl = 0, .lut = 0x0011223344556677 },
+ {.fl = 0, .lut = 0x0011223445566777 },
+};
+
static const struct dpu_qos_lut_entry sc8180x_qos_macrotile[] = {
{.fl = 10, .lut = 0x0000000344556677},
};
@@ -2298,6 +2432,34 @@ static const struct dpu_perf_cfg sm6115_perf_data = {
.bw_inefficiency_factor = 120,
};
+static const struct dpu_perf_cfg sm6350_perf_data = {
+ .max_bw_low = 4200000,
+ .max_bw_high = 5100000,
+ .min_core_ib = 2500000,
+ .min_llcc_ib = 0,
+ .min_dram_ib = 1600000,
+ .min_prefill_lines = 35,
+ /* TODO: confirm danger_lut_tbl */
+ .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
+ .qos_lut_tbl = {
+ {.nentry = ARRAY_SIZE(sm6350_qos_linear),
+ .entries = sm6350_qos_linear
+ },
+ {.nentry = ARRAY_SIZE(sm6350_qos_macrotile),
+ .entries = sm6350_qos_macrotile
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
+ .entries = sc7180_qos_nrt
+ },
+ },
+ .cdp_cfg = {
+ {.rd_enable = 1, .wr_enable = 1},
+ {.rd_enable = 1, .wr_enable = 0}
+ },
+ .clk_inefficiency_factor = 105,
+ .bw_inefficiency_factor = 120,
+};
+
static const struct dpu_perf_cfg sm8150_perf_data = {
.max_bw_low = 12800000,
.max_bw_high = 12800000,
@@ -2618,6 +2780,30 @@ static const struct dpu_mdss_cfg sm6115_dpu_cfg = {
.mdss_irqs = IRQ_SC7180_MASK,
};
+static const struct dpu_mdss_cfg sm6350_dpu_cfg = {
+ .caps = &sm6350_dpu_caps,
+ .mdp_count = ARRAY_SIZE(sm6350_mdp),
+ .mdp = sm6350_mdp,
+ .ctl_count = ARRAY_SIZE(sm6350_ctl),
+ .ctl = sm6350_ctl,
+ .sspp_count = ARRAY_SIZE(sm6350_sspp),
+ .sspp = sm6350_sspp,
+ .mixer_count = ARRAY_SIZE(sm6350_lm),
+ .mixer = sm6350_lm,
+ .dspp_count = ARRAY_SIZE(sm6350_dspp),
+ .dspp = sm6350_dspp,
+ .pingpong_count = ARRAY_SIZE(sm6350_pp),
+ .pingpong = sm6350_pp,
+ .intf_count = ARRAY_SIZE(sm6350_intf),
+ .intf = sm6350_intf,
+ .vbif_count = ARRAY_SIZE(sm6350_vbif),
+ .vbif = sm6350_vbif,
+ .reg_dma_count = 1,
+ .dma_cfg = &sm8250_regdma,
+ .perf = &sm6350_perf_data,
+ .mdss_irqs = IRQ_SC7180_MASK,
+};
+
static const struct dpu_mdss_cfg sm8150_dpu_cfg = {
.caps = &sm8150_dpu_caps,
.mdp_count = ARRAY_SIZE(sdm845_mdp),
@@ -2861,6 +3047,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
{ .hw_rev = DPU_HW_VER_600, .dpu_cfg = &sm8250_dpu_cfg},
{ .hw_rev = DPU_HW_VER_620, .dpu_cfg = &sc7180_dpu_cfg},
{ .hw_rev = DPU_HW_VER_630, .dpu_cfg = &sm6115_dpu_cfg},
+ { .hw_rev = DPU_HW_VER_640, .dpu_cfg = &sm6350_dpu_cfg},
{ .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg},
{ .hw_rev = DPU_HW_VER_700, .dpu_cfg = &sm8350_dpu_cfg},
{ .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg},
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index c7a2e6237d2b..cbf21613e121 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -45,6 +45,7 @@
#define DPU_HW_VER_600 DPU_HW_VER(6, 0, 0) /* sm8250 */
#define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */
#define DPU_HW_VER_630 DPU_HW_VER(6, 3, 0) /* sm6115|sm4250 */
+#define DPU_HW_VER_640 DPU_HW_VER(6, 4, 0) /* sm6350 */
#define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */
#define DPU_HW_VER_700 DPU_HW_VER(7, 0, 0) /* sm8350 */
#define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */
@@ -352,6 +353,8 @@ enum dpu_qos_lut_usage {
DPU_QOS_LUT_USAGE_LINEAR,
DPU_QOS_LUT_USAGE_MACROTILE,
DPU_QOS_LUT_USAGE_NRT,
+ DPU_QOS_LUT_USAGE_CWB,
+ DPU_QOS_LUT_USAGE_MACROTILE_QSEED,
DPU_QOS_LUT_USAGE_MAX,
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index a683bd9b5a04..ebfbbd2d105e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1306,6 +1306,7 @@ static const struct of_device_id dpu_dt_match[] = {
{ .compatible = "qcom,sc8180x-dpu", },
{ .compatible = "qcom,sc8280xp-dpu", },
{ .compatible = "qcom,sm6115-dpu", },
+ { .compatible = "qcom,sm6350-dpu", },
{ .compatible = "qcom,sm8150-dpu", },
{ .compatible = "qcom,sm8250-dpu", },
{ .compatible = "qcom,sm8350-dpu", },
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 02646e4bb4cd..841016f3983a 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -279,6 +279,7 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss)
msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 3, 1);
break;
case DPU_HW_VER_620:
+ case DPU_HW_VER_640:
/* UBWC_2_0 */
msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x1e);
break;
@@ -529,6 +530,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,sc8180x-mdss" },
{ .compatible = "qcom,sc8280xp-mdss" },
{ .compatible = "qcom,sm6115-mdss" },
+ { .compatible = "qcom,sm6350-mdss" },
{ .compatible = "qcom,sm8150-mdss" },
{ .compatible = "qcom,sm8250-mdss" },
{ .compatible = "qcom,sm8350-mdss" },
--
2.39.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 07/10] drm/msm/dpu: Add SM6375 support
[not found] <20230211122656.1479141-1-konrad.dybcio@linaro.org>
` (5 preceding siblings ...)
2023-02-11 12:26 ` [PATCH 06/10] drm/msm/dpu: Add SM6350 support Konrad Dybcio
@ 2023-02-11 12:26 ` Konrad Dybcio
2023-02-11 16:47 ` Dmitry Baryshkov
2023-02-11 12:26 ` [PATCH 08/10] iommu/arm-smmu-qcom: Add SM6375 DPU compatible Konrad Dybcio
` (2 subsequent siblings)
9 siblings, 1 reply; 36+ messages in thread
From: Konrad Dybcio @ 2023-02-11 12:26 UTC (permalink / raw)
To: linux-arm-msm, andersson, agross, krzysztof.kozlowski
Cc: marijn.suijten, Konrad Dybcio, Rob Clark, Abhinav Kumar,
Dmitry Baryshkov, Sean Paul, David Airlie, Daniel Vetter,
Robert Foss, AngeloGioacchino Del Regno, Vinod Koul,
Vinod Polimera, Stephen Boyd, Liu Shixin, dri-devel, freedreno,
linux-kernel
Add basic SM6375 support to the DPU1 driver to enable display output.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 120 ++++++++++++++++++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
drivers/gpu/drm/msm/msm_mdss.c | 1 +
4 files changed, 123 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index ba0bc795e5ff..327aa21f01fc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -383,6 +383,24 @@ static const struct dpu_caps sm6350_dpu_caps = {
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
};
+static const struct dpu_caps sm6375_dpu_caps = {
+ .max_mixer_width = 2048,
+ .max_mixer_blendstages = 0x4,
+ .qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
+ .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
+ .ubwc_version = DPU_HW_UBWC_VER_20,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ /*
+ * There is *NO* 3DMERGE hw, but we *need* to set this property to true,
+ * because SM6375 includes newer hardware that requires a different reset
+ * sequence and it is executed based on this confusingly named variable..
+ */
+ .has_3d_merge = true,
+ .max_linewidth = 2160,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
static const struct dpu_caps sm8150_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
@@ -592,6 +610,19 @@ static const struct dpu_mdp_cfg sm6350_mdp[] = {
},
};
+static const struct dpu_mdp_cfg sm6375_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0x0, .len = 0x494,
+ .features = 0,
+ .highest_bank_bit = 0x1,
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
+ .reg_off = 0x2ac, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
+ .reg_off = 0x2ac, .bit_off = 8},
+ },
+};
+
static const struct dpu_mdp_cfg sc8180x_mdp[] = {
{
.name = "top_0", .id = MDP_TOP,
@@ -1577,6 +1608,19 @@ static const struct dpu_lm_cfg sm6350_lm[] = {
&sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
};
+static const struct dpu_lm_sub_blks sm6375_lm_sblk = {
+ .maxwidth = 2048,
+ .maxblendstages = 4, /* excluding base layer */
+ .blendstage_base = { /* offsets relative to mixer base */
+ 0x20, 0x38, 0x50, 0x68
+ },
+};
+
+static const struct dpu_lm_cfg sm6375_lm[] = {
+ LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
+ &sm6375_lm_sblk, PINGPONG_0, 0, DSPP_0),
+};
+
/* SM8150 */
static const struct dpu_lm_cfg sm8150_lm[] = {
@@ -1984,6 +2028,11 @@ static const struct dpu_intf_cfg sm6350_intf[] = {
INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 35, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
};
+static const struct dpu_intf_cfg sm6375_intf[] = {
+ INTF_BLK("intf_0", INTF_0, 0x00000, 0x2c0, INTF_NONE, 0, 0, 0, 0, 0, 0),
+ INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
+};
+
static const struct dpu_intf_cfg sm8150_intf[] = {
INTF_BLK("intf_0", INTF_0, 0x6A000, 0x280, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
INTF_BLK("intf_1", INTF_1, 0x6A800, 0x280, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
@@ -2171,6 +2220,26 @@ static const struct dpu_reg_dma_cfg sc8280xp_regdma = {
.clk_ctrl = DPU_CLK_CTRL_REG_DMA,
};
+static const struct dpu_vbif_cfg sm6375_vbif[] = {
+ {
+ .name = "vbif_0", .id = VBIF_RT,
+ .base = 0, .len = 0x2008,
+ .features = BIT(DPU_VBIF_QOS_REMAP),
+ .xin_halt_timeout = 0x4000,
+ .qos_rp_remap_size = 0x40,
+ .qos_rt_tbl = {
+ .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
+ .priority_lvl = sdm845_rt_pri_lvl,
+ },
+ .qos_nrt_tbl = {
+ .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
+ .priority_lvl = sdm845_nrt_pri_lvl,
+ },
+ .memtype_count = 14,
+ .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
+ },
+};
+
static const struct dpu_reg_dma_cfg sdm845_regdma = {
.base = 0x0, .version = 0x1, .trigger_sel_off = 0x119c
};
@@ -2460,6 +2529,34 @@ static const struct dpu_perf_cfg sm6350_perf_data = {
.bw_inefficiency_factor = 120,
};
+static const struct dpu_perf_cfg sm6375_perf_data = {
+ .max_bw_low = 5200000,
+ .max_bw_high = 6200000,
+ .min_core_ib = 2500000,
+ .min_llcc_ib = 0,
+ .min_dram_ib = 1600000,
+ .min_prefill_lines = 24,
+ /* TODO: confirm danger_lut_tbl */
+ .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
+ .qos_lut_tbl = {
+ {.nentry = ARRAY_SIZE(sm6350_qos_linear),
+ .entries = sm6350_qos_linear
+ },
+ {.nentry = ARRAY_SIZE(sm6350_qos_macrotile),
+ .entries = sm6350_qos_macrotile
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
+ .entries = sc7180_qos_nrt
+ },
+ },
+ .cdp_cfg = {
+ {.rd_enable = 1, .wr_enable = 1},
+ {.rd_enable = 1, .wr_enable = 0}
+ },
+ .clk_inefficiency_factor = 105,
+ .bw_inefficiency_factor = 120,
+};
+
static const struct dpu_perf_cfg sm8150_perf_data = {
.max_bw_low = 12800000,
.max_bw_high = 12800000,
@@ -2804,6 +2901,28 @@ static const struct dpu_mdss_cfg sm6350_dpu_cfg = {
.mdss_irqs = IRQ_SC7180_MASK,
};
+static const struct dpu_mdss_cfg sm6375_dpu_cfg = {
+ .caps = &sm6350_dpu_caps,
+ .mdp_count = ARRAY_SIZE(sm6375_mdp),
+ .mdp = sm6375_mdp,
+ .ctl_count = ARRAY_SIZE(qcm2290_ctl),
+ .ctl = qcm2290_ctl,
+ .sspp_count = ARRAY_SIZE(sm6115_sspp),
+ .sspp = sm6115_sspp,
+ .mixer_count = ARRAY_SIZE(sm6375_lm),
+ .mixer = sm6375_lm,
+ .dspp_count = ARRAY_SIZE(qcm2290_dspp),
+ .dspp = qcm2290_dspp,
+ .pingpong_count = ARRAY_SIZE(qcm2290_pp),
+ .pingpong = qcm2290_pp,
+ .intf_count = ARRAY_SIZE(sm6375_intf),
+ .intf = sm6375_intf,
+ .vbif_count = ARRAY_SIZE(sm6375_vbif),
+ .vbif = sm6375_vbif,
+ .perf = &sm6375_perf_data,
+ .mdss_irqs = IRQ_SC7180_MASK,
+};
+
static const struct dpu_mdss_cfg sm8150_dpu_cfg = {
.caps = &sm8150_dpu_caps,
.mdp_count = ARRAY_SIZE(sdm845_mdp),
@@ -3049,6 +3168,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
{ .hw_rev = DPU_HW_VER_630, .dpu_cfg = &sm6115_dpu_cfg},
{ .hw_rev = DPU_HW_VER_640, .dpu_cfg = &sm6350_dpu_cfg},
{ .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg},
+ { .hw_rev = DPU_HW_VER_690, .dpu_cfg = &sm6375_dpu_cfg},
{ .hw_rev = DPU_HW_VER_700, .dpu_cfg = &sm8350_dpu_cfg},
{ .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg},
{ .hw_rev = DPU_HW_VER_800, .dpu_cfg = &sc8280xp_dpu_cfg},
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index cbf21613e121..a22b5965acfe 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -47,6 +47,7 @@
#define DPU_HW_VER_630 DPU_HW_VER(6, 3, 0) /* sm6115|sm4250 */
#define DPU_HW_VER_640 DPU_HW_VER(6, 4, 0) /* sm6350 */
#define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */
+#define DPU_HW_VER_690 DPU_HW_VER(6, 9, 0) /* sm6375 */
#define DPU_HW_VER_700 DPU_HW_VER(7, 0, 0) /* sm8350 */
#define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */
#define DPU_HW_VER_800 DPU_HW_VER(8, 0, 0) /* sc8280xp */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index ebfbbd2d105e..fd561974a6b1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1307,6 +1307,7 @@ static const struct of_device_id dpu_dt_match[] = {
{ .compatible = "qcom,sc8280xp-dpu", },
{ .compatible = "qcom,sm6115-dpu", },
{ .compatible = "qcom,sm6350-dpu", },
+ { .compatible = "qcom,sm6375-dpu", },
{ .compatible = "qcom,sm8150-dpu", },
{ .compatible = "qcom,sm8250-dpu", },
{ .compatible = "qcom,sm8350-dpu", },
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 841016f3983a..fedc1a1fc289 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -531,6 +531,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,sc8280xp-mdss" },
{ .compatible = "qcom,sm6115-mdss" },
{ .compatible = "qcom,sm6350-mdss" },
+ { .compatible = "qcom,sm6375-mdss" },
{ .compatible = "qcom,sm8150-mdss" },
{ .compatible = "qcom,sm8250-mdss" },
{ .compatible = "qcom,sm8350-mdss" },
--
2.39.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 08/10] iommu/arm-smmu-qcom: Add SM6375 DPU compatible
[not found] <20230211122656.1479141-1-konrad.dybcio@linaro.org>
` (6 preceding siblings ...)
2023-02-11 12:26 ` [PATCH 07/10] drm/msm/dpu: Add SM6375 support Konrad Dybcio
@ 2023-02-11 12:26 ` Konrad Dybcio
2023-02-11 12:26 ` [PATCH 09/10] iommu/arm-smmu-qcom: Add SM6350 " Konrad Dybcio
2023-02-11 12:26 ` [PATCH 10/10] iommu/arm-smmu-qcom: Sort the compatible list alphabetically Konrad Dybcio
9 siblings, 0 replies; 36+ messages in thread
From: Konrad Dybcio @ 2023-02-11 12:26 UTC (permalink / raw)
To: linux-arm-msm, andersson, agross, krzysztof.kozlowski
Cc: marijn.suijten, Konrad Dybcio, Will Deacon, Robin Murphy,
Joerg Roedel, Konrad Dybcio, Dmitry Baryshkov,
Sai Prakash Ranjan, Bjorn Andersson, Emma Anholt,
Adam Skladowski, linux-arm-kernel, iommu, linux-kernel
Add the SM6375 DPU compatible to clients compatible list, as it also
needs the workarounds.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index d1b296b95c86..7425424da974 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -255,6 +255,7 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
{ .compatible = "qcom,sm8250-mdss" },
{ .compatible = "qcom,sdm845-mdss" },
{ .compatible = "qcom,sdm845-mss-pil" },
+ { .compatible = "qcom,sm6375-mdss" },
{ }
};
--
2.39.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 09/10] iommu/arm-smmu-qcom: Add SM6350 DPU compatible
[not found] <20230211122656.1479141-1-konrad.dybcio@linaro.org>
` (7 preceding siblings ...)
2023-02-11 12:26 ` [PATCH 08/10] iommu/arm-smmu-qcom: Add SM6375 DPU compatible Konrad Dybcio
@ 2023-02-11 12:26 ` Konrad Dybcio
2023-02-11 12:26 ` [PATCH 10/10] iommu/arm-smmu-qcom: Sort the compatible list alphabetically Konrad Dybcio
9 siblings, 0 replies; 36+ messages in thread
From: Konrad Dybcio @ 2023-02-11 12:26 UTC (permalink / raw)
To: linux-arm-msm, andersson, agross, krzysztof.kozlowski
Cc: marijn.suijten, Konrad Dybcio, Konrad Dybcio, Will Deacon,
Robin Murphy, Joerg Roedel, Dmitry Baryshkov, Sai Prakash Ranjan,
Bjorn Andersson, Melody Olvera, linux-arm-kernel, iommu,
linux-kernel
From: Konrad Dybcio <konrad.dybcio@somainline.org>
Add the SM6350 DPU compatible to clients compatible list, as it also
needs the workarounds.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 7425424da974..959516bbfe65 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -255,6 +255,7 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
{ .compatible = "qcom,sm8250-mdss" },
{ .compatible = "qcom,sdm845-mdss" },
{ .compatible = "qcom,sdm845-mss-pil" },
+ { .compatible = "qcom,sm6350-mdss" },
{ .compatible = "qcom,sm6375-mdss" },
{ }
};
--
2.39.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 10/10] iommu/arm-smmu-qcom: Sort the compatible list alphabetically
[not found] <20230211122656.1479141-1-konrad.dybcio@linaro.org>
` (8 preceding siblings ...)
2023-02-11 12:26 ` [PATCH 09/10] iommu/arm-smmu-qcom: Add SM6350 " Konrad Dybcio
@ 2023-02-11 12:26 ` Konrad Dybcio
9 siblings, 0 replies; 36+ messages in thread
From: Konrad Dybcio @ 2023-02-11 12:26 UTC (permalink / raw)
To: linux-arm-msm, andersson, agross, krzysztof.kozlowski
Cc: marijn.suijten, Konrad Dybcio, Will Deacon, Robin Murphy,
Joerg Roedel, Konrad Dybcio, Dmitry Baryshkov,
Sai Prakash Ranjan, Bjorn Andersson, linux-arm-kernel, iommu,
linux-kernel
It got broken at some point, fix it up.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 959516bbfe65..d49cf7e0a777 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -251,10 +251,10 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
{ .compatible = "qcom,sc7280-mss-pil" },
{ .compatible = "qcom,sc8180x-mdss" },
{ .compatible = "qcom,sc8280xp-mdss" },
- { .compatible = "qcom,sm8150-mdss" },
- { .compatible = "qcom,sm8250-mdss" },
{ .compatible = "qcom,sdm845-mdss" },
{ .compatible = "qcom,sdm845-mss-pil" },
+ { .compatible = "qcom,sm8150-mdss" },
+ { .compatible = "qcom,sm8250-mdss" },
{ .compatible = "qcom,sm6350-mdss" },
{ .compatible = "qcom,sm6375-mdss" },
{ }
--
2.39.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [PATCH 06/10] drm/msm/dpu: Add SM6350 support
2023-02-11 12:26 ` [PATCH 06/10] drm/msm/dpu: Add SM6350 support Konrad Dybcio
@ 2023-02-11 16:32 ` Dmitry Baryshkov
2023-02-13 11:15 ` Konrad Dybcio
0 siblings, 1 reply; 36+ messages in thread
From: Dmitry Baryshkov @ 2023-02-11 16:32 UTC (permalink / raw)
To: Konrad Dybcio, linux-arm-msm, andersson, agross, krzysztof.kozlowski
Cc: marijn.suijten, Konrad Dybcio, Rob Clark, Abhinav Kumar,
Sean Paul, David Airlie, Daniel Vetter, Robert Foss,
AngeloGioacchino Del Regno, Vinod Koul, Vinod Polimera,
Stephen Boyd, Liu Shixin, dri-devel, freedreno, linux-kernel
On 11/02/2023 14:26, Konrad Dybcio wrote:
> Add SM6350 support to the DPU1 driver to enable display output.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 187 ++++++++++++++++++
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
> drivers/gpu/drm/msm/msm_mdss.c | 2 +
> 4 files changed, 193 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index d9ef1e133c1e..ba0bc795e5ff 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -364,6 +364,25 @@ static const struct dpu_caps sm6115_dpu_caps = {
> .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> };
>
> +static const struct dpu_caps sm6350_dpu_caps = {
> + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> + .max_mixer_blendstages = 0x7,
> + .qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
QSEED4
> + .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
> + .ubwc_version = DPU_HW_UBWC_VER_20,
> + .has_src_split = true,
> + .has_dim_layer = true,
> + .has_idle_pc = true,
> + /*
> + * There is *NO* 3DMERGE hw, but we *need* to set this property to true,
> + * because SM6350 includes newer hardware that requires a different reset
> + * sequence and it is executed based on this confusingly named variable..
> + */
Which reset sequence is that? Is it something that was not posted yet?
> + .has_3d_merge = true,
> + .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> +};
> +
> static const struct dpu_caps sm8150_dpu_caps = {
> .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> .max_mixer_blendstages = 0xb,
> @@ -554,6 +573,25 @@ static const struct dpu_mdp_cfg sc7180_mdp[] = {
> },
> };
>
> +static const struct dpu_mdp_cfg sm6350_mdp[] = {
> + {
> + .name = "top_0", .id = MDP_TOP,
> + .base = 0x0, .len = 0x494,
> + .features = 0,
> + .highest_bank_bit = 0x1,
> + .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
> + .reg_off = 0x2ac, .bit_off = 0},
> + .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
> + .reg_off = 0x2ac, .bit_off = 8},
> + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
DPU_CLK_CTRL_DMA1
> + .reg_off = 0x2b4, .bit_off = 8},
> + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
DPU_CLK_CTRL_DMA2
> + .reg_off = 0x2c4, .bit_off = 8},
> + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
> + .reg_off = 0x2bc, .bit_off = 20},
> + },
Please fit them into a single line
> +};
> +
> static const struct dpu_mdp_cfg sc8180x_mdp[] = {
> {
> .name = "top_0", .id = MDP_TOP,
> @@ -888,6 +926,33 @@ static const struct dpu_ctl_cfg sc8280xp_ctl[] = {
> },
> };
>
> +static const struct dpu_ctl_cfg sm6350_ctl[] = {
We need to fix sc7180_ctl[].len, then we can use it here instead.
> + {
> + .name = "ctl_0", .id = CTL_0,
> + .base = 0x1000, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> + },
> + {
> + .name = "ctl_1", .id = CTL_1,
> + .base = 0x1200, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> + },
> + {
> + .name = "ctl_2", .id = CTL_2,
> + .base = 0x1400, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> + },
> + {
> + .name = "ctl_3", .id = CTL_3,
> + .base = 0x1600, .len = 0x1dc,
> + .features = BIT(DPU_CTL_ACTIVE_CFG),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> + },
> +};
> +
> static const struct dpu_ctl_cfg sm8150_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
> @@ -1244,6 +1309,20 @@ static const struct dpu_sspp_cfg sm6115_sspp[] = {
> sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> };
>
> +static const struct dpu_sspp_sub_blks sm6350_vig_sblk_0 =
> + _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED3LITE);
QSEED4
> +
> +static const struct dpu_sspp_cfg sm6350_sspp[] = {
> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SM8250_MASK,
> + sm6350_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
> + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
> + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
DPU_CLK_CTRL_DMA1
> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
> + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
DPU_CLK_CTRL_DMA2
> +};
> +
> static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 =
> _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE);
> static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 =
> @@ -1491,6 +1570,13 @@ static const struct dpu_lm_cfg sc8280xp_lm[] = {
> LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
> };
>
> +static const struct dpu_lm_cfg sm6350_lm[] = {
I think we can use sc7180_lm here
> + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
> + &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
> + LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
> + &sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
> +};
> +
> /* SM8150 */
>
> static const struct dpu_lm_cfg sm8150_lm[] = {
> @@ -1572,6 +1658,11 @@ static const struct dpu_dspp_cfg sc7180_dspp[] = {
> &sc7180_dspp_sblk),
> };
>
> +static const struct dpu_dspp_cfg sm6350_dspp[] = {
sc7180_dspp
> + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
> + &sm8150_dspp_sblk),
> +};
> +
> static const struct dpu_dspp_cfg sm8150_dspp[] = {
> DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
> &sm8150_dspp_sblk),
> @@ -1674,6 +1765,15 @@ static struct dpu_pingpong_cfg sc8280xp_pp[] = {
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), -1),
> };
>
> +static struct dpu_pingpong_cfg sm6350_pp[] = {
> + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk,
No TE support?
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
> + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
> +};
> +
> static const struct dpu_pingpong_cfg sm8150_pp[] = {
> PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk_te,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> @@ -1879,6 +1979,11 @@ static const struct dpu_intf_cfg sc7180_intf[] = {
> INTF_BLK("intf_1", INTF_1, 0x6A800, 0x280, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> };
>
> +static const struct dpu_intf_cfg sm6350_intf[] = {
Interesting. Size is 0x2b8 for sc7180 (if I'm not mistaken), but 0x2c0
for sm6350. Do you know by chance what's the difference?
> + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x2c0, INTF_DP, 0, 35, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> + INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 35, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> +};
> +
> static const struct dpu_intf_cfg sm8150_intf[] = {
> INTF_BLK("intf_0", INTF_0, 0x6A000, 0x280, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> INTF_BLK("intf_1", INTF_1, 0x6A800, 0x280, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> @@ -2039,6 +2144,25 @@ static const struct dpu_vbif_cfg sdm845_vbif[] = {
> },
> };
>
> +static const struct dpu_vbif_cfg sm6350_vbif[] = {
> + {
> + .name = "vbif_0", .id = VBIF_RT,
> + .base = 0, .len = 0x1044,
So, the only difference from sdm845_vbif is the len? Can we ignore it?
> + .features = BIT(DPU_VBIF_QOS_REMAP),
> + .xin_halt_timeout = 0x4000,
> + .qos_rt_tbl = {
> + .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
> + .priority_lvl = sdm845_rt_pri_lvl,
> + },
> + .qos_nrt_tbl = {
> + .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
> + .priority_lvl = sdm845_nrt_pri_lvl,
> + },
> + .memtype_count = 14,
> + .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
> + },
> +};
> +
> static const struct dpu_reg_dma_cfg sc8280xp_regdma = {
> .base = 0x0,
> .version = 0x00020000,
> @@ -2128,6 +2252,11 @@ static const struct dpu_qos_lut_entry sc7180_qos_linear[] = {
> {.fl = 0, .lut = 0x0011222222335777},
> };
>
Two LUT entries with the same fill level sound strange. Yes, I see the
same in the vendor dts. Let me check how they are parsend and used.
> +static const struct dpu_qos_lut_entry sm6350_qos_linear[] = {
> + {.fl = 0, .lut = 0x0011223344556677 },
> + {.fl = 0, .lut = 0x0011223445566777 },
> +};
> +
> static const struct dpu_qos_lut_entry sm8150_qos_linear[] = {
> {.fl = 0, .lut = 0x0011222222223357 },
> };
> @@ -2153,6 +2282,11 @@ static const struct dpu_qos_lut_entry sc7180_qos_macrotile[] = {
> {.fl = 0, .lut = 0x0011223344556677},
> };
>
> +static const struct dpu_qos_lut_entry sm6350_qos_macrotile[] = {
> + {.fl = 0, .lut = 0x0011223344556677 },
> + {.fl = 0, .lut = 0x0011223445566777 },
> +};
> +
> static const struct dpu_qos_lut_entry sc8180x_qos_macrotile[] = {
> {.fl = 10, .lut = 0x0000000344556677},
> };
> @@ -2298,6 +2432,34 @@ static const struct dpu_perf_cfg sm6115_perf_data = {
> .bw_inefficiency_factor = 120,
> };
>
> +static const struct dpu_perf_cfg sm6350_perf_data = {
> + .max_bw_low = 4200000,
> + .max_bw_high = 5100000,
> + .min_core_ib = 2500000,
> + .min_llcc_ib = 0,
> + .min_dram_ib = 1600000,
> + .min_prefill_lines = 35,
> + /* TODO: confirm danger_lut_tbl */
> + .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
> + .qos_lut_tbl = {
> + {.nentry = ARRAY_SIZE(sm6350_qos_linear),
> + .entries = sm6350_qos_linear
> + },
> + {.nentry = ARRAY_SIZE(sm6350_qos_macrotile),
> + .entries = sm6350_qos_macrotile
> + },
> + {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
> + .entries = sc7180_qos_nrt
> + },
> + },
> + .cdp_cfg = {
> + {.rd_enable = 1, .wr_enable = 1},
> + {.rd_enable = 1, .wr_enable = 0}
> + },
> + .clk_inefficiency_factor = 105,
> + .bw_inefficiency_factor = 120,
> +};
> +
> static const struct dpu_perf_cfg sm8150_perf_data = {
> .max_bw_low = 12800000,
> .max_bw_high = 12800000,
> @@ -2618,6 +2780,30 @@ static const struct dpu_mdss_cfg sm6115_dpu_cfg = {
> .mdss_irqs = IRQ_SC7180_MASK,
> };
>
> +static const struct dpu_mdss_cfg sm6350_dpu_cfg = {
> + .caps = &sm6350_dpu_caps,
> + .mdp_count = ARRAY_SIZE(sm6350_mdp),
> + .mdp = sm6350_mdp,
> + .ctl_count = ARRAY_SIZE(sm6350_ctl),
> + .ctl = sm6350_ctl,
> + .sspp_count = ARRAY_SIZE(sm6350_sspp),
> + .sspp = sm6350_sspp,
> + .mixer_count = ARRAY_SIZE(sm6350_lm),
> + .mixer = sm6350_lm,
> + .dspp_count = ARRAY_SIZE(sm6350_dspp),
> + .dspp = sm6350_dspp,
> + .pingpong_count = ARRAY_SIZE(sm6350_pp),
> + .pingpong = sm6350_pp,
> + .intf_count = ARRAY_SIZE(sm6350_intf),
> + .intf = sm6350_intf,
> + .vbif_count = ARRAY_SIZE(sm6350_vbif),
> + .vbif = sm6350_vbif,
> + .reg_dma_count = 1,
> + .dma_cfg = &sm8250_regdma,
> + .perf = &sm6350_perf_data,
> + .mdss_irqs = IRQ_SC7180_MASK,
> +};
> +
> static const struct dpu_mdss_cfg sm8150_dpu_cfg = {
> .caps = &sm8150_dpu_caps,
> .mdp_count = ARRAY_SIZE(sdm845_mdp),
> @@ -2861,6 +3047,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
> { .hw_rev = DPU_HW_VER_600, .dpu_cfg = &sm8250_dpu_cfg},
> { .hw_rev = DPU_HW_VER_620, .dpu_cfg = &sc7180_dpu_cfg},
> { .hw_rev = DPU_HW_VER_630, .dpu_cfg = &sm6115_dpu_cfg},
> + { .hw_rev = DPU_HW_VER_640, .dpu_cfg = &sm6350_dpu_cfg},
> { .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg},
> { .hw_rev = DPU_HW_VER_700, .dpu_cfg = &sm8350_dpu_cfg},
> { .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg},
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index c7a2e6237d2b..cbf21613e121 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -45,6 +45,7 @@
> #define DPU_HW_VER_600 DPU_HW_VER(6, 0, 0) /* sm8250 */
> #define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */
> #define DPU_HW_VER_630 DPU_HW_VER(6, 3, 0) /* sm6115|sm4250 */
> +#define DPU_HW_VER_640 DPU_HW_VER(6, 4, 0) /* sm6350 */
> #define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */
> #define DPU_HW_VER_700 DPU_HW_VER(7, 0, 0) /* sm8350 */
> #define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */
> @@ -352,6 +353,8 @@ enum dpu_qos_lut_usage {
> DPU_QOS_LUT_USAGE_LINEAR,
> DPU_QOS_LUT_USAGE_MACROTILE,
> DPU_QOS_LUT_USAGE_NRT,
> + DPU_QOS_LUT_USAGE_CWB,
> + DPU_QOS_LUT_USAGE_MACROTILE_QSEED,
> DPU_QOS_LUT_USAGE_MAX,
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index a683bd9b5a04..ebfbbd2d105e 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -1306,6 +1306,7 @@ static const struct of_device_id dpu_dt_match[] = {
> { .compatible = "qcom,sc8180x-dpu", },
> { .compatible = "qcom,sc8280xp-dpu", },
> { .compatible = "qcom,sm6115-dpu", },
> + { .compatible = "qcom,sm6350-dpu", },
> { .compatible = "qcom,sm8150-dpu", },
> { .compatible = "qcom,sm8250-dpu", },
> { .compatible = "qcom,sm8350-dpu", },
> diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
Please split mdss to a separate patch.
> index 02646e4bb4cd..841016f3983a 100644
> --- a/drivers/gpu/drm/msm/msm_mdss.c
> +++ b/drivers/gpu/drm/msm/msm_mdss.c
> @@ -279,6 +279,7 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss)
> msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 3, 1);
> break;
> case DPU_HW_VER_620:
> + case DPU_HW_VER_640:
> /* UBWC_2_0 */
> msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x1e);
> break;
> @@ -529,6 +530,7 @@ static const struct of_device_id mdss_dt_match[] = {
> { .compatible = "qcom,sc8180x-mdss" },
> { .compatible = "qcom,sc8280xp-mdss" },
> { .compatible = "qcom,sm6115-mdss" },
> + { .compatible = "qcom,sm6350-mdss" },
> { .compatible = "qcom,sm8150-mdss" },
> { .compatible = "qcom,sm8250-mdss" },
> { .compatible = "qcom,sm8350-mdss" },
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 03/10] dt-bindings: display/msm: Add SM6350 DPU & MDSS
2023-02-11 12:26 ` [PATCH 03/10] dt-bindings: display/msm: Add SM6350 DPU & MDSS Konrad Dybcio
@ 2023-02-11 16:33 ` Dmitry Baryshkov
2023-02-13 15:09 ` Rob Herring
1 sibling, 0 replies; 36+ messages in thread
From: Dmitry Baryshkov @ 2023-02-11 16:33 UTC (permalink / raw)
To: Konrad Dybcio, linux-arm-msm, andersson, agross, krzysztof.kozlowski
Cc: marijn.suijten, Rob Clark, Abhinav Kumar, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, dri-devel, freedreno, devicetree,
linux-kernel
On 11/02/2023 14:26, Konrad Dybcio wrote:
> Document 6350 DPU and MDSS.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> .../bindings/display/msm/qcom,sm6350-dpu.yaml | 94 ++++++++
> .../display/msm/qcom,sm6350-mdss.yaml | 213 ++++++++++++++++++
> 2 files changed, 307 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml
> create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml
Could you please split mdss to a separate patch?
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 07/10] drm/msm/dpu: Add SM6375 support
2023-02-11 12:26 ` [PATCH 07/10] drm/msm/dpu: Add SM6375 support Konrad Dybcio
@ 2023-02-11 16:47 ` Dmitry Baryshkov
2023-02-13 11:16 ` Konrad Dybcio
0 siblings, 1 reply; 36+ messages in thread
From: Dmitry Baryshkov @ 2023-02-11 16:47 UTC (permalink / raw)
To: Konrad Dybcio, linux-arm-msm, andersson, agross, krzysztof.kozlowski
Cc: marijn.suijten, Rob Clark, Abhinav Kumar, Sean Paul,
David Airlie, Daniel Vetter, Robert Foss,
AngeloGioacchino Del Regno, Vinod Koul, Vinod Polimera,
Stephen Boyd, Liu Shixin, dri-devel, freedreno, linux-kernel
On 11/02/2023 14:26, Konrad Dybcio wrote:
> Add basic SM6375 support to the DPU1 driver to enable display output.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 120 ++++++++++++++++++
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
> drivers/gpu/drm/msm/msm_mdss.c | 1 +
> 4 files changed, 123 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index ba0bc795e5ff..327aa21f01fc 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -383,6 +383,24 @@ static const struct dpu_caps sm6350_dpu_caps = {
> .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> };
>
> +static const struct dpu_caps sm6375_dpu_caps = {
> + .max_mixer_width = 2048,
It looks like we got this wrong for sm6115, I
> + .max_mixer_blendstages = 0x4,
> + .qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
QSEED4
v3lite with the version >= 3.0 is v4. We should rework this to be more
sensible and easy to support.
> + .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
> + .ubwc_version = DPU_HW_UBWC_VER_20,
> + .has_dim_layer = true,
> + .has_idle_pc = true,
> + /*
> + * There is *NO* 3DMERGE hw, but we *need* to set this property to true,
> + * because SM6375 includes newer hardware that requires a different reset
> + * sequence and it is executed based on this confusingly named variable..
> + */
> + .has_3d_merge = true,
> + .max_linewidth = 2160,
> + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> +};
> +
> static const struct dpu_caps sm8150_dpu_caps = {
> .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> .max_mixer_blendstages = 0xb,
> @@ -592,6 +610,19 @@ static const struct dpu_mdp_cfg sm6350_mdp[] = {
> },
> };
>
> +static const struct dpu_mdp_cfg sm6375_mdp[] = {
sm6116_mdp ?
> + {
> + .name = "top_0", .id = MDP_TOP,
> + .base = 0x0, .len = 0x494,
> + .features = 0,
> + .highest_bank_bit = 0x1,
> + .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
> + .reg_off = 0x2ac, .bit_off = 0},
> + .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
> + .reg_off = 0x2ac, .bit_off = 8},
> + },
> +};
> +
> static const struct dpu_mdp_cfg sc8180x_mdp[] = {
> {
> .name = "top_0", .id = MDP_TOP,
> @@ -1577,6 +1608,19 @@ static const struct dpu_lm_cfg sm6350_lm[] = {
> &sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
> };
>
> +static const struct dpu_lm_sub_blks sm6375_lm_sblk = {
qcm2290_lm_sblk after we fix the width there.
> + .maxwidth = 2048,
> + .maxblendstages = 4, /* excluding base layer */
> + .blendstage_base = { /* offsets relative to mixer base */
> + 0x20, 0x38, 0x50, 0x68
> + },
> +};
> +
> +static const struct dpu_lm_cfg sm6375_lm[] = {
qcm2290_lm
> + LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
> + &sm6375_lm_sblk, PINGPONG_0, 0, DSPP_0),
> +};
> +
> /* SM8150 */
>
> static const struct dpu_lm_cfg sm8150_lm[] = {
> @@ -1984,6 +2028,11 @@ static const struct dpu_intf_cfg sm6350_intf[] = {
> INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 35, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> };
>
> +static const struct dpu_intf_cfg sm6375_intf[] = {
ack, size difference from sm6115/qcm2290
> + INTF_BLK("intf_0", INTF_0, 0x00000, 0x2c0, INTF_NONE, 0, 0, 0, 0, 0, 0),
> + INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> +};
> +
> static const struct dpu_intf_cfg sm8150_intf[] = {
> INTF_BLK("intf_0", INTF_0, 0x6A000, 0x280, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> INTF_BLK("intf_1", INTF_1, 0x6A800, 0x280, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> @@ -2171,6 +2220,26 @@ static const struct dpu_reg_dma_cfg sc8280xp_regdma = {
> .clk_ctrl = DPU_CLK_CTRL_REG_DMA,
> };
>
> +static const struct dpu_vbif_cfg sm6375_vbif[] = {
> + {
> + .name = "vbif_0", .id = VBIF_RT,
> + .base = 0, .len = 0x2008,
Ugh
> + .features = BIT(DPU_VBIF_QOS_REMAP),
> + .xin_halt_timeout = 0x4000,
> + .qos_rp_remap_size = 0x40,
> + .qos_rt_tbl = {
> + .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
> + .priority_lvl = sdm845_rt_pri_lvl,
> + },
> + .qos_nrt_tbl = {
> + .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
> + .priority_lvl = sdm845_nrt_pri_lvl,
> + },
> + .memtype_count = 14,
> + .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
> + },
> +};
> +
> static const struct dpu_reg_dma_cfg sdm845_regdma = {
> .base = 0x0, .version = 0x1, .trigger_sel_off = 0x119c
> };
> @@ -2460,6 +2529,34 @@ static const struct dpu_perf_cfg sm6350_perf_data = {
> .bw_inefficiency_factor = 120,
> };
>
> +static const struct dpu_perf_cfg sm6375_perf_data = {
> + .max_bw_low = 5200000,
> + .max_bw_high = 6200000,
> + .min_core_ib = 2500000,
> + .min_llcc_ib = 0,
> + .min_dram_ib = 1600000,
> + .min_prefill_lines = 24,
> + /* TODO: confirm danger_lut_tbl */
> + .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
> + .qos_lut_tbl = {
> + {.nentry = ARRAY_SIZE(sm6350_qos_linear),
> + .entries = sm6350_qos_linear
> + },
> + {.nentry = ARRAY_SIZE(sm6350_qos_macrotile),
> + .entries = sm6350_qos_macrotile
> + },
> + {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
> + .entries = sc7180_qos_nrt
> + },
> + },
> + .cdp_cfg = {
> + {.rd_enable = 1, .wr_enable = 1},
> + {.rd_enable = 1, .wr_enable = 0}
> + },
> + .clk_inefficiency_factor = 105,
> + .bw_inefficiency_factor = 120,
> +};
> +
> static const struct dpu_perf_cfg sm8150_perf_data = {
> .max_bw_low = 12800000,
> .max_bw_high = 12800000,
> @@ -2804,6 +2901,28 @@ static const struct dpu_mdss_cfg sm6350_dpu_cfg = {
> .mdss_irqs = IRQ_SC7180_MASK,
> };
>
> +static const struct dpu_mdss_cfg sm6375_dpu_cfg = {
> + .caps = &sm6350_dpu_caps,
> + .mdp_count = ARRAY_SIZE(sm6375_mdp),
> + .mdp = sm6375_mdp,
> + .ctl_count = ARRAY_SIZE(qcm2290_ctl),
> + .ctl = qcm2290_ctl,
> + .sspp_count = ARRAY_SIZE(sm6115_sspp),
> + .sspp = sm6115_sspp,
> + .mixer_count = ARRAY_SIZE(sm6375_lm),
> + .mixer = sm6375_lm,
> + .dspp_count = ARRAY_SIZE(qcm2290_dspp),
> + .dspp = qcm2290_dspp,
> + .pingpong_count = ARRAY_SIZE(qcm2290_pp),
> + .pingpong = qcm2290_pp,
> + .intf_count = ARRAY_SIZE(sm6375_intf),
> + .intf = sm6375_intf,
> + .vbif_count = ARRAY_SIZE(sm6375_vbif),
> + .vbif = sm6375_vbif,
> + .perf = &sm6375_perf_data,
> + .mdss_irqs = IRQ_SC7180_MASK,
> +};
> +
> static const struct dpu_mdss_cfg sm8150_dpu_cfg = {
> .caps = &sm8150_dpu_caps,
> .mdp_count = ARRAY_SIZE(sdm845_mdp),
> @@ -3049,6 +3168,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
> { .hw_rev = DPU_HW_VER_630, .dpu_cfg = &sm6115_dpu_cfg},
> { .hw_rev = DPU_HW_VER_640, .dpu_cfg = &sm6350_dpu_cfg},
> { .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg},
> + { .hw_rev = DPU_HW_VER_690, .dpu_cfg = &sm6375_dpu_cfg},
> { .hw_rev = DPU_HW_VER_700, .dpu_cfg = &sm8350_dpu_cfg},
> { .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg},
> { .hw_rev = DPU_HW_VER_800, .dpu_cfg = &sc8280xp_dpu_cfg},
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index cbf21613e121..a22b5965acfe 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -47,6 +47,7 @@
> #define DPU_HW_VER_630 DPU_HW_VER(6, 3, 0) /* sm6115|sm4250 */
> #define DPU_HW_VER_640 DPU_HW_VER(6, 4, 0) /* sm6350 */
> #define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */
> +#define DPU_HW_VER_690 DPU_HW_VER(6, 9, 0) /* sm6375 */
> #define DPU_HW_VER_700 DPU_HW_VER(7, 0, 0) /* sm8350 */
> #define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */
> #define DPU_HW_VER_800 DPU_HW_VER(8, 0, 0) /* sc8280xp */
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index ebfbbd2d105e..fd561974a6b1 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -1307,6 +1307,7 @@ static const struct of_device_id dpu_dt_match[] = {
> { .compatible = "qcom,sc8280xp-dpu", },
> { .compatible = "qcom,sm6115-dpu", },
> { .compatible = "qcom,sm6350-dpu", },
> + { .compatible = "qcom,sm6375-dpu", },
> { .compatible = "qcom,sm8150-dpu", },
> { .compatible = "qcom,sm8250-dpu", },
> { .compatible = "qcom,sm8350-dpu", },
> diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
> index 841016f3983a..fedc1a1fc289 100644
> --- a/drivers/gpu/drm/msm/msm_mdss.c
> +++ b/drivers/gpu/drm/msm/msm_mdss.c
Please split to the separate patch
> @@ -531,6 +531,7 @@ static const struct of_device_id mdss_dt_match[] = {
> { .compatible = "qcom,sc8280xp-mdss" },
> { .compatible = "qcom,sm6115-mdss" },
> { .compatible = "qcom,sm6350-mdss" },
> + { .compatible = "qcom,sm6375-mdss" },
Missing UBWC setup.
> { .compatible = "qcom,sm8150-mdss" },
> { .compatible = "qcom,sm8250-mdss" },
> { .compatible = "qcom,sm8350-mdss" },
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 05/10] drm/msm/dpu: Allow variable SSPP/INTF_BLK size
2023-02-11 12:26 ` [PATCH 05/10] drm/msm/dpu: Allow variable SSPP/INTF_BLK size Konrad Dybcio
@ 2023-02-11 17:00 ` Dmitry Baryshkov
2023-02-13 9:41 ` Konrad Dybcio
2023-02-13 11:12 ` Marijn Suijten
1 sibling, 1 reply; 36+ messages in thread
From: Dmitry Baryshkov @ 2023-02-11 17:00 UTC (permalink / raw)
To: Konrad Dybcio, linux-arm-msm, andersson, agross, krzysztof.kozlowski
Cc: marijn.suijten, Rob Clark, Abhinav Kumar, Sean Paul,
David Airlie, Daniel Vetter, Robert Foss,
AngeloGioacchino Del Regno, dri-devel, freedreno, linux-kernel
On 11/02/2023 14:26, Konrad Dybcio wrote:
> These blocks are of variable length on different SoCs. Set the
> correct values where I was able to retrieve it from downstream
> DTs and leave the old defaults (0x1c8 for sspp and 0x280 for
> intf) otherwise.
Could you please add FIXMEs close to the values where we are unsure?
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 242 +++++++++---------
> 1 file changed, 121 insertions(+), 121 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 802050118345..d9ef1e133c1e 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -1167,11 +1167,11 @@ static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK("9", 2);
> static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK("10", 3);
> static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11", 4);
>
> -#define SSPP_BLK(_name, _id, _base, _features, \
> +#define SSPP_BLK(_name, _id, _base, _len, _features, \
> _sblk, _xinid, _type, _clkctrl) \
> { \
> .name = _name, .id = _id, \
> - .base = _base, .len = 0x1c8, \
> + .base = _base, .len = _len, \
> .features = _features, \
> .sblk = &_sblk, \
> .xin_id = _xinid, \
> @@ -1180,40 +1180,40 @@ static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11", 4);
> }
>
> static const struct dpu_sspp_cfg msm8998_sspp[] = {
> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_MSM8998_MASK,
> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x184, VIG_MSM8998_MASK,
0x1ac ? Not completely sure though.
> msm8998_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_MSM8998_MASK,
> + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x184, VIG_MSM8998_MASK,
> msm8998_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
> - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_MSM8998_MASK,
> + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x184, VIG_MSM8998_MASK,
> msm8998_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
> - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_MSM8998_MASK,
> + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x184, VIG_MSM8998_MASK,
> msm8998_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_MSM8998_MASK,
> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x184, DMA_MSM8998_MASK,
> sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_MSM8998_MASK,
> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x184, DMA_MSM8998_MASK,
> sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
> - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_MSM8998_MASK,
> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x184, DMA_CURSOR_MSM8998_MASK,
> sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
> - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_MSM8998_MASK,
> + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x184, DMA_CURSOR_MSM8998_MASK,
> sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
> };
>
> static const struct dpu_sspp_cfg sdm845_sspp[] = {
> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SDM845_MASK,
> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1c8, VIG_SDM845_MASK,
> sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SDM845_MASK,
> + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1c8, VIG_SDM845_MASK,
> sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
> - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SDM845_MASK,
> + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1c8, VIG_SDM845_MASK,
> sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
> - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SDM845_MASK,
> + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1c8, VIG_SDM845_MASK,
> sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1c8, DMA_SDM845_MASK,
> sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK,
> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1c8, DMA_SDM845_MASK,
> sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
> - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1c8, DMA_CURSOR_SDM845_MASK,
> sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
> - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK,
> + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1c8, DMA_CURSOR_SDM845_MASK,
> sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
> };
>
> @@ -1224,13 +1224,13 @@ static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 =
> _VIG_SBLK_ROT("0", 4, DPU_SSPP_SCALER_QSEED4, &dpu_rot_sc7280_cfg_v2);
>
> static const struct dpu_sspp_cfg sc7180_sspp[] = {
0x1f8
> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK,
> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1c8, VIG_SC7180_MASK,
> sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1c8, DMA_SDM845_MASK,
> sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_CURSOR_SDM845_MASK,
> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1c8, DMA_CURSOR_SDM845_MASK,
> sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
> - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1c8, DMA_CURSOR_SDM845_MASK,
> sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
> };
>
> @@ -1238,9 +1238,9 @@ static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 =
> _VIG_SBLK("0", 2, DPU_SSPP_SCALER_QSEED3LITE);
>
> static const struct dpu_sspp_cfg sm6115_sspp[] = {
> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SM8250_MASK,
> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SM8250_MASK,
> sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
> sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> };
>
> @@ -1254,21 +1254,21 @@ static const struct dpu_sspp_sub_blks sm8250_vig_sblk_3 =
> _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3LITE);
>
> static const struct dpu_sspp_cfg sm8250_sspp[] = {
> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SM8250_MASK,
> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SM8250_MASK,
> sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SM8250_MASK,
> + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f8, VIG_SM8250_MASK,
> sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
> - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SM8250_MASK,
> + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f8, VIG_SM8250_MASK,
> sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
> - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SM8250_MASK,
> + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f8, VIG_SM8250_MASK,
> sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
> sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK,
> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_SDM845_MASK,
> sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
> - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
> sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
> - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK,
> + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f8, DMA_CURSOR_SDM845_MASK,
> sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
> };
>
> @@ -1282,21 +1282,21 @@ static const struct dpu_sspp_sub_blks sm8450_vig_sblk_3 =
> _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3LITE);
>
> static const struct dpu_sspp_cfg sm8450_sspp[] = {
> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK,
> - sm8450_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SC7180_MASK,
> - sm8450_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
> - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SC7180_MASK,
> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x328, VIG_SC7180_MASK,
> + sm8450_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x328, VIG_SC7180_MASK,
> + sm8450_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
> + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x328, VIG_SC7180_MASK,
> sm8450_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
> - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SC7180_MASK,
> - sm8450_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
> + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x328, VIG_SC7180_MASK,
> + sm8450_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x328, DMA_SDM845_MASK,
> sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK,
> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x328, DMA_SDM845_MASK,
> sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
> - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x328, DMA_CURSOR_SDM845_MASK,
> sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
> - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK,
> + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x328, DMA_CURSOR_SDM845_MASK,
> sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
> };
>
> @@ -1312,36 +1312,36 @@ static const struct dpu_sspp_sub_blks sm8550_dma_sblk_4 = _DMA_SBLK("12", 5);
> static const struct dpu_sspp_sub_blks sd8550_dma_sblk_5 = _DMA_SBLK("13", 6);
>
> static const struct dpu_sspp_cfg sm8550_sspp[] = {
> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK,
> - sm8550_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SC7180_MASK,
> - sm8550_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
> - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SC7180_MASK,
> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x344, VIG_SC7180_MASK,
> + sm8550_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x344, VIG_SC7180_MASK,
> + sm8550_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
> + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x344, VIG_SC7180_MASK,
> sm8550_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
> - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SC7180_MASK,
> - sm8550_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
> + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x344, VIG_SC7180_MASK,
> + sm8550_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x344, DMA_SDM845_MASK,
> sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK,
> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x344, DMA_SDM845_MASK,
> sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
> - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_SDM845_MASK,
> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x344, DMA_SDM845_MASK,
> sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
> - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_SDM845_MASK,
> + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x344, DMA_SDM845_MASK,
> sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
> - SSPP_BLK("sspp_12", SSPP_DMA4, 0x2c000, DMA_CURSOR_SDM845_MASK,
> + SSPP_BLK("sspp_12", SSPP_DMA4, 0x2c000, 0x344, DMA_CURSOR_SDM845_MASK,
> sm8550_dma_sblk_4, 14, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
> - SSPP_BLK("sspp_13", SSPP_DMA5, 0x2e000, DMA_CURSOR_SDM845_MASK,
> + SSPP_BLK("sspp_13", SSPP_DMA5, 0x2e000, 0x344, DMA_CURSOR_SDM845_MASK,
> sd8550_dma_sblk_5, 15, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
> };
>
> static const struct dpu_sspp_cfg sc7280_sspp[] = {
0x1f8
> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7280_MASK,
> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1c8, VIG_SC7280_MASK,
> sc7280_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1c8, DMA_SDM845_MASK,
> sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_CURSOR_SDM845_MASK,
> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1c8, DMA_CURSOR_SDM845_MASK,
> sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
> - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1c8, DMA_CURSOR_SDM845_MASK,
> sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
> };
>
> @@ -1355,21 +1355,21 @@ static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_3 =
> _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3LITE);
>
> static const struct dpu_sspp_cfg sc8280xp_sspp[] = {
Any particular source for 0x280? I'd assume it is also 0x328 with a FIXME
> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SM8250_MASK,
> - sc8280xp_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SM8250_MASK,
> - sc8280xp_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
> - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SM8250_MASK,
> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x280, VIG_SM8250_MASK,
> + sc8280xp_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x280, VIG_SM8250_MASK,
> + sc8280xp_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
> + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x280, VIG_SM8250_MASK,
> sc8280xp_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
> - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SM8250_MASK,
> - sc8280xp_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
> + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x280, VIG_SM8250_MASK,
> + sc8280xp_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x280, DMA_SDM845_MASK,
> sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK,
> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x280, DMA_SDM845_MASK,
> sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
> - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x280, DMA_CURSOR_SDM845_MASK,
> sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
> - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK,
> + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x280, DMA_CURSOR_SDM845_MASK,
> sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
> };
>
> @@ -1390,9 +1390,9 @@ static const struct dpu_sspp_sub_blks qcm2290_vig_sblk_0 = _VIG_SBLK_NOSCALE("0"
> static const struct dpu_sspp_sub_blks qcm2290_dma_sblk_0 = _DMA_SBLK("8", 1);
>
> static const struct dpu_sspp_cfg qcm2290_sspp[] = {
> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_QCM2290_MASK,
> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_QCM2290_MASK,
> qcm2290_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
> qcm2290_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> };
>
> @@ -1848,10 +1848,10 @@ static struct dpu_dsc_cfg sm8150_dsc[] = {
> /*************************************************************
> * INTF sub blocks config
> *************************************************************/
> -#define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \
> +#define INTF_BLK(_name, _id, _base, _len, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \
> {\
> .name = _name, .id = _id, \
> - .base = _base, .len = 0x280, \
> + .base = _base, .len = _len, \
> .features = _features, \
> .type = _type, \
> .controller_id = _ctrl_id, \
> @@ -1861,85 +1861,85 @@ static struct dpu_dsc_cfg sm8150_dsc[] = {
> }
>
> static const struct dpu_intf_cfg msm8998_intf[] = {
0x280? I'm not sure here though
> - INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> - INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> - INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
> - INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_HDMI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
> + INTF_BLK("intf_0", INTF_0, 0x6A000, 0x268, INTF_DP, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> + INTF_BLK("intf_1", INTF_1, 0x6A800, 0x268, INTF_DSI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> + INTF_BLK("intf_2", INTF_2, 0x6B000, 0x268, INTF_DSI, 1, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
> + INTF_BLK("intf_3", INTF_3, 0x6B800, 0x268, INTF_HDMI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
> };
>
> static const struct dpu_intf_cfg sdm845_intf[] = {
> - INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> - INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> - INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
> - INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
> + INTF_BLK("intf_0", INTF_0, 0x6A000, 0x280, INTF_DP, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> + INTF_BLK("intf_1", INTF_1, 0x6A800, 0x280, INTF_DSI, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> + INTF_BLK("intf_2", INTF_2, 0x6B000, 0x280, INTF_DSI, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
> + INTF_BLK("intf_3", INTF_3, 0x6B800, 0x280, INTF_DP, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
> };
>
> static const struct dpu_intf_cfg sc7180_intf[] = {
0x2b8
> - INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> - INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> + INTF_BLK("intf_0", INTF_0, 0x6A000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> + INTF_BLK("intf_1", INTF_1, 0x6A800, 0x280, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> };
>
> static const struct dpu_intf_cfg sm8150_intf[] = {
0x2b8
> - INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> - INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> - INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
> - INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
> + INTF_BLK("intf_0", INTF_0, 0x6A000, 0x280, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> + INTF_BLK("intf_1", INTF_1, 0x6A800, 0x280, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> + INTF_BLK("intf_2", INTF_2, 0x6B000, 0x280, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
> + INTF_BLK("intf_3", INTF_3, 0x6B800, 0x280, INTF_DP, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
> };
>
> static const struct dpu_intf_cfg sc7280_intf[] = {
0x2c4
> - INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> - INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> - INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
> + INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> + INTF_BLK("intf_1", INTF_1, 0x35000, 0x280, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> + INTF_BLK("intf_5", INTF_5, 0x39000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
> };
>
> static const struct dpu_intf_cfg sm8350_intf[] = {
> - INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> - INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> - INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
> - INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
> + INTF_BLK("intf_0", INTF_0, 0x34000, 0x2c4, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> + INTF_BLK("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> + INTF_BLK("intf_2", INTF_2, 0x36000, 0x2c4, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
> + INTF_BLK("intf_3", INTF_3, 0x37000, 0x2c4, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
> };
>
> static const struct dpu_intf_cfg sc8180x_intf[] = {
> - INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> - INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> - INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
> + INTF_BLK("intf_0", INTF_0, 0x6A000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> + INTF_BLK("intf_1", INTF_1, 0x6A800, 0x280, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> + INTF_BLK("intf_2", INTF_2, 0x6B000, 0x280, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
> /* INTF_3 is for MST, wired to INTF_DP 0 and 1, use dummy index until this is supported */
> - INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 999, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
> - INTF_BLK("intf_4", INTF_4, 0x6C000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 20, 21),
> - INTF_BLK("intf_5", INTF_5, 0x6C800, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
> + INTF_BLK("intf_3", INTF_3, 0x6B800, 0x280, INTF_DP, 999, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
> + INTF_BLK("intf_4", INTF_4, 0x6C000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 20, 21),
> + INTF_BLK("intf_5", INTF_5, 0x6C800, 0x280, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
> };
>
> /* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for now */
> static const struct dpu_intf_cfg sc8280xp_intf[] = {
I'd also suppose this is 0x2c4
> - INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> - INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> - INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
> - INTF_BLK("intf_3", INTF_3, 0x37000, INTF_NONE, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
> - INTF_BLK("intf_4", INTF_4, 0x38000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 20, 21),
> - INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, MSM_DP_CONTROLLER_3, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
> - INTF_BLK("intf_6", INTF_6, 0x3a000, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 16, 17),
> - INTF_BLK("intf_7", INTF_7, 0x3b000, INTF_NONE, MSM_DP_CONTROLLER_2, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 18, 19),
> - INTF_BLK("intf_8", INTF_8, 0x3c000, INTF_NONE, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 12, 13),
> + INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> + INTF_BLK("intf_1", INTF_1, 0x35000, 0x280, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> + INTF_BLK("intf_2", INTF_2, 0x36000, 0x280, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
> + INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_NONE, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
> + INTF_BLK("intf_4", INTF_4, 0x38000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 20, 21),
> + INTF_BLK("intf_5", INTF_5, 0x39000, 0x280, INTF_DP, MSM_DP_CONTROLLER_3, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
> + INTF_BLK("intf_6", INTF_6, 0x3a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 16, 17),
> + INTF_BLK("intf_7", INTF_7, 0x3b000, 0x280, INTF_NONE, MSM_DP_CONTROLLER_2, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 18, 19),
> + INTF_BLK("intf_8", INTF_8, 0x3c000, 0x280, INTF_NONE, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 12, 13),
> };
>
> static const struct dpu_intf_cfg qcm2290_intf[] = {
> - INTF_BLK("intf_0", INTF_0, 0x00000, INTF_NONE, 0, 0, 0, 0, 0, 0),
> - INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> + INTF_BLK("intf_0", INTF_0, 0x00000, 0x2b8, INTF_NONE, 0, 0, 0, 0, 0, 0),
> + INTF_BLK("intf_1", INTF_1, 0x6A800, 0x2b8, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> };
>
> static const struct dpu_intf_cfg sm8450_intf[] = {
> - INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> - INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> - INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
> - INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
> + INTF_BLK("intf_0", INTF_0, 0x34000, 0x2c4, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> + INTF_BLK("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> + INTF_BLK("intf_2", INTF_2, 0x36000, 0x2c4, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
> + INTF_BLK("intf_3", INTF_3, 0x37000, 0x2c4, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
> };
>
> static const struct dpu_intf_cfg sm8550_intf[] = {
> - INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> + INTF_BLK("intf_0", INTF_0, 0x34000, 0x300, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> /* TODO TE sub-blocks for intf1 & intf2 */
> - INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> - INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
> - INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
> + INTF_BLK("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> + INTF_BLK("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
> + INTF_BLK("intf_3", INTF_3, 0x37000, 0x300, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
> };
>
> /*************************************************************
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 05/10] drm/msm/dpu: Allow variable SSPP/INTF_BLK size
2023-02-11 17:00 ` Dmitry Baryshkov
@ 2023-02-13 9:41 ` Konrad Dybcio
0 siblings, 0 replies; 36+ messages in thread
From: Konrad Dybcio @ 2023-02-13 9:41 UTC (permalink / raw)
To: Dmitry Baryshkov, linux-arm-msm, andersson, agross, krzysztof.kozlowski
Cc: marijn.suijten, Rob Clark, Abhinav Kumar, Sean Paul,
David Airlie, Daniel Vetter, Robert Foss,
AngeloGioacchino Del Regno, dri-devel, freedreno, linux-kernel
On 11.02.2023 18:00, Dmitry Baryshkov wrote:
> On 11/02/2023 14:26, Konrad Dybcio wrote:
>> These blocks are of variable length on different SoCs. Set the
>> correct values where I was able to retrieve it from downstream
>> DTs and leave the old defaults (0x1c8 for sspp and 0x280 for
>> intf) otherwise.
>
> Could you please add FIXMEs close to the values where we are unsure?
>
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> ---
>> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 242 +++++++++---------
>> 1 file changed, 121 insertions(+), 121 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> index 802050118345..d9ef1e133c1e 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> @@ -1167,11 +1167,11 @@ static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK("9", 2);
>> static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK("10", 3);
>> static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11", 4);
>> -#define SSPP_BLK(_name, _id, _base, _features, \
>> +#define SSPP_BLK(_name, _id, _base, _len, _features, \
>> _sblk, _xinid, _type, _clkctrl) \
>> { \
>> .name = _name, .id = _id, \
>> - .base = _base, .len = 0x1c8, \
>> + .base = _base, .len = _len, \
>> .features = _features, \
>> .sblk = &_sblk, \
>> .xin_id = _xinid, \
>> @@ -1180,40 +1180,40 @@ static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11", 4);
>> }
>> static const struct dpu_sspp_cfg msm8998_sspp[] = {
>> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_MSM8998_MASK,
>> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x184, VIG_MSM8998_MASK,
>
> 0x1ac ? Not completely sure though.
(To be clear, "ack" in this review = "I checked deeper and agree
with what you found")
Ack
>
>> msm8998_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
>> - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_MSM8998_MASK,
>> + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x184, VIG_MSM8998_MASK,
>> msm8998_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
>> - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_MSM8998_MASK,
>> + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x184, VIG_MSM8998_MASK,
>> msm8998_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
>> - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_MSM8998_MASK,
>> + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x184, VIG_MSM8998_MASK,
>> msm8998_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
>> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_MSM8998_MASK,
>> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x184, DMA_MSM8998_MASK,
>> sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
>> - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_MSM8998_MASK,
>> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x184, DMA_MSM8998_MASK,
>> sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
>> - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_MSM8998_MASK,
>> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x184, DMA_CURSOR_MSM8998_MASK,
>> sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
>> - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_MSM8998_MASK,
>> + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x184, DMA_CURSOR_MSM8998_MASK,
>> sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
>> };
>> static const struct dpu_sspp_cfg sdm845_sspp[] = {
>> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SDM845_MASK,
>> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1c8, VIG_SDM845_MASK,
>> sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
>> - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SDM845_MASK,
>> + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1c8, VIG_SDM845_MASK,
>> sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
>> - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SDM845_MASK,
>> + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1c8, VIG_SDM845_MASK,
>> sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
>> - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SDM845_MASK,
>> + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1c8, VIG_SDM845_MASK,
>> sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
>> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
>> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1c8, DMA_SDM845_MASK,
>> sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
>> - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK,
>> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1c8, DMA_SDM845_MASK,
>> sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
>> - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
>> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1c8, DMA_CURSOR_SDM845_MASK,
>> sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
>> - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK,
>> + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1c8, DMA_CURSOR_SDM845_MASK,
>> sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
>> };
>> @@ -1224,13 +1224,13 @@ static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 =
>> _VIG_SBLK_ROT("0", 4, DPU_SSPP_SCALER_QSEED4, &dpu_rot_sc7280_cfg_v2);
>> static const struct dpu_sspp_cfg sc7180_sspp[] = {
>
> 0x1f8
Ack.
>
>> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK,
>> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1c8, VIG_SC7180_MASK,
>> sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
>> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
>> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1c8, DMA_SDM845_MASK,
>> sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
>> - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_CURSOR_SDM845_MASK,
>> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1c8, DMA_CURSOR_SDM845_MASK,
>> sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
>> - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
>> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1c8, DMA_CURSOR_SDM845_MASK,
>> sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
>> };
>> @@ -1238,9 +1238,9 @@ static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 =
>> _VIG_SBLK("0", 2, DPU_SSPP_SCALER_QSEED3LITE);
>> static const struct dpu_sspp_cfg sm6115_sspp[] = {
>> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SM8250_MASK,
>> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SM8250_MASK,
>> sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
>> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
>> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
>> sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
>> };
>> @@ -1254,21 +1254,21 @@ static const struct dpu_sspp_sub_blks sm8250_vig_sblk_3 =
>> _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3LITE);
>> static const struct dpu_sspp_cfg sm8250_sspp[] = {
>> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SM8250_MASK,
>> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SM8250_MASK,
>> sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
>> - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SM8250_MASK,
>> + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f8, VIG_SM8250_MASK,
>> sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
>> - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SM8250_MASK,
>> + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f8, VIG_SM8250_MASK,
>> sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
>> - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SM8250_MASK,
>> + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f8, VIG_SM8250_MASK,
>> sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
>> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
>> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
>> sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
>> - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK,
>> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_SDM845_MASK,
>> sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
>> - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
>> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
>> sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
>> - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK,
>> + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f8, DMA_CURSOR_SDM845_MASK,
>> sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
>> };
>> @@ -1282,21 +1282,21 @@ static const struct dpu_sspp_sub_blks sm8450_vig_sblk_3 =
>> _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3LITE);
>> static const struct dpu_sspp_cfg sm8450_sspp[] = {
>> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK,
>> - sm8450_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
>> - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SC7180_MASK,
>> - sm8450_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
>> - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SC7180_MASK,
>> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x328, VIG_SC7180_MASK,
>> + sm8450_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
>> + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x328, VIG_SC7180_MASK,
>> + sm8450_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
>> + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x328, VIG_SC7180_MASK,
>> sm8450_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
>> - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SC7180_MASK,
>> - sm8450_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
>> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
>> + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x328, VIG_SC7180_MASK,
>> + sm8450_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
>> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x328, DMA_SDM845_MASK,
>> sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
>> - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK,
>> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x328, DMA_SDM845_MASK,
>> sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
>> - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
>> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x328, DMA_CURSOR_SDM845_MASK,
>> sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
>> - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK,
>> + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x328, DMA_CURSOR_SDM845_MASK,
>> sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
>> };
>> @@ -1312,36 +1312,36 @@ static const struct dpu_sspp_sub_blks sm8550_dma_sblk_4 = _DMA_SBLK("12", 5);
>> static const struct dpu_sspp_sub_blks sd8550_dma_sblk_5 = _DMA_SBLK("13", 6);
>> static const struct dpu_sspp_cfg sm8550_sspp[] = {
>> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK,
>> - sm8550_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
>> - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SC7180_MASK,
>> - sm8550_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
>> - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SC7180_MASK,
>> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x344, VIG_SC7180_MASK,
>> + sm8550_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
>> + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x344, VIG_SC7180_MASK,
>> + sm8550_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
>> + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x344, VIG_SC7180_MASK,
>> sm8550_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
>> - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SC7180_MASK,
>> - sm8550_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
>> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
>> + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x344, VIG_SC7180_MASK,
>> + sm8550_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
>> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x344, DMA_SDM845_MASK,
>> sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
>> - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK,
>> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x344, DMA_SDM845_MASK,
>> sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
>> - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_SDM845_MASK,
>> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x344, DMA_SDM845_MASK,
>> sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
>> - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_SDM845_MASK,
>> + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x344, DMA_SDM845_MASK,
>> sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
>> - SSPP_BLK("sspp_12", SSPP_DMA4, 0x2c000, DMA_CURSOR_SDM845_MASK,
>> + SSPP_BLK("sspp_12", SSPP_DMA4, 0x2c000, 0x344, DMA_CURSOR_SDM845_MASK,
>> sm8550_dma_sblk_4, 14, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
>> - SSPP_BLK("sspp_13", SSPP_DMA5, 0x2e000, DMA_CURSOR_SDM845_MASK,
>> + SSPP_BLK("sspp_13", SSPP_DMA5, 0x2e000, 0x344, DMA_CURSOR_SDM845_MASK,
>> sd8550_dma_sblk_5, 15, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
>> };
>> static const struct dpu_sspp_cfg sc7280_sspp[] = {
>
> 0x1f8
Ack.
>
>> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7280_MASK,
>> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1c8, VIG_SC7280_MASK,
>> sc7280_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
>> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
>> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1c8, DMA_SDM845_MASK,
>> sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
>> - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_CURSOR_SDM845_MASK,
>> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1c8, DMA_CURSOR_SDM845_MASK,
>> sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
>> - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
>> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1c8, DMA_CURSOR_SDM845_MASK,
>> sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
>> };
>> @@ -1355,21 +1355,21 @@ static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_3 =
>> _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3LITE);
>> static const struct dpu_sspp_cfg sc8280xp_sspp[] = {
>
> Any particular source for 0x280? I'd assume it is also 0x328 with a FIXME
0x1c8 with a FIXME, this is a SSPP_BLK. I must have copypasted
the old default value for INTF_BLK here.
>
>> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SM8250_MASK,
>> - sc8280xp_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
>> - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SM8250_MASK,
>> - sc8280xp_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
>> - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SM8250_MASK,
>> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x280, VIG_SM8250_MASK,
>> + sc8280xp_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
>> + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x280, VIG_SM8250_MASK,
>> + sc8280xp_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
>> + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x280, VIG_SM8250_MASK,
>> sc8280xp_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
>> - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SM8250_MASK,
>> - sc8280xp_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
>> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
>> + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x280, VIG_SM8250_MASK,
>> + sc8280xp_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
>> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x280, DMA_SDM845_MASK,
>> sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
>> - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK,
>> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x280, DMA_SDM845_MASK,
>> sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
>> - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
>> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x280, DMA_CURSOR_SDM845_MASK,
>> sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
>> - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK,
>> + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x280, DMA_CURSOR_SDM845_MASK,
>> sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
>> };
>> @@ -1390,9 +1390,9 @@ static const struct dpu_sspp_sub_blks qcm2290_vig_sblk_0 = _VIG_SBLK_NOSCALE("0"
>> static const struct dpu_sspp_sub_blks qcm2290_dma_sblk_0 = _DMA_SBLK("8", 1);
>> static const struct dpu_sspp_cfg qcm2290_sspp[] = {
>> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_QCM2290_MASK,
>> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_QCM2290_MASK,
>> qcm2290_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
>> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
>> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
>> qcm2290_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
>> };
>> @@ -1848,10 +1848,10 @@ static struct dpu_dsc_cfg sm8150_dsc[] = {
>> /*************************************************************
>> * INTF sub blocks config
>> *************************************************************/
>> -#define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \
>> +#define INTF_BLK(_name, _id, _base, _len, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \
>> {\
>> .name = _name, .id = _id, \
>> - .base = _base, .len = 0x280, \
>> + .base = _base, .len = _len, \
>> .features = _features, \
>> .type = _type, \
>> .controller_id = _ctrl_id, \
>> @@ -1861,85 +1861,85 @@ static struct dpu_dsc_cfg sm8150_dsc[] = {
>> }
>> static const struct dpu_intf_cfg msm8998_intf[] = {
>
> 0x280? I'm not sure here though
Yep, I blame a certain Italian for messing with my go-to downstream.. :P
>
>> - INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
>> - INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
>> - INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
>> - INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_HDMI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
>> + INTF_BLK("intf_0", INTF_0, 0x6A000, 0x268, INTF_DP, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
>> + INTF_BLK("intf_1", INTF_1, 0x6A800, 0x268, INTF_DSI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
>> + INTF_BLK("intf_2", INTF_2, 0x6B000, 0x268, INTF_DSI, 1, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
>> + INTF_BLK("intf_3", INTF_3, 0x6B800, 0x268, INTF_HDMI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
>> };
>> static const struct dpu_intf_cfg sdm845_intf[] = {
>> - INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
>> - INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
>> - INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
>> - INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
>> + INTF_BLK("intf_0", INTF_0, 0x6A000, 0x280, INTF_DP, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
>> + INTF_BLK("intf_1", INTF_1, 0x6A800, 0x280, INTF_DSI, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
>> + INTF_BLK("intf_2", INTF_2, 0x6B000, 0x280, INTF_DSI, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
>> + INTF_BLK("intf_3", INTF_3, 0x6B800, 0x280, INTF_DP, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
>> };
>> static const struct dpu_intf_cfg sc7180_intf[] = {
>
> 0x2b8
Ack
>
>> - INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
>> - INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
>> + INTF_BLK("intf_0", INTF_0, 0x6A000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
>> + INTF_BLK("intf_1", INTF_1, 0x6A800, 0x280, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
>> };
>> static const struct dpu_intf_cfg sm8150_intf[] = {
>
> 0x2b8
Ack
>
>> - INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
>> - INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
>> - INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
>> - INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
>> + INTF_BLK("intf_0", INTF_0, 0x6A000, 0x280, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
>> + INTF_BLK("intf_1", INTF_1, 0x6A800, 0x280, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
>> + INTF_BLK("intf_2", INTF_2, 0x6B000, 0x280, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
>> + INTF_BLK("intf_3", INTF_3, 0x6B800, 0x280, INTF_DP, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
>> };
>> static const struct dpu_intf_cfg sc7280_intf[] = {
>
> 0x2c4
Ack
>
>> - INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
>> - INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
>> - INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
>> + INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
>> + INTF_BLK("intf_1", INTF_1, 0x35000, 0x280, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
>> + INTF_BLK("intf_5", INTF_5, 0x39000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
>> };
>> static const struct dpu_intf_cfg sm8350_intf[] = {
>> - INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
>> - INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
>> - INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
>> - INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
>> + INTF_BLK("intf_0", INTF_0, 0x34000, 0x2c4, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
>> + INTF_BLK("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
>> + INTF_BLK("intf_2", INTF_2, 0x36000, 0x2c4, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
>> + INTF_BLK("intf_3", INTF_3, 0x37000, 0x2c4, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
>> };
>> static const struct dpu_intf_cfg sc8180x_intf[] = {
>> - INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
>> - INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
>> - INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
>> + INTF_BLK("intf_0", INTF_0, 0x6A000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
>> + INTF_BLK("intf_1", INTF_1, 0x6A800, 0x280, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
>> + INTF_BLK("intf_2", INTF_2, 0x6B000, 0x280, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
>> /* INTF_3 is for MST, wired to INTF_DP 0 and 1, use dummy index until this is supported */
>> - INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 999, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
>> - INTF_BLK("intf_4", INTF_4, 0x6C000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 20, 21),
>> - INTF_BLK("intf_5", INTF_5, 0x6C800, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
>> + INTF_BLK("intf_3", INTF_3, 0x6B800, 0x280, INTF_DP, 999, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
>> + INTF_BLK("intf_4", INTF_4, 0x6C000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 20, 21),
>> + INTF_BLK("intf_5", INTF_5, 0x6C800, 0x280, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
>> };
>> /* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for now */
>> static const struct dpu_intf_cfg sc8280xp_intf[] = {
>
> I'd also suppose this is 0x2c4
No data, for now it's a 0x280 (with a FIXME though).
Konrad
>
>> - INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
>> - INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
>> - INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
>> - INTF_BLK("intf_3", INTF_3, 0x37000, INTF_NONE, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
>> - INTF_BLK("intf_4", INTF_4, 0x38000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 20, 21),
>> - INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, MSM_DP_CONTROLLER_3, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
>> - INTF_BLK("intf_6", INTF_6, 0x3a000, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 16, 17),
>> - INTF_BLK("intf_7", INTF_7, 0x3b000, INTF_NONE, MSM_DP_CONTROLLER_2, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 18, 19),
>> - INTF_BLK("intf_8", INTF_8, 0x3c000, INTF_NONE, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 12, 13),
>> + INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
>> + INTF_BLK("intf_1", INTF_1, 0x35000, 0x280, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
>> + INTF_BLK("intf_2", INTF_2, 0x36000, 0x280, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
>> + INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_NONE, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
>> + INTF_BLK("intf_4", INTF_4, 0x38000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 20, 21),
>> + INTF_BLK("intf_5", INTF_5, 0x39000, 0x280, INTF_DP, MSM_DP_CONTROLLER_3, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
>> + INTF_BLK("intf_6", INTF_6, 0x3a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 16, 17),
>> + INTF_BLK("intf_7", INTF_7, 0x3b000, 0x280, INTF_NONE, MSM_DP_CONTROLLER_2, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 18, 19),
>> + INTF_BLK("intf_8", INTF_8, 0x3c000, 0x280, INTF_NONE, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 12, 13),
>> };
>> static const struct dpu_intf_cfg qcm2290_intf[] = {
>> - INTF_BLK("intf_0", INTF_0, 0x00000, INTF_NONE, 0, 0, 0, 0, 0, 0),
>> - INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
>> + INTF_BLK("intf_0", INTF_0, 0x00000, 0x2b8, INTF_NONE, 0, 0, 0, 0, 0, 0),
>> + INTF_BLK("intf_1", INTF_1, 0x6A800, 0x2b8, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
>> };
>> static const struct dpu_intf_cfg sm8450_intf[] = {
>> - INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
>> - INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
>> - INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
>> - INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
>> + INTF_BLK("intf_0", INTF_0, 0x34000, 0x2c4, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
>> + INTF_BLK("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
>> + INTF_BLK("intf_2", INTF_2, 0x36000, 0x2c4, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
>> + INTF_BLK("intf_3", INTF_3, 0x37000, 0x2c4, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
>> };
>> static const struct dpu_intf_cfg sm8550_intf[] = {
>> - INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
>> + INTF_BLK("intf_0", INTF_0, 0x34000, 0x300, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
>> /* TODO TE sub-blocks for intf1 & intf2 */
>> - INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
>> - INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
>> - INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
>> + INTF_BLK("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
>> + INTF_BLK("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
>> + INTF_BLK("intf_3", INTF_3, 0x37000, 0x300, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
>> };
>> /*************************************************************
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 05/10] drm/msm/dpu: Allow variable SSPP/INTF_BLK size
2023-02-11 12:26 ` [PATCH 05/10] drm/msm/dpu: Allow variable SSPP/INTF_BLK size Konrad Dybcio
2023-02-11 17:00 ` Dmitry Baryshkov
@ 2023-02-13 11:12 ` Marijn Suijten
2023-02-13 11:38 ` Dmitry Baryshkov
1 sibling, 1 reply; 36+ messages in thread
From: Marijn Suijten @ 2023-02-13 11:12 UTC (permalink / raw)
To: Konrad Dybcio
Cc: linux-arm-msm, andersson, agross, krzysztof.kozlowski, Rob Clark,
Abhinav Kumar, Dmitry Baryshkov, Sean Paul, David Airlie,
Daniel Vetter, Robert Foss, AngeloGioacchino Del Regno,
dri-devel, freedreno, linux-kernel
On 2023-02-11 13:26:51, Konrad Dybcio wrote:
> These blocks are of variable length on different SoCs. Set the
> correct values where I was able to retrieve it from downstream
> DTs and leave the old defaults (0x1c8 for sspp and 0x280 for
> intf) otherwise.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 242 +++++++++---------
> 1 file changed, 121 insertions(+), 121 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 802050118345..d9ef1e133c1e 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
[..]
> @@ -1848,10 +1848,10 @@ static struct dpu_dsc_cfg sm8150_dsc[] = {
> /*************************************************************
> * INTF sub blocks config
> *************************************************************/
> -#define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \
> +#define INTF_BLK(_name, _id, _base, _len, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \
Dmitry and I discussed in #freedreno to instead add the INTF_BLK_DSI_TE
macro that accounts for the INTF TE registers using this higher register
area, as well as an extended signature to configure extra interrupts.
(Besides, I think the len is currently only used for snapshot dumping
and no validation for out-of-blk reads/writes)
> {\
> .name = _name, .id = _id, \
> - .base = _base, .len = 0x280, \
> + .base = _base, .len = _len, \
> .features = _features, \
> .type = _type, \
> .controller_id = _ctrl_id, \
[..]
- Marijn
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 06/10] drm/msm/dpu: Add SM6350 support
2023-02-11 16:32 ` Dmitry Baryshkov
@ 2023-02-13 11:15 ` Konrad Dybcio
2023-02-13 11:30 ` Marijn Suijten
0 siblings, 1 reply; 36+ messages in thread
From: Konrad Dybcio @ 2023-02-13 11:15 UTC (permalink / raw)
To: Dmitry Baryshkov, linux-arm-msm, andersson, agross, krzysztof.kozlowski
Cc: marijn.suijten, Konrad Dybcio, Rob Clark, Abhinav Kumar,
Sean Paul, David Airlie, Daniel Vetter, Robert Foss,
AngeloGioacchino Del Regno, Vinod Koul, Vinod Polimera,
Stephen Boyd, Liu Shixin, dri-devel, freedreno, linux-kernel
On 11.02.2023 17:32, Dmitry Baryshkov wrote:
> On 11/02/2023 14:26, Konrad Dybcio wrote:
>> Add SM6350 support to the DPU1 driver to enable display output.
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> ---
>> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 187 ++++++++++++++++++
>> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 +
>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
>> drivers/gpu/drm/msm/msm_mdss.c | 2 +
>> 4 files changed, 193 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> index d9ef1e133c1e..ba0bc795e5ff 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> @@ -364,6 +364,25 @@ static const struct dpu_caps sm6115_dpu_caps = {
>> .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
>> };
>> +static const struct dpu_caps sm6350_dpu_caps = {
>> + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
>> + .max_mixer_blendstages = 0x7,
>> + .qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
>
> QSEED4
Confirmed with a register write at 0x0ae05a00
(mdp_base + 0x4000 + 0xa00) => 0x3000 (QSEED4)
>
>> + .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
>> + .ubwc_version = DPU_HW_UBWC_VER_20,
>> + .has_src_split = true,
>> + .has_dim_layer = true,
>> + .has_idle_pc = true,
>> + /*
>> + * There is *NO* 3DMERGE hw, but we *need* to set this property to true,
>> + * because SM6350 includes newer hardware that requires a different reset
>> + * sequence and it is executed based on this confusingly named variable..
>> + */
>
> Which reset sequence is that? Is it something that was not posted yet?
Hm.. this patch came to life about 1.5y ago so it's hard to tell..
Grepping for 3dmerge I found that there is some legacy reset sequence
which should not be executed for anything >=8150 (probably related
to the intf te moving), but currently it's only evaluated in
disp/dpu1/dpu_encoder.c : dpu_encoder_get_topology(). Interestingly
enough, that legacy reset sequence is not implemented upstream, so
there was really no way to hit it..
Downstream has a has_3d_merge_reset flag for that and I'm not sure
how relevant the check we have upstream in dpu_encoder is to anything
newer than 845.
While testing on PDX213 is near impossible (the panel is acting up
and only initializes once in like 10 boots, otherwise it comes to life
after $random minutes; this is a panel-specific issue though..), Luca
reported no regressions after settings this to false on his Fairphone 4.
>
>> + .has_3d_merge = true,
>> + .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
>> + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
>> +};
>> +
>> static const struct dpu_caps sm8150_dpu_caps = {
>> .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
>> .max_mixer_blendstages = 0xb,
>> @@ -554,6 +573,25 @@ static const struct dpu_mdp_cfg sc7180_mdp[] = {
>> },
>> };
>> +static const struct dpu_mdp_cfg sm6350_mdp[] = {
>> + {
>> + .name = "top_0", .id = MDP_TOP,
>> + .base = 0x0, .len = 0x494,
>> + .features = 0,
>> + .highest_bank_bit = 0x1,
>> + .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
>> + .reg_off = 0x2ac, .bit_off = 0},
>> + .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
>> + .reg_off = 0x2ac, .bit_off = 8},
>> + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
>
> DPU_CLK_CTRL_DMA1
>
>> + .reg_off = 0x2b4, .bit_off = 8},
>> + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
>
> DPU_CLK_CTRL_DMA2
>
>> + .reg_off = 0x2c4, .bit_off = 8},
>> + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
>> + .reg_off = 0x2bc, .bit_off = 20},
>> + },
>
> Please fit them into a single line
Ack x3
>
>> +};
>> +
>> static const struct dpu_mdp_cfg sc8180x_mdp[] = {
>> {
>> .name = "top_0", .id = MDP_TOP,
>> @@ -888,6 +926,33 @@ static const struct dpu_ctl_cfg sc8280xp_ctl[] = {
>> },
>> };
>> +static const struct dpu_ctl_cfg sm6350_ctl[] = {
>
> We need to fix sc7180_ctl[].len, then we can use it here instead.
Yep, good find!
>
>> + {
>> + .name = "ctl_0", .id = CTL_0,
>> + .base = 0x1000, .len = 0x1dc,
>> + .features = BIT(DPU_CTL_ACTIVE_CFG),
>> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
>> + },
>> + {
>> + .name = "ctl_1", .id = CTL_1,
>> + .base = 0x1200, .len = 0x1dc,
>> + .features = BIT(DPU_CTL_ACTIVE_CFG),
>> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
>> + },
>> + {
>> + .name = "ctl_2", .id = CTL_2,
>> + .base = 0x1400, .len = 0x1dc,
>> + .features = BIT(DPU_CTL_ACTIVE_CFG),
>> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
>> + },
>> + {
>> + .name = "ctl_3", .id = CTL_3,
>> + .base = 0x1600, .len = 0x1dc,
>> + .features = BIT(DPU_CTL_ACTIVE_CFG),
>> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
>> + },
>> +};
>> +
>> static const struct dpu_ctl_cfg sm8150_ctl[] = {
>> {
>> .name = "ctl_0", .id = CTL_0,
>> @@ -1244,6 +1309,20 @@ static const struct dpu_sspp_cfg sm6115_sspp[] = {
>> sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
>> };
>> +static const struct dpu_sspp_sub_blks sm6350_vig_sblk_0 =
>> + _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED3LITE);
>
> QSEED4
Confirmed with a register read.
>
>> +
>> +static const struct dpu_sspp_cfg sm6350_sspp[] = {
>> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SM8250_MASK,
>> + sm6350_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
>> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
>> + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
>> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
>> + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
>
> DPU_CLK_CTRL_DMA1
>
>> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
>> + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
>
> DPU_CLK_CTRL_DMA2
Double ack
>
>> +};
>> +
>> static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 =
>> _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE);
>> static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 =
>> @@ -1491,6 +1570,13 @@ static const struct dpu_lm_cfg sc8280xp_lm[] = {
>> LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
>> };
>> +static const struct dpu_lm_cfg sm6350_lm[] = {
>
> I think we can use sc7180_lm here
Yep!
>
>> + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
>> + &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
>> + LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
>> + &sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
>> +};
>> +
>> /* SM8150 */
>> static const struct dpu_lm_cfg sm8150_lm[] = {
>> @@ -1572,6 +1658,11 @@ static const struct dpu_dspp_cfg sc7180_dspp[] = {
>> &sc7180_dspp_sblk),
>> };
>> +static const struct dpu_dspp_cfg sm6350_dspp[] = {
>
> sc7180_dspp
Yes, but 7180 should be fixed up too, as the downstream dt
entry for both is identical:
qcom,sde-dspp-pcc = <0x1700 0x00040000>;
(7180 sets version to 0x1000 upstream as of now)
>
>> + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
>> + &sm8150_dspp_sblk),
>> +};
>> +
>> static const struct dpu_dspp_cfg sm8150_dspp[] = {
>> DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
>> &sm8150_dspp_sblk),
>> @@ -1674,6 +1765,15 @@ static struct dpu_pingpong_cfg sc8280xp_pp[] = {
>> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), -1),
>> };
>> +static struct dpu_pingpong_cfg sm6350_pp[] = {
>> + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk,
>
> No TE support?
It's.. complicated.. With just this patch, display refreshes, albeit
not at 60fps. Marijn is working on getting it going, though
https://github.com/SoMainline/linux/commits/marijn/longbois-next/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>
>> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
>> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
>> + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk,
>> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
>> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
>> +};
>> +
>> static const struct dpu_pingpong_cfg sm8150_pp[] = {
>> PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk_te,
>> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
>> @@ -1879,6 +1979,11 @@ static const struct dpu_intf_cfg sc7180_intf[] = {
>> INTF_BLK("intf_1", INTF_1, 0x6A800, 0x280, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
>> };
>> +static const struct dpu_intf_cfg sm6350_intf[] = {
>
> Interesting. Size is 0x2b8 for sc7180 (if I'm not mistaken), but 0x2c0 for sm6350. Do you know by chance what's the difference?
2 bytes ;)
On a more serious note, I really don't, 7180 was made with TSMC and 6350 with
"foundry ID 3" (as per socinfo on my device), if that's Samsung or some other
fab, maybe they had to make some changes. Or wild erratas.
>
>> + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x2c0, INTF_DP, 0, 35, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
>> + INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 35, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
>> +};
>> +
>> static const struct dpu_intf_cfg sm8150_intf[] = {
>> INTF_BLK("intf_0", INTF_0, 0x6A000, 0x280, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
>> INTF_BLK("intf_1", INTF_1, 0x6A800, 0x280, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
>> @@ -2039,6 +2144,25 @@ static const struct dpu_vbif_cfg sdm845_vbif[] = {
>> },
>> };
>> +static const struct dpu_vbif_cfg sm6350_vbif[] = {
>> + {
>> + .name = "vbif_0", .id = VBIF_RT,
>> + .base = 0, .len = 0x1044,
>
> So, the only difference from sdm845_vbif is the len? Can we ignore it?
Won't that break/mess with at least register dumping?
>
>> + .features = BIT(DPU_VBIF_QOS_REMAP),
>> + .xin_halt_timeout = 0x4000,
>> + .qos_rt_tbl = {
>> + .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
>> + .priority_lvl = sdm845_rt_pri_lvl,
>> + },
>> + .qos_nrt_tbl = {
>> + .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
>> + .priority_lvl = sdm845_nrt_pri_lvl,
>> + },
>> + .memtype_count = 14,
>> + .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
>> + },
>> +};
>> +
>> static const struct dpu_reg_dma_cfg sc8280xp_regdma = {
>> .base = 0x0,
>> .version = 0x00020000,
>> @@ -2128,6 +2252,11 @@ static const struct dpu_qos_lut_entry sc7180_qos_linear[] = {
>> {.fl = 0, .lut = 0x0011222222335777},
>> };
>>
>
> Two LUT entries with the same fill level sound strange. Yes, I see the same in the vendor dts. Let me check how they are parsend and used.
>
>> +static const struct dpu_qos_lut_entry sm6350_qos_linear[] = {
>> + {.fl = 0, .lut = 0x0011223344556677 },
>> + {.fl = 0, .lut = 0x0011223445566777 },
>> +};
>> +
>> static const struct dpu_qos_lut_entry sm8150_qos_linear[] = {
>> {.fl = 0, .lut = 0x0011222222223357 },
>> };
>> @@ -2153,6 +2282,11 @@ static const struct dpu_qos_lut_entry sc7180_qos_macrotile[] = {
>> {.fl = 0, .lut = 0x0011223344556677},
>> };
>> +static const struct dpu_qos_lut_entry sm6350_qos_macrotile[] = {
>> + {.fl = 0, .lut = 0x0011223344556677 },
>> + {.fl = 0, .lut = 0x0011223445566777 },
>> +};
>> +
>> static const struct dpu_qos_lut_entry sc8180x_qos_macrotile[] = {
>> {.fl = 10, .lut = 0x0000000344556677},
>> };
>> @@ -2298,6 +2432,34 @@ static const struct dpu_perf_cfg sm6115_perf_data = {
>> .bw_inefficiency_factor = 120,
>> };
>> +static const struct dpu_perf_cfg sm6350_perf_data = {
>> + .max_bw_low = 4200000,
>> + .max_bw_high = 5100000,
>> + .min_core_ib = 2500000,
>> + .min_llcc_ib = 0,
>> + .min_dram_ib = 1600000,
>> + .min_prefill_lines = 35,
>> + /* TODO: confirm danger_lut_tbl */
>> + .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
>> + .qos_lut_tbl = {
>> + {.nentry = ARRAY_SIZE(sm6350_qos_linear),
>> + .entries = sm6350_qos_linear
>> + },
>> + {.nentry = ARRAY_SIZE(sm6350_qos_macrotile),
>> + .entries = sm6350_qos_macrotile
>> + },
>> + {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
>> + .entries = sc7180_qos_nrt
>> + },
>> + },
>> + .cdp_cfg = {
>> + {.rd_enable = 1, .wr_enable = 1},
>> + {.rd_enable = 1, .wr_enable = 0}
>> + },
>> + .clk_inefficiency_factor = 105,
>> + .bw_inefficiency_factor = 120,
>> +};
>> +
>> static const struct dpu_perf_cfg sm8150_perf_data = {
>> .max_bw_low = 12800000,
>> .max_bw_high = 12800000,
>> @@ -2618,6 +2780,30 @@ static const struct dpu_mdss_cfg sm6115_dpu_cfg = {
>> .mdss_irqs = IRQ_SC7180_MASK,
>> };
>> +static const struct dpu_mdss_cfg sm6350_dpu_cfg = {
>> + .caps = &sm6350_dpu_caps,
>> + .mdp_count = ARRAY_SIZE(sm6350_mdp),
>> + .mdp = sm6350_mdp,
>> + .ctl_count = ARRAY_SIZE(sm6350_ctl),
>> + .ctl = sm6350_ctl,
>> + .sspp_count = ARRAY_SIZE(sm6350_sspp),
>> + .sspp = sm6350_sspp,
>> + .mixer_count = ARRAY_SIZE(sm6350_lm),
>> + .mixer = sm6350_lm,
>> + .dspp_count = ARRAY_SIZE(sm6350_dspp),
>> + .dspp = sm6350_dspp,
>> + .pingpong_count = ARRAY_SIZE(sm6350_pp),
>> + .pingpong = sm6350_pp,
>> + .intf_count = ARRAY_SIZE(sm6350_intf),
>> + .intf = sm6350_intf,
>> + .vbif_count = ARRAY_SIZE(sm6350_vbif),
>> + .vbif = sm6350_vbif,
>> + .reg_dma_count = 1,
>> + .dma_cfg = &sm8250_regdma,
>> + .perf = &sm6350_perf_data,
>> + .mdss_irqs = IRQ_SC7180_MASK,
>> +};
>> +
>> static const struct dpu_mdss_cfg sm8150_dpu_cfg = {
>> .caps = &sm8150_dpu_caps,
>> .mdp_count = ARRAY_SIZE(sdm845_mdp),
>> @@ -2861,6 +3047,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
>> { .hw_rev = DPU_HW_VER_600, .dpu_cfg = &sm8250_dpu_cfg},
>> { .hw_rev = DPU_HW_VER_620, .dpu_cfg = &sc7180_dpu_cfg},
>> { .hw_rev = DPU_HW_VER_630, .dpu_cfg = &sm6115_dpu_cfg},
>> + { .hw_rev = DPU_HW_VER_640, .dpu_cfg = &sm6350_dpu_cfg},
>> { .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg},
>> { .hw_rev = DPU_HW_VER_700, .dpu_cfg = &sm8350_dpu_cfg},
>> { .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg},
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> index c7a2e6237d2b..cbf21613e121 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> @@ -45,6 +45,7 @@
>> #define DPU_HW_VER_600 DPU_HW_VER(6, 0, 0) /* sm8250 */
>> #define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */
>> #define DPU_HW_VER_630 DPU_HW_VER(6, 3, 0) /* sm6115|sm4250 */
>> +#define DPU_HW_VER_640 DPU_HW_VER(6, 4, 0) /* sm6350 */
>> #define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */
>> #define DPU_HW_VER_700 DPU_HW_VER(7, 0, 0) /* sm8350 */
>> #define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */
>> @@ -352,6 +353,8 @@ enum dpu_qos_lut_usage {
>> DPU_QOS_LUT_USAGE_LINEAR,
>> DPU_QOS_LUT_USAGE_MACROTILE,
>> DPU_QOS_LUT_USAGE_NRT,
>> + DPU_QOS_LUT_USAGE_CWB,
>> + DPU_QOS_LUT_USAGE_MACROTILE_QSEED,
>> DPU_QOS_LUT_USAGE_MAX,
>> };
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> index a683bd9b5a04..ebfbbd2d105e 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> @@ -1306,6 +1306,7 @@ static const struct of_device_id dpu_dt_match[] = {
>> { .compatible = "qcom,sc8180x-dpu", },
>> { .compatible = "qcom,sc8280xp-dpu", },
>> { .compatible = "qcom,sm6115-dpu", },
>> + { .compatible = "qcom,sm6350-dpu", },
>> { .compatible = "qcom,sm8150-dpu", },
>> { .compatible = "qcom,sm8250-dpu", },
>> { .compatible = "qcom,sm8350-dpu", },
>> diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
>
> Please split mdss to a separate patch.
Ack
Konrad
>
>> index 02646e4bb4cd..841016f3983a 100644
>> --- a/drivers/gpu/drm/msm/msm_mdss.c
>> +++ b/drivers/gpu/drm/msm/msm_mdss.c
>> @@ -279,6 +279,7 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss)
>> msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 3, 1);
>> break;
>> case DPU_HW_VER_620:
>> + case DPU_HW_VER_640:
>> /* UBWC_2_0 */
>> msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x1e);
>> break;
>> @@ -529,6 +530,7 @@ static const struct of_device_id mdss_dt_match[] = {
>> { .compatible = "qcom,sc8180x-mdss" },
>> { .compatible = "qcom,sc8280xp-mdss" },
>> { .compatible = "qcom,sm6115-mdss" },
>> + { .compatible = "qcom,sm6350-mdss" },
>> { .compatible = "qcom,sm8150-mdss" },
>> { .compatible = "qcom,sm8250-mdss" },
>> { .compatible = "qcom,sm8350-mdss" },
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 07/10] drm/msm/dpu: Add SM6375 support
2023-02-11 16:47 ` Dmitry Baryshkov
@ 2023-02-13 11:16 ` Konrad Dybcio
0 siblings, 0 replies; 36+ messages in thread
From: Konrad Dybcio @ 2023-02-13 11:16 UTC (permalink / raw)
To: Dmitry Baryshkov, linux-arm-msm, andersson, agross, krzysztof.kozlowski
Cc: marijn.suijten, Rob Clark, Abhinav Kumar, Sean Paul,
David Airlie, Daniel Vetter, Robert Foss,
AngeloGioacchino Del Regno, Vinod Koul, Vinod Polimera,
Stephen Boyd, Liu Shixin, dri-devel, freedreno, linux-kernel
On 11.02.2023 17:47, Dmitry Baryshkov wrote:
> On 11/02/2023 14:26, Konrad Dybcio wrote:
>> Add basic SM6375 support to the DPU1 driver to enable display output.
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> ---
In short, ack to all, thanks for prompt review.
Konrad
>> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 120 ++++++++++++++++++
>> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
>> drivers/gpu/drm/msm/msm_mdss.c | 1 +
>> 4 files changed, 123 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> index ba0bc795e5ff..327aa21f01fc 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> @@ -383,6 +383,24 @@ static const struct dpu_caps sm6350_dpu_caps = {
>> .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
>> };
>> +static const struct dpu_caps sm6375_dpu_caps = {
>> + .max_mixer_width = 2048,
>
> It looks like we got this wrong for sm6115, I
>
>> + .max_mixer_blendstages = 0x4,
>> + .qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
>
> QSEED4
>
> v3lite with the version >= 3.0 is v4. We should rework this to be more sensible and easy to support.
>
>> + .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
>> + .ubwc_version = DPU_HW_UBWC_VER_20,
>> + .has_dim_layer = true,
>> + .has_idle_pc = true,
>> + /*
>> + * There is *NO* 3DMERGE hw, but we *need* to set this property to true,
>> + * because SM6375 includes newer hardware that requires a different reset
>> + * sequence and it is executed based on this confusingly named variable..
>> + */
>> + .has_3d_merge = true,
>> + .max_linewidth = 2160,
>> + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
>> +};
>> +
>> static const struct dpu_caps sm8150_dpu_caps = {
>> .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
>> .max_mixer_blendstages = 0xb,
>> @@ -592,6 +610,19 @@ static const struct dpu_mdp_cfg sm6350_mdp[] = {
>> },
>> };
>> +static const struct dpu_mdp_cfg sm6375_mdp[] = {
>
> sm6116_mdp ?
>
>> + {
>> + .name = "top_0", .id = MDP_TOP,
>> + .base = 0x0, .len = 0x494,
>> + .features = 0,
>> + .highest_bank_bit = 0x1,
>> + .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
>> + .reg_off = 0x2ac, .bit_off = 0},
>> + .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
>> + .reg_off = 0x2ac, .bit_off = 8},
>> + },
>> +};
>> +
>> static const struct dpu_mdp_cfg sc8180x_mdp[] = {
>> {
>> .name = "top_0", .id = MDP_TOP,
>> @@ -1577,6 +1608,19 @@ static const struct dpu_lm_cfg sm6350_lm[] = {
>> &sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
>> };
>> +static const struct dpu_lm_sub_blks sm6375_lm_sblk = {
>
> qcm2290_lm_sblk after we fix the width there.
>
>> + .maxwidth = 2048,
>> + .maxblendstages = 4, /* excluding base layer */
>> + .blendstage_base = { /* offsets relative to mixer base */
>> + 0x20, 0x38, 0x50, 0x68
>> + },
>> +};
>> +
>> +static const struct dpu_lm_cfg sm6375_lm[] = {
>
> qcm2290_lm
>
>> + LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
>> + &sm6375_lm_sblk, PINGPONG_0, 0, DSPP_0),
>> +};
>> +
>> /* SM8150 */
>> static const struct dpu_lm_cfg sm8150_lm[] = {
>> @@ -1984,6 +2028,11 @@ static const struct dpu_intf_cfg sm6350_intf[] = {
>> INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 35, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
>> };
>> +static const struct dpu_intf_cfg sm6375_intf[] = {
>
> ack, size difference from sm6115/qcm2290
>
>> + INTF_BLK("intf_0", INTF_0, 0x00000, 0x2c0, INTF_NONE, 0, 0, 0, 0, 0, 0),
>> + INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
>> +};
>> +
>> static const struct dpu_intf_cfg sm8150_intf[] = {
>> INTF_BLK("intf_0", INTF_0, 0x6A000, 0x280, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
>> INTF_BLK("intf_1", INTF_1, 0x6A800, 0x280, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
>> @@ -2171,6 +2220,26 @@ static const struct dpu_reg_dma_cfg sc8280xp_regdma = {
>> .clk_ctrl = DPU_CLK_CTRL_REG_DMA,
>> };
>> +static const struct dpu_vbif_cfg sm6375_vbif[] = {
>> + {
>> + .name = "vbif_0", .id = VBIF_RT,
>> + .base = 0, .len = 0x2008,
>
> Ugh
>
>> + .features = BIT(DPU_VBIF_QOS_REMAP),
>> + .xin_halt_timeout = 0x4000,
>> + .qos_rp_remap_size = 0x40,
>> + .qos_rt_tbl = {
>> + .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
>> + .priority_lvl = sdm845_rt_pri_lvl,
>> + },
>> + .qos_nrt_tbl = {
>> + .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
>> + .priority_lvl = sdm845_nrt_pri_lvl,
>> + },
>> + .memtype_count = 14,
>> + .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
>> + },
>> +};
>> +
>> static const struct dpu_reg_dma_cfg sdm845_regdma = {
>> .base = 0x0, .version = 0x1, .trigger_sel_off = 0x119c
>> };
>> @@ -2460,6 +2529,34 @@ static const struct dpu_perf_cfg sm6350_perf_data = {
>> .bw_inefficiency_factor = 120,
>> };
>> +static const struct dpu_perf_cfg sm6375_perf_data = {
>> + .max_bw_low = 5200000,
>> + .max_bw_high = 6200000,
>> + .min_core_ib = 2500000,
>> + .min_llcc_ib = 0,
>> + .min_dram_ib = 1600000,
>> + .min_prefill_lines = 24,
>> + /* TODO: confirm danger_lut_tbl */
>> + .danger_lut_tbl = {0xffff, 0xffff, 0x0, 0x0, 0xffff},
>> + .qos_lut_tbl = {
>> + {.nentry = ARRAY_SIZE(sm6350_qos_linear),
>> + .entries = sm6350_qos_linear
>> + },
>> + {.nentry = ARRAY_SIZE(sm6350_qos_macrotile),
>> + .entries = sm6350_qos_macrotile
>> + },
>> + {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
>> + .entries = sc7180_qos_nrt
>> + },
>> + },
>> + .cdp_cfg = {
>> + {.rd_enable = 1, .wr_enable = 1},
>> + {.rd_enable = 1, .wr_enable = 0}
>> + },
>> + .clk_inefficiency_factor = 105,
>> + .bw_inefficiency_factor = 120,
>> +};
>> +
>> static const struct dpu_perf_cfg sm8150_perf_data = {
>> .max_bw_low = 12800000,
>> .max_bw_high = 12800000,
>> @@ -2804,6 +2901,28 @@ static const struct dpu_mdss_cfg sm6350_dpu_cfg = {
>> .mdss_irqs = IRQ_SC7180_MASK,
>> };
>> +static const struct dpu_mdss_cfg sm6375_dpu_cfg = {
>> + .caps = &sm6350_dpu_caps,
>> + .mdp_count = ARRAY_SIZE(sm6375_mdp),
>> + .mdp = sm6375_mdp,
>> + .ctl_count = ARRAY_SIZE(qcm2290_ctl),
>> + .ctl = qcm2290_ctl,
>> + .sspp_count = ARRAY_SIZE(sm6115_sspp),
>> + .sspp = sm6115_sspp,
>> + .mixer_count = ARRAY_SIZE(sm6375_lm),
>> + .mixer = sm6375_lm,
>> + .dspp_count = ARRAY_SIZE(qcm2290_dspp),
>> + .dspp = qcm2290_dspp,
>> + .pingpong_count = ARRAY_SIZE(qcm2290_pp),
>> + .pingpong = qcm2290_pp,
>> + .intf_count = ARRAY_SIZE(sm6375_intf),
>> + .intf = sm6375_intf,
>> + .vbif_count = ARRAY_SIZE(sm6375_vbif),
>> + .vbif = sm6375_vbif,
>> + .perf = &sm6375_perf_data,
>> + .mdss_irqs = IRQ_SC7180_MASK,
>> +};
>> +
>> static const struct dpu_mdss_cfg sm8150_dpu_cfg = {
>> .caps = &sm8150_dpu_caps,
>> .mdp_count = ARRAY_SIZE(sdm845_mdp),
>> @@ -3049,6 +3168,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
>> { .hw_rev = DPU_HW_VER_630, .dpu_cfg = &sm6115_dpu_cfg},
>> { .hw_rev = DPU_HW_VER_640, .dpu_cfg = &sm6350_dpu_cfg},
>> { .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg},
>> + { .hw_rev = DPU_HW_VER_690, .dpu_cfg = &sm6375_dpu_cfg},
>> { .hw_rev = DPU_HW_VER_700, .dpu_cfg = &sm8350_dpu_cfg},
>> { .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg},
>> { .hw_rev = DPU_HW_VER_800, .dpu_cfg = &sc8280xp_dpu_cfg},
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> index cbf21613e121..a22b5965acfe 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> @@ -47,6 +47,7 @@
>> #define DPU_HW_VER_630 DPU_HW_VER(6, 3, 0) /* sm6115|sm4250 */
>> #define DPU_HW_VER_640 DPU_HW_VER(6, 4, 0) /* sm6350 */
>> #define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */
>> +#define DPU_HW_VER_690 DPU_HW_VER(6, 9, 0) /* sm6375 */
>> #define DPU_HW_VER_700 DPU_HW_VER(7, 0, 0) /* sm8350 */
>> #define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */
>> #define DPU_HW_VER_800 DPU_HW_VER(8, 0, 0) /* sc8280xp */
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> index ebfbbd2d105e..fd561974a6b1 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> @@ -1307,6 +1307,7 @@ static const struct of_device_id dpu_dt_match[] = {
>> { .compatible = "qcom,sc8280xp-dpu", },
>> { .compatible = "qcom,sm6115-dpu", },
>> { .compatible = "qcom,sm6350-dpu", },
>> + { .compatible = "qcom,sm6375-dpu", },
>> { .compatible = "qcom,sm8150-dpu", },
>> { .compatible = "qcom,sm8250-dpu", },
>> { .compatible = "qcom,sm8350-dpu", },
>> diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
>> index 841016f3983a..fedc1a1fc289 100644
>> --- a/drivers/gpu/drm/msm/msm_mdss.c
>> +++ b/drivers/gpu/drm/msm/msm_mdss.c
>
> Please split to the separate patch
>
>> @@ -531,6 +531,7 @@ static const struct of_device_id mdss_dt_match[] = {
>> { .compatible = "qcom,sc8280xp-mdss" },
>> { .compatible = "qcom,sm6115-mdss" },
>> { .compatible = "qcom,sm6350-mdss" },
>> + { .compatible = "qcom,sm6375-mdss" },
>
> Missing UBWC setup.
>
>> { .compatible = "qcom,sm8150-mdss" },
>> { .compatible = "qcom,sm8250-mdss" },
>> { .compatible = "qcom,sm8350-mdss" },
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 06/10] drm/msm/dpu: Add SM6350 support
2023-02-13 11:15 ` Konrad Dybcio
@ 2023-02-13 11:30 ` Marijn Suijten
2023-02-13 11:35 ` Dmitry Baryshkov
0 siblings, 1 reply; 36+ messages in thread
From: Marijn Suijten @ 2023-02-13 11:30 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Dmitry Baryshkov, linux-arm-msm, andersson, agross,
krzysztof.kozlowski, Konrad Dybcio, Rob Clark, Abhinav Kumar,
Sean Paul, David Airlie, Daniel Vetter, Robert Foss,
AngeloGioacchino Del Regno, Vinod Koul, Vinod Polimera,
Stephen Boyd, Liu Shixin, dri-devel, freedreno, linux-kernel
On 2023-02-13 12:15:19, Konrad Dybcio wrote:
[...]
> >> @@ -1674,6 +1765,15 @@ static struct dpu_pingpong_cfg sc8280xp_pp[] = {
> >> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), -1),
> >> };
> >> +static struct dpu_pingpong_cfg sm6350_pp[] = {
> >> + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk,
> >
> > No TE support?
> It's.. complicated.. With just this patch, display refreshes, albeit
> not at 60fps. Marijn is working on getting it going, though
>
> https://github.com/SoMainline/linux/commits/marijn/longbois-next/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
This branch hasn't been updated for the longest time. I'm preparing v2
of the INTF TE series at:
https://github.com/SoMainline/linux/commits/marijn/dpu/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
and it has about ±40% of Dmitry's review applied. More to come now that
hiatus is over.
- Marijn
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 06/10] drm/msm/dpu: Add SM6350 support
2023-02-13 11:30 ` Marijn Suijten
@ 2023-02-13 11:35 ` Dmitry Baryshkov
2023-02-13 14:28 ` Marijn Suijten
0 siblings, 1 reply; 36+ messages in thread
From: Dmitry Baryshkov @ 2023-02-13 11:35 UTC (permalink / raw)
To: Marijn Suijten, Konrad Dybcio
Cc: linux-arm-msm, andersson, agross, krzysztof.kozlowski,
Konrad Dybcio, Rob Clark, Abhinav Kumar, Sean Paul, David Airlie,
Daniel Vetter, Robert Foss, AngeloGioacchino Del Regno,
Vinod Koul, Vinod Polimera, Stephen Boyd, Liu Shixin, dri-devel,
freedreno, linux-kernel
On 13/02/2023 13:30, Marijn Suijten wrote:
> On 2023-02-13 12:15:19, Konrad Dybcio wrote:
> [...]
>>>> @@ -1674,6 +1765,15 @@ static struct dpu_pingpong_cfg sc8280xp_pp[] = {
>>>> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), -1),
>>>> };
>>>> +static struct dpu_pingpong_cfg sm6350_pp[] = {
>>>> + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk,
>>>
>>> No TE support?
>> It's.. complicated.. With just this patch, display refreshes, albeit
>> not at 60fps. Marijn is working on getting it going, though
>>
>> https://github.com/SoMainline/linux/commits/marijn/longbois-next/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>
> This branch hasn't been updated for the longest time. I'm preparing v2
> of the INTF TE series at:
>
> https://github.com/SoMainline/linux/commits/marijn/dpu/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>
> and it has about ±40% of Dmitry's review applied. More to come now that
> hiatus is over.
We should agree on landing order for my rework vs your changes. Can I
try persuading you to review that 50-patches beast? With the hope that
you'd agree to land your changes on top of it?
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 05/10] drm/msm/dpu: Allow variable SSPP/INTF_BLK size
2023-02-13 11:12 ` Marijn Suijten
@ 2023-02-13 11:38 ` Dmitry Baryshkov
2023-02-13 14:31 ` Marijn Suijten
0 siblings, 1 reply; 36+ messages in thread
From: Dmitry Baryshkov @ 2023-02-13 11:38 UTC (permalink / raw)
To: Marijn Suijten, Konrad Dybcio
Cc: linux-arm-msm, andersson, agross, krzysztof.kozlowski, Rob Clark,
Abhinav Kumar, Sean Paul, David Airlie, Daniel Vetter,
Robert Foss, AngeloGioacchino Del Regno, dri-devel, freedreno,
linux-kernel
On 13/02/2023 13:12, Marijn Suijten wrote:
> On 2023-02-11 13:26:51, Konrad Dybcio wrote:
>> These blocks are of variable length on different SoCs. Set the
>> correct values where I was able to retrieve it from downstream
>> DTs and leave the old defaults (0x1c8 for sspp and 0x280 for
>> intf) otherwise.
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> ---
>> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 242 +++++++++---------
>> 1 file changed, 121 insertions(+), 121 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> index 802050118345..d9ef1e133c1e 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> [..]
>> @@ -1848,10 +1848,10 @@ static struct dpu_dsc_cfg sm8150_dsc[] = {
>> /*************************************************************
>> * INTF sub blocks config
>> *************************************************************/
>> -#define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \
>> +#define INTF_BLK(_name, _id, _base, _len, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \
>
> Dmitry and I discussed in #freedreno to instead add the INTF_BLK_DSI_TE
> macro that accounts for the INTF TE registers using this higher register
> area, as well as an extended signature to configure extra interrupts.
Yes, that's still the plan. It's slightly painful that we are touching
this are simultaneously.
>
> (Besides, I think the len is currently only used for snapshot dumping
> and no validation for out-of-blk reads/writes)
Yes. Because in most of the cases non-existing registers seem to be RAZ/WI.
>
>> {\
>> .name = _name, .id = _id, \
>> - .base = _base, .len = 0x280, \
>> + .base = _base, .len = _len, \
>> .features = _features, \
>> .type = _type, \
>> .controller_id = _ctrl_id, \
> [..]
>
> - Marijn
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 06/10] drm/msm/dpu: Add SM6350 support
2023-02-13 11:35 ` Dmitry Baryshkov
@ 2023-02-13 14:28 ` Marijn Suijten
2023-02-13 14:58 ` Dmitry Baryshkov
0 siblings, 1 reply; 36+ messages in thread
From: Marijn Suijten @ 2023-02-13 14:28 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Konrad Dybcio, linux-arm-msm, andersson, agross,
krzysztof.kozlowski, Konrad Dybcio, Rob Clark, Abhinav Kumar,
Sean Paul, David Airlie, Daniel Vetter, Robert Foss,
AngeloGioacchino Del Regno, Vinod Koul, Vinod Polimera,
Stephen Boyd, Liu Shixin, dri-devel, freedreno, linux-kernel
On 2023-02-13 13:35:01, Dmitry Baryshkov wrote:
> On 13/02/2023 13:30, Marijn Suijten wrote:
> > On 2023-02-13 12:15:19, Konrad Dybcio wrote:
> > [...]
> >>>> @@ -1674,6 +1765,15 @@ static struct dpu_pingpong_cfg sc8280xp_pp[] = {
> >>>> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), -1),
> >>>> };
> >>>> +static struct dpu_pingpong_cfg sm6350_pp[] = {
> >>>> + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk,
> >>>
> >>> No TE support?
> >> It's.. complicated.. With just this patch, display refreshes, albeit
> >> not at 60fps. Marijn is working on getting it going, though
> >>
> >> https://github.com/SoMainline/linux/commits/marijn/longbois-next/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> >
> > This branch hasn't been updated for the longest time. I'm preparing v2
> > of the INTF TE series at:
> >
> > https://github.com/SoMainline/linux/commits/marijn/dpu/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> >
> > and it has about ±40% of Dmitry's review applied. More to come now that
> > hiatus is over.
>
> We should agree on landing order for my rework vs your changes. Can I
> try persuading you to review that 50-patches beast? With the hope that
> you'd agree to land your changes on top of it?
SM6115 unexpectedly landing in advance of SM8[345]0 was already an
unnecessary headache to deal with, and now we're "changing direction" on
landing SM6350/75 in advance of INTF TE too... not to forget about
SM6125 which I also keep rebasing locally but planned on landing _after_
INTF TE. Regardless of the extra effort it will take from me I'd be
happy to land my patches after everyone else's to have final say over
which setup gets what bitflags and interrupts, as these typically got
botched in our trees after rebases leading to broken INTF TE.
Perhaps I should resubmit the individual Fixes: commits though?
Feel free to propose a merge order listing all the aforementioned SoCs,
your rework, my INTF TE patches and whatever else is in the pipeline.
As I've been away for a while, and only have limited hobby time (_and_
have to split that on various projects), I'm behind on what's currently
in swing for DPU (need additional time to catch back up) nor will be
able to rebase/resubmit my patches often (a set-in-stone merge order
will really help prioritise/plan ahead here).
Sure, I will at least start looking at your 50-patch as part of catching
back up. Do you want to process that on the mailing list or via
https://gitlab.freedesktop.org/drm/msm/-/merge_requests/44?
- Marijn
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 05/10] drm/msm/dpu: Allow variable SSPP/INTF_BLK size
2023-02-13 11:38 ` Dmitry Baryshkov
@ 2023-02-13 14:31 ` Marijn Suijten
2023-02-13 14:40 ` Dmitry Baryshkov
0 siblings, 1 reply; 36+ messages in thread
From: Marijn Suijten @ 2023-02-13 14:31 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Konrad Dybcio, linux-arm-msm, andersson, agross,
krzysztof.kozlowski, Rob Clark, Abhinav Kumar, Sean Paul,
David Airlie, Daniel Vetter, Robert Foss,
AngeloGioacchino Del Regno, dri-devel, freedreno, linux-kernel
On 2023-02-13 13:38:33, Dmitry Baryshkov wrote:
> On 13/02/2023 13:12, Marijn Suijten wrote:
> > On 2023-02-11 13:26:51, Konrad Dybcio wrote:
> >> These blocks are of variable length on different SoCs. Set the
> >> correct values where I was able to retrieve it from downstream
> >> DTs and leave the old defaults (0x1c8 for sspp and 0x280 for
> >> intf) otherwise.
> >>
> >> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> >> ---
> >> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 242 +++++++++---------
> >> 1 file changed, 121 insertions(+), 121 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> >> index 802050118345..d9ef1e133c1e 100644
> >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > [..]
> >> @@ -1848,10 +1848,10 @@ static struct dpu_dsc_cfg sm8150_dsc[] = {
> >> /*************************************************************
> >> * INTF sub blocks config
> >> *************************************************************/
> >> -#define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \
> >> +#define INTF_BLK(_name, _id, _base, _len, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \
> >
> > Dmitry and I discussed in #freedreno to instead add the INTF_BLK_DSI_TE
> > macro that accounts for the INTF TE registers using this higher register
> > area, as well as an extended signature to configure extra interrupts.
>
> Yes, that's still the plan. It's slightly painful that we are touching
> this are simultaneously.
Should we (Konrad) then drop this patch as there's no need to add these
(mostly RAZ/WI) registers to the dump until my INTF TE series starts
using them? That'll make rebasing easier on everyone too.
- Marijn
> > (Besides, I think the len is currently only used for snapshot dumping
> > and no validation for out-of-blk reads/writes)
>
> Yes. Because in most of the cases non-existing registers seem to be RAZ/WI.
>
> >
> >> {\
> >> .name = _name, .id = _id, \
> >> - .base = _base, .len = 0x280, \
> >> + .base = _base, .len = _len, \
> >> .features = _features, \
> >> .type = _type, \
> >> .controller_id = _ctrl_id, \
> > [..]
> >
> > - Marijn
>
> --
> With best wishes
> Dmitry
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 05/10] drm/msm/dpu: Allow variable SSPP/INTF_BLK size
2023-02-13 14:31 ` Marijn Suijten
@ 2023-02-13 14:40 ` Dmitry Baryshkov
2023-02-13 15:02 ` Marijn Suijten
0 siblings, 1 reply; 36+ messages in thread
From: Dmitry Baryshkov @ 2023-02-13 14:40 UTC (permalink / raw)
To: Marijn Suijten
Cc: Konrad Dybcio, linux-arm-msm, andersson, agross,
krzysztof.kozlowski, Rob Clark, Abhinav Kumar, Sean Paul,
David Airlie, Daniel Vetter, Robert Foss,
AngeloGioacchino Del Regno, dri-devel, freedreno, linux-kernel
On 13/02/2023 16:31, Marijn Suijten wrote:
> On 2023-02-13 13:38:33, Dmitry Baryshkov wrote:
>> On 13/02/2023 13:12, Marijn Suijten wrote:
>>> On 2023-02-11 13:26:51, Konrad Dybcio wrote:
>>>> These blocks are of variable length on different SoCs. Set the
>>>> correct values where I was able to retrieve it from downstream
>>>> DTs and leave the old defaults (0x1c8 for sspp and 0x280 for
>>>> intf) otherwise.
>>>>
>>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>>>> ---
>>>> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 242 +++++++++---------
>>>> 1 file changed, 121 insertions(+), 121 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>>> index 802050118345..d9ef1e133c1e 100644
>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>> [..]
>>>> @@ -1848,10 +1848,10 @@ static struct dpu_dsc_cfg sm8150_dsc[] = {
>>>> /*************************************************************
>>>> * INTF sub blocks config
>>>> *************************************************************/
>>>> -#define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \
>>>> +#define INTF_BLK(_name, _id, _base, _len, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \
>>>
>>> Dmitry and I discussed in #freedreno to instead add the INTF_BLK_DSI_TE
>>> macro that accounts for the INTF TE registers using this higher register
>>> area, as well as an extended signature to configure extra interrupts.
>>
>> Yes, that's still the plan. It's slightly painful that we are touching
>> this are simultaneously.
>
> Should we (Konrad) then drop this patch as there's no need to add these
> (mostly RAZ/WI) registers to the dump until my INTF TE series starts
> using them? That'll make rebasing easier on everyone too.
RAZ/WI is for not present registers (read-as-zero/write-ignore). I think
that the growing register space is getting populated with registers
(which we have been ignoring up to now).
>
> - Marijn
>
>>> (Besides, I think the len is currently only used for snapshot dumping
>>> and no validation for out-of-blk reads/writes)
>>
>> Yes. Because in most of the cases non-existing registers seem to be RAZ/WI.
>>
>>>
>>>> {\
>>>> .name = _name, .id = _id, \
>>>> - .base = _base, .len = 0x280, \
>>>> + .base = _base, .len = _len, \
>>>> .features = _features, \
>>>> .type = _type, \
>>>> .controller_id = _ctrl_id, \
>>> [..]
>>>
>>> - Marijn
>>
>> --
>> With best wishes
>> Dmitry
>>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 06/10] drm/msm/dpu: Add SM6350 support
2023-02-13 14:28 ` Marijn Suijten
@ 2023-02-13 14:58 ` Dmitry Baryshkov
2023-02-13 15:13 ` Dmitry Baryshkov
2023-02-13 15:14 ` Marijn Suijten
0 siblings, 2 replies; 36+ messages in thread
From: Dmitry Baryshkov @ 2023-02-13 14:58 UTC (permalink / raw)
To: Marijn Suijten
Cc: Konrad Dybcio, linux-arm-msm, andersson, agross,
krzysztof.kozlowski, Konrad Dybcio, Rob Clark, Abhinav Kumar,
Sean Paul, David Airlie, Daniel Vetter, Robert Foss,
AngeloGioacchino Del Regno, Vinod Koul, Vinod Polimera,
Stephen Boyd, Liu Shixin, dri-devel, freedreno, linux-kernel
On 13/02/2023 16:28, Marijn Suijten wrote:
> On 2023-02-13 13:35:01, Dmitry Baryshkov wrote:
>> On 13/02/2023 13:30, Marijn Suijten wrote:
>>> On 2023-02-13 12:15:19, Konrad Dybcio wrote:
>>> [...]
>>>>>> @@ -1674,6 +1765,15 @@ static struct dpu_pingpong_cfg sc8280xp_pp[] = {
>>>>>> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), -1),
>>>>>> };
>>>>>> +static struct dpu_pingpong_cfg sm6350_pp[] = {
>>>>>> + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk,
>>>>>
>>>>> No TE support?
>>>> It's.. complicated.. With just this patch, display refreshes, albeit
>>>> not at 60fps. Marijn is working on getting it going, though
>>>>
>>>> https://github.com/SoMainline/linux/commits/marijn/longbois-next/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>>
>>> This branch hasn't been updated for the longest time. I'm preparing v2
>>> of the INTF TE series at:
>>>
>>> https://github.com/SoMainline/linux/commits/marijn/dpu/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>>
>>> and it has about ±40% of Dmitry's review applied. More to come now that
>>> hiatus is over.
>>
>> We should agree on landing order for my rework vs your changes. Can I
>> try persuading you to review that 50-patches beast? With the hope that
>> you'd agree to land your changes on top of it?
>
> SM6115 unexpectedly landing in advance of SM8[345]0 was already an
> unnecessary headache to deal with, and now we're "changing direction" on
> landing SM6350/75 in advance of INTF TE too... not to forget about
> SM6125 which I also keep rebasing locally but planned on landing _after_
> INTF TE. Regardless of the extra effort it will take from me I'd be
> happy to land my patches after everyone else's to have final say over
> which setup gets what bitflags and interrupts, as these typically got
> botched in our trees after rebases leading to broken INTF TE.
> Perhaps I should resubmit the individual Fixes: commits though?
What is the current status of your INTF TE patchset? If it's mostly
ready, I can rebase my patch-bomb on top of it.
I definitely do not want to merge new platforms before sorting out INTF
TE and the catalog. Handling sc8280xp, sm8350, sm8450 and sm6115 was a
nightmare. The restructure targets making addition of new platforms simpler.
> Feel free to propose a merge order listing all the aforementioned SoCs,
> your rework, my INTF TE patches and whatever else is in the pipeline.
> As I've been away for a while, and only have limited hobby time (_and_
> have to split that on various projects), I'm behind on what's currently
> in swing for DPU (need additional time to catch back up) nor will be
> able to rebase/resubmit my patches often (a set-in-stone merge order
> will really help prioritise/plan ahead here).
We have several patchsets in the pipeline (PSR, color-transformation
rework, wide planes) which do not touch the catalog, so the amount of
conflicts should be pretty minimal. We are still waiting for DSC 1.2 v2,
but it definitely will take time to mature even if v2 is posted today.
So, *possible* the merge order is the following:
- fixes from https://patchwork.freedesktop.org/series/113910/ go to
msm-fixes
- fixes from your intf-te go to msm-fixes
- https://patchwork.freedesktop.org/series/111751/
- the rest of intf-te and catalog (*see below)
- DPU features
- new DPU platforms (might go together with DPU features)
* That really depends on the availability of the patchsets. Most
probably, as your patchset also contains several fixups, it would be
easier to land it before catalog split/rework.
So, if you have the available timeslot, could you please finish & send
intf te on top of msm-next.
> Sure, I will at least start looking at your 50-patch as part of catching
> back up. Do you want to process that on the mailing list or via
> https://gitlab.freedesktop.org/drm/msm/-/merge_requests/44?
I'd prefer to use email. The MR was open to doublecheck that nothing got
broken on sc7180.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 05/10] drm/msm/dpu: Allow variable SSPP/INTF_BLK size
2023-02-13 14:40 ` Dmitry Baryshkov
@ 2023-02-13 15:02 ` Marijn Suijten
2023-02-13 15:05 ` Dmitry Baryshkov
0 siblings, 1 reply; 36+ messages in thread
From: Marijn Suijten @ 2023-02-13 15:02 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Konrad Dybcio, linux-arm-msm, andersson, agross,
krzysztof.kozlowski, Rob Clark, Abhinav Kumar, Sean Paul,
David Airlie, Daniel Vetter, Robert Foss,
AngeloGioacchino Del Regno, dri-devel, freedreno, linux-kernel
On 2023-02-13 16:40:56, Dmitry Baryshkov wrote:
> On 13/02/2023 16:31, Marijn Suijten wrote:
> > On 2023-02-13 13:38:33, Dmitry Baryshkov wrote:
> >> On 13/02/2023 13:12, Marijn Suijten wrote:
> >>> On 2023-02-11 13:26:51, Konrad Dybcio wrote:
> >>>> These blocks are of variable length on different SoCs. Set the
> >>>> correct values where I was able to retrieve it from downstream
> >>>> DTs and leave the old defaults (0x1c8 for sspp and 0x280 for
> >>>> intf) otherwise.
> >>>>
> >>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> >>>> ---
> >>>> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 242 +++++++++---------
> >>>> 1 file changed, 121 insertions(+), 121 deletions(-)
> >>>>
> >>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> >>>> index 802050118345..d9ef1e133c1e 100644
> >>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> >>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> >>> [..]
> >>>> @@ -1848,10 +1848,10 @@ static struct dpu_dsc_cfg sm8150_dsc[] = {
> >>>> /*************************************************************
> >>>> * INTF sub blocks config
> >>>> *************************************************************/
> >>>> -#define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \
> >>>> +#define INTF_BLK(_name, _id, _base, _len, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \
> >>>
> >>> Dmitry and I discussed in #freedreno to instead add the INTF_BLK_DSI_TE
> >>> macro that accounts for the INTF TE registers using this higher register
> >>> area, as well as an extended signature to configure extra interrupts.
> >>
> >> Yes, that's still the plan. It's slightly painful that we are touching
> >> this are simultaneously.
> >
> > Should we (Konrad) then drop this patch as there's no need to add these
> > (mostly RAZ/WI) registers to the dump until my INTF TE series starts
> > using them? That'll make rebasing easier on everyone too.
>
> RAZ/WI is for not present registers (read-as-zero/write-ignore). I think
> that the growing register space is getting populated with registers
> (which we have been ignoring up to now).
They are, but not until my INTF TE series lands; hence again the request
to drop this patch until that happens?
- Marijn
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 05/10] drm/msm/dpu: Allow variable SSPP/INTF_BLK size
2023-02-13 15:02 ` Marijn Suijten
@ 2023-02-13 15:05 ` Dmitry Baryshkov
0 siblings, 0 replies; 36+ messages in thread
From: Dmitry Baryshkov @ 2023-02-13 15:05 UTC (permalink / raw)
To: Marijn Suijten
Cc: Konrad Dybcio, linux-arm-msm, andersson, agross,
krzysztof.kozlowski, Rob Clark, Abhinav Kumar, Sean Paul,
David Airlie, Daniel Vetter, Robert Foss,
AngeloGioacchino Del Regno, dri-devel, freedreno, linux-kernel
On 13/02/2023 17:02, Marijn Suijten wrote:
> On 2023-02-13 16:40:56, Dmitry Baryshkov wrote:
>> On 13/02/2023 16:31, Marijn Suijten wrote:
>>> On 2023-02-13 13:38:33, Dmitry Baryshkov wrote:
>>>> On 13/02/2023 13:12, Marijn Suijten wrote:
>>>>> On 2023-02-11 13:26:51, Konrad Dybcio wrote:
>>>>>> These blocks are of variable length on different SoCs. Set the
>>>>>> correct values where I was able to retrieve it from downstream
>>>>>> DTs and leave the old defaults (0x1c8 for sspp and 0x280 for
>>>>>> intf) otherwise.
>>>>>>
>>>>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>>>>>> ---
>>>>>> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 242 +++++++++---------
>>>>>> 1 file changed, 121 insertions(+), 121 deletions(-)
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>>>>> index 802050118345..d9ef1e133c1e 100644
>>>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>>>> [..]
>>>>>> @@ -1848,10 +1848,10 @@ static struct dpu_dsc_cfg sm8150_dsc[] = {
>>>>>> /*************************************************************
>>>>>> * INTF sub blocks config
>>>>>> *************************************************************/
>>>>>> -#define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \
>>>>>> +#define INTF_BLK(_name, _id, _base, _len, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \
>>>>>
>>>>> Dmitry and I discussed in #freedreno to instead add the INTF_BLK_DSI_TE
>>>>> macro that accounts for the INTF TE registers using this higher register
>>>>> area, as well as an extended signature to configure extra interrupts.
>>>>
>>>> Yes, that's still the plan. It's slightly painful that we are touching
>>>> this are simultaneously.
>>>
>>> Should we (Konrad) then drop this patch as there's no need to add these
>>> (mostly RAZ/WI) registers to the dump until my INTF TE series starts
>>> using them? That'll make rebasing easier on everyone too.
>>
>> RAZ/WI is for not present registers (read-as-zero/write-ignore). I think
>> that the growing register space is getting populated with registers
>> (which we have been ignoring up to now).
>
> They are, but not until my INTF TE series lands; hence again the request
> to drop this patch until that happens?
I see nothing wrong with including them into the snapshots.
Dropping this single patch will still result in the huge amount of
rejects. So, let's get your INTF TE done, I'll rebase my work on top of it.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 03/10] dt-bindings: display/msm: Add SM6350 DPU & MDSS
2023-02-11 12:26 ` [PATCH 03/10] dt-bindings: display/msm: Add SM6350 DPU & MDSS Konrad Dybcio
2023-02-11 16:33 ` Dmitry Baryshkov
@ 2023-02-13 15:09 ` Rob Herring
1 sibling, 0 replies; 36+ messages in thread
From: Rob Herring @ 2023-02-13 15:09 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Sean Paul, Abhinav Kumar, Rob Clark, linux-kernel,
Dmitry Baryshkov, linux-arm-msm, Daniel Vetter, Rob Herring,
Krishna Manikandan, devicetree, Krzysztof Kozlowski, freedreno,
marijn.suijten, David Airlie, andersson, dri-devel,
krzysztof.kozlowski, agross
On Sat, 11 Feb 2023 13:26:49 +0100, Konrad Dybcio wrote:
> Document 6350 DPU and MDSS.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> .../bindings/display/msm/qcom,sm6350-dpu.yaml | 94 ++++++++
> .../display/msm/qcom,sm6350-mdss.yaml | 213 ++++++++++++++++++
> 2 files changed, 307 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml
> create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
./Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml:55:11: [warning] wrong indentation: expected 8 but found 10 (indentation)
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml: patternProperties:^dsi@[0-9a-f]+$:properties:compatible: [{'const': 'qcom,sm6350-dsi-ctrl'}, {'const': 'qcom,mdss-dsi-ctrl'}] is not of type 'object', 'boolean'
from schema $id: http://json-schema.org/draft-07/schema#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml: ignoring, error in schema: patternProperties: ^dsi@[0-9a-f]+$: properties: compatible
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.example.dtb: dsi@ae94000: compatible:0: 'qcom,sm6350-dsi-ctrl' is not one of ['qcom,mdss-dsi-ctrl', 'qcom,dsi-ctrl-6g-qcm2290']
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.example.dtb: dsi@ae94000: compatible: ['qcom,sm6350-dsi-ctrl', 'qcom,mdss-dsi-ctrl'] is too long
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.example.dtb: phy@ae94400: 'vdds-supply' is a required property
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230211122656.1479141-4-konrad.dybcio@linaro.org
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 04/10] dt-bindings: display/msm: Add SM6375 DPU & MDSS
2023-02-11 12:26 ` [PATCH 04/10] dt-bindings: display/msm: Add SM6375 " Konrad Dybcio
@ 2023-02-13 15:09 ` Rob Herring
0 siblings, 0 replies; 36+ messages in thread
From: Rob Herring @ 2023-02-13 15:09 UTC (permalink / raw)
To: Konrad Dybcio
Cc: andersson, Daniel Vetter, krzysztof.kozlowski, dri-devel,
David Airlie, Sean Paul, Krzysztof Kozlowski, Rob Clark,
Dmitry Baryshkov, devicetree, Rob Herring, linux-kernel,
marijn.suijten, freedreno, Abhinav Kumar, linux-arm-msm, agross
On Sat, 11 Feb 2023 13:26:50 +0100, Konrad Dybcio wrote:
> Document SM6375 DPU and MDSS.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> .../bindings/display/msm/qcom,sm6375-dpu.yaml | 106 +++++++++
> .../display/msm/qcom,sm6375-mdss.yaml | 216 ++++++++++++++++++
> 2 files changed, 322 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm6375-dpu.yaml
> create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.example.dtb: dsi@5e94000: compatible:0: 'qcom,sm6375-dsi-ctrl' is not one of ['qcom,mdss-dsi-ctrl', 'qcom,dsi-ctrl-6g-qcm2290']
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.example.dtb: dsi@5e94000: compatible: ['qcom,sm6375-dsi-ctrl', 'qcom,mdss-dsi-ctrl'] is too long
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230211122656.1479141-5-konrad.dybcio@linaro.org
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 06/10] drm/msm/dpu: Add SM6350 support
2023-02-13 14:58 ` Dmitry Baryshkov
@ 2023-02-13 15:13 ` Dmitry Baryshkov
2023-02-13 15:14 ` Marijn Suijten
1 sibling, 0 replies; 36+ messages in thread
From: Dmitry Baryshkov @ 2023-02-13 15:13 UTC (permalink / raw)
To: Marijn Suijten
Cc: Konrad Dybcio, linux-arm-msm, andersson, agross,
krzysztof.kozlowski, Konrad Dybcio, Rob Clark, Abhinav Kumar,
Sean Paul, David Airlie, Daniel Vetter, Robert Foss,
AngeloGioacchino Del Regno, Vinod Koul, Vinod Polimera,
Stephen Boyd, Liu Shixin, dri-devel, freedreno, linux-kernel
On 13/02/2023 16:58, Dmitry Baryshkov wrote:
> On 13/02/2023 16:28, Marijn Suijten wrote:
>> Feel free to propose a merge order listing all the aforementioned SoCs,
>> your rework, my INTF TE patches and whatever else is in the pipeline.
>> As I've been away for a while, and only have limited hobby time (_and_
>> have to split that on various projects), I'm behind on what's currently
>> in swing for DPU (need additional time to catch back up) nor will be
>> able to rebase/resubmit my patches often (a set-in-stone merge order
>> will really help prioritise/plan ahead here).
>
> We have several patchsets in the pipeline (PSR, color-transformation
> rework, wide planes) which do not touch the catalog, so the amount of
> conflicts should be pretty minimal. We are still waiting for DSC 1.2 v2,
> but it definitely will take time to mature even if v2 is posted today.
>
> So, *possible* the merge order is the following:
> - fixes from https://patchwork.freedesktop.org/series/113910/ go to
> msm-fixes
> - fixes from your intf-te go to msm-fixes
> - https://patchwork.freedesktop.org/series/111751/
> - the rest of intf-te and catalog (*see below)
> - DPU features
> - new DPU platforms (might go together with DPU features)
Just to clarify here: I want to hold on adding new platforms to DPU
driver only. MDSS, DSI etc. patches are free to go.
>
> * That really depends on the availability of the patchsets. Most
> probably, as your patchset also contains several fixups, it would be
> easier to land it before catalog split/rework.
>
> So, if you have the available timeslot, could you please finish & send
> intf te on top of msm-next.
>
>> Sure, I will at least start looking at your 50-patch as part of catching
>> back up. Do you want to process that on the mailing list or via
>> https://gitlab.freedesktop.org/drm/msm/-/merge_requests/44?
>
> I'd prefer to use email. The MR was open to doublecheck that nothing got
> broken on sc7180.
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 06/10] drm/msm/dpu: Add SM6350 support
2023-02-13 14:58 ` Dmitry Baryshkov
2023-02-13 15:13 ` Dmitry Baryshkov
@ 2023-02-13 15:14 ` Marijn Suijten
2023-02-13 16:25 ` Dmitry Baryshkov
1 sibling, 1 reply; 36+ messages in thread
From: Marijn Suijten @ 2023-02-13 15:14 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Konrad Dybcio, linux-arm-msm, andersson, agross,
krzysztof.kozlowski, Konrad Dybcio, Rob Clark, Abhinav Kumar,
Sean Paul, David Airlie, Daniel Vetter, Robert Foss,
AngeloGioacchino Del Regno, Vinod Koul, Vinod Polimera,
Stephen Boyd, Liu Shixin, dri-devel, freedreno, linux-kernel
On 2023-02-13 16:58:00, Dmitry Baryshkov wrote:
> On 13/02/2023 16:28, Marijn Suijten wrote:
> > On 2023-02-13 13:35:01, Dmitry Baryshkov wrote:
> >> On 13/02/2023 13:30, Marijn Suijten wrote:
> >>> On 2023-02-13 12:15:19, Konrad Dybcio wrote:
> >>> [...]
> >>>>>> @@ -1674,6 +1765,15 @@ static struct dpu_pingpong_cfg sc8280xp_pp[] = {
> >>>>>> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), -1),
> >>>>>> };
> >>>>>> +static struct dpu_pingpong_cfg sm6350_pp[] = {
> >>>>>> + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk,
> >>>>>
> >>>>> No TE support?
> >>>> It's.. complicated.. With just this patch, display refreshes, albeit
> >>>> not at 60fps. Marijn is working on getting it going, though
> >>>>
> >>>> https://github.com/SoMainline/linux/commits/marijn/longbois-next/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> >>>
> >>> This branch hasn't been updated for the longest time. I'm preparing v2
> >>> of the INTF TE series at:
> >>>
> >>> https://github.com/SoMainline/linux/commits/marijn/dpu/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> >>>
> >>> and it has about ±40% of Dmitry's review applied. More to come now that
> >>> hiatus is over.
> >>
> >> We should agree on landing order for my rework vs your changes. Can I
> >> try persuading you to review that 50-patches beast? With the hope that
> >> you'd agree to land your changes on top of it?
> >
> > SM6115 unexpectedly landing in advance of SM8[345]0 was already an
> > unnecessary headache to deal with, and now we're "changing direction" on
> > landing SM6350/75 in advance of INTF TE too... not to forget about
> > SM6125 which I also keep rebasing locally but planned on landing _after_
> > INTF TE. Regardless of the extra effort it will take from me I'd be
> > happy to land my patches after everyone else's to have final say over
> > which setup gets what bitflags and interrupts, as these typically got
> > botched in our trees after rebases leading to broken INTF TE.
> > Perhaps I should resubmit the individual Fixes: commits though?
>
> What is the current status of your INTF TE patchset? If it's mostly
> ready, I can rebase my patch-bomb on top of it.
The catalog part is ready [1] and was rebased on -next a "week" ago, and
does not depend on any of the SM6125/6350/75 series. All that remains
is addressing review comments regarding restructuring function and
function pointer layout.
[1]: https://github.com/SoMainline/linux/commits/marijn/dpu/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> I definitely do not want to merge new platforms before sorting out INTF
> TE and the catalog. Handling sc8280xp, sm8350, sm8450 and sm6115 was a
> nightmare. The restructure targets making addition of new platforms simpler.
Ack, totally agree here, massive rebase conflict nightmare not to
mention fixups/followups.
> > Feel free to propose a merge order listing all the aforementioned SoCs,
> > your rework, my INTF TE patches and whatever else is in the pipeline.
> > As I've been away for a while, and only have limited hobby time (_and_
> > have to split that on various projects), I'm behind on what's currently
> > in swing for DPU (need additional time to catch back up) nor will be
> > able to rebase/resubmit my patches often (a set-in-stone merge order
> > will really help prioritise/plan ahead here).
>
> We have several patchsets in the pipeline (PSR, color-transformation
> rework, wide planes) which do not touch the catalog, so the amount of
> conflicts should be pretty minimal.
Sounds good.
> We are still waiting for DSC 1.2 v2,
> but it definitely will take time to mature even if v2 is posted today.
That'll hit the catalog to a minimal extent (I guess, to describe new
blocks / with a feature flag) but should be easy to delay / rebase.
> So, *possible* the merge order is the following:
> - fixes from https://patchwork.freedesktop.org/series/113910/ go to
> msm-fixes
> - fixes from your intf-te go to msm-fixes
> - https://patchwork.freedesktop.org/series/111751/
> - the rest of intf-te and catalog (*see below)
> - DPU features
> - new DPU platforms (might go together with DPU features)
>
> * That really depends on the availability of the patchsets. Most
> probably, as your patchset also contains several fixups, it would be
> easier to land it before catalog split/rework.
>
> So, if you have the available timeslot, could you please finish & send
> intf te on top of msm-next.
Ack, I'll get to that immediately. You might even pull in the
intermediate patches linked above (that touch the catalog) to see how it
integrates, if I remember correctly (it has been a while) the catalog
changes should now be independent of driver changes...?
> > Sure, I will at least start looking at your 50-patch as part of catching
> > back up. Do you want to process that on the mailing list or via
> > https://gitlab.freedesktop.org/drm/msm/-/merge_requests/44?
>
> I'd prefer to use email. The MR was open to doublecheck that nothing got
> broken on sc7180.
Ack; will try providing feedback on the 50-patch series via email in
parallel to getting INTF TE v2 out ASAP. As discussed before I should
probably add myself as reviewer to the drm/msm subsystem to have these
patches in my inbox from the get-go though...
- Marijn
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 06/10] drm/msm/dpu: Add SM6350 support
2023-02-13 15:14 ` Marijn Suijten
@ 2023-02-13 16:25 ` Dmitry Baryshkov
2023-02-13 19:14 ` [Freedreno] " Abhinav Kumar
0 siblings, 1 reply; 36+ messages in thread
From: Dmitry Baryshkov @ 2023-02-13 16:25 UTC (permalink / raw)
To: Marijn Suijten
Cc: Konrad Dybcio, linux-arm-msm, andersson, agross,
krzysztof.kozlowski, Konrad Dybcio, Rob Clark, Abhinav Kumar,
Sean Paul, David Airlie, Daniel Vetter, Robert Foss,
AngeloGioacchino Del Regno, Vinod Koul, Vinod Polimera,
Stephen Boyd, Liu Shixin, dri-devel, freedreno, linux-kernel
On 13/02/2023 17:14, Marijn Suijten wrote:
> On 2023-02-13 16:58:00, Dmitry Baryshkov wrote:
>> So, *possible* the merge order is the following:
>> - fixes from https://patchwork.freedesktop.org/series/113910/ go to
>> msm-fixes
>> - fixes from your intf-te go to msm-fixes
>> - https://patchwork.freedesktop.org/series/111751/
>> - the rest of intf-te and catalog (*see below)
>> - DPU features
>> - new DPU platforms (might go together with DPU features)
>>
>> * That really depends on the availability of the patchsets. Most
>> probably, as your patchset also contains several fixups, it would be
>> easier to land it before catalog split/rework.
>>
>> So, if you have the available timeslot, could you please finish & send
>> intf te on top of msm-next.
>
> Ack, I'll get to that immediately. You might even pull in the
> intermediate patches linked above (that touch the catalog) to see how it
> integrates, if I remember correctly (it has been a while) the catalog
> changes should now be independent of driver changes...?
I'll check and if it goes well, I'll just cherry-pick them into my branch.
>
>>> Sure, I will at least start looking at your 50-patch as part of catching
>>> back up. Do you want to process that on the mailing list or via
>>> https://gitlab.freedesktop.org/drm/msm/-/merge_requests/44?
>>
>> I'd prefer to use email. The MR was open to doublecheck that nothing got
>> broken on sc7180.
>
> Ack; will try providing feedback on the 50-patch series via email in
> parallel to getting INTF TE v2 out ASAP. As discussed before I should
> probably add myself as reviewer to the drm/msm subsystem to have these
> patches in my inbox from the get-go though...
I'd support this.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Freedreno] [PATCH 06/10] drm/msm/dpu: Add SM6350 support
2023-02-13 16:25 ` Dmitry Baryshkov
@ 2023-02-13 19:14 ` Abhinav Kumar
2023-02-13 20:24 ` Dmitry Baryshkov
0 siblings, 1 reply; 36+ messages in thread
From: Abhinav Kumar @ 2023-02-13 19:14 UTC (permalink / raw)
To: Dmitry Baryshkov, Marijn Suijten
Cc: Vinod Koul, Liu Shixin, Robert Foss, linux-arm-msm, andersson,
Konrad Dybcio, Rob Clark, Stephen Boyd, Konrad Dybcio, freedreno,
krzysztof.kozlowski, agross, dri-devel, Daniel Vetter,
AngeloGioacchino Del Regno, David Airlie, Vinod Polimera,
Sean Paul, linux-kernel
On 2/13/2023 8:25 AM, Dmitry Baryshkov wrote:
> On 13/02/2023 17:14, Marijn Suijten wrote:
>> On 2023-02-13 16:58:00, Dmitry Baryshkov wrote:
>>> So, *possible* the merge order is the following:
>>> - fixes from https://patchwork.freedesktop.org/series/113910/ go to
>>> msm-fixes
>>> - fixes from your intf-te go to msm-fixes
>>> - https://patchwork.freedesktop.org/series/111751/
>>> - the rest of intf-te and catalog (*see below)
>>> - DPU features
>>> - new DPU platforms (might go together with DPU features)
>>>
Fixes from https://patchwork.freedesktop.org/series/113910/ can be
pulled into -fixes. Will send it out in a MR. I can see that you have
absorbed a couple of independent fixes into this too (which were already
reviewed outside the HW catalog rework series)
And from the intf TE series only this one right?
https://patchwork.freedesktop.org/patch/516429/
Other than this there are no "fixes" in that series.
>>> * That really depends on the availability of the patchsets. Most
>>> probably, as your patchset also contains several fixups, it would be
>>> easier to land it before catalog split/rework.
>>>
>>> So, if you have the available timeslot, could you please finish & send
>>> intf te on top of msm-next.
>>
>> Ack, I'll get to that immediately. You might even pull in the
>> intermediate patches linked above (that touch the catalog) to see how it
>> integrates, if I remember correctly (it has been a while) the catalog
>> changes should now be independent of driver changes...?
>
> I'll check and if it goes well, I'll just cherry-pick them into my branch.
>
>>
>>>> Sure, I will at least start looking at your 50-patch as part of
>>>> catching
>>>> back up. Do you want to process that on the mailing list or via
>>>> https://gitlab.freedesktop.org/drm/msm/-/merge_requests/44?
>>>
>>> I'd prefer to use email. The MR was open to doublecheck that nothing got
>>> broken on sc7180.
>>
>> Ack; will try providing feedback on the 50-patch series via email in
>> parallel to getting INTF TE v2 out ASAP. As discussed before I should
>> probably add myself as reviewer to the drm/msm subsystem to have these
>> patches in my inbox from the get-go though...
>
Jessica had some minor comments/questions on the intf te series. We have
finished integrating and testing that on sm8350 while bringing up the
DSC 1.2 panel and thats what led to
https://patchwork.freedesktop.org/series/113851/
Please wait for her comments / R-b .
> I'd support this.
>
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Freedreno] [PATCH 06/10] drm/msm/dpu: Add SM6350 support
2023-02-13 19:14 ` [Freedreno] " Abhinav Kumar
@ 2023-02-13 20:24 ` Dmitry Baryshkov
0 siblings, 0 replies; 36+ messages in thread
From: Dmitry Baryshkov @ 2023-02-13 20:24 UTC (permalink / raw)
To: Abhinav Kumar
Cc: Marijn Suijten, Vinod Koul, Liu Shixin, Robert Foss,
linux-arm-msm, andersson, Konrad Dybcio, Rob Clark, Stephen Boyd,
Konrad Dybcio, freedreno, krzysztof.kozlowski, agross, dri-devel,
Daniel Vetter, AngeloGioacchino Del Regno, David Airlie,
Vinod Polimera, Sean Paul, linux-kernel
On Mon, 13 Feb 2023 at 21:14, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
> On 2/13/2023 8:25 AM, Dmitry Baryshkov wrote:
> > On 13/02/2023 17:14, Marijn Suijten wrote:
> >> On 2023-02-13 16:58:00, Dmitry Baryshkov wrote:
> >>> So, *possible* the merge order is the following:
> >>> - fixes from https://patchwork.freedesktop.org/series/113910/ go to
> >>> msm-fixes
> >>> - fixes from your intf-te go to msm-fixes
> >>> - https://patchwork.freedesktop.org/series/111751/
> >>> - the rest of intf-te and catalog (*see below)
> >>> - DPU features
> >>> - new DPU platforms (might go together with DPU features)
> >>>
>
> Fixes from https://patchwork.freedesktop.org/series/113910/ can be
> pulled into -fixes. Will send it out in a MR. I can see that you have
> absorbed a couple of independent fixes into this too (which were already
> reviewed outside the HW catalog rework series)
>
> And from the intf TE series only this one right?
>
> https://patchwork.freedesktop.org/patch/516429/
I think so. At least in the first submission.
>
> Other than this there are no "fixes" in that series.
>
> >>> * That really depends on the availability of the patchsets. Most
> >>> probably, as your patchset also contains several fixups, it would be
> >>> easier to land it before catalog split/rework.
> >>>
> >>> So, if you have the available timeslot, could you please finish & send
> >>> intf te on top of msm-next.
> >>
> >> Ack, I'll get to that immediately. You might even pull in the
> >> intermediate patches linked above (that touch the catalog) to see how it
> >> integrates, if I remember correctly (it has been a while) the catalog
> >> changes should now be independent of driver changes...?
> >
> > I'll check and if it goes well, I'll just cherry-pick them into my branch.
> >
> >>
> >>>> Sure, I will at least start looking at your 50-patch as part of
> >>>> catching
> >>>> back up. Do you want to process that on the mailing list or via
> >>>> https://gitlab.freedesktop.org/drm/msm/-/merge_requests/44?
> >>>
> >>> I'd prefer to use email. The MR was open to doublecheck that nothing got
> >>> broken on sc7180.
> >>
> >> Ack; will try providing feedback on the 50-patch series via email in
> >> parallel to getting INTF TE v2 out ASAP. As discussed before I should
> >> probably add myself as reviewer to the drm/msm subsystem to have these
> >> patches in my inbox from the get-go though...
> >
>
> Jessica had some minor comments/questions on the intf te series. We have
> finished integrating and testing that on sm8350 while bringing up the
> DSC 1.2 panel and thats what led to
> https://patchwork.freedesktop.org/series/113851/
>
> Please wait for her comments / R-b .
Yes. My plan is to think about cherry-picking hw-catalog entries from
that patchset, which hopefully are good on their own.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 01/10] dt-bindings: display/msm: dsi-controller-main: Add SM6350
2023-02-11 12:26 ` [PATCH 01/10] dt-bindings: display/msm: dsi-controller-main: Add SM6350 Konrad Dybcio
@ 2023-02-14 23:57 ` Rob Herring
0 siblings, 0 replies; 36+ messages in thread
From: Rob Herring @ 2023-02-14 23:57 UTC (permalink / raw)
To: Konrad Dybcio
Cc: andersson, Dmitry Baryshkov, Rob Clark, Sean Paul,
krzysztof.kozlowski, freedreno, Daniel Vetter, David Airlie,
marijn.suijten, Abhinav Kumar, linux-arm-msm, Rob Herring,
devicetree, agross, linux-kernel, dri-devel, Krzysztof Kozlowski,
Krishna Manikandan
On Sat, 11 Feb 2023 13:26:47 +0100, Konrad Dybcio wrote:
> Add the DSI host found on SM6350.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> .../devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 02/10] dt-bindings: display/msm: dsi-controller-main: Add SM6375
2023-02-11 12:26 ` [PATCH 02/10] dt-bindings: display/msm: dsi-controller-main: Add SM6375 Konrad Dybcio
@ 2023-02-14 23:57 ` Rob Herring
0 siblings, 0 replies; 36+ messages in thread
From: Rob Herring @ 2023-02-14 23:57 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Daniel Vetter, dri-devel, agross, Sean Paul, Rob Clark,
Abhinav Kumar, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, linux-kernel, David Airlie, marijn.suijten,
andersson, devicetree, Dmitry Baryshkov, linux-arm-msm,
freedreno, krzysztof.kozlowski
On Sat, 11 Feb 2023 13:26:48 +0100, Konrad Dybcio wrote:
> Add the DSI host found on SM6375.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> .../devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 36+ messages in thread
end of thread, other threads:[~2023-02-14 23:58 UTC | newest]
Thread overview: 36+ messages (download: mbox.gz / follow: Atom feed)
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2023-02-11 12:26 ` [PATCH 01/10] dt-bindings: display/msm: dsi-controller-main: Add SM6350 Konrad Dybcio
2023-02-14 23:57 ` Rob Herring
2023-02-11 12:26 ` [PATCH 02/10] dt-bindings: display/msm: dsi-controller-main: Add SM6375 Konrad Dybcio
2023-02-14 23:57 ` Rob Herring
2023-02-11 12:26 ` [PATCH 03/10] dt-bindings: display/msm: Add SM6350 DPU & MDSS Konrad Dybcio
2023-02-11 16:33 ` Dmitry Baryshkov
2023-02-13 15:09 ` Rob Herring
2023-02-11 12:26 ` [PATCH 04/10] dt-bindings: display/msm: Add SM6375 " Konrad Dybcio
2023-02-13 15:09 ` Rob Herring
2023-02-11 12:26 ` [PATCH 05/10] drm/msm/dpu: Allow variable SSPP/INTF_BLK size Konrad Dybcio
2023-02-11 17:00 ` Dmitry Baryshkov
2023-02-13 9:41 ` Konrad Dybcio
2023-02-13 11:12 ` Marijn Suijten
2023-02-13 11:38 ` Dmitry Baryshkov
2023-02-13 14:31 ` Marijn Suijten
2023-02-13 14:40 ` Dmitry Baryshkov
2023-02-13 15:02 ` Marijn Suijten
2023-02-13 15:05 ` Dmitry Baryshkov
2023-02-11 12:26 ` [PATCH 06/10] drm/msm/dpu: Add SM6350 support Konrad Dybcio
2023-02-11 16:32 ` Dmitry Baryshkov
2023-02-13 11:15 ` Konrad Dybcio
2023-02-13 11:30 ` Marijn Suijten
2023-02-13 11:35 ` Dmitry Baryshkov
2023-02-13 14:28 ` Marijn Suijten
2023-02-13 14:58 ` Dmitry Baryshkov
2023-02-13 15:13 ` Dmitry Baryshkov
2023-02-13 15:14 ` Marijn Suijten
2023-02-13 16:25 ` Dmitry Baryshkov
2023-02-13 19:14 ` [Freedreno] " Abhinav Kumar
2023-02-13 20:24 ` Dmitry Baryshkov
2023-02-11 12:26 ` [PATCH 07/10] drm/msm/dpu: Add SM6375 support Konrad Dybcio
2023-02-11 16:47 ` Dmitry Baryshkov
2023-02-13 11:16 ` Konrad Dybcio
2023-02-11 12:26 ` [PATCH 08/10] iommu/arm-smmu-qcom: Add SM6375 DPU compatible Konrad Dybcio
2023-02-11 12:26 ` [PATCH 09/10] iommu/arm-smmu-qcom: Add SM6350 " Konrad Dybcio
2023-02-11 12:26 ` [PATCH 10/10] iommu/arm-smmu-qcom: Sort the compatible list alphabetically Konrad Dybcio
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