* [PATCH 01/14] ARM: davinci: remove unused board support
2022-10-19 15:29 [PATCH 00/14] ARM: remove unused davinci board & drivers Arnd Bergmann
@ 2022-10-19 15:29 ` Arnd Bergmann
2022-10-20 11:27 ` Bartosz Golaszewski
2022-10-19 15:29 ` [PATCH 02/14] ARM: davinci: drop DAVINCI_DMxxx references Arnd Bergmann
` (15 subsequent siblings)
16 siblings, 1 reply; 48+ messages in thread
From: Arnd Bergmann @ 2022-10-19 15:29 UTC (permalink / raw)
To: Sekhar Nori, Bartosz Golaszewski, linux-arm-kernel
Cc: linux-kernel, Kevin Hilman, Arnd Bergmann
From: Arnd Bergmann <arnd@arndb.de>
All Kconfig entries marked as "depends on UNUSED_BOARD_FILES"
and their direct dependencies are removed here as planned.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
arch/arm/Kconfig.debug | 16 +-
arch/arm/mach-davinci/Kconfig | 130 +-
arch/arm/mach-davinci/Makefile | 9 -
arch/arm/mach-davinci/board-da830-evm.c | 690 ---------
arch/arm/mach-davinci/board-da850-evm.c | 1550 -------------------
arch/arm/mach-davinci/board-dm355-evm.c | 444 ------
arch/arm/mach-davinci/board-dm355-leopard.c | 278 ----
arch/arm/mach-davinci/board-dm365-evm.c | 855 ----------
arch/arm/mach-davinci/board-mityomapl138.c | 638 --------
arch/arm/mach-davinci/board-omapl138-hawk.c | 451 ------
arch/arm/mach-davinci/devices.c | 303 ----
arch/arm/mach-davinci/dm355.c | 832 ----------
arch/arm/mach-davinci/dm365.c | 1094 -------------
13 files changed, 5 insertions(+), 7285 deletions(-)
delete mode 100644 arch/arm/mach-davinci/board-da830-evm.c
delete mode 100644 arch/arm/mach-davinci/board-da850-evm.c
delete mode 100644 arch/arm/mach-davinci/board-dm355-evm.c
delete mode 100644 arch/arm/mach-davinci/board-dm355-leopard.c
delete mode 100644 arch/arm/mach-davinci/board-dm365-evm.c
delete mode 100644 arch/arm/mach-davinci/board-mityomapl138.c
delete mode 100644 arch/arm/mach-davinci/board-omapl138-hawk.c
delete mode 100644 arch/arm/mach-davinci/devices.c
delete mode 100644 arch/arm/mach-davinci/dm355.c
delete mode 100644 arch/arm/mach-davinci/dm365.c
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index c03fd448c59e..20312792340d 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -323,14 +323,6 @@ choice
Say Y here if you want the debug print routines to direct
their output to UART2 serial port on DaVinci DA8XX devices.
- config DEBUG_DAVINCI_DMx_UART0
- bool "Kernel low-level debugging on DaVinci DMx using UART0"
- depends on ARCH_DAVINCI_DMx
- select DEBUG_UART_8250
- help
- Say Y here if you want the debug print routines to direct
- their output to UART0 serial port on DaVinci DMx devices.
-
config DEBUG_DC21285_PORT
bool "Kernel low-level debugging messages via footbridge serial port"
depends on FOOTBRIDGE
@@ -1590,7 +1582,6 @@ config DEBUG_UART_8250
config DEBUG_UART_PHYS
hex "Physical base address of debug UART"
- default 0x01c20000 if DEBUG_DAVINCI_DMx_UART0
default 0x01c28000 if DEBUG_SUNXI_UART0
default 0x01c28400 if DEBUG_SUNXI_UART1
default 0x01d0c000 if DEBUG_DAVINCI_DA8XX_UART1
@@ -1810,7 +1801,6 @@ config DEBUG_UART_VIRT
default 0xfec03000 if DEBUG_SOCFPGA_CYCLONE5_UART1
default 0xfec12000 if DEBUG_MVEBU_UART0 || DEBUG_MVEBU_UART0_ALTERNATE
default 0xfec12100 if DEBUG_MVEBU_UART1_ALTERNATE
- default 0xfec20000 if DEBUG_DAVINCI_DMx_UART0
default 0xfec90000 if DEBUG_RK32_UART2
default 0xfed0c000 if DEBUG_DAVINCI_DA8XX_UART1
default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_SD5203_UART
@@ -1854,9 +1844,9 @@ config DEBUG_UART_8250_WORD
default y if DEBUG_SOCFPGA_UART0 || DEBUG_SOCFPGA_ARRIA10_UART1 || \
DEBUG_SOCFPGA_CYCLONE5_UART1 || DEBUG_KEYSTONE_UART0 || \
DEBUG_KEYSTONE_UART1 || DEBUG_ALPINE_UART0 || \
- DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \
- DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_BCM_IPROC_UART3 || \
- DEBUG_BCM_KONA_UART || DEBUG_RK32_UART2
+ DEBUG_DAVINCI_DA8XX_UART1 || DEBUG_DAVINCI_DA8XX_UART2 || \
+ DEBUG_BCM_IPROC_UART3 || DEBUG_BCM_KONA_UART || \
+ DEBUG_RK32_UART2
config DEBUG_UART_8250_PALMCHIP
bool "8250 UART is Palmchip BK-310x"
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index c8cbd9a30791..588213583051 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -14,20 +14,11 @@ menuconfig ARCH_DAVINCI
if ARCH_DAVINCI
-config ARCH_DAVINCI_DMx
- bool
-
comment "DaVinci Core Type"
-config ARCH_DAVINCI_DM355
- bool "DaVinci 355 based system"
- depends on ATAGS && UNUSED_BOARD_FILES
- select DAVINCI_AINTC
- select ARCH_DAVINCI_DMx
-
config ARCH_DAVINCI_DA830
bool "DA830/OMAP-L137/AM17x based system"
- depends on !ARCH_DAVINCI_DMx || (AUTO_ZRELADDR && ARM_PATCH_PHYS_VIRT)
+ depends on AUTO_ZRELADDR && ARM_PATCH_PHYS_VIRT
depends on ATAGS
select ARCH_DAVINCI_DA8XX
# needed on silicon revs 1.0, 1.1:
@@ -36,7 +27,7 @@ config ARCH_DAVINCI_DA830
config ARCH_DAVINCI_DA850
bool "DA850/OMAP-L138/AM18x based system"
- depends on !ARCH_DAVINCI_DMx || (AUTO_ZRELADDR && ARM_PATCH_PHYS_VIRT)
+ depends on AUTO_ZRELADDR && ARM_PATCH_PHYS_VIRT
depends on ATAGS
select ARCH_DAVINCI_DA8XX
select DAVINCI_CP_INTC
@@ -44,12 +35,6 @@ config ARCH_DAVINCI_DA850
config ARCH_DAVINCI_DA8XX
bool
-config ARCH_DAVINCI_DM365
- bool "DaVinci 365 based system"
- depends on ATAGS && UNUSED_BOARD_FILES
- select DAVINCI_AINTC
- select ARCH_DAVINCI_DMx
-
comment "DaVinci Board Type"
config MACH_DA8XX_DT
@@ -61,117 +46,6 @@ config MACH_DA8XX_DT
Say y here to include support for TI DaVinci DA850 based using
Flattened Device Tree. More information at Documentation/devicetree
-config MACH_DAVINCI_DM355_EVM
- bool "TI DM355 EVM"
- default ARCH_DAVINCI_DM355
- depends on ARCH_DAVINCI_DM355
- help
- Configure this option to specify the whether the board used
- for development is a DM355 EVM
-
-config MACH_DM355_LEOPARD
- bool "DM355 Leopard board"
- depends on ARCH_DAVINCI_DM355
- help
- Configure this option to specify the whether the board used
- for development is a DM355 Leopard board.
-
-config MACH_DAVINCI_DM365_EVM
- bool "TI DM365 EVM"
- default ARCH_DAVINCI_DM365
- depends on ARCH_DAVINCI_DM365
- help
- Configure this option to specify whether the board used
- for development is a DM365 EVM
-
-config MACH_DAVINCI_DA830_EVM
- bool "TI DA830/OMAP-L137/AM17x Reference Platform"
- default ARCH_DAVINCI_DA830
- depends on ATAGS && UNUSED_BOARD_FILES
- depends on ARCH_DAVINCI_DA830
- select GPIO_PCF857X if I2C
- help
- Say Y here to select the TI DA830/OMAP-L137/AM17x Evaluation Module.
-
-choice
- prompt "Select DA830/OMAP-L137/AM17x UI board peripheral"
- depends on MACH_DAVINCI_DA830_EVM
- help
- The presence of UI card on the DA830/OMAP-L137/AM17x EVM is
- detected automatically based on successful probe of the I2C
- based GPIO expander on that board. This option selected in this
- menu has an effect only in case of a successful UI card detection.
-
-config DA830_UI_LCD
- bool "LCD"
- help
- Say Y here to use the LCD as a framebuffer or simple character
- display.
-
-config DA830_UI_NAND
- bool "NAND flash"
- help
- Say Y here to use the NAND flash. Do not forget to setup
- the switch correctly.
-endchoice
-
-config MACH_DAVINCI_DA850_EVM
- bool "TI DA850/OMAP-L138/AM18x Reference Platform"
- depends on ATAGS && UNUSED_BOARD_FILES
- default ARCH_DAVINCI_DA850
- depends on ARCH_DAVINCI_DA850
- help
- Say Y here to select the TI DA850/OMAP-L138/AM18x Evaluation Module.
-
-choice
- prompt "Select peripherals connected to expander on UI board"
- depends on MACH_DAVINCI_DA850_EVM
- help
- The presence of User Interface (UI) card on the DA850/OMAP-L138/AM18x
- EVM is detected automatically based on successful probe of the I2C
- based GPIO expander on that card. This option selected in this
- menu has an effect only in case of a successful UI card detection.
-
-config DA850_UI_NONE
- bool "No peripheral is enabled"
- help
- Say Y if you do not want to enable any of the peripherals connected
- to TCA6416 expander on DA850/OMAP-L138/AM18x EVM UI card
-
-config DA850_UI_RMII
- bool "RMII Ethernet PHY"
- help
- Say Y if you want to use the RMII PHY on the DA850/OMAP-L138/AM18x
- EVM. This PHY is found on the UI daughter card that is supplied with
- the EVM.
- NOTE: Please take care while choosing this option, MII PHY will
- not be functional if RMII mode is selected.
-
-config DA850_UI_SD_VIDEO_PORT
- bool "Video Port Interface"
- help
- Say Y if you want to use Video Port Interface (VPIF) on the
- DA850/OMAP-L138 EVM. The Video decoders/encoders are found on the
- UI daughter card that is supplied with the EVM.
-
-endchoice
-
-config MACH_MITYOMAPL138
- bool "Critical Link MityDSP-L138/MityARM-1808 SoM"
- depends on ARCH_DAVINCI_DA850
- depends on ATAGS && UNUSED_BOARD_FILES
- help
- Say Y here to select the Critical Link MityDSP-L138/MityARM-1808
- System on Module. Information on this SoM may be found at
- https://www.mitydsp.com
-
-config MACH_OMAPL138_HAWKBOARD
- bool "TI AM1808 / OMAPL-138 Hawkboard platform"
- depends on ARCH_DAVINCI_DA850
- depends on ATAGS && UNUSED_BOARD_FILES
- help
- Say Y here to select the TI AM1808 / OMAPL-138 Hawkboard platform .
-
config DAVINCI_MUX
bool "DAVINCI multiplexing support"
depends on ARCH_DAVINCI
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 3f4894aa7528..5b15a3bbf909 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -10,20 +10,11 @@ obj-y := serial.o usb.o common.o sram.o
obj-$(CONFIG_DAVINCI_MUX) += mux.o
# Chip specific
-obj-$(CONFIG_ARCH_DAVINCI_DM355) += dm355.o devices.o
-obj-$(CONFIG_ARCH_DAVINCI_DM365) += dm365.o devices.o
obj-$(CONFIG_ARCH_DAVINCI_DA830) += da830.o devices-da8xx.o usb-da8xx.o
obj-$(CONFIG_ARCH_DAVINCI_DA850) += da850.o devices-da8xx.o usb-da8xx.o
# Board specific
obj-$(CONFIG_MACH_DA8XX_DT) += da8xx-dt.o pdata-quirks.o
-obj-$(CONFIG_MACH_DAVINCI_DM355_EVM) += board-dm355-evm.o
-obj-$(CONFIG_MACH_DM355_LEOPARD) += board-dm355-leopard.o
-obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o
-obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o
-obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o
-obj-$(CONFIG_MACH_MITYOMAPL138) += board-mityomapl138.o
-obj-$(CONFIG_MACH_OMAPL138_HAWKBOARD) += board-omapl138-hawk.o
# Power Management
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
deleted file mode 100644
index 6299e5c8f4ea..000000000000
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ /dev/null
@@ -1,690 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * TI DA830/OMAP L137 EVM board
- *
- * Author: Mark A. Greer <mgreer@mvista.com>
- * Derived from: arch/arm/mach-davinci/board-dm644x-evm.c
- *
- * 2007, 2009 (c) MontaVista Software, Inc.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/console.h>
-#include <linux/interrupt.h>
-#include <linux/gpio.h>
-#include <linux/gpio/machine.h>
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-#include <linux/platform_data/pcf857x.h>
-#include <linux/property.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/platform_data/gpio-davinci.h>
-#include <linux/platform_data/mtd-davinci.h>
-#include <linux/platform_data/mtd-davinci-aemif.h>
-#include <linux/platform_data/spi-davinci.h>
-#include <linux/platform_data/usb-davinci.h>
-#include <linux/platform_data/ti-aemif.h>
-#include <linux/regulator/fixed.h>
-#include <linux/regulator/machine.h>
-#include <linux/nvmem-provider.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include "common.h"
-#include "mux.h"
-#include "da8xx.h"
-#include "irqs.h"
-
-#define DA830_EVM_PHY_ID ""
-/*
- * USB1 VBUS is controlled by GPIO1[15], over-current is reported on GPIO2[4].
- */
-#define ON_BD_USB_DRV GPIO_TO_PIN(1, 15)
-#define ON_BD_USB_OVC GPIO_TO_PIN(2, 4)
-
-static const short da830_evm_usb11_pins[] = {
- DA830_GPIO1_15, DA830_GPIO2_4,
- -1
-};
-
-static struct regulator_consumer_supply da830_evm_usb_supplies[] = {
- REGULATOR_SUPPLY("vbus", NULL),
-};
-
-static struct regulator_init_data da830_evm_usb_vbus_data = {
- .consumer_supplies = da830_evm_usb_supplies,
- .num_consumer_supplies = ARRAY_SIZE(da830_evm_usb_supplies),
- .constraints = {
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- },
-};
-
-static struct fixed_voltage_config da830_evm_usb_vbus = {
- .supply_name = "vbus",
- .microvolts = 33000000,
- .init_data = &da830_evm_usb_vbus_data,
-};
-
-static struct platform_device da830_evm_usb_vbus_device = {
- .name = "reg-fixed-voltage",
- .id = 0,
- .dev = {
- .platform_data = &da830_evm_usb_vbus,
- },
-};
-
-static struct gpiod_lookup_table da830_evm_usb_oc_gpio_lookup = {
- .dev_id = "ohci-da8xx",
- .table = {
- GPIO_LOOKUP("davinci_gpio", ON_BD_USB_OVC, "oc", 0),
- { }
- },
-};
-
-static struct gpiod_lookup_table da830_evm_usb_vbus_gpio_lookup = {
- .dev_id = "reg-fixed-voltage.0",
- .table = {
- GPIO_LOOKUP("davinci_gpio", ON_BD_USB_DRV, NULL, 0),
- { }
- },
-};
-
-static struct gpiod_lookup_table *da830_evm_usb_gpio_lookups[] = {
- &da830_evm_usb_oc_gpio_lookup,
- &da830_evm_usb_vbus_gpio_lookup,
-};
-
-static struct da8xx_ohci_root_hub da830_evm_usb11_pdata = {
- /* TPS2065 switch @ 5V */
- .potpgt = (3 + 1) / 2, /* 3 ms max */
-};
-
-static __init void da830_evm_usb_init(void)
-{
- int ret;
-
- ret = da8xx_register_usb_phy_clocks();
- if (ret)
- pr_warn("%s: USB PHY CLK registration failed: %d\n",
- __func__, ret);
-
- gpiod_add_lookup_tables(da830_evm_usb_gpio_lookups,
- ARRAY_SIZE(da830_evm_usb_gpio_lookups));
-
- ret = da8xx_register_usb_phy();
- if (ret)
- pr_warn("%s: USB PHY registration failed: %d\n",
- __func__, ret);
-
- ret = davinci_cfg_reg(DA830_USB0_DRVVBUS);
- if (ret)
- pr_warn("%s: USB 2.0 PinMux setup failed: %d\n", __func__, ret);
- else {
- /*
- * TPS2065 switch @ 5V supplies 1 A (sustains 1.5 A),
- * with the power on to power good time of 3 ms.
- */
- ret = da8xx_register_usb20(1000, 3);
- if (ret)
- pr_warn("%s: USB 2.0 registration failed: %d\n",
- __func__, ret);
- }
-
- ret = davinci_cfg_reg_list(da830_evm_usb11_pins);
- if (ret) {
- pr_warn("%s: USB 1.1 PinMux setup failed: %d\n", __func__, ret);
- return;
- }
-
- ret = platform_device_register(&da830_evm_usb_vbus_device);
- if (ret) {
- pr_warn("%s: Unable to register the vbus supply\n", __func__);
- return;
- }
-
- ret = da8xx_register_usb11(&da830_evm_usb11_pdata);
- if (ret)
- pr_warn("%s: USB 1.1 registration failed: %d\n", __func__, ret);
-}
-
-static const short da830_evm_mcasp1_pins[] = {
- DA830_AHCLKX1, DA830_ACLKX1, DA830_AFSX1, DA830_AHCLKR1, DA830_AFSR1,
- DA830_AMUTE1, DA830_AXR1_0, DA830_AXR1_1, DA830_AXR1_2, DA830_AXR1_5,
- DA830_ACLKR1, DA830_AXR1_6, DA830_AXR1_7, DA830_AXR1_8, DA830_AXR1_10,
- DA830_AXR1_11,
- -1
-};
-
-static u8 da830_iis_serializer_direction[] = {
- RX_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
- INACTIVE_MODE, TX_MODE, INACTIVE_MODE, INACTIVE_MODE,
- INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
-};
-
-static struct snd_platform_data da830_evm_snd_data = {
- .tx_dma_offset = 0x2000,
- .rx_dma_offset = 0x2000,
- .op_mode = DAVINCI_MCASP_IIS_MODE,
- .num_serializer = ARRAY_SIZE(da830_iis_serializer_direction),
- .tdm_slots = 2,
- .serial_dir = da830_iis_serializer_direction,
- .asp_chan_q = EVENTQ_0,
- .version = MCASP_VERSION_2,
- .txnumevt = 1,
- .rxnumevt = 1,
-};
-
-/*
- * GPIO2[1] is used as MMC_SD_WP and GPIO2[2] as MMC_SD_INS.
- */
-static const short da830_evm_mmc_sd_pins[] = {
- DA830_MMCSD_DAT_0, DA830_MMCSD_DAT_1, DA830_MMCSD_DAT_2,
- DA830_MMCSD_DAT_3, DA830_MMCSD_DAT_4, DA830_MMCSD_DAT_5,
- DA830_MMCSD_DAT_6, DA830_MMCSD_DAT_7, DA830_MMCSD_CLK,
- DA830_MMCSD_CMD, DA830_GPIO2_1, DA830_GPIO2_2,
- -1
-};
-
-#define DA830_MMCSD_WP_PIN GPIO_TO_PIN(2, 1)
-#define DA830_MMCSD_CD_PIN GPIO_TO_PIN(2, 2)
-
-static struct gpiod_lookup_table mmc_gpios_table = {
- .dev_id = "da830-mmc.0",
- .table = {
- /* gpio chip 1 contains gpio range 32-63 */
- GPIO_LOOKUP("davinci_gpio", DA830_MMCSD_CD_PIN, "cd",
- GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("davinci_gpio", DA830_MMCSD_WP_PIN, "wp",
- GPIO_ACTIVE_LOW),
- { }
- },
-};
-
-static struct davinci_mmc_config da830_evm_mmc_config = {
- .wires = 8,
- .max_freq = 50000000,
- .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
-};
-
-static inline void da830_evm_init_mmc(void)
-{
- int ret;
-
- ret = davinci_cfg_reg_list(da830_evm_mmc_sd_pins);
- if (ret) {
- pr_warn("%s: mmc/sd mux setup failed: %d\n", __func__, ret);
- return;
- }
-
- gpiod_add_lookup_table(&mmc_gpios_table);
-
- ret = da8xx_register_mmcsd0(&da830_evm_mmc_config);
- if (ret) {
- pr_warn("%s: mmc/sd registration failed: %d\n", __func__, ret);
- gpiod_remove_lookup_table(&mmc_gpios_table);
- }
-}
-
-#define HAS_MMC IS_ENABLED(CONFIG_MMC_DAVINCI)
-
-#ifdef CONFIG_DA830_UI_NAND
-static struct mtd_partition da830_evm_nand_partitions[] = {
- /* bootloader (U-Boot, etc) in first sector */
- [0] = {
- .name = "bootloader",
- .offset = 0,
- .size = SZ_128K,
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- },
- /* bootloader params in the next sector */
- [1] = {
- .name = "params",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_128K,
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- },
- /* kernel */
- [2] = {
- .name = "kernel",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_2M,
- .mask_flags = 0,
- },
- /* file system */
- [3] = {
- .name = "filesystem",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- .mask_flags = 0,
- }
-};
-
-/* flash bbt descriptors */
-static uint8_t da830_evm_nand_bbt_pattern[] = { 'B', 'b', 't', '0' };
-static uint8_t da830_evm_nand_mirror_pattern[] = { '1', 't', 'b', 'B' };
-
-static struct nand_bbt_descr da830_evm_nand_bbt_main_descr = {
- .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE |
- NAND_BBT_WRITE | NAND_BBT_2BIT |
- NAND_BBT_VERSION | NAND_BBT_PERCHIP,
- .offs = 2,
- .len = 4,
- .veroffs = 16,
- .maxblocks = 4,
- .pattern = da830_evm_nand_bbt_pattern
-};
-
-static struct nand_bbt_descr da830_evm_nand_bbt_mirror_descr = {
- .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE |
- NAND_BBT_WRITE | NAND_BBT_2BIT |
- NAND_BBT_VERSION | NAND_BBT_PERCHIP,
- .offs = 2,
- .len = 4,
- .veroffs = 16,
- .maxblocks = 4,
- .pattern = da830_evm_nand_mirror_pattern
-};
-
-static struct davinci_aemif_timing da830_evm_nandflash_timing = {
- .wsetup = 24,
- .wstrobe = 21,
- .whold = 14,
- .rsetup = 19,
- .rstrobe = 50,
- .rhold = 0,
- .ta = 20,
-};
-
-static struct davinci_nand_pdata da830_evm_nand_pdata = {
- .core_chipsel = 1,
- .parts = da830_evm_nand_partitions,
- .nr_parts = ARRAY_SIZE(da830_evm_nand_partitions),
- .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
- .ecc_bits = 4,
- .bbt_options = NAND_BBT_USE_FLASH,
- .bbt_td = &da830_evm_nand_bbt_main_descr,
- .bbt_md = &da830_evm_nand_bbt_mirror_descr,
- .timing = &da830_evm_nandflash_timing,
-};
-
-static struct resource da830_evm_nand_resources[] = {
- [0] = { /* First memory resource is NAND I/O window */
- .start = DA8XX_AEMIF_CS3_BASE,
- .end = DA8XX_AEMIF_CS3_BASE + PAGE_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* Second memory resource is AEMIF control registers */
- .start = DA8XX_AEMIF_CTL_BASE,
- .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device da830_evm_aemif_devices[] = {
- {
- .name = "davinci_nand",
- .id = 1,
- .dev = {
- .platform_data = &da830_evm_nand_pdata,
- },
- .num_resources = ARRAY_SIZE(da830_evm_nand_resources),
- .resource = da830_evm_nand_resources,
- },
-};
-
-static struct resource da830_evm_aemif_resource[] = {
- {
- .start = DA8XX_AEMIF_CTL_BASE,
- .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct aemif_abus_data da830_evm_aemif_abus_data[] = {
- {
- .cs = 3,
- },
-};
-
-static struct aemif_platform_data da830_evm_aemif_pdata = {
- .abus_data = da830_evm_aemif_abus_data,
- .num_abus_data = ARRAY_SIZE(da830_evm_aemif_abus_data),
- .sub_devices = da830_evm_aemif_devices,
- .num_sub_devices = ARRAY_SIZE(da830_evm_aemif_devices),
- .cs_offset = 2,
-};
-
-static struct platform_device da830_evm_aemif_device = {
- .name = "ti-aemif",
- .id = -1,
- .dev = {
- .platform_data = &da830_evm_aemif_pdata,
- },
- .resource = da830_evm_aemif_resource,
- .num_resources = ARRAY_SIZE(da830_evm_aemif_resource),
-};
-
-/*
- * UI board NAND/NOR flashes only use 8-bit data bus.
- */
-static const short da830_evm_emif25_pins[] = {
- DA830_EMA_D_0, DA830_EMA_D_1, DA830_EMA_D_2, DA830_EMA_D_3,
- DA830_EMA_D_4, DA830_EMA_D_5, DA830_EMA_D_6, DA830_EMA_D_7,
- DA830_EMA_A_0, DA830_EMA_A_1, DA830_EMA_A_2, DA830_EMA_A_3,
- DA830_EMA_A_4, DA830_EMA_A_5, DA830_EMA_A_6, DA830_EMA_A_7,
- DA830_EMA_A_8, DA830_EMA_A_9, DA830_EMA_A_10, DA830_EMA_A_11,
- DA830_EMA_A_12, DA830_EMA_BA_0, DA830_EMA_BA_1, DA830_NEMA_WE,
- DA830_NEMA_CS_2, DA830_NEMA_CS_3, DA830_NEMA_OE, DA830_EMA_WAIT_0,
- -1
-};
-
-static inline void da830_evm_init_nand(int mux_mode)
-{
- int ret;
-
- if (HAS_MMC) {
- pr_warn("WARNING: both MMC/SD and NAND are enabled, but they share AEMIF pins\n"
- "\tDisable MMC/SD for NAND support\n");
- return;
- }
-
- ret = davinci_cfg_reg_list(da830_evm_emif25_pins);
- if (ret)
- pr_warn("%s: emif25 mux setup failed: %d\n", __func__, ret);
-
- ret = platform_device_register(&da830_evm_aemif_device);
- if (ret)
- pr_warn("%s: AEMIF device not registered\n", __func__);
-
- gpio_direction_output(mux_mode, 1);
-}
-#else
-static inline void da830_evm_init_nand(int mux_mode) { }
-#endif
-
-#ifdef CONFIG_DA830_UI_LCD
-static inline void da830_evm_init_lcdc(int mux_mode)
-{
- int ret;
-
- ret = davinci_cfg_reg_list(da830_lcdcntl_pins);
- if (ret)
- pr_warn("%s: lcdcntl mux setup failed: %d\n", __func__, ret);
-
- ret = da8xx_register_lcdc(&sharp_lcd035q3dg01_pdata);
- if (ret)
- pr_warn("%s: lcd setup failed: %d\n", __func__, ret);
-
- gpio_direction_output(mux_mode, 0);
-}
-#else
-static inline void da830_evm_init_lcdc(int mux_mode) { }
-#endif
-
-static struct nvmem_cell_info da830_evm_nvmem_cells[] = {
- {
- .name = "macaddr",
- .offset = 0x7f00,
- .bytes = ETH_ALEN,
- }
-};
-
-static struct nvmem_cell_table da830_evm_nvmem_cell_table = {
- .nvmem_name = "1-00500",
- .cells = da830_evm_nvmem_cells,
- .ncells = ARRAY_SIZE(da830_evm_nvmem_cells),
-};
-
-static struct nvmem_cell_lookup da830_evm_nvmem_cell_lookup = {
- .nvmem_name = "1-00500",
- .cell_name = "macaddr",
- .dev_id = "davinci_emac.1",
- .con_id = "mac-address",
-};
-
-static const struct property_entry da830_evm_i2c_eeprom_properties[] = {
- PROPERTY_ENTRY_U32("pagesize", 64),
- { }
-};
-
-static const struct software_node da830_evm_i2c_eeprom_node = {
- .properties = da830_evm_i2c_eeprom_properties,
-};
-
-static int __init da830_evm_ui_expander_setup(struct i2c_client *client,
- int gpio, unsigned ngpio, void *context)
-{
- gpio_request(gpio + 6, "UI MUX_MODE");
-
- /* Drive mux mode low to match the default without UI card */
- gpio_direction_output(gpio + 6, 0);
-
- da830_evm_init_lcdc(gpio + 6);
-
- da830_evm_init_nand(gpio + 6);
-
- return 0;
-}
-
-static void da830_evm_ui_expander_teardown(struct i2c_client *client, int gpio,
- unsigned ngpio, void *context)
-{
- gpio_free(gpio + 6);
-}
-
-static struct pcf857x_platform_data __initdata da830_evm_ui_expander_info = {
- .gpio_base = DAVINCI_N_GPIO,
- .setup = da830_evm_ui_expander_setup,
- .teardown = da830_evm_ui_expander_teardown,
-};
-
-static struct i2c_board_info __initdata da830_evm_i2c_devices[] = {
- {
- I2C_BOARD_INFO("24c256", 0x50),
- .swnode = &da830_evm_i2c_eeprom_node,
- },
- {
- I2C_BOARD_INFO("tlv320aic3x", 0x18),
- },
- {
- I2C_BOARD_INFO("pcf8574", 0x3f),
- .platform_data = &da830_evm_ui_expander_info,
- },
-};
-
-static struct davinci_i2c_platform_data da830_evm_i2c_0_pdata = {
- .bus_freq = 100, /* kHz */
- .bus_delay = 0, /* usec */
-};
-
-/*
- * The following EDMA channels/slots are not being used by drivers (for
- * example: Timer, GPIO, UART events etc) on da830/omap-l137 EVM, hence
- * they are being reserved for codecs on the DSP side.
- */
-static const s16 da830_dma_rsv_chans[][2] = {
- /* (offset, number) */
- { 8, 2},
- {12, 2},
- {24, 4},
- {30, 2},
- {-1, -1}
-};
-
-static const s16 da830_dma_rsv_slots[][2] = {
- /* (offset, number) */
- { 8, 2},
- {12, 2},
- {24, 4},
- {30, 26},
- {-1, -1}
-};
-
-static struct edma_rsv_info da830_edma_rsv[] = {
- {
- .rsv_chans = da830_dma_rsv_chans,
- .rsv_slots = da830_dma_rsv_slots,
- },
-};
-
-static struct mtd_partition da830evm_spiflash_part[] = {
- [0] = {
- .name = "DSP-UBL",
- .offset = 0,
- .size = SZ_8K,
- .mask_flags = MTD_WRITEABLE,
- },
- [1] = {
- .name = "ARM-UBL",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_16K + SZ_8K,
- .mask_flags = MTD_WRITEABLE,
- },
- [2] = {
- .name = "U-Boot",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_256K - SZ_32K,
- .mask_flags = MTD_WRITEABLE,
- },
- [3] = {
- .name = "U-Boot-Environment",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_16K,
- .mask_flags = 0,
- },
- [4] = {
- .name = "Kernel",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- .mask_flags = 0,
- },
-};
-
-static struct flash_platform_data da830evm_spiflash_data = {
- .name = "m25p80",
- .parts = da830evm_spiflash_part,
- .nr_parts = ARRAY_SIZE(da830evm_spiflash_part),
- .type = "w25x32",
-};
-
-static struct davinci_spi_config da830evm_spiflash_cfg = {
- .io_type = SPI_IO_TYPE_DMA,
- .c2tdelay = 8,
- .t2cdelay = 8,
-};
-
-static struct spi_board_info da830evm_spi_info[] = {
- {
- .modalias = "m25p80",
- .platform_data = &da830evm_spiflash_data,
- .controller_data = &da830evm_spiflash_cfg,
- .mode = SPI_MODE_0,
- .max_speed_hz = 30000000,
- .bus_num = 0,
- .chip_select = 0,
- },
-};
-
-static __init void da830_evm_init(void)
-{
- struct davinci_soc_info *soc_info = &davinci_soc_info;
- int ret;
-
- da830_register_clocks();
-
- ret = da830_register_gpio();
- if (ret)
- pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
-
- ret = da830_register_edma(da830_edma_rsv);
- if (ret)
- pr_warn("%s: edma registration failed: %d\n", __func__, ret);
-
- ret = davinci_cfg_reg_list(da830_i2c0_pins);
- if (ret)
- pr_warn("%s: i2c0 mux setup failed: %d\n", __func__, ret);
-
- ret = da8xx_register_i2c(0, &da830_evm_i2c_0_pdata);
- if (ret)
- pr_warn("%s: i2c0 registration failed: %d\n", __func__, ret);
-
- da830_evm_usb_init();
-
- soc_info->emac_pdata->rmii_en = 1;
- soc_info->emac_pdata->phy_id = DA830_EVM_PHY_ID;
-
- ret = davinci_cfg_reg_list(da830_cpgmac_pins);
- if (ret)
- pr_warn("%s: cpgmac mux setup failed: %d\n", __func__, ret);
-
- ret = da8xx_register_emac();
- if (ret)
- pr_warn("%s: emac registration failed: %d\n", __func__, ret);
-
- ret = da8xx_register_watchdog();
- if (ret)
- pr_warn("%s: watchdog registration failed: %d\n",
- __func__, ret);
-
- davinci_serial_init(da8xx_serial_device);
-
- nvmem_add_cell_table(&da830_evm_nvmem_cell_table);
- nvmem_add_cell_lookups(&da830_evm_nvmem_cell_lookup, 1);
-
- i2c_register_board_info(1, da830_evm_i2c_devices,
- ARRAY_SIZE(da830_evm_i2c_devices));
-
- ret = davinci_cfg_reg_list(da830_evm_mcasp1_pins);
- if (ret)
- pr_warn("%s: mcasp1 mux setup failed: %d\n", __func__, ret);
-
- da8xx_register_mcasp(1, &da830_evm_snd_data);
-
- da830_evm_init_mmc();
-
- ret = da8xx_register_rtc();
- if (ret)
- pr_warn("%s: rtc setup failed: %d\n", __func__, ret);
-
- ret = spi_register_board_info(da830evm_spi_info,
- ARRAY_SIZE(da830evm_spi_info));
- if (ret)
- pr_warn("%s: spi info registration failed: %d\n",
- __func__, ret);
-
- ret = da8xx_register_spi_bus(0, ARRAY_SIZE(da830evm_spi_info));
- if (ret)
- pr_warn("%s: spi 0 registration failed: %d\n", __func__, ret);
-
- regulator_has_full_constraints();
-}
-
-#ifdef CONFIG_SERIAL_8250_CONSOLE
-static int __init da830_evm_console_init(void)
-{
- if (!machine_is_davinci_da830_evm())
- return 0;
-
- return add_preferred_console("ttyS", 2, "115200");
-}
-console_initcall(da830_evm_console_init);
-#endif
-
-static void __init da830_evm_map_io(void)
-{
- da830_init();
-}
-
-MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137/AM17x EVM")
- .atag_offset = 0x100,
- .map_io = da830_evm_map_io,
- .init_irq = da830_init_irq,
- .init_time = da830_init_time,
- .init_machine = da830_evm_init,
- .init_late = davinci_init_late,
- .dma_zone_size = SZ_128M,
-MACHINE_END
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
deleted file mode 100644
index d752ee2b30ff..000000000000
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ /dev/null
@@ -1,1550 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * TI DA850/OMAP-L138 EVM board
- *
- * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/
- *
- * Derived from: arch/arm/mach-davinci/board-da830-evm.c
- * Original Copyrights follow:
- *
- * 2007, 2009 (c) MontaVista Software, Inc.
- */
-#include <linux/console.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/gpio_keys.h>
-#include <linux/gpio/machine.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/leds.h>
-#include <linux/i2c.h>
-#include <linux/platform_data/pca953x.h>
-#include <linux/input.h>
-#include <linux/input/tps6507x-ts.h>
-#include <linux/mfd/tps6507x.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/partitions.h>
-#include <linux/nvmem-provider.h>
-#include <linux/mtd/physmap.h>
-#include <linux/platform_device.h>
-#include <linux/platform_data/gpio-davinci.h>
-#include <linux/platform_data/mtd-davinci.h>
-#include <linux/platform_data/mtd-davinci-aemif.h>
-#include <linux/platform_data/ti-aemif.h>
-#include <linux/platform_data/spi-davinci.h>
-#include <linux/platform_data/uio_pruss.h>
-#include <linux/property.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/tps6507x.h>
-#include <linux/regulator/fixed.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-
-#include "common.h"
-#include "da8xx.h"
-#include "mux.h"
-#include "irqs.h"
-#include "sram.h"
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/system_info.h>
-
-#include <media/i2c/tvp514x.h>
-#include <media/i2c/adv7343.h>
-
-#define DA850_EVM_PHY_ID "davinci_mdio-0:00"
-#define DA850_LCD_PWR_PIN GPIO_TO_PIN(2, 8)
-#define DA850_LCD_BL_PIN GPIO_TO_PIN(2, 15)
-
-#define DA850_MII_MDIO_CLKEN_PIN GPIO_TO_PIN(2, 6)
-
-static struct mtd_partition da850evm_spiflash_part[] = {
- [0] = {
- .name = "UBL",
- .offset = 0,
- .size = SZ_64K,
- .mask_flags = MTD_WRITEABLE,
- },
- [1] = {
- .name = "U-Boot",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_512K,
- .mask_flags = MTD_WRITEABLE,
- },
- [2] = {
- .name = "U-Boot-Env",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_64K,
- .mask_flags = MTD_WRITEABLE,
- },
- [3] = {
- .name = "Kernel",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_2M + SZ_512K,
- .mask_flags = 0,
- },
- [4] = {
- .name = "Filesystem",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_4M,
- .mask_flags = 0,
- },
- [5] = {
- .name = "MAC-Address",
- .offset = SZ_8M - SZ_64K,
- .size = SZ_64K,
- .mask_flags = MTD_WRITEABLE,
- },
-};
-
-static struct nvmem_cell_info da850evm_nvmem_cells[] = {
- {
- .name = "macaddr",
- .offset = 0x0,
- .bytes = ETH_ALEN,
- }
-};
-
-static struct nvmem_cell_table da850evm_nvmem_cell_table = {
- /*
- * The nvmem name differs from the partition name because of the
- * internal works of the nvmem framework.
- */
- .nvmem_name = "MAC-Address0",
- .cells = da850evm_nvmem_cells,
- .ncells = ARRAY_SIZE(da850evm_nvmem_cells),
-};
-
-static struct nvmem_cell_lookup da850evm_nvmem_cell_lookup = {
- .nvmem_name = "MAC-Address0",
- .cell_name = "macaddr",
- .dev_id = "davinci_emac.1",
- .con_id = "mac-address",
-};
-
-static struct flash_platform_data da850evm_spiflash_data = {
- .name = "m25p80",
- .parts = da850evm_spiflash_part,
- .nr_parts = ARRAY_SIZE(da850evm_spiflash_part),
- .type = "m25p64",
-};
-
-static struct davinci_spi_config da850evm_spiflash_cfg = {
- .io_type = SPI_IO_TYPE_DMA,
- .c2tdelay = 8,
- .t2cdelay = 8,
-};
-
-static struct spi_board_info da850evm_spi_info[] = {
- {
- .modalias = "m25p80",
- .platform_data = &da850evm_spiflash_data,
- .controller_data = &da850evm_spiflash_cfg,
- .mode = SPI_MODE_0,
- .max_speed_hz = 30000000,
- .bus_num = 1,
- .chip_select = 0,
- },
-};
-
-static struct mtd_partition da850_evm_norflash_partition[] = {
- {
- .name = "bootloaders + env",
- .offset = 0,
- .size = SZ_512K,
- .mask_flags = MTD_WRITEABLE,
- },
- {
- .name = "kernel",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_2M,
- .mask_flags = 0,
- },
- {
- .name = "filesystem",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- .mask_flags = 0,
- },
-};
-
-static struct physmap_flash_data da850_evm_norflash_data = {
- .width = 2,
- .parts = da850_evm_norflash_partition,
- .nr_parts = ARRAY_SIZE(da850_evm_norflash_partition),
-};
-
-static struct resource da850_evm_norflash_resource[] = {
- {
- .start = DA8XX_AEMIF_CS2_BASE,
- .end = DA8XX_AEMIF_CS2_BASE + SZ_32M - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-/* DA850/OMAP-L138 EVM includes a 512 MByte large-page NAND flash
- * (128K blocks). It may be used instead of the (default) SPI flash
- * to boot, using TI's tools to install the secondary boot loader
- * (UBL) and U-Boot.
- */
-static struct mtd_partition da850_evm_nandflash_partition[] = {
- {
- .name = "u-boot env",
- .offset = 0,
- .size = SZ_128K,
- .mask_flags = MTD_WRITEABLE,
- },
- {
- .name = "UBL",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_128K,
- .mask_flags = MTD_WRITEABLE,
- },
- {
- .name = "u-boot",
- .offset = MTDPART_OFS_APPEND,
- .size = 4 * SZ_128K,
- .mask_flags = MTD_WRITEABLE,
- },
- {
- .name = "kernel",
- .offset = 0x200000,
- .size = SZ_2M,
- .mask_flags = 0,
- },
- {
- .name = "filesystem",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- .mask_flags = 0,
- },
-};
-
-static struct davinci_aemif_timing da850_evm_nandflash_timing = {
- .wsetup = 24,
- .wstrobe = 21,
- .whold = 14,
- .rsetup = 19,
- .rstrobe = 50,
- .rhold = 0,
- .ta = 20,
-};
-
-static struct davinci_nand_pdata da850_evm_nandflash_data = {
- .core_chipsel = 1,
- .parts = da850_evm_nandflash_partition,
- .nr_parts = ARRAY_SIZE(da850_evm_nandflash_partition),
- .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
- .ecc_bits = 4,
- .bbt_options = NAND_BBT_USE_FLASH,
- .timing = &da850_evm_nandflash_timing,
-};
-
-static struct resource da850_evm_nandflash_resource[] = {
- {
- .start = DA8XX_AEMIF_CS3_BASE,
- .end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DA8XX_AEMIF_CTL_BASE,
- .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct resource da850_evm_aemif_resource[] = {
- {
- .start = DA8XX_AEMIF_CTL_BASE,
- .end = DA8XX_AEMIF_CTL_BASE + SZ_32K,
- .flags = IORESOURCE_MEM,
- }
-};
-
-static struct aemif_abus_data da850_evm_aemif_abus_data[] = {
- {
- .cs = 3,
- }
-};
-
-static struct platform_device da850_evm_aemif_devices[] = {
- {
- .name = "davinci_nand",
- .id = 1,
- .dev = {
- .platform_data = &da850_evm_nandflash_data,
- },
- .num_resources = ARRAY_SIZE(da850_evm_nandflash_resource),
- .resource = da850_evm_nandflash_resource,
- },
- {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &da850_evm_norflash_data,
- },
- .num_resources = 1,
- .resource = da850_evm_norflash_resource,
- }
-};
-
-static struct aemif_platform_data da850_evm_aemif_pdata = {
- .cs_offset = 2,
- .abus_data = da850_evm_aemif_abus_data,
- .num_abus_data = ARRAY_SIZE(da850_evm_aemif_abus_data),
- .sub_devices = da850_evm_aemif_devices,
- .num_sub_devices = ARRAY_SIZE(da850_evm_aemif_devices),
-};
-
-static struct platform_device da850_evm_aemif_device = {
- .name = "ti-aemif",
- .id = -1,
- .dev = {
- .platform_data = &da850_evm_aemif_pdata,
- },
- .resource = da850_evm_aemif_resource,
- .num_resources = ARRAY_SIZE(da850_evm_aemif_resource),
-};
-
-static const short da850_evm_nand_pins[] = {
- DA850_EMA_D_0, DA850_EMA_D_1, DA850_EMA_D_2, DA850_EMA_D_3,
- DA850_EMA_D_4, DA850_EMA_D_5, DA850_EMA_D_6, DA850_EMA_D_7,
- DA850_EMA_A_1, DA850_EMA_A_2, DA850_NEMA_CS_3, DA850_NEMA_CS_4,
- DA850_NEMA_WE, DA850_NEMA_OE,
- -1
-};
-
-static const short da850_evm_nor_pins[] = {
- DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2,
- DA850_NEMA_WE, DA850_NEMA_OE, DA850_EMA_D_0, DA850_EMA_D_1,
- DA850_EMA_D_2, DA850_EMA_D_3, DA850_EMA_D_4, DA850_EMA_D_5,
- DA850_EMA_D_6, DA850_EMA_D_7, DA850_EMA_D_8, DA850_EMA_D_9,
- DA850_EMA_D_10, DA850_EMA_D_11, DA850_EMA_D_12, DA850_EMA_D_13,
- DA850_EMA_D_14, DA850_EMA_D_15, DA850_EMA_A_0, DA850_EMA_A_1,
- DA850_EMA_A_2, DA850_EMA_A_3, DA850_EMA_A_4, DA850_EMA_A_5,
- DA850_EMA_A_6, DA850_EMA_A_7, DA850_EMA_A_8, DA850_EMA_A_9,
- DA850_EMA_A_10, DA850_EMA_A_11, DA850_EMA_A_12, DA850_EMA_A_13,
- DA850_EMA_A_14, DA850_EMA_A_15, DA850_EMA_A_16, DA850_EMA_A_17,
- DA850_EMA_A_18, DA850_EMA_A_19, DA850_EMA_A_20, DA850_EMA_A_21,
- DA850_EMA_A_22, DA850_EMA_A_23,
- -1
-};
-
-#define HAS_MMC IS_ENABLED(CONFIG_MMC_DAVINCI)
-
-static inline void da850_evm_setup_nor_nand(void)
-{
- int ret = 0;
-
- if (!HAS_MMC) {
- ret = davinci_cfg_reg_list(da850_evm_nand_pins);
- if (ret)
- pr_warn("%s: NAND mux setup failed: %d\n",
- __func__, ret);
-
- ret = davinci_cfg_reg_list(da850_evm_nor_pins);
- if (ret)
- pr_warn("%s: NOR mux setup failed: %d\n",
- __func__, ret);
-
- ret = platform_device_register(&da850_evm_aemif_device);
- if (ret)
- pr_warn("%s: registering aemif failed: %d\n",
- __func__, ret);
- }
-}
-
-#ifdef CONFIG_DA850_UI_RMII
-static inline void da850_evm_setup_emac_rmii(int rmii_sel)
-{
- struct davinci_soc_info *soc_info = &davinci_soc_info;
-
- soc_info->emac_pdata->rmii_en = 1;
- gpio_set_value_cansleep(rmii_sel, 0);
-}
-#else
-static inline void da850_evm_setup_emac_rmii(int rmii_sel) { }
-#endif
-
-
-#define DA850_KEYS_DEBOUNCE_MS 10
-/*
- * At 200ms polling interval it is possible to miss an
- * event by tapping very lightly on the push button but most
- * pushes do result in an event; longer intervals require the
- * user to hold the button whereas shorter intervals require
- * more CPU time for polling.
- */
-#define DA850_GPIO_KEYS_POLL_MS 200
-
-enum da850_evm_ui_exp_pins {
- DA850_EVM_UI_EXP_SEL_C = 5,
- DA850_EVM_UI_EXP_SEL_B,
- DA850_EVM_UI_EXP_SEL_A,
- DA850_EVM_UI_EXP_PB8,
- DA850_EVM_UI_EXP_PB7,
- DA850_EVM_UI_EXP_PB6,
- DA850_EVM_UI_EXP_PB5,
- DA850_EVM_UI_EXP_PB4,
- DA850_EVM_UI_EXP_PB3,
- DA850_EVM_UI_EXP_PB2,
- DA850_EVM_UI_EXP_PB1,
-};
-
-static const char * const da850_evm_ui_exp[] = {
- [DA850_EVM_UI_EXP_SEL_C] = "sel_c",
- [DA850_EVM_UI_EXP_SEL_B] = "sel_b",
- [DA850_EVM_UI_EXP_SEL_A] = "sel_a",
- [DA850_EVM_UI_EXP_PB8] = "pb8",
- [DA850_EVM_UI_EXP_PB7] = "pb7",
- [DA850_EVM_UI_EXP_PB6] = "pb6",
- [DA850_EVM_UI_EXP_PB5] = "pb5",
- [DA850_EVM_UI_EXP_PB4] = "pb4",
- [DA850_EVM_UI_EXP_PB3] = "pb3",
- [DA850_EVM_UI_EXP_PB2] = "pb2",
- [DA850_EVM_UI_EXP_PB1] = "pb1",
-};
-
-#define DA850_N_UI_PB 8
-
-static struct gpio_keys_button da850_evm_ui_keys[] = {
- [0 ... DA850_N_UI_PB - 1] = {
- .type = EV_KEY,
- .active_low = 1,
- .wakeup = 0,
- .debounce_interval = DA850_KEYS_DEBOUNCE_MS,
- .code = -1, /* assigned at runtime */
- .gpio = -1, /* assigned at runtime */
- .desc = NULL, /* assigned at runtime */
- },
-};
-
-static struct gpio_keys_platform_data da850_evm_ui_keys_pdata = {
- .buttons = da850_evm_ui_keys,
- .nbuttons = ARRAY_SIZE(da850_evm_ui_keys),
- .poll_interval = DA850_GPIO_KEYS_POLL_MS,
-};
-
-static struct platform_device da850_evm_ui_keys_device = {
- .name = "gpio-keys-polled",
- .id = 0,
- .dev = {
- .platform_data = &da850_evm_ui_keys_pdata
- },
-};
-
-static void da850_evm_ui_keys_init(unsigned gpio)
-{
- int i;
- struct gpio_keys_button *button;
-
- for (i = 0; i < DA850_N_UI_PB; i++) {
- button = &da850_evm_ui_keys[i];
- button->code = KEY_F8 - i;
- button->desc = da850_evm_ui_exp[DA850_EVM_UI_EXP_PB8 + i];
- button->gpio = gpio + DA850_EVM_UI_EXP_PB8 + i;
- }
-}
-
-#ifdef CONFIG_DA850_UI_SD_VIDEO_PORT
-static inline void da850_evm_setup_video_port(int video_sel)
-{
- gpio_set_value_cansleep(video_sel, 0);
-}
-#else
-static inline void da850_evm_setup_video_port(int video_sel) { }
-#endif
-
-static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio,
- unsigned ngpio, void *c)
-{
- int sel_a, sel_b, sel_c, ret;
-
- sel_a = gpio + DA850_EVM_UI_EXP_SEL_A;
- sel_b = gpio + DA850_EVM_UI_EXP_SEL_B;
- sel_c = gpio + DA850_EVM_UI_EXP_SEL_C;
-
- ret = gpio_request(sel_a, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_A]);
- if (ret) {
- pr_warn("Cannot open UI expander pin %d\n", sel_a);
- goto exp_setup_sela_fail;
- }
-
- ret = gpio_request(sel_b, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_B]);
- if (ret) {
- pr_warn("Cannot open UI expander pin %d\n", sel_b);
- goto exp_setup_selb_fail;
- }
-
- ret = gpio_request(sel_c, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_C]);
- if (ret) {
- pr_warn("Cannot open UI expander pin %d\n", sel_c);
- goto exp_setup_selc_fail;
- }
-
- /* deselect all functionalities */
- gpio_direction_output(sel_a, 1);
- gpio_direction_output(sel_b, 1);
- gpio_direction_output(sel_c, 1);
-
- da850_evm_ui_keys_init(gpio);
- ret = platform_device_register(&da850_evm_ui_keys_device);
- if (ret) {
- pr_warn("Could not register UI GPIO expander push-buttons");
- goto exp_setup_keys_fail;
- }
-
- pr_info("DA850/OMAP-L138 EVM UI card detected\n");
-
- da850_evm_setup_nor_nand();
-
- da850_evm_setup_emac_rmii(sel_a);
-
- da850_evm_setup_video_port(sel_c);
-
- return 0;
-
-exp_setup_keys_fail:
- gpio_free(sel_c);
-exp_setup_selc_fail:
- gpio_free(sel_b);
-exp_setup_selb_fail:
- gpio_free(sel_a);
-exp_setup_sela_fail:
- return ret;
-}
-
-static void da850_evm_ui_expander_teardown(struct i2c_client *client,
- unsigned gpio, unsigned ngpio, void *c)
-{
- platform_device_unregister(&da850_evm_ui_keys_device);
-
- /* deselect all functionalities */
- gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_C, 1);
- gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_B, 1);
- gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_A, 1);
-
- gpio_free(gpio + DA850_EVM_UI_EXP_SEL_C);
- gpio_free(gpio + DA850_EVM_UI_EXP_SEL_B);
- gpio_free(gpio + DA850_EVM_UI_EXP_SEL_A);
-}
-
-/* assign the baseboard expander's GPIOs after the UI board's */
-#define DA850_UI_EXPANDER_N_GPIOS ARRAY_SIZE(da850_evm_ui_exp)
-#define DA850_BB_EXPANDER_GPIO_BASE (DAVINCI_N_GPIO + DA850_UI_EXPANDER_N_GPIOS)
-
-enum da850_evm_bb_exp_pins {
- DA850_EVM_BB_EXP_DEEP_SLEEP_EN = 0,
- DA850_EVM_BB_EXP_SW_RST,
- DA850_EVM_BB_EXP_TP_23,
- DA850_EVM_BB_EXP_TP_22,
- DA850_EVM_BB_EXP_TP_21,
- DA850_EVM_BB_EXP_USER_PB1,
- DA850_EVM_BB_EXP_USER_LED2,
- DA850_EVM_BB_EXP_USER_LED1,
- DA850_EVM_BB_EXP_USER_SW1,
- DA850_EVM_BB_EXP_USER_SW2,
- DA850_EVM_BB_EXP_USER_SW3,
- DA850_EVM_BB_EXP_USER_SW4,
- DA850_EVM_BB_EXP_USER_SW5,
- DA850_EVM_BB_EXP_USER_SW6,
- DA850_EVM_BB_EXP_USER_SW7,
- DA850_EVM_BB_EXP_USER_SW8
-};
-
-static const char * const da850_evm_bb_exp[] = {
- [DA850_EVM_BB_EXP_DEEP_SLEEP_EN] = "deep_sleep_en",
- [DA850_EVM_BB_EXP_SW_RST] = "sw_rst",
- [DA850_EVM_BB_EXP_TP_23] = "tp_23",
- [DA850_EVM_BB_EXP_TP_22] = "tp_22",
- [DA850_EVM_BB_EXP_TP_21] = "tp_21",
- [DA850_EVM_BB_EXP_USER_PB1] = "user_pb1",
- [DA850_EVM_BB_EXP_USER_LED2] = "user_led2",
- [DA850_EVM_BB_EXP_USER_LED1] = "user_led1",
- [DA850_EVM_BB_EXP_USER_SW1] = "user_sw1",
- [DA850_EVM_BB_EXP_USER_SW2] = "user_sw2",
- [DA850_EVM_BB_EXP_USER_SW3] = "user_sw3",
- [DA850_EVM_BB_EXP_USER_SW4] = "user_sw4",
- [DA850_EVM_BB_EXP_USER_SW5] = "user_sw5",
- [DA850_EVM_BB_EXP_USER_SW6] = "user_sw6",
- [DA850_EVM_BB_EXP_USER_SW7] = "user_sw7",
- [DA850_EVM_BB_EXP_USER_SW8] = "user_sw8",
-};
-
-#define DA850_N_BB_USER_SW 8
-
-static struct gpio_keys_button da850_evm_bb_keys[] = {
- [0] = {
- .type = EV_KEY,
- .active_low = 1,
- .wakeup = 0,
- .debounce_interval = DA850_KEYS_DEBOUNCE_MS,
- .code = KEY_PROG1,
- .desc = NULL, /* assigned at runtime */
- .gpio = -1, /* assigned at runtime */
- },
- [1 ... DA850_N_BB_USER_SW] = {
- .type = EV_SW,
- .active_low = 1,
- .wakeup = 0,
- .debounce_interval = DA850_KEYS_DEBOUNCE_MS,
- .code = -1, /* assigned at runtime */
- .desc = NULL, /* assigned at runtime */
- .gpio = -1, /* assigned at runtime */
- },
-};
-
-static struct gpio_keys_platform_data da850_evm_bb_keys_pdata = {
- .buttons = da850_evm_bb_keys,
- .nbuttons = ARRAY_SIZE(da850_evm_bb_keys),
- .poll_interval = DA850_GPIO_KEYS_POLL_MS,
-};
-
-static struct platform_device da850_evm_bb_keys_device = {
- .name = "gpio-keys-polled",
- .id = 1,
- .dev = {
- .platform_data = &da850_evm_bb_keys_pdata
- },
-};
-
-static void da850_evm_bb_keys_init(unsigned gpio)
-{
- int i;
- struct gpio_keys_button *button;
-
- button = &da850_evm_bb_keys[0];
- button->desc = da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_PB1];
- button->gpio = gpio + DA850_EVM_BB_EXP_USER_PB1;
-
- for (i = 0; i < DA850_N_BB_USER_SW; i++) {
- button = &da850_evm_bb_keys[i + 1];
- button->code = SW_LID + i;
- button->desc = da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_SW1 + i];
- button->gpio = gpio + DA850_EVM_BB_EXP_USER_SW1 + i;
- }
-}
-
-static struct gpio_led da850_evm_bb_leds[] = {
- {
- .name = "user_led2",
- },
- {
- .name = "user_led1",
- },
-};
-
-static struct gpio_led_platform_data da850_evm_bb_leds_pdata = {
- .leds = da850_evm_bb_leds,
- .num_leds = ARRAY_SIZE(da850_evm_bb_leds),
-};
-
-static struct gpiod_lookup_table da850_evm_bb_leds_gpio_table = {
- .dev_id = "leds-gpio",
- .table = {
- GPIO_LOOKUP_IDX("i2c-bb-expander",
- DA850_EVM_BB_EXP_USER_LED2, NULL,
- 0, GPIO_ACTIVE_LOW),
- GPIO_LOOKUP_IDX("i2c-bb-expander",
- DA850_EVM_BB_EXP_USER_LED2 + 1, NULL,
- 1, GPIO_ACTIVE_LOW),
-
- { },
- },
-};
-
-static struct platform_device da850_evm_bb_leds_device = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &da850_evm_bb_leds_pdata
- }
-};
-
-static int da850_evm_bb_expander_setup(struct i2c_client *client,
- unsigned gpio, unsigned ngpio,
- void *c)
-{
- int ret;
-
- /*
- * Register the switches and pushbutton on the baseboard as a gpio-keys
- * device.
- */
- da850_evm_bb_keys_init(gpio);
- ret = platform_device_register(&da850_evm_bb_keys_device);
- if (ret) {
- pr_warn("Could not register baseboard GPIO expander keys");
- goto io_exp_setup_sw_fail;
- }
-
- gpiod_add_lookup_table(&da850_evm_bb_leds_gpio_table);
- ret = platform_device_register(&da850_evm_bb_leds_device);
- if (ret) {
- pr_warn("Could not register baseboard GPIO expander LEDs");
- goto io_exp_setup_leds_fail;
- }
-
- return 0;
-
-io_exp_setup_leds_fail:
- platform_device_unregister(&da850_evm_bb_keys_device);
-io_exp_setup_sw_fail:
- return ret;
-}
-
-static void da850_evm_bb_expander_teardown(struct i2c_client *client,
- unsigned gpio, unsigned ngpio, void *c)
-{
- platform_device_unregister(&da850_evm_bb_leds_device);
- platform_device_unregister(&da850_evm_bb_keys_device);
-}
-
-static struct pca953x_platform_data da850_evm_ui_expander_info = {
- .gpio_base = DAVINCI_N_GPIO,
- .setup = da850_evm_ui_expander_setup,
- .teardown = da850_evm_ui_expander_teardown,
- .names = da850_evm_ui_exp,
-};
-
-static struct pca953x_platform_data da850_evm_bb_expander_info = {
- .gpio_base = DA850_BB_EXPANDER_GPIO_BASE,
- .setup = da850_evm_bb_expander_setup,
- .teardown = da850_evm_bb_expander_teardown,
- .names = da850_evm_bb_exp,
-};
-
-static struct i2c_board_info __initdata da850_evm_i2c_devices[] = {
- {
- I2C_BOARD_INFO("tlv320aic3x", 0x18),
- },
- {
- I2C_BOARD_INFO("tca6416", 0x20),
- .dev_name = "ui-expander",
- .platform_data = &da850_evm_ui_expander_info,
- },
- {
- I2C_BOARD_INFO("tca6416", 0x21),
- .dev_name = "bb-expander",
- .platform_data = &da850_evm_bb_expander_info,
- },
-};
-
-static struct davinci_i2c_platform_data da850_evm_i2c_0_pdata = {
- .bus_freq = 100, /* kHz */
- .bus_delay = 0, /* usec */
-};
-
-/* davinci da850 evm audio machine driver */
-static u8 da850_iis_serializer_direction[] = {
- INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
- INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
- INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, TX_MODE,
- RX_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
-};
-
-static struct snd_platform_data da850_evm_snd_data = {
- .tx_dma_offset = 0x2000,
- .rx_dma_offset = 0x2000,
- .op_mode = DAVINCI_MCASP_IIS_MODE,
- .num_serializer = ARRAY_SIZE(da850_iis_serializer_direction),
- .tdm_slots = 2,
- .serial_dir = da850_iis_serializer_direction,
- .asp_chan_q = EVENTQ_0,
- .ram_chan_q = EVENTQ_1,
- .version = MCASP_VERSION_2,
- .txnumevt = 1,
- .rxnumevt = 1,
- .sram_size_playback = SZ_8K,
- .sram_size_capture = SZ_8K,
-};
-
-static const short da850_evm_mcasp_pins[] __initconst = {
- DA850_AHCLKX, DA850_ACLKX, DA850_AFSX,
- DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE,
- DA850_AXR_11, DA850_AXR_12,
- -1
-};
-
-#define DA850_MMCSD_CD_PIN GPIO_TO_PIN(4, 0)
-#define DA850_MMCSD_WP_PIN GPIO_TO_PIN(4, 1)
-
-static struct gpiod_lookup_table mmc_gpios_table = {
- .dev_id = "da830-mmc.0",
- .table = {
- /* gpio chip 2 contains gpio range 64-95 */
- GPIO_LOOKUP("davinci_gpio", DA850_MMCSD_CD_PIN, "cd",
- GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("davinci_gpio", DA850_MMCSD_WP_PIN, "wp",
- GPIO_ACTIVE_HIGH),
- { }
- },
-};
-
-static struct davinci_mmc_config da850_mmc_config = {
- .wires = 4,
- .max_freq = 50000000,
- .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
-};
-
-static const short da850_evm_mmcsd0_pins[] __initconst = {
- DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2,
- DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD,
- DA850_GPIO4_0, DA850_GPIO4_1,
- -1
-};
-
-static struct property_entry da850_lcd_backlight_props[] = {
- PROPERTY_ENTRY_BOOL("default-on"),
- { }
-};
-
-static struct gpiod_lookup_table da850_lcd_backlight_gpio_table = {
- .dev_id = "gpio-backlight",
- .table = {
- GPIO_LOOKUP("davinci_gpio", DA850_LCD_BL_PIN, NULL, 0),
- { }
- },
-};
-
-static const struct platform_device_info da850_lcd_backlight_info = {
- .name = "gpio-backlight",
- .id = PLATFORM_DEVID_NONE,
- .properties = da850_lcd_backlight_props,
-};
-
-static struct regulator_consumer_supply da850_lcd_supplies[] = {
- REGULATOR_SUPPLY("lcd", NULL),
-};
-
-static struct regulator_init_data da850_lcd_supply_data = {
- .consumer_supplies = da850_lcd_supplies,
- .num_consumer_supplies = ARRAY_SIZE(da850_lcd_supplies),
- .constraints = {
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- },
-};
-
-static struct fixed_voltage_config da850_lcd_supply = {
- .supply_name = "lcd",
- .microvolts = 33000000,
- .init_data = &da850_lcd_supply_data,
-};
-
-static struct platform_device da850_lcd_supply_device = {
- .name = "reg-fixed-voltage",
- .id = 1, /* Dummy fixed regulator is 0 */
- .dev = {
- .platform_data = &da850_lcd_supply,
- },
-};
-
-static struct gpiod_lookup_table da850_lcd_supply_gpio_table = {
- .dev_id = "reg-fixed-voltage.1",
- .table = {
- GPIO_LOOKUP("davinci_gpio", DA850_LCD_PWR_PIN, NULL, 0),
- { }
- },
-};
-
-static struct gpiod_lookup_table *da850_lcd_gpio_lookups[] = {
- &da850_lcd_backlight_gpio_table,
- &da850_lcd_supply_gpio_table,
-};
-
-static int da850_lcd_hw_init(void)
-{
- struct platform_device *backlight;
- int status;
-
- gpiod_add_lookup_tables(da850_lcd_gpio_lookups,
- ARRAY_SIZE(da850_lcd_gpio_lookups));
-
- backlight = platform_device_register_full(&da850_lcd_backlight_info);
- if (IS_ERR(backlight))
- return PTR_ERR(backlight);
-
- status = platform_device_register(&da850_lcd_supply_device);
- if (status)
- return status;
-
- return 0;
-}
-
-/* Fixed regulator support */
-static struct regulator_consumer_supply fixed_supplies[] = {
- /* Baseboard 3.3V: 5V -> TPS73701DCQ -> 3.3V */
- REGULATOR_SUPPLY("AVDD", "1-0018"),
- REGULATOR_SUPPLY("DRVDD", "1-0018"),
-
- /* Baseboard 1.8V: 5V -> TPS73701DCQ -> 1.8V */
- REGULATOR_SUPPLY("DVDD", "1-0018"),
-
- /* UI card 3.3V: 5V -> TPS73701DCQ -> 3.3V */
- REGULATOR_SUPPLY("vcc", "1-0020"),
-};
-
-/* TPS65070 voltage regulator support */
-
-/* 3.3V */
-static struct regulator_consumer_supply tps65070_dcdc1_consumers[] = {
- {
- .supply = "usb0_vdda33",
- },
- {
- .supply = "usb1_vdda33",
- },
-};
-
-/* 3.3V or 1.8V */
-static struct regulator_consumer_supply tps65070_dcdc2_consumers[] = {
- {
- .supply = "dvdd3318_a",
- },
- {
- .supply = "dvdd3318_b",
- },
- {
- .supply = "dvdd3318_c",
- },
- REGULATOR_SUPPLY("IOVDD", "1-0018"),
-};
-
-/* 1.2V */
-static struct regulator_consumer_supply tps65070_dcdc3_consumers[] = {
- {
- .supply = "cvdd",
- },
-};
-
-/* 1.8V LDO */
-static struct regulator_consumer_supply tps65070_ldo1_consumers[] = {
- {
- .supply = "sata_vddr",
- },
- {
- .supply = "usb0_vdda18",
- },
- {
- .supply = "usb1_vdda18",
- },
- {
- .supply = "ddr_dvdd18",
- },
-};
-
-/* 1.2V LDO */
-static struct regulator_consumer_supply tps65070_ldo2_consumers[] = {
- {
- .supply = "sata_vdd",
- },
- {
- .supply = "pll0_vdda",
- },
- {
- .supply = "pll1_vdda",
- },
- {
- .supply = "usbs_cvdd",
- },
- {
- .supply = "vddarnwa1",
- },
-};
-
-/* We take advantage of the fact that both defdcdc{2,3} are tied high */
-static struct tps6507x_reg_platform_data tps6507x_platform_data = {
- .defdcdc_default = true,
-};
-
-static struct regulator_init_data tps65070_regulator_data[] = {
- /* dcdc1 */
- {
- .constraints = {
- .min_uV = 3150000,
- .max_uV = 3450000,
- .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
- REGULATOR_CHANGE_STATUS),
- .boot_on = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc1_consumers),
- .consumer_supplies = tps65070_dcdc1_consumers,
- },
-
- /* dcdc2 */
- {
- .constraints = {
- .min_uV = 1710000,
- .max_uV = 3450000,
- .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
- REGULATOR_CHANGE_STATUS),
- .boot_on = 1,
- .always_on = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc2_consumers),
- .consumer_supplies = tps65070_dcdc2_consumers,
- .driver_data = &tps6507x_platform_data,
- },
-
- /* dcdc3 */
- {
- .constraints = {
- .min_uV = 950000,
- .max_uV = 1350000,
- .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
- REGULATOR_CHANGE_STATUS),
- .boot_on = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc3_consumers),
- .consumer_supplies = tps65070_dcdc3_consumers,
- .driver_data = &tps6507x_platform_data,
- },
-
- /* ldo1 */
- {
- .constraints = {
- .min_uV = 1710000,
- .max_uV = 1890000,
- .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
- REGULATOR_CHANGE_STATUS),
- .boot_on = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65070_ldo1_consumers),
- .consumer_supplies = tps65070_ldo1_consumers,
- },
-
- /* ldo2 */
- {
- .constraints = {
- .min_uV = 1140000,
- .max_uV = 1320000,
- .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
- REGULATOR_CHANGE_STATUS),
- .boot_on = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65070_ldo2_consumers),
- .consumer_supplies = tps65070_ldo2_consumers,
- },
-};
-
-static struct touchscreen_init_data tps6507x_touchscreen_data = {
- .poll_period = 30, /* ms between touch samples */
- .min_pressure = 0x30, /* minimum pressure to trigger touch */
- .vendor = 0, /* /sys/class/input/input?/id/vendor */
- .product = 65070, /* /sys/class/input/input?/id/product */
- .version = 0x100, /* /sys/class/input/input?/id/version */
-};
-
-static struct tps6507x_board tps_board = {
- .tps6507x_pmic_init_data = &tps65070_regulator_data[0],
- .tps6507x_ts_init_data = &tps6507x_touchscreen_data,
-};
-
-static struct i2c_board_info __initdata da850_evm_tps65070_info[] = {
- {
- I2C_BOARD_INFO("tps6507x", 0x48),
- .platform_data = &tps_board,
- },
-};
-
-static int __init pmic_tps65070_init(void)
-{
- return i2c_register_board_info(1, da850_evm_tps65070_info,
- ARRAY_SIZE(da850_evm_tps65070_info));
-}
-
-static const short da850_evm_lcdc_pins[] = {
- DA850_GPIO2_8, DA850_GPIO2_15,
- -1
-};
-
-static const short da850_evm_mii_pins[] = {
- DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
- DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
- DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
- DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
- DA850_MDIO_D,
- -1
-};
-
-static const short da850_evm_rmii_pins[] = {
- DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
- DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
- DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
- DA850_MDIO_D,
- -1
-};
-
-static struct gpiod_hog da850_evm_emac_gpio_hogs[] = {
- {
- .chip_label = "davinci_gpio",
- .chip_hwnum = DA850_MII_MDIO_CLKEN_PIN,
- .line_name = "mdio_clk_en",
- .lflags = 0,
- /* dflags set in da850_evm_config_emac() */
- },
- { }
-};
-
-static int __init da850_evm_config_emac(void)
-{
- void __iomem *cfg_chip3_base;
- int ret;
- u32 val;
- struct davinci_soc_info *soc_info = &davinci_soc_info;
- u8 rmii_en;
-
- if (!machine_is_davinci_da850_evm())
- return 0;
-
- rmii_en = soc_info->emac_pdata->rmii_en;
-
- cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
-
- val = __raw_readl(cfg_chip3_base);
-
- if (rmii_en) {
- val |= BIT(8);
- ret = davinci_cfg_reg_list(da850_evm_rmii_pins);
- pr_info("EMAC: RMII PHY configured, MII PHY will not be"
- " functional\n");
- } else {
- val &= ~BIT(8);
- ret = davinci_cfg_reg_list(da850_evm_mii_pins);
- pr_info("EMAC: MII PHY configured, RMII PHY will not be"
- " functional\n");
- }
-
- if (ret)
- pr_warn("%s: CPGMAC/RMII mux setup failed: %d\n",
- __func__, ret);
-
- /* configure the CFGCHIP3 register for RMII or MII */
- __raw_writel(val, cfg_chip3_base);
-
- ret = davinci_cfg_reg(DA850_GPIO2_6);
- if (ret)
- pr_warn("%s:GPIO(2,6) mux setup failed\n", __func__);
-
- da850_evm_emac_gpio_hogs[0].dflags = rmii_en ? GPIOD_OUT_HIGH
- : GPIOD_OUT_LOW;
- gpiod_add_hogs(da850_evm_emac_gpio_hogs);
-
- soc_info->emac_pdata->phy_id = DA850_EVM_PHY_ID;
-
- ret = da8xx_register_emac();
- if (ret)
- pr_warn("%s: EMAC registration failed: %d\n", __func__, ret);
-
- return 0;
-}
-device_initcall(da850_evm_config_emac);
-
-/*
- * The following EDMA channels/slots are not being used by drivers (for
- * example: Timer, GPIO, UART events etc) on da850/omap-l138 EVM, hence
- * they are being reserved for codecs on the DSP side.
- */
-static const s16 da850_dma0_rsv_chans[][2] = {
- /* (offset, number) */
- { 8, 6},
- {24, 4},
- {30, 2},
- {-1, -1}
-};
-
-static const s16 da850_dma0_rsv_slots[][2] = {
- /* (offset, number) */
- { 8, 6},
- {24, 4},
- {30, 50},
- {-1, -1}
-};
-
-static const s16 da850_dma1_rsv_chans[][2] = {
- /* (offset, number) */
- { 0, 28},
- {30, 2},
- {-1, -1}
-};
-
-static const s16 da850_dma1_rsv_slots[][2] = {
- /* (offset, number) */
- { 0, 28},
- {30, 90},
- {-1, -1}
-};
-
-static struct edma_rsv_info da850_edma_cc0_rsv = {
- .rsv_chans = da850_dma0_rsv_chans,
- .rsv_slots = da850_dma0_rsv_slots,
-};
-
-static struct edma_rsv_info da850_edma_cc1_rsv = {
- .rsv_chans = da850_dma1_rsv_chans,
- .rsv_slots = da850_dma1_rsv_slots,
-};
-
-static struct edma_rsv_info *da850_edma_rsv[2] = {
- &da850_edma_cc0_rsv,
- &da850_edma_cc1_rsv,
-};
-
-#ifdef CONFIG_CPU_FREQ
-static __init int da850_evm_init_cpufreq(void)
-{
- switch (system_rev & 0xF) {
- case 3:
- da850_max_speed = 456000;
- break;
- case 2:
- da850_max_speed = 408000;
- break;
- case 1:
- da850_max_speed = 372000;
- break;
- }
-
- return da850_register_cpufreq("pll0_sysclk3");
-}
-#else
-static __init int da850_evm_init_cpufreq(void) { return 0; }
-#endif
-
-#if defined(CONFIG_DA850_UI_SD_VIDEO_PORT)
-
-#define TVP5147_CH0 "tvp514x-0"
-#define TVP5147_CH1 "tvp514x-1"
-
-/* VPIF capture configuration */
-static struct tvp514x_platform_data tvp5146_pdata = {
- .clk_polarity = 0,
- .hs_polarity = 1,
- .vs_polarity = 1,
-};
-
-#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
-
-static struct vpif_input da850_ch0_inputs[] = {
- {
- .input = {
- .index = 0,
- .name = "Composite",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .capabilities = V4L2_IN_CAP_STD,
- .std = TVP514X_STD_ALL,
- },
- .input_route = INPUT_CVBS_VI2B,
- .output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC,
- .subdev_name = TVP5147_CH0,
- },
-};
-
-static struct vpif_input da850_ch1_inputs[] = {
- {
- .input = {
- .index = 0,
- .name = "S-Video",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .capabilities = V4L2_IN_CAP_STD,
- .std = TVP514X_STD_ALL,
- },
- .input_route = INPUT_SVIDEO_VI2C_VI1C,
- .output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC,
- .subdev_name = TVP5147_CH1,
- },
-};
-
-static struct vpif_subdev_info da850_vpif_capture_sdev_info[] = {
- {
- .name = TVP5147_CH0,
- .board_info = {
- I2C_BOARD_INFO("tvp5146", 0x5d),
- .platform_data = &tvp5146_pdata,
- },
- },
- {
- .name = TVP5147_CH1,
- .board_info = {
- I2C_BOARD_INFO("tvp5146", 0x5c),
- .platform_data = &tvp5146_pdata,
- },
- },
-};
-
-static struct vpif_capture_config da850_vpif_capture_config = {
- .subdev_info = da850_vpif_capture_sdev_info,
- .subdev_count = ARRAY_SIZE(da850_vpif_capture_sdev_info),
- .i2c_adapter_id = 1,
- .chan_config[0] = {
- .inputs = da850_ch0_inputs,
- .input_count = ARRAY_SIZE(da850_ch0_inputs),
- .vpif_if = {
- .if_type = VPIF_IF_BT656,
- .hd_pol = 1,
- .vd_pol = 1,
- .fid_pol = 0,
- },
- },
- .chan_config[1] = {
- .inputs = da850_ch1_inputs,
- .input_count = ARRAY_SIZE(da850_ch1_inputs),
- .vpif_if = {
- .if_type = VPIF_IF_BT656,
- .hd_pol = 1,
- .vd_pol = 1,
- .fid_pol = 0,
- },
- },
- .card_name = "DA850/OMAP-L138 Video Capture",
-};
-
-/* VPIF display configuration */
-
-static struct adv7343_platform_data adv7343_pdata = {
- .mode_config = {
- .dac = { 1, 1, 1 },
- },
- .sd_config = {
- .sd_dac_out = { 1 },
- },
-};
-
-static struct vpif_subdev_info da850_vpif_subdev[] = {
- {
- .name = "adv7343",
- .board_info = {
- I2C_BOARD_INFO("adv7343", 0x2a),
- .platform_data = &adv7343_pdata,
- },
- },
-};
-
-static const struct vpif_output da850_ch0_outputs[] = {
- {
- .output = {
- .index = 0,
- .name = "Composite",
- .type = V4L2_OUTPUT_TYPE_ANALOG,
- .capabilities = V4L2_OUT_CAP_STD,
- .std = V4L2_STD_ALL,
- },
- .subdev_name = "adv7343",
- .output_route = ADV7343_COMPOSITE_ID,
- },
- {
- .output = {
- .index = 1,
- .name = "S-Video",
- .type = V4L2_OUTPUT_TYPE_ANALOG,
- .capabilities = V4L2_OUT_CAP_STD,
- .std = V4L2_STD_ALL,
- },
- .subdev_name = "adv7343",
- .output_route = ADV7343_SVIDEO_ID,
- },
-};
-
-static struct vpif_display_config da850_vpif_display_config = {
- .subdevinfo = da850_vpif_subdev,
- .subdev_count = ARRAY_SIZE(da850_vpif_subdev),
- .chan_config[0] = {
- .outputs = da850_ch0_outputs,
- .output_count = ARRAY_SIZE(da850_ch0_outputs),
- },
- .card_name = "DA850/OMAP-L138 Video Display",
- .i2c_adapter_id = 1,
-};
-
-static __init void da850_vpif_init(void)
-{
- int ret;
-
- ret = da850_register_vpif();
- if (ret)
- pr_warn("da850_evm_init: VPIF setup failed: %d\n", ret);
-
- ret = davinci_cfg_reg_list(da850_vpif_capture_pins);
- if (ret)
- pr_warn("da850_evm_init: VPIF capture mux setup failed: %d\n",
- ret);
-
- ret = da850_register_vpif_capture(&da850_vpif_capture_config);
- if (ret)
- pr_warn("da850_evm_init: VPIF capture setup failed: %d\n", ret);
-
- ret = davinci_cfg_reg_list(da850_vpif_display_pins);
- if (ret)
- pr_warn("da850_evm_init: VPIF display mux setup failed: %d\n",
- ret);
-
- ret = da850_register_vpif_display(&da850_vpif_display_config);
- if (ret)
- pr_warn("da850_evm_init: VPIF display setup failed: %d\n", ret);
-}
-
-#else
-static __init void da850_vpif_init(void) {}
-#endif
-
-#define DA850EVM_SATA_REFCLKPN_RATE (100 * 1000 * 1000)
-
-static __init void da850_evm_init(void)
-{
- int ret;
-
- da850_register_clocks();
-
- ret = da850_register_gpio();
- if (ret)
- pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
-
- regulator_register_fixed(0, fixed_supplies, ARRAY_SIZE(fixed_supplies));
-
- ret = pmic_tps65070_init();
- if (ret)
- pr_warn("%s: TPS65070 PMIC init failed: %d\n", __func__, ret);
-
- ret = da850_register_edma(da850_edma_rsv);
- if (ret)
- pr_warn("%s: EDMA registration failed: %d\n", __func__, ret);
-
- ret = davinci_cfg_reg_list(da850_i2c0_pins);
- if (ret)
- pr_warn("%s: I2C0 mux setup failed: %d\n", __func__, ret);
-
- ret = da8xx_register_i2c(0, &da850_evm_i2c_0_pdata);
- if (ret)
- pr_warn("%s: I2C0 registration failed: %d\n", __func__, ret);
-
-
- ret = da8xx_register_watchdog();
- if (ret)
- pr_warn("%s: watchdog registration failed: %d\n",
- __func__, ret);
-
- if (HAS_MMC) {
- ret = davinci_cfg_reg_list(da850_evm_mmcsd0_pins);
- if (ret)
- pr_warn("%s: MMCSD0 mux setup failed: %d\n",
- __func__, ret);
-
- gpiod_add_lookup_table(&mmc_gpios_table);
-
- ret = da8xx_register_mmcsd0(&da850_mmc_config);
- if (ret)
- pr_warn("%s: MMCSD0 registration failed: %d\n",
- __func__, ret);
- }
-
- davinci_serial_init(da8xx_serial_device);
-
- nvmem_add_cell_table(&da850evm_nvmem_cell_table);
- nvmem_add_cell_lookups(&da850evm_nvmem_cell_lookup, 1);
-
- i2c_register_board_info(1, da850_evm_i2c_devices,
- ARRAY_SIZE(da850_evm_i2c_devices));
-
- /*
- * shut down uart 0 and 1; they are not used on the board and
- * accessing them causes endless "too much work in irq53" messages
- * with arago fs
- */
- __raw_writel(0, IO_ADDRESS(DA8XX_UART1_BASE) + 0x30);
- __raw_writel(0, IO_ADDRESS(DA8XX_UART0_BASE) + 0x30);
-
- ret = davinci_cfg_reg_list(da850_evm_mcasp_pins);
- if (ret)
- pr_warn("%s: McASP mux setup failed: %d\n", __func__, ret);
-
- da850_evm_snd_data.sram_pool = sram_get_gen_pool();
- da8xx_register_mcasp(0, &da850_evm_snd_data);
-
- ret = davinci_cfg_reg_list(da850_lcdcntl_pins);
- if (ret)
- pr_warn("%s: LCDC mux setup failed: %d\n", __func__, ret);
-
- ret = da8xx_register_uio_pruss();
- if (ret)
- pr_warn("da850_evm_init: pruss initialization failed: %d\n",
- ret);
-
- /* Handle board specific muxing for LCD here */
- ret = davinci_cfg_reg_list(da850_evm_lcdc_pins);
- if (ret)
- pr_warn("%s: EVM specific LCD mux setup failed: %d\n",
- __func__, ret);
-
- ret = da850_lcd_hw_init();
- if (ret)
- pr_warn("%s: LCD initialization failed: %d\n", __func__, ret);
-
- ret = da8xx_register_lcdc(&sharp_lk043t1dg01_pdata);
- if (ret)
- pr_warn("%s: LCDC registration failed: %d\n", __func__, ret);
-
- ret = da8xx_register_rtc();
- if (ret)
- pr_warn("%s: RTC setup failed: %d\n", __func__, ret);
-
- ret = da850_evm_init_cpufreq();
- if (ret)
- pr_warn("%s: cpufreq registration failed: %d\n", __func__, ret);
-
- ret = da8xx_register_cpuidle();
- if (ret)
- pr_warn("%s: cpuidle registration failed: %d\n", __func__, ret);
-
- davinci_pm_init();
- da850_vpif_init();
-
- ret = spi_register_board_info(da850evm_spi_info,
- ARRAY_SIZE(da850evm_spi_info));
- if (ret)
- pr_warn("%s: spi info registration failed: %d\n", __func__,
- ret);
-
- ret = da8xx_register_spi_bus(1, ARRAY_SIZE(da850evm_spi_info));
- if (ret)
- pr_warn("%s: SPI 1 registration failed: %d\n", __func__, ret);
-
- ret = da850_register_sata(DA850EVM_SATA_REFCLKPN_RATE);
- if (ret)
- pr_warn("%s: SATA registration failed: %d\n", __func__, ret);
-
- ret = da8xx_register_rproc();
- if (ret)
- pr_warn("%s: dsp/rproc registration failed: %d\n",
- __func__, ret);
-
- regulator_has_full_constraints();
-}
-
-#ifdef CONFIG_SERIAL_8250_CONSOLE
-static int __init da850_evm_console_init(void)
-{
- if (!machine_is_davinci_da850_evm())
- return 0;
-
- return add_preferred_console("ttyS", 2, "115200");
-}
-console_initcall(da850_evm_console_init);
-#endif
-
-static void __init da850_evm_map_io(void)
-{
- da850_init();
-}
-
-MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138/AM18x EVM")
- .atag_offset = 0x100,
- .map_io = da850_evm_map_io,
- .init_irq = da850_init_irq,
- .init_time = da850_init_time,
- .init_machine = da850_evm_init,
- .init_late = davinci_init_late,
- .dma_zone_size = SZ_128M,
- .reserve = da8xx_rproc_reserve_cma,
-MACHINE_END
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
deleted file mode 100644
index b48ab1c3e48b..000000000000
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ /dev/null
@@ -1,444 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * TI DaVinci EVM board support
- *
- * Author: Kevin Hilman, Deep Root Systems, LLC
- *
- * 2007 (c) MontaVista Software, Inc.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/err.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
-#include <linux/gpio/machine.h>
-#include <linux/clk.h>
-#include <linux/dm9000.h>
-#include <linux/videodev2.h>
-#include <media/i2c/tvp514x.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/eeprom.h>
-#include <linux/platform_data/gpio-davinci.h>
-#include <linux/platform_data/i2c-davinci.h>
-#include <linux/platform_data/mtd-davinci.h>
-#include <linux/platform_data/mmc-davinci.h>
-#include <linux/platform_data/usb-davinci.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include "serial.h"
-#include "common.h"
-#include "davinci.h"
-
-/* NOTE: this is geared for the standard config, with a socketed
- * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
- * swap chips, maybe with a different block size, partitioning may
- * need to be changed.
- */
-#define NAND_BLOCK_SIZE SZ_128K
-
-static struct mtd_partition davinci_nand_partitions[] = {
- {
- /* UBL (a few copies) plus U-Boot */
- .name = "bootloader",
- .offset = 0,
- .size = 15 * NAND_BLOCK_SIZE,
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- }, {
- /* U-Boot environment */
- .name = "params",
- .offset = MTDPART_OFS_APPEND,
- .size = 1 * NAND_BLOCK_SIZE,
- .mask_flags = 0,
- }, {
- .name = "kernel",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_4M,
- .mask_flags = 0,
- }, {
- .name = "filesystem1",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_512M,
- .mask_flags = 0,
- }, {
- .name = "filesystem2",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- .mask_flags = 0,
- }
- /* two blocks with bad block table (and mirror) at the end */
-};
-
-static struct davinci_nand_pdata davinci_nand_data = {
- .core_chipsel = 0,
- .mask_chipsel = BIT(14),
- .parts = davinci_nand_partitions,
- .nr_parts = ARRAY_SIZE(davinci_nand_partitions),
- .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
- .bbt_options = NAND_BBT_USE_FLASH,
- .ecc_bits = 4,
-};
-
-static struct resource davinci_nand_resources[] = {
- {
- .start = DM355_ASYNC_EMIF_DATA_CE0_BASE,
- .end = DM355_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = DM355_ASYNC_EMIF_CONTROL_BASE,
- .end = DM355_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device davinci_nand_device = {
- .name = "davinci_nand",
- .id = 0,
-
- .num_resources = ARRAY_SIZE(davinci_nand_resources),
- .resource = davinci_nand_resources,
-
- .dev = {
- .platform_data = &davinci_nand_data,
- },
-};
-
-#define DM355_I2C_SDA_PIN GPIO_TO_PIN(0, 15)
-#define DM355_I2C_SCL_PIN GPIO_TO_PIN(0, 14)
-
-static struct gpiod_lookup_table i2c_recovery_gpiod_table = {
- .dev_id = "i2c_davinci.1",
- .table = {
- GPIO_LOOKUP("davinci_gpio", DM355_I2C_SDA_PIN, "sda",
- GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- GPIO_LOOKUP("davinci_gpio", DM355_I2C_SCL_PIN, "scl",
- GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- { }
- },
-};
-
-static struct davinci_i2c_platform_data i2c_pdata = {
- .bus_freq = 400 /* kHz */,
- .bus_delay = 0 /* usec */,
- .gpio_recovery = true,
-};
-
-static int dm355evm_mmc_gpios = -EINVAL;
-
-static void dm355evm_mmcsd_gpios(unsigned gpio)
-{
- gpio_request(gpio + 0, "mmc0_ro");
- gpio_request(gpio + 1, "mmc0_cd");
- gpio_request(gpio + 2, "mmc1_ro");
- gpio_request(gpio + 3, "mmc1_cd");
-
- /* we "know" these are input-only so we don't
- * need to call gpio_direction_input()
- */
-
- dm355evm_mmc_gpios = gpio;
-}
-
-static struct i2c_board_info dm355evm_i2c_info[] = {
- { I2C_BOARD_INFO("dm355evm_msp", 0x25),
- .platform_data = dm355evm_mmcsd_gpios,
- },
- /* { plus irq }, */
- { I2C_BOARD_INFO("tlv320aic33", 0x1b), },
-};
-
-static void __init evm_init_i2c(void)
-{
- gpiod_add_lookup_table(&i2c_recovery_gpiod_table);
- davinci_init_i2c(&i2c_pdata);
-
- gpio_request(5, "dm355evm_msp");
- gpio_direction_input(5);
- dm355evm_i2c_info[0].irq = gpio_to_irq(5);
-
- i2c_register_board_info(1, dm355evm_i2c_info,
- ARRAY_SIZE(dm355evm_i2c_info));
-}
-
-static struct resource dm355evm_dm9000_rsrc[] = {
- {
- /* addr */
- .start = 0x04014000,
- .end = 0x04014001,
- .flags = IORESOURCE_MEM,
- }, {
- /* data */
- .start = 0x04014002,
- .end = 0x04014003,
- .flags = IORESOURCE_MEM,
- }, {
- .flags = IORESOURCE_IRQ
- | IORESOURCE_IRQ_HIGHEDGE /* rising (active high) */,
- },
-};
-
-static struct dm9000_plat_data dm335evm_dm9000_platdata;
-
-static struct platform_device dm355evm_dm9000 = {
- .name = "dm9000",
- .id = -1,
- .resource = dm355evm_dm9000_rsrc,
- .num_resources = ARRAY_SIZE(dm355evm_dm9000_rsrc),
- .dev = {
- .platform_data = &dm335evm_dm9000_platdata,
- },
-};
-
-static struct tvp514x_platform_data tvp5146_pdata = {
- .clk_polarity = 0,
- .hs_polarity = 1,
- .vs_polarity = 1
-};
-
-#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
-/* Inputs available at the TVP5146 */
-static struct v4l2_input tvp5146_inputs[] = {
- {
- .index = 0,
- .name = "Composite",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = TVP514X_STD_ALL,
- },
- {
- .index = 1,
- .name = "S-Video",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = TVP514X_STD_ALL,
- },
-};
-
-/*
- * this is the route info for connecting each input to decoder
- * ouput that goes to vpfe. There is a one to one correspondence
- * with tvp5146_inputs
- */
-static struct vpfe_route tvp5146_routes[] = {
- {
- .input = INPUT_CVBS_VI2B,
- .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
- },
- {
- .input = INPUT_SVIDEO_VI2C_VI1C,
- .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
- },
-};
-
-static struct vpfe_subdev_info vpfe_sub_devs[] = {
- {
- .name = "tvp5146",
- .grp_id = 0,
- .num_inputs = ARRAY_SIZE(tvp5146_inputs),
- .inputs = tvp5146_inputs,
- .routes = tvp5146_routes,
- .can_route = 1,
- .ccdc_if_params = {
- .if_type = VPFE_BT656,
- .hdpol = VPFE_PINPOL_POSITIVE,
- .vdpol = VPFE_PINPOL_POSITIVE,
- },
- .board_info = {
- I2C_BOARD_INFO("tvp5146", 0x5d),
- .platform_data = &tvp5146_pdata,
- },
- }
-};
-
-static struct vpfe_config vpfe_cfg = {
- .num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
- .i2c_adapter_id = 1,
- .sub_devs = vpfe_sub_devs,
- .card_name = "DM355 EVM",
- .ccdc = "DM355 CCDC",
-};
-
-/* venc standards timings */
-static struct vpbe_enc_mode_info dm355evm_enc_preset_timing[] = {
- {
- .name = "ntsc",
- .timings_type = VPBE_ENC_STD,
- .std_id = V4L2_STD_NTSC,
- .interlaced = 1,
- .xres = 720,
- .yres = 480,
- .aspect = {11, 10},
- .fps = {30000, 1001},
- .left_margin = 0x79,
- .upper_margin = 0x10,
- },
- {
- .name = "pal",
- .timings_type = VPBE_ENC_STD,
- .std_id = V4L2_STD_PAL,
- .interlaced = 1,
- .xres = 720,
- .yres = 576,
- .aspect = {54, 59},
- .fps = {25, 1},
- .left_margin = 0x7E,
- .upper_margin = 0x16
- },
-};
-
-#define VENC_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
-
-/*
- * The outputs available from VPBE + ecnoders. Keep the
- * the order same as that of encoders. First those from venc followed by that
- * from encoders. Index in the output refers to index on a particular encoder.
- * Driver uses this index to pass it to encoder when it supports more than
- * one output. Application uses index of the array to set an output.
- */
-static struct vpbe_output dm355evm_vpbe_outputs[] = {
- {
- .output = {
- .index = 0,
- .name = "Composite",
- .type = V4L2_OUTPUT_TYPE_ANALOG,
- .std = VENC_STD_ALL,
- .capabilities = V4L2_OUT_CAP_STD,
- },
- .subdev_name = DM355_VPBE_VENC_SUBDEV_NAME,
- .default_mode = "ntsc",
- .num_modes = ARRAY_SIZE(dm355evm_enc_preset_timing),
- .modes = dm355evm_enc_preset_timing,
- .if_params = MEDIA_BUS_FMT_FIXED,
- },
-};
-
-static struct vpbe_config dm355evm_display_cfg = {
- .module_name = "dm355-vpbe-display",
- .i2c_adapter_id = 1,
- .osd = {
- .module_name = DM355_VPBE_OSD_SUBDEV_NAME,
- },
- .venc = {
- .module_name = DM355_VPBE_VENC_SUBDEV_NAME,
- },
- .num_outputs = ARRAY_SIZE(dm355evm_vpbe_outputs),
- .outputs = dm355evm_vpbe_outputs,
-};
-
-static struct platform_device *davinci_evm_devices[] __initdata = {
- &dm355evm_dm9000,
- &davinci_nand_device,
-};
-
-static void __init dm355_evm_map_io(void)
-{
- dm355_init();
-}
-
-static int dm355evm_mmc_get_cd(int module)
-{
- if (!gpio_is_valid(dm355evm_mmc_gpios))
- return -ENXIO;
- /* low == card present */
- return !gpio_get_value_cansleep(dm355evm_mmc_gpios + 2 * module + 1);
-}
-
-static int dm355evm_mmc_get_ro(int module)
-{
- if (!gpio_is_valid(dm355evm_mmc_gpios))
- return -ENXIO;
- /* high == card's write protect switch active */
- return gpio_get_value_cansleep(dm355evm_mmc_gpios + 2 * module + 0);
-}
-
-static struct davinci_mmc_config dm355evm_mmc_config = {
- .get_cd = dm355evm_mmc_get_cd,
- .get_ro = dm355evm_mmc_get_ro,
- .wires = 4,
- .max_freq = 50000000,
- .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
-};
-
-/* Don't connect anything to J10 unless you're only using USB host
- * mode *and* have to do so with some kind of gender-bender. If
- * you have proper Mini-B or Mini-A cables (or Mini-A adapters)
- * the ID pin won't need any help.
- */
-#define USB_ID_VALUE 1 /* ID pulled low */
-
-static struct spi_eeprom at25640a = {
- .byte_len = SZ_64K / 8,
- .name = "at25640a",
- .page_size = 32,
- .flags = EE_ADDR2,
-};
-
-static const struct spi_board_info dm355_evm_spi_info[] __initconst = {
- {
- .modalias = "at25",
- .platform_data = &at25640a,
- .max_speed_hz = 10 * 1000 * 1000, /* at 3v3 */
- .bus_num = 0,
- .chip_select = 0,
- .mode = SPI_MODE_0,
- },
-};
-
-static __init void dm355_evm_init(void)
-{
- struct clk *aemif;
- int ret;
-
- dm355_register_clocks();
-
- ret = dm355_gpio_register();
- if (ret)
- pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
-
- gpio_request(1, "dm9000");
- gpio_direction_input(1);
- dm355evm_dm9000_rsrc[2].start = gpio_to_irq(1);
-
- aemif = clk_get(&dm355evm_dm9000.dev, "aemif");
- if (!WARN(IS_ERR(aemif), "unable to get AEMIF clock\n"))
- clk_prepare_enable(aemif);
-
- platform_add_devices(davinci_evm_devices,
- ARRAY_SIZE(davinci_evm_devices));
- evm_init_i2c();
- davinci_serial_init(dm355_serial_device);
-
- /* NOTE: NAND flash timings set by the UBL are slower than
- * needed by MT29F16G08FAA chips ... EMIF.A1CR is 0x40400204
- * but could be 0x0400008c for about 25% faster page reads.
- */
-
- gpio_request(2, "usb_id_toggle");
- gpio_direction_output(2, USB_ID_VALUE);
- /* irlml6401 switches over 1A in under 8 msec */
- davinci_setup_usb(1000, 8);
-
- davinci_setup_mmc(0, &dm355evm_mmc_config);
- davinci_setup_mmc(1, &dm355evm_mmc_config);
-
- dm355_init_video(&vpfe_cfg, &dm355evm_display_cfg);
-
- dm355_init_spi0(BIT(0), dm355_evm_spi_info,
- ARRAY_SIZE(dm355_evm_spi_info));
-
- /* DM335 EVM uses ASP1; line-out is a stereo mini-jack */
- dm355_init_asp1(ASP1_TX_EVT_EN | ASP1_RX_EVT_EN);
-}
-
-MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM")
- .atag_offset = 0x100,
- .map_io = dm355_evm_map_io,
- .init_irq = dm355_init_irq,
- .init_time = dm355_init_time,
- .init_machine = dm355_evm_init,
- .init_late = davinci_init_late,
- .dma_zone_size = SZ_128M,
-MACHINE_END
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
deleted file mode 100644
index 32b9d607d025..000000000000
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ /dev/null
@@ -1,278 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * DM355 leopard board support
- *
- * Based on board-dm355-evm.c
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/err.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
-#include <linux/clk.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/eeprom.h>
-#include <linux/platform_data/i2c-davinci.h>
-#include <linux/platform_data/mmc-davinci.h>
-#include <linux/platform_data/mtd-davinci.h>
-#include <linux/platform_data/usb-davinci.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include "common.h"
-#include "serial.h"
-#include "davinci.h"
-
-/* NOTE: this is geared for the standard config, with a socketed
- * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
- * swap chips, maybe with a different block size, partitioning may
- * need to be changed.
- */
-#define NAND_BLOCK_SIZE SZ_128K
-
-static struct mtd_partition davinci_nand_partitions[] = {
- {
- /* UBL (a few copies) plus U-Boot */
- .name = "bootloader",
- .offset = 0,
- .size = 15 * NAND_BLOCK_SIZE,
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- }, {
- /* U-Boot environment */
- .name = "params",
- .offset = MTDPART_OFS_APPEND,
- .size = 1 * NAND_BLOCK_SIZE,
- .mask_flags = 0,
- }, {
- .name = "kernel",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_4M,
- .mask_flags = 0,
- }, {
- .name = "filesystem1",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_512M,
- .mask_flags = 0,
- }, {
- .name = "filesystem2",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- .mask_flags = 0,
- }
- /* two blocks with bad block table (and mirror) at the end */
-};
-
-static struct davinci_nand_pdata davinci_nand_data = {
- .core_chipsel = 0,
- .mask_chipsel = BIT(14),
- .parts = davinci_nand_partitions,
- .nr_parts = ARRAY_SIZE(davinci_nand_partitions),
- .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
- .ecc_placement = NAND_ECC_PLACEMENT_INTERLEAVED,
- .ecc_bits = 4,
- .bbt_options = NAND_BBT_USE_FLASH,
-};
-
-static struct resource davinci_nand_resources[] = {
- {
- .start = DM355_ASYNC_EMIF_DATA_CE0_BASE,
- .end = DM355_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = DM355_ASYNC_EMIF_CONTROL_BASE,
- .end = DM355_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device davinci_nand_device = {
- .name = "davinci_nand",
- .id = 0,
-
- .num_resources = ARRAY_SIZE(davinci_nand_resources),
- .resource = davinci_nand_resources,
-
- .dev = {
- .platform_data = &davinci_nand_data,
- },
-};
-
-static struct davinci_i2c_platform_data i2c_pdata = {
- .bus_freq = 400 /* kHz */,
- .bus_delay = 0 /* usec */,
-};
-
-static int leopard_mmc_gpio = -EINVAL;
-
-static void dm355leopard_mmcsd_gpios(unsigned gpio)
-{
- gpio_request(gpio + 0, "mmc0_ro");
- gpio_request(gpio + 1, "mmc0_cd");
- gpio_request(gpio + 2, "mmc1_ro");
- gpio_request(gpio + 3, "mmc1_cd");
-
- /* we "know" these are input-only so we don't
- * need to call gpio_direction_input()
- */
-
- leopard_mmc_gpio = gpio;
-}
-
-static struct i2c_board_info dm355leopard_i2c_info[] = {
- { I2C_BOARD_INFO("dm355leopard_msp", 0x25),
- .platform_data = dm355leopard_mmcsd_gpios,
- /* plus irq */ },
- /* { I2C_BOARD_INFO("tlv320aic3x", 0x1b), }, */
- /* { I2C_BOARD_INFO("tvp5146", 0x5d), }, */
-};
-
-static void __init leopard_init_i2c(void)
-{
- davinci_init_i2c(&i2c_pdata);
-
- gpio_request(5, "dm355leopard_msp");
- gpio_direction_input(5);
- dm355leopard_i2c_info[0].irq = gpio_to_irq(5);
-
- i2c_register_board_info(1, dm355leopard_i2c_info,
- ARRAY_SIZE(dm355leopard_i2c_info));
-}
-
-static struct resource dm355leopard_dm9000_rsrc[] = {
- {
- /* addr */
- .start = 0x04000000,
- .end = 0x04000001,
- .flags = IORESOURCE_MEM,
- }, {
- /* data */
- .start = 0x04000016,
- .end = 0x04000017,
- .flags = IORESOURCE_MEM,
- }, {
- .flags = IORESOURCE_IRQ
- | IORESOURCE_IRQ_HIGHEDGE /* rising (active high) */,
- },
-};
-
-static struct platform_device dm355leopard_dm9000 = {
- .name = "dm9000",
- .id = -1,
- .resource = dm355leopard_dm9000_rsrc,
- .num_resources = ARRAY_SIZE(dm355leopard_dm9000_rsrc),
-};
-
-static struct platform_device *davinci_leopard_devices[] __initdata = {
- &dm355leopard_dm9000,
- &davinci_nand_device,
-};
-
-static void __init dm355_leopard_map_io(void)
-{
- dm355_init();
-}
-
-static int dm355leopard_mmc_get_cd(int module)
-{
- if (!gpio_is_valid(leopard_mmc_gpio))
- return -ENXIO;
- /* low == card present */
- return !gpio_get_value_cansleep(leopard_mmc_gpio + 2 * module + 1);
-}
-
-static int dm355leopard_mmc_get_ro(int module)
-{
- if (!gpio_is_valid(leopard_mmc_gpio))
- return -ENXIO;
- /* high == card's write protect switch active */
- return gpio_get_value_cansleep(leopard_mmc_gpio + 2 * module + 0);
-}
-
-static struct davinci_mmc_config dm355leopard_mmc_config = {
- .get_cd = dm355leopard_mmc_get_cd,
- .get_ro = dm355leopard_mmc_get_ro,
- .wires = 4,
- .max_freq = 50000000,
- .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
-};
-
-/* Don't connect anything to J10 unless you're only using USB host
- * mode *and* have to do so with some kind of gender-bender. If
- * you have proper Mini-B or Mini-A cables (or Mini-A adapters)
- * the ID pin won't need any help.
- */
-#define USB_ID_VALUE 1 /* ID pulled low */
-
-static struct spi_eeprom at25640a = {
- .byte_len = SZ_64K / 8,
- .name = "at25640a",
- .page_size = 32,
- .flags = EE_ADDR2,
-};
-
-static const struct spi_board_info dm355_leopard_spi_info[] __initconst = {
- {
- .modalias = "at25",
- .platform_data = &at25640a,
- .max_speed_hz = 10 * 1000 * 1000, /* at 3v3 */
- .bus_num = 0,
- .chip_select = 0,
- .mode = SPI_MODE_0,
- },
-};
-
-static __init void dm355_leopard_init(void)
-{
- struct clk *aemif;
- int ret;
-
- dm355_register_clocks();
-
- ret = dm355_gpio_register();
- if (ret)
- pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
-
- gpio_request(9, "dm9000");
- gpio_direction_input(9);
- dm355leopard_dm9000_rsrc[2].start = gpio_to_irq(9);
-
- aemif = clk_get(&dm355leopard_dm9000.dev, "aemif");
- if (!WARN(IS_ERR(aemif), "unable to get AEMIF clock\n"))
- clk_prepare_enable(aemif);
-
- platform_add_devices(davinci_leopard_devices,
- ARRAY_SIZE(davinci_leopard_devices));
- leopard_init_i2c();
- davinci_serial_init(dm355_serial_device);
-
- /* NOTE: NAND flash timings set by the UBL are slower than
- * needed by MT29F16G08FAA chips ... EMIF.A1CR is 0x40400204
- * but could be 0x0400008c for about 25% faster page reads.
- */
-
- gpio_request(2, "usb_id_toggle");
- gpio_direction_output(2, USB_ID_VALUE);
- /* irlml6401 switches over 1A in under 8 msec */
- davinci_setup_usb(1000, 8);
-
- davinci_setup_mmc(0, &dm355leopard_mmc_config);
- davinci_setup_mmc(1, &dm355leopard_mmc_config);
-
- dm355_init_spi0(BIT(0), dm355_leopard_spi_info,
- ARRAY_SIZE(dm355_leopard_spi_info));
-}
-
-MACHINE_START(DM355_LEOPARD, "DaVinci DM355 leopard")
- .atag_offset = 0x100,
- .map_io = dm355_leopard_map_io,
- .init_irq = dm355_init_irq,
- .init_time = dm355_init_time,
- .init_machine = dm355_leopard_init,
- .init_late = davinci_init_late,
- .dma_zone_size = SZ_128M,
-MACHINE_END
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
deleted file mode 100644
index d8c6c360818b..000000000000
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ /dev/null
@@ -1,855 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * TI DaVinci DM365 EVM board support
- *
- * Copyright (C) 2009 Texas Instruments Incorporated
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/err.h>
-#include <linux/i2c.h>
-#include <linux/io.h>
-#include <linux/clk.h>
-#include <linux/property.h>
-#include <linux/leds.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/slab.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/nvmem-provider.h>
-#include <linux/input.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/eeprom.h>
-#include <linux/v4l2-dv-timings.h>
-#include <linux/platform_data/ti-aemif.h>
-#include <linux/regulator/fixed.h>
-#include <linux/regulator/machine.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include <linux/platform_data/i2c-davinci.h>
-#include <linux/platform_data/mmc-davinci.h>
-#include <linux/platform_data/mtd-davinci.h>
-#include <linux/platform_data/keyscan-davinci.h>
-
-#include <media/i2c/ths7303.h>
-#include <media/i2c/tvp514x.h>
-
-#include "mux.h"
-#include "common.h"
-#include "serial.h"
-#include "davinci.h"
-
-static inline int have_imager(void)
-{
- /* REVISIT when it's supported, trigger via Kconfig */
- return 0;
-}
-
-static inline int have_tvp7002(void)
-{
- /* REVISIT when it's supported, trigger via Kconfig */
- return 0;
-}
-
-#define DM365_EVM_PHY_ID "davinci_mdio-0:01"
-/*
- * A MAX-II CPLD is used for various board control functions.
- */
-#define CPLD_OFFSET(a13a8,a2a1) (((a13a8) << 10) + ((a2a1) << 3))
-
-#define CPLD_VERSION CPLD_OFFSET(0,0) /* r/o */
-#define CPLD_TEST CPLD_OFFSET(0,1)
-#define CPLD_LEDS CPLD_OFFSET(0,2)
-#define CPLD_MUX CPLD_OFFSET(0,3)
-#define CPLD_SWITCH CPLD_OFFSET(1,0) /* r/o */
-#define CPLD_POWER CPLD_OFFSET(1,1)
-#define CPLD_VIDEO CPLD_OFFSET(1,2)
-#define CPLD_CARDSTAT CPLD_OFFSET(1,3) /* r/o */
-
-#define CPLD_DILC_OUT CPLD_OFFSET(2,0)
-#define CPLD_DILC_IN CPLD_OFFSET(2,1) /* r/o */
-
-#define CPLD_IMG_DIR0 CPLD_OFFSET(2,2)
-#define CPLD_IMG_MUX0 CPLD_OFFSET(2,3)
-#define CPLD_IMG_MUX1 CPLD_OFFSET(3,0)
-#define CPLD_IMG_DIR1 CPLD_OFFSET(3,1)
-#define CPLD_IMG_MUX2 CPLD_OFFSET(3,2)
-#define CPLD_IMG_MUX3 CPLD_OFFSET(3,3)
-#define CPLD_IMG_DIR2 CPLD_OFFSET(4,0)
-#define CPLD_IMG_MUX4 CPLD_OFFSET(4,1)
-#define CPLD_IMG_MUX5 CPLD_OFFSET(4,2)
-
-#define CPLD_RESETS CPLD_OFFSET(4,3)
-
-#define CPLD_CCD_DIR1 CPLD_OFFSET(0x3e,0)
-#define CPLD_CCD_IO1 CPLD_OFFSET(0x3e,1)
-#define CPLD_CCD_DIR2 CPLD_OFFSET(0x3e,2)
-#define CPLD_CCD_IO2 CPLD_OFFSET(0x3e,3)
-#define CPLD_CCD_DIR3 CPLD_OFFSET(0x3f,0)
-#define CPLD_CCD_IO3 CPLD_OFFSET(0x3f,1)
-
-static void __iomem *cpld;
-
-
-/* NOTE: this is geared for the standard config, with a socketed
- * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
- * swap chips with a different block size, partitioning will
- * need to be changed. This NAND chip MT29F16G08FAA is the default
- * NAND shipped with the Spectrum Digital DM365 EVM
- */
-#define NAND_BLOCK_SIZE SZ_128K
-
-static struct mtd_partition davinci_nand_partitions[] = {
- {
- /* UBL (a few copies) plus U-Boot */
- .name = "bootloader",
- .offset = 0,
- .size = 30 * NAND_BLOCK_SIZE,
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- }, {
- /* U-Boot environment */
- .name = "params",
- .offset = MTDPART_OFS_APPEND,
- .size = 2 * NAND_BLOCK_SIZE,
- .mask_flags = 0,
- }, {
- .name = "kernel",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_4M,
- .mask_flags = 0,
- }, {
- .name = "filesystem1",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_512M,
- .mask_flags = 0,
- }, {
- .name = "filesystem2",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- .mask_flags = 0,
- }
- /* two blocks with bad block table (and mirror) at the end */
-};
-
-static struct davinci_nand_pdata davinci_nand_data = {
- .core_chipsel = 0,
- .mask_chipsel = BIT(14),
- .parts = davinci_nand_partitions,
- .nr_parts = ARRAY_SIZE(davinci_nand_partitions),
- .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
- .bbt_options = NAND_BBT_USE_FLASH,
- .ecc_bits = 4,
-};
-
-static struct resource davinci_nand_resources[] = {
- {
- .start = DM365_ASYNC_EMIF_DATA_CE0_BASE,
- .end = DM365_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = DM365_ASYNC_EMIF_CONTROL_BASE,
- .end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device davinci_aemif_devices[] = {
- {
- .name = "davinci_nand",
- .id = 0,
- .num_resources = ARRAY_SIZE(davinci_nand_resources),
- .resource = davinci_nand_resources,
- .dev = {
- .platform_data = &davinci_nand_data,
- },
- }
-};
-
-static struct resource davinci_aemif_resources[] = {
- {
- .start = DM365_ASYNC_EMIF_CONTROL_BASE,
- .end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct aemif_abus_data da850_evm_aemif_abus_data[] = {
- {
- .cs = 1,
- },
-};
-
-static struct aemif_platform_data davinci_aemif_pdata = {
- .abus_data = da850_evm_aemif_abus_data,
- .num_abus_data = ARRAY_SIZE(da850_evm_aemif_abus_data),
- .sub_devices = davinci_aemif_devices,
- .num_sub_devices = ARRAY_SIZE(davinci_aemif_devices),
-};
-
-static struct platform_device davinci_aemif_device = {
- .name = "ti-aemif",
- .id = -1,
- .dev = {
- .platform_data = &davinci_aemif_pdata,
- },
- .resource = davinci_aemif_resources,
- .num_resources = ARRAY_SIZE(davinci_aemif_resources),
-};
-
-static struct nvmem_cell_info davinci_nvmem_cells[] = {
- {
- .name = "macaddr",
- .offset = 0x7f00,
- .bytes = ETH_ALEN,
- }
-};
-
-static struct nvmem_cell_table davinci_nvmem_cell_table = {
- .nvmem_name = "1-00500",
- .cells = davinci_nvmem_cells,
- .ncells = ARRAY_SIZE(davinci_nvmem_cells),
-};
-
-static struct nvmem_cell_lookup davinci_nvmem_cell_lookup = {
- .nvmem_name = "1-00500",
- .cell_name = "macaddr",
- .dev_id = "davinci_emac.1",
- .con_id = "mac-address",
-};
-
-static const struct property_entry eeprom_properties[] = {
- PROPERTY_ENTRY_U32("pagesize", 64),
- { }
-};
-
-static const struct software_node eeprom_node = {
- .properties = eeprom_properties,
-};
-
-static struct i2c_board_info i2c_info[] = {
- {
- I2C_BOARD_INFO("24c256", 0x50),
- .swnode = &eeprom_node,
- },
- {
- I2C_BOARD_INFO("tlv320aic3x", 0x18),
- },
-};
-
-static struct davinci_i2c_platform_data i2c_pdata = {
- .bus_freq = 400 /* kHz */,
- .bus_delay = 0 /* usec */,
-};
-
-/* Fixed regulator support */
-static struct regulator_consumer_supply fixed_supplies_3_3v[] = {
- /* Baseboard 3.3V: 5V -> TPS767D301 -> 3.3V */
- REGULATOR_SUPPLY("AVDD", "1-0018"),
- REGULATOR_SUPPLY("DRVDD", "1-0018"),
- REGULATOR_SUPPLY("IOVDD", "1-0018"),
-};
-
-static struct regulator_consumer_supply fixed_supplies_1_8v[] = {
- /* Baseboard 1.8V: 5V -> TPS767D301 -> 1.8V */
- REGULATOR_SUPPLY("DVDD", "1-0018"),
-};
-
-static int dm365evm_keyscan_enable(struct device *dev)
-{
- return davinci_cfg_reg(DM365_KEYSCAN);
-}
-
-static unsigned short dm365evm_keymap[] = {
- KEY_KP2,
- KEY_LEFT,
- KEY_EXIT,
- KEY_DOWN,
- KEY_ENTER,
- KEY_UP,
- KEY_KP1,
- KEY_RIGHT,
- KEY_MENU,
- KEY_RECORD,
- KEY_REWIND,
- KEY_KPMINUS,
- KEY_STOP,
- KEY_FASTFORWARD,
- KEY_KPPLUS,
- KEY_PLAYPAUSE,
- 0
-};
-
-static struct davinci_ks_platform_data dm365evm_ks_data = {
- .device_enable = dm365evm_keyscan_enable,
- .keymap = dm365evm_keymap,
- .keymapsize = ARRAY_SIZE(dm365evm_keymap),
- .rep = 1,
- /* Scan period = strobe + interval */
- .strobe = 0x5,
- .interval = 0x2,
- .matrix_type = DAVINCI_KEYSCAN_MATRIX_4X4,
-};
-
-static int cpld_mmc_get_cd(int module)
-{
- if (!cpld)
- return -ENXIO;
-
- /* low == card present */
- return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0));
-}
-
-static int cpld_mmc_get_ro(int module)
-{
- if (!cpld)
- return -ENXIO;
-
- /* high == card's write protect switch active */
- return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1));
-}
-
-static struct davinci_mmc_config dm365evm_mmc_config = {
- .get_cd = cpld_mmc_get_cd,
- .get_ro = cpld_mmc_get_ro,
- .wires = 4,
- .max_freq = 50000000,
- .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
-};
-
-static void dm365evm_emac_configure(void)
-{
- /*
- * EMAC pins are multiplexed with GPIO and UART
- * Further details are available at the DM365 ARM
- * Subsystem Users Guide(sprufg5.pdf) pages 125 - 127
- */
- davinci_cfg_reg(DM365_EMAC_TX_EN);
- davinci_cfg_reg(DM365_EMAC_TX_CLK);
- davinci_cfg_reg(DM365_EMAC_COL);
- davinci_cfg_reg(DM365_EMAC_TXD3);
- davinci_cfg_reg(DM365_EMAC_TXD2);
- davinci_cfg_reg(DM365_EMAC_TXD1);
- davinci_cfg_reg(DM365_EMAC_TXD0);
- davinci_cfg_reg(DM365_EMAC_RXD3);
- davinci_cfg_reg(DM365_EMAC_RXD2);
- davinci_cfg_reg(DM365_EMAC_RXD1);
- davinci_cfg_reg(DM365_EMAC_RXD0);
- davinci_cfg_reg(DM365_EMAC_RX_CLK);
- davinci_cfg_reg(DM365_EMAC_RX_DV);
- davinci_cfg_reg(DM365_EMAC_RX_ER);
- davinci_cfg_reg(DM365_EMAC_CRS);
- davinci_cfg_reg(DM365_EMAC_MDIO);
- davinci_cfg_reg(DM365_EMAC_MDCLK);
-
- /*
- * EMAC interrupts are multiplexed with GPIO interrupts
- * Details are available at the DM365 ARM
- * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134
- */
- davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH);
- davinci_cfg_reg(DM365_INT_EMAC_RXPULSE);
- davinci_cfg_reg(DM365_INT_EMAC_TXPULSE);
- davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE);
-}
-
-static void dm365evm_mmc_configure(void)
-{
- /*
- * MMC/SD pins are multiplexed with GPIO and EMIF
- * Further details are available at the DM365 ARM
- * Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131
- */
- davinci_cfg_reg(DM365_SD1_CLK);
- davinci_cfg_reg(DM365_SD1_CMD);
- davinci_cfg_reg(DM365_SD1_DATA3);
- davinci_cfg_reg(DM365_SD1_DATA2);
- davinci_cfg_reg(DM365_SD1_DATA1);
- davinci_cfg_reg(DM365_SD1_DATA0);
-}
-
-static struct tvp514x_platform_data tvp5146_pdata = {
- .clk_polarity = 0,
- .hs_polarity = 1,
- .vs_polarity = 1
-};
-
-#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
-/* Inputs available at the TVP5146 */
-static struct v4l2_input tvp5146_inputs[] = {
- {
- .index = 0,
- .name = "Composite",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = TVP514X_STD_ALL,
- },
- {
- .index = 1,
- .name = "S-Video",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = TVP514X_STD_ALL,
- },
-};
-
-/*
- * this is the route info for connecting each input to decoder
- * ouput that goes to vpfe. There is a one to one correspondence
- * with tvp5146_inputs
- */
-static struct vpfe_route tvp5146_routes[] = {
- {
- .input = INPUT_CVBS_VI2B,
- .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
- },
-{
- .input = INPUT_SVIDEO_VI2C_VI1C,
- .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
- },
-};
-
-static struct vpfe_subdev_info vpfe_sub_devs[] = {
- {
- .name = "tvp5146",
- .grp_id = 0,
- .num_inputs = ARRAY_SIZE(tvp5146_inputs),
- .inputs = tvp5146_inputs,
- .routes = tvp5146_routes,
- .can_route = 1,
- .ccdc_if_params = {
- .if_type = VPFE_BT656,
- .hdpol = VPFE_PINPOL_POSITIVE,
- .vdpol = VPFE_PINPOL_POSITIVE,
- },
- .board_info = {
- I2C_BOARD_INFO("tvp5146", 0x5d),
- .platform_data = &tvp5146_pdata,
- },
- },
-};
-
-static struct vpfe_config vpfe_cfg = {
- .num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
- .sub_devs = vpfe_sub_devs,
- .i2c_adapter_id = 1,
- .card_name = "DM365 EVM",
- .ccdc = "ISIF",
-};
-
-/* venc standards timings */
-static struct vpbe_enc_mode_info dm365evm_enc_std_timing[] = {
- {
- .name = "ntsc",
- .timings_type = VPBE_ENC_STD,
- .std_id = V4L2_STD_NTSC,
- .interlaced = 1,
- .xres = 720,
- .yres = 480,
- .aspect = {11, 10},
- .fps = {30000, 1001},
- .left_margin = 0x79,
- .upper_margin = 0x10,
- },
- {
- .name = "pal",
- .timings_type = VPBE_ENC_STD,
- .std_id = V4L2_STD_PAL,
- .interlaced = 1,
- .xres = 720,
- .yres = 576,
- .aspect = {54, 59},
- .fps = {25, 1},
- .left_margin = 0x7E,
- .upper_margin = 0x16,
- },
-};
-
-/* venc dv timings */
-static struct vpbe_enc_mode_info dm365evm_enc_preset_timing[] = {
- {
- .name = "480p59_94",
- .timings_type = VPBE_ENC_DV_TIMINGS,
- .dv_timings = V4L2_DV_BT_CEA_720X480P59_94,
- .interlaced = 0,
- .xres = 720,
- .yres = 480,
- .aspect = {1, 1},
- .fps = {5994, 100},
- .left_margin = 0x8F,
- .upper_margin = 0x2D,
- },
- {
- .name = "576p50",
- .timings_type = VPBE_ENC_DV_TIMINGS,
- .dv_timings = V4L2_DV_BT_CEA_720X576P50,
- .interlaced = 0,
- .xres = 720,
- .yres = 576,
- .aspect = {1, 1},
- .fps = {50, 1},
- .left_margin = 0x8C,
- .upper_margin = 0x36,
- },
- {
- .name = "720p60",
- .timings_type = VPBE_ENC_DV_TIMINGS,
- .dv_timings = V4L2_DV_BT_CEA_1280X720P60,
- .interlaced = 0,
- .xres = 1280,
- .yres = 720,
- .aspect = {1, 1},
- .fps = {60, 1},
- .left_margin = 0x117,
- .right_margin = 70,
- .upper_margin = 38,
- .lower_margin = 3,
- .hsync_len = 80,
- .vsync_len = 5,
- },
- {
- .name = "1080i60",
- .timings_type = VPBE_ENC_DV_TIMINGS,
- .dv_timings = V4L2_DV_BT_CEA_1920X1080I60,
- .interlaced = 1,
- .xres = 1920,
- .yres = 1080,
- .aspect = {1, 1},
- .fps = {30, 1},
- .left_margin = 0xc9,
- .right_margin = 80,
- .upper_margin = 30,
- .lower_margin = 3,
- .hsync_len = 88,
- .vsync_len = 5,
- },
-};
-
-#define VENC_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
-
-/*
- * The outputs available from VPBE + ecnoders. Keep the
- * the order same as that of encoders. First those from venc followed by that
- * from encoders. Index in the output refers to index on a particular
- * encoder.Driver uses this index to pass it to encoder when it supports more
- * than one output. Application uses index of the array to set an output.
- */
-static struct vpbe_output dm365evm_vpbe_outputs[] = {
- {
- .output = {
- .index = 0,
- .name = "Composite",
- .type = V4L2_OUTPUT_TYPE_ANALOG,
- .std = VENC_STD_ALL,
- .capabilities = V4L2_OUT_CAP_STD,
- },
- .subdev_name = DM365_VPBE_VENC_SUBDEV_NAME,
- .default_mode = "ntsc",
- .num_modes = ARRAY_SIZE(dm365evm_enc_std_timing),
- .modes = dm365evm_enc_std_timing,
- .if_params = MEDIA_BUS_FMT_FIXED,
- },
- {
- .output = {
- .index = 1,
- .name = "Component",
- .type = V4L2_OUTPUT_TYPE_ANALOG,
- .capabilities = V4L2_OUT_CAP_DV_TIMINGS,
- },
- .subdev_name = DM365_VPBE_VENC_SUBDEV_NAME,
- .default_mode = "480p59_94",
- .num_modes = ARRAY_SIZE(dm365evm_enc_preset_timing),
- .modes = dm365evm_enc_preset_timing,
- .if_params = MEDIA_BUS_FMT_FIXED,
- },
-};
-
-/*
- * Amplifiers on the board
- */
-static struct ths7303_platform_data ths7303_pdata = {
- .ch_1 = 3,
- .ch_2 = 3,
- .ch_3 = 3,
-};
-
-static struct amp_config_info vpbe_amp = {
- .module_name = "ths7303",
- .is_i2c = 1,
- .board_info = {
- I2C_BOARD_INFO("ths7303", 0x2c),
- .platform_data = &ths7303_pdata,
- }
-};
-
-static struct vpbe_config dm365evm_display_cfg = {
- .module_name = "dm365-vpbe-display",
- .i2c_adapter_id = 1,
- .amp = &vpbe_amp,
- .osd = {
- .module_name = DM365_VPBE_OSD_SUBDEV_NAME,
- },
- .venc = {
- .module_name = DM365_VPBE_VENC_SUBDEV_NAME,
- },
- .num_outputs = ARRAY_SIZE(dm365evm_vpbe_outputs),
- .outputs = dm365evm_vpbe_outputs,
-};
-
-static void __init evm_init_i2c(void)
-{
- davinci_init_i2c(&i2c_pdata);
- i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
-}
-
-static inline int have_leds(void)
-{
-#ifdef CONFIG_LEDS_CLASS
- return 1;
-#else
- return 0;
-#endif
-}
-
-struct cpld_led {
- struct led_classdev cdev;
- u8 mask;
-};
-
-static const struct {
- const char *name;
- const char *trigger;
-} cpld_leds[] = {
- { "dm365evm::ds2", },
- { "dm365evm::ds3", },
- { "dm365evm::ds4", },
- { "dm365evm::ds5", },
- { "dm365evm::ds6", "nand-disk", },
- { "dm365evm::ds7", "mmc1", },
- { "dm365evm::ds8", "mmc0", },
- { "dm365evm::ds9", "heartbeat", },
-};
-
-static void cpld_led_set(struct led_classdev *cdev, enum led_brightness b)
-{
- struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
- u8 reg = __raw_readb(cpld + CPLD_LEDS);
-
- if (b != LED_OFF)
- reg &= ~led->mask;
- else
- reg |= led->mask;
- __raw_writeb(reg, cpld + CPLD_LEDS);
-}
-
-static enum led_brightness cpld_led_get(struct led_classdev *cdev)
-{
- struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
- u8 reg = __raw_readb(cpld + CPLD_LEDS);
-
- return (reg & led->mask) ? LED_OFF : LED_FULL;
-}
-
-static int __init cpld_leds_init(void)
-{
- int i;
-
- if (!have_leds() || !cpld)
- return 0;
-
- /* setup LEDs */
- __raw_writeb(0xff, cpld + CPLD_LEDS);
- for (i = 0; i < ARRAY_SIZE(cpld_leds); i++) {
- struct cpld_led *led;
-
- led = kzalloc(sizeof(*led), GFP_KERNEL);
- if (!led)
- break;
-
- led->cdev.name = cpld_leds[i].name;
- led->cdev.brightness_set = cpld_led_set;
- led->cdev.brightness_get = cpld_led_get;
- led->cdev.default_trigger = cpld_leds[i].trigger;
- led->mask = BIT(i);
-
- if (led_classdev_register(NULL, &led->cdev) < 0) {
- kfree(led);
- break;
- }
- }
-
- return 0;
-}
-/* run after subsys_initcall() for LEDs */
-fs_initcall(cpld_leds_init);
-
-
-static void __init evm_init_cpld(void)
-{
- u8 mux, resets;
- const char *label;
- struct clk *aemif_clk;
- int rc;
-
- /* Make sure we can configure the CPLD through CS1. Then
- * leave it on for later access to MMC and LED registers.
- */
- aemif_clk = clk_get(NULL, "aemif");
- if (IS_ERR(aemif_clk))
- return;
- clk_prepare_enable(aemif_clk);
-
- if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE,
- "cpld") == NULL)
- goto fail;
- cpld = ioremap(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE);
- if (!cpld) {
- release_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE,
- SECTION_SIZE);
-fail:
- pr_err("ERROR: can't map CPLD\n");
- clk_disable_unprepare(aemif_clk);
- return;
- }
-
- /* External muxing for some signals */
- mux = 0;
-
- /* Read SW5 to set up NAND + keypad _or_ OneNAND (sync read).
- * NOTE: SW4 bus width setting must match!
- */
- if ((__raw_readb(cpld + CPLD_SWITCH) & BIT(5)) == 0) {
- /* external keypad mux */
- mux |= BIT(7);
-
- rc = platform_device_register(&davinci_aemif_device);
- if (rc)
- pr_warn("%s(): error registering the aemif device: %d\n",
- __func__, rc);
- } else {
- /* no OneNAND support yet */
- }
-
- /* Leave external chips in reset when unused. */
- resets = BIT(3) | BIT(2) | BIT(1) | BIT(0);
-
- /* Static video input config with SN74CBT16214 1-of-3 mux:
- * - port b1 == tvp7002 (mux lowbits == 1 or 6)
- * - port b2 == imager (mux lowbits == 2 or 7)
- * - port b3 == tvp5146 (mux lowbits == 5)
- *
- * Runtime switching could work too, with limitations.
- */
- if (have_imager()) {
- label = "HD imager";
- mux |= 2;
-
- /* externally mux MMC1/ENET/AIC33 to imager */
- mux |= BIT(6) | BIT(5) | BIT(3);
- } else {
- struct davinci_soc_info *soc_info = &davinci_soc_info;
-
- /* we can use MMC1 ... */
- dm365evm_mmc_configure();
- davinci_setup_mmc(1, &dm365evm_mmc_config);
-
- /* ... and ENET ... */
- dm365evm_emac_configure();
- soc_info->emac_pdata->phy_id = DM365_EVM_PHY_ID;
- resets &= ~BIT(3);
-
- /* ... and AIC33 */
- resets &= ~BIT(1);
-
- if (have_tvp7002()) {
- mux |= 1;
- resets &= ~BIT(2);
- label = "tvp7002 HD";
- } else {
- /* default to tvp5146 */
- mux |= 5;
- resets &= ~BIT(0);
- label = "tvp5146 SD";
- }
- }
- __raw_writeb(mux, cpld + CPLD_MUX);
- __raw_writeb(resets, cpld + CPLD_RESETS);
- pr_info("EVM: %s video input\n", label);
-
- /* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */
-}
-
-static void __init dm365_evm_map_io(void)
-{
- dm365_init();
-}
-
-static struct spi_eeprom at25640 = {
- .byte_len = SZ_64K / 8,
- .name = "at25640",
- .page_size = 32,
- .flags = EE_ADDR2,
-};
-
-static const struct spi_board_info dm365_evm_spi_info[] __initconst = {
- {
- .modalias = "at25",
- .platform_data = &at25640,
- .max_speed_hz = 10 * 1000 * 1000,
- .bus_num = 0,
- .chip_select = 0,
- .mode = SPI_MODE_0,
- },
-};
-
-static __init void dm365_evm_init(void)
-{
- int ret;
-
- dm365_register_clocks();
-
- ret = dm365_gpio_register();
- if (ret)
- pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
-
- regulator_register_always_on(0, "fixed-dummy", fixed_supplies_1_8v,
- ARRAY_SIZE(fixed_supplies_1_8v), 1800000);
- regulator_register_always_on(1, "fixed-dummy", fixed_supplies_3_3v,
- ARRAY_SIZE(fixed_supplies_3_3v), 3300000);
-
- nvmem_add_cell_table(&davinci_nvmem_cell_table);
- nvmem_add_cell_lookups(&davinci_nvmem_cell_lookup, 1);
-
- evm_init_i2c();
- davinci_serial_init(dm365_serial_device);
-
- dm365evm_emac_configure();
- dm365evm_mmc_configure();
-
- davinci_setup_mmc(0, &dm365evm_mmc_config);
-
- dm365_init_video(&vpfe_cfg, &dm365evm_display_cfg);
-
- /* maybe setup mmc1/etc ... _after_ mmc0 */
- evm_init_cpld();
-
-#ifdef CONFIG_SND_SOC_DM365_AIC3X_CODEC
- dm365_init_asp();
-#elif defined(CONFIG_SND_SOC_DM365_VOICE_CODEC)
- dm365_init_vc();
-#endif
- dm365_init_rtc();
- dm365_init_ks(&dm365evm_ks_data);
-
- dm365_init_spi0(BIT(0), dm365_evm_spi_info,
- ARRAY_SIZE(dm365_evm_spi_info));
-}
-
-MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
- .atag_offset = 0x100,
- .map_io = dm365_evm_map_io,
- .init_irq = dm365_init_irq,
- .init_time = dm365_init_time,
- .init_machine = dm365_evm_init,
- .init_late = davinci_init_late,
- .dma_zone_size = SZ_128M,
-MACHINE_END
diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c
deleted file mode 100644
index a46e7b9ff8e0..000000000000
--- a/arch/arm/mach-davinci/board-mityomapl138.c
+++ /dev/null
@@ -1,638 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Critical Link MityOMAP-L138 SoM
- *
- * Copyright (C) 2010 Critical Link LLC - https://www.criticallink.com
- */
-
-#define pr_fmt(fmt) "MityOMAPL138: " fmt
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/console.h>
-#include <linux/platform_device.h>
-#include <linux/property.h>
-#include <linux/mtd/partitions.h>
-#include <linux/notifier.h>
-#include <linux/nvmem-consumer.h>
-#include <linux/nvmem-provider.h>
-#include <linux/regulator/machine.h>
-#include <linux/i2c.h>
-#include <linux/etherdevice.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-
-#include <asm/io.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include "common.h"
-#include "da8xx.h"
-#include "mux.h"
-
-#include <linux/platform_data/mtd-davinci.h>
-#include <linux/platform_data/mtd-davinci-aemif.h>
-#include <linux/platform_data/ti-aemif.h>
-#include <linux/platform_data/spi-davinci.h>
-
-#define MITYOMAPL138_PHY_ID ""
-
-#define FACTORY_CONFIG_MAGIC 0x012C0138
-#define FACTORY_CONFIG_VERSION 0x00010001
-
-/* Data Held in On-Board I2C device */
-struct factory_config {
- u32 magic;
- u32 version;
- u8 mac[6];
- u32 fpga_type;
- u32 spare;
- u32 serialnumber;
- char partnum[32];
-};
-
-static struct factory_config factory_config;
-
-#ifdef CONFIG_CPU_FREQ
-struct part_no_info {
- const char *part_no; /* part number string of interest */
- int max_freq; /* khz */
-};
-
-static struct part_no_info mityomapl138_pn_info[] = {
- {
- .part_no = "L138-C",
- .max_freq = 300000,
- },
- {
- .part_no = "L138-D",
- .max_freq = 375000,
- },
- {
- .part_no = "L138-F",
- .max_freq = 456000,
- },
- {
- .part_no = "1808-C",
- .max_freq = 300000,
- },
- {
- .part_no = "1808-D",
- .max_freq = 375000,
- },
- {
- .part_no = "1808-F",
- .max_freq = 456000,
- },
- {
- .part_no = "1810-D",
- .max_freq = 375000,
- },
-};
-
-static void mityomapl138_cpufreq_init(const char *partnum)
-{
- int i, ret;
-
- for (i = 0; partnum && i < ARRAY_SIZE(mityomapl138_pn_info); i++) {
- /*
- * the part number has additional characters beyond what is
- * stored in the table. This information is not needed for
- * determining the speed grade, and would require several
- * more table entries. Only check the first N characters
- * for a match.
- */
- if (!strncmp(partnum, mityomapl138_pn_info[i].part_no,
- strlen(mityomapl138_pn_info[i].part_no))) {
- da850_max_speed = mityomapl138_pn_info[i].max_freq;
- break;
- }
- }
-
- ret = da850_register_cpufreq("pll0_sysclk3");
- if (ret)
- pr_warn("cpufreq registration failed: %d\n", ret);
-}
-#else
-static void mityomapl138_cpufreq_init(const char *partnum) { }
-#endif
-
-static int read_factory_config(struct notifier_block *nb,
- unsigned long event, void *data)
-{
- int ret;
- const char *partnum = NULL;
- struct nvmem_device *nvmem = data;
-
- if (strcmp(nvmem_dev_name(nvmem), "1-00500") != 0)
- return NOTIFY_DONE;
-
- if (!IS_BUILTIN(CONFIG_NVMEM)) {
- pr_warn("Factory Config not available without CONFIG_NVMEM\n");
- goto bad_config;
- }
-
- ret = nvmem_device_read(nvmem, 0, sizeof(factory_config),
- &factory_config);
- if (ret != sizeof(struct factory_config)) {
- pr_warn("Read Factory Config Failed: %d\n", ret);
- goto bad_config;
- }
-
- if (factory_config.magic != FACTORY_CONFIG_MAGIC) {
- pr_warn("Factory Config Magic Wrong (%X)\n",
- factory_config.magic);
- goto bad_config;
- }
-
- if (factory_config.version != FACTORY_CONFIG_VERSION) {
- pr_warn("Factory Config Version Wrong (%X)\n",
- factory_config.version);
- goto bad_config;
- }
-
- partnum = factory_config.partnum;
- pr_info("Part Number = %s\n", partnum);
-
-bad_config:
- /* default maximum speed is valid for all platforms */
- mityomapl138_cpufreq_init(partnum);
-
- return NOTIFY_STOP;
-}
-
-static struct notifier_block mityomapl138_nvmem_notifier = {
- .notifier_call = read_factory_config,
-};
-
-/*
- * We don't define a cell for factory config as it will be accessed from the
- * board file using the nvmem notifier chain.
- */
-static struct nvmem_cell_info mityomapl138_nvmem_cells[] = {
- {
- .name = "macaddr",
- .offset = 0x64,
- .bytes = ETH_ALEN,
- }
-};
-
-static struct nvmem_cell_table mityomapl138_nvmem_cell_table = {
- .nvmem_name = "1-00500",
- .cells = mityomapl138_nvmem_cells,
- .ncells = ARRAY_SIZE(mityomapl138_nvmem_cells),
-};
-
-static struct nvmem_cell_lookup mityomapl138_nvmem_cell_lookup = {
- .nvmem_name = "1-00500",
- .cell_name = "macaddr",
- .dev_id = "davinci_emac.1",
- .con_id = "mac-address",
-};
-
-static const struct property_entry mityomapl138_fd_chip_properties[] = {
- PROPERTY_ENTRY_U32("pagesize", 8),
- PROPERTY_ENTRY_BOOL("read-only"),
- { }
-};
-
-static const struct software_node mityomapl138_fd_chip_node = {
- .properties = mityomapl138_fd_chip_properties,
-};
-
-static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = {
- .bus_freq = 100, /* kHz */
- .bus_delay = 0, /* usec */
-};
-
-/* TPS65023 voltage regulator support */
-/* 1.2V Core */
-static struct regulator_consumer_supply tps65023_dcdc1_consumers[] = {
- {
- .supply = "cvdd",
- },
-};
-
-/* 1.8V */
-static struct regulator_consumer_supply tps65023_dcdc2_consumers[] = {
- {
- .supply = "usb0_vdda18",
- },
- {
- .supply = "usb1_vdda18",
- },
- {
- .supply = "ddr_dvdd18",
- },
- {
- .supply = "sata_vddr",
- },
-};
-
-/* 1.2V */
-static struct regulator_consumer_supply tps65023_dcdc3_consumers[] = {
- {
- .supply = "sata_vdd",
- },
- {
- .supply = "usb_cvdd",
- },
- {
- .supply = "pll0_vdda",
- },
- {
- .supply = "pll1_vdda",
- },
-};
-
-/* 1.8V Aux LDO, not used */
-static struct regulator_consumer_supply tps65023_ldo1_consumers[] = {
- {
- .supply = "1.8v_aux",
- },
-};
-
-/* FPGA VCC Aux (2.5 or 3.3) LDO */
-static struct regulator_consumer_supply tps65023_ldo2_consumers[] = {
- {
- .supply = "vccaux",
- },
-};
-
-static struct regulator_init_data tps65023_regulator_data[] = {
- /* dcdc1 */
- {
- .constraints = {
- .min_uV = 1150000,
- .max_uV = 1350000,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
- REGULATOR_CHANGE_STATUS,
- .boot_on = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers),
- .consumer_supplies = tps65023_dcdc1_consumers,
- },
- /* dcdc2 */
- {
- .constraints = {
- .min_uV = 1800000,
- .max_uV = 1800000,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- .boot_on = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers),
- .consumer_supplies = tps65023_dcdc2_consumers,
- },
- /* dcdc3 */
- {
- .constraints = {
- .min_uV = 1200000,
- .max_uV = 1200000,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- .boot_on = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers),
- .consumer_supplies = tps65023_dcdc3_consumers,
- },
- /* ldo1 */
- {
- .constraints = {
- .min_uV = 1800000,
- .max_uV = 1800000,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- .boot_on = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers),
- .consumer_supplies = tps65023_ldo1_consumers,
- },
- /* ldo2 */
- {
- .constraints = {
- .min_uV = 2500000,
- .max_uV = 3300000,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
- REGULATOR_CHANGE_STATUS,
- .boot_on = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers),
- .consumer_supplies = tps65023_ldo2_consumers,
- },
-};
-
-static struct i2c_board_info __initdata mityomap_tps65023_info[] = {
- {
- I2C_BOARD_INFO("tps65023", 0x48),
- .platform_data = &tps65023_regulator_data[0],
- },
- {
- I2C_BOARD_INFO("24c02", 0x50),
- .swnode = &mityomapl138_fd_chip_node,
- },
-};
-
-static int __init pmic_tps65023_init(void)
-{
- return i2c_register_board_info(1, mityomap_tps65023_info,
- ARRAY_SIZE(mityomap_tps65023_info));
-}
-
-/*
- * SPI Devices:
- * SPI1_CS0: 8M Flash ST-M25P64-VME6G
- */
-static struct mtd_partition spi_flash_partitions[] = {
- [0] = {
- .name = "ubl",
- .offset = 0,
- .size = SZ_64K,
- .mask_flags = MTD_WRITEABLE,
- },
- [1] = {
- .name = "u-boot",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_512K,
- .mask_flags = MTD_WRITEABLE,
- },
- [2] = {
- .name = "u-boot-env",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_64K,
- .mask_flags = MTD_WRITEABLE,
- },
- [3] = {
- .name = "periph-config",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_64K,
- .mask_flags = MTD_WRITEABLE,
- },
- [4] = {
- .name = "reserved",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_256K + SZ_64K,
- },
- [5] = {
- .name = "kernel",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_2M + SZ_1M,
- },
- [6] = {
- .name = "fpga",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_2M,
- },
- [7] = {
- .name = "spare",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct flash_platform_data mityomapl138_spi_flash_data = {
- .name = "m25p80",
- .parts = spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(spi_flash_partitions),
- .type = "m24p64",
-};
-
-static struct davinci_spi_config spi_eprom_config = {
- .io_type = SPI_IO_TYPE_DMA,
- .c2tdelay = 8,
- .t2cdelay = 8,
-};
-
-static struct spi_board_info mityomapl138_spi_flash_info[] = {
- {
- .modalias = "m25p80",
- .platform_data = &mityomapl138_spi_flash_data,
- .controller_data = &spi_eprom_config,
- .mode = SPI_MODE_0,
- .max_speed_hz = 30000000,
- .bus_num = 1,
- .chip_select = 0,
- },
-};
-
-/*
- * MityDSP-L138 includes a 256 MByte large-page NAND flash
- * (128K blocks).
- */
-static struct mtd_partition mityomapl138_nandflash_partition[] = {
- {
- .name = "rootfs",
- .offset = 0,
- .size = SZ_128M,
- .mask_flags = 0, /* MTD_WRITEABLE, */
- },
- {
- .name = "homefs",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- .mask_flags = 0,
- },
-};
-
-static struct davinci_nand_pdata mityomapl138_nandflash_data = {
- .core_chipsel = 1,
- .parts = mityomapl138_nandflash_partition,
- .nr_parts = ARRAY_SIZE(mityomapl138_nandflash_partition),
- .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
- .bbt_options = NAND_BBT_USE_FLASH,
- .options = NAND_BUSWIDTH_16,
- .ecc_bits = 1, /* 4 bit mode is not supported with 16 bit NAND */
-};
-
-static struct resource mityomapl138_nandflash_resource[] = {
- {
- .start = DA8XX_AEMIF_CS3_BASE,
- .end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DA8XX_AEMIF_CTL_BASE,
- .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device mityomapl138_aemif_devices[] = {
- {
- .name = "davinci_nand",
- .id = 1,
- .dev = {
- .platform_data = &mityomapl138_nandflash_data,
- },
- .num_resources = ARRAY_SIZE(mityomapl138_nandflash_resource),
- .resource = mityomapl138_nandflash_resource,
- },
-};
-
-static struct resource mityomapl138_aemif_resources[] = {
- {
- .start = DA8XX_AEMIF_CTL_BASE,
- .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct aemif_abus_data mityomapl138_aemif_abus_data[] = {
- {
- .cs = 1,
- },
-};
-
-static struct aemif_platform_data mityomapl138_aemif_pdata = {
- .abus_data = mityomapl138_aemif_abus_data,
- .num_abus_data = ARRAY_SIZE(mityomapl138_aemif_abus_data),
- .sub_devices = mityomapl138_aemif_devices,
- .num_sub_devices = ARRAY_SIZE(mityomapl138_aemif_devices),
-};
-
-static struct platform_device mityomapl138_aemif_device = {
- .name = "ti-aemif",
- .id = -1,
- .dev = {
- .platform_data = &mityomapl138_aemif_pdata,
- },
- .resource = mityomapl138_aemif_resources,
- .num_resources = ARRAY_SIZE(mityomapl138_aemif_resources),
-};
-
-static void __init mityomapl138_setup_nand(void)
-{
- if (platform_device_register(&mityomapl138_aemif_device))
- pr_warn("%s: Cannot register AEMIF device\n", __func__);
-}
-
-static const short mityomap_mii_pins[] = {
- DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
- DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
- DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
- DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
- DA850_MDIO_D,
- -1
-};
-
-static const short mityomap_rmii_pins[] = {
- DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
- DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
- DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
- DA850_MDIO_D,
- -1
-};
-
-static void __init mityomapl138_config_emac(void)
-{
- void __iomem *cfg_chip3_base;
- int ret;
- u32 val;
- struct davinci_soc_info *soc_info = &davinci_soc_info;
-
- soc_info->emac_pdata->rmii_en = 0; /* hardcoded for now */
-
- cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
- val = __raw_readl(cfg_chip3_base);
-
- if (soc_info->emac_pdata->rmii_en) {
- val |= BIT(8);
- ret = davinci_cfg_reg_list(mityomap_rmii_pins);
- pr_info("RMII PHY configured\n");
- } else {
- val &= ~BIT(8);
- ret = davinci_cfg_reg_list(mityomap_mii_pins);
- pr_info("MII PHY configured\n");
- }
-
- if (ret) {
- pr_warn("mii/rmii mux setup failed: %d\n", ret);
- return;
- }
-
- /* configure the CFGCHIP3 register for RMII or MII */
- __raw_writel(val, cfg_chip3_base);
-
- soc_info->emac_pdata->phy_id = MITYOMAPL138_PHY_ID;
-
- ret = da8xx_register_emac();
- if (ret)
- pr_warn("emac registration failed: %d\n", ret);
-}
-
-static void __init mityomapl138_init(void)
-{
- int ret;
-
- da850_register_clocks();
-
- /* for now, no special EDMA channels are reserved */
- ret = da850_register_edma(NULL);
- if (ret)
- pr_warn("edma registration failed: %d\n", ret);
-
- ret = da8xx_register_watchdog();
- if (ret)
- pr_warn("watchdog registration failed: %d\n", ret);
-
- davinci_serial_init(da8xx_serial_device);
-
- nvmem_register_notifier(&mityomapl138_nvmem_notifier);
- nvmem_add_cell_table(&mityomapl138_nvmem_cell_table);
- nvmem_add_cell_lookups(&mityomapl138_nvmem_cell_lookup, 1);
-
- ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
- if (ret)
- pr_warn("i2c0 registration failed: %d\n", ret);
-
- ret = pmic_tps65023_init();
- if (ret)
- pr_warn("TPS65023 PMIC init failed: %d\n", ret);
-
- mityomapl138_setup_nand();
-
- ret = spi_register_board_info(mityomapl138_spi_flash_info,
- ARRAY_SIZE(mityomapl138_spi_flash_info));
- if (ret)
- pr_warn("spi info registration failed: %d\n", ret);
-
- ret = da8xx_register_spi_bus(1,
- ARRAY_SIZE(mityomapl138_spi_flash_info));
- if (ret)
- pr_warn("spi 1 registration failed: %d\n", ret);
-
- mityomapl138_config_emac();
-
- ret = da8xx_register_rtc();
- if (ret)
- pr_warn("rtc setup failed: %d\n", ret);
-
- ret = da8xx_register_cpuidle();
- if (ret)
- pr_warn("cpuidle registration failed: %d\n", ret);
-
- davinci_pm_init();
-}
-
-#ifdef CONFIG_SERIAL_8250_CONSOLE
-static int __init mityomapl138_console_init(void)
-{
- if (!machine_is_mityomapl138())
- return 0;
-
- return add_preferred_console("ttyS", 1, "115200");
-}
-console_initcall(mityomapl138_console_init);
-#endif
-
-static void __init mityomapl138_map_io(void)
-{
- da850_init();
-}
-
-MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
- .atag_offset = 0x100,
- .map_io = mityomapl138_map_io,
- .init_irq = da850_init_irq,
- .init_time = da850_init_time,
- .init_machine = mityomapl138_init,
- .init_late = davinci_init_late,
- .dma_zone_size = SZ_128M,
-MACHINE_END
diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c
deleted file mode 100644
index 8a80115999ad..000000000000
--- a/arch/arm/mach-davinci/board-omapl138-hawk.c
+++ /dev/null
@@ -1,451 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Hawkboard.org based on TI's OMAP-L138 Platform
- *
- * Initial code: Syed Mohammed Khasim
- *
- * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/console.h>
-#include <linux/interrupt.h>
-#include <linux/gpio.h>
-#include <linux/gpio/machine.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/platform_data/gpio-davinci.h>
-#include <linux/platform_data/mtd-davinci.h>
-#include <linux/platform_data/mtd-davinci-aemif.h>
-#include <linux/platform_data/ti-aemif.h>
-#include <linux/regulator/fixed.h>
-#include <linux/regulator/machine.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include "common.h"
-#include "da8xx.h"
-#include "mux.h"
-
-#define HAWKBOARD_PHY_ID "davinci_mdio-0:07"
-
-#define DA850_USB1_VBUS_PIN GPIO_TO_PIN(2, 4)
-#define DA850_USB1_OC_PIN GPIO_TO_PIN(6, 13)
-
-static short omapl138_hawk_mii_pins[] __initdata = {
- DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
- DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
- DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
- DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
- DA850_MDIO_D,
- -1
-};
-
-static __init void omapl138_hawk_config_emac(void)
-{
- void __iomem *cfgchip3 = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
- int ret;
- u32 val;
- struct davinci_soc_info *soc_info = &davinci_soc_info;
-
- val = __raw_readl(cfgchip3);
- val &= ~BIT(8);
- ret = davinci_cfg_reg_list(omapl138_hawk_mii_pins);
- if (ret) {
- pr_warn("%s: CPGMAC/MII mux setup failed: %d\n", __func__, ret);
- return;
- }
-
- /* configure the CFGCHIP3 register for MII */
- __raw_writel(val, cfgchip3);
- pr_info("EMAC: MII PHY configured\n");
-
- soc_info->emac_pdata->phy_id = HAWKBOARD_PHY_ID;
-
- ret = da8xx_register_emac();
- if (ret)
- pr_warn("%s: EMAC registration failed: %d\n", __func__, ret);
-}
-
-/*
- * The following EDMA channels/slots are not being used by drivers (for
- * example: Timer, GPIO, UART events etc) on da850/omap-l138 EVM/Hawkboard,
- * hence they are being reserved for codecs on the DSP side.
- */
-static const s16 da850_dma0_rsv_chans[][2] = {
- /* (offset, number) */
- { 8, 6},
- {24, 4},
- {30, 2},
- {-1, -1}
-};
-
-static const s16 da850_dma0_rsv_slots[][2] = {
- /* (offset, number) */
- { 8, 6},
- {24, 4},
- {30, 50},
- {-1, -1}
-};
-
-static const s16 da850_dma1_rsv_chans[][2] = {
- /* (offset, number) */
- { 0, 28},
- {30, 2},
- {-1, -1}
-};
-
-static const s16 da850_dma1_rsv_slots[][2] = {
- /* (offset, number) */
- { 0, 28},
- {30, 90},
- {-1, -1}
-};
-
-static struct edma_rsv_info da850_edma_cc0_rsv = {
- .rsv_chans = da850_dma0_rsv_chans,
- .rsv_slots = da850_dma0_rsv_slots,
-};
-
-static struct edma_rsv_info da850_edma_cc1_rsv = {
- .rsv_chans = da850_dma1_rsv_chans,
- .rsv_slots = da850_dma1_rsv_slots,
-};
-
-static struct edma_rsv_info *da850_edma_rsv[2] = {
- &da850_edma_cc0_rsv,
- &da850_edma_cc1_rsv,
-};
-
-static const short hawk_mmcsd0_pins[] = {
- DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2,
- DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD,
- DA850_GPIO3_12, DA850_GPIO3_13,
- -1
-};
-
-#define DA850_HAWK_MMCSD_CD_PIN GPIO_TO_PIN(3, 12)
-#define DA850_HAWK_MMCSD_WP_PIN GPIO_TO_PIN(3, 13)
-
-static struct gpiod_lookup_table mmc_gpios_table = {
- .dev_id = "da830-mmc.0",
- .table = {
- GPIO_LOOKUP("davinci_gpio", DA850_HAWK_MMCSD_CD_PIN, "cd",
- GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("davinci_gpio", DA850_HAWK_MMCSD_WP_PIN, "wp",
- GPIO_ACTIVE_LOW),
- },
-};
-
-static struct davinci_mmc_config da850_mmc_config = {
- .wires = 4,
- .max_freq = 50000000,
- .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
-};
-
-static __init void omapl138_hawk_mmc_init(void)
-{
- int ret;
-
- ret = davinci_cfg_reg_list(hawk_mmcsd0_pins);
- if (ret) {
- pr_warn("%s: MMC/SD0 mux setup failed: %d\n", __func__, ret);
- return;
- }
-
- gpiod_add_lookup_table(&mmc_gpios_table);
-
- ret = da8xx_register_mmcsd0(&da850_mmc_config);
- if (ret) {
- pr_warn("%s: MMC/SD0 registration failed: %d\n", __func__, ret);
- goto mmc_setup_mmcsd_fail;
- }
-
- return;
-
-mmc_setup_mmcsd_fail:
- gpiod_remove_lookup_table(&mmc_gpios_table);
-}
-
-static struct mtd_partition omapl138_hawk_nandflash_partition[] = {
- {
- .name = "u-boot env",
- .offset = 0,
- .size = SZ_128K,
- .mask_flags = MTD_WRITEABLE,
- },
- {
- .name = "u-boot",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_512K,
- .mask_flags = MTD_WRITEABLE,
- },
- {
- .name = "free space",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- .mask_flags = 0,
- },
-};
-
-static struct davinci_aemif_timing omapl138_hawk_nandflash_timing = {
- .wsetup = 24,
- .wstrobe = 21,
- .whold = 14,
- .rsetup = 19,
- .rstrobe = 50,
- .rhold = 0,
- .ta = 20,
-};
-
-static struct davinci_nand_pdata omapl138_hawk_nandflash_data = {
- .core_chipsel = 1,
- .parts = omapl138_hawk_nandflash_partition,
- .nr_parts = ARRAY_SIZE(omapl138_hawk_nandflash_partition),
- .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
- .ecc_bits = 4,
- .bbt_options = NAND_BBT_USE_FLASH,
- .options = NAND_BUSWIDTH_16,
- .timing = &omapl138_hawk_nandflash_timing,
- .mask_chipsel = 0,
- .mask_ale = 0,
- .mask_cle = 0,
-};
-
-static struct resource omapl138_hawk_nandflash_resource[] = {
- {
- .start = DA8XX_AEMIF_CS3_BASE,
- .end = DA8XX_AEMIF_CS3_BASE + SZ_32M,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DA8XX_AEMIF_CTL_BASE,
- .end = DA8XX_AEMIF_CTL_BASE + SZ_32K,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct resource omapl138_hawk_aemif_resource[] = {
- {
- .start = DA8XX_AEMIF_CTL_BASE,
- .end = DA8XX_AEMIF_CTL_BASE + SZ_32K,
- .flags = IORESOURCE_MEM,
- }
-};
-
-static struct aemif_abus_data omapl138_hawk_aemif_abus_data[] = {
- {
- .cs = 3,
- }
-};
-
-static struct platform_device omapl138_hawk_aemif_devices[] = {
- {
- .name = "davinci_nand",
- .id = -1,
- .dev = {
- .platform_data = &omapl138_hawk_nandflash_data,
- },
- .resource = omapl138_hawk_nandflash_resource,
- .num_resources = ARRAY_SIZE(omapl138_hawk_nandflash_resource),
- }
-};
-
-static struct aemif_platform_data omapl138_hawk_aemif_pdata = {
- .cs_offset = 2,
- .abus_data = omapl138_hawk_aemif_abus_data,
- .num_abus_data = ARRAY_SIZE(omapl138_hawk_aemif_abus_data),
- .sub_devices = omapl138_hawk_aemif_devices,
- .num_sub_devices = ARRAY_SIZE(omapl138_hawk_aemif_devices),
-};
-
-static struct platform_device omapl138_hawk_aemif_device = {
- .name = "ti-aemif",
- .id = -1,
- .dev = {
- .platform_data = &omapl138_hawk_aemif_pdata,
- },
- .resource = omapl138_hawk_aemif_resource,
- .num_resources = ARRAY_SIZE(omapl138_hawk_aemif_resource),
-};
-
-static const short omapl138_hawk_nand_pins[] = {
- DA850_EMA_WAIT_1, DA850_NEMA_OE, DA850_NEMA_WE, DA850_NEMA_CS_3,
- DA850_EMA_D_0, DA850_EMA_D_1, DA850_EMA_D_2, DA850_EMA_D_3,
- DA850_EMA_D_4, DA850_EMA_D_5, DA850_EMA_D_6, DA850_EMA_D_7,
- DA850_EMA_D_8, DA850_EMA_D_9, DA850_EMA_D_10, DA850_EMA_D_11,
- DA850_EMA_D_12, DA850_EMA_D_13, DA850_EMA_D_14, DA850_EMA_D_15,
- DA850_EMA_A_1, DA850_EMA_A_2,
- -1
-};
-
-static int omapl138_hawk_register_aemif(void)
-{
- int ret;
-
- ret = davinci_cfg_reg_list(omapl138_hawk_nand_pins);
- if (ret)
- pr_warn("%s: NAND mux setup failed: %d\n", __func__, ret);
-
- return platform_device_register(&omapl138_hawk_aemif_device);
-}
-
-static const short da850_hawk_usb11_pins[] = {
- DA850_GPIO2_4, DA850_GPIO6_13,
- -1
-};
-
-static struct regulator_consumer_supply hawk_usb_supplies[] = {
- REGULATOR_SUPPLY("vbus", NULL),
-};
-
-static struct regulator_init_data hawk_usb_vbus_data = {
- .consumer_supplies = hawk_usb_supplies,
- .num_consumer_supplies = ARRAY_SIZE(hawk_usb_supplies),
- .constraints = {
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- },
-};
-
-static struct fixed_voltage_config hawk_usb_vbus = {
- .supply_name = "vbus",
- .microvolts = 3300000,
- .init_data = &hawk_usb_vbus_data,
-};
-
-static struct platform_device hawk_usb_vbus_device = {
- .name = "reg-fixed-voltage",
- .id = 0,
- .dev = {
- .platform_data = &hawk_usb_vbus,
- },
-};
-
-static struct gpiod_lookup_table hawk_usb_oc_gpio_lookup = {
- .dev_id = "ohci-da8xx",
- .table = {
- GPIO_LOOKUP("davinci_gpio", DA850_USB1_OC_PIN, "oc", 0),
- { }
- },
-};
-
-static struct gpiod_lookup_table hawk_usb_vbus_gpio_lookup = {
- .dev_id = "reg-fixed-voltage.0",
- .table = {
- GPIO_LOOKUP("davinci_gpio", DA850_USB1_VBUS_PIN, NULL, 0),
- { }
- },
-};
-
-static struct gpiod_lookup_table *hawk_usb_gpio_lookups[] = {
- &hawk_usb_oc_gpio_lookup,
- &hawk_usb_vbus_gpio_lookup,
-};
-
-static struct da8xx_ohci_root_hub omapl138_hawk_usb11_pdata = {
- /* TPS2087 switch @ 5V */
- .potpgt = (3 + 1) / 2, /* 3 ms max */
-};
-
-static __init void omapl138_hawk_usb_init(void)
-{
- int ret;
-
- ret = davinci_cfg_reg_list(da850_hawk_usb11_pins);
- if (ret) {
- pr_warn("%s: USB 1.1 PinMux setup failed: %d\n", __func__, ret);
- return;
- }
-
- ret = da8xx_register_usb_phy_clocks();
- if (ret)
- pr_warn("%s: USB PHY CLK registration failed: %d\n",
- __func__, ret);
-
- gpiod_add_lookup_tables(hawk_usb_gpio_lookups,
- ARRAY_SIZE(hawk_usb_gpio_lookups));
-
- ret = da8xx_register_usb_phy();
- if (ret)
- pr_warn("%s: USB PHY registration failed: %d\n",
- __func__, ret);
-
- ret = platform_device_register(&hawk_usb_vbus_device);
- if (ret) {
- pr_warn("%s: Unable to register the vbus supply\n", __func__);
- return;
- }
-
- ret = da8xx_register_usb11(&omapl138_hawk_usb11_pdata);
- if (ret)
- pr_warn("%s: USB 1.1 registration failed: %d\n", __func__, ret);
-
- return;
-}
-
-static __init void omapl138_hawk_init(void)
-{
- int ret;
-
- da850_register_clocks();
-
- ret = da850_register_gpio();
- if (ret)
- pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
-
- davinci_serial_init(da8xx_serial_device);
-
- omapl138_hawk_config_emac();
-
- ret = da850_register_edma(da850_edma_rsv);
- if (ret)
- pr_warn("%s: EDMA registration failed: %d\n", __func__, ret);
-
- omapl138_hawk_mmc_init();
-
- omapl138_hawk_usb_init();
-
- ret = omapl138_hawk_register_aemif();
- if (ret)
- pr_warn("%s: aemif registration failed: %d\n", __func__, ret);
-
- ret = da8xx_register_watchdog();
- if (ret)
- pr_warn("%s: watchdog registration failed: %d\n",
- __func__, ret);
-
- ret = da8xx_register_rproc();
- if (ret)
- pr_warn("%s: dsp/rproc registration failed: %d\n",
- __func__, ret);
-
- regulator_has_full_constraints();
-}
-
-#ifdef CONFIG_SERIAL_8250_CONSOLE
-static int __init omapl138_hawk_console_init(void)
-{
- if (!machine_is_omapl138_hawkboard())
- return 0;
-
- return add_preferred_console("ttyS", 2, "115200");
-}
-console_initcall(omapl138_hawk_console_init);
-#endif
-
-static void __init omapl138_hawk_map_io(void)
-{
- da850_init();
-}
-
-MACHINE_START(OMAPL138_HAWKBOARD, "AM18x/OMAP-L138 Hawkboard")
- .atag_offset = 0x100,
- .map_io = omapl138_hawk_map_io,
- .init_irq = da850_init_irq,
- .init_time = da850_init_time,
- .init_machine = omapl138_hawk_init,
- .init_late = davinci_init_late,
- .dma_zone_size = SZ_128M,
- .reserve = da8xx_rproc_reserve_cma,
-MACHINE_END
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
deleted file mode 100644
index 199c26d9a2b6..000000000000
--- a/arch/arm/mach-davinci/devices.c
+++ /dev/null
@@ -1,303 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * mach-davinci/devices.c
- *
- * DaVinci platform device setup/initialization
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/platform_data/i2c-davinci.h>
-#include <linux/platform_data/mmc-davinci.h>
-#include <linux/platform_data/edma.h>
-#include <linux/dma-mapping.h>
-#include <linux/io.h>
-#include <linux/reboot.h>
-
-#include "hardware.h"
-#include "cputype.h"
-#include "mux.h"
-#include "davinci.h"
-#include "irqs.h"
-
-#define DAVINCI_I2C_BASE 0x01C21000
-#define DAVINCI_ATA_BASE 0x01C66000
-#define DAVINCI_MMCSD0_BASE 0x01E10000
-#define DM355_MMCSD0_BASE 0x01E11000
-#define DM355_MMCSD1_BASE 0x01E00000
-#define DM365_MMCSD0_BASE 0x01D11000
-#define DM365_MMCSD1_BASE 0x01D00000
-
-void __iomem *davinci_sysmod_base;
-
-void davinci_map_sysmod(void)
-{
- davinci_sysmod_base = ioremap(DAVINCI_SYSTEM_MODULE_BASE,
- 0x800);
- /*
- * Throw a bug since a lot of board initialization code depends
- * on system module availability. ioremap() failing this early
- * need careful looking into anyway.
- */
- BUG_ON(!davinci_sysmod_base);
-}
-
-static struct resource i2c_resources[] = {
- {
- .start = DAVINCI_I2C_BASE,
- .end = DAVINCI_I2C_BASE + 0x40,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_I2C),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device davinci_i2c_device = {
- .name = "i2c_davinci",
- .id = 1,
- .num_resources = ARRAY_SIZE(i2c_resources),
- .resource = i2c_resources,
-};
-
-void __init davinci_init_i2c(struct davinci_i2c_platform_data *pdata)
-{
- if (cpu_is_davinci_dm644x())
- davinci_cfg_reg(DM644X_I2C);
-
- davinci_i2c_device.dev.platform_data = pdata;
- (void) platform_device_register(&davinci_i2c_device);
-}
-
-static struct resource ide_resources[] = {
- {
- .start = DAVINCI_ATA_BASE,
- .end = DAVINCI_ATA_BASE + 0x7ff,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_IDE),
- .end = DAVINCI_INTC_IRQ(IRQ_IDE),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static u64 ide_dma_mask = DMA_BIT_MASK(32);
-
-static struct platform_device ide_device = {
- .name = "palm_bk3710",
- .id = -1,
- .resource = ide_resources,
- .num_resources = ARRAY_SIZE(ide_resources),
- .dev = {
- .dma_mask = &ide_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-};
-
-void __init davinci_init_ide(void)
-{
- if (cpu_is_davinci_dm644x()) {
- davinci_cfg_reg(DM644X_HPIEN_DISABLE);
- davinci_cfg_reg(DM644X_ATAEN);
- davinci_cfg_reg(DM644X_HDIREN);
- } else if (cpu_is_davinci_dm646x()) {
- /* IRQ_DM646X_IDE is the same as IRQ_IDE */
- davinci_cfg_reg(DM646X_ATAEN);
- } else {
- WARN_ON(1);
- return;
- }
-
- platform_device_register(&ide_device);
-}
-
-#if IS_ENABLED(CONFIG_MMC_DAVINCI)
-
-static u64 mmcsd0_dma_mask = DMA_BIT_MASK(32);
-
-static struct resource mmcsd0_resources[] = {
- {
- /* different on dm355 */
- .start = DAVINCI_MMCSD0_BASE,
- .end = DAVINCI_MMCSD0_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
- /* IRQs: MMC/SD, then SDIO */
- {
- .start = DAVINCI_INTC_IRQ(IRQ_MMCINT),
- .flags = IORESOURCE_IRQ,
- }, {
- /* different on dm355 */
- .start = DAVINCI_INTC_IRQ(IRQ_SDIOINT),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device davinci_mmcsd0_device = {
- .name = "dm6441-mmc",
- .id = 0,
- .dev = {
- .dma_mask = &mmcsd0_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .num_resources = ARRAY_SIZE(mmcsd0_resources),
- .resource = mmcsd0_resources,
-};
-
-static u64 mmcsd1_dma_mask = DMA_BIT_MASK(32);
-
-static struct resource mmcsd1_resources[] = {
- {
- .start = DM355_MMCSD1_BASE,
- .end = DM355_MMCSD1_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
- /* IRQs: MMC/SD, then SDIO */
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM355_MMCINT1),
- .flags = IORESOURCE_IRQ,
- }, {
- .start = DAVINCI_INTC_IRQ(IRQ_DM355_SDIOINT1),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device davinci_mmcsd1_device = {
- .name = "dm6441-mmc",
- .id = 1,
- .dev = {
- .dma_mask = &mmcsd1_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .num_resources = ARRAY_SIZE(mmcsd1_resources),
- .resource = mmcsd1_resources,
-};
-
-
-void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
-{
- struct platform_device *pdev = NULL;
-
- if (WARN_ON(cpu_is_davinci_dm646x()))
- return;
-
- /* REVISIT: update PINMUX, ARM_IRQMUX, and EDMA_EVTMUX here too;
- * for example if MMCSD1 is used for SDIO, maybe DAT2 is unused.
- *
- * FIXME dm6441 (no MMC/SD), dm357 (one), and dm335 (two) are
- * not handled right here ...
- */
- switch (module) {
- case 1:
- if (cpu_is_davinci_dm355()) {
- /* REVISIT we may not need all these pins if e.g. this
- * is a hard-wired SDIO device...
- */
- davinci_cfg_reg(DM355_SD1_CMD);
- davinci_cfg_reg(DM355_SD1_CLK);
- davinci_cfg_reg(DM355_SD1_DATA0);
- davinci_cfg_reg(DM355_SD1_DATA1);
- davinci_cfg_reg(DM355_SD1_DATA2);
- davinci_cfg_reg(DM355_SD1_DATA3);
- } else if (cpu_is_davinci_dm365()) {
- /* Configure pull down control */
- unsigned v;
-
- v = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_PUPDCTL1));
- __raw_writel(v & ~0xfc0,
- DAVINCI_SYSMOD_VIRT(SYSMOD_PUPDCTL1));
-
- mmcsd1_resources[0].start = DM365_MMCSD1_BASE;
- mmcsd1_resources[0].end = DM365_MMCSD1_BASE +
- SZ_4K - 1;
- mmcsd1_resources[2].start = DAVINCI_INTC_IRQ(
- IRQ_DM365_SDIOINT1);
- davinci_mmcsd1_device.name = "da830-mmc";
- } else
- break;
-
- pdev = &davinci_mmcsd1_device;
- break;
- case 0:
- if (cpu_is_davinci_dm355()) {
- mmcsd0_resources[0].start = DM355_MMCSD0_BASE;
- mmcsd0_resources[0].end = DM355_MMCSD0_BASE + SZ_4K - 1;
- mmcsd0_resources[2].start = DAVINCI_INTC_IRQ(
- IRQ_DM355_SDIOINT0);
-
- /* expose all 6 MMC0 signals: CLK, CMD, DATA[0..3] */
- davinci_cfg_reg(DM355_MMCSD0);
-
- /* enable RX EDMA */
- davinci_cfg_reg(DM355_EVT26_MMC0_RX);
- } else if (cpu_is_davinci_dm365()) {
- mmcsd0_resources[0].start = DM365_MMCSD0_BASE;
- mmcsd0_resources[0].end = DM365_MMCSD0_BASE +
- SZ_4K - 1;
- mmcsd0_resources[2].start = DAVINCI_INTC_IRQ(
- IRQ_DM365_SDIOINT0);
- davinci_mmcsd0_device.name = "da830-mmc";
- } else if (cpu_is_davinci_dm644x()) {
- /* REVISIT: should this be in board-init code? */
- /* Power-on 3.3V IO cells */
- __raw_writel(0,
- DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
- /*Set up the pull regiter for MMC */
- davinci_cfg_reg(DM644X_MSTK);
- }
-
- pdev = &davinci_mmcsd0_device;
- break;
- }
-
- if (WARN_ON(!pdev))
- return;
-
- pdev->dev.platform_data = config;
- platform_device_register(pdev);
-}
-
-#else
-
-void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
-{
-}
-
-#endif
-
-/*-------------------------------------------------------------------------*/
-
-static struct resource wdt_resources[] = {
- {
- .start = DAVINCI_WDOG_BASE,
- .end = DAVINCI_WDOG_BASE + SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device davinci_wdt_device = {
- .name = "davinci-wdt",
- .id = -1,
- .num_resources = ARRAY_SIZE(wdt_resources),
- .resource = wdt_resources,
-};
-
-int davinci_init_wdt(void)
-{
- return platform_device_register(&davinci_wdt_device);
-}
-
-static struct platform_device davinci_gpio_device = {
- .name = "davinci_gpio",
- .id = -1,
-};
-
-int davinci_gpio_register(struct resource *res, int size, void *pdata)
-{
- davinci_gpio_device.resource = res;
- davinci_gpio_device.num_resources = size;
- davinci_gpio_device.dev.platform_data = pdata;
- return platform_device_register(&davinci_gpio_device);
-}
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
deleted file mode 100644
index a12ba859beca..000000000000
--- a/arch/arm/mach-davinci/dm355.c
+++ /dev/null
@@ -1,832 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * TI DaVinci DM355 chip specific setup
- *
- * Author: Kevin Hilman, Deep Root Systems, LLC
- *
- * 2007 (c) Deep Root Systems, LLC.
- */
-
-#include <linux/clk-provider.h>
-#include <linux/clk/davinci.h>
-#include <linux/clkdev.h>
-#include <linux/dma-mapping.h>
-#include <linux/dmaengine.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/irqchip/irq-davinci-aintc.h>
-#include <linux/platform_data/edma.h>
-#include <linux/platform_data/gpio-davinci.h>
-#include <linux/platform_data/spi-davinci.h>
-#include <linux/platform_device.h>
-#include <linux/serial_8250.h>
-#include <linux/spi/spi.h>
-
-#include <clocksource/timer-davinci.h>
-
-#include <asm/mach/map.h>
-
-#include "common.h"
-#include "cputype.h"
-#include "serial.h"
-#include "asp.h"
-#include "davinci.h"
-#include "irqs.h"
-#include "mux.h"
-
-#define DM355_UART2_BASE (IO_PHYS + 0x206000)
-#define DM355_OSD_BASE (IO_PHYS + 0x70200)
-#define DM355_VENC_BASE (IO_PHYS + 0x70400)
-
-/*
- * Device specific clocks
- */
-#define DM355_REF_FREQ 24000000 /* 24 or 36 MHz */
-
-static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32);
-
-static struct resource dm355_spi0_resources[] = {
- {
- .start = 0x01c66000,
- .end = 0x01c667ff,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM355_SPINT0_0),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct davinci_spi_platform_data dm355_spi0_pdata = {
- .version = SPI_VERSION_1,
- .num_chipselect = 2,
- .cshold_bug = true,
- .dma_event_q = EVENTQ_1,
- .prescaler_limit = 1,
-};
-static struct platform_device dm355_spi0_device = {
- .name = "spi_davinci",
- .id = 0,
- .dev = {
- .dma_mask = &dm355_spi0_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &dm355_spi0_pdata,
- },
- .num_resources = ARRAY_SIZE(dm355_spi0_resources),
- .resource = dm355_spi0_resources,
-};
-
-void __init dm355_init_spi0(unsigned chipselect_mask,
- const struct spi_board_info *info, unsigned len)
-{
- /* for now, assume we need MISO */
- davinci_cfg_reg(DM355_SPI0_SDI);
-
- /* not all slaves will be wired up */
- if (chipselect_mask & BIT(0))
- davinci_cfg_reg(DM355_SPI0_SDENA0);
- if (chipselect_mask & BIT(1))
- davinci_cfg_reg(DM355_SPI0_SDENA1);
-
- spi_register_board_info(info, len);
-
- platform_device_register(&dm355_spi0_device);
-}
-
-/*----------------------------------------------------------------------*/
-
-#define INTMUX 0x18
-#define EVTMUX 0x1c
-
-/*
- * Device specific mux setup
- *
- * soc description mux mode mode mux dbg
- * reg offset mask mode
- */
-static const struct mux_config dm355_pins[] = {
-#ifdef CONFIG_DAVINCI_MUX
-MUX_CFG(DM355, MMCSD0, 4, 2, 1, 0, false)
-
-MUX_CFG(DM355, SD1_CLK, 3, 6, 1, 1, false)
-MUX_CFG(DM355, SD1_CMD, 3, 7, 1, 1, false)
-MUX_CFG(DM355, SD1_DATA3, 3, 8, 3, 1, false)
-MUX_CFG(DM355, SD1_DATA2, 3, 10, 3, 1, false)
-MUX_CFG(DM355, SD1_DATA1, 3, 12, 3, 1, false)
-MUX_CFG(DM355, SD1_DATA0, 3, 14, 3, 1, false)
-
-MUX_CFG(DM355, I2C_SDA, 3, 19, 1, 1, false)
-MUX_CFG(DM355, I2C_SCL, 3, 20, 1, 1, false)
-
-MUX_CFG(DM355, MCBSP0_BDX, 3, 0, 1, 1, false)
-MUX_CFG(DM355, MCBSP0_X, 3, 1, 1, 1, false)
-MUX_CFG(DM355, MCBSP0_BFSX, 3, 2, 1, 1, false)
-MUX_CFG(DM355, MCBSP0_BDR, 3, 3, 1, 1, false)
-MUX_CFG(DM355, MCBSP0_R, 3, 4, 1, 1, false)
-MUX_CFG(DM355, MCBSP0_BFSR, 3, 5, 1, 1, false)
-
-MUX_CFG(DM355, SPI0_SDI, 4, 1, 1, 0, false)
-MUX_CFG(DM355, SPI0_SDENA0, 4, 0, 1, 0, false)
-MUX_CFG(DM355, SPI0_SDENA1, 3, 28, 1, 1, false)
-
-INT_CFG(DM355, INT_EDMA_CC, 2, 1, 1, false)
-INT_CFG(DM355, INT_EDMA_TC0_ERR, 3, 1, 1, false)
-INT_CFG(DM355, INT_EDMA_TC1_ERR, 4, 1, 1, false)
-
-EVT_CFG(DM355, EVT8_ASP1_TX, 0, 1, 0, false)
-EVT_CFG(DM355, EVT9_ASP1_RX, 1, 1, 0, false)
-EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false)
-
-MUX_CFG(DM355, VOUT_FIELD, 1, 18, 3, 1, false)
-MUX_CFG(DM355, VOUT_FIELD_G70, 1, 18, 3, 0, false)
-MUX_CFG(DM355, VOUT_HVSYNC, 1, 16, 1, 0, false)
-MUX_CFG(DM355, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false)
-MUX_CFG(DM355, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false)
-
-MUX_CFG(DM355, VIN_PCLK, 0, 14, 1, 1, false)
-MUX_CFG(DM355, VIN_CAM_WEN, 0, 13, 1, 1, false)
-MUX_CFG(DM355, VIN_CAM_VD, 0, 12, 1, 1, false)
-MUX_CFG(DM355, VIN_CAM_HD, 0, 11, 1, 1, false)
-MUX_CFG(DM355, VIN_YIN_EN, 0, 10, 1, 1, false)
-MUX_CFG(DM355, VIN_CINL_EN, 0, 0, 0xff, 0x55, false)
-MUX_CFG(DM355, VIN_CINH_EN, 0, 8, 3, 3, false)
-#endif
-};
-
-static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
- [IRQ_DM355_CCDC_VDINT0] = 2,
- [IRQ_DM355_CCDC_VDINT1] = 6,
- [IRQ_DM355_CCDC_VDINT2] = 6,
- [IRQ_DM355_IPIPE_HST] = 6,
- [IRQ_DM355_H3AINT] = 6,
- [IRQ_DM355_IPIPE_SDR] = 6,
- [IRQ_DM355_IPIPEIFINT] = 6,
- [IRQ_DM355_OSDINT] = 7,
- [IRQ_DM355_VENCINT] = 6,
- [IRQ_ASQINT] = 6,
- [IRQ_IMXINT] = 6,
- [IRQ_USBINT] = 4,
- [IRQ_DM355_RTOINT] = 4,
- [IRQ_DM355_UARTINT2] = 7,
- [IRQ_DM355_TINT6] = 7,
- [IRQ_CCINT0] = 5, /* dma */
- [IRQ_CCERRINT] = 5, /* dma */
- [IRQ_TCERRINT0] = 5, /* dma */
- [IRQ_TCERRINT] = 5, /* dma */
- [IRQ_DM355_SPINT2_1] = 7,
- [IRQ_DM355_TINT7] = 4,
- [IRQ_DM355_SDIOINT0] = 7,
- [IRQ_MBXINT] = 7,
- [IRQ_MBRINT] = 7,
- [IRQ_MMCINT] = 7,
- [IRQ_DM355_MMCINT1] = 7,
- [IRQ_DM355_PWMINT3] = 7,
- [IRQ_DDRINT] = 7,
- [IRQ_AEMIFINT] = 7,
- [IRQ_DM355_SDIOINT1] = 4,
- [IRQ_TINT0_TINT12] = 2, /* clockevent */
- [IRQ_TINT0_TINT34] = 2, /* clocksource */
- [IRQ_TINT1_TINT12] = 7, /* DSP timer */
- [IRQ_TINT1_TINT34] = 7, /* system tick */
- [IRQ_PWMINT0] = 7,
- [IRQ_PWMINT1] = 7,
- [IRQ_PWMINT2] = 7,
- [IRQ_I2C] = 3,
- [IRQ_UARTINT0] = 3,
- [IRQ_UARTINT1] = 3,
- [IRQ_DM355_SPINT0_0] = 3,
- [IRQ_DM355_SPINT0_1] = 3,
- [IRQ_DM355_GPIO0] = 3,
- [IRQ_DM355_GPIO1] = 7,
- [IRQ_DM355_GPIO2] = 4,
- [IRQ_DM355_GPIO3] = 4,
- [IRQ_DM355_GPIO4] = 7,
- [IRQ_DM355_GPIO5] = 7,
- [IRQ_DM355_GPIO6] = 7,
- [IRQ_DM355_GPIO7] = 7,
- [IRQ_DM355_GPIO8] = 7,
- [IRQ_DM355_GPIO9] = 7,
- [IRQ_DM355_GPIOBNK0] = 7,
- [IRQ_DM355_GPIOBNK1] = 7,
- [IRQ_DM355_GPIOBNK2] = 7,
- [IRQ_DM355_GPIOBNK3] = 7,
- [IRQ_DM355_GPIOBNK4] = 7,
- [IRQ_DM355_GPIOBNK5] = 7,
- [IRQ_DM355_GPIOBNK6] = 7,
- [IRQ_COMMTX] = 7,
- [IRQ_COMMRX] = 7,
- [IRQ_EMUINT] = 7,
-};
-
-/*----------------------------------------------------------------------*/
-
-static s8 queue_priority_mapping[][2] = {
- /* {event queue no, Priority} */
- {0, 3},
- {1, 7},
- {-1, -1},
-};
-
-static const struct dma_slave_map dm355_edma_map[] = {
- { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 2) },
- { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 3) },
- { "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 8) },
- { "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 9) },
- { "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) },
- { "spi_davinci.2", "rx", EDMA_FILTER_PARAM(0, 11) },
- { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 14) },
- { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 15) },
- { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 16) },
- { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) },
- { "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
- { "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
- { "dm6441-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) },
- { "dm6441-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) },
-};
-
-static struct edma_soc_info dm355_edma_pdata = {
- .queue_priority_mapping = queue_priority_mapping,
- .default_queue = EVENTQ_1,
- .slave_map = dm355_edma_map,
- .slavecnt = ARRAY_SIZE(dm355_edma_map),
-};
-
-static struct resource edma_resources[] = {
- {
- .name = "edma3_cc",
- .start = 0x01c00000,
- .end = 0x01c00000 + SZ_64K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "edma3_tc0",
- .start = 0x01c10000,
- .end = 0x01c10000 + SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "edma3_tc1",
- .start = 0x01c10400,
- .end = 0x01c10400 + SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "edma3_ccint",
- .start = DAVINCI_INTC_IRQ(IRQ_CCINT0),
- .flags = IORESOURCE_IRQ,
- },
- {
- .name = "edma3_ccerrint",
- .start = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
- .flags = IORESOURCE_IRQ,
- },
- /* not using (or muxing) TC*_ERR */
-};
-
-static const struct platform_device_info dm355_edma_device __initconst = {
- .name = "edma",
- .id = 0,
- .dma_mask = DMA_BIT_MASK(32),
- .res = edma_resources,
- .num_res = ARRAY_SIZE(edma_resources),
- .data = &dm355_edma_pdata,
- .size_data = sizeof(dm355_edma_pdata),
-};
-
-static struct resource dm355_asp1_resources[] = {
- {
- .name = "mpu",
- .start = DAVINCI_ASP1_BASE,
- .end = DAVINCI_ASP1_BASE + SZ_8K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DAVINCI_DMA_ASP1_TX,
- .end = DAVINCI_DMA_ASP1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = DAVINCI_DMA_ASP1_RX,
- .end = DAVINCI_DMA_ASP1_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device dm355_asp1_device = {
- .name = "davinci-mcbsp",
- .id = 1,
- .num_resources = ARRAY_SIZE(dm355_asp1_resources),
- .resource = dm355_asp1_resources,
-};
-
-static void dm355_ccdc_setup_pinmux(void)
-{
- davinci_cfg_reg(DM355_VIN_PCLK);
- davinci_cfg_reg(DM355_VIN_CAM_WEN);
- davinci_cfg_reg(DM355_VIN_CAM_VD);
- davinci_cfg_reg(DM355_VIN_CAM_HD);
- davinci_cfg_reg(DM355_VIN_YIN_EN);
- davinci_cfg_reg(DM355_VIN_CINL_EN);
- davinci_cfg_reg(DM355_VIN_CINH_EN);
-}
-
-static struct resource dm355_vpss_resources[] = {
- {
- /* VPSS BL Base address */
- .name = "vpss",
- .start = 0x01c70800,
- .end = 0x01c70800 + 0xff,
- .flags = IORESOURCE_MEM,
- },
- {
- /* VPSS CLK Base address */
- .name = "vpss",
- .start = 0x01c70000,
- .end = 0x01c70000 + 0xf,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device dm355_vpss_device = {
- .name = "vpss",
- .id = -1,
- .dev.platform_data = "dm355_vpss",
- .num_resources = ARRAY_SIZE(dm355_vpss_resources),
- .resource = dm355_vpss_resources,
-};
-
-static struct resource vpfe_resources[] = {
- {
- .start = DAVINCI_INTC_IRQ(IRQ_VDINT0),
- .end = DAVINCI_INTC_IRQ(IRQ_VDINT0),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_VDINT1),
- .end = DAVINCI_INTC_IRQ(IRQ_VDINT1),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
-static struct resource dm355_ccdc_resource[] = {
- /* CCDC Base address */
- {
- .flags = IORESOURCE_MEM,
- .start = 0x01c70600,
- .end = 0x01c70600 + 0x1ff,
- },
-};
-static struct platform_device dm355_ccdc_dev = {
- .name = "dm355_ccdc",
- .id = -1,
- .num_resources = ARRAY_SIZE(dm355_ccdc_resource),
- .resource = dm355_ccdc_resource,
- .dev = {
- .dma_mask = &vpfe_capture_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = dm355_ccdc_setup_pinmux,
- },
-};
-
-static struct platform_device vpfe_capture_dev = {
- .name = CAPTURE_DRV_NAME,
- .id = -1,
- .num_resources = ARRAY_SIZE(vpfe_resources),
- .resource = vpfe_resources,
- .dev = {
- .dma_mask = &vpfe_capture_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-};
-
-static struct resource dm355_osd_resources[] = {
- {
- .start = DM355_OSD_BASE,
- .end = DM355_OSD_BASE + 0x17f,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device dm355_osd_dev = {
- .name = DM355_VPBE_OSD_SUBDEV_NAME,
- .id = -1,
- .num_resources = ARRAY_SIZE(dm355_osd_resources),
- .resource = dm355_osd_resources,
- .dev = {
- .dma_mask = &vpfe_capture_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-};
-
-static struct resource dm355_venc_resources[] = {
- {
- .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
- .end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
- .flags = IORESOURCE_IRQ,
- },
- /* venc registers io space */
- {
- .start = DM355_VENC_BASE,
- .end = DM355_VENC_BASE + 0x17f,
- .flags = IORESOURCE_MEM,
- },
- /* VDAC config register io space */
- {
- .start = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG,
- .end = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct resource dm355_v4l2_disp_resources[] = {
- {
- .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
- .end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
- .flags = IORESOURCE_IRQ,
- },
- /* venc registers io space */
- {
- .start = DM355_VENC_BASE,
- .end = DM355_VENC_BASE + 0x17f,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static int dm355_vpbe_setup_pinmux(u32 if_type, int field)
-{
- switch (if_type) {
- case MEDIA_BUS_FMT_SGRBG8_1X8:
- davinci_cfg_reg(DM355_VOUT_FIELD_G70);
- break;
- case MEDIA_BUS_FMT_YUYV10_1X20:
- if (field)
- davinci_cfg_reg(DM355_VOUT_FIELD);
- else
- davinci_cfg_reg(DM355_VOUT_FIELD_G70);
- break;
- default:
- return -EINVAL;
- }
-
- davinci_cfg_reg(DM355_VOUT_COUTL_EN);
- davinci_cfg_reg(DM355_VOUT_COUTH_EN);
-
- return 0;
-}
-
-static int dm355_venc_setup_clock(enum vpbe_enc_timings_type type,
- unsigned int pclock)
-{
- void __iomem *vpss_clk_ctrl_reg;
-
- vpss_clk_ctrl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL);
-
- switch (type) {
- case VPBE_ENC_STD:
- writel(VPSS_DACCLKEN_ENABLE | VPSS_VENCCLKEN_ENABLE,
- vpss_clk_ctrl_reg);
- break;
- case VPBE_ENC_DV_TIMINGS:
- if (pclock > 27000000)
- /*
- * For HD, use external clock source since we cannot
- * support HD mode with internal clocks.
- */
- writel(VPSS_MUXSEL_EXTCLK_ENABLE, vpss_clk_ctrl_reg);
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-static struct platform_device dm355_vpbe_display = {
- .name = "vpbe-v4l2",
- .id = -1,
- .num_resources = ARRAY_SIZE(dm355_v4l2_disp_resources),
- .resource = dm355_v4l2_disp_resources,
- .dev = {
- .dma_mask = &vpfe_capture_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-};
-
-static struct venc_platform_data dm355_venc_pdata = {
- .setup_pinmux = dm355_vpbe_setup_pinmux,
- .setup_clock = dm355_venc_setup_clock,
-};
-
-static struct platform_device dm355_venc_dev = {
- .name = DM355_VPBE_VENC_SUBDEV_NAME,
- .id = -1,
- .num_resources = ARRAY_SIZE(dm355_venc_resources),
- .resource = dm355_venc_resources,
- .dev = {
- .dma_mask = &vpfe_capture_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = (void *)&dm355_venc_pdata,
- },
-};
-
-static struct platform_device dm355_vpbe_dev = {
- .name = "vpbe_controller",
- .id = -1,
- .dev = {
- .dma_mask = &vpfe_capture_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-};
-
-static struct resource dm355_gpio_resources[] = {
- { /* registers */
- .start = DAVINCI_GPIO_BASE,
- .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
- { /* interrupt */
- .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK0),
- .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK0),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK1),
- .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK1),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK2),
- .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK2),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK3),
- .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK3),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK4),
- .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK4),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK5),
- .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK5),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK6),
- .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK6),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct davinci_gpio_platform_data dm355_gpio_platform_data = {
- .no_auto_base = true,
- .base = 0,
- .ngpio = 104,
-};
-
-int __init dm355_gpio_register(void)
-{
- return davinci_gpio_register(dm355_gpio_resources,
- ARRAY_SIZE(dm355_gpio_resources),
- &dm355_gpio_platform_data);
-}
-/*----------------------------------------------------------------------*/
-
-static struct map_desc dm355_io_desc[] = {
- {
- .virtual = IO_VIRT,
- .pfn = __phys_to_pfn(IO_PHYS),
- .length = IO_SIZE,
- .type = MT_DEVICE
- },
-};
-
-/* Contents of JTAG ID register used to identify exact cpu type */
-static struct davinci_id dm355_ids[] = {
- {
- .variant = 0x0,
- .part_no = 0xb73b,
- .manufacturer = 0x00f,
- .cpu_id = DAVINCI_CPU_ID_DM355,
- .name = "dm355",
- },
-};
-
-/*
- * Bottom half of timer0 is used for clockevent, top half is used for
- * clocksource.
- */
-static const struct davinci_timer_cfg dm355_timer_cfg = {
- .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K),
- .irq = {
- DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
- DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
- },
-};
-
-static struct plat_serial8250_port dm355_serial0_platform_data[] = {
- {
- .mapbase = DAVINCI_UART0_BASE,
- .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
- UPF_IOREMAP,
- .iotype = UPIO_MEM,
- .regshift = 2,
- },
- {
- .flags = 0,
- }
-};
-static struct plat_serial8250_port dm355_serial1_platform_data[] = {
- {
- .mapbase = DAVINCI_UART1_BASE,
- .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
- UPF_IOREMAP,
- .iotype = UPIO_MEM,
- .regshift = 2,
- },
- {
- .flags = 0,
- }
-};
-static struct plat_serial8250_port dm355_serial2_platform_data[] = {
- {
- .mapbase = DM355_UART2_BASE,
- .irq = DAVINCI_INTC_IRQ(IRQ_DM355_UARTINT2),
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
- UPF_IOREMAP,
- .iotype = UPIO_MEM,
- .regshift = 2,
- },
- {
- .flags = 0,
- }
-};
-
-struct platform_device dm355_serial_device[] = {
- {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM,
- .dev = {
- .platform_data = dm355_serial0_platform_data,
- }
- },
- {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM1,
- .dev = {
- .platform_data = dm355_serial1_platform_data,
- }
- },
- {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM2,
- .dev = {
- .platform_data = dm355_serial2_platform_data,
- }
- },
- {
- }
-};
-
-static const struct davinci_soc_info davinci_soc_info_dm355 = {
- .io_desc = dm355_io_desc,
- .io_desc_num = ARRAY_SIZE(dm355_io_desc),
- .jtag_id_reg = 0x01c40028,
- .ids = dm355_ids,
- .ids_num = ARRAY_SIZE(dm355_ids),
- .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
- .pinmux_pins = dm355_pins,
- .pinmux_pins_num = ARRAY_SIZE(dm355_pins),
- .sram_dma = 0x00010000,
- .sram_len = SZ_32K,
-};
-
-void __init dm355_init_asp1(u32 evt_enable)
-{
- /* we don't use ASP1 IRQs, or we'd need to mux them ... */
- if (evt_enable & ASP1_TX_EVT_EN)
- davinci_cfg_reg(DM355_EVT8_ASP1_TX);
-
- if (evt_enable & ASP1_RX_EVT_EN)
- davinci_cfg_reg(DM355_EVT9_ASP1_RX);
-
- platform_device_register(&dm355_asp1_device);
-}
-
-void __init dm355_init(void)
-{
- davinci_common_init(&davinci_soc_info_dm355);
- davinci_map_sysmod();
-}
-
-void __init dm355_init_time(void)
-{
- void __iomem *pll1, *psc;
- struct clk *clk;
- int rv;
-
- clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM355_REF_FREQ);
-
- pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
- dm355_pll1_init(NULL, pll1, NULL);
-
- psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
- dm355_psc_init(NULL, psc);
-
- clk = clk_get(NULL, "timer0");
- if (WARN_ON(IS_ERR(clk))) {
- pr_err("Unable to get the timer clock\n");
- return;
- }
-
- rv = davinci_timer_register(clk, &dm355_timer_cfg);
- WARN(rv, "Unable to register the timer: %d\n", rv);
-}
-
-static struct resource dm355_pll2_resources[] = {
- {
- .start = DAVINCI_PLL2_BASE,
- .end = DAVINCI_PLL2_BASE + SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device dm355_pll2_device = {
- .name = "dm355-pll2",
- .id = -1,
- .resource = dm355_pll2_resources,
- .num_resources = ARRAY_SIZE(dm355_pll2_resources),
-};
-
-void __init dm355_register_clocks(void)
-{
- /* PLL1 and PSC are registered in dm355_init_time() */
- platform_device_register(&dm355_pll2_device);
-}
-
-int __init dm355_init_video(struct vpfe_config *vpfe_cfg,
- struct vpbe_config *vpbe_cfg)
-{
- if (vpfe_cfg || vpbe_cfg)
- platform_device_register(&dm355_vpss_device);
-
- if (vpfe_cfg) {
- vpfe_capture_dev.dev.platform_data = vpfe_cfg;
- platform_device_register(&dm355_ccdc_dev);
- platform_device_register(&vpfe_capture_dev);
- }
-
- if (vpbe_cfg) {
- dm355_vpbe_dev.dev.platform_data = vpbe_cfg;
- platform_device_register(&dm355_osd_dev);
- platform_device_register(&dm355_venc_dev);
- platform_device_register(&dm355_vpbe_dev);
- platform_device_register(&dm355_vpbe_display);
- }
-
- return 0;
-}
-
-static const struct davinci_aintc_config dm355_aintc_config = {
- .reg = {
- .start = DAVINCI_ARM_INTC_BASE,
- .end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
- .num_irqs = 64,
- .prios = dm355_default_priorities,
-};
-
-void __init dm355_init_irq(void)
-{
- davinci_aintc_init(&dm355_aintc_config);
-}
-
-static int __init dm355_init_devices(void)
-{
- struct platform_device *edma_pdev;
- int ret = 0;
-
- if (!cpu_is_davinci_dm355())
- return 0;
-
- davinci_cfg_reg(DM355_INT_EDMA_CC);
- edma_pdev = platform_device_register_full(&dm355_edma_device);
- if (IS_ERR(edma_pdev)) {
- pr_warn("%s: Failed to register eDMA\n", __func__);
- return PTR_ERR(edma_pdev);
- }
-
- ret = davinci_init_wdt();
- if (ret)
- pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
-
- return ret;
-}
-postcore_initcall(dm355_init_devices);
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
deleted file mode 100644
index 7538bb87f373..000000000000
--- a/arch/arm/mach-davinci/dm365.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * TI DaVinci DM365 chip specific setup
- *
- * Copyright (C) 2009 Texas Instruments
- */
-
-#include <linux/clk-provider.h>
-#include <linux/clk/davinci.h>
-#include <linux/clkdev.h>
-#include <linux/dma-mapping.h>
-#include <linux/dmaengine.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/irqchip/irq-davinci-aintc.h>
-#include <linux/platform_data/edma.h>
-#include <linux/platform_data/gpio-davinci.h>
-#include <linux/platform_data/keyscan-davinci.h>
-#include <linux/platform_data/spi-davinci.h>
-#include <linux/platform_device.h>
-#include <linux/serial_8250.h>
-#include <linux/spi/spi.h>
-
-#include <clocksource/timer-davinci.h>
-
-#include <asm/mach/map.h>
-
-#include "common.h"
-#include "cputype.h"
-#include "serial.h"
-#include "asp.h"
-#include "davinci.h"
-#include "irqs.h"
-#include "mux.h"
-
-#define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */
-#define DM365_RTC_BASE 0x01c69000
-#define DM365_KEYSCAN_BASE 0x01c69400
-#define DM365_OSD_BASE 0x01c71c00
-#define DM365_VENC_BASE 0x01c71e00
-#define DAVINCI_DM365_VC_BASE 0x01d0c000
-#define DAVINCI_DMA_VC_TX 2
-#define DAVINCI_DMA_VC_RX 3
-#define DM365_EMAC_BASE 0x01d07000
-#define DM365_EMAC_MDIO_BASE (DM365_EMAC_BASE + 0x4000)
-#define DM365_EMAC_CNTRL_OFFSET 0x0000
-#define DM365_EMAC_CNTRL_MOD_OFFSET 0x3000
-#define DM365_EMAC_CNTRL_RAM_OFFSET 0x1000
-#define DM365_EMAC_CNTRL_RAM_SIZE 0x2000
-
-#define INTMUX 0x18
-#define EVTMUX 0x1c
-
-
-static const struct mux_config dm365_pins[] = {
-#ifdef CONFIG_DAVINCI_MUX
-MUX_CFG(DM365, MMCSD0, 0, 24, 1, 0, false)
-
-MUX_CFG(DM365, SD1_CLK, 0, 16, 3, 1, false)
-MUX_CFG(DM365, SD1_CMD, 4, 30, 3, 1, false)
-MUX_CFG(DM365, SD1_DATA3, 4, 28, 3, 1, false)
-MUX_CFG(DM365, SD1_DATA2, 4, 26, 3, 1, false)
-MUX_CFG(DM365, SD1_DATA1, 4, 24, 3, 1, false)
-MUX_CFG(DM365, SD1_DATA0, 4, 22, 3, 1, false)
-
-MUX_CFG(DM365, I2C_SDA, 3, 23, 3, 2, false)
-MUX_CFG(DM365, I2C_SCL, 3, 21, 3, 2, false)
-
-MUX_CFG(DM365, AEMIF_AR_A14, 2, 0, 3, 1, false)
-MUX_CFG(DM365, AEMIF_AR_BA0, 2, 0, 3, 2, false)
-MUX_CFG(DM365, AEMIF_A3, 2, 2, 3, 1, false)
-MUX_CFG(DM365, AEMIF_A7, 2, 4, 3, 1, false)
-MUX_CFG(DM365, AEMIF_D15_8, 2, 6, 1, 1, false)
-MUX_CFG(DM365, AEMIF_CE0, 2, 7, 1, 0, false)
-MUX_CFG(DM365, AEMIF_CE1, 2, 8, 1, 0, false)
-MUX_CFG(DM365, AEMIF_WE_OE, 2, 9, 1, 0, false)
-
-MUX_CFG(DM365, MCBSP0_BDX, 0, 23, 1, 1, false)
-MUX_CFG(DM365, MCBSP0_X, 0, 22, 1, 1, false)
-MUX_CFG(DM365, MCBSP0_BFSX, 0, 21, 1, 1, false)
-MUX_CFG(DM365, MCBSP0_BDR, 0, 20, 1, 1, false)
-MUX_CFG(DM365, MCBSP0_R, 0, 19, 1, 1, false)
-MUX_CFG(DM365, MCBSP0_BFSR, 0, 18, 1, 1, false)
-
-MUX_CFG(DM365, SPI0_SCLK, 3, 28, 1, 1, false)
-MUX_CFG(DM365, SPI0_SDI, 3, 26, 3, 1, false)
-MUX_CFG(DM365, SPI0_SDO, 3, 25, 1, 1, false)
-MUX_CFG(DM365, SPI0_SDENA0, 3, 29, 3, 1, false)
-MUX_CFG(DM365, SPI0_SDENA1, 3, 26, 3, 2, false)
-
-MUX_CFG(DM365, UART0_RXD, 3, 20, 1, 1, false)
-MUX_CFG(DM365, UART0_TXD, 3, 19, 1, 1, false)
-MUX_CFG(DM365, UART1_RXD, 3, 17, 3, 2, false)
-MUX_CFG(DM365, UART1_TXD, 3, 15, 3, 2, false)
-MUX_CFG(DM365, UART1_RTS, 3, 23, 3, 1, false)
-MUX_CFG(DM365, UART1_CTS, 3, 21, 3, 1, false)
-
-MUX_CFG(DM365, EMAC_TX_EN, 3, 17, 3, 1, false)
-MUX_CFG(DM365, EMAC_TX_CLK, 3, 15, 3, 1, false)
-MUX_CFG(DM365, EMAC_COL, 3, 14, 1, 1, false)
-MUX_CFG(DM365, EMAC_TXD3, 3, 13, 1, 1, false)
-MUX_CFG(DM365, EMAC_TXD2, 3, 12, 1, 1, false)
-MUX_CFG(DM365, EMAC_TXD1, 3, 11, 1, 1, false)
-MUX_CFG(DM365, EMAC_TXD0, 3, 10, 1, 1, false)
-MUX_CFG(DM365, EMAC_RXD3, 3, 9, 1, 1, false)
-MUX_CFG(DM365, EMAC_RXD2, 3, 8, 1, 1, false)
-MUX_CFG(DM365, EMAC_RXD1, 3, 7, 1, 1, false)
-MUX_CFG(DM365, EMAC_RXD0, 3, 6, 1, 1, false)
-MUX_CFG(DM365, EMAC_RX_CLK, 3, 5, 1, 1, false)
-MUX_CFG(DM365, EMAC_RX_DV, 3, 4, 1, 1, false)
-MUX_CFG(DM365, EMAC_RX_ER, 3, 3, 1, 1, false)
-MUX_CFG(DM365, EMAC_CRS, 3, 2, 1, 1, false)
-MUX_CFG(DM365, EMAC_MDIO, 3, 1, 1, 1, false)
-MUX_CFG(DM365, EMAC_MDCLK, 3, 0, 1, 1, false)
-
-MUX_CFG(DM365, KEYSCAN, 2, 0, 0x3f, 0x3f, false)
-
-MUX_CFG(DM365, PWM0, 1, 0, 3, 2, false)
-MUX_CFG(DM365, PWM0_G23, 3, 26, 3, 3, false)
-MUX_CFG(DM365, PWM1, 1, 2, 3, 2, false)
-MUX_CFG(DM365, PWM1_G25, 3, 29, 3, 2, false)
-MUX_CFG(DM365, PWM2_G87, 1, 10, 3, 2, false)
-MUX_CFG(DM365, PWM2_G88, 1, 8, 3, 2, false)
-MUX_CFG(DM365, PWM2_G89, 1, 6, 3, 2, false)
-MUX_CFG(DM365, PWM2_G90, 1, 4, 3, 2, false)
-MUX_CFG(DM365, PWM3_G80, 1, 20, 3, 3, false)
-MUX_CFG(DM365, PWM3_G81, 1, 18, 3, 3, false)
-MUX_CFG(DM365, PWM3_G85, 1, 14, 3, 2, false)
-MUX_CFG(DM365, PWM3_G86, 1, 12, 3, 2, false)
-
-MUX_CFG(DM365, SPI1_SCLK, 4, 2, 3, 1, false)
-MUX_CFG(DM365, SPI1_SDI, 3, 31, 1, 1, false)
-MUX_CFG(DM365, SPI1_SDO, 4, 0, 3, 1, false)
-MUX_CFG(DM365, SPI1_SDENA0, 4, 4, 3, 1, false)
-MUX_CFG(DM365, SPI1_SDENA1, 4, 0, 3, 2, false)
-
-MUX_CFG(DM365, SPI2_SCLK, 4, 10, 3, 1, false)
-MUX_CFG(DM365, SPI2_SDI, 4, 6, 3, 1, false)
-MUX_CFG(DM365, SPI2_SDO, 4, 8, 3, 1, false)
-MUX_CFG(DM365, SPI2_SDENA0, 4, 12, 3, 1, false)
-MUX_CFG(DM365, SPI2_SDENA1, 4, 8, 3, 2, false)
-
-MUX_CFG(DM365, SPI3_SCLK, 0, 0, 3, 2, false)
-MUX_CFG(DM365, SPI3_SDI, 0, 2, 3, 2, false)
-MUX_CFG(DM365, SPI3_SDO, 0, 6, 3, 2, false)
-MUX_CFG(DM365, SPI3_SDENA0, 0, 4, 3, 2, false)
-MUX_CFG(DM365, SPI3_SDENA1, 0, 6, 3, 3, false)
-
-MUX_CFG(DM365, SPI4_SCLK, 4, 18, 3, 1, false)
-MUX_CFG(DM365, SPI4_SDI, 4, 14, 3, 1, false)
-MUX_CFG(DM365, SPI4_SDO, 4, 16, 3, 1, false)
-MUX_CFG(DM365, SPI4_SDENA0, 4, 20, 3, 1, false)
-MUX_CFG(DM365, SPI4_SDENA1, 4, 16, 3, 2, false)
-
-MUX_CFG(DM365, CLKOUT0, 4, 20, 3, 3, false)
-MUX_CFG(DM365, CLKOUT1, 4, 16, 3, 3, false)
-MUX_CFG(DM365, CLKOUT2, 4, 8, 3, 3, false)
-
-MUX_CFG(DM365, GPIO20, 3, 21, 3, 0, false)
-MUX_CFG(DM365, GPIO30, 4, 6, 3, 0, false)
-MUX_CFG(DM365, GPIO31, 4, 8, 3, 0, false)
-MUX_CFG(DM365, GPIO32, 4, 10, 3, 0, false)
-MUX_CFG(DM365, GPIO33, 4, 12, 3, 0, false)
-MUX_CFG(DM365, GPIO40, 4, 26, 3, 0, false)
-MUX_CFG(DM365, GPIO64_57, 2, 6, 1, 0, false)
-
-MUX_CFG(DM365, VOUT_FIELD, 1, 18, 3, 1, false)
-MUX_CFG(DM365, VOUT_FIELD_G81, 1, 18, 3, 0, false)
-MUX_CFG(DM365, VOUT_HVSYNC, 1, 16, 1, 0, false)
-MUX_CFG(DM365, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false)
-MUX_CFG(DM365, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false)
-MUX_CFG(DM365, VIN_CAM_WEN, 0, 14, 3, 0, false)
-MUX_CFG(DM365, VIN_CAM_VD, 0, 13, 1, 0, false)
-MUX_CFG(DM365, VIN_CAM_HD, 0, 12, 1, 0, false)
-MUX_CFG(DM365, VIN_YIN4_7_EN, 0, 0, 0xff, 0, false)
-MUX_CFG(DM365, VIN_YIN0_3_EN, 0, 8, 0xf, 0, false)
-
-INT_CFG(DM365, INT_EDMA_CC, 2, 1, 1, false)
-INT_CFG(DM365, INT_EDMA_TC0_ERR, 3, 1, 1, false)
-INT_CFG(DM365, INT_EDMA_TC1_ERR, 4, 1, 1, false)
-INT_CFG(DM365, INT_EDMA_TC2_ERR, 22, 1, 1, false)
-INT_CFG(DM365, INT_EDMA_TC3_ERR, 23, 1, 1, false)
-INT_CFG(DM365, INT_PRTCSS, 10, 1, 1, false)
-INT_CFG(DM365, INT_EMAC_RXTHRESH, 14, 1, 1, false)
-INT_CFG(DM365, INT_EMAC_RXPULSE, 15, 1, 1, false)
-INT_CFG(DM365, INT_EMAC_TXPULSE, 16, 1, 1, false)
-INT_CFG(DM365, INT_EMAC_MISCPULSE, 17, 1, 1, false)
-INT_CFG(DM365, INT_IMX0_ENABLE, 0, 1, 0, false)
-INT_CFG(DM365, INT_IMX0_DISABLE, 0, 1, 1, false)
-INT_CFG(DM365, INT_HDVICP_ENABLE, 0, 1, 1, false)
-INT_CFG(DM365, INT_HDVICP_DISABLE, 0, 1, 0, false)
-INT_CFG(DM365, INT_IMX1_ENABLE, 24, 1, 1, false)
-INT_CFG(DM365, INT_IMX1_DISABLE, 24, 1, 0, false)
-INT_CFG(DM365, INT_NSF_ENABLE, 25, 1, 1, false)
-INT_CFG(DM365, INT_NSF_DISABLE, 25, 1, 0, false)
-
-EVT_CFG(DM365, EVT2_ASP_TX, 0, 1, 0, false)
-EVT_CFG(DM365, EVT3_ASP_RX, 1, 1, 0, false)
-EVT_CFG(DM365, EVT2_VC_TX, 0, 1, 1, false)
-EVT_CFG(DM365, EVT3_VC_RX, 1, 1, 1, false)
-#endif
-};
-
-static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
-
-static struct davinci_spi_platform_data dm365_spi0_pdata = {
- .version = SPI_VERSION_1,
- .num_chipselect = 2,
- .dma_event_q = EVENTQ_3,
- .prescaler_limit = 1,
-};
-
-static struct resource dm365_spi0_resources[] = {
- {
- .start = 0x01c66000,
- .end = 0x01c667ff,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM365_SPIINT0_0),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device dm365_spi0_device = {
- .name = "spi_davinci",
- .id = 0,
- .dev = {
- .dma_mask = &dm365_spi0_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &dm365_spi0_pdata,
- },
- .num_resources = ARRAY_SIZE(dm365_spi0_resources),
- .resource = dm365_spi0_resources,
-};
-
-void __init dm365_init_spi0(unsigned chipselect_mask,
- const struct spi_board_info *info, unsigned len)
-{
- davinci_cfg_reg(DM365_SPI0_SCLK);
- davinci_cfg_reg(DM365_SPI0_SDI);
- davinci_cfg_reg(DM365_SPI0_SDO);
-
- /* not all slaves will be wired up */
- if (chipselect_mask & BIT(0))
- davinci_cfg_reg(DM365_SPI0_SDENA0);
- if (chipselect_mask & BIT(1))
- davinci_cfg_reg(DM365_SPI0_SDENA1);
-
- spi_register_board_info(info, len);
-
- platform_device_register(&dm365_spi0_device);
-}
-
-static struct resource dm365_gpio_resources[] = {
- { /* registers */
- .start = DAVINCI_GPIO_BASE,
- .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
- { /* interrupt */
- .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO0),
- .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO0),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO1),
- .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO1),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO2),
- .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO2),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO3),
- .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO3),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO4),
- .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO4),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO5),
- .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO5),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO6),
- .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO6),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO7),
- .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO7),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct davinci_gpio_platform_data dm365_gpio_platform_data = {
- .no_auto_base = true,
- .base = 0,
- .ngpio = 104,
- .gpio_unbanked = 8,
-};
-
-int __init dm365_gpio_register(void)
-{
- return davinci_gpio_register(dm365_gpio_resources,
- ARRAY_SIZE(dm365_gpio_resources),
- &dm365_gpio_platform_data);
-}
-
-static struct emac_platform_data dm365_emac_pdata = {
- .ctrl_reg_offset = DM365_EMAC_CNTRL_OFFSET,
- .ctrl_mod_reg_offset = DM365_EMAC_CNTRL_MOD_OFFSET,
- .ctrl_ram_offset = DM365_EMAC_CNTRL_RAM_OFFSET,
- .ctrl_ram_size = DM365_EMAC_CNTRL_RAM_SIZE,
- .version = EMAC_VERSION_2,
-};
-
-static struct resource dm365_emac_resources[] = {
- {
- .start = DM365_EMAC_BASE,
- .end = DM365_EMAC_BASE + SZ_16K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXTHRESH),
- .end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXTHRESH),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXPULSE),
- .end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXPULSE),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_TXPULSE),
- .end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_TXPULSE),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_MISCPULSE),
- .end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_MISCPULSE),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device dm365_emac_device = {
- .name = "davinci_emac",
- .id = 1,
- .dev = {
- .platform_data = &dm365_emac_pdata,
- },
- .num_resources = ARRAY_SIZE(dm365_emac_resources),
- .resource = dm365_emac_resources,
-};
-
-static struct resource dm365_mdio_resources[] = {
- {
- .start = DM365_EMAC_MDIO_BASE,
- .end = DM365_EMAC_MDIO_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device dm365_mdio_device = {
- .name = "davinci_mdio",
- .id = 0,
- .num_resources = ARRAY_SIZE(dm365_mdio_resources),
- .resource = dm365_mdio_resources,
-};
-
-static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
- [IRQ_VDINT0] = 2,
- [IRQ_VDINT1] = 6,
- [IRQ_VDINT2] = 6,
- [IRQ_HISTINT] = 6,
- [IRQ_H3AINT] = 6,
- [IRQ_PRVUINT] = 6,
- [IRQ_RSZINT] = 6,
- [IRQ_DM365_INSFINT] = 7,
- [IRQ_VENCINT] = 6,
- [IRQ_ASQINT] = 6,
- [IRQ_IMXINT] = 6,
- [IRQ_DM365_IMCOPINT] = 4,
- [IRQ_USBINT] = 4,
- [IRQ_DM365_RTOINT] = 7,
- [IRQ_DM365_TINT5] = 7,
- [IRQ_DM365_TINT6] = 5,
- [IRQ_CCINT0] = 5,
- [IRQ_CCERRINT] = 5,
- [IRQ_TCERRINT0] = 5,
- [IRQ_TCERRINT] = 7,
- [IRQ_PSCIN] = 4,
- [IRQ_DM365_SPINT2_1] = 7,
- [IRQ_DM365_TINT7] = 7,
- [IRQ_DM365_SDIOINT0] = 7,
- [IRQ_MBXINT] = 7,
- [IRQ_MBRINT] = 7,
- [IRQ_MMCINT] = 7,
- [IRQ_DM365_MMCINT1] = 7,
- [IRQ_DM365_PWMINT3] = 7,
- [IRQ_AEMIFINT] = 2,
- [IRQ_DM365_SDIOINT1] = 2,
- [IRQ_TINT0_TINT12] = 7,
- [IRQ_TINT0_TINT34] = 7,
- [IRQ_TINT1_TINT12] = 7,
- [IRQ_TINT1_TINT34] = 7,
- [IRQ_PWMINT0] = 7,
- [IRQ_PWMINT1] = 3,
- [IRQ_PWMINT2] = 3,
- [IRQ_I2C] = 3,
- [IRQ_UARTINT0] = 3,
- [IRQ_UARTINT1] = 3,
- [IRQ_DM365_RTCINT] = 3,
- [IRQ_DM365_SPIINT0_0] = 3,
- [IRQ_DM365_SPIINT3_0] = 3,
- [IRQ_DM365_GPIO0] = 3,
- [IRQ_DM365_GPIO1] = 7,
- [IRQ_DM365_GPIO2] = 4,
- [IRQ_DM365_GPIO3] = 4,
- [IRQ_DM365_GPIO4] = 7,
- [IRQ_DM365_GPIO5] = 7,
- [IRQ_DM365_GPIO6] = 7,
- [IRQ_DM365_GPIO7] = 7,
- [IRQ_DM365_EMAC_RXTHRESH] = 7,
- [IRQ_DM365_EMAC_RXPULSE] = 7,
- [IRQ_DM365_EMAC_TXPULSE] = 7,
- [IRQ_DM365_EMAC_MISCPULSE] = 7,
- [IRQ_DM365_GPIO12] = 7,
- [IRQ_DM365_GPIO13] = 7,
- [IRQ_DM365_GPIO14] = 7,
- [IRQ_DM365_GPIO15] = 7,
- [IRQ_DM365_KEYINT] = 7,
- [IRQ_DM365_TCERRINT2] = 7,
- [IRQ_DM365_TCERRINT3] = 7,
- [IRQ_DM365_EMUINT] = 7,
-};
-
-/* Four Transfer Controllers on DM365 */
-static s8 dm365_queue_priority_mapping[][2] = {
- /* {event queue no, Priority} */
- {0, 7},
- {1, 7},
- {2, 7},
- {3, 0},
- {-1, -1},
-};
-
-static const struct dma_slave_map dm365_edma_map[] = {
- { "davinci-mcbsp", "tx", EDMA_FILTER_PARAM(0, 2) },
- { "davinci-mcbsp", "rx", EDMA_FILTER_PARAM(0, 3) },
- { "davinci_voicecodec", "tx", EDMA_FILTER_PARAM(0, 2) },
- { "davinci_voicecodec", "rx", EDMA_FILTER_PARAM(0, 3) },
- { "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) },
- { "spi_davinci.2", "rx", EDMA_FILTER_PARAM(0, 11) },
- { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 14) },
- { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 15) },
- { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 16) },
- { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) },
- { "spi_davinci.3", "tx", EDMA_FILTER_PARAM(0, 18) },
- { "spi_davinci.3", "rx", EDMA_FILTER_PARAM(0, 19) },
- { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
- { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
- { "da830-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) },
- { "da830-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) },
-};
-
-static struct edma_soc_info dm365_edma_pdata = {
- .queue_priority_mapping = dm365_queue_priority_mapping,
- .default_queue = EVENTQ_3,
- .slave_map = dm365_edma_map,
- .slavecnt = ARRAY_SIZE(dm365_edma_map),
-};
-
-static struct resource edma_resources[] = {
- {
- .name = "edma3_cc",
- .start = 0x01c00000,
- .end = 0x01c00000 + SZ_64K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "edma3_tc0",
- .start = 0x01c10000,
- .end = 0x01c10000 + SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "edma3_tc1",
- .start = 0x01c10400,
- .end = 0x01c10400 + SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "edma3_tc2",
- .start = 0x01c10800,
- .end = 0x01c10800 + SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "edma3_tc3",
- .start = 0x01c10c00,
- .end = 0x01c10c00 + SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "edma3_ccint",
- .start = DAVINCI_INTC_IRQ(IRQ_CCINT0),
- .flags = IORESOURCE_IRQ,
- },
- {
- .name = "edma3_ccerrint",
- .start = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
- .flags = IORESOURCE_IRQ,
- },
- /* not using TC*_ERR */
-};
-
-static const struct platform_device_info dm365_edma_device __initconst = {
- .name = "edma",
- .id = 0,
- .dma_mask = DMA_BIT_MASK(32),
- .res = edma_resources,
- .num_res = ARRAY_SIZE(edma_resources),
- .data = &dm365_edma_pdata,
- .size_data = sizeof(dm365_edma_pdata),
-};
-
-static struct resource dm365_asp_resources[] = {
- {
- .name = "mpu",
- .start = DAVINCI_DM365_ASP0_BASE,
- .end = DAVINCI_DM365_ASP0_BASE + SZ_8K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DAVINCI_DMA_ASP0_TX,
- .end = DAVINCI_DMA_ASP0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = DAVINCI_DMA_ASP0_RX,
- .end = DAVINCI_DMA_ASP0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device dm365_asp_device = {
- .name = "davinci-mcbsp",
- .id = -1,
- .num_resources = ARRAY_SIZE(dm365_asp_resources),
- .resource = dm365_asp_resources,
-};
-
-static struct resource dm365_vc_resources[] = {
- {
- .start = DAVINCI_DM365_VC_BASE,
- .end = DAVINCI_DM365_VC_BASE + SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DAVINCI_DMA_VC_TX,
- .end = DAVINCI_DMA_VC_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = DAVINCI_DMA_VC_RX,
- .end = DAVINCI_DMA_VC_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device dm365_vc_device = {
- .name = "davinci_voicecodec",
- .id = -1,
- .num_resources = ARRAY_SIZE(dm365_vc_resources),
- .resource = dm365_vc_resources,
-};
-
-static struct resource dm365_rtc_resources[] = {
- {
- .start = DM365_RTC_BASE,
- .end = DM365_RTC_BASE + SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM365_RTCINT),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device dm365_rtc_device = {
- .name = "rtc_davinci",
- .id = 0,
- .num_resources = ARRAY_SIZE(dm365_rtc_resources),
- .resource = dm365_rtc_resources,
-};
-
-static struct map_desc dm365_io_desc[] = {
- {
- .virtual = IO_VIRT,
- .pfn = __phys_to_pfn(IO_PHYS),
- .length = IO_SIZE,
- .type = MT_DEVICE
- },
-};
-
-static struct resource dm365_ks_resources[] = {
- {
- /* registers */
- .start = DM365_KEYSCAN_BASE,
- .end = DM365_KEYSCAN_BASE + SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- /* interrupt */
- .start = DAVINCI_INTC_IRQ(IRQ_DM365_KEYINT),
- .end = DAVINCI_INTC_IRQ(IRQ_DM365_KEYINT),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device dm365_ks_device = {
- .name = "davinci_keyscan",
- .id = 0,
- .num_resources = ARRAY_SIZE(dm365_ks_resources),
- .resource = dm365_ks_resources,
-};
-
-/* Contents of JTAG ID register used to identify exact cpu type */
-static struct davinci_id dm365_ids[] = {
- {
- .variant = 0x0,
- .part_no = 0xb83e,
- .manufacturer = 0x017,
- .cpu_id = DAVINCI_CPU_ID_DM365,
- .name = "dm365_rev1.1",
- },
- {
- .variant = 0x8,
- .part_no = 0xb83e,
- .manufacturer = 0x017,
- .cpu_id = DAVINCI_CPU_ID_DM365,
- .name = "dm365_rev1.2",
- },
-};
-
-/*
- * Bottom half of timer0 is used for clockevent, top half is used for
- * clocksource.
- */
-static const struct davinci_timer_cfg dm365_timer_cfg = {
- .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_128),
- .irq = {
- DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
- DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
- },
-};
-
-#define DM365_UART1_BASE (IO_PHYS + 0x106000)
-
-static struct plat_serial8250_port dm365_serial0_platform_data[] = {
- {
- .mapbase = DAVINCI_UART0_BASE,
- .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
- UPF_IOREMAP,
- .iotype = UPIO_MEM,
- .regshift = 2,
- },
- {
- .flags = 0,
- }
-};
-static struct plat_serial8250_port dm365_serial1_platform_data[] = {
- {
- .mapbase = DM365_UART1_BASE,
- .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
- UPF_IOREMAP,
- .iotype = UPIO_MEM,
- .regshift = 2,
- },
- {
- .flags = 0,
- }
-};
-
-struct platform_device dm365_serial_device[] = {
- {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM,
- .dev = {
- .platform_data = dm365_serial0_platform_data,
- }
- },
- {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM1,
- .dev = {
- .platform_data = dm365_serial1_platform_data,
- }
- },
- {
- }
-};
-
-static const struct davinci_soc_info davinci_soc_info_dm365 = {
- .io_desc = dm365_io_desc,
- .io_desc_num = ARRAY_SIZE(dm365_io_desc),
- .jtag_id_reg = 0x01c40028,
- .ids = dm365_ids,
- .ids_num = ARRAY_SIZE(dm365_ids),
- .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
- .pinmux_pins = dm365_pins,
- .pinmux_pins_num = ARRAY_SIZE(dm365_pins),
- .emac_pdata = &dm365_emac_pdata,
- .sram_dma = 0x00010000,
- .sram_len = SZ_32K,
-};
-
-void __init dm365_init_asp(void)
-{
- davinci_cfg_reg(DM365_MCBSP0_BDX);
- davinci_cfg_reg(DM365_MCBSP0_X);
- davinci_cfg_reg(DM365_MCBSP0_BFSX);
- davinci_cfg_reg(DM365_MCBSP0_BDR);
- davinci_cfg_reg(DM365_MCBSP0_R);
- davinci_cfg_reg(DM365_MCBSP0_BFSR);
- davinci_cfg_reg(DM365_EVT2_ASP_TX);
- davinci_cfg_reg(DM365_EVT3_ASP_RX);
- platform_device_register(&dm365_asp_device);
-}
-
-void __init dm365_init_vc(void)
-{
- davinci_cfg_reg(DM365_EVT2_VC_TX);
- davinci_cfg_reg(DM365_EVT3_VC_RX);
- platform_device_register(&dm365_vc_device);
-}
-
-void __init dm365_init_ks(struct davinci_ks_platform_data *pdata)
-{
- dm365_ks_device.dev.platform_data = pdata;
- platform_device_register(&dm365_ks_device);
-}
-
-void __init dm365_init_rtc(void)
-{
- davinci_cfg_reg(DM365_INT_PRTCSS);
- platform_device_register(&dm365_rtc_device);
-}
-
-void __init dm365_init(void)
-{
- davinci_common_init(&davinci_soc_info_dm365);
- davinci_map_sysmod();
-}
-
-void __init dm365_init_time(void)
-{
- void __iomem *pll1, *pll2, *psc;
- struct clk *clk;
- int rv;
-
- clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM365_REF_FREQ);
-
- pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
- dm365_pll1_init(NULL, pll1, NULL);
-
- pll2 = ioremap(DAVINCI_PLL2_BASE, SZ_1K);
- dm365_pll2_init(NULL, pll2, NULL);
-
- psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
- dm365_psc_init(NULL, psc);
-
- clk = clk_get(NULL, "timer0");
- if (WARN_ON(IS_ERR(clk))) {
- pr_err("Unable to get the timer clock\n");
- return;
- }
-
- rv = davinci_timer_register(clk, &dm365_timer_cfg);
- WARN(rv, "Unable to register the timer: %d\n", rv);
-}
-
-void __init dm365_register_clocks(void)
-{
- /* all clocks are currently registered in dm365_init_time() */
-}
-
-static struct resource dm365_vpss_resources[] = {
- {
- /* VPSS ISP5 Base address */
- .name = "isp5",
- .start = 0x01c70000,
- .end = 0x01c70000 + 0xff,
- .flags = IORESOURCE_MEM,
- },
- {
- /* VPSS CLK Base address */
- .name = "vpss",
- .start = 0x01c70200,
- .end = 0x01c70200 + 0xff,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device dm365_vpss_device = {
- .name = "vpss",
- .id = -1,
- .dev.platform_data = "dm365_vpss",
- .num_resources = ARRAY_SIZE(dm365_vpss_resources),
- .resource = dm365_vpss_resources,
-};
-
-static struct resource vpfe_resources[] = {
- {
- .start = DAVINCI_INTC_IRQ(IRQ_VDINT0),
- .end = DAVINCI_INTC_IRQ(IRQ_VDINT0),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_VDINT1),
- .end = DAVINCI_INTC_IRQ(IRQ_VDINT1),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
-static struct platform_device vpfe_capture_dev = {
- .name = CAPTURE_DRV_NAME,
- .id = -1,
- .num_resources = ARRAY_SIZE(vpfe_resources),
- .resource = vpfe_resources,
- .dev = {
- .dma_mask = &vpfe_capture_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-};
-
-static void dm365_isif_setup_pinmux(void)
-{
- davinci_cfg_reg(DM365_VIN_CAM_WEN);
- davinci_cfg_reg(DM365_VIN_CAM_VD);
- davinci_cfg_reg(DM365_VIN_CAM_HD);
- davinci_cfg_reg(DM365_VIN_YIN4_7_EN);
- davinci_cfg_reg(DM365_VIN_YIN0_3_EN);
-}
-
-static struct resource isif_resource[] = {
- /* ISIF Base address */
- {
- .start = 0x01c71000,
- .end = 0x01c71000 + 0x1ff,
- .flags = IORESOURCE_MEM,
- },
- /* ISIF Linearization table 0 */
- {
- .start = 0x1C7C000,
- .end = 0x1C7C000 + 0x2ff,
- .flags = IORESOURCE_MEM,
- },
- /* ISIF Linearization table 1 */
- {
- .start = 0x1C7C400,
- .end = 0x1C7C400 + 0x2ff,
- .flags = IORESOURCE_MEM,
- },
-};
-static struct platform_device dm365_isif_dev = {
- .name = "isif",
- .id = -1,
- .num_resources = ARRAY_SIZE(isif_resource),
- .resource = isif_resource,
- .dev = {
- .dma_mask = &vpfe_capture_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = dm365_isif_setup_pinmux,
- },
-};
-
-static struct resource dm365_osd_resources[] = {
- {
- .start = DM365_OSD_BASE,
- .end = DM365_OSD_BASE + 0xff,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static u64 dm365_video_dma_mask = DMA_BIT_MASK(32);
-
-static struct platform_device dm365_osd_dev = {
- .name = DM365_VPBE_OSD_SUBDEV_NAME,
- .id = -1,
- .num_resources = ARRAY_SIZE(dm365_osd_resources),
- .resource = dm365_osd_resources,
- .dev = {
- .dma_mask = &dm365_video_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-};
-
-static struct resource dm365_venc_resources[] = {
- {
- .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
- .end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
- .flags = IORESOURCE_IRQ,
- },
- /* venc registers io space */
- {
- .start = DM365_VENC_BASE,
- .end = DM365_VENC_BASE + 0x177,
- .flags = IORESOURCE_MEM,
- },
- /* vdaccfg registers io space */
- {
- .start = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG,
- .end = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct resource dm365_v4l2_disp_resources[] = {
- {
- .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
- .end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
- .flags = IORESOURCE_IRQ,
- },
- /* venc registers io space */
- {
- .start = DM365_VENC_BASE,
- .end = DM365_VENC_BASE + 0x177,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static int dm365_vpbe_setup_pinmux(u32 if_type, int field)
-{
- switch (if_type) {
- case MEDIA_BUS_FMT_SGRBG8_1X8:
- davinci_cfg_reg(DM365_VOUT_FIELD_G81);
- davinci_cfg_reg(DM365_VOUT_COUTL_EN);
- davinci_cfg_reg(DM365_VOUT_COUTH_EN);
- break;
- case MEDIA_BUS_FMT_YUYV10_1X20:
- if (field)
- davinci_cfg_reg(DM365_VOUT_FIELD);
- else
- davinci_cfg_reg(DM365_VOUT_FIELD_G81);
- davinci_cfg_reg(DM365_VOUT_COUTL_EN);
- davinci_cfg_reg(DM365_VOUT_COUTH_EN);
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int dm365_venc_setup_clock(enum vpbe_enc_timings_type type,
- unsigned int pclock)
-{
- void __iomem *vpss_clkctl_reg;
- u32 val;
-
- vpss_clkctl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL);
-
- switch (type) {
- case VPBE_ENC_STD:
- val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
- break;
- case VPBE_ENC_DV_TIMINGS:
- if (pclock <= 27000000) {
- val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
- } else {
- /* set sysclk4 to output 74.25 MHz from pll1 */
- val = VPSS_PLLC2SYSCLK5_ENABLE | VPSS_DACCLKEN_ENABLE |
- VPSS_VENCCLKEN_ENABLE;
- }
- break;
- default:
- return -EINVAL;
- }
- writel(val, vpss_clkctl_reg);
-
- return 0;
-}
-
-static struct platform_device dm365_vpbe_display = {
- .name = "vpbe-v4l2",
- .id = -1,
- .num_resources = ARRAY_SIZE(dm365_v4l2_disp_resources),
- .resource = dm365_v4l2_disp_resources,
- .dev = {
- .dma_mask = &dm365_video_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-};
-
-static struct venc_platform_data dm365_venc_pdata = {
- .setup_pinmux = dm365_vpbe_setup_pinmux,
- .setup_clock = dm365_venc_setup_clock,
-};
-
-static struct platform_device dm365_venc_dev = {
- .name = DM365_VPBE_VENC_SUBDEV_NAME,
- .id = -1,
- .num_resources = ARRAY_SIZE(dm365_venc_resources),
- .resource = dm365_venc_resources,
- .dev = {
- .dma_mask = &dm365_video_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = (void *)&dm365_venc_pdata,
- },
-};
-
-static struct platform_device dm365_vpbe_dev = {
- .name = "vpbe_controller",
- .id = -1,
- .dev = {
- .dma_mask = &dm365_video_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-};
-
-int __init dm365_init_video(struct vpfe_config *vpfe_cfg,
- struct vpbe_config *vpbe_cfg)
-{
- if (vpfe_cfg || vpbe_cfg)
- platform_device_register(&dm365_vpss_device);
-
- if (vpfe_cfg) {
- vpfe_capture_dev.dev.platform_data = vpfe_cfg;
- platform_device_register(&dm365_isif_dev);
- platform_device_register(&vpfe_capture_dev);
- }
- if (vpbe_cfg) {
- dm365_vpbe_dev.dev.platform_data = vpbe_cfg;
- platform_device_register(&dm365_osd_dev);
- platform_device_register(&dm365_venc_dev);
- platform_device_register(&dm365_vpbe_dev);
- platform_device_register(&dm365_vpbe_display);
- }
-
- return 0;
-}
-
-static const struct davinci_aintc_config dm365_aintc_config = {
- .reg = {
- .start = DAVINCI_ARM_INTC_BASE,
- .end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
- .num_irqs = 64,
- .prios = dm365_default_priorities,
-};
-
-void __init dm365_init_irq(void)
-{
- davinci_aintc_init(&dm365_aintc_config);
-}
-
-static int __init dm365_init_devices(void)
-{
- struct platform_device *edma_pdev;
- int ret = 0;
-
- if (!cpu_is_davinci_dm365())
- return 0;
-
- davinci_cfg_reg(DM365_INT_EDMA_CC);
- edma_pdev = platform_device_register_full(&dm365_edma_device);
- if (IS_ERR(edma_pdev)) {
- pr_warn("%s: Failed to register eDMA\n", __func__);
- return PTR_ERR(edma_pdev);
- }
-
- platform_device_register(&dm365_mdio_device);
- platform_device_register(&dm365_emac_device);
-
- ret = davinci_init_wdt();
- if (ret)
- pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
-
- return ret;
-}
-postcore_initcall(dm365_init_devices);
--
2.29.2
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCH 02/14] ARM: davinci: drop DAVINCI_DMxxx references
2022-10-19 15:29 [PATCH 00/14] ARM: remove unused davinci board & drivers Arnd Bergmann
2022-10-19 15:29 ` [PATCH 01/14] ARM: davinci: remove unused board support Arnd Bergmann
@ 2022-10-19 15:29 ` Arnd Bergmann
2022-10-19 16:37 ` David Lechner
2022-10-27 1:10 ` Stephen Boyd
2022-10-19 15:29 ` [PATCH 03/14] ARM: davinci: clean up platform support Arnd Bergmann
` (14 subsequent siblings)
16 siblings, 2 replies; 48+ messages in thread
From: Arnd Bergmann @ 2022-10-19 15:29 UTC (permalink / raw)
To: Sekhar Nori, Bartosz Golaszewski, linux-arm-kernel,
David Lechner, Michael Turquette, Stephen Boyd
Cc: linux-kernel, Kevin Hilman, Arnd Bergmann, linux-clk
From: Arnd Bergmann <arnd@arndb.de>
Support for all the dm3xx/dm64xx SoCs is no longer
available, so drop all other references to those.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
arch/arm/mach-davinci/cputype.h | 32 --------------------------------
arch/arm/mach-davinci/serial.c | 4 ----
arch/arm/mach-davinci/usb.c | 13 -------------
drivers/clk/davinci/pll.c | 8 --------
drivers/clk/davinci/pll.h | 5 -----
drivers/clk/davinci/psc.c | 6 ------
drivers/clk/davinci/psc.h | 7 -------
include/linux/clk/davinci.h | 9 ---------
8 files changed, 84 deletions(-)
diff --git a/arch/arm/mach-davinci/cputype.h b/arch/arm/mach-davinci/cputype.h
index 4590afdbe449..87ee56068a16 100644
--- a/arch/arm/mach-davinci/cputype.h
+++ b/arch/arm/mach-davinci/cputype.h
@@ -25,10 +25,6 @@ struct davinci_id {
};
/* Can use lower 16 bits of cpu id for a variant when required */
-#define DAVINCI_CPU_ID_DM6446 0x64460000
-#define DAVINCI_CPU_ID_DM6467 0x64670000
-#define DAVINCI_CPU_ID_DM355 0x03550000
-#define DAVINCI_CPU_ID_DM365 0x03650000
#define DAVINCI_CPU_ID_DA830 0x08300000
#define DAVINCI_CPU_ID_DA850 0x08500000
@@ -38,37 +34,9 @@ static inline int is_davinci_ ##type(void) \
return (davinci_soc_info.cpu_id == (id)); \
}
-IS_DAVINCI_CPU(dm644x, DAVINCI_CPU_ID_DM6446)
-IS_DAVINCI_CPU(dm646x, DAVINCI_CPU_ID_DM6467)
-IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355)
-IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365)
IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830)
IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850)
-#ifdef CONFIG_ARCH_DAVINCI_DM644x
-#define cpu_is_davinci_dm644x() is_davinci_dm644x()
-#else
-#define cpu_is_davinci_dm644x() 0
-#endif
-
-#ifdef CONFIG_ARCH_DAVINCI_DM646x
-#define cpu_is_davinci_dm646x() is_davinci_dm646x()
-#else
-#define cpu_is_davinci_dm646x() 0
-#endif
-
-#ifdef CONFIG_ARCH_DAVINCI_DM355
-#define cpu_is_davinci_dm355() is_davinci_dm355()
-#else
-#define cpu_is_davinci_dm355() 0
-#endif
-
-#ifdef CONFIG_ARCH_DAVINCI_DM365
-#define cpu_is_davinci_dm365() is_davinci_dm365()
-#else
-#define cpu_is_davinci_dm365() 0
-#endif
-
#ifdef CONFIG_ARCH_DAVINCI_DA830
#define cpu_is_davinci_da830() is_davinci_da830()
#else
diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c
index 7f7814807bb5..ac1929bb0ef2 100644
--- a/arch/arm/mach-davinci/serial.c
+++ b/arch/arm/mach-davinci/serial.c
@@ -40,10 +40,6 @@ static void __init davinci_serial_reset(struct plat_serial8250_port *p)
pwremu |= (0x3 << 13);
pwremu |= 0x1;
serial_write_reg(p, UART_DAVINCI_PWREMU, pwremu);
-
- if (cpu_is_davinci_dm646x())
- serial_write_reg(p, UART_DM646X_SCR,
- UART_DM646X_SCR_TX_WATERMARK);
}
int __init davinci_serial_init(struct platform_device *serial_dev)
diff --git a/arch/arm/mach-davinci/usb.c b/arch/arm/mach-davinci/usb.c
index a9e5c6e91e5d..9dc14c7977b3 100644
--- a/arch/arm/mach-davinci/usb.c
+++ b/arch/arm/mach-davinci/usb.c
@@ -41,11 +41,6 @@ static struct resource usb_resources[] = {
.flags = IORESOURCE_IRQ,
.name = "mc"
},
- {
- /* placeholder for the dedicated CPPI IRQ */
- .flags = IORESOURCE_IRQ,
- .name = "dma"
- },
};
static u64 usb_dmamask = DMA_BIT_MASK(32);
@@ -67,14 +62,6 @@ void __init davinci_setup_usb(unsigned mA, unsigned potpgt_ms)
usb_data.power = mA > 510 ? 255 : mA / 2;
usb_data.potpgt = (potpgt_ms + 1) / 2;
- if (cpu_is_davinci_dm646x()) {
- /* Override the defaults as DM6467 uses different IRQs. */
- usb_dev.resource[1].start = DAVINCI_INTC_IRQ(IRQ_DM646X_USBINT);
- usb_dev.resource[2].start = DAVINCI_INTC_IRQ(
- IRQ_DM646X_USBDMAINT);
- } else /* other devices don't have dedicated CPPI IRQ */
- usb_dev.num_resources = 2;
-
platform_device_register(&usb_dev);
}
diff --git a/drivers/clk/davinci/pll.c b/drivers/clk/davinci/pll.c
index f862f5e2b3fc..87bdf8879045 100644
--- a/drivers/clk/davinci/pll.c
+++ b/drivers/clk/davinci/pll.c
@@ -881,14 +881,6 @@ static const struct platform_device_id davinci_pll_id_table[] = {
#ifdef CONFIG_ARCH_DAVINCI_DA850
{ .name = "da850-pll0", .driver_data = (kernel_ulong_t)da850_pll0_init },
{ .name = "da850-pll1", .driver_data = (kernel_ulong_t)da850_pll1_init },
-#endif
-#ifdef CONFIG_ARCH_DAVINCI_DM355
- { .name = "dm355-pll1", .driver_data = (kernel_ulong_t)dm355_pll1_init },
- { .name = "dm355-pll2", .driver_data = (kernel_ulong_t)dm355_pll2_init },
-#endif
-#ifdef CONFIG_ARCH_DAVINCI_DM365
- { .name = "dm365-pll1", .driver_data = (kernel_ulong_t)dm365_pll1_init },
- { .name = "dm365-pll2", .driver_data = (kernel_ulong_t)dm365_pll2_init },
#endif
{ }
};
diff --git a/drivers/clk/davinci/pll.h b/drivers/clk/davinci/pll.h
index 1773277bc690..20bfcec2d3b5 100644
--- a/drivers/clk/davinci/pll.h
+++ b/drivers/clk/davinci/pll.h
@@ -122,13 +122,8 @@ int of_davinci_pll_init(struct device *dev, struct device_node *node,
/* Platform-specific callbacks */
-#ifdef CONFIG_ARCH_DAVINCI_DA850
int da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
void of_da850_pll0_init(struct device_node *node);
int of_da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
-#endif
-#ifdef CONFIG_ARCH_DAVINCI_DM355
-int dm355_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
-#endif
#endif /* __CLK_DAVINCI_PLL_H___ */
diff --git a/drivers/clk/davinci/psc.c b/drivers/clk/davinci/psc.c
index 42a59dbd49c8..cd85d9f158b0 100644
--- a/drivers/clk/davinci/psc.c
+++ b/drivers/clk/davinci/psc.c
@@ -510,12 +510,6 @@ static const struct platform_device_id davinci_psc_id_table[] = {
#ifdef CONFIG_ARCH_DAVINCI_DA850
{ .name = "da850-psc0", .driver_data = (kernel_ulong_t)&da850_psc0_init_data },
{ .name = "da850-psc1", .driver_data = (kernel_ulong_t)&da850_psc1_init_data },
-#endif
-#ifdef CONFIG_ARCH_DAVINCI_DM355
- { .name = "dm355-psc", .driver_data = (kernel_ulong_t)&dm355_psc_init_data },
-#endif
-#ifdef CONFIG_ARCH_DAVINCI_DM365
- { .name = "dm365-psc", .driver_data = (kernel_ulong_t)&dm365_psc_init_data },
#endif
{ }
};
diff --git a/drivers/clk/davinci/psc.h b/drivers/clk/davinci/psc.h
index 5e382b675518..bd23f6fd56df 100644
--- a/drivers/clk/davinci/psc.h
+++ b/drivers/clk/davinci/psc.h
@@ -104,11 +104,4 @@ extern const struct davinci_psc_init_data da850_psc1_init_data;
extern const struct davinci_psc_init_data of_da850_psc0_init_data;
extern const struct davinci_psc_init_data of_da850_psc1_init_data;
#endif
-#ifdef CONFIG_ARCH_DAVINCI_DM355
-extern const struct davinci_psc_init_data dm355_psc_init_data;
-#endif
-#ifdef CONFIG_ARCH_DAVINCI_DM365
-extern const struct davinci_psc_init_data dm365_psc_init_data;
-#endif
-
#endif /* __CLK_DAVINCI_PSC_H__ */
diff --git a/include/linux/clk/davinci.h b/include/linux/clk/davinci.h
index f6ebab6228c2..e1d37451e03f 100644
--- a/include/linux/clk/davinci.h
+++ b/include/linux/clk/davinci.h
@@ -19,14 +19,5 @@ int da830_pll_init(struct device *dev, void __iomem *base, struct regmap *cfgchi
#ifdef CONFIG_ARCH_DAVINCI_DA850
int da850_pll0_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
#endif
-#ifdef CONFIG_ARCH_DAVINCI_DM355
-int dm355_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
-int dm355_psc_init(struct device *dev, void __iomem *base);
-#endif
-#ifdef CONFIG_ARCH_DAVINCI_DM365
-int dm365_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
-int dm365_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
-int dm365_psc_init(struct device *dev, void __iomem *base);
-#endif
#endif /* __LINUX_CLK_DAVINCI_PLL_H___ */
--
2.29.2
^ permalink raw reply related [flat|nested] 48+ messages in thread* Re: [PATCH 02/14] ARM: davinci: drop DAVINCI_DMxxx references
2022-10-19 15:29 ` [PATCH 02/14] ARM: davinci: drop DAVINCI_DMxxx references Arnd Bergmann
@ 2022-10-19 16:37 ` David Lechner
2022-10-19 20:32 ` Arnd Bergmann
2022-10-27 1:10 ` Stephen Boyd
1 sibling, 1 reply; 48+ messages in thread
From: David Lechner @ 2022-10-19 16:37 UTC (permalink / raw)
To: Arnd Bergmann, Sekhar Nori, Bartosz Golaszewski,
linux-arm-kernel, Michael Turquette, Stephen Boyd
Cc: linux-kernel, Kevin Hilman, Arnd Bergmann, linux-clk
On 10/19/22 10:29 AM, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> Support for all the dm3xx/dm64xx SoCs is no longer
> available, so drop all other references to those.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
> int __init davinci_serial_init(struct platform_device *serial_dev)
> diff --git a/arch/arm/mach-davinci/usb.c b/arch/arm/mach-davinci/usb.c
> index a9e5c6e91e5d..9dc14c7977b3 100644
> --- a/arch/arm/mach-davinci/usb.c
> +++ b/arch/arm/mach-davinci/usb.c
> @@ -41,11 +41,6 @@ static struct resource usb_resources[] = {
> .flags = IORESOURCE_IRQ,
> .name = "mc"
> },
> - {
> - /* placeholder for the dedicated CPPI IRQ */
> - .flags = IORESOURCE_IRQ,
> - .name = "dma"
> - },
> };
>
> static u64 usb_dmamask = DMA_BIT_MASK(32);
> @@ -67,14 +62,6 @@ void __init davinci_setup_usb(unsigned mA, unsigned potpgt_ms)
> usb_data.power = mA > 510 ? 255 : mA / 2;
> usb_data.potpgt = (potpgt_ms + 1) / 2;
>
> - if (cpu_is_davinci_dm646x()) {
> - /* Override the defaults as DM6467 uses different IRQs. */
> - usb_dev.resource[1].start = DAVINCI_INTC_IRQ(IRQ_DM646X_USBINT);
> - usb_dev.resource[2].start = DAVINCI_INTC_IRQ(
> - IRQ_DM646X_USBDMAINT);
> - } else /* other devices don't have dedicated CPPI IRQ */
> - usb_dev.num_resources = 2;
> -
> platform_device_register(&usb_dev);
> }
>
Shouldn't the else case be kept since it applies to *all* "other devices"?
(and therfore the usb_resources shouldn't be modified either?)
^ permalink raw reply [flat|nested] 48+ messages in thread* Re: [PATCH 02/14] ARM: davinci: drop DAVINCI_DMxxx references
2022-10-19 16:37 ` David Lechner
@ 2022-10-19 20:32 ` Arnd Bergmann
0 siblings, 0 replies; 48+ messages in thread
From: Arnd Bergmann @ 2022-10-19 20:32 UTC (permalink / raw)
To: David Lechner, Arnd Bergmann, Sekhar Nori, Bartosz Golaszewski,
linux-arm-kernel, Michael Turquette, Stephen Boyd
Cc: linux-kernel, Kevin Hilman, linux-clk
On Wed, Oct 19, 2022, at 18:37, David Lechner wrote:
> On 10/19/22 10:29 AM, Arnd Bergmann wrote:
>> static u64 usb_dmamask = DMA_BIT_MASK(32);
>> @@ -67,14 +62,6 @@ void __init davinci_setup_usb(unsigned mA, unsigned potpgt_ms)
>> usb_data.power = mA > 510 ? 255 : mA / 2;
>> usb_data.potpgt = (potpgt_ms + 1) / 2;
>>
>> - if (cpu_is_davinci_dm646x()) {
>> - /* Override the defaults as DM6467 uses different IRQs. */
>> - usb_dev.resource[1].start = DAVINCI_INTC_IRQ(IRQ_DM646X_USBINT);
>> - usb_dev.resource[2].start = DAVINCI_INTC_IRQ(
>> - IRQ_DM646X_USBDMAINT);
>> - } else /* other devices don't have dedicated CPPI IRQ */
>> - usb_dev.num_resources = 2;
>> -
>> platform_device_register(&usb_dev);
>> }
>>
>
> Shouldn't the else case be kept since it applies to *all* "other devices"?
> (and therfore the usb_resources shouldn't be modified either?)
.num_resources is already initialized to 2 from ARRAY_SIZE(),
so it does not have to be changed afterwards.
Arnd
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 02/14] ARM: davinci: drop DAVINCI_DMxxx references
2022-10-19 15:29 ` [PATCH 02/14] ARM: davinci: drop DAVINCI_DMxxx references Arnd Bergmann
2022-10-19 16:37 ` David Lechner
@ 2022-10-27 1:10 ` Stephen Boyd
1 sibling, 0 replies; 48+ messages in thread
From: Stephen Boyd @ 2022-10-27 1:10 UTC (permalink / raw)
To: Arnd Bergmann, Bartosz Golaszewski, David Lechner,
Michael Turquette, Sekhar Nori, linux-arm-kernel
Cc: linux-kernel, Kevin Hilman, Arnd Bergmann, linux-clk
Quoting Arnd Bergmann (2022-10-19 08:29:28)
> From: Arnd Bergmann <arnd@arndb.de>
>
> Support for all the dm3xx/dm64xx SoCs is no longer
> available, so drop all other references to those.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
Acked-by: Stephen Boyd <sboyd@kernel.org>
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH 03/14] ARM: davinci: clean up platform support
2022-10-19 15:29 [PATCH 00/14] ARM: remove unused davinci board & drivers Arnd Bergmann
2022-10-19 15:29 ` [PATCH 01/14] ARM: davinci: remove unused board support Arnd Bergmann
2022-10-19 15:29 ` [PATCH 02/14] ARM: davinci: drop DAVINCI_DMxxx references Arnd Bergmann
@ 2022-10-19 15:29 ` Arnd Bergmann
2022-10-20 11:32 ` Bartosz Golaszewski
2022-10-19 15:29 ` [PATCH 04/14] clk: remove davinci dm3xx drivers Arnd Bergmann
` (13 subsequent siblings)
16 siblings, 1 reply; 48+ messages in thread
From: Arnd Bergmann @ 2022-10-19 15:29 UTC (permalink / raw)
To: Sekhar Nori, Bartosz Golaszewski, linux-arm-kernel
Cc: linux-kernel, Kevin Hilman, Arnd Bergmann
From: Arnd Bergmann <arnd@arndb.de>
With the board file support gone, and the platform using
DT only, a lot of the remaining code is no longer referenced
and can be removed.
Technically, the DT file only references DA850, but since that
is very similar to DA830, I'm leaving the latter.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
arch/arm/mach-davinci/Kconfig | 16 -
arch/arm/mach-davinci/Makefile | 9 +-
arch/arm/mach-davinci/asp.h | 57 --
arch/arm/mach-davinci/common.h | 7 +-
arch/arm/mach-davinci/cputype.h | 21 -
arch/arm/mach-davinci/da830.c | 274 -------
arch/arm/mach-davinci/da850.c | 400 +--------
arch/arm/mach-davinci/da8xx.h | 95 +--
arch/arm/mach-davinci/davinci.h | 136 ---
arch/arm/mach-davinci/devices-da8xx.c | 1095 -------------------------
arch/arm/mach-davinci/irqs.h | 217 -----
arch/arm/mach-davinci/mux.c | 15 -
arch/arm/mach-davinci/mux.h | 315 -------
arch/arm/mach-davinci/psc.h | 64 --
arch/arm/mach-davinci/serial.c | 88 --
arch/arm/mach-davinci/serial.h | 35 -
arch/arm/mach-davinci/usb-da8xx.c | 146 ----
arch/arm/mach-davinci/usb.c | 74 --
18 files changed, 11 insertions(+), 3053 deletions(-)
delete mode 100644 arch/arm/mach-davinci/asp.h
delete mode 100644 arch/arm/mach-davinci/davinci.h
delete mode 100644 arch/arm/mach-davinci/serial.c
delete mode 100644 arch/arm/mach-davinci/serial.h
delete mode 100644 arch/arm/mach-davinci/usb-da8xx.c
delete mode 100644 arch/arm/mach-davinci/usb.c
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 588213583051..4316e1370627 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -18,8 +18,6 @@ comment "DaVinci Core Type"
config ARCH_DAVINCI_DA830
bool "DA830/OMAP-L137/AM17x based system"
- depends on AUTO_ZRELADDR && ARM_PATCH_PHYS_VIRT
- depends on ATAGS
select ARCH_DAVINCI_DA8XX
# needed on silicon revs 1.0, 1.1:
select CPU_DCACHE_WRITETHROUGH if !CPU_DCACHE_DISABLE
@@ -27,25 +25,11 @@ config ARCH_DAVINCI_DA830
config ARCH_DAVINCI_DA850
bool "DA850/OMAP-L138/AM18x based system"
- depends on AUTO_ZRELADDR && ARM_PATCH_PHYS_VIRT
- depends on ATAGS
- select ARCH_DAVINCI_DA8XX
select DAVINCI_CP_INTC
config ARCH_DAVINCI_DA8XX
bool
-comment "DaVinci Board Type"
-
-config MACH_DA8XX_DT
- bool "Support DA8XX platforms using device tree"
- default y
- depends on ARCH_DAVINCI_DA850
- select PINCTRL
- help
- Say y here to include support for TI DaVinci DA850 based using
- Flattened Device Tree. More information at Documentation/devicetree
-
config DAVINCI_MUX
bool "DAVINCI multiplexing support"
depends on ARCH_DAVINCI
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 5b15a3bbf909..5ab1766fc306 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -5,16 +5,15 @@
#
#
# Common objects
-obj-y := serial.o usb.o common.o sram.o
+obj-y := common.o sram.o devices-da8xx.o
obj-$(CONFIG_DAVINCI_MUX) += mux.o
# Chip specific
-obj-$(CONFIG_ARCH_DAVINCI_DA830) += da830.o devices-da8xx.o usb-da8xx.o
-obj-$(CONFIG_ARCH_DAVINCI_DA850) += da850.o devices-da8xx.o usb-da8xx.o
+obj-$(CONFIG_ARCH_DAVINCI_DA830) += da830.o
+obj-$(CONFIG_ARCH_DAVINCI_DA850) += da850.o
-# Board specific
-obj-$(CONFIG_MACH_DA8XX_DT) += da8xx-dt.o pdata-quirks.o
+obj-y += da8xx-dt.o pdata-quirks.o
# Power Management
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
diff --git a/arch/arm/mach-davinci/asp.h b/arch/arm/mach-davinci/asp.h
deleted file mode 100644
index d0ecd1d0f084..000000000000
--- a/arch/arm/mach-davinci/asp.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * TI DaVinci Audio definitions
- */
-#ifndef __ASM_ARCH_DAVINCI_ASP_H
-#define __ASM_ARCH_DAVINCI_ASP_H
-
-/* Bases of dm644x and dm355 register banks */
-#define DAVINCI_ASP0_BASE 0x01E02000
-#define DAVINCI_ASP1_BASE 0x01E04000
-
-/* Bases of dm365 register banks */
-#define DAVINCI_DM365_ASP0_BASE 0x01D02000
-
-/* Bases of dm646x register banks */
-#define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D01000
-#define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D01800
-
-/* Bases of da850/da830 McASP0 register banks */
-#define DAVINCI_DA8XX_MCASP0_REG_BASE 0x01D00000
-
-/* Bases of da830 McASP1 register banks */
-#define DAVINCI_DA830_MCASP1_REG_BASE 0x01D04000
-
-/* Bases of da830 McASP2 register banks */
-#define DAVINCI_DA830_MCASP2_REG_BASE 0x01D08000
-
-/* EDMA channels of dm644x and dm355 */
-#define DAVINCI_DMA_ASP0_TX 2
-#define DAVINCI_DMA_ASP0_RX 3
-#define DAVINCI_DMA_ASP1_TX 8
-#define DAVINCI_DMA_ASP1_RX 9
-
-/* EDMA channels of dm646x */
-#define DAVINCI_DM646X_DMA_MCASP0_AXEVT0 6
-#define DAVINCI_DM646X_DMA_MCASP0_AREVT0 9
-#define DAVINCI_DM646X_DMA_MCASP1_AXEVT1 12
-
-/* EDMA channels of da850/da830 McASP0 */
-#define DAVINCI_DA8XX_DMA_MCASP0_AREVT 0
-#define DAVINCI_DA8XX_DMA_MCASP0_AXEVT 1
-
-/* EDMA channels of da830 McASP1 */
-#define DAVINCI_DA830_DMA_MCASP1_AREVT 2
-#define DAVINCI_DA830_DMA_MCASP1_AXEVT 3
-
-/* EDMA channels of da830 McASP2 */
-#define DAVINCI_DA830_DMA_MCASP2_AREVT 4
-#define DAVINCI_DA830_DMA_MCASP2_AXEVT 5
-
-/* Interrupts */
-#define DAVINCI_ASP0_RX_INT DAVINCI_INTC_IRQ(IRQ_MBRINT)
-#define DAVINCI_ASP0_TX_INT DAVINCI_INTC_IRQ(IRQ_MBXINT)
-#define DAVINCI_ASP1_RX_INT DAVINCI_INTC_IRQ(IRQ_MBRINT)
-#define DAVINCI_ASP1_TX_INT DAVINCI_INTC_IRQ(IRQ_MBXINT)
-
-#endif /* __ASM_ARCH_DAVINCI_ASP_H */
diff --git a/arch/arm/mach-davinci/common.h b/arch/arm/mach-davinci/common.h
index 772b51e0ac5e..b4fd0e9acf6c 100644
--- a/arch/arm/mach-davinci/common.h
+++ b/arch/arm/mach-davinci/common.h
@@ -17,8 +17,8 @@
#include <asm/irq.h>
-#define DAVINCI_INTC_START NR_IRQS
-#define DAVINCI_INTC_IRQ(_irqnum) (DAVINCI_INTC_START + (_irqnum))
+#define DAVINCI_INTC_START NR_IRQS
+#define DAVINCI_INTC_IRQ(_irqnum) (DAVINCI_INTC_START + (_irqnum))
struct davinci_gpio_controller;
@@ -45,9 +45,6 @@ struct davinci_soc_info {
unsigned gpio_num;
unsigned gpio_irq;
unsigned gpio_unbanked;
- struct davinci_gpio_controller *gpio_ctlrs;
- int gpio_ctlrs_num;
- struct emac_platform_data *emac_pdata;
dma_addr_t sram_dma;
unsigned sram_len;
};
diff --git a/arch/arm/mach-davinci/cputype.h b/arch/arm/mach-davinci/cputype.h
index 87ee56068a16..148a738391dc 100644
--- a/arch/arm/mach-davinci/cputype.h
+++ b/arch/arm/mach-davinci/cputype.h
@@ -28,25 +28,4 @@ struct davinci_id {
#define DAVINCI_CPU_ID_DA830 0x08300000
#define DAVINCI_CPU_ID_DA850 0x08500000
-#define IS_DAVINCI_CPU(type, id) \
-static inline int is_davinci_ ##type(void) \
-{ \
- return (davinci_soc_info.cpu_id == (id)); \
-}
-
-IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830)
-IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850)
-
-#ifdef CONFIG_ARCH_DAVINCI_DA830
-#define cpu_is_davinci_da830() is_davinci_da830()
-#else
-#define cpu_is_davinci_da830() 0
-#endif
-
-#ifdef CONFIG_ARCH_DAVINCI_DA850
-#define cpu_is_davinci_da850() is_davinci_da850()
-#else
-#define cpu_is_davinci_da850() 0
-#endif
-
#endif
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index eab5fac18806..2e497745b624 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -12,7 +12,6 @@
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irqchip/irq-davinci-cp-intc.h>
-#include <linux/platform_data/gpio-davinci.h>
#include <clocksource/timer-davinci.h>
@@ -448,181 +447,6 @@ static const struct mux_config da830_pins[] = {
#endif
};
-const short da830_emif25_pins[] __initconst = {
- DA830_EMA_D_0, DA830_EMA_D_1, DA830_EMA_D_2, DA830_EMA_D_3,
- DA830_EMA_D_4, DA830_EMA_D_5, DA830_EMA_D_6, DA830_EMA_D_7,
- DA830_EMA_D_8, DA830_EMA_D_9, DA830_EMA_D_10, DA830_EMA_D_11,
- DA830_EMA_D_12, DA830_EMA_D_13, DA830_EMA_D_14, DA830_EMA_D_15,
- DA830_EMA_A_0, DA830_EMA_A_1, DA830_EMA_A_2, DA830_EMA_A_3,
- DA830_EMA_A_4, DA830_EMA_A_5, DA830_EMA_A_6, DA830_EMA_A_7,
- DA830_EMA_A_8, DA830_EMA_A_9, DA830_EMA_A_10, DA830_EMA_A_11,
- DA830_EMA_A_12, DA830_EMA_BA_0, DA830_EMA_BA_1, DA830_EMA_CLK,
- DA830_EMA_SDCKE, DA830_NEMA_CS_4, DA830_NEMA_CS_5, DA830_NEMA_WE,
- DA830_NEMA_CS_0, DA830_NEMA_CS_2, DA830_NEMA_CS_3, DA830_NEMA_OE,
- DA830_NEMA_WE_DQM_1, DA830_NEMA_WE_DQM_0, DA830_EMA_WAIT_0,
- -1
-};
-
-const short da830_spi0_pins[] __initconst = {
- DA830_SPI0_SOMI_0, DA830_SPI0_SIMO_0, DA830_SPI0_CLK, DA830_NSPI0_ENA,
- DA830_NSPI0_SCS_0,
- -1
-};
-
-const short da830_spi1_pins[] __initconst = {
- DA830_SPI1_SOMI_0, DA830_SPI1_SIMO_0, DA830_SPI1_CLK, DA830_NSPI1_ENA,
- DA830_NSPI1_SCS_0,
- -1
-};
-
-const short da830_mmc_sd_pins[] __initconst = {
- DA830_MMCSD_DAT_0, DA830_MMCSD_DAT_1, DA830_MMCSD_DAT_2,
- DA830_MMCSD_DAT_3, DA830_MMCSD_DAT_4, DA830_MMCSD_DAT_5,
- DA830_MMCSD_DAT_6, DA830_MMCSD_DAT_7, DA830_MMCSD_CLK,
- DA830_MMCSD_CMD,
- -1
-};
-
-const short da830_uart0_pins[] __initconst = {
- DA830_NUART0_CTS, DA830_NUART0_RTS, DA830_UART0_RXD, DA830_UART0_TXD,
- -1
-};
-
-const short da830_uart1_pins[] __initconst = {
- DA830_UART1_RXD, DA830_UART1_TXD,
- -1
-};
-
-const short da830_uart2_pins[] __initconst = {
- DA830_UART2_RXD, DA830_UART2_TXD,
- -1
-};
-
-const short da830_usb20_pins[] __initconst = {
- DA830_USB0_DRVVBUS, DA830_USB_REFCLKIN,
- -1
-};
-
-const short da830_usb11_pins[] __initconst = {
- DA830_USB_REFCLKIN,
- -1
-};
-
-const short da830_uhpi_pins[] __initconst = {
- DA830_UHPI_HD_0, DA830_UHPI_HD_1, DA830_UHPI_HD_2, DA830_UHPI_HD_3,
- DA830_UHPI_HD_4, DA830_UHPI_HD_5, DA830_UHPI_HD_6, DA830_UHPI_HD_7,
- DA830_UHPI_HD_8, DA830_UHPI_HD_9, DA830_UHPI_HD_10, DA830_UHPI_HD_11,
- DA830_UHPI_HD_12, DA830_UHPI_HD_13, DA830_UHPI_HD_14, DA830_UHPI_HD_15,
- DA830_UHPI_HCNTL0, DA830_UHPI_HCNTL1, DA830_UHPI_HHWIL, DA830_UHPI_HRNW,
- DA830_NUHPI_HAS, DA830_NUHPI_HCS, DA830_NUHPI_HDS1, DA830_NUHPI_HDS2,
- DA830_NUHPI_HINT, DA830_NUHPI_HRDY,
- -1
-};
-
-const short da830_cpgmac_pins[] __initconst = {
- DA830_RMII_TXD_0, DA830_RMII_TXD_1, DA830_RMII_TXEN, DA830_RMII_CRS_DV,
- DA830_RMII_RXD_0, DA830_RMII_RXD_1, DA830_RMII_RXER, DA830_MDIO_CLK,
- DA830_MDIO_D,
- -1
-};
-
-const short da830_emif3c_pins[] __initconst = {
- DA830_EMB_SDCKE, DA830_EMB_CLK_GLUE, DA830_EMB_CLK, DA830_NEMB_CS_0,
- DA830_NEMB_CAS, DA830_NEMB_RAS, DA830_NEMB_WE, DA830_EMB_BA_1,
- DA830_EMB_BA_0, DA830_EMB_A_0, DA830_EMB_A_1, DA830_EMB_A_2,
- DA830_EMB_A_3, DA830_EMB_A_4, DA830_EMB_A_5, DA830_EMB_A_6,
- DA830_EMB_A_7, DA830_EMB_A_8, DA830_EMB_A_9, DA830_EMB_A_10,
- DA830_EMB_A_11, DA830_EMB_A_12, DA830_NEMB_WE_DQM_3,
- DA830_NEMB_WE_DQM_2, DA830_EMB_D_0, DA830_EMB_D_1, DA830_EMB_D_2,
- DA830_EMB_D_3, DA830_EMB_D_4, DA830_EMB_D_5, DA830_EMB_D_6,
- DA830_EMB_D_7, DA830_EMB_D_8, DA830_EMB_D_9, DA830_EMB_D_10,
- DA830_EMB_D_11, DA830_EMB_D_12, DA830_EMB_D_13, DA830_EMB_D_14,
- DA830_EMB_D_15, DA830_EMB_D_16, DA830_EMB_D_17, DA830_EMB_D_18,
- DA830_EMB_D_19, DA830_EMB_D_20, DA830_EMB_D_21, DA830_EMB_D_22,
- DA830_EMB_D_23, DA830_EMB_D_24, DA830_EMB_D_25, DA830_EMB_D_26,
- DA830_EMB_D_27, DA830_EMB_D_28, DA830_EMB_D_29, DA830_EMB_D_30,
- DA830_EMB_D_31, DA830_NEMB_WE_DQM_1, DA830_NEMB_WE_DQM_0,
- -1
-};
-
-const short da830_mcasp0_pins[] __initconst = {
- DA830_AHCLKX0, DA830_ACLKX0, DA830_AFSX0,
- DA830_AHCLKR0, DA830_ACLKR0, DA830_AFSR0, DA830_AMUTE0,
- DA830_AXR0_0, DA830_AXR0_1, DA830_AXR0_2, DA830_AXR0_3,
- DA830_AXR0_4, DA830_AXR0_5, DA830_AXR0_6, DA830_AXR0_7,
- DA830_AXR0_8, DA830_AXR0_9, DA830_AXR0_10, DA830_AXR0_11,
- DA830_AXR0_12, DA830_AXR0_13, DA830_AXR0_14, DA830_AXR0_15,
- -1
-};
-
-const short da830_mcasp1_pins[] __initconst = {
- DA830_AHCLKX1, DA830_ACLKX1, DA830_AFSX1,
- DA830_AHCLKR1, DA830_ACLKR1, DA830_AFSR1, DA830_AMUTE1,
- DA830_AXR1_0, DA830_AXR1_1, DA830_AXR1_2, DA830_AXR1_3,
- DA830_AXR1_4, DA830_AXR1_5, DA830_AXR1_6, DA830_AXR1_7,
- DA830_AXR1_8, DA830_AXR1_9, DA830_AXR1_10, DA830_AXR1_11,
- -1
-};
-
-const short da830_mcasp2_pins[] __initconst = {
- DA830_AHCLKX2, DA830_ACLKX2, DA830_AFSX2,
- DA830_AHCLKR2, DA830_ACLKR2, DA830_AFSR2, DA830_AMUTE2,
- DA830_AXR2_0, DA830_AXR2_1, DA830_AXR2_2, DA830_AXR2_3,
- -1
-};
-
-const short da830_i2c0_pins[] __initconst = {
- DA830_I2C0_SDA, DA830_I2C0_SCL,
- -1
-};
-
-const short da830_i2c1_pins[] __initconst = {
- DA830_I2C1_SCL, DA830_I2C1_SDA,
- -1
-};
-
-const short da830_lcdcntl_pins[] __initconst = {
- DA830_LCD_D_0, DA830_LCD_D_1, DA830_LCD_D_2, DA830_LCD_D_3,
- DA830_LCD_D_4, DA830_LCD_D_5, DA830_LCD_D_6, DA830_LCD_D_7,
- DA830_LCD_D_8, DA830_LCD_D_9, DA830_LCD_D_10, DA830_LCD_D_11,
- DA830_LCD_D_12, DA830_LCD_D_13, DA830_LCD_D_14, DA830_LCD_D_15,
- DA830_LCD_PCLK, DA830_LCD_HSYNC, DA830_LCD_VSYNC, DA830_NLCD_AC_ENB_CS,
- DA830_LCD_MCLK,
- -1
-};
-
-const short da830_pwm_pins[] __initconst = {
- DA830_ECAP0_APWM0, DA830_ECAP1_APWM1, DA830_EPWM0B, DA830_EPWM0A,
- DA830_EPWMSYNCI, DA830_EPWMSYNC0, DA830_ECAP2_APWM2, DA830_EHRPWMGLUETZ,
- DA830_EPWM2B, DA830_EPWM2A, DA830_EPWM1B, DA830_EPWM1A,
- -1
-};
-
-const short da830_ecap0_pins[] __initconst = {
- DA830_ECAP0_APWM0,
- -1
-};
-
-const short da830_ecap1_pins[] __initconst = {
- DA830_ECAP1_APWM1,
- -1
-};
-
-const short da830_ecap2_pins[] __initconst = {
- DA830_ECAP2_APWM2,
- -1
-};
-
-const short da830_eqep0_pins[] __initconst = {
- DA830_EQEP0I, DA830_EQEP0S, DA830_EQEP0A, DA830_EQEP0B,
- -1
-};
-
-const short da830_eqep1_pins[] __initconst = {
- DA830_EQEP1I, DA830_EQEP1S, DA830_EQEP1A, DA830_EQEP1B,
- -1
-};
-
static struct map_desc da830_io_desc[] = {
{
.virtual = IO_VIRT,
@@ -663,30 +487,6 @@ static struct davinci_id da830_ids[] = {
},
};
-static struct davinci_gpio_platform_data da830_gpio_platform_data = {
- .no_auto_base = true,
- .base = 0,
- .ngpio = 128,
-};
-
-int __init da830_register_gpio(void)
-{
- return da8xx_register_gpio(&da830_gpio_platform_data);
-}
-
-/*
- * Bottom half of timer0 is used both for clock even and clocksource.
- * Top half is used by DSP.
- */
-static const struct davinci_timer_cfg da830_timer_cfg = {
- .reg = DEFINE_RES_IO(DA8XX_TIMER64P0_BASE, SZ_4K),
- .irq = {
- DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA830_T12CMPINT0_0)),
- DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0)),
- },
- .cmp_off = DA830_CMP12_0,
-};
-
static const struct davinci_soc_info davinci_soc_info_da830 = {
.io_desc = da830_io_desc,
.io_desc_num = ARRAY_SIZE(da830_io_desc),
@@ -696,7 +496,6 @@ static const struct davinci_soc_info davinci_soc_info_da830 = {
.pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
.pinmux_pins = da830_pins,
.pinmux_pins_num = ARRAY_SIZE(da830_pins),
- .emac_pdata = &da8xx_emac_pdata,
};
void __init da830_init(void)
@@ -706,76 +505,3 @@ void __init da830_init(void)
da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module");
}
-
-static const struct davinci_cp_intc_config da830_cp_intc_config = {
- .reg = {
- .start = DA8XX_CP_INTC_BASE,
- .end = DA8XX_CP_INTC_BASE + SZ_8K - 1,
- .flags = IORESOURCE_MEM,
- },
- .num_irqs = DA830_N_CP_INTC_IRQ,
-};
-
-void __init da830_init_irq(void)
-{
- davinci_cp_intc_init(&da830_cp_intc_config);
-}
-
-void __init da830_init_time(void)
-{
- void __iomem *pll;
- struct clk *clk;
- int rv;
-
- clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DA830_REF_FREQ);
-
- pll = ioremap(DA8XX_PLL0_BASE, SZ_4K);
-
- da830_pll_init(NULL, pll, NULL);
-
- clk = clk_get(NULL, "timer0");
- if (WARN_ON(IS_ERR(clk))) {
- pr_err("Unable to get the timer clock\n");
- return;
- }
-
- rv = davinci_timer_register(clk, &da830_timer_cfg);
- WARN(rv, "Unable to register the timer: %d\n", rv);
-}
-
-static struct resource da830_psc0_resources[] = {
- {
- .start = DA8XX_PSC0_BASE,
- .end = DA8XX_PSC0_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device da830_psc0_device = {
- .name = "da830-psc0",
- .id = -1,
- .resource = da830_psc0_resources,
- .num_resources = ARRAY_SIZE(da830_psc0_resources),
-};
-
-static struct resource da830_psc1_resources[] = {
- {
- .start = DA8XX_PSC1_BASE,
- .end = DA8XX_PSC1_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device da830_psc1_device = {
- .name = "da830-psc1",
- .id = -1,
- .resource = da830_psc1_resources,
- .num_resources = ARRAY_SIZE(da830_psc1_resources),
-};
-
-void __init da830_register_clocks(void)
-{
- /* PLL is registered in da830_init_time() */
- platform_device_register(&da830_psc0_device);
- platform_device_register(&da830_psc1_device);
-}
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 635e88daf5dd..287dd987908e 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -10,19 +10,10 @@
* 2009 (c) MontaVista Software, Inc.
*/
-#include <linux/clk-provider.h>
-#include <linux/clk/davinci.h>
-#include <linux/clkdev.h>
-#include <linux/cpufreq.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/io.h>
-#include <linux/irqchip/irq-davinci-cp-intc.h>
#include <linux/mfd/da8xx-cfgchip.h>
-#include <linux/platform_data/clk-da8xx-cfgchip.h>
-#include <linux/platform_data/clk-davinci-pll.h>
-#include <linux/platform_data/davinci-cpufreq.h>
-#include <linux/platform_data/gpio-davinci.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
@@ -33,6 +24,7 @@
#include "common.h"
#include "cputype.h"
#include "da8xx.h"
+#include "hardware.h"
#include "pm.h"
#include "irqs.h"
#include "mux.h"
@@ -258,45 +250,6 @@ static const struct mux_config da850_pins[] = {
#endif
};
-const short da850_i2c0_pins[] __initconst = {
- DA850_I2C0_SDA, DA850_I2C0_SCL,
- -1
-};
-
-const short da850_i2c1_pins[] __initconst = {
- DA850_I2C1_SCL, DA850_I2C1_SDA,
- -1
-};
-
-const short da850_lcdcntl_pins[] __initconst = {
- DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
- DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
- DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11,
- DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15,
- DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS,
- -1
-};
-
-const short da850_vpif_capture_pins[] __initconst = {
- DA850_VPIF_DIN0, DA850_VPIF_DIN1, DA850_VPIF_DIN2, DA850_VPIF_DIN3,
- DA850_VPIF_DIN4, DA850_VPIF_DIN5, DA850_VPIF_DIN6, DA850_VPIF_DIN7,
- DA850_VPIF_DIN8, DA850_VPIF_DIN9, DA850_VPIF_DIN10, DA850_VPIF_DIN11,
- DA850_VPIF_DIN12, DA850_VPIF_DIN13, DA850_VPIF_DIN14, DA850_VPIF_DIN15,
- DA850_VPIF_CLKIN0, DA850_VPIF_CLKIN1, DA850_VPIF_CLKIN2,
- DA850_VPIF_CLKIN3,
- -1
-};
-
-const short da850_vpif_display_pins[] __initconst = {
- DA850_VPIF_DOUT0, DA850_VPIF_DOUT1, DA850_VPIF_DOUT2, DA850_VPIF_DOUT3,
- DA850_VPIF_DOUT4, DA850_VPIF_DOUT5, DA850_VPIF_DOUT6, DA850_VPIF_DOUT7,
- DA850_VPIF_DOUT8, DA850_VPIF_DOUT9, DA850_VPIF_DOUT10,
- DA850_VPIF_DOUT11, DA850_VPIF_DOUT12, DA850_VPIF_DOUT13,
- DA850_VPIF_DOUT14, DA850_VPIF_DOUT15, DA850_VPIF_CLKO2,
- DA850_VPIF_CLKO3,
- -1
-};
-
static struct map_desc da850_io_desc[] = {
{
.virtual = IO_VIRT,
@@ -330,204 +283,9 @@ static struct davinci_id da850_ids[] = {
},
};
-/*
- * Bottom half of timer 0 is used for clock_event, top half for
- * clocksource.
- */
-static const struct davinci_timer_cfg da850_timer_cfg = {
- .reg = DEFINE_RES_IO(DA8XX_TIMER64P0_BASE, SZ_4K),
- .irq = {
- DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0)),
- DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_0)),
- },
-};
-
-#ifdef CONFIG_CPU_FREQ
-/*
- * Notes:
- * According to the TRM, minimum PLLM results in maximum power savings.
- * The OPP definitions below should keep the PLLM as low as possible.
- *
- * The output of the PLLM must be between 300 to 600 MHz.
- */
-struct da850_opp {
- unsigned int freq; /* in KHz */
- unsigned int prediv;
- unsigned int mult;
- unsigned int postdiv;
- unsigned int cvdd_min; /* in uV */
- unsigned int cvdd_max; /* in uV */
-};
-
-static const struct da850_opp da850_opp_456 = {
- .freq = 456000,
- .prediv = 1,
- .mult = 19,
- .postdiv = 1,
- .cvdd_min = 1300000,
- .cvdd_max = 1350000,
-};
-
-static const struct da850_opp da850_opp_408 = {
- .freq = 408000,
- .prediv = 1,
- .mult = 17,
- .postdiv = 1,
- .cvdd_min = 1300000,
- .cvdd_max = 1350000,
-};
-
-static const struct da850_opp da850_opp_372 = {
- .freq = 372000,
- .prediv = 2,
- .mult = 31,
- .postdiv = 1,
- .cvdd_min = 1200000,
- .cvdd_max = 1320000,
-};
-
-static const struct da850_opp da850_opp_300 = {
- .freq = 300000,
- .prediv = 1,
- .mult = 25,
- .postdiv = 2,
- .cvdd_min = 1200000,
- .cvdd_max = 1320000,
-};
-
-static const struct da850_opp da850_opp_200 = {
- .freq = 200000,
- .prediv = 1,
- .mult = 25,
- .postdiv = 3,
- .cvdd_min = 1100000,
- .cvdd_max = 1160000,
-};
-
-static const struct da850_opp da850_opp_96 = {
- .freq = 96000,
- .prediv = 1,
- .mult = 20,
- .postdiv = 5,
- .cvdd_min = 1000000,
- .cvdd_max = 1050000,
-};
-
-#define OPP(freq) \
- { \
- .driver_data = (unsigned int) &da850_opp_##freq, \
- .frequency = freq * 1000, \
- }
-
-static struct cpufreq_frequency_table da850_freq_table[] = {
- OPP(456),
- OPP(408),
- OPP(372),
- OPP(300),
- OPP(200),
- OPP(96),
- {
- .driver_data = 0,
- .frequency = CPUFREQ_TABLE_END,
- },
-};
-
-#ifdef CONFIG_REGULATOR
-static int da850_set_voltage(unsigned int index);
-static int da850_regulator_init(void);
-#endif
-
-static struct davinci_cpufreq_config cpufreq_info = {
- .freq_table = da850_freq_table,
-#ifdef CONFIG_REGULATOR
- .init = da850_regulator_init,
- .set_voltage = da850_set_voltage,
-#endif
-};
-
-#ifdef CONFIG_REGULATOR
-static struct regulator *cvdd;
-
-static int da850_set_voltage(unsigned int index)
-{
- struct da850_opp *opp;
-
- if (!cvdd)
- return -ENODEV;
-
- opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data;
-
- return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max);
-}
-
-static int da850_regulator_init(void)
-{
- cvdd = regulator_get(NULL, "cvdd");
- if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;"
- " voltage scaling unsupported\n")) {
- return PTR_ERR(cvdd);
- }
-
- return 0;
-}
-#endif
-
-static struct platform_device da850_cpufreq_device = {
- .name = "cpufreq-davinci",
- .dev = {
- .platform_data = &cpufreq_info,
- },
- .id = -1,
-};
-
-unsigned int da850_max_speed = 300000;
-
-int da850_register_cpufreq(char *async_clk)
-{
- int i;
-
- /* cpufreq driver can help keep an "async" clock constant */
- if (async_clk)
- clk_add_alias("async", da850_cpufreq_device.name,
- async_clk, NULL);
- for (i = 0; i < ARRAY_SIZE(da850_freq_table); i++) {
- if (da850_freq_table[i].frequency <= da850_max_speed) {
- cpufreq_info.freq_table = &da850_freq_table[i];
- break;
- }
- }
-
- return platform_device_register(&da850_cpufreq_device);
-}
-#else
-int __init da850_register_cpufreq(char *async_clk)
-{
- return 0;
-}
-#endif
-
/* VPIF resource, platform data */
static u64 da850_vpif_dma_mask = DMA_BIT_MASK(32);
-static struct resource da850_vpif_resource[] = {
- {
- .start = DA8XX_VPIF_BASE,
- .end = DA8XX_VPIF_BASE + 0xfff,
- .flags = IORESOURCE_MEM,
- }
-};
-
-static struct platform_device da850_vpif_dev = {
- .name = "vpif",
- .id = -1,
- .dev = {
- .dma_mask = &da850_vpif_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .resource = da850_vpif_resource,
- .num_resources = ARRAY_SIZE(da850_vpif_resource),
-};
-
static struct resource da850_vpif_display_resource[] = {
{
.start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
@@ -571,11 +329,6 @@ static struct platform_device da850_vpif_capture_dev = {
.num_resources = ARRAY_SIZE(da850_vpif_capture_resource),
};
-int __init da850_register_vpif(void)
-{
- return platform_device_register(&da850_vpif_dev);
-}
-
int __init da850_register_vpif_display(struct vpif_display_config
*display_config)
{
@@ -590,17 +343,6 @@ int __init da850_register_vpif_capture(struct vpif_capture_config
return platform_device_register(&da850_vpif_capture_dev);
}
-static struct davinci_gpio_platform_data da850_gpio_platform_data = {
- .no_auto_base = true,
- .base = 0,
- .ngpio = 144,
-};
-
-int __init da850_register_gpio(void)
-{
- return da8xx_register_gpio(&da850_gpio_platform_data);
-}
-
static const struct davinci_soc_info davinci_soc_info_da850 = {
.io_desc = da850_io_desc,
.io_desc_num = ARRAY_SIZE(da850_io_desc),
@@ -610,7 +352,6 @@ static const struct davinci_soc_info davinci_soc_info_da850 = {
.pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
.pinmux_pins = da850_pins,
.pinmux_pins_num = ARRAY_SIZE(da850_pins),
- .emac_pdata = &da8xx_emac_pdata,
.sram_dma = DA8XX_SHARED_RAM_BASE,
.sram_len = SZ_128K,
};
@@ -626,142 +367,3 @@ void __init da850_init(void)
da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K);
WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module");
}
-
-static const struct davinci_cp_intc_config da850_cp_intc_config = {
- .reg = {
- .start = DA8XX_CP_INTC_BASE,
- .end = DA8XX_CP_INTC_BASE + SZ_8K - 1,
- .flags = IORESOURCE_MEM,
- },
- .num_irqs = DA850_N_CP_INTC_IRQ,
-};
-
-void __init da850_init_irq(void)
-{
- davinci_cp_intc_init(&da850_cp_intc_config);
-}
-
-void __init da850_init_time(void)
-{
- void __iomem *pll0;
- struct regmap *cfgchip;
- struct clk *clk;
- int rv;
-
- clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DA850_REF_FREQ);
-
- pll0 = ioremap(DA8XX_PLL0_BASE, SZ_4K);
- cfgchip = da8xx_get_cfgchip();
-
- da850_pll0_init(NULL, pll0, cfgchip);
-
- clk = clk_get(NULL, "timer0");
- if (WARN_ON(IS_ERR(clk))) {
- pr_err("Unable to get the timer clock\n");
- return;
- }
-
- rv = davinci_timer_register(clk, &da850_timer_cfg);
- WARN(rv, "Unable to register the timer: %d\n", rv);
-}
-
-static struct resource da850_pll1_resources[] = {
- {
- .start = DA850_PLL1_BASE,
- .end = DA850_PLL1_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct davinci_pll_platform_data da850_pll1_pdata;
-
-static struct platform_device da850_pll1_device = {
- .name = "da850-pll1",
- .id = -1,
- .resource = da850_pll1_resources,
- .num_resources = ARRAY_SIZE(da850_pll1_resources),
- .dev = {
- .platform_data = &da850_pll1_pdata,
- },
-};
-
-static struct resource da850_psc0_resources[] = {
- {
- .start = DA8XX_PSC0_BASE,
- .end = DA8XX_PSC0_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device da850_psc0_device = {
- .name = "da850-psc0",
- .id = -1,
- .resource = da850_psc0_resources,
- .num_resources = ARRAY_SIZE(da850_psc0_resources),
-};
-
-static struct resource da850_psc1_resources[] = {
- {
- .start = DA8XX_PSC1_BASE,
- .end = DA8XX_PSC1_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device da850_psc1_device = {
- .name = "da850-psc1",
- .id = -1,
- .resource = da850_psc1_resources,
- .num_resources = ARRAY_SIZE(da850_psc1_resources),
-};
-
-static struct da8xx_cfgchip_clk_platform_data da850_async1_pdata;
-
-static struct platform_device da850_async1_clksrc_device = {
- .name = "da850-async1-clksrc",
- .id = -1,
- .dev = {
- .platform_data = &da850_async1_pdata,
- },
-};
-
-static struct da8xx_cfgchip_clk_platform_data da850_async3_pdata;
-
-static struct platform_device da850_async3_clksrc_device = {
- .name = "da850-async3-clksrc",
- .id = -1,
- .dev = {
- .platform_data = &da850_async3_pdata,
- },
-};
-
-static struct da8xx_cfgchip_clk_platform_data da850_tbclksync_pdata;
-
-static struct platform_device da850_tbclksync_device = {
- .name = "da830-tbclksync",
- .id = -1,
- .dev = {
- .platform_data = &da850_tbclksync_pdata,
- },
-};
-
-void __init da850_register_clocks(void)
-{
- /* PLL0 is registered in da850_init_time() */
-
- da850_pll1_pdata.cfgchip = da8xx_get_cfgchip();
- platform_device_register(&da850_pll1_device);
-
- da850_async1_pdata.cfgchip = da8xx_get_cfgchip();
- platform_device_register(&da850_async1_clksrc_device);
-
- da850_async3_pdata.cfgchip = da8xx_get_cfgchip();
- platform_device_register(&da850_async3_clksrc_device);
-
- platform_device_register(&da850_psc0_device);
-
- platform_device_register(&da850_psc1_device);
-
- da850_tbclksync_pdata.cfgchip = da8xx_get_cfgchip();
- platform_device_register(&da850_tbclksync_device);
-}
diff --git a/arch/arm/mach-davinci/da8xx.h b/arch/arm/mach-davinci/da8xx.h
index 382811dbbc3b..54a255b8d8d8 100644
--- a/arch/arm/mach-davinci/da8xx.h
+++ b/arch/arm/mach-davinci/da8xx.h
@@ -9,38 +9,20 @@
#ifndef __ASM_ARCH_DAVINCI_DA8XX_H
#define __ASM_ARCH_DAVINCI_DA8XX_H
-#include <video/da8xx-fb.h>
-
+#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
-#include <linux/davinci_emac.h>
-#include <linux/spi/spi.h>
-#include <linux/platform_data/davinci_asp.h>
+#include <linux/videodev2.h>
#include <linux/reboot.h>
#include <linux/regmap.h>
-#include <linux/videodev2.h>
-#include "serial.h"
+#include "hardware.h"
#include "pm.h"
-#include <linux/platform_data/edma.h>
-#include <linux/platform_data/i2c-davinci.h>
-#include <linux/platform_data/mmc-davinci.h>
-#include <linux/platform_data/usb-davinci.h>
-#include <linux/platform_data/spi-davinci.h>
-#include <linux/platform_data/uio_pruss.h>
-
#include <media/davinci/vpif_types.h>
extern void __iomem *da8xx_syscfg0_base;
extern void __iomem *da8xx_syscfg1_base;
-/*
- * If the DA850/OMAP-L138/AM18x SoC on board is of a higher speed grade
- * (than the regular 300MHz variant), the board code should set this up
- * with the supported speed before calling da850_register_cpufreq().
- */
-extern unsigned int da850_max_speed;
-
/*
* The cp_intc interrupt controller for the da8xx isn't in the same
* chunk of physical memory space as the other registers (like it is
@@ -87,83 +69,14 @@ extern unsigned int da850_max_speed;
#define DA8XX_ARM_RAM_BASE 0xffff0000
void da830_init(void);
-void da830_init_irq(void);
-void da830_init_time(void);
-void da830_register_clocks(void);
void da850_init(void);
-void da850_init_irq(void);
-void da850_init_time(void);
-void da850_register_clocks(void);
-int da830_register_edma(struct edma_rsv_info *rsv);
-int da850_register_edma(struct edma_rsv_info *rsv[2]);
-int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata);
-int da8xx_register_spi_bus(int instance, unsigned num_chipselect);
-int da8xx_register_watchdog(void);
-int da8xx_register_usb_phy(void);
-int da8xx_register_usb20(unsigned mA, unsigned potpgt);
-int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata);
-int da8xx_register_usb_phy_clocks(void);
-int da850_register_sata_refclk(int rate);
-int da8xx_register_emac(void);
-int da8xx_register_uio_pruss(void);
-int da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata);
-int da8xx_register_mmcsd0(struct davinci_mmc_config *config);
-int da850_register_mmcsd1(struct davinci_mmc_config *config);
-void da8xx_register_mcasp(int id, struct snd_platform_data *pdata);
-int da8xx_register_rtc(void);
-int da8xx_register_gpio(void *pdata);
-int da850_register_cpufreq(char *async_clk);
-int da8xx_register_cpuidle(void);
-void __iomem *da8xx_get_mem_ctlr(void);
-int da850_register_sata(unsigned long refclkpn);
-int da850_register_vpif(void);
int da850_register_vpif_display
(struct vpif_display_config *display_config);
int da850_register_vpif_capture
(struct vpif_capture_config *capture_config);
-void da8xx_rproc_reserve_cma(void);
-int da8xx_register_rproc(void);
-int da850_register_gpio(void);
-int da830_register_gpio(void);
struct regmap *da8xx_get_cfgchip(void);
-
-extern struct platform_device da8xx_serial_device[];
-extern struct emac_platform_data da8xx_emac_pdata;
-extern struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata;
-extern struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata;
-
-
-extern const short da830_emif25_pins[];
-extern const short da830_spi0_pins[];
-extern const short da830_spi1_pins[];
-extern const short da830_mmc_sd_pins[];
-extern const short da830_uart0_pins[];
-extern const short da830_uart1_pins[];
-extern const short da830_uart2_pins[];
-extern const short da830_usb20_pins[];
-extern const short da830_usb11_pins[];
-extern const short da830_uhpi_pins[];
-extern const short da830_cpgmac_pins[];
-extern const short da830_emif3c_pins[];
-extern const short da830_mcasp0_pins[];
-extern const short da830_mcasp1_pins[];
-extern const short da830_mcasp2_pins[];
-extern const short da830_i2c0_pins[];
-extern const short da830_i2c1_pins[];
-extern const short da830_lcdcntl_pins[];
-extern const short da830_pwm_pins[];
-extern const short da830_ecap0_pins[];
-extern const short da830_ecap1_pins[];
-extern const short da830_ecap2_pins[];
-extern const short da830_eqep0_pins[];
-extern const short da830_eqep1_pins[];
-extern const short da850_vpif_capture_pins[];
-extern const short da850_vpif_display_pins[];
-
-extern const short da850_i2c0_pins[];
-extern const short da850_i2c1_pins[];
-extern const short da850_lcdcntl_pins[];
+void __iomem *da8xx_get_mem_ctlr(void);
#endif /* __ASM_ARCH_DAVINCI_DA8XX_H */
diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h
deleted file mode 100644
index b7172797692b..000000000000
--- a/arch/arm/mach-davinci/davinci.h
+++ /dev/null
@@ -1,136 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * This file contains the processor specific definitions
- * of the TI DM644x, DM355, DM365, and DM646x.
- *
- * Copyright (C) 2011 Texas Instruments Incorporated
- * Copyright (c) 2007 Deep Root Systems, LLC
- */
-#ifndef __DAVINCI_H
-#define __DAVINCI_H
-
-#include <linux/clk.h>
-#include <linux/videodev2.h>
-#include <linux/davinci_emac.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/platform_data/davinci_asp.h>
-#include <linux/platform_data/edma.h>
-#include <linux/platform_data/keyscan-davinci.h>
-
-#include "hardware.h"
-
-#include <media/davinci/vpfe_capture.h>
-#include <media/davinci/vpif_types.h>
-#include <media/davinci/vpss.h>
-#include <media/davinci/vpbe_types.h>
-#include <media/davinci/vpbe_venc.h>
-#include <media/davinci/vpbe.h>
-#include <media/davinci/vpbe_osd.h>
-
-#define DAVINCI_PLL1_BASE 0x01c40800
-#define DAVINCI_PLL2_BASE 0x01c40c00
-#define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01c41000
-
-#define DAVINCI_SYSTEM_MODULE_BASE 0x01c40000
-#define SYSMOD_VDAC_CONFIG 0x2c
-#define SYSMOD_VIDCLKCTL 0x38
-#define SYSMOD_VPSS_CLKCTL 0x44
-#define SYSMOD_VDD3P3VPWDN 0x48
-#define SYSMOD_VSCLKDIS 0x6c
-#define SYSMOD_PUPDCTL1 0x7c
-
-/* VPSS CLKCTL bit definitions */
-#define VPSS_MUXSEL_EXTCLK_ENABLE BIT(1)
-#define VPSS_VENCCLKEN_ENABLE BIT(3)
-#define VPSS_DACCLKEN_ENABLE BIT(4)
-#define VPSS_PLLC2SYSCLK5_ENABLE BIT(5)
-
-extern void __iomem *davinci_sysmod_base;
-#define DAVINCI_SYSMOD_VIRT(x) (davinci_sysmod_base + (x))
-void davinci_map_sysmod(void);
-
-#define DAVINCI_GPIO_BASE 0x01C67000
-int davinci_gpio_register(struct resource *res, int size, void *pdata);
-
-#define DAVINCI_TIMER0_BASE (IO_PHYS + 0x21400)
-#define DAVINCI_WDOG_BASE (IO_PHYS + 0x21C00)
-
-/* DM355 base addresses */
-#define DM355_ASYNC_EMIF_CONTROL_BASE 0x01e10000
-#define DM355_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
-
-#define ASP1_TX_EVT_EN 1
-#define ASP1_RX_EVT_EN 2
-
-/* DM365 base addresses */
-#define DM365_ASYNC_EMIF_CONTROL_BASE 0x01d10000
-#define DM365_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
-#define DM365_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
-
-/* DM644x base addresses */
-#define DM644X_ASYNC_EMIF_CONTROL_BASE 0x01e00000
-#define DM644X_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
-#define DM644X_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
-#define DM644X_ASYNC_EMIF_DATA_CE2_BASE 0x06000000
-#define DM644X_ASYNC_EMIF_DATA_CE3_BASE 0x08000000
-
-/* DM646x base addresses */
-#define DM646X_ASYNC_EMIF_CONTROL_BASE 0x20008000
-#define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000
-
-int davinci_init_wdt(void);
-
-/* DM355 function declarations */
-void dm355_init(void);
-void dm355_init_time(void);
-void dm355_init_irq(void);
-void dm355_register_clocks(void);
-void dm355_init_spi0(unsigned chipselect_mask,
- const struct spi_board_info *info, unsigned len);
-void dm355_init_asp1(u32 evt_enable);
-int dm355_init_video(struct vpfe_config *, struct vpbe_config *);
-int dm355_gpio_register(void);
-
-/* DM365 function declarations */
-void dm365_init(void);
-void dm365_init_irq(void);
-void dm365_init_time(void);
-void dm365_register_clocks(void);
-void dm365_init_asp(void);
-void dm365_init_vc(void);
-void dm365_init_ks(struct davinci_ks_platform_data *pdata);
-void dm365_init_rtc(void);
-void dm365_init_spi0(unsigned chipselect_mask,
- const struct spi_board_info *info, unsigned len);
-int dm365_init_video(struct vpfe_config *, struct vpbe_config *);
-int dm365_gpio_register(void);
-
-/* DM644x function declarations */
-void dm644x_init(void);
-void dm644x_init_irq(void);
-void dm644x_init_devices(void);
-void dm644x_init_time(void);
-void dm644x_register_clocks(void);
-void dm644x_init_asp(void);
-int dm644x_init_video(struct vpfe_config *, struct vpbe_config *);
-int dm644x_gpio_register(void);
-
-/* DM646x function declarations */
-void dm646x_init(void);
-void dm646x_init_irq(void);
-void dm646x_init_time(unsigned long ref_clk_rate, unsigned long aux_clkin_rate);
-void dm646x_register_clocks(void);
-void dm646x_init_mcasp0(struct snd_platform_data *pdata);
-void dm646x_init_mcasp1(struct snd_platform_data *pdata);
-int dm646x_init_edma(struct edma_rsv_info *rsv);
-void dm646x_video_init(void);
-void dm646x_setup_vpif(struct vpif_display_config *,
- struct vpif_capture_config *);
-int dm646x_gpio_register(void);
-
-extern struct platform_device dm365_serial_device[];
-extern struct platform_device dm355_serial_device[];
-extern struct platform_device dm644x_serial_device[];
-extern struct platform_device dm646x_serial_device[];
-#endif /*__DAVINCI_H */
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index ef9593558e5f..6939166c33c2 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -21,7 +21,6 @@
#include "common.h"
#include "cputype.h"
#include "da8xx.h"
-#include "asp.h"
#include "cpuidle.h"
#include "irqs.h"
#include "sram.h"
@@ -57,911 +56,6 @@
void __iomem *da8xx_syscfg0_base;
void __iomem *da8xx_syscfg1_base;
-static struct plat_serial8250_port da8xx_serial0_pdata[] = {
- {
- .mapbase = DA8XX_UART0_BASE,
- .irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT0),
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
- UPF_IOREMAP,
- .iotype = UPIO_MEM,
- .regshift = 2,
- },
- {
- .flags = 0,
- }
-};
-static struct plat_serial8250_port da8xx_serial1_pdata[] = {
- {
- .mapbase = DA8XX_UART1_BASE,
- .irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT1),
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
- UPF_IOREMAP,
- .iotype = UPIO_MEM,
- .regshift = 2,
- },
- {
- .flags = 0,
- }
-};
-static struct plat_serial8250_port da8xx_serial2_pdata[] = {
- {
- .mapbase = DA8XX_UART2_BASE,
- .irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT2),
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
- UPF_IOREMAP,
- .iotype = UPIO_MEM,
- .regshift = 2,
- },
- {
- .flags = 0,
- }
-};
-
-struct platform_device da8xx_serial_device[] = {
- {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM,
- .dev = {
- .platform_data = da8xx_serial0_pdata,
- }
- },
- {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM1,
- .dev = {
- .platform_data = da8xx_serial1_pdata,
- }
- },
- {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM2,
- .dev = {
- .platform_data = da8xx_serial2_pdata,
- }
- },
- {
- }
-};
-
-static s8 da8xx_queue_priority_mapping[][2] = {
- /* {event queue no, Priority} */
- {0, 3},
- {1, 7},
- {-1, -1}
-};
-
-static s8 da850_queue_priority_mapping[][2] = {
- /* {event queue no, Priority} */
- {0, 3},
- {-1, -1}
-};
-
-static struct edma_soc_info da8xx_edma0_pdata = {
- .queue_priority_mapping = da8xx_queue_priority_mapping,
- .default_queue = EVENTQ_1,
-};
-
-static struct edma_soc_info da850_edma1_pdata = {
- .queue_priority_mapping = da850_queue_priority_mapping,
- .default_queue = EVENTQ_0,
-};
-
-static struct resource da8xx_edma0_resources[] = {
- {
- .name = "edma3_cc",
- .start = DA8XX_TPCC_BASE,
- .end = DA8XX_TPCC_BASE + SZ_32K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "edma3_tc0",
- .start = DA8XX_TPTC0_BASE,
- .end = DA8XX_TPTC0_BASE + SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "edma3_tc1",
- .start = DA8XX_TPTC1_BASE,
- .end = DA8XX_TPTC1_BASE + SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "edma3_ccint",
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_CCINT0),
- .flags = IORESOURCE_IRQ,
- },
- {
- .name = "edma3_ccerrint",
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_CCERRINT),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct resource da850_edma1_resources[] = {
- {
- .name = "edma3_cc",
- .start = DA850_TPCC1_BASE,
- .end = DA850_TPCC1_BASE + SZ_32K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "edma3_tc0",
- .start = DA850_TPTC2_BASE,
- .end = DA850_TPTC2_BASE + SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "edma3_ccint",
- .start = DAVINCI_INTC_IRQ(IRQ_DA850_CCINT1),
- .flags = IORESOURCE_IRQ,
- },
- {
- .name = "edma3_ccerrint",
- .start = DAVINCI_INTC_IRQ(IRQ_DA850_CCERRINT1),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static const struct platform_device_info da8xx_edma0_device __initconst = {
- .name = "edma",
- .id = 0,
- .dma_mask = DMA_BIT_MASK(32),
- .res = da8xx_edma0_resources,
- .num_res = ARRAY_SIZE(da8xx_edma0_resources),
- .data = &da8xx_edma0_pdata,
- .size_data = sizeof(da8xx_edma0_pdata),
-};
-
-static const struct platform_device_info da850_edma1_device __initconst = {
- .name = "edma",
- .id = 1,
- .dma_mask = DMA_BIT_MASK(32),
- .res = da850_edma1_resources,
- .num_res = ARRAY_SIZE(da850_edma1_resources),
- .data = &da850_edma1_pdata,
- .size_data = sizeof(da850_edma1_pdata),
-};
-
-static const struct dma_slave_map da830_edma_map[] = {
- { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
- { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
- { "davinci-mcasp.1", "rx", EDMA_FILTER_PARAM(0, 2) },
- { "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 3) },
- { "davinci-mcasp.2", "rx", EDMA_FILTER_PARAM(0, 4) },
- { "davinci-mcasp.2", "tx", EDMA_FILTER_PARAM(0, 5) },
- { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
- { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
- { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
- { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
- { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
- { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
-};
-
-int __init da830_register_edma(struct edma_rsv_info *rsv)
-{
- struct platform_device *edma_pdev;
-
- da8xx_edma0_pdata.rsv = rsv;
-
- da8xx_edma0_pdata.slave_map = da830_edma_map;
- da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da830_edma_map);
-
- edma_pdev = platform_device_register_full(&da8xx_edma0_device);
- return PTR_ERR_OR_ZERO(edma_pdev);
-}
-
-static const struct dma_slave_map da850_edma0_map[] = {
- { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
- { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
- { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 2) },
- { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 3) },
- { "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 4) },
- { "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 5) },
- { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
- { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
- { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
- { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
- { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
- { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
-};
-
-static const struct dma_slave_map da850_edma1_map[] = {
- { "da830-mmc.1", "rx", EDMA_FILTER_PARAM(1, 28) },
- { "da830-mmc.1", "tx", EDMA_FILTER_PARAM(1, 29) },
-};
-
-int __init da850_register_edma(struct edma_rsv_info *rsv[2])
-{
- struct platform_device *edma_pdev;
-
- if (rsv) {
- da8xx_edma0_pdata.rsv = rsv[0];
- da850_edma1_pdata.rsv = rsv[1];
- }
-
- da8xx_edma0_pdata.slave_map = da850_edma0_map;
- da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da850_edma0_map);
-
- edma_pdev = platform_device_register_full(&da8xx_edma0_device);
- if (IS_ERR(edma_pdev)) {
- pr_warn("%s: Failed to register eDMA0\n", __func__);
- return PTR_ERR(edma_pdev);
- }
-
- da850_edma1_pdata.slave_map = da850_edma1_map;
- da850_edma1_pdata.slavecnt = ARRAY_SIZE(da850_edma1_map);
-
- edma_pdev = platform_device_register_full(&da850_edma1_device);
- return PTR_ERR_OR_ZERO(edma_pdev);
-}
-
-static struct resource da8xx_i2c_resources0[] = {
- {
- .start = DA8XX_I2C0_BASE,
- .end = DA8XX_I2C0_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT0),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT0),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device da8xx_i2c_device0 = {
- .name = "i2c_davinci",
- .id = 1,
- .num_resources = ARRAY_SIZE(da8xx_i2c_resources0),
- .resource = da8xx_i2c_resources0,
-};
-
-static struct resource da8xx_i2c_resources1[] = {
- {
- .start = DA8XX_I2C1_BASE,
- .end = DA8XX_I2C1_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT1),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT1),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device da8xx_i2c_device1 = {
- .name = "i2c_davinci",
- .id = 2,
- .num_resources = ARRAY_SIZE(da8xx_i2c_resources1),
- .resource = da8xx_i2c_resources1,
-};
-
-int __init da8xx_register_i2c(int instance,
- struct davinci_i2c_platform_data *pdata)
-{
- struct platform_device *pdev;
-
- if (instance == 0)
- pdev = &da8xx_i2c_device0;
- else if (instance == 1)
- pdev = &da8xx_i2c_device1;
- else
- return -EINVAL;
-
- pdev->dev.platform_data = pdata;
- return platform_device_register(pdev);
-}
-
-static struct resource da8xx_watchdog_resources[] = {
- {
- .start = DA8XX_WDOG_BASE,
- .end = DA8XX_WDOG_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device da8xx_wdt_device = {
- .name = "davinci-wdt",
- .id = -1,
- .num_resources = ARRAY_SIZE(da8xx_watchdog_resources),
- .resource = da8xx_watchdog_resources,
-};
-
-int __init da8xx_register_watchdog(void)
-{
- return platform_device_register(&da8xx_wdt_device);
-}
-
-static struct resource da8xx_emac_resources[] = {
- {
- .start = DA8XX_EMAC_CPPI_PORT_BASE,
- .end = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_THRESH_PULSE),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_THRESH_PULSE),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_PULSE),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_PULSE),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_TX_PULSE),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_TX_PULSE),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_MISC_PULSE),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_MISC_PULSE),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct emac_platform_data da8xx_emac_pdata = {
- .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET,
- .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET,
- .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET,
- .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE,
- .version = EMAC_VERSION_2,
-};
-
-static struct platform_device da8xx_emac_device = {
- .name = "davinci_emac",
- .id = 1,
- .dev = {
- .platform_data = &da8xx_emac_pdata,
- },
- .num_resources = ARRAY_SIZE(da8xx_emac_resources),
- .resource = da8xx_emac_resources,
-};
-
-static struct resource da8xx_mdio_resources[] = {
- {
- .start = DA8XX_EMAC_MDIO_BASE,
- .end = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device da8xx_mdio_device = {
- .name = "davinci_mdio",
- .id = 0,
- .num_resources = ARRAY_SIZE(da8xx_mdio_resources),
- .resource = da8xx_mdio_resources,
-};
-
-int __init da8xx_register_emac(void)
-{
- int ret;
-
- ret = platform_device_register(&da8xx_mdio_device);
- if (ret < 0)
- return ret;
-
- return platform_device_register(&da8xx_emac_device);
-}
-
-static struct resource da830_mcasp1_resources[] = {
- {
- .name = "mpu",
- .start = DAVINCI_DA830_MCASP1_REG_BASE,
- .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
- .flags = IORESOURCE_MEM,
- },
- /* TX event */
- {
- .name = "tx",
- .start = DAVINCI_DA830_DMA_MCASP1_AXEVT,
- .end = DAVINCI_DA830_DMA_MCASP1_AXEVT,
- .flags = IORESOURCE_DMA,
- },
- /* RX event */
- {
- .name = "rx",
- .start = DAVINCI_DA830_DMA_MCASP1_AREVT,
- .end = DAVINCI_DA830_DMA_MCASP1_AREVT,
- .flags = IORESOURCE_DMA,
- },
- {
- .name = "common",
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device da830_mcasp1_device = {
- .name = "davinci-mcasp",
- .id = 1,
- .num_resources = ARRAY_SIZE(da830_mcasp1_resources),
- .resource = da830_mcasp1_resources,
-};
-
-static struct resource da830_mcasp2_resources[] = {
- {
- .name = "mpu",
- .start = DAVINCI_DA830_MCASP2_REG_BASE,
- .end = DAVINCI_DA830_MCASP2_REG_BASE + (SZ_1K * 12) - 1,
- .flags = IORESOURCE_MEM,
- },
- /* TX event */
- {
- .name = "tx",
- .start = DAVINCI_DA830_DMA_MCASP2_AXEVT,
- .end = DAVINCI_DA830_DMA_MCASP2_AXEVT,
- .flags = IORESOURCE_DMA,
- },
- /* RX event */
- {
- .name = "rx",
- .start = DAVINCI_DA830_DMA_MCASP2_AREVT,
- .end = DAVINCI_DA830_DMA_MCASP2_AREVT,
- .flags = IORESOURCE_DMA,
- },
- {
- .name = "common",
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device da830_mcasp2_device = {
- .name = "davinci-mcasp",
- .id = 2,
- .num_resources = ARRAY_SIZE(da830_mcasp2_resources),
- .resource = da830_mcasp2_resources,
-};
-
-static struct resource da850_mcasp_resources[] = {
- {
- .name = "mpu",
- .start = DAVINCI_DA8XX_MCASP0_REG_BASE,
- .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
- .flags = IORESOURCE_MEM,
- },
- /* TX event */
- {
- .name = "tx",
- .start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
- .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
- .flags = IORESOURCE_DMA,
- },
- /* RX event */
- {
- .name = "rx",
- .start = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
- .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
- .flags = IORESOURCE_DMA,
- },
- {
- .name = "common",
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device da850_mcasp_device = {
- .name = "davinci-mcasp",
- .id = 0,
- .num_resources = ARRAY_SIZE(da850_mcasp_resources),
- .resource = da850_mcasp_resources,
-};
-
-void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
-{
- struct platform_device *pdev;
-
- switch (id) {
- case 0:
- /* Valid for DA830/OMAP-L137 or DA850/OMAP-L138 */
- pdev = &da850_mcasp_device;
- break;
- case 1:
- /* Valid for DA830/OMAP-L137 only */
- if (!cpu_is_davinci_da830())
- return;
- pdev = &da830_mcasp1_device;
- break;
- case 2:
- /* Valid for DA830/OMAP-L137 only */
- if (!cpu_is_davinci_da830())
- return;
- pdev = &da830_mcasp2_device;
- break;
- default:
- return;
- }
-
- pdev->dev.platform_data = pdata;
- platform_device_register(pdev);
-}
-
-static struct resource da8xx_pruss_resources[] = {
- {
- .start = DA8XX_PRUSS_MEM_BASE,
- .end = DA8XX_PRUSS_MEM_BASE + 0xFFFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT0),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT0),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT1),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT1),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT2),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT2),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT3),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT3),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT4),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT4),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT5),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT5),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT6),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT6),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT7),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT7),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct uio_pruss_pdata da8xx_uio_pruss_pdata = {
- .pintc_base = 0x4000,
-};
-
-static struct platform_device da8xx_uio_pruss_dev = {
- .name = "pruss_uio",
- .id = -1,
- .num_resources = ARRAY_SIZE(da8xx_pruss_resources),
- .resource = da8xx_pruss_resources,
- .dev = {
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &da8xx_uio_pruss_pdata,
- }
-};
-
-int __init da8xx_register_uio_pruss(void)
-{
- da8xx_uio_pruss_pdata.sram_pool = sram_get_gen_pool();
- return platform_device_register(&da8xx_uio_pruss_dev);
-}
-
-static struct lcd_ctrl_config lcd_cfg = {
- .panel_shade = COLOR_ACTIVE,
- .bpp = 16,
-};
-
-struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
- .manu_name = "sharp",
- .controller_data = &lcd_cfg,
- .type = "Sharp_LCD035Q3DG01",
-};
-
-struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = {
- .manu_name = "sharp",
- .controller_data = &lcd_cfg,
- .type = "Sharp_LK043T1DG01",
-};
-
-static struct resource da8xx_lcdc_resources[] = {
- [0] = { /* registers */
- .start = DA8XX_LCD_CNTRL_BASE,
- .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* interrupt */
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_LCDINT),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_LCDINT),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device da8xx_lcdc_device = {
- .name = "da8xx_lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(da8xx_lcdc_resources),
- .resource = da8xx_lcdc_resources,
- .dev = {
- .coherent_dma_mask = DMA_BIT_MASK(32),
- }
-};
-
-int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
-{
- da8xx_lcdc_device.dev.platform_data = pdata;
- return platform_device_register(&da8xx_lcdc_device);
-}
-
-static struct resource da8xx_gpio_resources[] = {
- { /* registers */
- .start = DA8XX_GPIO_BASE,
- .end = DA8XX_GPIO_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
- { /* interrupt */
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO0),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO0),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO1),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO1),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO2),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO2),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO3),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO3),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO4),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO4),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO5),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO5),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO6),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO6),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO7),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO7),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO8),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO8),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device da8xx_gpio_device = {
- .name = "davinci_gpio",
- .id = -1,
- .num_resources = ARRAY_SIZE(da8xx_gpio_resources),
- .resource = da8xx_gpio_resources,
-};
-
-int __init da8xx_register_gpio(void *pdata)
-{
- da8xx_gpio_device.dev.platform_data = pdata;
- return platform_device_register(&da8xx_gpio_device);
-}
-
-static struct resource da8xx_mmcsd0_resources[] = {
- { /* registers */
- .start = DA8XX_MMCSD0_BASE,
- .end = DA8XX_MMCSD0_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
- { /* interrupt */
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MMCSDINT0),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_MMCSDINT0),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device da8xx_mmcsd0_device = {
- .name = "da830-mmc",
- .id = 0,
- .num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources),
- .resource = da8xx_mmcsd0_resources,
-};
-
-int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
-{
- da8xx_mmcsd0_device.dev.platform_data = config;
- return platform_device_register(&da8xx_mmcsd0_device);
-}
-
-#ifdef CONFIG_ARCH_DAVINCI_DA850
-static struct resource da850_mmcsd1_resources[] = {
- { /* registers */
- .start = DA850_MMCSD1_BASE,
- .end = DA850_MMCSD1_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
- { /* interrupt */
- .start = DAVINCI_INTC_IRQ(IRQ_DA850_MMCSDINT0_1),
- .end = DAVINCI_INTC_IRQ(IRQ_DA850_MMCSDINT0_1),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device da850_mmcsd1_device = {
- .name = "da830-mmc",
- .id = 1,
- .num_resources = ARRAY_SIZE(da850_mmcsd1_resources),
- .resource = da850_mmcsd1_resources,
-};
-
-int __init da850_register_mmcsd1(struct davinci_mmc_config *config)
-{
- da850_mmcsd1_device.dev.platform_data = config;
- return platform_device_register(&da850_mmcsd1_device);
-}
-#endif
-
-static struct resource da8xx_rproc_resources[] = {
- { /* DSP boot address */
- .name = "host1cfg",
- .start = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG,
- .end = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG + 3,
- .flags = IORESOURCE_MEM,
- },
- { /* DSP interrupt registers */
- .name = "chipsig",
- .start = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG,
- .end = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7,
- .flags = IORESOURCE_MEM,
- },
- { /* DSP L2 RAM */
- .name = "l2sram",
- .start = DA8XX_DSP_L2_RAM_BASE,
- .end = DA8XX_DSP_L2_RAM_BASE + SZ_256K - 1,
- .flags = IORESOURCE_MEM,
- },
- { /* DSP L1P RAM */
- .name = "l1pram",
- .start = DA8XX_DSP_L1P_RAM_BASE,
- .end = DA8XX_DSP_L1P_RAM_BASE + SZ_32K - 1,
- .flags = IORESOURCE_MEM,
- },
- { /* DSP L1D RAM */
- .name = "l1dram",
- .start = DA8XX_DSP_L1D_RAM_BASE,
- .end = DA8XX_DSP_L1D_RAM_BASE + SZ_32K - 1,
- .flags = IORESOURCE_MEM,
- },
- { /* dsp irq */
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_CHIPINT0),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_CHIPINT0),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device da8xx_dsp = {
- .name = "davinci-rproc",
- .dev = {
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .num_resources = ARRAY_SIZE(da8xx_rproc_resources),
- .resource = da8xx_rproc_resources,
-};
-
-static bool rproc_mem_inited __initdata;
-
-#if IS_ENABLED(CONFIG_DA8XX_REMOTEPROC)
-
-static phys_addr_t rproc_base __initdata;
-static unsigned long rproc_size __initdata;
-
-static int __init early_rproc_mem(char *p)
-{
- char *endp;
-
- if (p == NULL)
- return 0;
-
- rproc_size = memparse(p, &endp);
- if (*endp == '@')
- rproc_base = memparse(endp + 1, NULL);
-
- return 0;
-}
-early_param("rproc_mem", early_rproc_mem);
-
-void __init da8xx_rproc_reserve_cma(void)
-{
- struct cma *cma;
- int ret;
-
- if (!rproc_base || !rproc_size) {
- pr_err("%s: 'rproc_mem=nn@address' badly specified\n"
- " 'nn' and 'address' must both be non-zero\n",
- __func__);
-
- return;
- }
-
- pr_info("%s: reserving 0x%lx @ 0x%lx...\n",
- __func__, rproc_size, (unsigned long)rproc_base);
-
- ret = dma_contiguous_reserve_area(rproc_size, rproc_base, 0, &cma,
- true);
- if (ret) {
- pr_err("%s: dma_contiguous_reserve_area failed %d\n",
- __func__, ret);
- return;
- }
- da8xx_dsp.dev.cma_area = cma;
- rproc_mem_inited = true;
-}
-#else
-
-void __init da8xx_rproc_reserve_cma(void)
-{
-}
-
-#endif
-
-int __init da8xx_register_rproc(void)
-{
- int ret;
-
- if (!rproc_mem_inited) {
- pr_warn("%s: memory not reserved for DSP, not registering DSP device\n",
- __func__);
- return -ENOMEM;
- }
-
- ret = platform_device_register(&da8xx_dsp);
- if (ret)
- pr_err("%s: can't register DSP device: %d\n", __func__, ret);
-
- return ret;
-};
-
-static struct resource da8xx_rtc_resources[] = {
- {
- .start = DA8XX_RTC_BASE,
- .end = DA8XX_RTC_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
- { /* timer irq */
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
- .flags = IORESOURCE_IRQ,
- },
- { /* alarm irq */
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device da8xx_rtc_device = {
- .name = "da830-rtc",
- .id = -1,
- .num_resources = ARRAY_SIZE(da8xx_rtc_resources),
- .resource = da8xx_rtc_resources,
-};
-
-int da8xx_register_rtc(void)
-{
- return platform_device_register(&da8xx_rtc_device);
-}
-
static void __iomem *da8xx_ddr2_ctlr_base;
void __iomem * __init da8xx_get_mem_ctlr(void)
{
@@ -974,192 +68,3 @@ void __iomem * __init da8xx_get_mem_ctlr(void)
return da8xx_ddr2_ctlr_base;
}
-
-static struct resource da8xx_cpuidle_resources[] = {
- {
- .start = DA8XX_DDR2_CTL_BASE,
- .end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-/* DA8XX devices support DDR2 power down */
-static struct davinci_cpuidle_config da8xx_cpuidle_pdata = {
- .ddr2_pdown = 1,
-};
-
-
-static struct platform_device da8xx_cpuidle_device = {
- .name = "cpuidle-davinci",
- .num_resources = ARRAY_SIZE(da8xx_cpuidle_resources),
- .resource = da8xx_cpuidle_resources,
- .dev = {
- .platform_data = &da8xx_cpuidle_pdata,
- },
-};
-
-int __init da8xx_register_cpuidle(void)
-{
- da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();
-
- return platform_device_register(&da8xx_cpuidle_device);
-}
-
-static struct resource da8xx_spi0_resources[] = {
- [0] = {
- .start = DA8XX_SPI0_BASE,
- .end = DA8XX_SPI0_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT0),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT0),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct resource da8xx_spi1_resources[] = {
- [0] = {
- .start = DA830_SPI1_BASE,
- .end = DA830_SPI1_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT1),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT1),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct davinci_spi_platform_data da8xx_spi_pdata[] = {
- [0] = {
- .version = SPI_VERSION_2,
- .intr_line = 1,
- .dma_event_q = EVENTQ_0,
- .prescaler_limit = 2,
- },
- [1] = {
- .version = SPI_VERSION_2,
- .intr_line = 1,
- .dma_event_q = EVENTQ_0,
- .prescaler_limit = 2,
- },
-};
-
-static struct platform_device da8xx_spi_device[] = {
- [0] = {
- .name = "spi_davinci",
- .id = 0,
- .num_resources = ARRAY_SIZE(da8xx_spi0_resources),
- .resource = da8xx_spi0_resources,
- .dev = {
- .platform_data = &da8xx_spi_pdata[0],
- },
- },
- [1] = {
- .name = "spi_davinci",
- .id = 1,
- .num_resources = ARRAY_SIZE(da8xx_spi1_resources),
- .resource = da8xx_spi1_resources,
- .dev = {
- .platform_data = &da8xx_spi_pdata[1],
- },
- },
-};
-
-int __init da8xx_register_spi_bus(int instance, unsigned num_chipselect)
-{
- if (instance < 0 || instance > 1)
- return -EINVAL;
-
- da8xx_spi_pdata[instance].num_chipselect = num_chipselect;
-
- if (instance == 1 && cpu_is_davinci_da850()) {
- da8xx_spi1_resources[0].start = DA850_SPI1_BASE;
- da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1;
- }
-
- return platform_device_register(&da8xx_spi_device[instance]);
-}
-
-#ifdef CONFIG_ARCH_DAVINCI_DA850
-int __init da850_register_sata_refclk(int rate)
-{
- struct clk *clk;
-
- clk = clk_register_fixed_rate(NULL, "sata_refclk", NULL, 0, rate);
- if (IS_ERR(clk))
- return PTR_ERR(clk);
-
- return clk_register_clkdev(clk, "refclk", "ahci_da850");
-}
-
-static struct resource da850_sata_resources[] = {
- {
- .start = DA850_SATA_BASE,
- .end = DA850_SATA_BASE + 0x1fff,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG,
- .end = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG + 0x3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA850_SATAINT),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static u64 da850_sata_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device da850_sata_device = {
- .name = "ahci_da850",
- .id = -1,
- .dev = {
- .dma_mask = &da850_sata_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .num_resources = ARRAY_SIZE(da850_sata_resources),
- .resource = da850_sata_resources,
-};
-
-int __init da850_register_sata(unsigned long refclkpn)
-{
- int ret;
-
- ret = da850_register_sata_refclk(refclkpn);
- if (ret)
- return ret;
-
- return platform_device_register(&da850_sata_device);
-}
-#endif
-
-static struct regmap *da8xx_cfgchip;
-
-static const struct regmap_config da8xx_cfgchip_config __initconst = {
- .name = "cfgchip",
- .reg_bits = 32,
- .val_bits = 32,
- .reg_stride = 4,
- .max_register = DA8XX_CFGCHIP4_REG - DA8XX_CFGCHIP0_REG,
-};
-
-/**
- * da8xx_get_cfgchip - Lazy gets CFGCHIP as regmap
- *
- * This is for use on non-DT boards only. For DT boards, use
- * syscon_regmap_lookup_by_compatible("ti,da830-cfgchip")
- *
- * Returns: Pointer to the CFGCHIP regmap or negative error code.
- */
-struct regmap * __init da8xx_get_cfgchip(void)
-{
- if (IS_ERR_OR_NULL(da8xx_cfgchip))
- da8xx_cfgchip = regmap_init_mmio(NULL,
- DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG),
- &da8xx_cfgchip_config);
-
- return da8xx_cfgchip;
-}
diff --git a/arch/arm/mach-davinci/irqs.h b/arch/arm/mach-davinci/irqs.h
index 8f9fc7a56ce8..b1ceed81e9fa 100644
--- a/arch/arm/mach-davinci/irqs.h
+++ b/arch/arm/mach-davinci/irqs.h
@@ -27,219 +27,6 @@
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H
-/* Base address */
-#define DAVINCI_ARM_INTC_BASE 0x01C48000
-
-/* Interrupt lines */
-#define IRQ_VDINT0 0
-#define IRQ_VDINT1 1
-#define IRQ_VDINT2 2
-#define IRQ_HISTINT 3
-#define IRQ_H3AINT 4
-#define IRQ_PRVUINT 5
-#define IRQ_RSZINT 6
-#define IRQ_VFOCINT 7
-#define IRQ_VENCINT 8
-#define IRQ_ASQINT 9
-#define IRQ_IMXINT 10
-#define IRQ_VLCDINT 11
-#define IRQ_USBINT 12
-#define IRQ_EMACINT 13
-
-#define IRQ_CCINT0 16
-#define IRQ_CCERRINT 17
-#define IRQ_TCERRINT0 18
-#define IRQ_TCERRINT 19
-#define IRQ_PSCIN 20
-
-#define IRQ_IDE 22
-#define IRQ_HPIINT 23
-#define IRQ_MBXINT 24
-#define IRQ_MBRINT 25
-#define IRQ_MMCINT 26
-#define IRQ_SDIOINT 27
-#define IRQ_MSINT 28
-#define IRQ_DDRINT 29
-#define IRQ_AEMIFINT 30
-#define IRQ_VLQINT 31
-#define IRQ_TINT0_TINT12 32
-#define IRQ_TINT0_TINT34 33
-#define IRQ_TINT1_TINT12 34
-#define IRQ_TINT1_TINT34 35
-#define IRQ_PWMINT0 36
-#define IRQ_PWMINT1 37
-#define IRQ_PWMINT2 38
-#define IRQ_I2C 39
-#define IRQ_UARTINT0 40
-#define IRQ_UARTINT1 41
-#define IRQ_UARTINT2 42
-#define IRQ_SPINT0 43
-#define IRQ_SPINT1 44
-
-#define IRQ_DSP2ARM0 46
-#define IRQ_DSP2ARM1 47
-#define IRQ_GPIO0 48
-#define IRQ_GPIO1 49
-#define IRQ_GPIO2 50
-#define IRQ_GPIO3 51
-#define IRQ_GPIO4 52
-#define IRQ_GPIO5 53
-#define IRQ_GPIO6 54
-#define IRQ_GPIO7 55
-#define IRQ_GPIOBNK0 56
-#define IRQ_GPIOBNK1 57
-#define IRQ_GPIOBNK2 58
-#define IRQ_GPIOBNK3 59
-#define IRQ_GPIOBNK4 60
-#define IRQ_COMMTX 61
-#define IRQ_COMMRX 62
-#define IRQ_EMUINT 63
-
-#define DAVINCI_N_AINTC_IRQ 64
-
-#define ARCH_TIMER_IRQ IRQ_TINT1_TINT34
-
-/* DaVinci DM6467-specific Interrupts */
-#define IRQ_DM646X_VP_VERTINT0 0
-#define IRQ_DM646X_VP_VERTINT1 1
-#define IRQ_DM646X_VP_VERTINT2 2
-#define IRQ_DM646X_VP_VERTINT3 3
-#define IRQ_DM646X_VP_ERRINT 4
-#define IRQ_DM646X_RESERVED_1 5
-#define IRQ_DM646X_RESERVED_2 6
-#define IRQ_DM646X_WDINT 7
-#define IRQ_DM646X_CRGENINT0 8
-#define IRQ_DM646X_CRGENINT1 9
-#define IRQ_DM646X_TSIFINT0 10
-#define IRQ_DM646X_TSIFINT1 11
-#define IRQ_DM646X_VDCEINT 12
-#define IRQ_DM646X_USBINT 13
-#define IRQ_DM646X_USBDMAINT 14
-#define IRQ_DM646X_PCIINT 15
-#define IRQ_DM646X_TCERRINT2 20
-#define IRQ_DM646X_TCERRINT3 21
-#define IRQ_DM646X_IDE 22
-#define IRQ_DM646X_HPIINT 23
-#define IRQ_DM646X_EMACRXTHINT 24
-#define IRQ_DM646X_EMACRXINT 25
-#define IRQ_DM646X_EMACTXINT 26
-#define IRQ_DM646X_EMACMISCINT 27
-#define IRQ_DM646X_MCASP0TXINT 28
-#define IRQ_DM646X_MCASP0RXINT 29
-#define IRQ_DM646X_MCASP1TXINT 30
-#define IRQ_DM646X_RESERVED_3 31
-#define IRQ_DM646X_VLQINT 38
-#define IRQ_DM646X_UARTINT2 42
-#define IRQ_DM646X_SPINT0 43
-#define IRQ_DM646X_SPINT1 44
-#define IRQ_DM646X_DSP2ARMINT 45
-#define IRQ_DM646X_RESERVED_4 46
-#define IRQ_DM646X_PSCINT 47
-#define IRQ_DM646X_GPIO0 48
-#define IRQ_DM646X_GPIO1 49
-#define IRQ_DM646X_GPIO2 50
-#define IRQ_DM646X_GPIO3 51
-#define IRQ_DM646X_GPIO4 52
-#define IRQ_DM646X_GPIO5 53
-#define IRQ_DM646X_GPIO6 54
-#define IRQ_DM646X_GPIO7 55
-#define IRQ_DM646X_GPIOBNK0 56
-#define IRQ_DM646X_GPIOBNK1 57
-#define IRQ_DM646X_GPIOBNK2 58
-#define IRQ_DM646X_DDRINT 59
-#define IRQ_DM646X_AEMIFINT 60
-
-/* DaVinci DM355-specific Interrupts */
-#define IRQ_DM355_CCDC_VDINT0 0
-#define IRQ_DM355_CCDC_VDINT1 1
-#define IRQ_DM355_CCDC_VDINT2 2
-#define IRQ_DM355_IPIPE_HST 3
-#define IRQ_DM355_H3AINT 4
-#define IRQ_DM355_IPIPE_SDR 5
-#define IRQ_DM355_IPIPEIFINT 6
-#define IRQ_DM355_OSDINT 7
-#define IRQ_DM355_VENCINT 8
-#define IRQ_DM355_IMCOPINT 11
-#define IRQ_DM355_RTOINT 13
-#define IRQ_DM355_TINT4 13
-#define IRQ_DM355_TINT2_TINT12 13
-#define IRQ_DM355_UARTINT2 14
-#define IRQ_DM355_TINT5 14
-#define IRQ_DM355_TINT2_TINT34 14
-#define IRQ_DM355_TINT6 15
-#define IRQ_DM355_TINT3_TINT12 15
-#define IRQ_DM355_SPINT1_0 17
-#define IRQ_DM355_SPINT1_1 18
-#define IRQ_DM355_SPINT2_0 19
-#define IRQ_DM355_SPINT2_1 21
-#define IRQ_DM355_TINT7 22
-#define IRQ_DM355_TINT3_TINT34 22
-#define IRQ_DM355_SDIOINT0 23
-#define IRQ_DM355_MMCINT0 26
-#define IRQ_DM355_MSINT 26
-#define IRQ_DM355_MMCINT1 27
-#define IRQ_DM355_PWMINT3 28
-#define IRQ_DM355_SDIOINT1 31
-#define IRQ_DM355_SPINT0_0 42
-#define IRQ_DM355_SPINT0_1 43
-#define IRQ_DM355_GPIO0 44
-#define IRQ_DM355_GPIO1 45
-#define IRQ_DM355_GPIO2 46
-#define IRQ_DM355_GPIO3 47
-#define IRQ_DM355_GPIO4 48
-#define IRQ_DM355_GPIO5 49
-#define IRQ_DM355_GPIO6 50
-#define IRQ_DM355_GPIO7 51
-#define IRQ_DM355_GPIO8 52
-#define IRQ_DM355_GPIO9 53
-#define IRQ_DM355_GPIOBNK0 54
-#define IRQ_DM355_GPIOBNK1 55
-#define IRQ_DM355_GPIOBNK2 56
-#define IRQ_DM355_GPIOBNK3 57
-#define IRQ_DM355_GPIOBNK4 58
-#define IRQ_DM355_GPIOBNK5 59
-#define IRQ_DM355_GPIOBNK6 60
-
-/* DaVinci DM365-specific Interrupts */
-#define IRQ_DM365_INSFINT 7
-#define IRQ_DM365_IMXINT1 8
-#define IRQ_DM365_IMXINT0 10
-#define IRQ_DM365_KLD_ARMINT 10
-#define IRQ_DM365_IMCOPINT 11
-#define IRQ_DM365_RTOINT 13
-#define IRQ_DM365_TINT5 14
-#define IRQ_DM365_TINT6 15
-#define IRQ_DM365_SPINT2_1 21
-#define IRQ_DM365_TINT7 22
-#define IRQ_DM365_SDIOINT0 23
-#define IRQ_DM365_MMCINT1 27
-#define IRQ_DM365_PWMINT3 28
-#define IRQ_DM365_RTCINT 29
-#define IRQ_DM365_SDIOINT1 31
-#define IRQ_DM365_SPIINT0_0 42
-#define IRQ_DM365_SPIINT3_0 43
-#define IRQ_DM365_GPIO0 44
-#define IRQ_DM365_GPIO1 45
-#define IRQ_DM365_GPIO2 46
-#define IRQ_DM365_GPIO3 47
-#define IRQ_DM365_GPIO4 48
-#define IRQ_DM365_GPIO5 49
-#define IRQ_DM365_GPIO6 50
-#define IRQ_DM365_GPIO7 51
-#define IRQ_DM365_EMAC_RXTHRESH 52
-#define IRQ_DM365_EMAC_RXPULSE 53
-#define IRQ_DM365_EMAC_TXPULSE 54
-#define IRQ_DM365_EMAC_MISCPULSE 55
-#define IRQ_DM365_GPIO12 56
-#define IRQ_DM365_GPIO13 57
-#define IRQ_DM365_GPIO14 58
-#define IRQ_DM365_GPIO15 59
-#define IRQ_DM365_ADCINT 59
-#define IRQ_DM365_KEYINT 60
-#define IRQ_DM365_TCERRINT2 61
-#define IRQ_DM365_TCERRINT3 62
-#define IRQ_DM365_EMUINT 63
-
/* DA8XX interrupts */
#define IRQ_DA8XX_COMMTX 0
#define IRQ_DA8XX_COMMRX 1
@@ -398,8 +185,4 @@
#define DA850_N_CP_INTC_IRQ 101
-/* da850 currently has the most gpio pins (144) */
-#define DAVINCI_N_GPIO 144
-/* da850 currently has the most irqs so use DA850_N_CP_INTC_IRQ */
-
#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c
index 814a6b714010..37de35eb6e8b 100644
--- a/arch/arm/mach-davinci/mux.c
+++ b/arch/arm/mach-davinci/mux.c
@@ -97,18 +97,3 @@ int davinci_cfg_reg(const unsigned long index)
return 0;
}
-EXPORT_SYMBOL(davinci_cfg_reg);
-
-int davinci_cfg_reg_list(const short pins[])
-{
- int i, error = -EINVAL;
-
- if (pins)
- for (i = 0; pins[i] >= 0; i++) {
- error = davinci_cfg_reg(pins[i]);
- if (error)
- break;
- }
-
- return error;
-}
diff --git a/arch/arm/mach-davinci/mux.h b/arch/arm/mach-davinci/mux.h
index b5effe16402c..38f0e427291e 100644
--- a/arch/arm/mach-davinci/mux.h
+++ b/arch/arm/mach-davinci/mux.h
@@ -21,321 +21,6 @@ struct mux_config {
bool debug;
};
-enum davinci_dm644x_index {
- /* ATA and HDDIR functions */
- DM644X_HDIREN,
- DM644X_ATAEN,
- DM644X_ATAEN_DISABLE,
-
- /* HPI functions */
- DM644X_HPIEN_DISABLE,
-
- /* AEAW functions */
- DM644X_AEAW,
- DM644X_AEAW0,
- DM644X_AEAW1,
- DM644X_AEAW2,
- DM644X_AEAW3,
- DM644X_AEAW4,
-
- /* Memory Stick */
- DM644X_MSTK,
-
- /* I2C */
- DM644X_I2C,
-
- /* ASP function */
- DM644X_MCBSP,
-
- /* UART1 */
- DM644X_UART1,
-
- /* UART2 */
- DM644X_UART2,
-
- /* PWM0 */
- DM644X_PWM0,
-
- /* PWM1 */
- DM644X_PWM1,
-
- /* PWM2 */
- DM644X_PWM2,
-
- /* VLYNQ function */
- DM644X_VLYNQEN,
- DM644X_VLSCREN,
- DM644X_VLYNQWD,
-
- /* EMAC and MDIO function */
- DM644X_EMACEN,
-
- /* GPIO3V[0:16] pins */
- DM644X_GPIO3V,
-
- /* GPIO pins */
- DM644X_GPIO0,
- DM644X_GPIO3,
- DM644X_GPIO43_44,
- DM644X_GPIO46_47,
-
- /* VPBE */
- DM644X_RGB666,
-
- /* LCD */
- DM644X_LOEEN,
- DM644X_LFLDEN,
-};
-
-enum davinci_dm646x_index {
- /* ATA function */
- DM646X_ATAEN,
-
- /* AUDIO Clock */
- DM646X_AUDCK1,
- DM646X_AUDCK0,
-
- /* CRGEN Control */
- DM646X_CRGMUX,
-
- /* VPIF Control */
- DM646X_STSOMUX_DISABLE,
- DM646X_STSIMUX_DISABLE,
- DM646X_PTSOMUX_DISABLE,
- DM646X_PTSIMUX_DISABLE,
-
- /* TSIF Control */
- DM646X_STSOMUX,
- DM646X_STSIMUX,
- DM646X_PTSOMUX_PARALLEL,
- DM646X_PTSIMUX_PARALLEL,
- DM646X_PTSOMUX_SERIAL,
- DM646X_PTSIMUX_SERIAL,
-};
-
-enum davinci_dm355_index {
- /* MMC/SD 0 */
- DM355_MMCSD0,
-
- /* MMC/SD 1 */
- DM355_SD1_CLK,
- DM355_SD1_CMD,
- DM355_SD1_DATA3,
- DM355_SD1_DATA2,
- DM355_SD1_DATA1,
- DM355_SD1_DATA0,
-
- /* I2C */
- DM355_I2C_SDA,
- DM355_I2C_SCL,
-
- /* ASP0 function */
- DM355_MCBSP0_BDX,
- DM355_MCBSP0_X,
- DM355_MCBSP0_BFSX,
- DM355_MCBSP0_BDR,
- DM355_MCBSP0_R,
- DM355_MCBSP0_BFSR,
-
- /* SPI0 */
- DM355_SPI0_SDI,
- DM355_SPI0_SDENA0,
- DM355_SPI0_SDENA1,
-
- /* IRQ muxing */
- DM355_INT_EDMA_CC,
- DM355_INT_EDMA_TC0_ERR,
- DM355_INT_EDMA_TC1_ERR,
-
- /* EDMA event muxing */
- DM355_EVT8_ASP1_TX,
- DM355_EVT9_ASP1_RX,
- DM355_EVT26_MMC0_RX,
-
- /* Video Out */
- DM355_VOUT_FIELD,
- DM355_VOUT_FIELD_G70,
- DM355_VOUT_HVSYNC,
- DM355_VOUT_COUTL_EN,
- DM355_VOUT_COUTH_EN,
-
- /* Video In Pin Mux */
- DM355_VIN_PCLK,
- DM355_VIN_CAM_WEN,
- DM355_VIN_CAM_VD,
- DM355_VIN_CAM_HD,
- DM355_VIN_YIN_EN,
- DM355_VIN_CINL_EN,
- DM355_VIN_CINH_EN,
-};
-
-enum davinci_dm365_index {
- /* MMC/SD 0 */
- DM365_MMCSD0,
-
- /* MMC/SD 1 */
- DM365_SD1_CLK,
- DM365_SD1_CMD,
- DM365_SD1_DATA3,
- DM365_SD1_DATA2,
- DM365_SD1_DATA1,
- DM365_SD1_DATA0,
-
- /* I2C */
- DM365_I2C_SDA,
- DM365_I2C_SCL,
-
- /* AEMIF */
- DM365_AEMIF_AR_A14,
- DM365_AEMIF_AR_BA0,
- DM365_AEMIF_A3,
- DM365_AEMIF_A7,
- DM365_AEMIF_D15_8,
- DM365_AEMIF_CE0,
- DM365_AEMIF_CE1,
- DM365_AEMIF_WE_OE,
-
- /* ASP0 function */
- DM365_MCBSP0_BDX,
- DM365_MCBSP0_X,
- DM365_MCBSP0_BFSX,
- DM365_MCBSP0_BDR,
- DM365_MCBSP0_R,
- DM365_MCBSP0_BFSR,
-
- /* SPI0 */
- DM365_SPI0_SCLK,
- DM365_SPI0_SDI,
- DM365_SPI0_SDO,
- DM365_SPI0_SDENA0,
- DM365_SPI0_SDENA1,
-
- /* UART */
- DM365_UART0_RXD,
- DM365_UART0_TXD,
- DM365_UART1_RXD,
- DM365_UART1_TXD,
- DM365_UART1_RTS,
- DM365_UART1_CTS,
-
- /* EMAC */
- DM365_EMAC_TX_EN,
- DM365_EMAC_TX_CLK,
- DM365_EMAC_COL,
- DM365_EMAC_TXD3,
- DM365_EMAC_TXD2,
- DM365_EMAC_TXD1,
- DM365_EMAC_TXD0,
- DM365_EMAC_RXD3,
- DM365_EMAC_RXD2,
- DM365_EMAC_RXD1,
- DM365_EMAC_RXD0,
- DM365_EMAC_RX_CLK,
- DM365_EMAC_RX_DV,
- DM365_EMAC_RX_ER,
- DM365_EMAC_CRS,
- DM365_EMAC_MDIO,
- DM365_EMAC_MDCLK,
-
- /* Key Scan */
- DM365_KEYSCAN,
-
- /* PWM */
- DM365_PWM0,
- DM365_PWM0_G23,
- DM365_PWM1,
- DM365_PWM1_G25,
- DM365_PWM2_G87,
- DM365_PWM2_G88,
- DM365_PWM2_G89,
- DM365_PWM2_G90,
- DM365_PWM3_G80,
- DM365_PWM3_G81,
- DM365_PWM3_G85,
- DM365_PWM3_G86,
-
- /* SPI1 */
- DM365_SPI1_SCLK,
- DM365_SPI1_SDO,
- DM365_SPI1_SDI,
- DM365_SPI1_SDENA0,
- DM365_SPI1_SDENA1,
-
- /* SPI2 */
- DM365_SPI2_SCLK,
- DM365_SPI2_SDO,
- DM365_SPI2_SDI,
- DM365_SPI2_SDENA0,
- DM365_SPI2_SDENA1,
-
- /* SPI3 */
- DM365_SPI3_SCLK,
- DM365_SPI3_SDO,
- DM365_SPI3_SDI,
- DM365_SPI3_SDENA0,
- DM365_SPI3_SDENA1,
-
- /* SPI4 */
- DM365_SPI4_SCLK,
- DM365_SPI4_SDO,
- DM365_SPI4_SDI,
- DM365_SPI4_SDENA0,
- DM365_SPI4_SDENA1,
-
- /* Clock */
- DM365_CLKOUT0,
- DM365_CLKOUT1,
- DM365_CLKOUT2,
-
- /* GPIO */
- DM365_GPIO20,
- DM365_GPIO30,
- DM365_GPIO31,
- DM365_GPIO32,
- DM365_GPIO33,
- DM365_GPIO40,
- DM365_GPIO64_57,
-
- /* Video */
- DM365_VOUT_FIELD,
- DM365_VOUT_FIELD_G81,
- DM365_VOUT_HVSYNC,
- DM365_VOUT_COUTL_EN,
- DM365_VOUT_COUTH_EN,
- DM365_VIN_CAM_WEN,
- DM365_VIN_CAM_VD,
- DM365_VIN_CAM_HD,
- DM365_VIN_YIN4_7_EN,
- DM365_VIN_YIN0_3_EN,
-
- /* IRQ muxing */
- DM365_INT_EDMA_CC,
- DM365_INT_EDMA_TC0_ERR,
- DM365_INT_EDMA_TC1_ERR,
- DM365_INT_EDMA_TC2_ERR,
- DM365_INT_EDMA_TC3_ERR,
- DM365_INT_PRTCSS,
- DM365_INT_EMAC_RXTHRESH,
- DM365_INT_EMAC_RXPULSE,
- DM365_INT_EMAC_TXPULSE,
- DM365_INT_EMAC_MISCPULSE,
- DM365_INT_IMX0_ENABLE,
- DM365_INT_IMX0_DISABLE,
- DM365_INT_HDVICP_ENABLE,
- DM365_INT_HDVICP_DISABLE,
- DM365_INT_IMX1_ENABLE,
- DM365_INT_IMX1_DISABLE,
- DM365_INT_NSF_ENABLE,
- DM365_INT_NSF_DISABLE,
-
- /* EDMA event muxing */
- DM365_EVT2_ASP_TX,
- DM365_EVT3_ASP_RX,
- DM365_EVT2_VC_TX,
- DM365_EVT3_VC_RX,
- DM365_EVT26_MMC0_RX,
-};
-
enum da830_index {
DA830_GPIO7_14,
DA830_RTCK,
diff --git a/arch/arm/mach-davinci/psc.h b/arch/arm/mach-davinci/psc.h
index 68cd9d3fc82b..acfef063295f 100644
--- a/arch/arm/mach-davinci/psc.h
+++ b/arch/arm/mach-davinci/psc.h
@@ -70,70 +70,6 @@
#define DAVINCI_LPSC_GEM 39
#define DAVINCI_LPSC_IMCOP 40
-#define DM355_LPSC_TIMER3 5
-#define DM355_LPSC_SPI1 6
-#define DM355_LPSC_MMC_SD1 7
-#define DM355_LPSC_McBSP1 8
-#define DM355_LPSC_PWM3 10
-#define DM355_LPSC_SPI2 11
-#define DM355_LPSC_RTO 12
-#define DM355_LPSC_VPSS_DAC 41
-
-/* DM365 */
-#define DM365_LPSC_TIMER3 5
-#define DM365_LPSC_SPI1 6
-#define DM365_LPSC_MMC_SD1 7
-#define DM365_LPSC_McBSP1 8
-#define DM365_LPSC_PWM3 10
-#define DM365_LPSC_SPI2 11
-#define DM365_LPSC_RTO 12
-#define DM365_LPSC_TIMER4 17
-#define DM365_LPSC_SPI0 22
-#define DM365_LPSC_SPI3 38
-#define DM365_LPSC_SPI4 39
-#define DM365_LPSC_EMAC 40
-#define DM365_LPSC_VOICE_CODEC 44
-#define DM365_LPSC_DAC_CLK 46
-#define DM365_LPSC_VPSSMSTR 47
-#define DM365_LPSC_MJCP 50
-
-/*
- * LPSC Assignments
- */
-#define DM646X_LPSC_ARM 0
-#define DM646X_LPSC_C64X_CPU 1
-#define DM646X_LPSC_HDVICP0 2
-#define DM646X_LPSC_HDVICP1 3
-#define DM646X_LPSC_TPCC 4
-#define DM646X_LPSC_TPTC0 5
-#define DM646X_LPSC_TPTC1 6
-#define DM646X_LPSC_TPTC2 7
-#define DM646X_LPSC_TPTC3 8
-#define DM646X_LPSC_PCI 13
-#define DM646X_LPSC_EMAC 14
-#define DM646X_LPSC_VDCE 15
-#define DM646X_LPSC_VPSSMSTR 16
-#define DM646X_LPSC_VPSSSLV 17
-#define DM646X_LPSC_TSIF0 18
-#define DM646X_LPSC_TSIF1 19
-#define DM646X_LPSC_DDR_EMIF 20
-#define DM646X_LPSC_AEMIF 21
-#define DM646X_LPSC_McASP0 22
-#define DM646X_LPSC_McASP1 23
-#define DM646X_LPSC_CRGEN0 24
-#define DM646X_LPSC_CRGEN1 25
-#define DM646X_LPSC_UART0 26
-#define DM646X_LPSC_UART1 27
-#define DM646X_LPSC_UART2 28
-#define DM646X_LPSC_PWM0 29
-#define DM646X_LPSC_PWM1 30
-#define DM646X_LPSC_I2C 31
-#define DM646X_LPSC_SPI 32
-#define DM646X_LPSC_GPIO 33
-#define DM646X_LPSC_TIMER0 34
-#define DM646X_LPSC_TIMER1 35
-#define DM646X_LPSC_ARM_INTC 45
-
/* PSC0 defines */
#define DA8XX_LPSC0_TPCC 0
#define DA8XX_LPSC0_TPTC0 1
diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c
deleted file mode 100644
index ac1929bb0ef2..000000000000
--- a/arch/arm/mach-davinci/serial.c
+++ /dev/null
@@ -1,88 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * TI DaVinci serial driver
- *
- * Copyright (C) 2006 Texas Instruments.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/serial_8250.h>
-#include <linux/serial_reg.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-
-#include "serial.h"
-#include "cputype.h"
-
-static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
- int value)
-{
- offset <<= p->regshift;
-
- WARN_ONCE(!p->membase, "unmapped write: uart[%d]\n", offset);
-
- __raw_writel(value, p->membase + offset);
-}
-
-static void __init davinci_serial_reset(struct plat_serial8250_port *p)
-{
- unsigned int pwremu = 0;
-
- serial_write_reg(p, UART_IER, 0); /* disable all interrupts */
-
- /* reset both transmitter and receiver: bits 14,13 = UTRST, URRST */
- serial_write_reg(p, UART_DAVINCI_PWREMU, pwremu);
- mdelay(10);
-
- pwremu |= (0x3 << 13);
- pwremu |= 0x1;
- serial_write_reg(p, UART_DAVINCI_PWREMU, pwremu);
-}
-
-int __init davinci_serial_init(struct platform_device *serial_dev)
-{
- int i, ret = 0;
- struct device *dev;
- struct plat_serial8250_port *p;
- struct clk *clk;
-
- /*
- * Make sure the serial ports are muxed on at this point.
- * You have to mux them off in device drivers later on if not needed.
- */
- for (i = 0; serial_dev[i].dev.platform_data != NULL; i++) {
- dev = &serial_dev[i].dev;
- p = dev->platform_data;
-
- ret = platform_device_register(&serial_dev[i]);
- if (ret)
- continue;
-
- clk = clk_get(dev, NULL);
- if (IS_ERR(clk)) {
- pr_err("%s:%d: failed to get UART%d clock\n",
- __func__, __LINE__, i);
- continue;
- }
-
- clk_prepare_enable(clk);
-
- p->uartclk = clk_get_rate(clk);
-
- if (!p->membase && p->mapbase) {
- p->membase = ioremap(p->mapbase, SZ_4K);
-
- if (p->membase)
- p->flags &= ~UPF_IOREMAP;
- else
- pr_err("uart regs ioremap failed\n");
- }
-
- if (p->membase && p->type != PORT_AR7)
- davinci_serial_reset(p);
- }
- return ret;
-}
diff --git a/arch/arm/mach-davinci/serial.h b/arch/arm/mach-davinci/serial.h
deleted file mode 100644
index c4a4ba553d45..000000000000
--- a/arch/arm/mach-davinci/serial.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * DaVinci serial device definitions
- *
- * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
- *
- * 2007 (c) MontaVista Software, Inc.
- */
-#ifndef __ASM_ARCH_SERIAL_H
-#define __ASM_ARCH_SERIAL_H
-
-#include <asm/memory.h>
-
-#include "hardware.h"
-
-#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000)
-#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400)
-#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800)
-
-#define DA8XX_UART0_BASE (IO_PHYS + 0x042000)
-#define DA8XX_UART1_BASE (IO_PHYS + 0x10c000)
-#define DA8XX_UART2_BASE (IO_PHYS + 0x10d000)
-
-/* DaVinci UART register offsets */
-#define UART_DAVINCI_PWREMU 0x0c
-#define UART_DM646X_SCR 0x10
-#define UART_DM646X_SCR_TX_WATERMARK 0x08
-
-#ifndef __ASSEMBLY__
-#include <linux/platform_device.h>
-
-extern int davinci_serial_init(struct platform_device *);
-#endif
-
-#endif /* __ASM_ARCH_SERIAL_H */
diff --git a/arch/arm/mach-davinci/usb-da8xx.c b/arch/arm/mach-davinci/usb-da8xx.c
deleted file mode 100644
index 9c8fc5031907..000000000000
--- a/arch/arm/mach-davinci/usb-da8xx.c
+++ /dev/null
@@ -1,146 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * DA8xx USB
- */
-#include <linux/clk-provider.h>
-#include <linux/delay.h>
-#include <linux/dma-mapping.h>
-#include <linux/init.h>
-#include <linux/mfd/da8xx-cfgchip.h>
-#include <linux/mfd/syscon.h>
-#include <linux/phy/phy.h>
-#include <linux/platform_data/clk-da8xx-cfgchip.h>
-#include <linux/platform_data/phy-da8xx-usb.h>
-#include <linux/platform_data/usb-davinci.h>
-#include <linux/platform_device.h>
-#include <linux/usb/musb.h>
-
-#include "common.h"
-#include "cputype.h"
-#include "da8xx.h"
-#include "irqs.h"
-
-#define DA8XX_USB0_BASE 0x01e00000
-#define DA8XX_USB1_BASE 0x01e25000
-
-#ifndef CONFIG_COMMON_CLK
-static struct clk *usb20_clk;
-#endif
-
-static struct da8xx_usb_phy_platform_data da8xx_usb_phy_pdata;
-
-static struct platform_device da8xx_usb_phy = {
- .name = "da8xx-usb-phy",
- .id = -1,
- .dev = {
- /*
- * Setting init_name so that clock lookup will work in
- * da8xx_register_usb11_phy_clk() even if this device is not
- * registered yet.
- */
- .init_name = "da8xx-usb-phy",
- .platform_data = &da8xx_usb_phy_pdata,
- },
-};
-
-int __init da8xx_register_usb_phy(void)
-{
- da8xx_usb_phy_pdata.cfgchip = da8xx_get_cfgchip();
-
- return platform_device_register(&da8xx_usb_phy);
-}
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = true,
- .num_eps = 5,
- .ram_bits = 10,
-};
-
-static struct musb_hdrc_platform_data usb_data = {
- /* OTG requires a Mini-AB connector */
- .mode = MUSB_OTG,
- .clock = "usb20",
- .config = &musb_config,
-};
-
-static struct resource da8xx_usb20_resources[] = {
- {
- .start = DA8XX_USB0_BASE,
- .end = DA8XX_USB0_BASE + SZ_64K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_USB_INT),
- .flags = IORESOURCE_IRQ,
- .name = "mc",
- },
-};
-
-static u64 usb_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device da8xx_usb20_dev = {
- .name = "musb-da8xx",
- .id = -1,
- .dev = {
- .platform_data = &usb_data,
- .dma_mask = &usb_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .resource = da8xx_usb20_resources,
- .num_resources = ARRAY_SIZE(da8xx_usb20_resources),
-};
-
-int __init da8xx_register_usb20(unsigned int mA, unsigned int potpgt)
-{
- usb_data.power = mA > 510 ? 255 : mA / 2;
- usb_data.potpgt = (potpgt + 1) / 2;
-
- return platform_device_register(&da8xx_usb20_dev);
-}
-
-static struct resource da8xx_usb11_resources[] = {
- [0] = {
- .start = DA8XX_USB1_BASE,
- .end = DA8XX_USB1_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_IRQN),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_IRQN),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static u64 da8xx_usb11_dma_mask = DMA_BIT_MASK(32);
-
-static struct platform_device da8xx_usb11_device = {
- .name = "ohci-da8xx",
- .id = -1,
- .dev = {
- .dma_mask = &da8xx_usb11_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .num_resources = ARRAY_SIZE(da8xx_usb11_resources),
- .resource = da8xx_usb11_resources,
-};
-
-int __init da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata)
-{
- da8xx_usb11_device.dev.platform_data = pdata;
- return platform_device_register(&da8xx_usb11_device);
-}
-
-static struct platform_device da8xx_usb_phy_clks_device = {
- .name = "da830-usb-phy-clks",
- .id = -1,
-};
-
-int __init da8xx_register_usb_phy_clocks(void)
-{
- struct da8xx_cfgchip_clk_platform_data pdata;
-
- pdata.cfgchip = da8xx_get_cfgchip();
- da8xx_usb_phy_clks_device.dev.platform_data = &pdata;
-
- return platform_device_register(&da8xx_usb_phy_clks_device);
-}
diff --git a/arch/arm/mach-davinci/usb.c b/arch/arm/mach-davinci/usb.c
deleted file mode 100644
index 9dc14c7977b3..000000000000
--- a/arch/arm/mach-davinci/usb.c
+++ /dev/null
@@ -1,74 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * USB
- */
-#include <linux/dma-mapping.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/platform_data/usb-davinci.h>
-#include <linux/usb/musb.h>
-
-#include "common.h"
-#include "cputype.h"
-#include "irqs.h"
-
-#define DAVINCI_USB_OTG_BASE 0x01c64000
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-static struct musb_hdrc_config musb_config = {
- .multipoint = true,
-
- .num_eps = 5,
- .ram_bits = 10,
-};
-
-static struct musb_hdrc_platform_data usb_data = {
- /* OTG requires a Mini-AB connector */
- .mode = MUSB_OTG,
- .clock = "usb",
- .config = &musb_config,
-};
-
-static struct resource usb_resources[] = {
- {
- /* physical address */
- .start = DAVINCI_USB_OTG_BASE,
- .end = DAVINCI_USB_OTG_BASE + 0x5ff,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_USBINT),
- .flags = IORESOURCE_IRQ,
- .name = "mc"
- },
-};
-
-static u64 usb_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device usb_dev = {
- .name = "musb-davinci",
- .id = -1,
- .dev = {
- .platform_data = &usb_data,
- .dma_mask = &usb_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .resource = usb_resources,
- .num_resources = ARRAY_SIZE(usb_resources),
-};
-
-void __init davinci_setup_usb(unsigned mA, unsigned potpgt_ms)
-{
- usb_data.power = mA > 510 ? 255 : mA / 2;
- usb_data.potpgt = (potpgt_ms + 1) / 2;
-
- platform_device_register(&usb_dev);
-}
-
-#else
-
-void __init davinci_setup_usb(unsigned mA, unsigned potpgt_ms)
-{
-}
-
-#endif /* CONFIG_USB_MUSB_HDRC */
--
2.29.2
^ permalink raw reply related [flat|nested] 48+ messages in thread* Re: [PATCH 03/14] ARM: davinci: clean up platform support
2022-10-19 15:29 ` [PATCH 03/14] ARM: davinci: clean up platform support Arnd Bergmann
@ 2022-10-20 11:32 ` Bartosz Golaszewski
0 siblings, 0 replies; 48+ messages in thread
From: Bartosz Golaszewski @ 2022-10-20 11:32 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Sekhar Nori, linux-arm-kernel, linux-kernel, Kevin Hilman, Arnd Bergmann
On Wed, Oct 19, 2022 at 5:33 PM Arnd Bergmann <arnd@kernel.org> wrote:
>
> From: Arnd Bergmann <arnd@arndb.de>
>
> With the board file support gone, and the platform using
> DT only, a lot of the remaining code is no longer referenced
> and can be removed.
>
> Technically, the DT file only references DA850, but since that
> is very similar to DA830, I'm leaving the latter.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH 04/14] clk: remove davinci dm3xx drivers
2022-10-19 15:29 [PATCH 00/14] ARM: remove unused davinci board & drivers Arnd Bergmann
` (2 preceding siblings ...)
2022-10-19 15:29 ` [PATCH 03/14] ARM: davinci: clean up platform support Arnd Bergmann
@ 2022-10-19 15:29 ` Arnd Bergmann
2022-10-19 16:39 ` David Lechner
` (3 more replies)
2022-10-19 15:29 ` [PATCH 05/14] usb: musb: remove unused davinci support Arnd Bergmann
` (12 subsequent siblings)
16 siblings, 4 replies; 48+ messages in thread
From: Arnd Bergmann @ 2022-10-19 15:29 UTC (permalink / raw)
To: Sekhar Nori, Bartosz Golaszewski, linux-arm-kernel,
David Lechner, Michael Turquette, Stephen Boyd
Cc: linux-kernel, Kevin Hilman, Arnd Bergmann, Lukas Bulwahn,
Linus Walleij, linux-clk
From: Arnd Bergmann <arnd@arndb.de>
The davinci dm3xx machines are all removed, so the clk driver
is no longer needed. The da8xx platforms are now using DT
exclusively, so those drivers remain untouched.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
drivers/clk/davinci/Makefile | 4 -
drivers/clk/davinci/pll-dm355.c | 77 -----------------
drivers/clk/davinci/pll-dm365.c | 146 --------------------------------
drivers/clk/davinci/psc-dm355.c | 89 -------------------
drivers/clk/davinci/psc-dm365.c | 111 ------------------------
5 files changed, 427 deletions(-)
delete mode 100644 drivers/clk/davinci/pll-dm355.c
delete mode 100644 drivers/clk/davinci/pll-dm365.c
delete mode 100644 drivers/clk/davinci/psc-dm355.c
delete mode 100644 drivers/clk/davinci/psc-dm365.c
diff --git a/drivers/clk/davinci/Makefile b/drivers/clk/davinci/Makefile
index be6f55d37b49..5d0ae1ee72ec 100644
--- a/drivers/clk/davinci/Makefile
+++ b/drivers/clk/davinci/Makefile
@@ -6,12 +6,8 @@ obj-$(CONFIG_ARCH_DAVINCI_DA8XX) += da8xx-cfgchip.o
obj-y += pll.o
obj-$(CONFIG_ARCH_DAVINCI_DA830) += pll-da830.o
obj-$(CONFIG_ARCH_DAVINCI_DA850) += pll-da850.o
-obj-$(CONFIG_ARCH_DAVINCI_DM355) += pll-dm355.o
-obj-$(CONFIG_ARCH_DAVINCI_DM365) += pll-dm365.o
obj-y += psc.o
obj-$(CONFIG_ARCH_DAVINCI_DA830) += psc-da830.o
obj-$(CONFIG_ARCH_DAVINCI_DA850) += psc-da850.o
-obj-$(CONFIG_ARCH_DAVINCI_DM355) += psc-dm355.o
-obj-$(CONFIG_ARCH_DAVINCI_DM365) += psc-dm365.o
endif
diff --git a/drivers/clk/davinci/pll-dm355.c b/drivers/clk/davinci/pll-dm355.c
deleted file mode 100644
index 505aed80be9a..000000000000
--- a/drivers/clk/davinci/pll-dm355.c
+++ /dev/null
@@ -1,77 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * PLL clock descriptions for TI DM355
- *
- * Copyright (C) 2018 David Lechner <david@lechnology.com>
- */
-
-#include <linux/bitops.h>
-#include <linux/clk/davinci.h>
-#include <linux/clkdev.h>
-#include <linux/init.h>
-#include <linux/types.h>
-
-#include "pll.h"
-
-static const struct davinci_pll_clk_info dm355_pll1_info = {
- .name = "pll1",
- .pllm_mask = GENMASK(7, 0),
- .pllm_min = 92,
- .pllm_max = 184,
- .flags = PLL_HAS_CLKMODE | PLL_HAS_PREDIV | PLL_PREDIV_ALWAYS_ENABLED |
- PLL_PREDIV_FIXED8 | PLL_HAS_POSTDIV |
- PLL_POSTDIV_ALWAYS_ENABLED | PLL_POSTDIV_FIXED_DIV,
-};
-
-SYSCLK(1, pll1_sysclk1, pll1_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
-SYSCLK(2, pll1_sysclk2, pll1_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
-SYSCLK(3, pll1_sysclk3, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
-SYSCLK(4, pll1_sysclk4, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
-
-int dm355_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
-{
- struct clk *clk;
-
- davinci_pll_clk_register(dev, &dm355_pll1_info, "ref_clk", base, cfgchip);
-
- clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
- clk_register_clkdev(clk, "pll1_sysclk1", "dm355-psc");
-
- clk = davinci_pll_sysclk_register(dev, &pll1_sysclk2, base);
- clk_register_clkdev(clk, "pll1_sysclk2", "dm355-psc");
-
- clk = davinci_pll_sysclk_register(dev, &pll1_sysclk3, base);
- clk_register_clkdev(clk, "pll1_sysclk3", "dm355-psc");
-
- clk = davinci_pll_sysclk_register(dev, &pll1_sysclk4, base);
- clk_register_clkdev(clk, "pll1_sysclk4", "dm355-psc");
-
- clk = davinci_pll_auxclk_register(dev, "pll1_auxclk", base);
- clk_register_clkdev(clk, "pll1_auxclk", "dm355-psc");
-
- davinci_pll_sysclkbp_clk_register(dev, "pll1_sysclkbp", base);
-
- return 0;
-}
-
-static const struct davinci_pll_clk_info dm355_pll2_info = {
- .name = "pll2",
- .pllm_mask = GENMASK(7, 0),
- .pllm_min = 92,
- .pllm_max = 184,
- .flags = PLL_HAS_PREDIV | PLL_PREDIV_ALWAYS_ENABLED | PLL_HAS_POSTDIV |
- PLL_POSTDIV_ALWAYS_ENABLED | PLL_POSTDIV_FIXED_DIV,
-};
-
-SYSCLK(1, pll2_sysclk1, pll2_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
-
-int dm355_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
-{
- davinci_pll_clk_register(dev, &dm355_pll2_info, "oscin", base, cfgchip);
-
- davinci_pll_sysclk_register(dev, &pll2_sysclk1, base);
-
- davinci_pll_sysclkbp_clk_register(dev, "pll2_sysclkbp", base);
-
- return 0;
-}
diff --git a/drivers/clk/davinci/pll-dm365.c b/drivers/clk/davinci/pll-dm365.c
deleted file mode 100644
index 2d29712753a3..000000000000
--- a/drivers/clk/davinci/pll-dm365.c
+++ /dev/null
@@ -1,146 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * PLL clock descriptions for TI DM365
- *
- * Copyright (C) 2018 David Lechner <david@lechnology.com>
- */
-
-#include <linux/bitops.h>
-#include <linux/clkdev.h>
-#include <linux/clk/davinci.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-
-#include "pll.h"
-
-#define OCSEL_OCSRC_ENABLE 0
-
-static const struct davinci_pll_clk_info dm365_pll1_info = {
- .name = "pll1",
- .pllm_mask = GENMASK(9, 0),
- .pllm_min = 1,
- .pllm_max = 1023,
- .flags = PLL_HAS_CLKMODE | PLL_HAS_PREDIV | PLL_HAS_POSTDIV |
- PLL_POSTDIV_ALWAYS_ENABLED | PLL_PLLM_2X,
-};
-
-SYSCLK(1, pll1_sysclk1, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
-SYSCLK(2, pll1_sysclk2, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
-SYSCLK(3, pll1_sysclk3, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
-SYSCLK(4, pll1_sysclk4, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
-SYSCLK(5, pll1_sysclk5, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
-SYSCLK(6, pll1_sysclk6, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
-SYSCLK(7, pll1_sysclk7, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
-SYSCLK(8, pll1_sysclk8, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
-SYSCLK(9, pll1_sysclk9, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
-
-/*
- * This is a bit of a hack to make OCSEL[OCSRC] on DM365 look like OCSEL[OCSRC]
- * on DA850. On DM365, OCSEL[OCSRC] is just an enable/disable bit instead of a
- * multiplexer. By modeling it as a single parent mux clock, the clock code will
- * still do the right thing in this case.
- */
-static const char * const dm365_pll_obsclk_parent_names[] = {
- "oscin",
-};
-
-static u32 dm365_pll_obsclk_table[] = {
- OCSEL_OCSRC_ENABLE,
-};
-
-static const struct davinci_pll_obsclk_info dm365_pll1_obsclk_info = {
- .name = "pll1_obsclk",
- .parent_names = dm365_pll_obsclk_parent_names,
- .num_parents = ARRAY_SIZE(dm365_pll_obsclk_parent_names),
- .table = dm365_pll_obsclk_table,
- .ocsrc_mask = BIT(4),
-};
-
-int dm365_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
-{
- struct clk *clk;
-
- davinci_pll_clk_register(dev, &dm365_pll1_info, "ref_clk", base, cfgchip);
-
- clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
- clk_register_clkdev(clk, "pll1_sysclk1", "dm365-psc");
-
- clk = davinci_pll_sysclk_register(dev, &pll1_sysclk2, base);
- clk_register_clkdev(clk, "pll1_sysclk2", "dm365-psc");
-
- clk = davinci_pll_sysclk_register(dev, &pll1_sysclk3, base);
- clk_register_clkdev(clk, "pll1_sysclk3", "dm365-psc");
-
- clk = davinci_pll_sysclk_register(dev, &pll1_sysclk4, base);
- clk_register_clkdev(clk, "pll1_sysclk4", "dm365-psc");
-
- clk = davinci_pll_sysclk_register(dev, &pll1_sysclk5, base);
- clk_register_clkdev(clk, "pll1_sysclk5", "dm365-psc");
-
- davinci_pll_sysclk_register(dev, &pll1_sysclk6, base);
-
- davinci_pll_sysclk_register(dev, &pll1_sysclk7, base);
-
- clk = davinci_pll_sysclk_register(dev, &pll1_sysclk8, base);
- clk_register_clkdev(clk, "pll1_sysclk8", "dm365-psc");
-
- davinci_pll_sysclk_register(dev, &pll1_sysclk9, base);
-
- clk = davinci_pll_auxclk_register(dev, "pll1_auxclk", base);
- clk_register_clkdev(clk, "pll1_auxclk", "dm355-psc");
-
- davinci_pll_sysclkbp_clk_register(dev, "pll1_sysclkbp", base);
-
- davinci_pll_obsclk_register(dev, &dm365_pll1_obsclk_info, base);
-
- return 0;
-}
-
-static const struct davinci_pll_clk_info dm365_pll2_info = {
- .name = "pll2",
- .pllm_mask = GENMASK(9, 0),
- .pllm_min = 1,
- .pllm_max = 1023,
- .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV | PLL_POSTDIV_ALWAYS_ENABLED |
- PLL_PLLM_2X,
-};
-
-SYSCLK(1, pll2_sysclk1, pll2_pllen, 5, SYSCLK_ALWAYS_ENABLED);
-SYSCLK(2, pll2_sysclk2, pll2_pllen, 5, SYSCLK_ALWAYS_ENABLED);
-SYSCLK(3, pll2_sysclk3, pll2_pllen, 5, SYSCLK_ALWAYS_ENABLED);
-SYSCLK(4, pll2_sysclk4, pll2_pllen, 5, SYSCLK_ALWAYS_ENABLED);
-SYSCLK(5, pll2_sysclk5, pll2_pllen, 5, SYSCLK_ALWAYS_ENABLED);
-
-static const struct davinci_pll_obsclk_info dm365_pll2_obsclk_info = {
- .name = "pll2_obsclk",
- .parent_names = dm365_pll_obsclk_parent_names,
- .num_parents = ARRAY_SIZE(dm365_pll_obsclk_parent_names),
- .table = dm365_pll_obsclk_table,
- .ocsrc_mask = BIT(4),
-};
-
-int dm365_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
-{
- struct clk *clk;
-
- davinci_pll_clk_register(dev, &dm365_pll2_info, "oscin", base, cfgchip);
-
- davinci_pll_sysclk_register(dev, &pll2_sysclk1, base);
-
- clk = davinci_pll_sysclk_register(dev, &pll2_sysclk2, base);
- clk_register_clkdev(clk, "pll1_sysclk2", "dm365-psc");
-
- davinci_pll_sysclk_register(dev, &pll2_sysclk3, base);
-
- clk = davinci_pll_sysclk_register(dev, &pll2_sysclk4, base);
- clk_register_clkdev(clk, "pll1_sysclk4", "dm365-psc");
-
- davinci_pll_sysclk_register(dev, &pll2_sysclk5, base);
-
- davinci_pll_auxclk_register(dev, "pll2_auxclk", base);
-
- davinci_pll_obsclk_register(dev, &dm365_pll2_obsclk_info, base);
-
- return 0;
-}
diff --git a/drivers/clk/davinci/psc-dm355.c b/drivers/clk/davinci/psc-dm355.c
deleted file mode 100644
index ddd250107c4e..000000000000
--- a/drivers/clk/davinci/psc-dm355.c
+++ /dev/null
@@ -1,89 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * PSC clock descriptions for TI DaVinci DM355
- *
- * Copyright (C) 2018 David Lechner <david@lechnology.com>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/clk/davinci.h>
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-
-#include "psc.h"
-
-LPSC_CLKDEV1(vpss_master_clkdev, "master", "vpss");
-LPSC_CLKDEV1(vpss_slave_clkdev, "slave", "vpss");
-LPSC_CLKDEV1(spi1_clkdev, NULL, "spi_davinci.1");
-LPSC_CLKDEV1(mmcsd1_clkdev, NULL, "dm6441-mmc.1");
-LPSC_CLKDEV1(mcbsp1_clkdev, NULL, "davinci-mcbsp.1");
-LPSC_CLKDEV1(usb_clkdev, "usb", NULL);
-LPSC_CLKDEV1(spi2_clkdev, NULL, "spi_davinci.2");
-LPSC_CLKDEV1(aemif_clkdev, "aemif", NULL);
-LPSC_CLKDEV1(mmcsd0_clkdev, NULL, "dm6441-mmc.0");
-LPSC_CLKDEV1(mcbsp0_clkdev, NULL, "davinci-mcbsp.0");
-LPSC_CLKDEV1(i2c_clkdev, NULL, "i2c_davinci.1");
-LPSC_CLKDEV1(uart0_clkdev, NULL, "serial8250.0");
-LPSC_CLKDEV1(uart1_clkdev, NULL, "serial8250.1");
-LPSC_CLKDEV1(uart2_clkdev, NULL, "serial8250.2");
-LPSC_CLKDEV1(spi0_clkdev, NULL, "spi_davinci.0");
-/* REVISIT: gpio-davinci.c should be modified to drop con_id */
-LPSC_CLKDEV1(gpio_clkdev, "gpio", NULL);
-LPSC_CLKDEV1(timer0_clkdev, "timer0", NULL);
-LPSC_CLKDEV1(timer2_clkdev, NULL, "davinci-wdt");
-LPSC_CLKDEV1(vpss_dac_clkdev, "vpss_dac", NULL);
-
-static const struct davinci_lpsc_clk_info dm355_psc_info[] = {
- LPSC(0, 0, vpss_master, pll1_sysclk4, vpss_master_clkdev, 0),
- LPSC(1, 0, vpss_slave, pll1_sysclk4, vpss_slave_clkdev, 0),
- LPSC(5, 0, timer3, pll1_auxclk, NULL, 0),
- LPSC(6, 0, spi1, pll1_sysclk2, spi1_clkdev, 0),
- LPSC(7, 0, mmcsd1, pll1_sysclk2, mmcsd1_clkdev, 0),
- LPSC(8, 0, asp1, pll1_sysclk2, mcbsp1_clkdev, 0),
- LPSC(9, 0, usb, pll1_sysclk2, usb_clkdev, 0),
- LPSC(10, 0, pwm3, pll1_auxclk, NULL, 0),
- LPSC(11, 0, spi2, pll1_sysclk2, spi2_clkdev, 0),
- LPSC(12, 0, rto, pll1_auxclk, NULL, 0),
- LPSC(14, 0, aemif, pll1_sysclk2, aemif_clkdev, 0),
- LPSC(15, 0, mmcsd0, pll1_sysclk2, mmcsd0_clkdev, 0),
- LPSC(17, 0, asp0, pll1_sysclk2, mcbsp0_clkdev, 0),
- LPSC(18, 0, i2c, pll1_auxclk, i2c_clkdev, 0),
- LPSC(19, 0, uart0, pll1_auxclk, uart0_clkdev, 0),
- LPSC(20, 0, uart1, pll1_auxclk, uart1_clkdev, 0),
- LPSC(21, 0, uart2, pll1_sysclk2, uart2_clkdev, 0),
- LPSC(22, 0, spi0, pll1_sysclk2, spi0_clkdev, 0),
- LPSC(23, 0, pwm0, pll1_auxclk, NULL, 0),
- LPSC(24, 0, pwm1, pll1_auxclk, NULL, 0),
- LPSC(25, 0, pwm2, pll1_auxclk, NULL, 0),
- LPSC(26, 0, gpio, pll1_sysclk2, gpio_clkdev, 0),
- LPSC(27, 0, timer0, pll1_auxclk, timer0_clkdev, LPSC_ALWAYS_ENABLED),
- LPSC(28, 0, timer1, pll1_auxclk, NULL, 0),
- /* REVISIT: why can't this be disabled? */
- LPSC(29, 0, timer2, pll1_auxclk, timer2_clkdev, LPSC_ALWAYS_ENABLED),
- LPSC(31, 0, arm, pll1_sysclk1, NULL, LPSC_ALWAYS_ENABLED),
- LPSC(40, 0, mjcp, pll1_sysclk1, NULL, 0),
- LPSC(41, 0, vpss_dac, pll1_sysclk3, vpss_dac_clkdev, 0),
- { }
-};
-
-int dm355_psc_init(struct device *dev, void __iomem *base)
-{
- return davinci_psc_register_clocks(dev, dm355_psc_info, 42, base);
-}
-
-static struct clk_bulk_data dm355_psc_parent_clks[] = {
- { .id = "pll1_sysclk1" },
- { .id = "pll1_sysclk2" },
- { .id = "pll1_sysclk3" },
- { .id = "pll1_sysclk4" },
- { .id = "pll1_auxclk" },
-};
-
-const struct davinci_psc_init_data dm355_psc_init_data = {
- .parent_clks = dm355_psc_parent_clks,
- .num_parent_clks = ARRAY_SIZE(dm355_psc_parent_clks),
- .psc_init = &dm355_psc_init,
-};
diff --git a/drivers/clk/davinci/psc-dm365.c b/drivers/clk/davinci/psc-dm365.c
deleted file mode 100644
index c75424f4ea3b..000000000000
--- a/drivers/clk/davinci/psc-dm365.c
+++ /dev/null
@@ -1,111 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * PSC clock descriptions for TI DaVinci DM365
- *
- * Copyright (C) 2018 David Lechner <david@lechnology.com>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/clk/davinci.h>
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-
-#include "psc.h"
-
-LPSC_CLKDEV1(vpss_slave_clkdev, "slave", "vpss");
-LPSC_CLKDEV1(spi1_clkdev, NULL, "spi_davinci.1");
-LPSC_CLKDEV1(mmcsd1_clkdev, NULL, "da830-mmc.1");
-LPSC_CLKDEV1(asp0_clkdev, NULL, "davinci-mcbsp");
-LPSC_CLKDEV1(usb_clkdev, "usb", NULL);
-LPSC_CLKDEV1(spi2_clkdev, NULL, "spi_davinci.2");
-LPSC_CLKDEV2(aemif_clkdev, "aemif", NULL,
- NULL, "ti-aemif");
-LPSC_CLKDEV1(mmcsd0_clkdev, NULL, "da830-mmc.0");
-LPSC_CLKDEV1(i2c_clkdev, NULL, "i2c_davinci.1");
-LPSC_CLKDEV1(uart0_clkdev, NULL, "serial8250.0");
-LPSC_CLKDEV1(uart1_clkdev, NULL, "serial8250.1");
-LPSC_CLKDEV1(spi0_clkdev, NULL, "spi_davinci.0");
-/* REVISIT: gpio-davinci.c should be modified to drop con_id */
-LPSC_CLKDEV1(gpio_clkdev, "gpio", NULL);
-LPSC_CLKDEV1(timer0_clkdev, "timer0", NULL);
-LPSC_CLKDEV1(timer2_clkdev, NULL, "davinci-wdt");
-LPSC_CLKDEV1(spi3_clkdev, NULL, "spi_davinci.3");
-LPSC_CLKDEV1(spi4_clkdev, NULL, "spi_davinci.4");
-LPSC_CLKDEV2(emac_clkdev, NULL, "davinci_emac.1",
- "fck", "davinci_mdio.0");
-LPSC_CLKDEV1(voice_codec_clkdev, NULL, "davinci_voicecodec");
-LPSC_CLKDEV1(vpss_dac_clkdev, "vpss_dac", NULL);
-LPSC_CLKDEV1(vpss_master_clkdev, "master", "vpss");
-
-static const struct davinci_lpsc_clk_info dm365_psc_info[] = {
- LPSC(1, 0, vpss_slave, pll1_sysclk5, vpss_slave_clkdev, 0),
- LPSC(5, 0, timer3, pll1_auxclk, NULL, 0),
- LPSC(6, 0, spi1, pll1_sysclk4, spi1_clkdev, 0),
- LPSC(7, 0, mmcsd1, pll1_sysclk4, mmcsd1_clkdev, 0),
- LPSC(8, 0, asp0, pll1_sysclk4, asp0_clkdev, 0),
- LPSC(9, 0, usb, pll1_auxclk, usb_clkdev, 0),
- LPSC(10, 0, pwm3, pll1_auxclk, NULL, 0),
- LPSC(11, 0, spi2, pll1_sysclk4, spi2_clkdev, 0),
- LPSC(12, 0, rto, pll1_sysclk4, NULL, 0),
- LPSC(14, 0, aemif, pll1_sysclk4, aemif_clkdev, 0),
- LPSC(15, 0, mmcsd0, pll1_sysclk8, mmcsd0_clkdev, 0),
- LPSC(18, 0, i2c, pll1_auxclk, i2c_clkdev, 0),
- LPSC(19, 0, uart0, pll1_auxclk, uart0_clkdev, 0),
- LPSC(20, 0, uart1, pll1_sysclk4, uart1_clkdev, 0),
- LPSC(22, 0, spi0, pll1_sysclk4, spi0_clkdev, 0),
- LPSC(23, 0, pwm0, pll1_auxclk, NULL, 0),
- LPSC(24, 0, pwm1, pll1_auxclk, NULL, 0),
- LPSC(25, 0, pwm2, pll1_auxclk, NULL, 0),
- LPSC(26, 0, gpio, pll1_sysclk4, gpio_clkdev, 0),
- LPSC(27, 0, timer0, pll1_auxclk, timer0_clkdev, LPSC_ALWAYS_ENABLED),
- LPSC(28, 0, timer1, pll1_auxclk, NULL, 0),
- /* REVISIT: why can't this be disabled? */
- LPSC(29, 0, timer2, pll1_auxclk, timer2_clkdev, LPSC_ALWAYS_ENABLED),
- LPSC(31, 0, arm, pll2_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
- LPSC(38, 0, spi3, pll1_sysclk4, spi3_clkdev, 0),
- LPSC(39, 0, spi4, pll1_auxclk, spi4_clkdev, 0),
- LPSC(40, 0, emac, pll1_sysclk4, emac_clkdev, 0),
- /*
- * The TRM (ARM Subsystem User's Guide) shows two clocks input into
- * voice codec module (PLL2 SYSCLK4 with a DIV2 and PLL1 SYSCLK4). Its
- * not fully clear from documentation which clock should be considered
- * as parent for PSC. The clock chosen here is to maintain
- * compatibility with existing code in arch/arm/mach-davinci/dm365.c
- */
- LPSC(44, 0, voice_codec, pll2_sysclk4, voice_codec_clkdev, 0),
- /*
- * Its not fully clear from TRM (ARM Subsystem User's Guide) as to what
- * the parent of VPSS DAC LPSC should actually be. PLL1 SYSCLK3 feeds
- * into HDVICP and MJCP. The clock chosen here is to remain compatible
- * with code existing in arch/arm/mach-davinci/dm365.c
- */
- LPSC(46, 0, vpss_dac, pll1_sysclk3, vpss_dac_clkdev, 0),
- LPSC(47, 0, vpss_master, pll1_sysclk5, vpss_master_clkdev, 0),
- LPSC(50, 0, mjcp, pll1_sysclk3, NULL, 0),
- { }
-};
-
-int dm365_psc_init(struct device *dev, void __iomem *base)
-{
- return davinci_psc_register_clocks(dev, dm365_psc_info, 52, base);
-}
-
-static struct clk_bulk_data dm365_psc_parent_clks[] = {
- { .id = "pll1_sysclk1" },
- { .id = "pll1_sysclk3" },
- { .id = "pll1_sysclk4" },
- { .id = "pll1_sysclk5" },
- { .id = "pll1_sysclk8" },
- { .id = "pll2_sysclk2" },
- { .id = "pll2_sysclk4" },
- { .id = "pll1_auxclk" },
-};
-
-const struct davinci_psc_init_data dm365_psc_init_data = {
- .parent_clks = dm365_psc_parent_clks,
- .num_parent_clks = ARRAY_SIZE(dm365_psc_parent_clks),
- .psc_init = &dm365_psc_init,
-};
--
2.29.2
^ permalink raw reply related [flat|nested] 48+ messages in thread* Re: [PATCH 04/14] clk: remove davinci dm3xx drivers
2022-10-19 15:29 ` [PATCH 04/14] clk: remove davinci dm3xx drivers Arnd Bergmann
@ 2022-10-19 16:39 ` David Lechner
2022-10-20 7:53 ` Linus Walleij
` (2 subsequent siblings)
3 siblings, 0 replies; 48+ messages in thread
From: David Lechner @ 2022-10-19 16:39 UTC (permalink / raw)
To: Arnd Bergmann, Sekhar Nori, Bartosz Golaszewski,
linux-arm-kernel, Michael Turquette, Stephen Boyd
Cc: linux-kernel, Kevin Hilman, Arnd Bergmann, Lukas Bulwahn,
Linus Walleij, linux-clk
On 10/19/22 10:29 AM, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> The davinci dm3xx machines are all removed, so the clk driver
> is no longer needed. The da8xx platforms are now using DT
> exclusively, so those drivers remain untouched.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
Reviewed-by: David Lechner <david@lechnology.com>
^ permalink raw reply [flat|nested] 48+ messages in thread* Re: [PATCH 04/14] clk: remove davinci dm3xx drivers
2022-10-19 15:29 ` [PATCH 04/14] clk: remove davinci dm3xx drivers Arnd Bergmann
2022-10-19 16:39 ` David Lechner
@ 2022-10-20 7:53 ` Linus Walleij
2022-10-20 11:44 ` Bartosz Golaszewski
2022-10-27 1:10 ` Stephen Boyd
3 siblings, 0 replies; 48+ messages in thread
From: Linus Walleij @ 2022-10-20 7:53 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Sekhar Nori, Bartosz Golaszewski, linux-arm-kernel,
David Lechner, Michael Turquette, Stephen Boyd, linux-kernel,
Kevin Hilman, Arnd Bergmann, Lukas Bulwahn, linux-clk
On Wed, Oct 19, 2022 at 5:33 PM Arnd Bergmann <arnd@kernel.org> wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> The davinci dm3xx machines are all removed, so the clk driver
> is no longer needed. The da8xx platforms are now using DT
> exclusively, so those drivers remain untouched.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 04/14] clk: remove davinci dm3xx drivers
2022-10-19 15:29 ` [PATCH 04/14] clk: remove davinci dm3xx drivers Arnd Bergmann
2022-10-19 16:39 ` David Lechner
2022-10-20 7:53 ` Linus Walleij
@ 2022-10-20 11:44 ` Bartosz Golaszewski
2022-10-27 1:10 ` Stephen Boyd
3 siblings, 0 replies; 48+ messages in thread
From: Bartosz Golaszewski @ 2022-10-20 11:44 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Sekhar Nori, linux-arm-kernel, David Lechner, Michael Turquette,
Stephen Boyd, linux-kernel, Kevin Hilman, Arnd Bergmann,
Lukas Bulwahn, Linus Walleij, linux-clk
On Wed, Oct 19, 2022 at 5:33 PM Arnd Bergmann <arnd@kernel.org> wrote:
>
> From: Arnd Bergmann <arnd@arndb.de>
>
> The davinci dm3xx machines are all removed, so the clk driver
> is no longer needed. The da8xx platforms are now using DT
> exclusively, so those drivers remain untouched.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 04/14] clk: remove davinci dm3xx drivers
2022-10-19 15:29 ` [PATCH 04/14] clk: remove davinci dm3xx drivers Arnd Bergmann
` (2 preceding siblings ...)
2022-10-20 11:44 ` Bartosz Golaszewski
@ 2022-10-27 1:10 ` Stephen Boyd
3 siblings, 0 replies; 48+ messages in thread
From: Stephen Boyd @ 2022-10-27 1:10 UTC (permalink / raw)
To: Arnd Bergmann, Bartosz Golaszewski, David Lechner,
Michael Turquette, Sekhar Nori, linux-arm-kernel
Cc: linux-kernel, Kevin Hilman, Arnd Bergmann, Lukas Bulwahn,
Linus Walleij, linux-clk
Quoting Arnd Bergmann (2022-10-19 08:29:30)
> From: Arnd Bergmann <arnd@arndb.de>
>
> The davinci dm3xx machines are all removed, so the clk driver
> is no longer needed. The da8xx platforms are now using DT
> exclusively, so those drivers remain untouched.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
Acked-by: Stephen Boyd <sboyd@kernel.org>
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH 05/14] usb: musb: remove unused davinci support
2022-10-19 15:29 [PATCH 00/14] ARM: remove unused davinci board & drivers Arnd Bergmann
` (3 preceding siblings ...)
2022-10-19 15:29 ` [PATCH 04/14] clk: remove davinci dm3xx drivers Arnd Bergmann
@ 2022-10-19 15:29 ` Arnd Bergmann
2022-10-20 11:34 ` Bartosz Golaszewski
2022-10-19 15:29 ` [PATCH 06/14] mfd: remove dm355evm_msp driver Arnd Bergmann
` (11 subsequent siblings)
16 siblings, 1 reply; 48+ messages in thread
From: Arnd Bergmann @ 2022-10-19 15:29 UTC (permalink / raw)
To: Sekhar Nori, Bartosz Golaszewski, linux-arm-kernel, Bin Liu,
Greg Kroah-Hartman
Cc: linux-kernel, Kevin Hilman, Arnd Bergmann, linux-usb
From: Arnd Bergmann <arnd@arndb.de>
The musb-davinci driver was only used on dm644x, which got removed
in linux-6.0. The only remaining davinci machines are da8xx
devicetree based and do not use this hardware.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
drivers/usb/musb/Kconfig | 12 -
drivers/usb/musb/Makefile | 2 -
drivers/usb/musb/cppi_dma.c | 1547 -----------------------------------
drivers/usb/musb/davinci.c | 606 --------------
drivers/usb/musb/davinci.h | 103 ---
5 files changed, 2270 deletions(-)
delete mode 100644 drivers/usb/musb/cppi_dma.c
delete mode 100644 drivers/usb/musb/davinci.c
delete mode 100644 drivers/usb/musb/davinci.h
diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig
index 6c8f7763e75e..f9eec666103c 100644
--- a/drivers/usb/musb/Kconfig
+++ b/drivers/usb/musb/Kconfig
@@ -70,12 +70,6 @@ config USB_MUSB_SUNXI
select GENERIC_PHY
select SUNXI_SRAM
-config USB_MUSB_DAVINCI
- tristate "DaVinci"
- depends on ARCH_DAVINCI_DMx
- depends on NOP_USB_XCEIV
- depends on BROKEN
-
config USB_MUSB_DA8XX
tristate "DA8xx/OMAP-L1x"
depends on ARCH_DAVINCI_DA8XX
@@ -161,12 +155,6 @@ config USB_INVENTRA_DMA
help
Enable DMA transfers using Mentor's engine.
-config USB_TI_CPPI_DMA
- bool 'TI CPPI (Davinci)'
- depends on USB_MUSB_DAVINCI
- help
- Enable DMA transfers when TI CPPI DMA is available.
-
config USB_TI_CPPI41_DMA
bool 'TI CPPI 4.1'
depends on (ARCH_OMAP || ARCH_DAVINCI_DA8XX) && DMADEVICES
diff --git a/drivers/usb/musb/Makefile b/drivers/usb/musb/Makefile
index 51dd54a8de49..44a9e27b2157 100644
--- a/drivers/usb/musb/Makefile
+++ b/drivers/usb/musb/Makefile
@@ -19,7 +19,6 @@ obj-$(CONFIG_USB_MUSB_OMAP2PLUS) += omap2430.o
obj-$(CONFIG_USB_MUSB_AM35X) += am35x.o
obj-$(CONFIG_USB_MUSB_DSPS) += musb_dsps.o
obj-$(CONFIG_USB_MUSB_TUSB6010) += tusb6010.o
-obj-$(CONFIG_USB_MUSB_DAVINCI) += davinci.o
obj-$(CONFIG_USB_MUSB_DA8XX) += da8xx.o
obj-$(CONFIG_USB_MUSB_UX500) += ux500.o
obj-$(CONFIG_USB_MUSB_JZ4740) += jz4740.o
@@ -33,7 +32,6 @@ obj-$(CONFIG_USB_MUSB_POLARFIRE_SOC) += mpfs.o
# though PIO is always there to back up DMA, and for ep0
musb_hdrc-$(CONFIG_USB_INVENTRA_DMA) += musbhsdma.o
-musb_hdrc-$(CONFIG_USB_TI_CPPI_DMA) += cppi_dma.o
musb_hdrc-$(CONFIG_USB_TUSB_OMAP_DMA) += tusb6010_omap.o
musb_hdrc-$(CONFIG_USB_UX500_DMA) += ux500_dma.o
musb_hdrc-$(CONFIG_USB_TI_CPPI41_DMA) += musb_cppi41.o
diff --git a/drivers/usb/musb/cppi_dma.c b/drivers/usb/musb/cppi_dma.c
deleted file mode 100644
index edb5b63d7063..000000000000
--- a/drivers/usb/musb/cppi_dma.c
+++ /dev/null
@@ -1,1547 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2005-2006 by Texas Instruments
- *
- * This file implements a DMA interface using TI's CPPI DMA.
- * For now it's DaVinci-only, but CPPI isn't specific to DaVinci or USB.
- * The TUSB6020, using VLYNQ, has CPPI that looks much like DaVinci.
- */
-
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-#include <linux/usb.h>
-
-#include "musb_core.h"
-#include "musb_debug.h"
-#include "cppi_dma.h"
-#include "davinci.h"
-
-
-/* CPPI DMA status 7-mar-2006:
- *
- * - See musb_{host,gadget}.c for more info
- *
- * - Correct RX DMA generally forces the engine into irq-per-packet mode,
- * which can easily saturate the CPU under non-mass-storage loads.
- *
- * NOTES 24-aug-2006 (2.6.18-rc4):
- *
- * - peripheral RXDMA wedged in a test with packets of length 512/512/1.
- * evidently after the 1 byte packet was received and acked, the queue
- * of BDs got garbaged so it wouldn't empty the fifo. (rxcsr 0x2003,
- * and RX DMA0: 4 left, 80000000 8feff880, 8feff860 8feff860; 8f321401
- * 004001ff 00000001 .. 8feff860) Host was just getting NAKed on tx
- * of its next (512 byte) packet. IRQ issues?
- *
- * REVISIT: the "transfer DMA" glue between CPPI and USB fifos will
- * evidently also directly update the RX and TX CSRs ... so audit all
- * host and peripheral side DMA code to avoid CSR access after DMA has
- * been started.
- */
-
-/* REVISIT now we can avoid preallocating these descriptors; or
- * more simply, switch to a global freelist not per-channel ones.
- * Note: at full speed, 64 descriptors == 4K bulk data.
- */
-#define NUM_TXCHAN_BD 64
-#define NUM_RXCHAN_BD 64
-
-static inline void cpu_drain_writebuffer(void)
-{
- wmb();
-#ifdef CONFIG_CPU_ARM926T
- /* REVISIT this "should not be needed",
- * but lack of it sure seemed to hurt ...
- */
- asm("mcr p15, 0, r0, c7, c10, 4 @ drain write buffer\n");
-#endif
-}
-
-static inline struct cppi_descriptor *cppi_bd_alloc(struct cppi_channel *c)
-{
- struct cppi_descriptor *bd = c->freelist;
-
- if (bd)
- c->freelist = bd->next;
- return bd;
-}
-
-static inline void
-cppi_bd_free(struct cppi_channel *c, struct cppi_descriptor *bd)
-{
- if (!bd)
- return;
- bd->next = c->freelist;
- c->freelist = bd;
-}
-
-/*
- * Start DMA controller
- *
- * Initialize the DMA controller as necessary.
- */
-
-/* zero out entire rx state RAM entry for the channel */
-static void cppi_reset_rx(struct cppi_rx_stateram __iomem *rx)
-{
- musb_writel(&rx->rx_skipbytes, 0, 0);
- musb_writel(&rx->rx_head, 0, 0);
- musb_writel(&rx->rx_sop, 0, 0);
- musb_writel(&rx->rx_current, 0, 0);
- musb_writel(&rx->rx_buf_current, 0, 0);
- musb_writel(&rx->rx_len_len, 0, 0);
- musb_writel(&rx->rx_cnt_cnt, 0, 0);
-}
-
-/* zero out entire tx state RAM entry for the channel */
-static void cppi_reset_tx(struct cppi_tx_stateram __iomem *tx, u32 ptr)
-{
- musb_writel(&tx->tx_head, 0, 0);
- musb_writel(&tx->tx_buf, 0, 0);
- musb_writel(&tx->tx_current, 0, 0);
- musb_writel(&tx->tx_buf_current, 0, 0);
- musb_writel(&tx->tx_info, 0, 0);
- musb_writel(&tx->tx_rem_len, 0, 0);
- /* musb_writel(&tx->tx_dummy, 0, 0); */
- musb_writel(&tx->tx_complete, 0, ptr);
-}
-
-static void cppi_pool_init(struct cppi *cppi, struct cppi_channel *c)
-{
- int j;
-
- /* initialize channel fields */
- c->head = NULL;
- c->tail = NULL;
- c->last_processed = NULL;
- c->channel.status = MUSB_DMA_STATUS_UNKNOWN;
- c->controller = cppi;
- c->is_rndis = 0;
- c->freelist = NULL;
-
- /* build the BD Free list for the channel */
- for (j = 0; j < NUM_TXCHAN_BD + 1; j++) {
- struct cppi_descriptor *bd;
- dma_addr_t dma;
-
- bd = dma_pool_alloc(cppi->pool, GFP_KERNEL, &dma);
- bd->dma = dma;
- cppi_bd_free(c, bd);
- }
-}
-
-static int cppi_channel_abort(struct dma_channel *);
-
-static void cppi_pool_free(struct cppi_channel *c)
-{
- struct cppi *cppi = c->controller;
- struct cppi_descriptor *bd;
-
- (void) cppi_channel_abort(&c->channel);
- c->channel.status = MUSB_DMA_STATUS_UNKNOWN;
- c->controller = NULL;
-
- /* free all its bds */
- bd = c->last_processed;
- do {
- if (bd)
- dma_pool_free(cppi->pool, bd, bd->dma);
- bd = cppi_bd_alloc(c);
- } while (bd);
- c->last_processed = NULL;
-}
-
-static void cppi_controller_start(struct cppi *controller)
-{
- void __iomem *tibase;
- int i;
-
- /* do whatever is necessary to start controller */
- for (i = 0; i < ARRAY_SIZE(controller->tx); i++) {
- controller->tx[i].transmit = true;
- controller->tx[i].index = i;
- }
- for (i = 0; i < ARRAY_SIZE(controller->rx); i++) {
- controller->rx[i].transmit = false;
- controller->rx[i].index = i;
- }
-
- /* setup BD list on a per channel basis */
- for (i = 0; i < ARRAY_SIZE(controller->tx); i++)
- cppi_pool_init(controller, controller->tx + i);
- for (i = 0; i < ARRAY_SIZE(controller->rx); i++)
- cppi_pool_init(controller, controller->rx + i);
-
- tibase = controller->tibase;
- INIT_LIST_HEAD(&controller->tx_complete);
-
- /* initialise tx/rx channel head pointers to zero */
- for (i = 0; i < ARRAY_SIZE(controller->tx); i++) {
- struct cppi_channel *tx_ch = controller->tx + i;
- struct cppi_tx_stateram __iomem *tx;
-
- INIT_LIST_HEAD(&tx_ch->tx_complete);
-
- tx = tibase + DAVINCI_TXCPPI_STATERAM_OFFSET(i);
- tx_ch->state_ram = tx;
- cppi_reset_tx(tx, 0);
- }
- for (i = 0; i < ARRAY_SIZE(controller->rx); i++) {
- struct cppi_channel *rx_ch = controller->rx + i;
- struct cppi_rx_stateram __iomem *rx;
-
- INIT_LIST_HEAD(&rx_ch->tx_complete);
-
- rx = tibase + DAVINCI_RXCPPI_STATERAM_OFFSET(i);
- rx_ch->state_ram = rx;
- cppi_reset_rx(rx);
- }
-
- /* enable individual cppi channels */
- musb_writel(tibase, DAVINCI_TXCPPI_INTENAB_REG,
- DAVINCI_DMA_ALL_CHANNELS_ENABLE);
- musb_writel(tibase, DAVINCI_RXCPPI_INTENAB_REG,
- DAVINCI_DMA_ALL_CHANNELS_ENABLE);
-
- /* enable tx/rx CPPI control */
- musb_writel(tibase, DAVINCI_TXCPPI_CTRL_REG, DAVINCI_DMA_CTRL_ENABLE);
- musb_writel(tibase, DAVINCI_RXCPPI_CTRL_REG, DAVINCI_DMA_CTRL_ENABLE);
-
- /* disable RNDIS mode, also host rx RNDIS autorequest */
- musb_writel(tibase, DAVINCI_RNDIS_REG, 0);
- musb_writel(tibase, DAVINCI_AUTOREQ_REG, 0);
-}
-
-/*
- * Stop DMA controller
- *
- * De-Init the DMA controller as necessary.
- */
-
-static void cppi_controller_stop(struct cppi *controller)
-{
- void __iomem *tibase;
- int i;
- struct musb *musb;
-
- musb = controller->controller.musb;
-
- tibase = controller->tibase;
- /* DISABLE INDIVIDUAL CHANNEL Interrupts */
- musb_writel(tibase, DAVINCI_TXCPPI_INTCLR_REG,
- DAVINCI_DMA_ALL_CHANNELS_ENABLE);
- musb_writel(tibase, DAVINCI_RXCPPI_INTCLR_REG,
- DAVINCI_DMA_ALL_CHANNELS_ENABLE);
-
- musb_dbg(musb, "Tearing down RX and TX Channels");
- for (i = 0; i < ARRAY_SIZE(controller->tx); i++) {
- /* FIXME restructure of txdma to use bds like rxdma */
- controller->tx[i].last_processed = NULL;
- cppi_pool_free(controller->tx + i);
- }
- for (i = 0; i < ARRAY_SIZE(controller->rx); i++)
- cppi_pool_free(controller->rx + i);
-
- /* in Tx Case proper teardown is supported. We resort to disabling
- * Tx/Rx CPPI after cleanup of Tx channels. Before TX teardown is
- * complete TX CPPI cannot be disabled.
- */
- /*disable tx/rx cppi */
- musb_writel(tibase, DAVINCI_TXCPPI_CTRL_REG, DAVINCI_DMA_CTRL_DISABLE);
- musb_writel(tibase, DAVINCI_RXCPPI_CTRL_REG, DAVINCI_DMA_CTRL_DISABLE);
-}
-
-/* While dma channel is allocated, we only want the core irqs active
- * for fault reports, otherwise we'd get irqs that we don't care about.
- * Except for TX irqs, where dma done != fifo empty and reusable ...
- *
- * NOTE: docs don't say either way, but irq masking **enables** irqs.
- *
- * REVISIT same issue applies to pure PIO usage too, and non-cppi dma...
- */
-static inline void core_rxirq_disable(void __iomem *tibase, unsigned epnum)
-{
- musb_writel(tibase, DAVINCI_USB_INT_MASK_CLR_REG, 1 << (epnum + 8));
-}
-
-static inline void core_rxirq_enable(void __iomem *tibase, unsigned epnum)
-{
- musb_writel(tibase, DAVINCI_USB_INT_MASK_SET_REG, 1 << (epnum + 8));
-}
-
-
-/*
- * Allocate a CPPI Channel for DMA. With CPPI, channels are bound to
- * each transfer direction of a non-control endpoint, so allocating
- * (and deallocating) is mostly a way to notice bad housekeeping on
- * the software side. We assume the irqs are always active.
- */
-static struct dma_channel *
-cppi_channel_allocate(struct dma_controller *c,
- struct musb_hw_ep *ep, u8 transmit)
-{
- struct cppi *controller;
- u8 index;
- struct cppi_channel *cppi_ch;
- void __iomem *tibase;
- struct musb *musb;
-
- controller = container_of(c, struct cppi, controller);
- tibase = controller->tibase;
- musb = c->musb;
-
- /* ep0 doesn't use DMA; remember cppi indices are 0..N-1 */
- index = ep->epnum - 1;
-
- /* return the corresponding CPPI Channel Handle, and
- * probably disable the non-CPPI irq until we need it.
- */
- if (transmit) {
- if (index >= ARRAY_SIZE(controller->tx)) {
- musb_dbg(musb, "no %cX%d CPPI channel", 'T', index);
- return NULL;
- }
- cppi_ch = controller->tx + index;
- } else {
- if (index >= ARRAY_SIZE(controller->rx)) {
- musb_dbg(musb, "no %cX%d CPPI channel", 'R', index);
- return NULL;
- }
- cppi_ch = controller->rx + index;
- core_rxirq_disable(tibase, ep->epnum);
- }
-
- /* REVISIT make this an error later once the same driver code works
- * with the other DMA engine too
- */
- if (cppi_ch->hw_ep)
- musb_dbg(musb, "re-allocating DMA%d %cX channel %p",
- index, transmit ? 'T' : 'R', cppi_ch);
- cppi_ch->hw_ep = ep;
- cppi_ch->channel.status = MUSB_DMA_STATUS_FREE;
- cppi_ch->channel.max_len = 0x7fffffff;
-
- musb_dbg(musb, "Allocate CPPI%d %cX", index, transmit ? 'T' : 'R');
- return &cppi_ch->channel;
-}
-
-/* Release a CPPI Channel. */
-static void cppi_channel_release(struct dma_channel *channel)
-{
- struct cppi_channel *c;
- void __iomem *tibase;
-
- /* REVISIT: for paranoia, check state and abort if needed... */
-
- c = container_of(channel, struct cppi_channel, channel);
- tibase = c->controller->tibase;
- if (!c->hw_ep)
- musb_dbg(c->controller->controller.musb,
- "releasing idle DMA channel %p", c);
- else if (!c->transmit)
- core_rxirq_enable(tibase, c->index + 1);
-
- /* for now, leave its cppi IRQ enabled (we won't trigger it) */
- c->hw_ep = NULL;
- channel->status = MUSB_DMA_STATUS_UNKNOWN;
-}
-
-/* Context: controller irqlocked */
-static void
-cppi_dump_rx(int level, struct cppi_channel *c, const char *tag)
-{
- void __iomem *base = c->controller->mregs;
- struct cppi_rx_stateram __iomem *rx = c->state_ram;
-
- musb_ep_select(base, c->index + 1);
-
- musb_dbg(c->controller->controller.musb,
- "RX DMA%d%s: %d left, csr %04x, "
- "%08x H%08x S%08x C%08x, "
- "B%08x L%08x %08x .. %08x",
- c->index, tag,
- musb_readl(c->controller->tibase,
- DAVINCI_RXCPPI_BUFCNT0_REG + 4 * c->index),
- musb_readw(c->hw_ep->regs, MUSB_RXCSR),
-
- musb_readl(&rx->rx_skipbytes, 0),
- musb_readl(&rx->rx_head, 0),
- musb_readl(&rx->rx_sop, 0),
- musb_readl(&rx->rx_current, 0),
-
- musb_readl(&rx->rx_buf_current, 0),
- musb_readl(&rx->rx_len_len, 0),
- musb_readl(&rx->rx_cnt_cnt, 0),
- musb_readl(&rx->rx_complete, 0)
- );
-}
-
-/* Context: controller irqlocked */
-static void
-cppi_dump_tx(int level, struct cppi_channel *c, const char *tag)
-{
- void __iomem *base = c->controller->mregs;
- struct cppi_tx_stateram __iomem *tx = c->state_ram;
-
- musb_ep_select(base, c->index + 1);
-
- musb_dbg(c->controller->controller.musb,
- "TX DMA%d%s: csr %04x, "
- "H%08x S%08x C%08x %08x, "
- "F%08x L%08x .. %08x",
- c->index, tag,
- musb_readw(c->hw_ep->regs, MUSB_TXCSR),
-
- musb_readl(&tx->tx_head, 0),
- musb_readl(&tx->tx_buf, 0),
- musb_readl(&tx->tx_current, 0),
- musb_readl(&tx->tx_buf_current, 0),
-
- musb_readl(&tx->tx_info, 0),
- musb_readl(&tx->tx_rem_len, 0),
- /* dummy/unused word 6 */
- musb_readl(&tx->tx_complete, 0)
- );
-}
-
-/* Context: controller irqlocked */
-static inline void
-cppi_rndis_update(struct cppi_channel *c, int is_rx,
- void __iomem *tibase, int is_rndis)
-{
- /* we may need to change the rndis flag for this cppi channel */
- if (c->is_rndis != is_rndis) {
- u32 value = musb_readl(tibase, DAVINCI_RNDIS_REG);
- u32 temp = 1 << (c->index);
-
- if (is_rx)
- temp <<= 16;
- if (is_rndis)
- value |= temp;
- else
- value &= ~temp;
- musb_writel(tibase, DAVINCI_RNDIS_REG, value);
- c->is_rndis = is_rndis;
- }
-}
-
-static void cppi_dump_rxbd(const char *tag, struct cppi_descriptor *bd)
-{
- pr_debug("RXBD/%s %08x: "
- "nxt %08x buf %08x off.blen %08x opt.plen %08x\n",
- tag, bd->dma,
- bd->hw_next, bd->hw_bufp, bd->hw_off_len,
- bd->hw_options);
-}
-
-static void cppi_dump_rxq(int level, const char *tag, struct cppi_channel *rx)
-{
- struct cppi_descriptor *bd;
-
- cppi_dump_rx(level, rx, tag);
- if (rx->last_processed)
- cppi_dump_rxbd("last", rx->last_processed);
- for (bd = rx->head; bd; bd = bd->next)
- cppi_dump_rxbd("active", bd);
-}
-
-
-/* NOTE: DaVinci autoreq is ignored except for host side "RNDIS" mode RX;
- * so we won't ever use it (see "CPPI RX Woes" below).
- */
-static inline int cppi_autoreq_update(struct cppi_channel *rx,
- void __iomem *tibase, int onepacket, unsigned n_bds)
-{
- u32 val;
-
-#ifdef RNDIS_RX_IS_USABLE
- u32 tmp;
- /* assert(is_host_active(musb)) */
-
- /* start from "AutoReq never" */
- tmp = musb_readl(tibase, DAVINCI_AUTOREQ_REG);
- val = tmp & ~((0x3) << (rx->index * 2));
-
- /* HCD arranged reqpkt for packet #1. we arrange int
- * for all but the last one, maybe in two segments.
- */
- if (!onepacket) {
-#if 0
- /* use two segments, autoreq "all" then the last "never" */
- val |= ((0x3) << (rx->index * 2));
- n_bds--;
-#else
- /* one segment, autoreq "all-but-last" */
- val |= ((0x1) << (rx->index * 2));
-#endif
- }
-
- if (val != tmp) {
- int n = 100;
-
- /* make sure that autoreq is updated before continuing */
- musb_writel(tibase, DAVINCI_AUTOREQ_REG, val);
- do {
- tmp = musb_readl(tibase, DAVINCI_AUTOREQ_REG);
- if (tmp == val)
- break;
- cpu_relax();
- } while (n-- > 0);
- }
-#endif
-
- /* REQPKT is turned off after each segment */
- if (n_bds && rx->channel.actual_len) {
- void __iomem *regs = rx->hw_ep->regs;
-
- val = musb_readw(regs, MUSB_RXCSR);
- if (!(val & MUSB_RXCSR_H_REQPKT)) {
- val |= MUSB_RXCSR_H_REQPKT | MUSB_RXCSR_H_WZC_BITS;
- musb_writew(regs, MUSB_RXCSR, val);
- /* flush writebuffer */
- val = musb_readw(regs, MUSB_RXCSR);
- }
- }
- return n_bds;
-}
-
-
-/* Buffer enqueuing Logic:
- *
- * - RX builds new queues each time, to help handle routine "early
- * termination" cases (faults, including errors and short reads)
- * more correctly.
- *
- * - for now, TX reuses the same queue of BDs every time
- *
- * REVISIT long term, we want a normal dynamic model.
- * ... the goal will be to append to the
- * existing queue, processing completed "dma buffers" (segments) on the fly.
- *
- * Otherwise we force an IRQ latency between requests, which slows us a lot
- * (especially in "transparent" dma). Unfortunately that model seems to be
- * inherent in the DMA model from the Mentor code, except in the rare case
- * of transfers big enough (~128+ KB) that we could append "middle" segments
- * in the TX paths. (RX can't do this, see below.)
- *
- * That's true even in the CPPI- friendly iso case, where most urbs have
- * several small segments provided in a group and where the "packet at a time"
- * "transparent" DMA model is always correct, even on the RX side.
- */
-
-/*
- * CPPI TX:
- * ========
- * TX is a lot more reasonable than RX; it doesn't need to run in
- * irq-per-packet mode very often. RNDIS mode seems to behave too
- * (except how it handles the exactly-N-packets case). Building a
- * txdma queue with multiple requests (urb or usb_request) looks
- * like it would work ... but fault handling would need much testing.
- *
- * The main issue with TX mode RNDIS relates to transfer lengths that
- * are an exact multiple of the packet length. It appears that there's
- * a hiccup in that case (maybe the DMA completes before the ZLP gets
- * written?) boiling down to not being able to rely on CPPI writing any
- * terminating zero length packet before the next transfer is written.
- * So that's punted to PIO; better yet, gadget drivers can avoid it.
- *
- * Plus, there's allegedly an undocumented constraint that rndis transfer
- * length be a multiple of 64 bytes ... but the chip doesn't act that
- * way, and we really don't _want_ that behavior anyway.
- *
- * On TX, "transparent" mode works ... although experiments have shown
- * problems trying to use the SOP/EOP bits in different USB packets.
- *
- * REVISIT try to handle terminating zero length packets using CPPI
- * instead of doing it by PIO after an IRQ. (Meanwhile, make Ethernet
- * links avoid that issue by forcing them to avoid zlps.)
- */
-static void
-cppi_next_tx_segment(struct musb *musb, struct cppi_channel *tx)
-{
- unsigned maxpacket = tx->maxpacket;
- dma_addr_t addr = tx->buf_dma + tx->offset;
- size_t length = tx->buf_len - tx->offset;
- struct cppi_descriptor *bd;
- unsigned n_bds;
- unsigned i;
- struct cppi_tx_stateram __iomem *tx_ram = tx->state_ram;
- int rndis;
-
- /* TX can use the CPPI "rndis" mode, where we can probably fit this
- * transfer in one BD and one IRQ. The only time we would NOT want
- * to use it is when hardware constraints prevent it, or if we'd
- * trigger the "send a ZLP?" confusion.
- */
- rndis = (maxpacket & 0x3f) == 0
- && length > maxpacket
- && length < 0xffff
- && (length % maxpacket) != 0;
-
- if (rndis) {
- maxpacket = length;
- n_bds = 1;
- } else {
- if (length)
- n_bds = DIV_ROUND_UP(length, maxpacket);
- else
- n_bds = 1;
- n_bds = min(n_bds, (unsigned) NUM_TXCHAN_BD);
- length = min(n_bds * maxpacket, length);
- }
-
- musb_dbg(musb, "TX DMA%d, pktSz %d %s bds %d dma 0x%llx len %u",
- tx->index,
- maxpacket,
- rndis ? "rndis" : "transparent",
- n_bds,
- (unsigned long long)addr, length);
-
- cppi_rndis_update(tx, 0, musb->ctrl_base, rndis);
-
- /* assuming here that channel_program is called during
- * transfer initiation ... current code maintains state
- * for one outstanding request only (no queues, not even
- * the implicit ones of an iso urb).
- */
-
- bd = tx->freelist;
- tx->head = bd;
- tx->last_processed = NULL;
-
- /* FIXME use BD pool like RX side does, and just queue
- * the minimum number for this request.
- */
-
- /* Prepare queue of BDs first, then hand it to hardware.
- * All BDs except maybe the last should be of full packet
- * size; for RNDIS there _is_ only that last packet.
- */
- for (i = 0; i < n_bds; ) {
- if (++i < n_bds && bd->next)
- bd->hw_next = bd->next->dma;
- else
- bd->hw_next = 0;
-
- bd->hw_bufp = tx->buf_dma + tx->offset;
-
- /* FIXME set EOP only on the last packet,
- * SOP only on the first ... avoid IRQs
- */
- if ((tx->offset + maxpacket) <= tx->buf_len) {
- tx->offset += maxpacket;
- bd->hw_off_len = maxpacket;
- bd->hw_options = CPPI_SOP_SET | CPPI_EOP_SET
- | CPPI_OWN_SET | maxpacket;
- } else {
- /* only this one may be a partial USB Packet */
- u32 partial_len;
-
- partial_len = tx->buf_len - tx->offset;
- tx->offset = tx->buf_len;
- bd->hw_off_len = partial_len;
-
- bd->hw_options = CPPI_SOP_SET | CPPI_EOP_SET
- | CPPI_OWN_SET | partial_len;
- if (partial_len == 0)
- bd->hw_options |= CPPI_ZERO_SET;
- }
-
- musb_dbg(musb, "TXBD %p: nxt %08x buf %08x len %04x opt %08x",
- bd, bd->hw_next, bd->hw_bufp,
- bd->hw_off_len, bd->hw_options);
-
- /* update the last BD enqueued to the list */
- tx->tail = bd;
- bd = bd->next;
- }
-
- /* BDs live in DMA-coherent memory, but writes might be pending */
- cpu_drain_writebuffer();
-
- /* Write to the HeadPtr in state RAM to trigger */
- musb_writel(&tx_ram->tx_head, 0, (u32)tx->freelist->dma);
-
- cppi_dump_tx(5, tx, "/S");
-}
-
-/*
- * CPPI RX Woes:
- * =============
- * Consider a 1KB bulk RX buffer in two scenarios: (a) it's fed two 300 byte
- * packets back-to-back, and (b) it's fed two 512 byte packets back-to-back.
- * (Full speed transfers have similar scenarios.)
- *
- * The correct behavior for Linux is that (a) fills the buffer with 300 bytes,
- * and the next packet goes into a buffer that's queued later; while (b) fills
- * the buffer with 1024 bytes. How to do that with CPPI?
- *
- * - RX queues in "rndis" mode -- one single BD -- handle (a) correctly, but
- * (b) loses **BADLY** because nothing (!) happens when that second packet
- * fills the buffer, much less when a third one arrives. (Which makes this
- * not a "true" RNDIS mode. In the RNDIS protocol short-packet termination
- * is optional, and it's fine if peripherals -- not hosts! -- pad messages
- * out to end-of-buffer. Standard PCI host controller DMA descriptors
- * implement that mode by default ... which is no accident.)
- *
- * - RX queues in "transparent" mode -- two BDs with 512 bytes each -- have
- * converse problems: (b) is handled right, but (a) loses badly. CPPI RX
- * ignores SOP/EOP markings and processes both of those BDs; so both packets
- * are loaded into the buffer (with a 212 byte gap between them), and the next
- * buffer queued will NOT get its 300 bytes of data. (It seems like SOP/EOP
- * are intended as outputs for RX queues, not inputs...)
- *
- * - A variant of "transparent" mode -- one BD at a time -- is the only way to
- * reliably make both cases work, with software handling both cases correctly
- * and at the significant penalty of needing an IRQ per packet. (The lack of
- * I/O overlap can be slightly ameliorated by enabling double buffering.)
- *
- * So how to get rid of IRQ-per-packet? The transparent multi-BD case could
- * be used in special cases like mass storage, which sets URB_SHORT_NOT_OK
- * (or maybe its peripheral side counterpart) to flag (a) scenarios as errors
- * with guaranteed driver level fault recovery and scrubbing out what's left
- * of that garbaged datastream.
- *
- * But there seems to be no way to identify the cases where CPPI RNDIS mode
- * is appropriate -- which do NOT include RNDIS host drivers, but do include
- * the CDC Ethernet driver! -- and the documentation is incomplete/wrong.
- * So we can't _ever_ use RX RNDIS mode ... except by using a heuristic
- * that applies best on the peripheral side (and which could fail rudely).
- *
- * Leaving only "transparent" mode; we avoid multi-bd modes in almost all
- * cases other than mass storage class. Otherwise we're correct but slow,
- * since CPPI penalizes our need for a "true RNDIS" default mode.
- */
-
-
-/* Heuristic, intended to kick in for ethernet/rndis peripheral ONLY
- *
- * IFF
- * (a) peripheral mode ... since rndis peripherals could pad their
- * writes to hosts, causing i/o failure; or we'd have to cope with
- * a largely unknowable variety of host side protocol variants
- * (b) and short reads are NOT errors ... since full reads would
- * cause those same i/o failures
- * (c) and read length is
- * - less than 64KB (max per cppi descriptor)
- * - not a multiple of 4096 (g_zero default, full reads typical)
- * - N (>1) packets long, ditto (full reads not EXPECTED)
- * THEN
- * try rx rndis mode
- *
- * Cost of heuristic failing: RXDMA wedges at the end of transfers that
- * fill out the whole buffer. Buggy host side usb network drivers could
- * trigger that, but "in the field" such bugs seem to be all but unknown.
- *
- * So this module parameter lets the heuristic be disabled. When using
- * gadgetfs, the heuristic will probably need to be disabled.
- */
-static bool cppi_rx_rndis = 1;
-
-module_param(cppi_rx_rndis, bool, 0);
-MODULE_PARM_DESC(cppi_rx_rndis, "enable/disable RX RNDIS heuristic");
-
-
-/**
- * cppi_next_rx_segment - dma read for the next chunk of a buffer
- * @musb: the controller
- * @rx: dma channel
- * @onepacket: true unless caller treats short reads as errors, and
- * performs fault recovery above usbcore.
- * Context: controller irqlocked
- *
- * See above notes about why we can't use multi-BD RX queues except in
- * rare cases (mass storage class), and can never use the hardware "rndis"
- * mode (since it's not a "true" RNDIS mode) with complete safety..
- *
- * It's ESSENTIAL that callers specify "onepacket" mode unless they kick in
- * code to recover from corrupted datastreams after each short transfer.
- */
-static void
-cppi_next_rx_segment(struct musb *musb, struct cppi_channel *rx, int onepacket)
-{
- unsigned maxpacket = rx->maxpacket;
- dma_addr_t addr = rx->buf_dma + rx->offset;
- size_t length = rx->buf_len - rx->offset;
- struct cppi_descriptor *bd, *tail;
- unsigned n_bds;
- unsigned i;
- void __iomem *tibase = musb->ctrl_base;
- int is_rndis = 0;
- struct cppi_rx_stateram __iomem *rx_ram = rx->state_ram;
- struct cppi_descriptor *d;
-
- if (onepacket) {
- /* almost every USB driver, host or peripheral side */
- n_bds = 1;
-
- /* maybe apply the heuristic above */
- if (cppi_rx_rndis
- && is_peripheral_active(musb)
- && length > maxpacket
- && (length & ~0xffff) == 0
- && (length & 0x0fff) != 0
- && (length & (maxpacket - 1)) == 0) {
- maxpacket = length;
- is_rndis = 1;
- }
- } else {
- /* virtually nothing except mass storage class */
- if (length > 0xffff) {
- n_bds = 0xffff / maxpacket;
- length = n_bds * maxpacket;
- } else {
- n_bds = DIV_ROUND_UP(length, maxpacket);
- }
- if (n_bds == 1)
- onepacket = 1;
- else
- n_bds = min(n_bds, (unsigned) NUM_RXCHAN_BD);
- }
-
- /* In host mode, autorequest logic can generate some IN tokens; it's
- * tricky since we can't leave REQPKT set in RXCSR after the transfer
- * finishes. So: multipacket transfers involve two or more segments.
- * And always at least two IRQs ... RNDIS mode is not an option.
- */
- if (is_host_active(musb))
- n_bds = cppi_autoreq_update(rx, tibase, onepacket, n_bds);
-
- cppi_rndis_update(rx, 1, musb->ctrl_base, is_rndis);
-
- length = min(n_bds * maxpacket, length);
-
- musb_dbg(musb, "RX DMA%d seg, maxp %d %s bds %d (cnt %d) "
- "dma 0x%llx len %u %u/%u",
- rx->index, maxpacket,
- onepacket
- ? (is_rndis ? "rndis" : "onepacket")
- : "multipacket",
- n_bds,
- musb_readl(tibase,
- DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4))
- & 0xffff,
- (unsigned long long)addr, length,
- rx->channel.actual_len, rx->buf_len);
-
- /* only queue one segment at a time, since the hardware prevents
- * correct queue shutdown after unexpected short packets
- */
- bd = cppi_bd_alloc(rx);
- rx->head = bd;
-
- /* Build BDs for all packets in this segment */
- for (i = 0, tail = NULL; bd && i < n_bds; i++, tail = bd) {
- u32 bd_len;
-
- if (i) {
- bd = cppi_bd_alloc(rx);
- if (!bd)
- break;
- tail->next = bd;
- tail->hw_next = bd->dma;
- }
- bd->hw_next = 0;
-
- /* all but the last packet will be maxpacket size */
- if (maxpacket < length)
- bd_len = maxpacket;
- else
- bd_len = length;
-
- bd->hw_bufp = addr;
- addr += bd_len;
- rx->offset += bd_len;
-
- bd->hw_off_len = (0 /*offset*/ << 16) + bd_len;
- bd->buflen = bd_len;
-
- bd->hw_options = CPPI_OWN_SET | (i == 0 ? length : 0);
- length -= bd_len;
- }
-
- /* we always expect at least one reusable BD! */
- if (!tail) {
- WARNING("rx dma%d -- no BDs? need %d\n", rx->index, n_bds);
- return;
- } else if (i < n_bds)
- WARNING("rx dma%d -- only %d of %d BDs\n", rx->index, i, n_bds);
-
- tail->next = NULL;
- tail->hw_next = 0;
-
- bd = rx->head;
- rx->tail = tail;
-
- /* short reads and other faults should terminate this entire
- * dma segment. we want one "dma packet" per dma segment, not
- * one per USB packet, terminating the whole queue at once...
- * NOTE that current hardware seems to ignore SOP and EOP.
- */
- bd->hw_options |= CPPI_SOP_SET;
- tail->hw_options |= CPPI_EOP_SET;
-
- for (d = rx->head; d; d = d->next)
- cppi_dump_rxbd("S", d);
-
- /* in case the preceding transfer left some state... */
- tail = rx->last_processed;
- if (tail) {
- tail->next = bd;
- tail->hw_next = bd->dma;
- }
-
- core_rxirq_enable(tibase, rx->index + 1);
-
- /* BDs live in DMA-coherent memory, but writes might be pending */
- cpu_drain_writebuffer();
-
- /* REVISIT specs say to write this AFTER the BUFCNT register
- * below ... but that loses badly.
- */
- musb_writel(&rx_ram->rx_head, 0, bd->dma);
-
- /* bufferCount must be at least 3, and zeroes on completion
- * unless it underflows below zero, or stops at two, or keeps
- * growing ... grr.
- */
- i = musb_readl(tibase,
- DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4))
- & 0xffff;
-
- if (!i)
- musb_writel(tibase,
- DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4),
- n_bds + 2);
- else if (n_bds > (i - 3))
- musb_writel(tibase,
- DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4),
- n_bds - (i - 3));
-
- i = musb_readl(tibase,
- DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4))
- & 0xffff;
- if (i < (2 + n_bds)) {
- musb_dbg(musb, "bufcnt%d underrun - %d (for %d)",
- rx->index, i, n_bds);
- musb_writel(tibase,
- DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4),
- n_bds + 2);
- }
-
- cppi_dump_rx(4, rx, "/S");
-}
-
-/**
- * cppi_channel_program - program channel for data transfer
- * @ch: the channel
- * @maxpacket: max packet size
- * @mode: For RX, 1 unless the usb protocol driver promised to treat
- * all short reads as errors and kick in high level fault recovery.
- * For TX, ignored because of RNDIS mode races/glitches.
- * @dma_addr: dma address of buffer
- * @len: length of buffer
- * Context: controller irqlocked
- */
-static int cppi_channel_program(struct dma_channel *ch,
- u16 maxpacket, u8 mode,
- dma_addr_t dma_addr, u32 len)
-{
- struct cppi_channel *cppi_ch;
- struct cppi *controller;
- struct musb *musb;
-
- cppi_ch = container_of(ch, struct cppi_channel, channel);
- controller = cppi_ch->controller;
- musb = controller->controller.musb;
-
- switch (ch->status) {
- case MUSB_DMA_STATUS_BUS_ABORT:
- case MUSB_DMA_STATUS_CORE_ABORT:
- /* fault irq handler should have handled cleanup */
- WARNING("%cX DMA%d not cleaned up after abort!\n",
- cppi_ch->transmit ? 'T' : 'R',
- cppi_ch->index);
- /* WARN_ON(1); */
- break;
- case MUSB_DMA_STATUS_BUSY:
- WARNING("program active channel? %cX DMA%d\n",
- cppi_ch->transmit ? 'T' : 'R',
- cppi_ch->index);
- /* WARN_ON(1); */
- break;
- case MUSB_DMA_STATUS_UNKNOWN:
- musb_dbg(musb, "%cX DMA%d not allocated!",
- cppi_ch->transmit ? 'T' : 'R',
- cppi_ch->index);
- fallthrough;
- case MUSB_DMA_STATUS_FREE:
- break;
- }
-
- ch->status = MUSB_DMA_STATUS_BUSY;
-
- /* set transfer parameters, then queue up its first segment */
- cppi_ch->buf_dma = dma_addr;
- cppi_ch->offset = 0;
- cppi_ch->maxpacket = maxpacket;
- cppi_ch->buf_len = len;
- cppi_ch->channel.actual_len = 0;
-
- /* TX channel? or RX? */
- if (cppi_ch->transmit)
- cppi_next_tx_segment(musb, cppi_ch);
- else
- cppi_next_rx_segment(musb, cppi_ch, mode);
-
- return true;
-}
-
-static bool cppi_rx_scan(struct cppi *cppi, unsigned ch)
-{
- struct cppi_channel *rx = &cppi->rx[ch];
- struct cppi_rx_stateram __iomem *state = rx->state_ram;
- struct cppi_descriptor *bd;
- struct cppi_descriptor *last = rx->last_processed;
- bool completed = false;
- bool acked = false;
- int i;
- dma_addr_t safe2ack;
- void __iomem *regs = rx->hw_ep->regs;
- struct musb *musb = cppi->controller.musb;
-
- cppi_dump_rx(6, rx, "/K");
-
- bd = last ? last->next : rx->head;
- if (!bd)
- return false;
-
- /* run through all completed BDs */
- for (i = 0, safe2ack = musb_readl(&state->rx_complete, 0);
- (safe2ack || completed) && bd && i < NUM_RXCHAN_BD;
- i++, bd = bd->next) {
- u16 len;
-
- /* catch latest BD writes from CPPI */
- rmb();
- if (!completed && (bd->hw_options & CPPI_OWN_SET))
- break;
-
- musb_dbg(musb, "C/RXBD %llx: nxt %08x buf %08x "
- "off.len %08x opt.len %08x (%d)",
- (unsigned long long)bd->dma, bd->hw_next, bd->hw_bufp,
- bd->hw_off_len, bd->hw_options,
- rx->channel.actual_len);
-
- /* actual packet received length */
- if ((bd->hw_options & CPPI_SOP_SET) && !completed)
- len = bd->hw_off_len & CPPI_RECV_PKTLEN_MASK;
- else
- len = 0;
-
- if (bd->hw_options & CPPI_EOQ_MASK)
- completed = true;
-
- if (!completed && len < bd->buflen) {
- /* NOTE: when we get a short packet, RXCSR_H_REQPKT
- * must have been cleared, and no more DMA packets may
- * active be in the queue... TI docs didn't say, but
- * CPPI ignores those BDs even though OWN is still set.
- */
- completed = true;
- musb_dbg(musb, "rx short %d/%d (%d)",
- len, bd->buflen,
- rx->channel.actual_len);
- }
-
- /* If we got here, we expect to ack at least one BD; meanwhile
- * CPPI may completing other BDs while we scan this list...
- *
- * RACE: we can notice OWN cleared before CPPI raises the
- * matching irq by writing that BD as the completion pointer.
- * In such cases, stop scanning and wait for the irq, avoiding
- * lost acks and states where BD ownership is unclear.
- */
- if (bd->dma == safe2ack) {
- musb_writel(&state->rx_complete, 0, safe2ack);
- safe2ack = musb_readl(&state->rx_complete, 0);
- acked = true;
- if (bd->dma == safe2ack)
- safe2ack = 0;
- }
-
- rx->channel.actual_len += len;
-
- cppi_bd_free(rx, last);
- last = bd;
-
- /* stop scanning on end-of-segment */
- if (bd->hw_next == 0)
- completed = true;
- }
- rx->last_processed = last;
-
- /* dma abort, lost ack, or ... */
- if (!acked && last) {
- int csr;
-
- if (safe2ack == 0 || safe2ack == rx->last_processed->dma)
- musb_writel(&state->rx_complete, 0, safe2ack);
- if (safe2ack == 0) {
- cppi_bd_free(rx, last);
- rx->last_processed = NULL;
-
- /* if we land here on the host side, H_REQPKT will
- * be clear and we need to restart the queue...
- */
- WARN_ON(rx->head);
- }
- musb_ep_select(cppi->mregs, rx->index + 1);
- csr = musb_readw(regs, MUSB_RXCSR);
- if (csr & MUSB_RXCSR_DMAENAB) {
- musb_dbg(musb, "list%d %p/%p, last %llx%s, csr %04x",
- rx->index,
- rx->head, rx->tail,
- rx->last_processed
- ? (unsigned long long)
- rx->last_processed->dma
- : 0,
- completed ? ", completed" : "",
- csr);
- cppi_dump_rxq(4, "/what?", rx);
- }
- }
- if (!completed) {
- int csr;
-
- rx->head = bd;
-
- /* REVISIT seems like "autoreq all but EOP" doesn't...
- * setting it here "should" be racey, but seems to work
- */
- csr = musb_readw(rx->hw_ep->regs, MUSB_RXCSR);
- if (is_host_active(cppi->controller.musb)
- && bd
- && !(csr & MUSB_RXCSR_H_REQPKT)) {
- csr |= MUSB_RXCSR_H_REQPKT;
- musb_writew(regs, MUSB_RXCSR,
- MUSB_RXCSR_H_WZC_BITS | csr);
- csr = musb_readw(rx->hw_ep->regs, MUSB_RXCSR);
- }
- } else {
- rx->head = NULL;
- rx->tail = NULL;
- }
-
- cppi_dump_rx(6, rx, completed ? "/completed" : "/cleaned");
- return completed;
-}
-
-irqreturn_t cppi_interrupt(int irq, void *dev_id)
-{
- struct musb *musb = dev_id;
- struct cppi *cppi;
- void __iomem *tibase;
- struct musb_hw_ep *hw_ep = NULL;
- u32 rx, tx;
- int i, index;
- unsigned long flags;
-
- cppi = container_of(musb->dma_controller, struct cppi, controller);
- if (cppi->irq)
- spin_lock_irqsave(&musb->lock, flags);
-
- tibase = musb->ctrl_base;
-
- tx = musb_readl(tibase, DAVINCI_TXCPPI_MASKED_REG);
- rx = musb_readl(tibase, DAVINCI_RXCPPI_MASKED_REG);
-
- if (!tx && !rx) {
- if (cppi->irq)
- spin_unlock_irqrestore(&musb->lock, flags);
- return IRQ_NONE;
- }
-
- musb_dbg(musb, "CPPI IRQ Tx%x Rx%x", tx, rx);
-
- /* process TX channels */
- for (index = 0; tx; tx = tx >> 1, index++) {
- struct cppi_channel *tx_ch;
- struct cppi_tx_stateram __iomem *tx_ram;
- bool completed = false;
- struct cppi_descriptor *bd;
-
- if (!(tx & 1))
- continue;
-
- tx_ch = cppi->tx + index;
- tx_ram = tx_ch->state_ram;
-
- /* FIXME need a cppi_tx_scan() routine, which
- * can also be called from abort code
- */
-
- cppi_dump_tx(5, tx_ch, "/E");
-
- bd = tx_ch->head;
-
- /*
- * If Head is null then this could mean that a abort interrupt
- * that needs to be acknowledged.
- */
- if (NULL == bd) {
- musb_dbg(musb, "null BD");
- musb_writel(&tx_ram->tx_complete, 0, 0);
- continue;
- }
-
- /* run through all completed BDs */
- for (i = 0; !completed && bd && i < NUM_TXCHAN_BD;
- i++, bd = bd->next) {
- u16 len;
-
- /* catch latest BD writes from CPPI */
- rmb();
- if (bd->hw_options & CPPI_OWN_SET)
- break;
-
- musb_dbg(musb, "C/TXBD %p n %x b %x off %x opt %x",
- bd, bd->hw_next, bd->hw_bufp,
- bd->hw_off_len, bd->hw_options);
-
- len = bd->hw_off_len & CPPI_BUFFER_LEN_MASK;
- tx_ch->channel.actual_len += len;
-
- tx_ch->last_processed = bd;
-
- /* write completion register to acknowledge
- * processing of completed BDs, and possibly
- * release the IRQ; EOQ might not be set ...
- *
- * REVISIT use the same ack strategy as rx
- *
- * REVISIT have observed bit 18 set; huh??
- */
- /* if ((bd->hw_options & CPPI_EOQ_MASK)) */
- musb_writel(&tx_ram->tx_complete, 0, bd->dma);
-
- /* stop scanning on end-of-segment */
- if (bd->hw_next == 0)
- completed = true;
- }
-
- /* on end of segment, maybe go to next one */
- if (completed) {
- /* cppi_dump_tx(4, tx_ch, "/complete"); */
-
- /* transfer more, or report completion */
- if (tx_ch->offset >= tx_ch->buf_len) {
- tx_ch->head = NULL;
- tx_ch->tail = NULL;
- tx_ch->channel.status = MUSB_DMA_STATUS_FREE;
-
- hw_ep = tx_ch->hw_ep;
-
- musb_dma_completion(musb, index + 1, 1);
-
- } else {
- /* Bigger transfer than we could fit in
- * that first batch of descriptors...
- */
- cppi_next_tx_segment(musb, tx_ch);
- }
- } else
- tx_ch->head = bd;
- }
-
- /* Start processing the RX block */
- for (index = 0; rx; rx = rx >> 1, index++) {
-
- if (rx & 1) {
- struct cppi_channel *rx_ch;
-
- rx_ch = cppi->rx + index;
-
- /* let incomplete dma segments finish */
- if (!cppi_rx_scan(cppi, index))
- continue;
-
- /* start another dma segment if needed */
- if (rx_ch->channel.actual_len != rx_ch->buf_len
- && rx_ch->channel.actual_len
- == rx_ch->offset) {
- cppi_next_rx_segment(musb, rx_ch, 1);
- continue;
- }
-
- /* all segments completed! */
- rx_ch->channel.status = MUSB_DMA_STATUS_FREE;
-
- hw_ep = rx_ch->hw_ep;
-
- core_rxirq_disable(tibase, index + 1);
- musb_dma_completion(musb, index + 1, 0);
- }
- }
-
- /* write to CPPI EOI register to re-enable interrupts */
- musb_writel(tibase, DAVINCI_CPPI_EOI_REG, 0);
-
- if (cppi->irq)
- spin_unlock_irqrestore(&musb->lock, flags);
-
- return IRQ_HANDLED;
-}
-EXPORT_SYMBOL_GPL(cppi_interrupt);
-
-/* Instantiate a software object representing a DMA controller. */
-struct dma_controller *
-cppi_dma_controller_create(struct musb *musb, void __iomem *mregs)
-{
- struct cppi *controller;
- struct device *dev = musb->controller;
- struct platform_device *pdev = to_platform_device(dev);
- int irq = platform_get_irq_byname(pdev, "dma");
-
- controller = kzalloc(sizeof *controller, GFP_KERNEL);
- if (!controller)
- return NULL;
-
- controller->mregs = mregs;
- controller->tibase = mregs - DAVINCI_BASE_OFFSET;
-
- controller->controller.musb = musb;
- controller->controller.channel_alloc = cppi_channel_allocate;
- controller->controller.channel_release = cppi_channel_release;
- controller->controller.channel_program = cppi_channel_program;
- controller->controller.channel_abort = cppi_channel_abort;
-
- /* NOTE: allocating from on-chip SRAM would give the least
- * contention for memory access, if that ever matters here.
- */
-
- /* setup BufferPool */
- controller->pool = dma_pool_create("cppi",
- controller->controller.musb->controller,
- sizeof(struct cppi_descriptor),
- CPPI_DESCRIPTOR_ALIGN, 0);
- if (!controller->pool) {
- kfree(controller);
- return NULL;
- }
-
- if (irq > 0) {
- if (request_irq(irq, cppi_interrupt, 0, "cppi-dma", musb)) {
- dev_err(dev, "request_irq %d failed!\n", irq);
- musb_dma_controller_destroy(&controller->controller);
- return NULL;
- }
- controller->irq = irq;
- }
-
- cppi_controller_start(controller);
- return &controller->controller;
-}
-EXPORT_SYMBOL_GPL(cppi_dma_controller_create);
-
-/*
- * Destroy a previously-instantiated DMA controller.
- */
-void cppi_dma_controller_destroy(struct dma_controller *c)
-{
- struct cppi *cppi;
-
- cppi = container_of(c, struct cppi, controller);
-
- cppi_controller_stop(cppi);
-
- if (cppi->irq)
- free_irq(cppi->irq, cppi->controller.musb);
-
- /* assert: caller stopped the controller first */
- dma_pool_destroy(cppi->pool);
-
- kfree(cppi);
-}
-EXPORT_SYMBOL_GPL(cppi_dma_controller_destroy);
-
-/*
- * Context: controller irqlocked, endpoint selected
- */
-static int cppi_channel_abort(struct dma_channel *channel)
-{
- struct cppi_channel *cppi_ch;
- struct cppi *controller;
- void __iomem *mbase;
- void __iomem *tibase;
- void __iomem *regs;
- u32 value;
- struct cppi_descriptor *queue;
-
- cppi_ch = container_of(channel, struct cppi_channel, channel);
-
- controller = cppi_ch->controller;
-
- switch (channel->status) {
- case MUSB_DMA_STATUS_BUS_ABORT:
- case MUSB_DMA_STATUS_CORE_ABORT:
- /* from RX or TX fault irq handler */
- case MUSB_DMA_STATUS_BUSY:
- /* the hardware needs shutting down */
- regs = cppi_ch->hw_ep->regs;
- break;
- case MUSB_DMA_STATUS_UNKNOWN:
- case MUSB_DMA_STATUS_FREE:
- return 0;
- default:
- return -EINVAL;
- }
-
- if (!cppi_ch->transmit && cppi_ch->head)
- cppi_dump_rxq(3, "/abort", cppi_ch);
-
- mbase = controller->mregs;
- tibase = controller->tibase;
-
- queue = cppi_ch->head;
- cppi_ch->head = NULL;
- cppi_ch->tail = NULL;
-
- /* REVISIT should rely on caller having done this,
- * and caller should rely on us not changing it.
- * peripheral code is safe ... check host too.
- */
- musb_ep_select(mbase, cppi_ch->index + 1);
-
- if (cppi_ch->transmit) {
- struct cppi_tx_stateram __iomem *tx_ram;
- /* REVISIT put timeouts on these controller handshakes */
-
- cppi_dump_tx(6, cppi_ch, " (teardown)");
-
- /* teardown DMA engine then usb core */
- do {
- value = musb_readl(tibase, DAVINCI_TXCPPI_TEAR_REG);
- } while (!(value & CPPI_TEAR_READY));
- musb_writel(tibase, DAVINCI_TXCPPI_TEAR_REG, cppi_ch->index);
-
- tx_ram = cppi_ch->state_ram;
- do {
- value = musb_readl(&tx_ram->tx_complete, 0);
- } while (0xFFFFFFFC != value);
-
- /* FIXME clean up the transfer state ... here?
- * the completion routine should get called with
- * an appropriate status code.
- */
-
- value = musb_readw(regs, MUSB_TXCSR);
- value &= ~MUSB_TXCSR_DMAENAB;
- value |= MUSB_TXCSR_FLUSHFIFO;
- musb_writew(regs, MUSB_TXCSR, value);
- musb_writew(regs, MUSB_TXCSR, value);
-
- /*
- * 1. Write to completion Ptr value 0x1(bit 0 set)
- * (write back mode)
- * 2. Wait for abort interrupt and then put the channel in
- * compare mode by writing 1 to the tx_complete register.
- */
- cppi_reset_tx(tx_ram, 1);
- cppi_ch->head = NULL;
- musb_writel(&tx_ram->tx_complete, 0, 1);
- cppi_dump_tx(5, cppi_ch, " (done teardown)");
-
- /* REVISIT tx side _should_ clean up the same way
- * as the RX side ... this does no cleanup at all!
- */
-
- } else /* RX */ {
- u16 csr;
-
- /* NOTE: docs don't guarantee any of this works ... we
- * expect that if the usb core stops telling the cppi core
- * to pull more data from it, then it'll be safe to flush
- * current RX DMA state iff any pending fifo transfer is done.
- */
-
- core_rxirq_disable(tibase, cppi_ch->index + 1);
-
- /* for host, ensure ReqPkt is never set again */
- if (is_host_active(cppi_ch->controller->controller.musb)) {
- value = musb_readl(tibase, DAVINCI_AUTOREQ_REG);
- value &= ~((0x3) << (cppi_ch->index * 2));
- musb_writel(tibase, DAVINCI_AUTOREQ_REG, value);
- }
-
- csr = musb_readw(regs, MUSB_RXCSR);
-
- /* for host, clear (just) ReqPkt at end of current packet(s) */
- if (is_host_active(cppi_ch->controller->controller.musb)) {
- csr |= MUSB_RXCSR_H_WZC_BITS;
- csr &= ~MUSB_RXCSR_H_REQPKT;
- } else
- csr |= MUSB_RXCSR_P_WZC_BITS;
-
- /* clear dma enable */
- csr &= ~(MUSB_RXCSR_DMAENAB);
- musb_writew(regs, MUSB_RXCSR, csr);
- csr = musb_readw(regs, MUSB_RXCSR);
-
- /* Quiesce: wait for current dma to finish (if not cleanup).
- * We can't use bit zero of stateram->rx_sop, since that
- * refers to an entire "DMA packet" not just emptying the
- * current fifo. Most segments need multiple usb packets.
- */
- if (channel->status == MUSB_DMA_STATUS_BUSY)
- udelay(50);
-
- /* scan the current list, reporting any data that was
- * transferred and acking any IRQ
- */
- cppi_rx_scan(controller, cppi_ch->index);
-
- /* clobber the existing state once it's idle
- *
- * NOTE: arguably, we should also wait for all the other
- * RX channels to quiesce (how??) and then temporarily
- * disable RXCPPI_CTRL_REG ... but it seems that we can
- * rely on the controller restarting from state ram, with
- * only RXCPPI_BUFCNT state being bogus. BUFCNT will
- * correct itself after the next DMA transfer though.
- *
- * REVISIT does using rndis mode change that?
- */
- cppi_reset_rx(cppi_ch->state_ram);
-
- /* next DMA request _should_ load cppi head ptr */
-
- /* ... we don't "free" that list, only mutate it in place. */
- cppi_dump_rx(5, cppi_ch, " (done abort)");
-
- /* clean up previously pending bds */
- cppi_bd_free(cppi_ch, cppi_ch->last_processed);
- cppi_ch->last_processed = NULL;
-
- while (queue) {
- struct cppi_descriptor *tmp = queue->next;
-
- cppi_bd_free(cppi_ch, queue);
- queue = tmp;
- }
- }
-
- channel->status = MUSB_DMA_STATUS_FREE;
- cppi_ch->buf_dma = 0;
- cppi_ch->offset = 0;
- cppi_ch->buf_len = 0;
- cppi_ch->maxpacket = 0;
- return 0;
-}
-
-/* TBD Queries:
- *
- * Power Management ... probably turn off cppi during suspend, restart;
- * check state ram? Clocking is presumably shared with usb core.
- */
diff --git a/drivers/usb/musb/davinci.c b/drivers/usb/musb/davinci.c
deleted file mode 100644
index 704435526394..000000000000
--- a/drivers/usb/musb/davinci.c
+++ /dev/null
@@ -1,606 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2005-2006 by Texas Instruments
- *
- * This file is part of the Inventra Controller Driver for Linux.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/list.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/gpio/consumer.h>
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/usb/usb_phy_generic.h>
-
-#include <mach/cputype.h>
-#include <mach/hardware.h>
-
-#include <asm/mach-types.h>
-
-#include "musb_core.h"
-
-#include "davinci.h"
-#include "cppi_dma.h"
-
-
-#define USB_PHY_CTRL IO_ADDRESS(USBPHY_CTL_PADDR)
-#define DM355_DEEPSLEEP IO_ADDRESS(DM355_DEEPSLEEP_PADDR)
-
-struct davinci_glue {
- struct device *dev;
- struct platform_device *musb;
- struct clk *clk;
- bool vbus_state;
- struct gpio_desc *vbus;
- struct work_struct vbus_work;
-};
-
-/* REVISIT (PM) we should be able to keep the PHY in low power mode most
- * of the time (24 MHZ oscillator and PLL off, etc) by setting POWER.D0
- * and, when in host mode, autosuspending idle root ports... PHYPLLON
- * (overriding SUSPENDM?) then likely needs to stay off.
- */
-
-static inline void phy_on(void)
-{
- u32 phy_ctrl = __raw_readl(USB_PHY_CTRL);
-
- /* power everything up; start the on-chip PHY and its PLL */
- phy_ctrl &= ~(USBPHY_OSCPDWN | USBPHY_OTGPDWN | USBPHY_PHYPDWN);
- phy_ctrl |= USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON;
- __raw_writel(phy_ctrl, USB_PHY_CTRL);
-
- /* wait for PLL to lock before proceeding */
- while ((__raw_readl(USB_PHY_CTRL) & USBPHY_PHYCLKGD) == 0)
- cpu_relax();
-}
-
-static inline void phy_off(void)
-{
- u32 phy_ctrl = __raw_readl(USB_PHY_CTRL);
-
- /* powerdown the on-chip PHY, its PLL, and the OTG block */
- phy_ctrl &= ~(USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON);
- phy_ctrl |= USBPHY_OSCPDWN | USBPHY_OTGPDWN | USBPHY_PHYPDWN;
- __raw_writel(phy_ctrl, USB_PHY_CTRL);
-}
-
-static int dma_off = 1;
-
-static void davinci_musb_enable(struct musb *musb)
-{
- u32 tmp, old, val;
-
- /* workaround: setup irqs through both register sets */
- tmp = (musb->epmask & DAVINCI_USB_TX_ENDPTS_MASK)
- << DAVINCI_USB_TXINT_SHIFT;
- musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
- old = tmp;
- tmp = (musb->epmask & (0xfffe & DAVINCI_USB_RX_ENDPTS_MASK))
- << DAVINCI_USB_RXINT_SHIFT;
- musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
- tmp |= old;
-
- val = ~MUSB_INTR_SOF;
- tmp |= ((val & 0x01ff) << DAVINCI_USB_USBINT_SHIFT);
- musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
-
- if (is_dma_capable() && !dma_off)
- printk(KERN_WARNING "%s %s: dma not reactivated\n",
- __FILE__, __func__);
- else
- dma_off = 0;
-
- /* force a DRVVBUS irq so we can start polling for ID change */
- musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
- DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT);
-}
-
-/*
- * Disable the HDRC and flush interrupts
- */
-static void davinci_musb_disable(struct musb *musb)
-{
- /* because we don't set CTRLR.UINT, "important" to:
- * - not read/write INTRUSB/INTRUSBE
- * - (except during initial setup, as workaround)
- * - use INTSETR/INTCLRR instead
- */
- musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_CLR_REG,
- DAVINCI_USB_USBINT_MASK
- | DAVINCI_USB_TXINT_MASK
- | DAVINCI_USB_RXINT_MASK);
- musb_writel(musb->ctrl_base, DAVINCI_USB_EOI_REG, 0);
-
- if (is_dma_capable() && !dma_off)
- WARNING("dma still active\n");
-}
-
-
-#define portstate(stmt) stmt
-
-/*
- * VBUS SWITCHING IS BOARD-SPECIFIC ... at least for the DM6446 EVM,
- * which doesn't wire DRVVBUS to the FET that switches it. Unclear
- * if that's a problem with the DM6446 chip or just with that board.
- *
- * In either case, the DM355 EVM automates DRVVBUS the normal way,
- * when J10 is out, and TI documents it as handling OTG.
- */
-
-/* I2C operations are always synchronous, and require a task context.
- * With unloaded systems, using the shared workqueue seems to suffice
- * to satisfy the 100msec A_WAIT_VRISE timeout...
- */
-static void evm_deferred_drvvbus(struct work_struct *work)
-{
- struct davinci_glue *glue = container_of(work, struct davinci_glue,
- vbus_work);
-
- gpiod_set_value_cansleep(glue->vbus, glue->vbus_state);
- glue->vbus_state = !glue->vbus_state;
-}
-
-static void davinci_musb_source_power(struct musb *musb, int is_on,
- int immediate)
-{
- struct davinci_glue *glue = dev_get_drvdata(musb->controller->parent);
-
- /* This GPIO handling is entirely optional */
- if (!glue->vbus)
- return;
-
- if (is_on)
- is_on = 1;
-
- if (glue->vbus_state == is_on)
- return;
- /* 0/1 vs "-1 == unknown/init" */
- glue->vbus_state = !is_on;
-
- if (machine_is_davinci_evm()) {
- if (immediate)
- gpiod_set_value_cansleep(glue->vbus, glue->vbus_state);
- else
- schedule_work(&glue->vbus_work);
- }
- if (immediate)
- glue->vbus_state = is_on;
-}
-
-static void davinci_musb_set_vbus(struct musb *musb, int is_on)
-{
- WARN_ON(is_on && is_peripheral_active(musb));
- davinci_musb_source_power(musb, is_on, 0);
-}
-
-
-#define POLL_SECONDS 2
-
-static void otg_timer(struct timer_list *t)
-{
- struct musb *musb = from_timer(musb, t, dev_timer);
- void __iomem *mregs = musb->mregs;
- u8 devctl;
- unsigned long flags;
-
- /* We poll because DaVinci's won't expose several OTG-critical
- * status change events (from the transceiver) otherwise.
- */
- devctl = musb_readb(mregs, MUSB_DEVCTL);
- dev_dbg(musb->controller, "poll devctl %02x (%s)\n", devctl,
- usb_otg_state_string(musb->xceiv->otg->state));
-
- spin_lock_irqsave(&musb->lock, flags);
- switch (musb->xceiv->otg->state) {
- case OTG_STATE_A_WAIT_VFALL:
- /* Wait till VBUS falls below SessionEnd (~0.2V); the 1.3 RTL
- * seems to mis-handle session "start" otherwise (or in our
- * case "recover"), in routine "VBUS was valid by the time
- * VBUSERR got reported during enumeration" cases.
- */
- if (devctl & MUSB_DEVCTL_VBUS) {
- mod_timer(&musb->dev_timer, jiffies + POLL_SECONDS * HZ);
- break;
- }
- musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
- musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
- MUSB_INTR_VBUSERROR << DAVINCI_USB_USBINT_SHIFT);
- break;
- case OTG_STATE_B_IDLE:
- /*
- * There's no ID-changed IRQ, so we have no good way to tell
- * when to switch to the A-Default state machine (by setting
- * the DEVCTL.SESSION flag).
- *
- * Workaround: whenever we're in B_IDLE, try setting the
- * session flag every few seconds. If it works, ID was
- * grounded and we're now in the A-Default state machine.
- *
- * NOTE setting the session flag is _supposed_ to trigger
- * SRP, but clearly it doesn't.
- */
- musb_writeb(mregs, MUSB_DEVCTL,
- devctl | MUSB_DEVCTL_SESSION);
- devctl = musb_readb(mregs, MUSB_DEVCTL);
- if (devctl & MUSB_DEVCTL_BDEVICE)
- mod_timer(&musb->dev_timer, jiffies + POLL_SECONDS * HZ);
- else
- musb->xceiv->otg->state = OTG_STATE_A_IDLE;
- break;
- default:
- break;
- }
- spin_unlock_irqrestore(&musb->lock, flags);
-}
-
-static irqreturn_t davinci_musb_interrupt(int irq, void *__hci)
-{
- unsigned long flags;
- irqreturn_t retval = IRQ_NONE;
- struct musb *musb = __hci;
- struct usb_otg *otg = musb->xceiv->otg;
- void __iomem *tibase = musb->ctrl_base;
- struct cppi *cppi;
- u32 tmp;
-
- spin_lock_irqsave(&musb->lock, flags);
-
- /* NOTE: DaVinci shadows the Mentor IRQs. Don't manage them through
- * the Mentor registers (except for setup), use the TI ones and EOI.
- *
- * Docs describe irq "vector" registers associated with the CPPI and
- * USB EOI registers. These hold a bitmask corresponding to the
- * current IRQ, not an irq handler address. Would using those bits
- * resolve some of the races observed in this dispatch code??
- */
-
- /* CPPI interrupts share the same IRQ line, but have their own
- * mask, state, "vector", and EOI registers.
- */
- cppi = container_of(musb->dma_controller, struct cppi, controller);
- if (is_cppi_enabled(musb) && musb->dma_controller && !cppi->irq)
- retval = cppi_interrupt(irq, __hci);
-
- /* ack and handle non-CPPI interrupts */
- tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG);
- musb_writel(tibase, DAVINCI_USB_INT_SRC_CLR_REG, tmp);
- dev_dbg(musb->controller, "IRQ %08x\n", tmp);
-
- musb->int_rx = (tmp & DAVINCI_USB_RXINT_MASK)
- >> DAVINCI_USB_RXINT_SHIFT;
- musb->int_tx = (tmp & DAVINCI_USB_TXINT_MASK)
- >> DAVINCI_USB_TXINT_SHIFT;
- musb->int_usb = (tmp & DAVINCI_USB_USBINT_MASK)
- >> DAVINCI_USB_USBINT_SHIFT;
-
- /* DRVVBUS irqs are the only proxy we have (a very poor one!) for
- * DaVinci's missing ID change IRQ. We need an ID change IRQ to
- * switch appropriately between halves of the OTG state machine.
- * Managing DEVCTL.SESSION per Mentor docs requires we know its
- * value, but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
- * Also, DRVVBUS pulses for SRP (but not at 5V) ...
- */
- if (tmp & (DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT)) {
- int drvvbus = musb_readl(tibase, DAVINCI_USB_STAT_REG);
- void __iomem *mregs = musb->mregs;
- u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
- int err = musb->int_usb & MUSB_INTR_VBUSERROR;
-
- err = musb->int_usb & MUSB_INTR_VBUSERROR;
- if (err) {
- /* The Mentor core doesn't debounce VBUS as needed
- * to cope with device connect current spikes. This
- * means it's not uncommon for bus-powered devices
- * to get VBUS errors during enumeration.
- *
- * This is a workaround, but newer RTL from Mentor
- * seems to allow a better one: "re"starting sessions
- * without waiting (on EVM, a **long** time) for VBUS
- * to stop registering in devctl.
- */
- musb->int_usb &= ~MUSB_INTR_VBUSERROR;
- musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
- mod_timer(&musb->dev_timer, jiffies + POLL_SECONDS * HZ);
- WARNING("VBUS error workaround (delay coming)\n");
- } else if (drvvbus) {
- MUSB_HST_MODE(musb);
- musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
- portstate(musb->port1_status |= USB_PORT_STAT_POWER);
- del_timer(&musb->dev_timer);
- } else {
- musb->is_active = 0;
- MUSB_DEV_MODE(musb);
- musb->xceiv->otg->state = OTG_STATE_B_IDLE;
- portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
- }
-
- /* NOTE: this must complete poweron within 100 msec
- * (OTG_TIME_A_WAIT_VRISE) but we don't check for that.
- */
- davinci_musb_source_power(musb, drvvbus, 0);
- dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
- drvvbus ? "on" : "off",
- usb_otg_state_string(musb->xceiv->otg->state),
- err ? " ERROR" : "",
- devctl);
- retval = IRQ_HANDLED;
- }
-
- if (musb->int_tx || musb->int_rx || musb->int_usb)
- retval |= musb_interrupt(musb);
-
- /* irq stays asserted until EOI is written */
- musb_writel(tibase, DAVINCI_USB_EOI_REG, 0);
-
- /* poll for ID change */
- if (musb->xceiv->otg->state == OTG_STATE_B_IDLE)
- mod_timer(&musb->dev_timer, jiffies + POLL_SECONDS * HZ);
-
- spin_unlock_irqrestore(&musb->lock, flags);
-
- return retval;
-}
-
-static int davinci_musb_set_mode(struct musb *musb, u8 mode)
-{
- /* EVM can't do this (right?) */
- return -EIO;
-}
-
-static int davinci_musb_init(struct musb *musb)
-{
- void __iomem *tibase = musb->ctrl_base;
- u32 revision;
- int ret = -ENODEV;
-
- musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
- if (IS_ERR_OR_NULL(musb->xceiv)) {
- ret = -EPROBE_DEFER;
- goto unregister;
- }
-
- musb->mregs += DAVINCI_BASE_OFFSET;
-
- /* returns zero if e.g. not clocked */
- revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG);
- if (revision == 0)
- goto fail;
-
- timer_setup(&musb->dev_timer, otg_timer, 0);
-
- davinci_musb_source_power(musb, 0, 1);
-
- /* dm355 EVM swaps D+/D- for signal integrity, and
- * is clocked from the main 24 MHz crystal.
- */
- if (machine_is_davinci_dm355_evm()) {
- u32 phy_ctrl = __raw_readl(USB_PHY_CTRL);
-
- phy_ctrl &= ~(3 << 9);
- phy_ctrl |= USBPHY_DATAPOL;
- __raw_writel(phy_ctrl, USB_PHY_CTRL);
- }
-
- /* On dm355, the default-A state machine needs DRVVBUS control.
- * If we won't be a host, there's no need to turn it on.
- */
- if (cpu_is_davinci_dm355()) {
- u32 deepsleep = __raw_readl(DM355_DEEPSLEEP);
-
- deepsleep &= ~DRVVBUS_FORCE;
- __raw_writel(deepsleep, DM355_DEEPSLEEP);
- }
-
- /* reset the controller */
- musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1);
-
- /* start the on-chip PHY and its PLL */
- phy_on();
-
- msleep(5);
-
- /* NOTE: irqs are in mixed mode, not bypass to pure-musb */
- pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n",
- revision, __raw_readl(USB_PHY_CTRL),
- musb_readb(tibase, DAVINCI_USB_CTRL_REG));
-
- musb->isr = davinci_musb_interrupt;
- return 0;
-
-fail:
- usb_put_phy(musb->xceiv);
-unregister:
- usb_phy_generic_unregister();
- return ret;
-}
-
-static int davinci_musb_exit(struct musb *musb)
-{
- int maxdelay = 30;
- u8 devctl, warn = 0;
-
- del_timer_sync(&musb->dev_timer);
-
- /* force VBUS off */
- if (cpu_is_davinci_dm355()) {
- u32 deepsleep = __raw_readl(DM355_DEEPSLEEP);
-
- deepsleep &= ~DRVVBUS_FORCE;
- deepsleep |= DRVVBUS_OVERRIDE;
- __raw_writel(deepsleep, DM355_DEEPSLEEP);
- }
-
- davinci_musb_source_power(musb, 0 /*off*/, 1);
-
- /*
- * delay, to avoid problems with module reload.
- * if there's no peripheral connected, this can take a
- * long time to fall, especially on EVM with huge C133.
- */
- do {
- devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
- if (!(devctl & MUSB_DEVCTL_VBUS))
- break;
- if ((devctl & MUSB_DEVCTL_VBUS) != warn) {
- warn = devctl & MUSB_DEVCTL_VBUS;
- dev_dbg(musb->controller, "VBUS %d\n",
- warn >> MUSB_DEVCTL_VBUS_SHIFT);
- }
- msleep(1000);
- maxdelay--;
- } while (maxdelay > 0);
-
- /* in OTG mode, another host might be connected */
- if (devctl & MUSB_DEVCTL_VBUS)
- dev_dbg(musb->controller, "VBUS off timeout (devctl %02x)\n", devctl);
-
- phy_off();
-
- usb_put_phy(musb->xceiv);
-
- return 0;
-}
-
-static const struct musb_platform_ops davinci_ops = {
- .quirks = MUSB_DMA_CPPI,
- .init = davinci_musb_init,
- .exit = davinci_musb_exit,
-
-#ifdef CONFIG_USB_TI_CPPI_DMA
- .dma_init = cppi_dma_controller_create,
- .dma_exit = cppi_dma_controller_destroy,
-#endif
- .enable = davinci_musb_enable,
- .disable = davinci_musb_disable,
-
- .set_mode = davinci_musb_set_mode,
-
- .set_vbus = davinci_musb_set_vbus,
-};
-
-static const struct platform_device_info davinci_dev_info = {
- .name = "musb-hdrc",
- .id = PLATFORM_DEVID_AUTO,
- .dma_mask = DMA_BIT_MASK(32),
-};
-
-static int davinci_probe(struct platform_device *pdev)
-{
- struct resource musb_resources[3];
- struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev);
- struct platform_device *musb;
- struct davinci_glue *glue;
- struct platform_device_info pinfo;
- struct clk *clk;
-
- int ret = -ENOMEM;
-
- glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
- if (!glue)
- goto err0;
-
- clk = devm_clk_get(&pdev->dev, "usb");
- if (IS_ERR(clk)) {
- dev_err(&pdev->dev, "failed to get clock\n");
- ret = PTR_ERR(clk);
- goto err0;
- }
-
- ret = clk_enable(clk);
- if (ret) {
- dev_err(&pdev->dev, "failed to enable clock\n");
- goto err0;
- }
-
- glue->dev = &pdev->dev;
- glue->clk = clk;
-
- pdata->platform_ops = &davinci_ops;
-
- glue->vbus = devm_gpiod_get_optional(&pdev->dev, NULL, GPIOD_OUT_LOW);
- if (IS_ERR(glue->vbus)) {
- ret = PTR_ERR(glue->vbus);
- goto err0;
- } else {
- glue->vbus_state = -1;
- INIT_WORK(&glue->vbus_work, evm_deferred_drvvbus);
- }
-
- usb_phy_generic_register();
- platform_set_drvdata(pdev, glue);
-
- memset(musb_resources, 0x00, sizeof(*musb_resources) *
- ARRAY_SIZE(musb_resources));
-
- musb_resources[0].name = pdev->resource[0].name;
- musb_resources[0].start = pdev->resource[0].start;
- musb_resources[0].end = pdev->resource[0].end;
- musb_resources[0].flags = pdev->resource[0].flags;
-
- musb_resources[1].name = pdev->resource[1].name;
- musb_resources[1].start = pdev->resource[1].start;
- musb_resources[1].end = pdev->resource[1].end;
- musb_resources[1].flags = pdev->resource[1].flags;
-
- /*
- * For DM6467 3 resources are passed. A placeholder for the 3rd
- * resource is always there, so it's safe to always copy it...
- */
- musb_resources[2].name = pdev->resource[2].name;
- musb_resources[2].start = pdev->resource[2].start;
- musb_resources[2].end = pdev->resource[2].end;
- musb_resources[2].flags = pdev->resource[2].flags;
-
- pinfo = davinci_dev_info;
- pinfo.parent = &pdev->dev;
- pinfo.res = musb_resources;
- pinfo.num_res = ARRAY_SIZE(musb_resources);
- pinfo.data = pdata;
- pinfo.size_data = sizeof(*pdata);
-
- glue->musb = musb = platform_device_register_full(&pinfo);
- if (IS_ERR(musb)) {
- ret = PTR_ERR(musb);
- dev_err(&pdev->dev, "failed to register musb device: %d\n", ret);
- goto err1;
- }
-
- return 0;
-
-err1:
- clk_disable(clk);
-
-err0:
- return ret;
-}
-
-static int davinci_remove(struct platform_device *pdev)
-{
- struct davinci_glue *glue = platform_get_drvdata(pdev);
-
- platform_device_unregister(glue->musb);
- usb_phy_generic_unregister();
- clk_disable(glue->clk);
-
- return 0;
-}
-
-static struct platform_driver davinci_driver = {
- .probe = davinci_probe,
- .remove = davinci_remove,
- .driver = {
- .name = "musb-davinci",
- },
-};
-
-MODULE_DESCRIPTION("DaVinci MUSB Glue Layer");
-MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
-MODULE_LICENSE("GPL v2");
-module_platform_driver(davinci_driver);
diff --git a/drivers/usb/musb/davinci.h b/drivers/usb/musb/davinci.h
deleted file mode 100644
index c8e67d15b510..000000000000
--- a/drivers/usb/musb/davinci.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2005-2006 by Texas Instruments
- */
-
-#ifndef __MUSB_HDRDF_H__
-#define __MUSB_HDRDF_H__
-
-/*
- * DaVinci-specific definitions
- */
-
-/* Integrated highspeed/otg PHY */
-#define USBPHY_CTL_PADDR 0x01c40034
-#define USBPHY_DATAPOL BIT(11) /* (dm355) switch D+/D- */
-#define USBPHY_PHYCLKGD BIT(8)
-#define USBPHY_SESNDEN BIT(7) /* v(sess_end) comparator */
-#define USBPHY_VBDTCTEN BIT(6) /* v(bus) comparator */
-#define USBPHY_VBUSSENS BIT(5) /* (dm355,ro) is vbus > 0.5V */
-#define USBPHY_PHYPLLON BIT(4) /* override pll suspend */
-#define USBPHY_CLKO1SEL BIT(3)
-#define USBPHY_OSCPDWN BIT(2)
-#define USBPHY_OTGPDWN BIT(1)
-#define USBPHY_PHYPDWN BIT(0)
-
-#define DM355_DEEPSLEEP_PADDR 0x01c40048
-#define DRVVBUS_FORCE BIT(2)
-#define DRVVBUS_OVERRIDE BIT(1)
-
-/* For now include usb OTG module registers here */
-#define DAVINCI_USB_VERSION_REG 0x00
-#define DAVINCI_USB_CTRL_REG 0x04
-#define DAVINCI_USB_STAT_REG 0x08
-#define DAVINCI_RNDIS_REG 0x10
-#define DAVINCI_AUTOREQ_REG 0x14
-#define DAVINCI_USB_INT_SOURCE_REG 0x20
-#define DAVINCI_USB_INT_SET_REG 0x24
-#define DAVINCI_USB_INT_SRC_CLR_REG 0x28
-#define DAVINCI_USB_INT_MASK_REG 0x2c
-#define DAVINCI_USB_INT_MASK_SET_REG 0x30
-#define DAVINCI_USB_INT_MASK_CLR_REG 0x34
-#define DAVINCI_USB_INT_SRC_MASKED_REG 0x38
-#define DAVINCI_USB_EOI_REG 0x3c
-#define DAVINCI_USB_EOI_INTVEC 0x40
-
-/* BEGIN CPPI-generic (?) */
-
-/* CPPI related registers */
-#define DAVINCI_TXCPPI_CTRL_REG 0x80
-#define DAVINCI_TXCPPI_TEAR_REG 0x84
-#define DAVINCI_CPPI_EOI_REG 0x88
-#define DAVINCI_CPPI_INTVEC_REG 0x8c
-#define DAVINCI_TXCPPI_MASKED_REG 0x90
-#define DAVINCI_TXCPPI_RAW_REG 0x94
-#define DAVINCI_TXCPPI_INTENAB_REG 0x98
-#define DAVINCI_TXCPPI_INTCLR_REG 0x9c
-
-#define DAVINCI_RXCPPI_CTRL_REG 0xC0
-#define DAVINCI_RXCPPI_MASKED_REG 0xD0
-#define DAVINCI_RXCPPI_RAW_REG 0xD4
-#define DAVINCI_RXCPPI_INTENAB_REG 0xD8
-#define DAVINCI_RXCPPI_INTCLR_REG 0xDC
-
-#define DAVINCI_RXCPPI_BUFCNT0_REG 0xE0
-#define DAVINCI_RXCPPI_BUFCNT1_REG 0xE4
-#define DAVINCI_RXCPPI_BUFCNT2_REG 0xE8
-#define DAVINCI_RXCPPI_BUFCNT3_REG 0xEC
-
-/* CPPI state RAM entries */
-#define DAVINCI_CPPI_STATERAM_BASE_OFFSET 0x100
-
-#define DAVINCI_TXCPPI_STATERAM_OFFSET(chnum) \
- (DAVINCI_CPPI_STATERAM_BASE_OFFSET + ((chnum) * 0x40))
-#define DAVINCI_RXCPPI_STATERAM_OFFSET(chnum) \
- (DAVINCI_CPPI_STATERAM_BASE_OFFSET + 0x20 + ((chnum) * 0x40))
-
-/* CPPI masks */
-#define DAVINCI_DMA_CTRL_ENABLE 1
-#define DAVINCI_DMA_CTRL_DISABLE 0
-
-#define DAVINCI_DMA_ALL_CHANNELS_ENABLE 0xF
-#define DAVINCI_DMA_ALL_CHANNELS_DISABLE 0xF
-
-/* END CPPI-generic (?) */
-
-#define DAVINCI_USB_TX_ENDPTS_MASK 0x1f /* ep0 + 4 tx */
-#define DAVINCI_USB_RX_ENDPTS_MASK 0x1e /* 4 rx */
-
-#define DAVINCI_USB_USBINT_SHIFT 16
-#define DAVINCI_USB_TXINT_SHIFT 0
-#define DAVINCI_USB_RXINT_SHIFT 8
-
-#define DAVINCI_INTR_DRVVBUS 0x0100
-
-#define DAVINCI_USB_USBINT_MASK 0x01ff0000 /* 8 Mentor, DRVVBUS */
-#define DAVINCI_USB_TXINT_MASK \
- (DAVINCI_USB_TX_ENDPTS_MASK << DAVINCI_USB_TXINT_SHIFT)
-#define DAVINCI_USB_RXINT_MASK \
- (DAVINCI_USB_RX_ENDPTS_MASK << DAVINCI_USB_RXINT_SHIFT)
-
-#define DAVINCI_BASE_OFFSET 0x400
-
-#endif /* __MUSB_HDRDF_H__ */
--
2.29.2
^ permalink raw reply related [flat|nested] 48+ messages in thread* Re: [PATCH 05/14] usb: musb: remove unused davinci support
2022-10-19 15:29 ` [PATCH 05/14] usb: musb: remove unused davinci support Arnd Bergmann
@ 2022-10-20 11:34 ` Bartosz Golaszewski
0 siblings, 0 replies; 48+ messages in thread
From: Bartosz Golaszewski @ 2022-10-20 11:34 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Sekhar Nori, linux-arm-kernel, Bin Liu, Greg Kroah-Hartman,
linux-kernel, Kevin Hilman, Arnd Bergmann, linux-usb
On Wed, Oct 19, 2022 at 5:34 PM Arnd Bergmann <arnd@kernel.org> wrote:
>
> From: Arnd Bergmann <arnd@arndb.de>
>
> The musb-davinci driver was only used on dm644x, which got removed
> in linux-6.0. The only remaining davinci machines are da8xx
> devicetree based and do not use this hardware.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH 06/14] mfd: remove dm355evm_msp driver
2022-10-19 15:29 [PATCH 00/14] ARM: remove unused davinci board & drivers Arnd Bergmann
` (4 preceding siblings ...)
2022-10-19 15:29 ` [PATCH 05/14] usb: musb: remove unused davinci support Arnd Bergmann
@ 2022-10-19 15:29 ` Arnd Bergmann
2022-10-20 11:35 ` Bartosz Golaszewski
2022-10-31 15:01 ` Lee Jones
2022-10-19 15:29 ` [PATCH 07/14] input: remove davinci keyboard driver Arnd Bergmann
` (10 subsequent siblings)
16 siblings, 2 replies; 48+ messages in thread
From: Arnd Bergmann @ 2022-10-19 15:29 UTC (permalink / raw)
To: Sekhar Nori, Bartosz Golaszewski, linux-arm-kernel, Lee Jones
Cc: linux-kernel, Kevin Hilman, Arnd Bergmann, Dmitry Torokhov,
Alessandro Zummo, Alexandre Belloni, linux-input, linux-rtc
From: Arnd Bergmann <arnd@arndb.de>
The DaVinci DM355EVM platform is gone after the removal of all
unused board files, so the MTD device along with its sub-devices
can be removed as well.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
drivers/input/misc/Kconfig | 11 -
drivers/input/misc/Makefile | 1 -
drivers/input/misc/dm355evm_keys.c | 238 ---------------
drivers/mfd/Kconfig | 8 -
drivers/mfd/Makefile | 1 -
drivers/mfd/dm355evm_msp.c | 454 -----------------------------
drivers/rtc/Kconfig | 6 -
drivers/rtc/Makefile | 1 -
drivers/rtc/rtc-dm355evm.c | 151 ----------
include/linux/mfd/dm355evm_msp.h | 79 -----
10 files changed, 950 deletions(-)
delete mode 100644 drivers/input/misc/dm355evm_keys.c
delete mode 100644 drivers/mfd/dm355evm_msp.c
delete mode 100644 drivers/rtc/rtc-dm355evm.c
delete mode 100644 include/linux/mfd/dm355evm_msp.h
diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig
index 9f088900f863..540633b164d4 100644
--- a/drivers/input/misc/Kconfig
+++ b/drivers/input/misc/Kconfig
@@ -662,17 +662,6 @@ config INPUT_DA9063_ONKEY
To compile this driver as a module, choose M here: the module
will be called da9063_onkey.
-config INPUT_DM355EVM
- tristate "TI DaVinci DM355 EVM Keypad and IR Remote"
- depends on MFD_DM355EVM_MSP
- select INPUT_SPARSEKMAP
- help
- Supports the pushbuttons and IR remote used with
- the DM355 EVM board.
-
- To compile this driver as a module, choose M here: the
- module will be called dm355evm_keys.
-
config INPUT_WM831X_ON
tristate "WM831X ON pin"
depends on MFD_WM831X
diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile
index 6abefc41037b..156f9c21f53b 100644
--- a/drivers/input/misc/Makefile
+++ b/drivers/input/misc/Makefile
@@ -31,7 +31,6 @@ obj-$(CONFIG_INPUT_DA7280_HAPTICS) += da7280.o
obj-$(CONFIG_INPUT_DA9052_ONKEY) += da9052_onkey.o
obj-$(CONFIG_INPUT_DA9055_ONKEY) += da9055_onkey.o
obj-$(CONFIG_INPUT_DA9063_ONKEY) += da9063_onkey.o
-obj-$(CONFIG_INPUT_DM355EVM) += dm355evm_keys.o
obj-$(CONFIG_INPUT_E3X0_BUTTON) += e3x0-button.o
obj-$(CONFIG_INPUT_DRV260X_HAPTICS) += drv260x.o
obj-$(CONFIG_INPUT_DRV2665_HAPTICS) += drv2665.o
diff --git a/drivers/input/misc/dm355evm_keys.c b/drivers/input/misc/dm355evm_keys.c
deleted file mode 100644
index 397ca7c787cc..000000000000
--- a/drivers/input/misc/dm355evm_keys.c
+++ /dev/null
@@ -1,238 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * dm355evm_keys.c - support buttons and IR remote on DM355 EVM board
- *
- * Copyright (c) 2008 by David Brownell
- */
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/input.h>
-#include <linux/input/sparse-keymap.h>
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-
-#include <linux/mfd/dm355evm_msp.h>
-#include <linux/module.h>
-
-
-/*
- * The MSP430 firmware on the DM355 EVM monitors on-board pushbuttons
- * and an IR receptor used for the remote control. When any key is
- * pressed, or its autorepeat kicks in, an event is sent. This driver
- * read those events from the small (32 event) queue and reports them.
- *
- * Note that physically there can only be one of these devices.
- *
- * This driver was tested with firmware revision A4.
- */
-struct dm355evm_keys {
- struct input_dev *input;
- struct device *dev;
-};
-
-/* These initial keycodes can be remapped */
-static const struct key_entry dm355evm_keys[] = {
- /*
- * Pushbuttons on the EVM board ... note that the labels for these
- * are SW10/SW11/etc on the PC board. The left/right orientation
- * comes only from the firmware's documentation, and presumes the
- * power connector is immediately in front of you and the IR sensor
- * is to the right. (That is, rotate the board counter-clockwise
- * by 90 degrees from the SW10/etc and "DM355 EVM" labels.)
- */
- { KE_KEY, 0x00d8, { KEY_OK } }, /* SW12 */
- { KE_KEY, 0x00b8, { KEY_UP } }, /* SW13 */
- { KE_KEY, 0x00e8, { KEY_DOWN } }, /* SW11 */
- { KE_KEY, 0x0078, { KEY_LEFT } }, /* SW14 */
- { KE_KEY, 0x00f0, { KEY_RIGHT } }, /* SW10 */
-
- /*
- * IR buttons ... codes assigned to match the universal remote
- * provided with the EVM (Philips PM4S) using DVD code 0020.
- *
- * These event codes match firmware documentation, but other
- * remote controls could easily send more RC5-encoded events.
- * The PM4S manual was used in several cases to help select
- * a keycode reflecting the intended usage.
- *
- * RC5 codes are 14 bits, with two start bits (0x3 prefix)
- * and a toggle bit (masked out below).
- */
- { KE_KEY, 0x300c, { KEY_POWER } }, /* NOTE: docs omit this */
- { KE_KEY, 0x3000, { KEY_NUMERIC_0 } },
- { KE_KEY, 0x3001, { KEY_NUMERIC_1 } },
- { KE_KEY, 0x3002, { KEY_NUMERIC_2 } },
- { KE_KEY, 0x3003, { KEY_NUMERIC_3 } },
- { KE_KEY, 0x3004, { KEY_NUMERIC_4 } },
- { KE_KEY, 0x3005, { KEY_NUMERIC_5 } },
- { KE_KEY, 0x3006, { KEY_NUMERIC_6 } },
- { KE_KEY, 0x3007, { KEY_NUMERIC_7 } },
- { KE_KEY, 0x3008, { KEY_NUMERIC_8 } },
- { KE_KEY, 0x3009, { KEY_NUMERIC_9 } },
- { KE_KEY, 0x3022, { KEY_ENTER } },
- { KE_KEY, 0x30ec, { KEY_MODE } }, /* "tv/vcr/..." */
- { KE_KEY, 0x300f, { KEY_SELECT } }, /* "info" */
- { KE_KEY, 0x3020, { KEY_CHANNELUP } }, /* "up" */
- { KE_KEY, 0x302e, { KEY_MENU } }, /* "in/out" */
- { KE_KEY, 0x3011, { KEY_VOLUMEDOWN } }, /* "left" */
- { KE_KEY, 0x300d, { KEY_MUTE } }, /* "ok" */
- { KE_KEY, 0x3010, { KEY_VOLUMEUP } }, /* "right" */
- { KE_KEY, 0x301e, { KEY_SUBTITLE } }, /* "cc" */
- { KE_KEY, 0x3021, { KEY_CHANNELDOWN } },/* "down" */
- { KE_KEY, 0x3022, { KEY_PREVIOUS } },
- { KE_KEY, 0x3026, { KEY_SLEEP } },
- { KE_KEY, 0x3172, { KEY_REWIND } }, /* NOTE: docs wrongly say 0x30ca */
- { KE_KEY, 0x3175, { KEY_PLAY } },
- { KE_KEY, 0x3174, { KEY_FASTFORWARD } },
- { KE_KEY, 0x3177, { KEY_RECORD } },
- { KE_KEY, 0x3176, { KEY_STOP } },
- { KE_KEY, 0x3169, { KEY_PAUSE } },
-};
-
-/*
- * Because we communicate with the MSP430 using I2C, and all I2C calls
- * in Linux sleep, we use a threaded IRQ handler. The IRQ itself is
- * active low, but we go through the GPIO controller so we can trigger
- * on falling edges and not worry about enabling/disabling the IRQ in
- * the keypress handling path.
- */
-static irqreturn_t dm355evm_keys_irq(int irq, void *_keys)
-{
- static u16 last_event;
- struct dm355evm_keys *keys = _keys;
- const struct key_entry *ke;
- unsigned int keycode;
- int status;
- u16 event;
-
- /* For simplicity we ignore INPUT_COUNT and just read
- * events until we get the "queue empty" indicator.
- * Reading INPUT_LOW decrements the count.
- */
- for (;;) {
- status = dm355evm_msp_read(DM355EVM_MSP_INPUT_HIGH);
- if (status < 0) {
- dev_dbg(keys->dev, "input high err %d\n",
- status);
- break;
- }
- event = status << 8;
-
- status = dm355evm_msp_read(DM355EVM_MSP_INPUT_LOW);
- if (status < 0) {
- dev_dbg(keys->dev, "input low err %d\n",
- status);
- break;
- }
- event |= status;
- if (event == 0xdead)
- break;
-
- /* Press and release a button: two events, same code.
- * Press and hold (autorepeat), then release: N events
- * (N > 2), same code. For RC5 buttons the toggle bits
- * distinguish (for example) "1-autorepeat" from "1 1";
- * but PCB buttons don't support that bit.
- *
- * So we must synthesize release events. We do that by
- * mapping events to a press/release event pair; then
- * to avoid adding extra events, skip the second event
- * of each pair.
- */
- if (event == last_event) {
- last_event = 0;
- continue;
- }
- last_event = event;
-
- /* ignore the RC5 toggle bit */
- event &= ~0x0800;
-
- /* find the key, or report it as unknown */
- ke = sparse_keymap_entry_from_scancode(keys->input, event);
- keycode = ke ? ke->keycode : KEY_UNKNOWN;
- dev_dbg(keys->dev,
- "input event 0x%04x--> keycode %d\n",
- event, keycode);
-
- /* report press + release */
- input_report_key(keys->input, keycode, 1);
- input_sync(keys->input);
- input_report_key(keys->input, keycode, 0);
- input_sync(keys->input);
- }
-
- return IRQ_HANDLED;
-}
-
-/*----------------------------------------------------------------------*/
-
-static int dm355evm_keys_probe(struct platform_device *pdev)
-{
- struct dm355evm_keys *keys;
- struct input_dev *input;
- int irq;
- int error;
-
- keys = devm_kzalloc(&pdev->dev, sizeof (*keys), GFP_KERNEL);
- if (!keys)
- return -ENOMEM;
-
- input = devm_input_allocate_device(&pdev->dev);
- if (!input)
- return -ENOMEM;
-
- keys->dev = &pdev->dev;
- keys->input = input;
-
- input->name = "DM355 EVM Controls";
- input->phys = "dm355evm/input0";
-
- input->id.bustype = BUS_I2C;
- input->id.product = 0x0355;
- input->id.version = dm355evm_msp_read(DM355EVM_MSP_FIRMREV);
-
- error = sparse_keymap_setup(input, dm355evm_keys, NULL);
- if (error)
- return error;
-
- /* REVISIT: flush the event queue? */
-
- /* set up "threaded IRQ handler" */
- irq = platform_get_irq(pdev, 0);
- if (irq < 0)
- return irq;
-
- error = devm_request_threaded_irq(&pdev->dev, irq,
- NULL, dm355evm_keys_irq,
- IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
- dev_name(&pdev->dev), keys);
- if (error)
- return error;
-
- /* register */
- error = input_register_device(input);
- if (error)
- return error;
-
- return 0;
-}
-
-/* REVISIT: add suspend/resume when DaVinci supports it. The IRQ should
- * be able to wake up the system. When device_may_wakeup(&pdev->dev), call
- * enable_irq_wake() on suspend, and disable_irq_wake() on resume.
- */
-
-/*
- * I2C is used to talk to the MSP430, but this platform device is
- * exposed by an MFD driver that manages I2C communications.
- */
-static struct platform_driver dm355evm_keys_driver = {
- .probe = dm355evm_keys_probe,
- .driver = {
- .name = "dm355evm_keys",
- },
-};
-module_platform_driver(dm355evm_keys_driver);
-
-MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 11c3bd0bd669..31751cd3c4ed 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -1439,14 +1439,6 @@ config MFD_TI_AM335X_TSCADC
To compile this driver as a module, choose M here: the
module will be called ti_am335x_tscadc.
-config MFD_DM355EVM_MSP
- bool "TI DaVinci DM355 EVM microcontroller"
- depends on I2C=y && MACH_DAVINCI_DM355_EVM
- help
- This driver supports the MSP430 microcontroller used on these
- boards. MSP430 firmware manages resets and power sequencing,
- inputs from buttons and the IR remote, LEDs, an RTC, and more.
-
config MFD_LP3943
tristate "TI/National Semiconductor LP3943 MFD Driver"
depends on I2C
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index d74bf111f88e..a3a304f8c762 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -24,7 +24,6 @@ obj-$(CONFIG_MFD_TI_LP873X) += lp873x.o
obj-$(CONFIG_MFD_TI_LP87565) += lp87565.o
obj-$(CONFIG_MFD_DAVINCI_VOICECODEC) += davinci_voicecodec.o
-obj-$(CONFIG_MFD_DM355EVM_MSP) += dm355evm_msp.o
obj-$(CONFIG_MFD_TI_AM335X_TSCADC) += ti_am335x_tscadc.o
obj-$(CONFIG_MFD_STA2X11) += sta2x11-mfd.o
diff --git a/drivers/mfd/dm355evm_msp.c b/drivers/mfd/dm355evm_msp.c
deleted file mode 100644
index 759c59690680..000000000000
--- a/drivers/mfd/dm355evm_msp.c
+++ /dev/null
@@ -1,454 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * dm355evm_msp.c - driver for MSP430 firmware on DM355EVM board
- *
- * Copyright (C) 2008 David Brownell
- */
-
-#include <linux/init.h>
-#include <linux/mutex.h>
-#include <linux/platform_device.h>
-#include <linux/clk.h>
-#include <linux/module.h>
-#include <linux/err.h>
-#include <linux/gpio.h>
-#include <linux/gpio/machine.h>
-#include <linux/leds.h>
-#include <linux/i2c.h>
-#include <linux/mfd/dm355evm_msp.h>
-
-
-/*
- * The DM355 is a DaVinci chip with video support but no C64+ DSP. Its
- * EVM board has an MSP430 programmed with firmware for various board
- * support functions. This driver exposes some of them directly, and
- * supports other drivers (e.g. RTC, input) for more complex access.
- *
- * Because this firmware is entirely board-specific, this file embeds
- * knowledge that would be passed as platform_data in a generic driver.
- *
- * This driver was tested with firmware revision A4.
- */
-
-#if IS_ENABLED(CONFIG_INPUT_DM355EVM)
-#define msp_has_keyboard() true
-#else
-#define msp_has_keyboard() false
-#endif
-
-#if IS_ENABLED(CONFIG_LEDS_GPIO)
-#define msp_has_leds() true
-#else
-#define msp_has_leds() false
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_DM355EVM)
-#define msp_has_rtc() true
-#else
-#define msp_has_rtc() false
-#endif
-
-#if IS_ENABLED(CONFIG_VIDEO_TVP514X)
-#define msp_has_tvp() true
-#else
-#define msp_has_tvp() false
-#endif
-
-
-/*----------------------------------------------------------------------*/
-
-/* REVISIT for paranoia's sake, retry reads/writes on error */
-
-static struct i2c_client *msp430;
-
-/**
- * dm355evm_msp_write - Writes a register in dm355evm_msp
- * @value: the value to be written
- * @reg: register address
- *
- * Returns result of operation - 0 is success, else negative errno
- */
-int dm355evm_msp_write(u8 value, u8 reg)
-{
- return i2c_smbus_write_byte_data(msp430, reg, value);
-}
-EXPORT_SYMBOL(dm355evm_msp_write);
-
-/**
- * dm355evm_msp_read - Reads a register from dm355evm_msp
- * @reg: register address
- *
- * Returns result of operation - value, or negative errno
- */
-int dm355evm_msp_read(u8 reg)
-{
- return i2c_smbus_read_byte_data(msp430, reg);
-}
-EXPORT_SYMBOL(dm355evm_msp_read);
-
-/*----------------------------------------------------------------------*/
-
-/*
- * Many of the msp430 pins are just used as fixed-direction GPIOs.
- * We could export a few more of them this way, if we wanted.
- */
-#define MSP_GPIO(bit, reg) ((DM355EVM_MSP_ ## reg) << 3 | (bit))
-
-static const u8 msp_gpios[] = {
- /* eight leds */
- MSP_GPIO(0, LED), MSP_GPIO(1, LED),
- MSP_GPIO(2, LED), MSP_GPIO(3, LED),
- MSP_GPIO(4, LED), MSP_GPIO(5, LED),
- MSP_GPIO(6, LED), MSP_GPIO(7, LED),
- /* SW6 and the NTSC/nPAL jumper */
- MSP_GPIO(0, SWITCH1), MSP_GPIO(1, SWITCH1),
- MSP_GPIO(2, SWITCH1), MSP_GPIO(3, SWITCH1),
- MSP_GPIO(4, SWITCH1),
- /* switches on MMC/SD sockets */
- /*
- * Note: EVMDM355_ECP_VA4.pdf suggests that Bit 2 and 4 should be
- * checked for card detection. However on the EVM bit 1 and 3 gives
- * this status, for 0 and 1 instance respectively. The pdf also
- * suggests that Bit 1 and 3 should be checked for write protection.
- * However on the EVM bit 2 and 4 gives this status,for 0 and 1
- * instance respectively.
- */
- MSP_GPIO(2, SDMMC), MSP_GPIO(1, SDMMC), /* mmc0 WP, nCD */
- MSP_GPIO(4, SDMMC), MSP_GPIO(3, SDMMC), /* mmc1 WP, nCD */
-};
-
-static struct gpio_led evm_leds[] = {
- { .name = "dm355evm::ds14",
- .default_trigger = "heartbeat", },
- { .name = "dm355evm::ds15",
- .default_trigger = "mmc0", },
- { .name = "dm355evm::ds16",
- /* could also be a CE-ATA drive */
- .default_trigger = "mmc1", },
- { .name = "dm355evm::ds17",
- .default_trigger = "nand-disk", },
- { .name = "dm355evm::ds18", },
- { .name = "dm355evm::ds19", },
- { .name = "dm355evm::ds20", },
- { .name = "dm355evm::ds21", },
-};
-
-static struct gpio_led_platform_data evm_led_data = {
- .num_leds = ARRAY_SIZE(evm_leds),
- .leds = evm_leds,
-};
-
-static struct gpiod_lookup_table evm_leds_gpio_table = {
- .dev_id = "leds-gpio",
- .table = {
- /*
- * These GPIOs are on the dm355evm_msp
- * GPIO chip at index 0..7
- */
- GPIO_LOOKUP_IDX("dm355evm_msp", 0, NULL,
- 0, GPIO_ACTIVE_LOW),
- GPIO_LOOKUP_IDX("dm355evm_msp", 1, NULL,
- 1, GPIO_ACTIVE_LOW),
- GPIO_LOOKUP_IDX("dm355evm_msp", 2, NULL,
- 2, GPIO_ACTIVE_LOW),
- GPIO_LOOKUP_IDX("dm355evm_msp", 3, NULL,
- 3, GPIO_ACTIVE_LOW),
- GPIO_LOOKUP_IDX("dm355evm_msp", 4, NULL,
- 4, GPIO_ACTIVE_LOW),
- GPIO_LOOKUP_IDX("dm355evm_msp", 5, NULL,
- 5, GPIO_ACTIVE_LOW),
- GPIO_LOOKUP_IDX("dm355evm_msp", 6, NULL,
- 6, GPIO_ACTIVE_LOW),
- GPIO_LOOKUP_IDX("dm355evm_msp", 7, NULL,
- 7, GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-#define MSP_GPIO_REG(offset) (msp_gpios[(offset)] >> 3)
-#define MSP_GPIO_MASK(offset) BIT(msp_gpios[(offset)] & 0x07)
-
-static int msp_gpio_in(struct gpio_chip *chip, unsigned offset)
-{
- switch (MSP_GPIO_REG(offset)) {
- case DM355EVM_MSP_SWITCH1:
- case DM355EVM_MSP_SWITCH2:
- case DM355EVM_MSP_SDMMC:
- return 0;
- default:
- return -EINVAL;
- }
-}
-
-static u8 msp_led_cache;
-
-static int msp_gpio_get(struct gpio_chip *chip, unsigned offset)
-{
- int reg, status;
-
- reg = MSP_GPIO_REG(offset);
- status = dm355evm_msp_read(reg);
- if (status < 0)
- return status;
- if (reg == DM355EVM_MSP_LED)
- msp_led_cache = status;
- return !!(status & MSP_GPIO_MASK(offset));
-}
-
-static int msp_gpio_out(struct gpio_chip *chip, unsigned offset, int value)
-{
- int mask, bits;
-
- /* NOTE: there are some other signals that could be
- * packaged as output GPIOs, but they aren't as useful
- * as the LEDs ... so for now we don't.
- */
- if (MSP_GPIO_REG(offset) != DM355EVM_MSP_LED)
- return -EINVAL;
-
- mask = MSP_GPIO_MASK(offset);
- bits = msp_led_cache;
-
- bits &= ~mask;
- if (value)
- bits |= mask;
- msp_led_cache = bits;
-
- return dm355evm_msp_write(bits, DM355EVM_MSP_LED);
-}
-
-static void msp_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
-{
- msp_gpio_out(chip, offset, value);
-}
-
-static struct gpio_chip dm355evm_msp_gpio = {
- .label = "dm355evm_msp",
- .owner = THIS_MODULE,
- .direction_input = msp_gpio_in,
- .get = msp_gpio_get,
- .direction_output = msp_gpio_out,
- .set = msp_gpio_set,
- .base = -EINVAL, /* dynamic assignment */
- .ngpio = ARRAY_SIZE(msp_gpios),
- .can_sleep = true,
-};
-
-/*----------------------------------------------------------------------*/
-
-static struct device *add_child(struct i2c_client *client, const char *name,
- void *pdata, unsigned pdata_len,
- bool can_wakeup, int irq)
-{
- struct platform_device *pdev;
- int status;
-
- pdev = platform_device_alloc(name, -1);
- if (!pdev)
- return ERR_PTR(-ENOMEM);
-
- device_init_wakeup(&pdev->dev, can_wakeup);
- pdev->dev.parent = &client->dev;
-
- if (pdata) {
- status = platform_device_add_data(pdev, pdata, pdata_len);
- if (status < 0) {
- dev_dbg(&pdev->dev, "can't add platform_data\n");
- goto put_device;
- }
- }
-
- if (irq) {
- struct resource r = {
- .start = irq,
- .flags = IORESOURCE_IRQ,
- };
-
- status = platform_device_add_resources(pdev, &r, 1);
- if (status < 0) {
- dev_dbg(&pdev->dev, "can't add irq\n");
- goto put_device;
- }
- }
-
- status = platform_device_add(pdev);
- if (status)
- goto put_device;
-
- return &pdev->dev;
-
-put_device:
- platform_device_put(pdev);
- dev_err(&client->dev, "failed to add device %s\n", name);
- return ERR_PTR(status);
-}
-
-static int add_children(struct i2c_client *client)
-{
- static const struct {
- int offset;
- char *label;
- } config_inputs[] = {
- /* 8 == right after the LEDs */
- { 8 + 0, "sw6_1", },
- { 8 + 1, "sw6_2", },
- { 8 + 2, "sw6_3", },
- { 8 + 3, "sw6_4", },
- { 8 + 4, "NTSC/nPAL", },
- };
-
- struct device *child;
- int status;
- int i;
-
- /* GPIO-ish stuff */
- dm355evm_msp_gpio.parent = &client->dev;
- status = gpiochip_add_data(&dm355evm_msp_gpio, NULL);
- if (status < 0)
- return status;
-
- /* LED output */
- if (msp_has_leds()) {
- gpiod_add_lookup_table(&evm_leds_gpio_table);
- /* NOTE: these are the only fully programmable LEDs
- * on the board, since GPIO-61/ds22 (and many signals
- * going to DC7) must be used for AEMIF address lines
- * unless the top 1 GB of NAND is unused...
- */
- child = add_child(client, "leds-gpio",
- &evm_led_data, sizeof(evm_led_data),
- false, 0);
- if (IS_ERR(child))
- return PTR_ERR(child);
- }
-
- /* configuration inputs */
- for (i = 0; i < ARRAY_SIZE(config_inputs); i++) {
- int gpio = dm355evm_msp_gpio.base + config_inputs[i].offset;
-
- gpio_request_one(gpio, GPIOF_IN, config_inputs[i].label);
-
- /* make it easy for userspace to see these */
- gpio_export(gpio, false);
- }
-
- /* MMC/SD inputs -- right after the last config input */
- if (dev_get_platdata(&client->dev)) {
- void (*mmcsd_setup)(unsigned) = dev_get_platdata(&client->dev);
-
- mmcsd_setup(dm355evm_msp_gpio.base + 8 + 5);
- }
-
- /* RTC is a 32 bit counter, no alarm */
- if (msp_has_rtc()) {
- child = add_child(client, "rtc-dm355evm",
- NULL, 0, false, 0);
- if (IS_ERR(child))
- return PTR_ERR(child);
- }
-
- /* input from buttons and IR remote (uses the IRQ) */
- if (msp_has_keyboard()) {
- child = add_child(client, "dm355evm_keys",
- NULL, 0, true, client->irq);
- if (IS_ERR(child))
- return PTR_ERR(child);
- }
-
- return 0;
-}
-
-/*----------------------------------------------------------------------*/
-
-static void dm355evm_command(unsigned command)
-{
- int status;
-
- status = dm355evm_msp_write(command, DM355EVM_MSP_COMMAND);
- if (status < 0)
- dev_err(&msp430->dev, "command %d failure %d\n",
- command, status);
-}
-
-static void dm355evm_power_off(void)
-{
- dm355evm_command(MSP_COMMAND_POWEROFF);
-}
-
-static void dm355evm_msp_remove(struct i2c_client *client)
-{
- pm_power_off = NULL;
- msp430 = NULL;
-}
-
-static int
-dm355evm_msp_probe(struct i2c_client *client, const struct i2c_device_id *id)
-{
- int status;
- const char *video = msp_has_tvp() ? "TVP5146" : "imager";
-
- if (msp430)
- return -EBUSY;
- msp430 = client;
-
- /* display revision status; doubles as sanity check */
- status = dm355evm_msp_read(DM355EVM_MSP_FIRMREV);
- if (status < 0)
- goto fail;
- dev_info(&client->dev, "firmware v.%02X, %s as video-in\n",
- status, video);
-
- /* mux video input: either tvp5146 or some external imager */
- status = dm355evm_msp_write(msp_has_tvp() ? 0 : MSP_VIDEO_IMAGER,
- DM355EVM_MSP_VIDEO_IN);
- if (status < 0)
- dev_warn(&client->dev, "error %d muxing %s as video-in\n",
- status, video);
-
- /* init LED cache, and turn off the LEDs */
- msp_led_cache = 0xff;
- dm355evm_msp_write(msp_led_cache, DM355EVM_MSP_LED);
-
- /* export capabilities we support */
- status = add_children(client);
- if (status < 0)
- goto fail;
-
- /* PM hookup */
- pm_power_off = dm355evm_power_off;
-
- return 0;
-
-fail:
- /* FIXME remove children ... */
- dm355evm_msp_remove(client);
- return status;
-}
-
-static const struct i2c_device_id dm355evm_msp_ids[] = {
- { "dm355evm_msp", 0 },
- { /* end of list */ },
-};
-MODULE_DEVICE_TABLE(i2c, dm355evm_msp_ids);
-
-static struct i2c_driver dm355evm_msp_driver = {
- .driver.name = "dm355evm_msp",
- .id_table = dm355evm_msp_ids,
- .probe = dm355evm_msp_probe,
- .remove = dm355evm_msp_remove,
-};
-
-static int __init dm355evm_msp_init(void)
-{
- return i2c_add_driver(&dm355evm_msp_driver);
-}
-subsys_initcall(dm355evm_msp_init);
-
-static void __exit dm355evm_msp_exit(void)
-{
- i2c_del_driver(&dm355evm_msp_driver);
-}
-module_exit(dm355evm_msp_exit);
-
-MODULE_DESCRIPTION("Interface to MSP430 firmware on DM355EVM");
-MODULE_LICENSE("GPL");
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index bb63edb507da..35298c651730 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -540,12 +540,6 @@ config RTC_DRV_BQ32K
This driver can also be built as a module. If so, the module
will be called rtc-bq32k.
-config RTC_DRV_DM355EVM
- tristate "TI DaVinci DM355 EVM RTC"
- depends on MFD_DM355EVM_MSP
- help
- Supports the RTC firmware in the MSP430 on the DM355 EVM.
-
config RTC_DRV_TWL92330
bool "TI TWL92330/Menelaus"
depends on MENELAUS
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index aab22bc63432..c2d474985919 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -46,7 +46,6 @@ obj-$(CONFIG_RTC_DRV_DA9055) += rtc-da9055.o
obj-$(CONFIG_RTC_DRV_DA9063) += rtc-da9063.o
obj-$(CONFIG_RTC_DRV_DAVINCI) += rtc-davinci.o
obj-$(CONFIG_RTC_DRV_DIGICOLOR) += rtc-digicolor.o
-obj-$(CONFIG_RTC_DRV_DM355EVM) += rtc-dm355evm.o
obj-$(CONFIG_RTC_DRV_DS1216) += rtc-ds1216.o
obj-$(CONFIG_RTC_DRV_DS1286) += rtc-ds1286.o
obj-$(CONFIG_RTC_DRV_DS1302) += rtc-ds1302.o
diff --git a/drivers/rtc/rtc-dm355evm.c b/drivers/rtc/rtc-dm355evm.c
deleted file mode 100644
index 94fb16ac3e0f..000000000000
--- a/drivers/rtc/rtc-dm355evm.c
+++ /dev/null
@@ -1,151 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * rtc-dm355evm.c - access battery-backed counter in MSP430 firmware
- *
- * Copyright (c) 2008 by David Brownell
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/rtc.h>
-#include <linux/platform_device.h>
-
-#include <linux/mfd/dm355evm_msp.h>
-#include <linux/module.h>
-
-
-/*
- * The MSP430 firmware on the DM355 EVM uses a watch crystal to feed
- * a 1 Hz counter. When a backup battery is supplied, that makes a
- * reasonable RTC for applications where alarms and non-NTP drift
- * compensation aren't important.
- *
- * The only real glitch is the inability to read or write all four
- * counter bytes atomically: the count may increment in the middle
- * of an operation, causing trouble when the LSB rolls over.
- *
- * This driver was tested with firmware revision A4.
- */
-union evm_time {
- u8 bytes[4];
- u32 value;
-};
-
-static int dm355evm_rtc_read_time(struct device *dev, struct rtc_time *tm)
-{
- union evm_time time;
- int status;
- int tries = 0;
-
- do {
- /*
- * Read LSB(0) to MSB(3) bytes. Defend against the counter
- * rolling over by re-reading until the value is stable,
- * and assuming the four reads take at most a few seconds.
- */
- status = dm355evm_msp_read(DM355EVM_MSP_RTC_0);
- if (status < 0)
- return status;
- if (tries && time.bytes[0] == status)
- break;
- time.bytes[0] = status;
-
- status = dm355evm_msp_read(DM355EVM_MSP_RTC_1);
- if (status < 0)
- return status;
- if (tries && time.bytes[1] == status)
- break;
- time.bytes[1] = status;
-
- status = dm355evm_msp_read(DM355EVM_MSP_RTC_2);
- if (status < 0)
- return status;
- if (tries && time.bytes[2] == status)
- break;
- time.bytes[2] = status;
-
- status = dm355evm_msp_read(DM355EVM_MSP_RTC_3);
- if (status < 0)
- return status;
- if (tries && time.bytes[3] == status)
- break;
- time.bytes[3] = status;
-
- } while (++tries < 5);
-
- dev_dbg(dev, "read timestamp %08x\n", time.value);
-
- rtc_time64_to_tm(le32_to_cpu(time.value), tm);
- return 0;
-}
-
-static int dm355evm_rtc_set_time(struct device *dev, struct rtc_time *tm)
-{
- union evm_time time;
- unsigned long value;
- int status;
-
- value = rtc_tm_to_time64(tm);
- time.value = cpu_to_le32(value);
-
- dev_dbg(dev, "write timestamp %08x\n", time.value);
-
- /*
- * REVISIT handle non-atomic writes ... maybe just retry until
- * byte[1] sticks (no rollover)?
- */
- status = dm355evm_msp_write(time.bytes[0], DM355EVM_MSP_RTC_0);
- if (status < 0)
- return status;
-
- status = dm355evm_msp_write(time.bytes[1], DM355EVM_MSP_RTC_1);
- if (status < 0)
- return status;
-
- status = dm355evm_msp_write(time.bytes[2], DM355EVM_MSP_RTC_2);
- if (status < 0)
- return status;
-
- status = dm355evm_msp_write(time.bytes[3], DM355EVM_MSP_RTC_3);
- if (status < 0)
- return status;
-
- return 0;
-}
-
-static const struct rtc_class_ops dm355evm_rtc_ops = {
- .read_time = dm355evm_rtc_read_time,
- .set_time = dm355evm_rtc_set_time,
-};
-
-/*----------------------------------------------------------------------*/
-
-static int dm355evm_rtc_probe(struct platform_device *pdev)
-{
- struct rtc_device *rtc;
-
- rtc = devm_rtc_allocate_device(&pdev->dev);
- if (IS_ERR(rtc))
- return PTR_ERR(rtc);
-
- platform_set_drvdata(pdev, rtc);
-
- rtc->ops = &dm355evm_rtc_ops;
- rtc->range_max = U32_MAX;
-
- return devm_rtc_register_device(rtc);
-}
-
-/*
- * I2C is used to talk to the MSP430, but this platform device is
- * exposed by an MFD driver that manages I2C communications.
- */
-static struct platform_driver rtc_dm355evm_driver = {
- .probe = dm355evm_rtc_probe,
- .driver = {
- .name = "rtc-dm355evm",
- },
-};
-
-module_platform_driver(rtc_dm355evm_driver);
-
-MODULE_LICENSE("GPL");
diff --git a/include/linux/mfd/dm355evm_msp.h b/include/linux/mfd/dm355evm_msp.h
deleted file mode 100644
index 372470350fab..000000000000
--- a/include/linux/mfd/dm355evm_msp.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * dm355evm_msp.h - support MSP430 microcontroller on DM355EVM board
- */
-#ifndef __LINUX_I2C_DM355EVM_MSP
-#define __LINUX_I2C_DM355EVM_MSP
-
-/*
- * Written against Spectrum's writeup for the A4 firmware revision,
- * and tweaked to match source and rev D2 schematics by removing CPLD
- * and NOR flash hooks (which were last appropriate in rev B boards).
- *
- * Note that the firmware supports a flavor of write posting ... to be
- * sure a write completes, issue another read or write.
- */
-
-/* utilities to access "registers" emulated by msp430 firmware */
-extern int dm355evm_msp_write(u8 value, u8 reg);
-extern int dm355evm_msp_read(u8 reg);
-
-
-/* command/control registers */
-#define DM355EVM_MSP_COMMAND 0x00
-# define MSP_COMMAND_NULL 0
-# define MSP_COMMAND_RESET_COLD 1
-# define MSP_COMMAND_RESET_WARM 2
-# define MSP_COMMAND_RESET_WARM_I 3
-# define MSP_COMMAND_POWEROFF 4
-# define MSP_COMMAND_IR_REINIT 5
-#define DM355EVM_MSP_STATUS 0x01
-# define MSP_STATUS_BAD_OFFSET BIT(0)
-# define MSP_STATUS_BAD_COMMAND BIT(1)
-# define MSP_STATUS_POWER_ERROR BIT(2)
-# define MSP_STATUS_RXBUF_OVERRUN BIT(3)
-#define DM355EVM_MSP_RESET 0x02 /* 0 bits == in reset */
-# define MSP_RESET_DC5 BIT(0)
-# define MSP_RESET_TVP5154 BIT(2)
-# define MSP_RESET_IMAGER BIT(3)
-# define MSP_RESET_ETHERNET BIT(4)
-# define MSP_RESET_SYS BIT(5)
-# define MSP_RESET_AIC33 BIT(7)
-
-/* GPIO registers ... bit patterns mostly match the source MSP ports */
-#define DM355EVM_MSP_LED 0x03 /* active low (MSP P4) */
-#define DM355EVM_MSP_SWITCH1 0x04 /* (MSP P5, masked) */
-# define MSP_SWITCH1_SW6_1 BIT(0)
-# define MSP_SWITCH1_SW6_2 BIT(1)
-# define MSP_SWITCH1_SW6_3 BIT(2)
-# define MSP_SWITCH1_SW6_4 BIT(3)
-# define MSP_SWITCH1_J1 BIT(4) /* NTSC/PAL */
-# define MSP_SWITCH1_MSP_INT BIT(5) /* active low */
-#define DM355EVM_MSP_SWITCH2 0x05 /* (MSP P6, masked) */
-# define MSP_SWITCH2_SW10 BIT(3)
-# define MSP_SWITCH2_SW11 BIT(4)
-# define MSP_SWITCH2_SW12 BIT(5)
-# define MSP_SWITCH2_SW13 BIT(6)
-# define MSP_SWITCH2_SW14 BIT(7)
-#define DM355EVM_MSP_SDMMC 0x06 /* (MSP P2, masked) */
-# define MSP_SDMMC_0_WP BIT(1)
-# define MSP_SDMMC_0_CD BIT(2) /* active low */
-# define MSP_SDMMC_1_WP BIT(3)
-# define MSP_SDMMC_1_CD BIT(4) /* active low */
-#define DM355EVM_MSP_FIRMREV 0x07 /* not a GPIO (out of order) */
-#define DM355EVM_MSP_VIDEO_IN 0x08 /* (MSP P3, masked) */
-# define MSP_VIDEO_IMAGER BIT(7) /* low == tvp5146 */
-
-/* power supply registers are currently omitted */
-
-/* RTC registers */
-#define DM355EVM_MSP_RTC_0 0x12 /* LSB */
-#define DM355EVM_MSP_RTC_1 0x13
-#define DM355EVM_MSP_RTC_2 0x14
-#define DM355EVM_MSP_RTC_3 0x15 /* MSB */
-
-/* input event queue registers; code == ((HIGH << 8) | LOW) */
-#define DM355EVM_MSP_INPUT_COUNT 0x16 /* decrement by reading LOW */
-#define DM355EVM_MSP_INPUT_HIGH 0x17
-#define DM355EVM_MSP_INPUT_LOW 0x18
-
-#endif /* __LINUX_I2C_DM355EVM_MSP */
--
2.29.2
^ permalink raw reply related [flat|nested] 48+ messages in thread* Re: [PATCH 06/14] mfd: remove dm355evm_msp driver
2022-10-19 15:29 ` [PATCH 06/14] mfd: remove dm355evm_msp driver Arnd Bergmann
@ 2022-10-20 11:35 ` Bartosz Golaszewski
2022-10-31 15:01 ` Lee Jones
1 sibling, 0 replies; 48+ messages in thread
From: Bartosz Golaszewski @ 2022-10-20 11:35 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Sekhar Nori, linux-arm-kernel, Lee Jones, linux-kernel,
Kevin Hilman, Arnd Bergmann, Dmitry Torokhov, Alessandro Zummo,
Alexandre Belloni, linux-input, linux-rtc
On Wed, Oct 19, 2022 at 5:35 PM Arnd Bergmann <arnd@kernel.org> wrote:
>
> From: Arnd Bergmann <arnd@arndb.de>
>
> The DaVinci DM355EVM platform is gone after the removal of all
> unused board files, so the MTD device along with its sub-devices
> can be removed as well.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 06/14] mfd: remove dm355evm_msp driver
2022-10-19 15:29 ` [PATCH 06/14] mfd: remove dm355evm_msp driver Arnd Bergmann
2022-10-20 11:35 ` Bartosz Golaszewski
@ 2022-10-31 15:01 ` Lee Jones
2022-10-31 15:01 ` Lee Jones
1 sibling, 1 reply; 48+ messages in thread
From: Lee Jones @ 2022-10-31 15:01 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Sekhar Nori, Bartosz Golaszewski, linux-arm-kernel, linux-kernel,
Kevin Hilman, Arnd Bergmann, Dmitry Torokhov, Alessandro Zummo,
Alexandre Belloni, linux-input, linux-rtc
On Wed, 19 Oct 2022, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> The DaVinci DM355EVM platform is gone after the removal of all
> unused board files, so the MTD device along with its sub-devices
> can be removed as well.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
> drivers/input/misc/Kconfig | 11 -
> drivers/input/misc/Makefile | 1 -
> drivers/input/misc/dm355evm_keys.c | 238 ---------------
> drivers/mfd/Kconfig | 8 -
> drivers/mfd/Makefile | 1 -
> drivers/mfd/dm355evm_msp.c | 454 -----------------------------
> drivers/rtc/Kconfig | 6 -
> drivers/rtc/Makefile | 1 -
> drivers/rtc/rtc-dm355evm.c | 151 ----------
> include/linux/mfd/dm355evm_msp.h | 79 -----
> 10 files changed, 950 deletions(-)
> delete mode 100644 drivers/input/misc/dm355evm_keys.c
> delete mode 100644 drivers/mfd/dm355evm_msp.c
> delete mode 100644 drivers/rtc/rtc-dm355evm.c
> delete mode 100644 include/linux/mfd/dm355evm_msp.h
Acked-by: Lee Jones <lee@kernel.org>
--
Lee Jones [李琼斯]
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 06/14] mfd: remove dm355evm_msp driver
2022-10-31 15:01 ` Lee Jones
@ 2022-10-31 15:01 ` Lee Jones
0 siblings, 0 replies; 48+ messages in thread
From: Lee Jones @ 2022-10-31 15:01 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Sekhar Nori, Bartosz Golaszewski, linux-arm-kernel, linux-kernel,
Kevin Hilman, Arnd Bergmann, Dmitry Torokhov, Alessandro Zummo,
Alexandre Belloni, linux-input, linux-rtc
On Mon, 31 Oct 2022, Lee Jones wrote:
> On Wed, 19 Oct 2022, Arnd Bergmann wrote:
>
> > From: Arnd Bergmann <arnd@arndb.de>
> >
> > The DaVinci DM355EVM platform is gone after the removal of all
> > unused board files, so the MTD device along with its sub-devices
> > can be removed as well.
> >
> > Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> > ---
> > drivers/input/misc/Kconfig | 11 -
> > drivers/input/misc/Makefile | 1 -
> > drivers/input/misc/dm355evm_keys.c | 238 ---------------
> > drivers/mfd/Kconfig | 8 -
> > drivers/mfd/Makefile | 1 -
> > drivers/mfd/dm355evm_msp.c | 454 -----------------------------
> > drivers/rtc/Kconfig | 6 -
> > drivers/rtc/Makefile | 1 -
> > drivers/rtc/rtc-dm355evm.c | 151 ----------
> > include/linux/mfd/dm355evm_msp.h | 79 -----
> > 10 files changed, 950 deletions(-)
> > delete mode 100644 drivers/input/misc/dm355evm_keys.c
> > delete mode 100644 drivers/mfd/dm355evm_msp.c
> > delete mode 100644 drivers/rtc/rtc-dm355evm.c
> > delete mode 100644 include/linux/mfd/dm355evm_msp.h
>
> Acked-by: Lee Jones <lee@kernel.org>
Any reason not to do this per-subsystem?
--
Lee Jones [李琼斯]
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH 07/14] input: remove davinci keyboard driver
2022-10-19 15:29 [PATCH 00/14] ARM: remove unused davinci board & drivers Arnd Bergmann
` (5 preceding siblings ...)
2022-10-19 15:29 ` [PATCH 06/14] mfd: remove dm355evm_msp driver Arnd Bergmann
@ 2022-10-19 15:29 ` Arnd Bergmann
2022-10-20 8:02 ` Mattijs Korpershoek
2022-10-20 11:17 ` Bartosz Golaszewski
2022-10-19 15:29 ` [PATCH 08/14] rtc: remove davinci rtc driver Arnd Bergmann
` (9 subsequent siblings)
16 siblings, 2 replies; 48+ messages in thread
From: Arnd Bergmann @ 2022-10-19 15:29 UTC (permalink / raw)
To: Sekhar Nori, Bartosz Golaszewski, linux-arm-kernel, Dmitry Torokhov
Cc: linux-kernel, Kevin Hilman, Arnd Bergmann, Andy Shevchenko,
Mattijs Korpershoek, linux-input
From: Arnd Bergmann <arnd@arndb.de>
The dm365evm board was removed, and no other users of this
device exist.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
drivers/input/keyboard/Kconfig | 10 -
drivers/input/keyboard/Makefile | 1 -
drivers/input/keyboard/davinci_keyscan.c | 315 -----------------------
3 files changed, 326 deletions(-)
delete mode 100644 drivers/input/keyboard/davinci_keyscan.c
diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
index 00292118b79b..957cc6728f4c 100644
--- a/drivers/input/keyboard/Kconfig
+++ b/drivers/input/keyboard/Kconfig
@@ -657,16 +657,6 @@ config KEYBOARD_SUN4I_LRADC
To compile this driver as a module, choose M here: the
module will be called sun4i-lradc-keys.
-config KEYBOARD_DAVINCI
- tristate "TI DaVinci Key Scan"
- depends on ARCH_DAVINCI_DM365
- help
- Say Y to enable keypad module support for the TI DaVinci
- platforms (DM365).
-
- To compile this driver as a module, choose M here: the
- module will be called davinci_keyscan.
-
config KEYBOARD_IPAQ_MICRO
tristate "Buttons on Micro SoC (iPaq h3100,h3600,h3700)"
depends on MFD_IPAQ_MICRO
diff --git a/drivers/input/keyboard/Makefile b/drivers/input/keyboard/Makefile
index 5f67196bb2c1..5ccfdf5c0222 100644
--- a/drivers/input/keyboard/Makefile
+++ b/drivers/input/keyboard/Makefile
@@ -18,7 +18,6 @@ obj-$(CONFIG_KEYBOARD_CAP11XX) += cap11xx.o
obj-$(CONFIG_KEYBOARD_CLPS711X) += clps711x-keypad.o
obj-$(CONFIG_KEYBOARD_CROS_EC) += cros_ec_keyb.o
obj-$(CONFIG_KEYBOARD_CYPRESS_SF) += cypress-sf.o
-obj-$(CONFIG_KEYBOARD_DAVINCI) += davinci_keyscan.o
obj-$(CONFIG_KEYBOARD_DLINK_DIR685) += dlink-dir685-touchkeys.o
obj-$(CONFIG_KEYBOARD_EP93XX) += ep93xx_keypad.o
obj-$(CONFIG_KEYBOARD_GOLDFISH_EVENTS) += goldfish_events.o
diff --git a/drivers/input/keyboard/davinci_keyscan.c b/drivers/input/keyboard/davinci_keyscan.c
deleted file mode 100644
index f489cd585b33..000000000000
--- a/drivers/input/keyboard/davinci_keyscan.c
+++ /dev/null
@@ -1,315 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * DaVinci Key Scan Driver for TI platforms
- *
- * Copyright (C) 2009 Texas Instruments, Inc
- *
- * Author: Miguel Aguilar <miguel.aguilar@ridgerun.com>
- *
- * Initial Code: Sandeep Paulraj <s-paulraj@ti.com>
- */
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/types.h>
-#include <linux/input.h>
-#include <linux/kernel.h>
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/errno.h>
-#include <linux/slab.h>
-
-#include <linux/platform_data/keyscan-davinci.h>
-
-/* Key scan registers */
-#define DAVINCI_KEYSCAN_KEYCTRL 0x0000
-#define DAVINCI_KEYSCAN_INTENA 0x0004
-#define DAVINCI_KEYSCAN_INTFLAG 0x0008
-#define DAVINCI_KEYSCAN_INTCLR 0x000c
-#define DAVINCI_KEYSCAN_STRBWIDTH 0x0010
-#define DAVINCI_KEYSCAN_INTERVAL 0x0014
-#define DAVINCI_KEYSCAN_CONTTIME 0x0018
-#define DAVINCI_KEYSCAN_CURRENTST 0x001c
-#define DAVINCI_KEYSCAN_PREVSTATE 0x0020
-#define DAVINCI_KEYSCAN_EMUCTRL 0x0024
-#define DAVINCI_KEYSCAN_IODFTCTRL 0x002c
-
-/* Key Control Register (KEYCTRL) */
-#define DAVINCI_KEYSCAN_KEYEN 0x00000001
-#define DAVINCI_KEYSCAN_PREVMODE 0x00000002
-#define DAVINCI_KEYSCAN_CHATOFF 0x00000004
-#define DAVINCI_KEYSCAN_AUTODET 0x00000008
-#define DAVINCI_KEYSCAN_SCANMODE 0x00000010
-#define DAVINCI_KEYSCAN_OUTTYPE 0x00000020
-
-/* Masks for the interrupts */
-#define DAVINCI_KEYSCAN_INT_CONT 0x00000008
-#define DAVINCI_KEYSCAN_INT_OFF 0x00000004
-#define DAVINCI_KEYSCAN_INT_ON 0x00000002
-#define DAVINCI_KEYSCAN_INT_CHANGE 0x00000001
-#define DAVINCI_KEYSCAN_INT_ALL 0x0000000f
-
-struct davinci_ks {
- struct input_dev *input;
- struct davinci_ks_platform_data *pdata;
- int irq;
- void __iomem *base;
- resource_size_t pbase;
- size_t base_size;
- unsigned short keymap[];
-};
-
-/* Initializing the kp Module */
-static int __init davinci_ks_initialize(struct davinci_ks *davinci_ks)
-{
- struct device *dev = &davinci_ks->input->dev;
- struct davinci_ks_platform_data *pdata = davinci_ks->pdata;
- u32 matrix_ctrl;
-
- /* Enable all interrupts */
- __raw_writel(DAVINCI_KEYSCAN_INT_ALL,
- davinci_ks->base + DAVINCI_KEYSCAN_INTENA);
-
- /* Clear interrupts if any */
- __raw_writel(DAVINCI_KEYSCAN_INT_ALL,
- davinci_ks->base + DAVINCI_KEYSCAN_INTCLR);
-
- /* Setup the scan period = strobe + interval */
- __raw_writel(pdata->strobe,
- davinci_ks->base + DAVINCI_KEYSCAN_STRBWIDTH);
- __raw_writel(pdata->interval,
- davinci_ks->base + DAVINCI_KEYSCAN_INTERVAL);
- __raw_writel(0x01,
- davinci_ks->base + DAVINCI_KEYSCAN_CONTTIME);
-
- /* Define matrix type */
- switch (pdata->matrix_type) {
- case DAVINCI_KEYSCAN_MATRIX_4X4:
- matrix_ctrl = 0;
- break;
- case DAVINCI_KEYSCAN_MATRIX_5X3:
- matrix_ctrl = (1 << 6);
- break;
- default:
- dev_err(dev->parent, "wrong matrix type\n");
- return -EINVAL;
- }
-
- /* Enable key scan module and set matrix type */
- __raw_writel(DAVINCI_KEYSCAN_AUTODET | DAVINCI_KEYSCAN_KEYEN |
- matrix_ctrl, davinci_ks->base + DAVINCI_KEYSCAN_KEYCTRL);
-
- return 0;
-}
-
-static irqreturn_t davinci_ks_interrupt(int irq, void *dev_id)
-{
- struct davinci_ks *davinci_ks = dev_id;
- struct device *dev = &davinci_ks->input->dev;
- unsigned short *keymap = davinci_ks->keymap;
- int keymapsize = davinci_ks->pdata->keymapsize;
- u32 prev_status, new_status, changed;
- bool release;
- int keycode = KEY_UNKNOWN;
- int i;
-
- /* Disable interrupt */
- __raw_writel(0x0, davinci_ks->base + DAVINCI_KEYSCAN_INTENA);
-
- /* Reading previous and new status of the key scan */
- prev_status = __raw_readl(davinci_ks->base + DAVINCI_KEYSCAN_PREVSTATE);
- new_status = __raw_readl(davinci_ks->base + DAVINCI_KEYSCAN_CURRENTST);
-
- changed = prev_status ^ new_status;
-
- if (changed) {
- /*
- * It goes through all bits in 'changed' to ensure
- * that no key changes are being missed
- */
- for (i = 0 ; i < keymapsize; i++) {
- if ((changed>>i) & 0x1) {
- keycode = keymap[i];
- release = (new_status >> i) & 0x1;
- dev_dbg(dev->parent, "key %d %s\n", keycode,
- release ? "released" : "pressed");
- input_report_key(davinci_ks->input, keycode,
- !release);
- input_sync(davinci_ks->input);
- }
- }
- /* Clearing interrupt */
- __raw_writel(DAVINCI_KEYSCAN_INT_ALL,
- davinci_ks->base + DAVINCI_KEYSCAN_INTCLR);
- }
-
- /* Enable interrupts */
- __raw_writel(0x1, davinci_ks->base + DAVINCI_KEYSCAN_INTENA);
-
- return IRQ_HANDLED;
-}
-
-static int __init davinci_ks_probe(struct platform_device *pdev)
-{
- struct davinci_ks *davinci_ks;
- struct input_dev *key_dev;
- struct resource *res, *mem;
- struct device *dev = &pdev->dev;
- struct davinci_ks_platform_data *pdata = dev_get_platdata(dev);
- int error, i;
-
- if (pdata->device_enable) {
- error = pdata->device_enable(dev);
- if (error < 0) {
- dev_dbg(dev, "device enable function failed\n");
- return error;
- }
- }
-
- if (!pdata->keymap) {
- dev_dbg(dev, "no keymap from pdata\n");
- return -EINVAL;
- }
-
- davinci_ks = kzalloc(sizeof(struct davinci_ks) +
- sizeof(unsigned short) * pdata->keymapsize, GFP_KERNEL);
- if (!davinci_ks) {
- dev_dbg(dev, "could not allocate memory for private data\n");
- return -ENOMEM;
- }
-
- memcpy(davinci_ks->keymap, pdata->keymap,
- sizeof(unsigned short) * pdata->keymapsize);
-
- key_dev = input_allocate_device();
- if (!key_dev) {
- dev_dbg(dev, "could not allocate input device\n");
- error = -ENOMEM;
- goto fail1;
- }
-
- davinci_ks->input = key_dev;
-
- davinci_ks->irq = platform_get_irq(pdev, 0);
- if (davinci_ks->irq < 0) {
- error = davinci_ks->irq;
- goto fail2;
- }
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!res) {
- dev_err(dev, "no mem resource\n");
- error = -EINVAL;
- goto fail2;
- }
-
- davinci_ks->pbase = res->start;
- davinci_ks->base_size = resource_size(res);
-
- mem = request_mem_region(davinci_ks->pbase, davinci_ks->base_size,
- pdev->name);
- if (!mem) {
- dev_err(dev, "key scan registers at %08x are not free\n",
- davinci_ks->pbase);
- error = -EBUSY;
- goto fail2;
- }
-
- davinci_ks->base = ioremap(davinci_ks->pbase, davinci_ks->base_size);
- if (!davinci_ks->base) {
- dev_err(dev, "can't ioremap MEM resource.\n");
- error = -ENOMEM;
- goto fail3;
- }
-
- /* Enable auto repeat feature of Linux input subsystem */
- if (pdata->rep)
- __set_bit(EV_REP, key_dev->evbit);
-
- /* Setup input device */
- __set_bit(EV_KEY, key_dev->evbit);
-
- /* Setup the platform data */
- davinci_ks->pdata = pdata;
-
- for (i = 0; i < davinci_ks->pdata->keymapsize; i++)
- __set_bit(davinci_ks->pdata->keymap[i], key_dev->keybit);
-
- key_dev->name = "davinci_keyscan";
- key_dev->phys = "davinci_keyscan/input0";
- key_dev->dev.parent = dev;
- key_dev->id.bustype = BUS_HOST;
- key_dev->id.vendor = 0x0001;
- key_dev->id.product = 0x0001;
- key_dev->id.version = 0x0001;
- key_dev->keycode = davinci_ks->keymap;
- key_dev->keycodesize = sizeof(davinci_ks->keymap[0]);
- key_dev->keycodemax = davinci_ks->pdata->keymapsize;
-
- error = input_register_device(davinci_ks->input);
- if (error < 0) {
- dev_err(dev, "unable to register davinci key scan device\n");
- goto fail4;
- }
-
- error = request_irq(davinci_ks->irq, davinci_ks_interrupt,
- 0, pdev->name, davinci_ks);
- if (error < 0) {
- dev_err(dev, "unable to register davinci key scan interrupt\n");
- goto fail5;
- }
-
- error = davinci_ks_initialize(davinci_ks);
- if (error < 0) {
- dev_err(dev, "unable to initialize davinci key scan device\n");
- goto fail6;
- }
-
- platform_set_drvdata(pdev, davinci_ks);
- return 0;
-
-fail6:
- free_irq(davinci_ks->irq, davinci_ks);
-fail5:
- input_unregister_device(davinci_ks->input);
- key_dev = NULL;
-fail4:
- iounmap(davinci_ks->base);
-fail3:
- release_mem_region(davinci_ks->pbase, davinci_ks->base_size);
-fail2:
- input_free_device(key_dev);
-fail1:
- kfree(davinci_ks);
-
- return error;
-}
-
-static int davinci_ks_remove(struct platform_device *pdev)
-{
- struct davinci_ks *davinci_ks = platform_get_drvdata(pdev);
-
- free_irq(davinci_ks->irq, davinci_ks);
-
- input_unregister_device(davinci_ks->input);
-
- iounmap(davinci_ks->base);
- release_mem_region(davinci_ks->pbase, davinci_ks->base_size);
-
- kfree(davinci_ks);
-
- return 0;
-}
-
-static struct platform_driver davinci_ks_driver = {
- .driver = {
- .name = "davinci_keyscan",
- },
- .remove = davinci_ks_remove,
-};
-
-module_platform_driver_probe(davinci_ks_driver, davinci_ks_probe);
-
-MODULE_AUTHOR("Miguel Aguilar");
-MODULE_DESCRIPTION("Texas Instruments DaVinci Key Scan Driver");
-MODULE_LICENSE("GPL");
--
2.29.2
^ permalink raw reply related [flat|nested] 48+ messages in thread* Re: [PATCH 07/14] input: remove davinci keyboard driver
2022-10-19 15:29 ` [PATCH 07/14] input: remove davinci keyboard driver Arnd Bergmann
@ 2022-10-20 8:02 ` Mattijs Korpershoek
2022-10-20 11:17 ` Bartosz Golaszewski
1 sibling, 0 replies; 48+ messages in thread
From: Mattijs Korpershoek @ 2022-10-20 8:02 UTC (permalink / raw)
To: Arnd Bergmann, Sekhar Nori, Bartosz Golaszewski,
linux-arm-kernel, Dmitry Torokhov
Cc: linux-kernel, Kevin Hilman, Arnd Bergmann, Andy Shevchenko, linux-input
On Wed, Oct 19, 2022 at 17:29, Arnd Bergmann <arnd@kernel.org> wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> The dm365evm board was removed, and no other users of this
> device exist.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
> ---
> drivers/input/keyboard/Kconfig | 10 -
> drivers/input/keyboard/Makefile | 1 -
> drivers/input/keyboard/davinci_keyscan.c | 315 -----------------------
> 3 files changed, 326 deletions(-)
> delete mode 100644 drivers/input/keyboard/davinci_keyscan.c
>
> diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
> index 00292118b79b..957cc6728f4c 100644
> --- a/drivers/input/keyboard/Kconfig
> +++ b/drivers/input/keyboard/Kconfig
> @@ -657,16 +657,6 @@ config KEYBOARD_SUN4I_LRADC
> To compile this driver as a module, choose M here: the
> module will be called sun4i-lradc-keys.
>
> -config KEYBOARD_DAVINCI
> - tristate "TI DaVinci Key Scan"
> - depends on ARCH_DAVINCI_DM365
> - help
> - Say Y to enable keypad module support for the TI DaVinci
> - platforms (DM365).
> -
> - To compile this driver as a module, choose M here: the
> - module will be called davinci_keyscan.
> -
> config KEYBOARD_IPAQ_MICRO
> tristate "Buttons on Micro SoC (iPaq h3100,h3600,h3700)"
> depends on MFD_IPAQ_MICRO
> diff --git a/drivers/input/keyboard/Makefile b/drivers/input/keyboard/Makefile
> index 5f67196bb2c1..5ccfdf5c0222 100644
> --- a/drivers/input/keyboard/Makefile
> +++ b/drivers/input/keyboard/Makefile
> @@ -18,7 +18,6 @@ obj-$(CONFIG_KEYBOARD_CAP11XX) += cap11xx.o
> obj-$(CONFIG_KEYBOARD_CLPS711X) += clps711x-keypad.o
> obj-$(CONFIG_KEYBOARD_CROS_EC) += cros_ec_keyb.o
> obj-$(CONFIG_KEYBOARD_CYPRESS_SF) += cypress-sf.o
> -obj-$(CONFIG_KEYBOARD_DAVINCI) += davinci_keyscan.o
> obj-$(CONFIG_KEYBOARD_DLINK_DIR685) += dlink-dir685-touchkeys.o
> obj-$(CONFIG_KEYBOARD_EP93XX) += ep93xx_keypad.o
> obj-$(CONFIG_KEYBOARD_GOLDFISH_EVENTS) += goldfish_events.o
> diff --git a/drivers/input/keyboard/davinci_keyscan.c b/drivers/input/keyboard/davinci_keyscan.c
> deleted file mode 100644
> index f489cd585b33..000000000000
> --- a/drivers/input/keyboard/davinci_keyscan.c
> +++ /dev/null
> @@ -1,315 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-or-later
> -/*
> - * DaVinci Key Scan Driver for TI platforms
> - *
> - * Copyright (C) 2009 Texas Instruments, Inc
> - *
> - * Author: Miguel Aguilar <miguel.aguilar@ridgerun.com>
> - *
> - * Initial Code: Sandeep Paulraj <s-paulraj@ti.com>
> - */
> -#include <linux/module.h>
> -#include <linux/init.h>
> -#include <linux/interrupt.h>
> -#include <linux/types.h>
> -#include <linux/input.h>
> -#include <linux/kernel.h>
> -#include <linux/delay.h>
> -#include <linux/platform_device.h>
> -#include <linux/errno.h>
> -#include <linux/slab.h>
> -
> -#include <linux/platform_data/keyscan-davinci.h>
> -
> -/* Key scan registers */
> -#define DAVINCI_KEYSCAN_KEYCTRL 0x0000
> -#define DAVINCI_KEYSCAN_INTENA 0x0004
> -#define DAVINCI_KEYSCAN_INTFLAG 0x0008
> -#define DAVINCI_KEYSCAN_INTCLR 0x000c
> -#define DAVINCI_KEYSCAN_STRBWIDTH 0x0010
> -#define DAVINCI_KEYSCAN_INTERVAL 0x0014
> -#define DAVINCI_KEYSCAN_CONTTIME 0x0018
> -#define DAVINCI_KEYSCAN_CURRENTST 0x001c
> -#define DAVINCI_KEYSCAN_PREVSTATE 0x0020
> -#define DAVINCI_KEYSCAN_EMUCTRL 0x0024
> -#define DAVINCI_KEYSCAN_IODFTCTRL 0x002c
> -
> -/* Key Control Register (KEYCTRL) */
> -#define DAVINCI_KEYSCAN_KEYEN 0x00000001
> -#define DAVINCI_KEYSCAN_PREVMODE 0x00000002
> -#define DAVINCI_KEYSCAN_CHATOFF 0x00000004
> -#define DAVINCI_KEYSCAN_AUTODET 0x00000008
> -#define DAVINCI_KEYSCAN_SCANMODE 0x00000010
> -#define DAVINCI_KEYSCAN_OUTTYPE 0x00000020
> -
> -/* Masks for the interrupts */
> -#define DAVINCI_KEYSCAN_INT_CONT 0x00000008
> -#define DAVINCI_KEYSCAN_INT_OFF 0x00000004
> -#define DAVINCI_KEYSCAN_INT_ON 0x00000002
> -#define DAVINCI_KEYSCAN_INT_CHANGE 0x00000001
> -#define DAVINCI_KEYSCAN_INT_ALL 0x0000000f
> -
> -struct davinci_ks {
> - struct input_dev *input;
> - struct davinci_ks_platform_data *pdata;
> - int irq;
> - void __iomem *base;
> - resource_size_t pbase;
> - size_t base_size;
> - unsigned short keymap[];
> -};
> -
> -/* Initializing the kp Module */
> -static int __init davinci_ks_initialize(struct davinci_ks *davinci_ks)
> -{
> - struct device *dev = &davinci_ks->input->dev;
> - struct davinci_ks_platform_data *pdata = davinci_ks->pdata;
> - u32 matrix_ctrl;
> -
> - /* Enable all interrupts */
> - __raw_writel(DAVINCI_KEYSCAN_INT_ALL,
> - davinci_ks->base + DAVINCI_KEYSCAN_INTENA);
> -
> - /* Clear interrupts if any */
> - __raw_writel(DAVINCI_KEYSCAN_INT_ALL,
> - davinci_ks->base + DAVINCI_KEYSCAN_INTCLR);
> -
> - /* Setup the scan period = strobe + interval */
> - __raw_writel(pdata->strobe,
> - davinci_ks->base + DAVINCI_KEYSCAN_STRBWIDTH);
> - __raw_writel(pdata->interval,
> - davinci_ks->base + DAVINCI_KEYSCAN_INTERVAL);
> - __raw_writel(0x01,
> - davinci_ks->base + DAVINCI_KEYSCAN_CONTTIME);
> -
> - /* Define matrix type */
> - switch (pdata->matrix_type) {
> - case DAVINCI_KEYSCAN_MATRIX_4X4:
> - matrix_ctrl = 0;
> - break;
> - case DAVINCI_KEYSCAN_MATRIX_5X3:
> - matrix_ctrl = (1 << 6);
> - break;
> - default:
> - dev_err(dev->parent, "wrong matrix type\n");
> - return -EINVAL;
> - }
> -
> - /* Enable key scan module and set matrix type */
> - __raw_writel(DAVINCI_KEYSCAN_AUTODET | DAVINCI_KEYSCAN_KEYEN |
> - matrix_ctrl, davinci_ks->base + DAVINCI_KEYSCAN_KEYCTRL);
> -
> - return 0;
> -}
> -
> -static irqreturn_t davinci_ks_interrupt(int irq, void *dev_id)
> -{
> - struct davinci_ks *davinci_ks = dev_id;
> - struct device *dev = &davinci_ks->input->dev;
> - unsigned short *keymap = davinci_ks->keymap;
> - int keymapsize = davinci_ks->pdata->keymapsize;
> - u32 prev_status, new_status, changed;
> - bool release;
> - int keycode = KEY_UNKNOWN;
> - int i;
> -
> - /* Disable interrupt */
> - __raw_writel(0x0, davinci_ks->base + DAVINCI_KEYSCAN_INTENA);
> -
> - /* Reading previous and new status of the key scan */
> - prev_status = __raw_readl(davinci_ks->base + DAVINCI_KEYSCAN_PREVSTATE);
> - new_status = __raw_readl(davinci_ks->base + DAVINCI_KEYSCAN_CURRENTST);
> -
> - changed = prev_status ^ new_status;
> -
> - if (changed) {
> - /*
> - * It goes through all bits in 'changed' to ensure
> - * that no key changes are being missed
> - */
> - for (i = 0 ; i < keymapsize; i++) {
> - if ((changed>>i) & 0x1) {
> - keycode = keymap[i];
> - release = (new_status >> i) & 0x1;
> - dev_dbg(dev->parent, "key %d %s\n", keycode,
> - release ? "released" : "pressed");
> - input_report_key(davinci_ks->input, keycode,
> - !release);
> - input_sync(davinci_ks->input);
> - }
> - }
> - /* Clearing interrupt */
> - __raw_writel(DAVINCI_KEYSCAN_INT_ALL,
> - davinci_ks->base + DAVINCI_KEYSCAN_INTCLR);
> - }
> -
> - /* Enable interrupts */
> - __raw_writel(0x1, davinci_ks->base + DAVINCI_KEYSCAN_INTENA);
> -
> - return IRQ_HANDLED;
> -}
> -
> -static int __init davinci_ks_probe(struct platform_device *pdev)
> -{
> - struct davinci_ks *davinci_ks;
> - struct input_dev *key_dev;
> - struct resource *res, *mem;
> - struct device *dev = &pdev->dev;
> - struct davinci_ks_platform_data *pdata = dev_get_platdata(dev);
> - int error, i;
> -
> - if (pdata->device_enable) {
> - error = pdata->device_enable(dev);
> - if (error < 0) {
> - dev_dbg(dev, "device enable function failed\n");
> - return error;
> - }
> - }
> -
> - if (!pdata->keymap) {
> - dev_dbg(dev, "no keymap from pdata\n");
> - return -EINVAL;
> - }
> -
> - davinci_ks = kzalloc(sizeof(struct davinci_ks) +
> - sizeof(unsigned short) * pdata->keymapsize, GFP_KERNEL);
> - if (!davinci_ks) {
> - dev_dbg(dev, "could not allocate memory for private data\n");
> - return -ENOMEM;
> - }
> -
> - memcpy(davinci_ks->keymap, pdata->keymap,
> - sizeof(unsigned short) * pdata->keymapsize);
> -
> - key_dev = input_allocate_device();
> - if (!key_dev) {
> - dev_dbg(dev, "could not allocate input device\n");
> - error = -ENOMEM;
> - goto fail1;
> - }
> -
> - davinci_ks->input = key_dev;
> -
> - davinci_ks->irq = platform_get_irq(pdev, 0);
> - if (davinci_ks->irq < 0) {
> - error = davinci_ks->irq;
> - goto fail2;
> - }
> -
> - res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> - if (!res) {
> - dev_err(dev, "no mem resource\n");
> - error = -EINVAL;
> - goto fail2;
> - }
> -
> - davinci_ks->pbase = res->start;
> - davinci_ks->base_size = resource_size(res);
> -
> - mem = request_mem_region(davinci_ks->pbase, davinci_ks->base_size,
> - pdev->name);
> - if (!mem) {
> - dev_err(dev, "key scan registers at %08x are not free\n",
> - davinci_ks->pbase);
> - error = -EBUSY;
> - goto fail2;
> - }
> -
> - davinci_ks->base = ioremap(davinci_ks->pbase, davinci_ks->base_size);
> - if (!davinci_ks->base) {
> - dev_err(dev, "can't ioremap MEM resource.\n");
> - error = -ENOMEM;
> - goto fail3;
> - }
> -
> - /* Enable auto repeat feature of Linux input subsystem */
> - if (pdata->rep)
> - __set_bit(EV_REP, key_dev->evbit);
> -
> - /* Setup input device */
> - __set_bit(EV_KEY, key_dev->evbit);
> -
> - /* Setup the platform data */
> - davinci_ks->pdata = pdata;
> -
> - for (i = 0; i < davinci_ks->pdata->keymapsize; i++)
> - __set_bit(davinci_ks->pdata->keymap[i], key_dev->keybit);
> -
> - key_dev->name = "davinci_keyscan";
> - key_dev->phys = "davinci_keyscan/input0";
> - key_dev->dev.parent = dev;
> - key_dev->id.bustype = BUS_HOST;
> - key_dev->id.vendor = 0x0001;
> - key_dev->id.product = 0x0001;
> - key_dev->id.version = 0x0001;
> - key_dev->keycode = davinci_ks->keymap;
> - key_dev->keycodesize = sizeof(davinci_ks->keymap[0]);
> - key_dev->keycodemax = davinci_ks->pdata->keymapsize;
> -
> - error = input_register_device(davinci_ks->input);
> - if (error < 0) {
> - dev_err(dev, "unable to register davinci key scan device\n");
> - goto fail4;
> - }
> -
> - error = request_irq(davinci_ks->irq, davinci_ks_interrupt,
> - 0, pdev->name, davinci_ks);
> - if (error < 0) {
> - dev_err(dev, "unable to register davinci key scan interrupt\n");
> - goto fail5;
> - }
> -
> - error = davinci_ks_initialize(davinci_ks);
> - if (error < 0) {
> - dev_err(dev, "unable to initialize davinci key scan device\n");
> - goto fail6;
> - }
> -
> - platform_set_drvdata(pdev, davinci_ks);
> - return 0;
> -
> -fail6:
> - free_irq(davinci_ks->irq, davinci_ks);
> -fail5:
> - input_unregister_device(davinci_ks->input);
> - key_dev = NULL;
> -fail4:
> - iounmap(davinci_ks->base);
> -fail3:
> - release_mem_region(davinci_ks->pbase, davinci_ks->base_size);
> -fail2:
> - input_free_device(key_dev);
> -fail1:
> - kfree(davinci_ks);
> -
> - return error;
> -}
> -
> -static int davinci_ks_remove(struct platform_device *pdev)
> -{
> - struct davinci_ks *davinci_ks = platform_get_drvdata(pdev);
> -
> - free_irq(davinci_ks->irq, davinci_ks);
> -
> - input_unregister_device(davinci_ks->input);
> -
> - iounmap(davinci_ks->base);
> - release_mem_region(davinci_ks->pbase, davinci_ks->base_size);
> -
> - kfree(davinci_ks);
> -
> - return 0;
> -}
> -
> -static struct platform_driver davinci_ks_driver = {
> - .driver = {
> - .name = "davinci_keyscan",
> - },
> - .remove = davinci_ks_remove,
> -};
> -
> -module_platform_driver_probe(davinci_ks_driver, davinci_ks_probe);
> -
> -MODULE_AUTHOR("Miguel Aguilar");
> -MODULE_DESCRIPTION("Texas Instruments DaVinci Key Scan Driver");
> -MODULE_LICENSE("GPL");
> --
> 2.29.2
^ permalink raw reply [flat|nested] 48+ messages in thread* Re: [PATCH 07/14] input: remove davinci keyboard driver
2022-10-19 15:29 ` [PATCH 07/14] input: remove davinci keyboard driver Arnd Bergmann
2022-10-20 8:02 ` Mattijs Korpershoek
@ 2022-10-20 11:17 ` Bartosz Golaszewski
1 sibling, 0 replies; 48+ messages in thread
From: Bartosz Golaszewski @ 2022-10-20 11:17 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Sekhar Nori, linux-arm-kernel, Dmitry Torokhov, linux-kernel,
Kevin Hilman, Arnd Bergmann, Andy Shevchenko,
Mattijs Korpershoek, linux-input
On Wed, Oct 19, 2022 at 5:36 PM Arnd Bergmann <arnd@kernel.org> wrote:
>
> From: Arnd Bergmann <arnd@arndb.de>
>
> The dm365evm board was removed, and no other users of this
> device exist.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH 08/14] rtc: remove davinci rtc driver
2022-10-19 15:29 [PATCH 00/14] ARM: remove unused davinci board & drivers Arnd Bergmann
` (6 preceding siblings ...)
2022-10-19 15:29 ` [PATCH 07/14] input: remove davinci keyboard driver Arnd Bergmann
@ 2022-10-19 15:29 ` Arnd Bergmann
2022-10-20 11:35 ` Bartosz Golaszewski
2022-10-19 15:29 ` [PATCH 09/14] ASoC: remove unused davinci support Arnd Bergmann
` (8 subsequent siblings)
16 siblings, 1 reply; 48+ messages in thread
From: Arnd Bergmann @ 2022-10-19 15:29 UTC (permalink / raw)
To: Sekhar Nori, Bartosz Golaszewski, linux-arm-kernel,
Alessandro Zummo, Alexandre Belloni
Cc: linux-kernel, Kevin Hilman, Arnd Bergmann, linux-rtc
From: Arnd Bergmann <arnd@arndb.de>
The Davinci dm365 SoC support was removed, so the rtc driver
has no remaining users.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
drivers/rtc/Kconfig | 10 -
drivers/rtc/Makefile | 1 -
drivers/rtc/rtc-davinci.c | 512 --------------------------------------
3 files changed, 523 deletions(-)
delete mode 100644 drivers/rtc/rtc-davinci.c
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 35298c651730..ab9a1f814119 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -1345,16 +1345,6 @@ config RTC_DRV_ASM9260
This driver can also be built as a module. If so, the module
will be called rtc-asm9260.
-config RTC_DRV_DAVINCI
- tristate "TI DaVinci RTC"
- depends on ARCH_DAVINCI_DM365 || COMPILE_TEST
- help
- If you say yes here you get support for the RTC on the
- DaVinci platforms (DM365).
-
- This driver can also be built as a module. If so, the module
- will be called rtc-davinci.
-
config RTC_DRV_DIGICOLOR
tristate "Conexant Digicolor RTC"
depends on ARCH_DIGICOLOR || COMPILE_TEST
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index c2d474985919..d3c042dcbc73 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -44,7 +44,6 @@ obj-$(CONFIG_RTC_DRV_CROS_EC) += rtc-cros-ec.o
obj-$(CONFIG_RTC_DRV_DA9052) += rtc-da9052.o
obj-$(CONFIG_RTC_DRV_DA9055) += rtc-da9055.o
obj-$(CONFIG_RTC_DRV_DA9063) += rtc-da9063.o
-obj-$(CONFIG_RTC_DRV_DAVINCI) += rtc-davinci.o
obj-$(CONFIG_RTC_DRV_DIGICOLOR) += rtc-digicolor.o
obj-$(CONFIG_RTC_DRV_DS1216) += rtc-ds1216.o
obj-$(CONFIG_RTC_DRV_DS1286) += rtc-ds1286.o
diff --git a/drivers/rtc/rtc-davinci.c b/drivers/rtc/rtc-davinci.c
deleted file mode 100644
index 6bef0f2353da..000000000000
--- a/drivers/rtc/rtc-davinci.c
+++ /dev/null
@@ -1,512 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * DaVinci Power Management and Real Time Clock Driver for TI platforms
- *
- * Copyright (C) 2009 Texas Instruments, Inc
- *
- * Author: Miguel Aguilar <miguel.aguilar@ridgerun.com>
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/ioport.h>
-#include <linux/delay.h>
-#include <linux/spinlock.h>
-#include <linux/rtc.h>
-#include <linux/bcd.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-
-/*
- * The DaVinci RTC is a simple RTC with the following
- * Sec: 0 - 59 : BCD count
- * Min: 0 - 59 : BCD count
- * Hour: 0 - 23 : BCD count
- * Day: 0 - 0x7FFF(32767) : Binary count ( Over 89 years )
- */
-
-/* PRTC interface registers */
-#define DAVINCI_PRTCIF_PID 0x00
-#define PRTCIF_CTLR 0x04
-#define PRTCIF_LDATA 0x08
-#define PRTCIF_UDATA 0x0C
-#define PRTCIF_INTEN 0x10
-#define PRTCIF_INTFLG 0x14
-
-/* PRTCIF_CTLR bit fields */
-#define PRTCIF_CTLR_BUSY BIT(31)
-#define PRTCIF_CTLR_SIZE BIT(25)
-#define PRTCIF_CTLR_DIR BIT(24)
-#define PRTCIF_CTLR_BENU_MSB BIT(23)
-#define PRTCIF_CTLR_BENU_3RD_BYTE BIT(22)
-#define PRTCIF_CTLR_BENU_2ND_BYTE BIT(21)
-#define PRTCIF_CTLR_BENU_LSB BIT(20)
-#define PRTCIF_CTLR_BENU_MASK (0x00F00000)
-#define PRTCIF_CTLR_BENL_MSB BIT(19)
-#define PRTCIF_CTLR_BENL_3RD_BYTE BIT(18)
-#define PRTCIF_CTLR_BENL_2ND_BYTE BIT(17)
-#define PRTCIF_CTLR_BENL_LSB BIT(16)
-#define PRTCIF_CTLR_BENL_MASK (0x000F0000)
-
-/* PRTCIF_INTEN bit fields */
-#define PRTCIF_INTEN_RTCSS BIT(1)
-#define PRTCIF_INTEN_RTCIF BIT(0)
-#define PRTCIF_INTEN_MASK (PRTCIF_INTEN_RTCSS \
- | PRTCIF_INTEN_RTCIF)
-
-/* PRTCIF_INTFLG bit fields */
-#define PRTCIF_INTFLG_RTCSS BIT(1)
-#define PRTCIF_INTFLG_RTCIF BIT(0)
-#define PRTCIF_INTFLG_MASK (PRTCIF_INTFLG_RTCSS \
- | PRTCIF_INTFLG_RTCIF)
-
-/* PRTC subsystem registers */
-#define PRTCSS_RTC_INTC_EXTENA1 (0x0C)
-#define PRTCSS_RTC_CTRL (0x10)
-#define PRTCSS_RTC_WDT (0x11)
-#define PRTCSS_RTC_TMR0 (0x12)
-#define PRTCSS_RTC_TMR1 (0x13)
-#define PRTCSS_RTC_CCTRL (0x14)
-#define PRTCSS_RTC_SEC (0x15)
-#define PRTCSS_RTC_MIN (0x16)
-#define PRTCSS_RTC_HOUR (0x17)
-#define PRTCSS_RTC_DAY0 (0x18)
-#define PRTCSS_RTC_DAY1 (0x19)
-#define PRTCSS_RTC_AMIN (0x1A)
-#define PRTCSS_RTC_AHOUR (0x1B)
-#define PRTCSS_RTC_ADAY0 (0x1C)
-#define PRTCSS_RTC_ADAY1 (0x1D)
-#define PRTCSS_RTC_CLKC_CNT (0x20)
-
-/* PRTCSS_RTC_INTC_EXTENA1 */
-#define PRTCSS_RTC_INTC_EXTENA1_MASK (0x07)
-
-/* PRTCSS_RTC_CTRL bit fields */
-#define PRTCSS_RTC_CTRL_WDTBUS BIT(7)
-#define PRTCSS_RTC_CTRL_WEN BIT(6)
-#define PRTCSS_RTC_CTRL_WDRT BIT(5)
-#define PRTCSS_RTC_CTRL_WDTFLG BIT(4)
-#define PRTCSS_RTC_CTRL_TE BIT(3)
-#define PRTCSS_RTC_CTRL_TIEN BIT(2)
-#define PRTCSS_RTC_CTRL_TMRFLG BIT(1)
-#define PRTCSS_RTC_CTRL_TMMD BIT(0)
-
-/* PRTCSS_RTC_CCTRL bit fields */
-#define PRTCSS_RTC_CCTRL_CALBUSY BIT(7)
-#define PRTCSS_RTC_CCTRL_DAEN BIT(5)
-#define PRTCSS_RTC_CCTRL_HAEN BIT(4)
-#define PRTCSS_RTC_CCTRL_MAEN BIT(3)
-#define PRTCSS_RTC_CCTRL_ALMFLG BIT(2)
-#define PRTCSS_RTC_CCTRL_AIEN BIT(1)
-#define PRTCSS_RTC_CCTRL_CAEN BIT(0)
-
-static DEFINE_SPINLOCK(davinci_rtc_lock);
-
-struct davinci_rtc {
- struct rtc_device *rtc;
- void __iomem *base;
- int irq;
-};
-
-static inline void rtcif_write(struct davinci_rtc *davinci_rtc,
- u32 val, u32 addr)
-{
- writel(val, davinci_rtc->base + addr);
-}
-
-static inline u32 rtcif_read(struct davinci_rtc *davinci_rtc, u32 addr)
-{
- return readl(davinci_rtc->base + addr);
-}
-
-static inline void rtcif_wait(struct davinci_rtc *davinci_rtc)
-{
- while (rtcif_read(davinci_rtc, PRTCIF_CTLR) & PRTCIF_CTLR_BUSY)
- cpu_relax();
-}
-
-static inline void rtcss_write(struct davinci_rtc *davinci_rtc,
- unsigned long val, u8 addr)
-{
- rtcif_wait(davinci_rtc);
-
- rtcif_write(davinci_rtc, PRTCIF_CTLR_BENL_LSB | addr, PRTCIF_CTLR);
- rtcif_write(davinci_rtc, val, PRTCIF_LDATA);
-
- rtcif_wait(davinci_rtc);
-}
-
-static inline u8 rtcss_read(struct davinci_rtc *davinci_rtc, u8 addr)
-{
- rtcif_wait(davinci_rtc);
-
- rtcif_write(davinci_rtc, PRTCIF_CTLR_DIR | PRTCIF_CTLR_BENL_LSB | addr,
- PRTCIF_CTLR);
-
- rtcif_wait(davinci_rtc);
-
- return rtcif_read(davinci_rtc, PRTCIF_LDATA);
-}
-
-static inline void davinci_rtcss_calendar_wait(struct davinci_rtc *davinci_rtc)
-{
- while (rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL) &
- PRTCSS_RTC_CCTRL_CALBUSY)
- cpu_relax();
-}
-
-static irqreturn_t davinci_rtc_interrupt(int irq, void *class_dev)
-{
- struct davinci_rtc *davinci_rtc = class_dev;
- unsigned long events = 0;
- u32 irq_flg;
- u8 alm_irq, tmr_irq;
- u8 rtc_ctrl, rtc_cctrl;
- int ret = IRQ_NONE;
-
- irq_flg = rtcif_read(davinci_rtc, PRTCIF_INTFLG) &
- PRTCIF_INTFLG_RTCSS;
-
- alm_irq = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL) &
- PRTCSS_RTC_CCTRL_ALMFLG;
-
- tmr_irq = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL) &
- PRTCSS_RTC_CTRL_TMRFLG;
-
- if (irq_flg) {
- if (alm_irq) {
- events |= RTC_IRQF | RTC_AF;
- rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
- rtc_cctrl |= PRTCSS_RTC_CCTRL_ALMFLG;
- rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
- } else if (tmr_irq) {
- events |= RTC_IRQF | RTC_PF;
- rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
- rtc_ctrl |= PRTCSS_RTC_CTRL_TMRFLG;
- rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
- }
-
- rtcif_write(davinci_rtc, PRTCIF_INTFLG_RTCSS,
- PRTCIF_INTFLG);
- rtc_update_irq(davinci_rtc->rtc, 1, events);
-
- ret = IRQ_HANDLED;
- }
-
- return ret;
-}
-
-static int
-davinci_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
-{
- struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
- u8 rtc_ctrl;
- unsigned long flags;
- int ret = 0;
-
- spin_lock_irqsave(&davinci_rtc_lock, flags);
-
- rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
-
- switch (cmd) {
- case RTC_WIE_ON:
- rtc_ctrl |= PRTCSS_RTC_CTRL_WEN | PRTCSS_RTC_CTRL_WDTFLG;
- break;
- case RTC_WIE_OFF:
- rtc_ctrl &= ~PRTCSS_RTC_CTRL_WEN;
- break;
- default:
- ret = -ENOIOCTLCMD;
- }
-
- rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
-
- spin_unlock_irqrestore(&davinci_rtc_lock, flags);
-
- return ret;
-}
-
-static void convertfromdays(u16 days, struct rtc_time *tm)
-{
- int tmp_days, year, mon;
-
- for (year = 2000;; year++) {
- tmp_days = rtc_year_days(1, 12, year);
- if (days >= tmp_days)
- days -= tmp_days;
- else {
- for (mon = 0;; mon++) {
- tmp_days = rtc_month_days(mon, year);
- if (days >= tmp_days) {
- days -= tmp_days;
- } else {
- tm->tm_year = year - 1900;
- tm->tm_mon = mon;
- tm->tm_mday = days + 1;
- break;
- }
- }
- break;
- }
- }
-}
-
-static void convert2days(u16 *days, struct rtc_time *tm)
-{
- int i;
- *days = 0;
-
- for (i = 2000; i < 1900 + tm->tm_year; i++)
- *days += rtc_year_days(1, 12, i);
-
- *days += rtc_year_days(tm->tm_mday, tm->tm_mon, 1900 + tm->tm_year);
-}
-
-static int davinci_rtc_read_time(struct device *dev, struct rtc_time *tm)
-{
- struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
- u16 days = 0;
- u8 day0, day1;
- unsigned long flags;
-
- spin_lock_irqsave(&davinci_rtc_lock, flags);
-
- davinci_rtcss_calendar_wait(davinci_rtc);
- tm->tm_sec = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_SEC));
-
- davinci_rtcss_calendar_wait(davinci_rtc);
- tm->tm_min = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_MIN));
-
- davinci_rtcss_calendar_wait(davinci_rtc);
- tm->tm_hour = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_HOUR));
-
- davinci_rtcss_calendar_wait(davinci_rtc);
- day0 = rtcss_read(davinci_rtc, PRTCSS_RTC_DAY0);
-
- davinci_rtcss_calendar_wait(davinci_rtc);
- day1 = rtcss_read(davinci_rtc, PRTCSS_RTC_DAY1);
-
- spin_unlock_irqrestore(&davinci_rtc_lock, flags);
-
- days |= day1;
- days <<= 8;
- days |= day0;
-
- convertfromdays(days, tm);
-
- return 0;
-}
-
-static int davinci_rtc_set_time(struct device *dev, struct rtc_time *tm)
-{
- struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
- u16 days;
- u8 rtc_cctrl;
- unsigned long flags;
-
- convert2days(&days, tm);
-
- spin_lock_irqsave(&davinci_rtc_lock, flags);
-
- davinci_rtcss_calendar_wait(davinci_rtc);
- rtcss_write(davinci_rtc, bin2bcd(tm->tm_sec), PRTCSS_RTC_SEC);
-
- davinci_rtcss_calendar_wait(davinci_rtc);
- rtcss_write(davinci_rtc, bin2bcd(tm->tm_min), PRTCSS_RTC_MIN);
-
- davinci_rtcss_calendar_wait(davinci_rtc);
- rtcss_write(davinci_rtc, bin2bcd(tm->tm_hour), PRTCSS_RTC_HOUR);
-
- davinci_rtcss_calendar_wait(davinci_rtc);
- rtcss_write(davinci_rtc, days & 0xFF, PRTCSS_RTC_DAY0);
-
- davinci_rtcss_calendar_wait(davinci_rtc);
- rtcss_write(davinci_rtc, (days & 0xFF00) >> 8, PRTCSS_RTC_DAY1);
-
- rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
- rtc_cctrl |= PRTCSS_RTC_CCTRL_CAEN;
- rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
-
- spin_unlock_irqrestore(&davinci_rtc_lock, flags);
-
- return 0;
-}
-
-static int davinci_rtc_alarm_irq_enable(struct device *dev,
- unsigned int enabled)
-{
- struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
- unsigned long flags;
- u8 rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
-
- spin_lock_irqsave(&davinci_rtc_lock, flags);
-
- if (enabled)
- rtc_cctrl |= PRTCSS_RTC_CCTRL_DAEN |
- PRTCSS_RTC_CCTRL_HAEN |
- PRTCSS_RTC_CCTRL_MAEN |
- PRTCSS_RTC_CCTRL_ALMFLG |
- PRTCSS_RTC_CCTRL_AIEN;
- else
- rtc_cctrl &= ~PRTCSS_RTC_CCTRL_AIEN;
-
- davinci_rtcss_calendar_wait(davinci_rtc);
- rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
-
- spin_unlock_irqrestore(&davinci_rtc_lock, flags);
-
- return 0;
-}
-
-static int davinci_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
-{
- struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
- u16 days = 0;
- u8 day0, day1;
- unsigned long flags;
-
- alm->time.tm_sec = 0;
-
- spin_lock_irqsave(&davinci_rtc_lock, flags);
-
- davinci_rtcss_calendar_wait(davinci_rtc);
- alm->time.tm_min = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_AMIN));
-
- davinci_rtcss_calendar_wait(davinci_rtc);
- alm->time.tm_hour = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_AHOUR));
-
- davinci_rtcss_calendar_wait(davinci_rtc);
- day0 = rtcss_read(davinci_rtc, PRTCSS_RTC_ADAY0);
-
- davinci_rtcss_calendar_wait(davinci_rtc);
- day1 = rtcss_read(davinci_rtc, PRTCSS_RTC_ADAY1);
-
- spin_unlock_irqrestore(&davinci_rtc_lock, flags);
- days |= day1;
- days <<= 8;
- days |= day0;
-
- convertfromdays(days, &alm->time);
-
- alm->pending = !!(rtcss_read(davinci_rtc,
- PRTCSS_RTC_CCTRL) &
- PRTCSS_RTC_CCTRL_AIEN);
- alm->enabled = alm->pending && device_may_wakeup(dev);
-
- return 0;
-}
-
-static int davinci_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
-{
- struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
- unsigned long flags;
- u16 days;
-
- convert2days(&days, &alm->time);
-
- spin_lock_irqsave(&davinci_rtc_lock, flags);
-
- davinci_rtcss_calendar_wait(davinci_rtc);
- rtcss_write(davinci_rtc, bin2bcd(alm->time.tm_min), PRTCSS_RTC_AMIN);
-
- davinci_rtcss_calendar_wait(davinci_rtc);
- rtcss_write(davinci_rtc, bin2bcd(alm->time.tm_hour), PRTCSS_RTC_AHOUR);
-
- davinci_rtcss_calendar_wait(davinci_rtc);
- rtcss_write(davinci_rtc, days & 0xFF, PRTCSS_RTC_ADAY0);
-
- davinci_rtcss_calendar_wait(davinci_rtc);
- rtcss_write(davinci_rtc, (days & 0xFF00) >> 8, PRTCSS_RTC_ADAY1);
-
- spin_unlock_irqrestore(&davinci_rtc_lock, flags);
-
- return 0;
-}
-
-static const struct rtc_class_ops davinci_rtc_ops = {
- .ioctl = davinci_rtc_ioctl,
- .read_time = davinci_rtc_read_time,
- .set_time = davinci_rtc_set_time,
- .alarm_irq_enable = davinci_rtc_alarm_irq_enable,
- .read_alarm = davinci_rtc_read_alarm,
- .set_alarm = davinci_rtc_set_alarm,
-};
-
-static int __init davinci_rtc_probe(struct platform_device *pdev)
-{
- struct device *dev = &pdev->dev;
- struct davinci_rtc *davinci_rtc;
- int ret = 0;
-
- davinci_rtc = devm_kzalloc(&pdev->dev, sizeof(struct davinci_rtc), GFP_KERNEL);
- if (!davinci_rtc)
- return -ENOMEM;
-
- davinci_rtc->irq = platform_get_irq(pdev, 0);
- if (davinci_rtc->irq < 0)
- return davinci_rtc->irq;
-
- davinci_rtc->base = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(davinci_rtc->base))
- return PTR_ERR(davinci_rtc->base);
-
- platform_set_drvdata(pdev, davinci_rtc);
-
- davinci_rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
- if (IS_ERR(davinci_rtc->rtc))
- return PTR_ERR(davinci_rtc->rtc);
-
- davinci_rtc->rtc->ops = &davinci_rtc_ops;
- davinci_rtc->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
- davinci_rtc->rtc->range_max = RTC_TIMESTAMP_BEGIN_2000 + (1 << 16) * 86400ULL - 1;
-
- rtcif_write(davinci_rtc, PRTCIF_INTFLG_RTCSS, PRTCIF_INTFLG);
- rtcif_write(davinci_rtc, 0, PRTCIF_INTEN);
- rtcss_write(davinci_rtc, 0, PRTCSS_RTC_INTC_EXTENA1);
-
- rtcss_write(davinci_rtc, 0, PRTCSS_RTC_CTRL);
- rtcss_write(davinci_rtc, 0, PRTCSS_RTC_CCTRL);
-
- ret = devm_request_irq(dev, davinci_rtc->irq, davinci_rtc_interrupt,
- 0, "davinci_rtc", davinci_rtc);
- if (ret < 0) {
- dev_err(dev, "unable to register davinci RTC interrupt\n");
- return ret;
- }
-
- /* Enable interrupts */
- rtcif_write(davinci_rtc, PRTCIF_INTEN_RTCSS, PRTCIF_INTEN);
- rtcss_write(davinci_rtc, PRTCSS_RTC_INTC_EXTENA1_MASK,
- PRTCSS_RTC_INTC_EXTENA1);
-
- rtcss_write(davinci_rtc, PRTCSS_RTC_CCTRL_CAEN, PRTCSS_RTC_CCTRL);
-
- device_init_wakeup(&pdev->dev, 0);
-
- return devm_rtc_register_device(davinci_rtc->rtc);
-}
-
-static int __exit davinci_rtc_remove(struct platform_device *pdev)
-{
- struct davinci_rtc *davinci_rtc = platform_get_drvdata(pdev);
-
- device_init_wakeup(&pdev->dev, 0);
-
- rtcif_write(davinci_rtc, 0, PRTCIF_INTEN);
-
- return 0;
-}
-
-static struct platform_driver davinci_rtc_driver = {
- .remove = __exit_p(davinci_rtc_remove),
- .driver = {
- .name = "rtc_davinci",
- },
-};
-
-module_platform_driver_probe(davinci_rtc_driver, davinci_rtc_probe);
-
-MODULE_AUTHOR("Miguel Aguilar <miguel.aguilar@ridgerun.com>");
-MODULE_DESCRIPTION("Texas Instruments DaVinci PRTC Driver");
-MODULE_LICENSE("GPL");
--
2.29.2
^ permalink raw reply related [flat|nested] 48+ messages in thread* Re: [PATCH 08/14] rtc: remove davinci rtc driver
2022-10-19 15:29 ` [PATCH 08/14] rtc: remove davinci rtc driver Arnd Bergmann
@ 2022-10-20 11:35 ` Bartosz Golaszewski
0 siblings, 0 replies; 48+ messages in thread
From: Bartosz Golaszewski @ 2022-10-20 11:35 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Sekhar Nori, linux-arm-kernel, Alessandro Zummo,
Alexandre Belloni, linux-kernel, Kevin Hilman, Arnd Bergmann,
linux-rtc
On Wed, Oct 19, 2022 at 5:36 PM Arnd Bergmann <arnd@kernel.org> wrote:
>
> From: Arnd Bergmann <arnd@arndb.de>
>
> The Davinci dm365 SoC support was removed, so the rtc driver
> has no remaining users.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH 09/14] ASoC: remove unused davinci support
2022-10-19 15:29 [PATCH 00/14] ARM: remove unused davinci board & drivers Arnd Bergmann
` (7 preceding siblings ...)
2022-10-19 15:29 ` [PATCH 08/14] rtc: remove davinci rtc driver Arnd Bergmann
@ 2022-10-19 15:29 ` Arnd Bergmann
2022-10-19 15:52 ` Mark Brown
2022-10-19 15:29 ` [PATCH 10/14] mfd: remove davinci voicecodec driver Arnd Bergmann
` (7 subsequent siblings)
16 siblings, 1 reply; 48+ messages in thread
From: Arnd Bergmann @ 2022-10-19 15:29 UTC (permalink / raw)
To: Sekhar Nori, Bartosz Golaszewski, linux-arm-kernel,
Peter Ujfalusi, Liam Girdwood, Mark Brown, Jaroslav Kysela,
Takashi Iwai
Cc: linux-kernel, Kevin Hilman, Arnd Bergmann, Charles Keepax, alsa-devel
From: Arnd Bergmann <arnd@arndb.de>
The dm644x and dm3xx SoCs have been removed, as have the
da850_evm/da830_evm machines, the remaining machines all use the
DT based probing and do not use the vcif driver.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
sound/soc/ti/Kconfig | 40 ------
sound/soc/ti/Makefile | 2 -
sound/soc/ti/davinci-evm.c | 267 +-----------------------------------
sound/soc/ti/davinci-vcif.c | 247 ---------------------------------
4 files changed, 3 insertions(+), 553 deletions(-)
delete mode 100644 sound/soc/ti/davinci-vcif.c
diff --git a/sound/soc/ti/Kconfig b/sound/soc/ti/Kconfig
index 40110e9a9e8a..593be22503b5 100644
--- a/sound/soc/ti/Kconfig
+++ b/sound/soc/ti/Kconfig
@@ -40,13 +40,6 @@ config SND_SOC_DAVINCI_MCASP
- Keystone devices
- K3 devices (am654, j721e)
-config SND_SOC_DAVINCI_VCIF
- tristate "daVinci Voice Interface (VCIF) support"
- depends on ARCH_DAVINCI || COMPILE_TEST
- select SND_SOC_TI_EDMA_PCM
- help
- Say Y or M here if you want audio support via daVinci VCIF.
-
config SND_SOC_OMAP_DMIC
tristate "Digital Microphone Module (DMIC) support"
depends on ARCH_OMAP4 || SOC_OMAP5 || COMPILE_TEST && COMMON_CLK
@@ -177,14 +170,6 @@ config SND_SOC_OMAP_OSK5912
config SND_SOC_DAVINCI_EVM
tristate "SoC Audio support for DaVinci EVMs"
depends on ARCH_DAVINCI && I2C
- select SND_SOC_DAVINCI_ASP if MACH_DAVINCI_DM355_EVM
- select SND_SOC_DAVINCI_ASP if SND_SOC_DM365_AIC3X_CODEC
- select SND_SOC_DAVINCI_VCIF if SND_SOC_DM365_VOICE_CODEC
- select SND_SOC_DAVINCI_ASP if MACH_DAVINCI_EVM # DM6446
- select SND_SOC_DAVINCI_MCASP if MACH_DAVINCI_DM6467_EVM
- select SND_SOC_SPDIF if MACH_DAVINCI_DM6467_EVM
- select SND_SOC_DAVINCI_MCASP if MACH_DAVINCI_DA830_EVM
- select SND_SOC_DAVINCI_MCASP if MACH_DAVINCI_DA850_EVM
select SND_SOC_TLV320AIC3X
help
Say Y if you want to add support for SoC audio on the following TI
@@ -196,31 +181,6 @@ config SND_SOC_DAVINCI_EVM
- DM830
- DM850
-choice
- prompt "DM365 codec select"
- depends on SND_SOC_DAVINCI_EVM
- depends on MACH_DAVINCI_DM365_EVM
-
-config SND_SOC_DM365_AIC3X_CODEC
- bool "Audio Codec - AIC3101"
- help
- Say Y if you want to add support for AIC3101 audio codec
-
-config SND_SOC_DM365_VOICE_CODEC
- bool "Voice Codec - CQ93VC"
- help
- Say Y if you want to add support for SoC On-chip voice codec
-endchoice
-
-config SND_SOC_DM365_SELECT_VOICE_CODECS
- def_tristate y
- depends on SND_SOC_DM365_VOICE_CODEC && SND_SOC
- select MFD_DAVINCI_VOICECODEC
- select SND_SOC_CQ0093VC
- help
- The is an internal symbol needed to ensure that the codec
- and MFD driver can be built as loadable modules if necessary.
-
config SND_SOC_J721E_EVM
tristate "SoC Audio support for j721e EVM"
depends on ARCH_K3 || COMPILE_TEST && COMMON_CLK
diff --git a/sound/soc/ti/Makefile b/sound/soc/ti/Makefile
index a21e5b0061de..41cdcaec770d 100644
--- a/sound/soc/ti/Makefile
+++ b/sound/soc/ti/Makefile
@@ -12,14 +12,12 @@ obj-$(CONFIG_SND_SOC_TI_UDMA_PCM) += snd-soc-ti-udma.o
# CPU DAI drivers
snd-soc-davinci-asp-objs := davinci-i2s.o
snd-soc-davinci-mcasp-objs := davinci-mcasp.o
-snd-soc-davinci-vcif-objs := davinci-vcif.o
snd-soc-omap-dmic-objs := omap-dmic.o
snd-soc-omap-mcbsp-objs := omap-mcbsp.o omap-mcbsp-st.o
snd-soc-omap-mcpdm-objs := omap-mcpdm.o
obj-$(CONFIG_SND_SOC_DAVINCI_ASP) += snd-soc-davinci-asp.o
obj-$(CONFIG_SND_SOC_DAVINCI_MCASP) += snd-soc-davinci-mcasp.o
-obj-$(CONFIG_SND_SOC_DAVINCI_VCIF) += snd-soc-davinci-vcif.o
obj-$(CONFIG_SND_SOC_OMAP_DMIC) += snd-soc-omap-dmic.o
obj-$(CONFIG_SND_SOC_OMAP_MCBSP) += snd-soc-omap-mcbsp.o
obj-$(CONFIG_SND_SOC_OMAP_MCPDM) += snd-soc-omap-mcpdm.o
diff --git a/sound/soc/ti/davinci-evm.c b/sound/soc/ti/davinci-evm.c
index 68d69e32681a..983d69b951b0 100644
--- a/sound/soc/ti/davinci-evm.c
+++ b/sound/soc/ti/davinci-evm.c
@@ -138,214 +138,6 @@ static int evm_aic3x_init(struct snd_soc_pcm_runtime *rtd)
return 0;
}
-/* davinci-evm digital audio interface glue - connects codec <--> CPU */
-SND_SOC_DAILINK_DEFS(dm6446,
- DAILINK_COMP_ARRAY(COMP_CPU("davinci-mcbsp")),
- DAILINK_COMP_ARRAY(COMP_CODEC("tlv320aic3x-codec.1-001b",
- "tlv320aic3x-hifi")),
- DAILINK_COMP_ARRAY(COMP_PLATFORM("davinci-mcbsp")));
-
-static struct snd_soc_dai_link dm6446_evm_dai = {
- .name = "TLV320AIC3X",
- .stream_name = "AIC3X",
- .init = evm_aic3x_init,
- .ops = &evm_ops,
- .dai_fmt = SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_CBM_CFM |
- SND_SOC_DAIFMT_IB_NF,
- SND_SOC_DAILINK_REG(dm6446),
-};
-
-SND_SOC_DAILINK_DEFS(dm355,
- DAILINK_COMP_ARRAY(COMP_CPU("davinci-mcbsp.1")),
- DAILINK_COMP_ARRAY(COMP_CODEC("tlv320aic3x-codec.1-001b",
- "tlv320aic3x-hifi")),
- DAILINK_COMP_ARRAY(COMP_PLATFORM("davinci-mcbsp.1")));
-
-static struct snd_soc_dai_link dm355_evm_dai = {
- .name = "TLV320AIC3X",
- .stream_name = "AIC3X",
- .init = evm_aic3x_init,
- .ops = &evm_ops,
- .dai_fmt = SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_CBM_CFM |
- SND_SOC_DAIFMT_IB_NF,
- SND_SOC_DAILINK_REG(dm355),
-};
-
-#ifdef CONFIG_SND_SOC_DM365_AIC3X_CODEC
-SND_SOC_DAILINK_DEFS(dm365,
- DAILINK_COMP_ARRAY(COMP_CPU("davinci-mcbsp")),
- DAILINK_COMP_ARRAY(COMP_CODEC("tlv320aic3x-codec.1-0018",
- "tlv320aic3x-hifi")),
- DAILINK_COMP_ARRAY(COMP_PLATFORM("davinci-mcbsp")));
-#elif defined(CONFIG_SND_SOC_DM365_VOICE_CODEC)
-SND_SOC_DAILINK_DEFS(dm365,
- DAILINK_COMP_ARRAY(COMP_CPU("davinci-vcif")),
- DAILINK_COMP_ARRAY(COMP_CODEC("cq93vc-codec", "cq93vc-hifi")),
- DAILINK_COMP_ARRAY(COMP_PLATFORM("davinci-vcif")));
-#endif
-
-static struct snd_soc_dai_link dm365_evm_dai = {
-#ifdef CONFIG_SND_SOC_DM365_AIC3X_CODEC
- .name = "TLV320AIC3X",
- .stream_name = "AIC3X",
- .init = evm_aic3x_init,
- .ops = &evm_ops,
- .dai_fmt = SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_CBM_CFM |
- SND_SOC_DAIFMT_IB_NF,
- SND_SOC_DAILINK_REG(dm365),
-#elif defined(CONFIG_SND_SOC_DM365_VOICE_CODEC)
- .name = "Voice Codec - CQ93VC",
- .stream_name = "CQ93",
- SND_SOC_DAILINK_REG(dm365),
-#endif
-};
-
-SND_SOC_DAILINK_DEFS(dm6467_aic3x,
- DAILINK_COMP_ARRAY(COMP_CPU("davinci-mcasp.0")),
- DAILINK_COMP_ARRAY(COMP_CODEC("tlv320aic3x-codec.0-001a",
- "tlv320aic3x-hifi")),
- DAILINK_COMP_ARRAY(COMP_PLATFORM("davinci-mcasp.0")));
-
-SND_SOC_DAILINK_DEFS(dm6467_spdif,
- DAILINK_COMP_ARRAY(COMP_CPU("davinci-mcasp.1")),
- DAILINK_COMP_ARRAY(COMP_CODEC("spdif_dit", "dit-hifi")),
- DAILINK_COMP_ARRAY(COMP_PLATFORM("davinci-mcasp.1")));
-
-static struct snd_soc_dai_link dm6467_evm_dai[] = {
- {
- .name = "TLV320AIC3X",
- .stream_name = "AIC3X",
- .init = evm_aic3x_init,
- .ops = &evm_ops,
- .dai_fmt = SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_CBM_CFM |
- SND_SOC_DAIFMT_IB_NF,
- SND_SOC_DAILINK_REG(dm6467_aic3x),
- },
- {
- .name = "McASP",
- .stream_name = "spdif",
- .dai_fmt = SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_CBM_CFM |
- SND_SOC_DAIFMT_IB_NF,
- SND_SOC_DAILINK_REG(dm6467_spdif),
- },
-};
-
-SND_SOC_DAILINK_DEFS(da830,
- DAILINK_COMP_ARRAY(COMP_CPU("davinci-mcasp.1")),
- DAILINK_COMP_ARRAY(COMP_CODEC("tlv320aic3x-codec.1-0018",
- "tlv320aic3x-hifi")),
- DAILINK_COMP_ARRAY(COMP_PLATFORM("davinci-mcasp.1")));
-
-static struct snd_soc_dai_link da830_evm_dai = {
- .name = "TLV320AIC3X",
- .stream_name = "AIC3X",
- .init = evm_aic3x_init,
- .ops = &evm_ops,
- .dai_fmt = SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_CBM_CFM |
- SND_SOC_DAIFMT_IB_NF,
- SND_SOC_DAILINK_REG(da830),
-};
-
-SND_SOC_DAILINK_DEFS(da850,
- DAILINK_COMP_ARRAY(COMP_CPU("davinci-mcasp.0")),
- DAILINK_COMP_ARRAY(COMP_CODEC("tlv320aic3x-codec.1-0018",
- "tlv320aic3x-hifi")),
- DAILINK_COMP_ARRAY(COMP_PLATFORM("davinci-mcasp.0")));
-
-static struct snd_soc_dai_link da850_evm_dai = {
- .name = "TLV320AIC3X",
- .stream_name = "AIC3X",
- .init = evm_aic3x_init,
- .ops = &evm_ops,
- .dai_fmt = SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_CBM_CFM |
- SND_SOC_DAIFMT_IB_NF,
- SND_SOC_DAILINK_REG(da850),
-};
-
-/* davinci dm6446 evm audio machine driver */
-/*
- * ASP0 in DM6446 EVM is clocked by U55, as configured by
- * board-dm644x-evm.c using GPIOs from U18. There are six
- * options; here we "know" we use a 48 KHz sample rate.
- */
-static struct snd_soc_card_drvdata_davinci dm6446_snd_soc_card_drvdata = {
- .sysclk = 12288000,
-};
-
-static struct snd_soc_card dm6446_snd_soc_card_evm = {
- .name = "DaVinci DM6446 EVM",
- .owner = THIS_MODULE,
- .dai_link = &dm6446_evm_dai,
- .num_links = 1,
- .drvdata = &dm6446_snd_soc_card_drvdata,
-};
-
-/* davinci dm355 evm audio machine driver */
-/* ASP1 on DM355 EVM is clocked by an external oscillator */
-static struct snd_soc_card_drvdata_davinci dm355_snd_soc_card_drvdata = {
- .sysclk = 27000000,
-};
-
-static struct snd_soc_card dm355_snd_soc_card_evm = {
- .name = "DaVinci DM355 EVM",
- .owner = THIS_MODULE,
- .dai_link = &dm355_evm_dai,
- .num_links = 1,
- .drvdata = &dm355_snd_soc_card_drvdata,
-};
-
-/* davinci dm365 evm audio machine driver */
-static struct snd_soc_card_drvdata_davinci dm365_snd_soc_card_drvdata = {
- .sysclk = 27000000,
-};
-
-static struct snd_soc_card dm365_snd_soc_card_evm = {
- .name = "DaVinci DM365 EVM",
- .owner = THIS_MODULE,
- .dai_link = &dm365_evm_dai,
- .num_links = 1,
- .drvdata = &dm365_snd_soc_card_drvdata,
-};
-
-/* davinci dm6467 evm audio machine driver */
-static struct snd_soc_card_drvdata_davinci dm6467_snd_soc_card_drvdata = {
- .sysclk = 27000000,
-};
-
-static struct snd_soc_card dm6467_snd_soc_card_evm = {
- .name = "DaVinci DM6467 EVM",
- .owner = THIS_MODULE,
- .dai_link = dm6467_evm_dai,
- .num_links = ARRAY_SIZE(dm6467_evm_dai),
- .drvdata = &dm6467_snd_soc_card_drvdata,
-};
-
-static struct snd_soc_card_drvdata_davinci da830_snd_soc_card_drvdata = {
- .sysclk = 24576000,
-};
-
-static struct snd_soc_card da830_snd_soc_card = {
- .name = "DA830/OMAP-L137 EVM",
- .owner = THIS_MODULE,
- .dai_link = &da830_evm_dai,
- .num_links = 1,
- .drvdata = &da830_snd_soc_card_drvdata,
-};
-
-static struct snd_soc_card_drvdata_davinci da850_snd_soc_card_drvdata = {
- .sysclk = 24576000,
-};
-
-static struct snd_soc_card da850_snd_soc_card = {
- .name = "DA850/OMAP-L138 EVM",
- .owner = THIS_MODULE,
- .dai_link = &da850_evm_dai,
- .num_links = 1,
- .drvdata = &da850_snd_soc_card_drvdata,
-};
-
-#if defined(CONFIG_OF)
-
/*
* The struct is used as place holder. It will be completely
* filled with data from dt node.
@@ -461,71 +253,18 @@ static struct platform_driver davinci_evm_driver = {
.driver = {
.name = "davinci_evm",
.pm = &snd_soc_pm_ops,
- .of_match_table = of_match_ptr(davinci_evm_dt_ids),
+ .of_match_table = davinci_evm_dt_ids,
},
};
-#endif
-
-static struct platform_device *evm_snd_device;
static int __init evm_init(void)
{
- struct snd_soc_card *evm_snd_dev_data;
- int index;
- int ret;
-
- /*
- * If dtb is there, the devices will be created dynamically.
- * Only register platfrom driver structure.
- */
-#if defined(CONFIG_OF)
- if (of_have_populated_dt())
- return platform_driver_register(&davinci_evm_driver);
-#endif
-
- if (machine_is_davinci_evm()) {
- evm_snd_dev_data = &dm6446_snd_soc_card_evm;
- index = 0;
- } else if (machine_is_davinci_dm355_evm()) {
- evm_snd_dev_data = &dm355_snd_soc_card_evm;
- index = 1;
- } else if (machine_is_davinci_dm365_evm()) {
- evm_snd_dev_data = &dm365_snd_soc_card_evm;
- index = 0;
- } else if (machine_is_davinci_dm6467_evm()) {
- evm_snd_dev_data = &dm6467_snd_soc_card_evm;
- index = 0;
- } else if (machine_is_davinci_da830_evm()) {
- evm_snd_dev_data = &da830_snd_soc_card;
- index = 1;
- } else if (machine_is_davinci_da850_evm()) {
- evm_snd_dev_data = &da850_snd_soc_card;
- index = 0;
- } else
- return -EINVAL;
-
- evm_snd_device = platform_device_alloc("soc-audio", index);
- if (!evm_snd_device)
- return -ENOMEM;
-
- platform_set_drvdata(evm_snd_device, evm_snd_dev_data);
- ret = platform_device_add(evm_snd_device);
- if (ret)
- platform_device_put(evm_snd_device);
-
- return ret;
+ return platform_driver_register(&davinci_evm_driver);
}
static void __exit evm_exit(void)
{
-#if defined(CONFIG_OF)
- if (of_have_populated_dt()) {
- platform_driver_unregister(&davinci_evm_driver);
- return;
- }
-#endif
-
- platform_device_unregister(evm_snd_device);
+ platform_driver_unregister(&davinci_evm_driver);
}
module_init(evm_init);
diff --git a/sound/soc/ti/davinci-vcif.c b/sound/soc/ti/davinci-vcif.c
deleted file mode 100644
index 36fa97e2b9e2..000000000000
--- a/sound/soc/ti/davinci-vcif.c
+++ /dev/null
@@ -1,247 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * ALSA SoC Voice Codec Interface for TI DAVINCI processor
- *
- * Copyright (C) 2010 Texas Instruments.
- *
- * Author: Miguel Aguilar <miguel.aguilar@ridgerun.com>
- */
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/device.h>
-#include <linux/delay.h>
-#include <linux/slab.h>
-#include <linux/io.h>
-#include <linux/mfd/davinci_voicecodec.h>
-
-#include <sound/core.h>
-#include <sound/pcm.h>
-#include <sound/pcm_params.h>
-#include <sound/initval.h>
-#include <sound/soc.h>
-#include <sound/dmaengine_pcm.h>
-
-#include "edma-pcm.h"
-#include "davinci-i2s.h"
-
-#define MOD_REG_BIT(val, mask, set) do { \
- if (set) { \
- val |= mask; \
- } else { \
- val &= ~mask; \
- } \
-} while (0)
-
-struct davinci_vcif_dev {
- struct davinci_vc *davinci_vc;
- struct snd_dmaengine_dai_dma_data dma_data[2];
- int dma_request[2];
-};
-
-static void davinci_vcif_start(struct snd_pcm_substream *substream)
-{
- struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
- struct davinci_vcif_dev *davinci_vcif_dev =
- snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
- struct davinci_vc *davinci_vc = davinci_vcif_dev->davinci_vc;
- u32 w;
-
- /* Start the sample generator and enable transmitter/receiver */
- w = readl(davinci_vc->base + DAVINCI_VC_CTRL);
-
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
- MOD_REG_BIT(w, DAVINCI_VC_CTRL_RSTDAC, 0);
- else
- MOD_REG_BIT(w, DAVINCI_VC_CTRL_RSTADC, 0);
-
- writel(w, davinci_vc->base + DAVINCI_VC_CTRL);
-}
-
-static void davinci_vcif_stop(struct snd_pcm_substream *substream)
-{
- struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
- struct davinci_vcif_dev *davinci_vcif_dev =
- snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
- struct davinci_vc *davinci_vc = davinci_vcif_dev->davinci_vc;
- u32 w;
-
- /* Reset transmitter/receiver and sample rate/frame sync generators */
- w = readl(davinci_vc->base + DAVINCI_VC_CTRL);
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
- MOD_REG_BIT(w, DAVINCI_VC_CTRL_RSTDAC, 1);
- else
- MOD_REG_BIT(w, DAVINCI_VC_CTRL_RSTADC, 1);
-
- writel(w, davinci_vc->base + DAVINCI_VC_CTRL);
-}
-
-static int davinci_vcif_hw_params(struct snd_pcm_substream *substream,
- struct snd_pcm_hw_params *params,
- struct snd_soc_dai *dai)
-{
- struct davinci_vcif_dev *davinci_vcif_dev = snd_soc_dai_get_drvdata(dai);
- struct davinci_vc *davinci_vc = davinci_vcif_dev->davinci_vc;
- u32 w;
-
- /* Restart the codec before setup */
- davinci_vcif_stop(substream);
- davinci_vcif_start(substream);
-
- /* General line settings */
- writel(DAVINCI_VC_CTRL_MASK, davinci_vc->base + DAVINCI_VC_CTRL);
-
- writel(DAVINCI_VC_INT_MASK, davinci_vc->base + DAVINCI_VC_INTCLR);
-
- writel(DAVINCI_VC_INT_MASK, davinci_vc->base + DAVINCI_VC_INTEN);
-
- w = readl(davinci_vc->base + DAVINCI_VC_CTRL);
-
- /* Determine xfer data type */
- switch (params_format(params)) {
- case SNDRV_PCM_FORMAT_U8:
- MOD_REG_BIT(w, DAVINCI_VC_CTRL_RD_BITS_8 |
- DAVINCI_VC_CTRL_RD_UNSIGNED |
- DAVINCI_VC_CTRL_WD_BITS_8 |
- DAVINCI_VC_CTRL_WD_UNSIGNED, 1);
- break;
- case SNDRV_PCM_FORMAT_S8:
- MOD_REG_BIT(w, DAVINCI_VC_CTRL_RD_BITS_8 |
- DAVINCI_VC_CTRL_WD_BITS_8, 1);
-
- MOD_REG_BIT(w, DAVINCI_VC_CTRL_RD_UNSIGNED |
- DAVINCI_VC_CTRL_WD_UNSIGNED, 0);
- break;
- case SNDRV_PCM_FORMAT_S16_LE:
- MOD_REG_BIT(w, DAVINCI_VC_CTRL_RD_BITS_8 |
- DAVINCI_VC_CTRL_RD_UNSIGNED |
- DAVINCI_VC_CTRL_WD_BITS_8 |
- DAVINCI_VC_CTRL_WD_UNSIGNED, 0);
- break;
- default:
- printk(KERN_WARNING "davinci-vcif: unsupported PCM format");
- return -EINVAL;
- }
-
- writel(w, davinci_vc->base + DAVINCI_VC_CTRL);
-
- return 0;
-}
-
-static int davinci_vcif_trigger(struct snd_pcm_substream *substream, int cmd,
- struct snd_soc_dai *dai)
-{
- int ret = 0;
-
- switch (cmd) {
- case SNDRV_PCM_TRIGGER_START:
- case SNDRV_PCM_TRIGGER_RESUME:
- case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
- davinci_vcif_start(substream);
- break;
- case SNDRV_PCM_TRIGGER_STOP:
- case SNDRV_PCM_TRIGGER_SUSPEND:
- case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
- davinci_vcif_stop(substream);
- break;
- default:
- ret = -EINVAL;
- }
-
- return ret;
-}
-
-#define DAVINCI_VCIF_RATES SNDRV_PCM_RATE_8000_48000
-
-static const struct snd_soc_dai_ops davinci_vcif_dai_ops = {
- .trigger = davinci_vcif_trigger,
- .hw_params = davinci_vcif_hw_params,
-};
-
-static int davinci_vcif_dai_probe(struct snd_soc_dai *dai)
-{
- struct davinci_vcif_dev *dev = snd_soc_dai_get_drvdata(dai);
-
- dai->playback_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
- dai->capture_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_CAPTURE];
-
- return 0;
-}
-
-static struct snd_soc_dai_driver davinci_vcif_dai = {
- .probe = davinci_vcif_dai_probe,
- .playback = {
- .channels_min = 1,
- .channels_max = 2,
- .rates = DAVINCI_VCIF_RATES,
- .formats = SNDRV_PCM_FMTBIT_S16_LE,},
- .capture = {
- .channels_min = 1,
- .channels_max = 2,
- .rates = DAVINCI_VCIF_RATES,
- .formats = SNDRV_PCM_FMTBIT_S16_LE,},
- .ops = &davinci_vcif_dai_ops,
-
-};
-
-static const struct snd_soc_component_driver davinci_vcif_component = {
- .name = "davinci-vcif",
- .legacy_dai_naming = 1,
-};
-
-static int davinci_vcif_probe(struct platform_device *pdev)
-{
- struct davinci_vc *davinci_vc = pdev->dev.platform_data;
- struct davinci_vcif_dev *davinci_vcif_dev;
- int ret;
-
- davinci_vcif_dev = devm_kzalloc(&pdev->dev,
- sizeof(struct davinci_vcif_dev),
- GFP_KERNEL);
- if (!davinci_vcif_dev)
- return -ENOMEM;
-
- /* DMA tx params */
- davinci_vcif_dev->davinci_vc = davinci_vc;
- davinci_vcif_dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data =
- &davinci_vc->davinci_vcif.dma_tx_channel;
- davinci_vcif_dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr =
- davinci_vc->davinci_vcif.dma_tx_addr;
-
- /* DMA rx params */
- davinci_vcif_dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].filter_data =
- &davinci_vc->davinci_vcif.dma_rx_channel;
- davinci_vcif_dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr =
- davinci_vc->davinci_vcif.dma_rx_addr;
-
- dev_set_drvdata(&pdev->dev, davinci_vcif_dev);
-
- ret = devm_snd_soc_register_component(&pdev->dev,
- &davinci_vcif_component,
- &davinci_vcif_dai, 1);
- if (ret != 0) {
- dev_err(&pdev->dev, "could not register dai\n");
- return ret;
- }
-
- ret = edma_pcm_platform_register(&pdev->dev);
- if (ret) {
- dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
- return ret;
- }
-
- return 0;
-}
-
-static struct platform_driver davinci_vcif_driver = {
- .probe = davinci_vcif_probe,
- .driver = {
- .name = "davinci-vcif",
- },
-};
-
-module_platform_driver(davinci_vcif_driver);
-
-MODULE_AUTHOR("Miguel Aguilar");
-MODULE_DESCRIPTION("Texas Instruments DaVinci ASoC Voice Codec Interface");
-MODULE_LICENSE("GPL");
--
2.29.2
^ permalink raw reply related [flat|nested] 48+ messages in thread* Re: [PATCH 09/14] ASoC: remove unused davinci support
2022-10-19 15:29 ` [PATCH 09/14] ASoC: remove unused davinci support Arnd Bergmann
@ 2022-10-19 15:52 ` Mark Brown
0 siblings, 0 replies; 48+ messages in thread
From: Mark Brown @ 2022-10-19 15:52 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Sekhar Nori, Bartosz Golaszewski, linux-arm-kernel,
Peter Ujfalusi, Liam Girdwood, Jaroslav Kysela, Takashi Iwai,
linux-kernel, Kevin Hilman, Arnd Bergmann, Charles Keepax,
alsa-devel
[-- Attachment #1: Type: text/plain, Size: 332 bytes --]
On Wed, Oct 19, 2022 at 05:29:35PM +0200, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> The dm644x and dm3xx SoCs have been removed, as have the
> da850_evm/da830_evm machines, the remaining machines all use the
> DT based probing and do not use the vcif driver.
Acked-by: Mark Brown <broonie@kernel.org>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 484 bytes --]
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH 10/14] mfd: remove davinci voicecodec driver
2022-10-19 15:29 [PATCH 00/14] ARM: remove unused davinci board & drivers Arnd Bergmann
` (8 preceding siblings ...)
2022-10-19 15:29 ` [PATCH 09/14] ASoC: remove unused davinci support Arnd Bergmann
@ 2022-10-19 15:29 ` Arnd Bergmann
2022-10-20 11:35 ` Bartosz Golaszewski
2022-10-31 15:17 ` Lee Jones
2022-10-19 15:29 ` [PATCH 11/14] pata: remove palmchip bk3710 driver Arnd Bergmann
` (6 subsequent siblings)
16 siblings, 2 replies; 48+ messages in thread
From: Arnd Bergmann @ 2022-10-19 15:29 UTC (permalink / raw)
To: Sekhar Nori, Bartosz Golaszewski, linux-arm-kernel, Lee Jones
Cc: linux-kernel, Kevin Hilman, Arnd Bergmann, Hans de Goede,
Andy Shevchenko
From: Arnd Bergmann <arnd@arndb.de>
The ASoC davinci voicecodec support is no longer used after
the removal of the dm3xx SoC platform, so the MFD driver is never
selected.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
drivers/mfd/Kconfig | 5 --
drivers/mfd/Makefile | 2 -
drivers/mfd/davinci_voicecodec.c | 136 -------------------------------
3 files changed, 143 deletions(-)
delete mode 100644 drivers/mfd/davinci_voicecodec.c
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 31751cd3c4ed..e05474ba687c 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -1423,11 +1423,6 @@ config MFD_SYSCON
Select this option to enable accessing system control registers
via regmap.
-config MFD_DAVINCI_VOICECODEC
- tristate
- select MFD_CORE
- select REGMAP_MMIO
-
config MFD_TI_AM335X_TSCADC
tristate "TI ADC / Touch Screen chip support"
select MFD_CORE
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index a3a304f8c762..38d9bf03c249 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -22,8 +22,6 @@ obj-$(CONFIG_HTC_PASIC3) += htc-pasic3.o
obj-$(CONFIG_MFD_TI_LP873X) += lp873x.o
obj-$(CONFIG_MFD_TI_LP87565) += lp87565.o
-
-obj-$(CONFIG_MFD_DAVINCI_VOICECODEC) += davinci_voicecodec.o
obj-$(CONFIG_MFD_TI_AM335X_TSCADC) += ti_am335x_tscadc.o
obj-$(CONFIG_MFD_STA2X11) += sta2x11-mfd.o
diff --git a/drivers/mfd/davinci_voicecodec.c b/drivers/mfd/davinci_voicecodec.c
deleted file mode 100644
index 965820481f1e..000000000000
--- a/drivers/mfd/davinci_voicecodec.c
+++ /dev/null
@@ -1,136 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * DaVinci Voice Codec Core Interface for TI platforms
- *
- * Copyright (C) 2010 Texas Instruments, Inc
- *
- * Author: Miguel Aguilar <miguel.aguilar@ridgerun.com>
- */
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/device.h>
-#include <linux/slab.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/clk.h>
-#include <linux/regmap.h>
-
-#include <sound/pcm.h>
-
-#include <linux/mfd/davinci_voicecodec.h>
-
-static const struct regmap_config davinci_vc_regmap = {
- .reg_bits = 32,
- .val_bits = 32,
-};
-
-static int __init davinci_vc_probe(struct platform_device *pdev)
-{
- struct davinci_vc *davinci_vc;
- struct resource *res;
- struct mfd_cell *cell = NULL;
- dma_addr_t fifo_base;
- int ret;
-
- davinci_vc = devm_kzalloc(&pdev->dev,
- sizeof(struct davinci_vc), GFP_KERNEL);
- if (!davinci_vc)
- return -ENOMEM;
-
- davinci_vc->clk = devm_clk_get(&pdev->dev, NULL);
- if (IS_ERR(davinci_vc->clk)) {
- dev_dbg(&pdev->dev,
- "could not get the clock for voice codec\n");
- return -ENODEV;
- }
- clk_enable(davinci_vc->clk);
-
- davinci_vc->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
- if (IS_ERR(davinci_vc->base)) {
- ret = PTR_ERR(davinci_vc->base);
- goto fail;
- }
- fifo_base = (dma_addr_t)res->start;
-
- davinci_vc->regmap = devm_regmap_init_mmio(&pdev->dev,
- davinci_vc->base,
- &davinci_vc_regmap);
- if (IS_ERR(davinci_vc->regmap)) {
- ret = PTR_ERR(davinci_vc->regmap);
- goto fail;
- }
-
- res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
- if (!res) {
- dev_err(&pdev->dev, "no DMA resource\n");
- ret = -ENXIO;
- goto fail;
- }
-
- davinci_vc->davinci_vcif.dma_tx_channel = res->start;
- davinci_vc->davinci_vcif.dma_tx_addr = fifo_base + DAVINCI_VC_WFIFO;
-
- res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
- if (!res) {
- dev_err(&pdev->dev, "no DMA resource\n");
- ret = -ENXIO;
- goto fail;
- }
-
- davinci_vc->davinci_vcif.dma_rx_channel = res->start;
- davinci_vc->davinci_vcif.dma_rx_addr = fifo_base + DAVINCI_VC_RFIFO;
-
- davinci_vc->dev = &pdev->dev;
- davinci_vc->pdev = pdev;
-
- /* Voice codec interface client */
- cell = &davinci_vc->cells[DAVINCI_VC_VCIF_CELL];
- cell->name = "davinci-vcif";
- cell->platform_data = davinci_vc;
- cell->pdata_size = sizeof(*davinci_vc);
-
- /* Voice codec CQ93VC client */
- cell = &davinci_vc->cells[DAVINCI_VC_CQ93VC_CELL];
- cell->name = "cq93vc-codec";
- cell->platform_data = davinci_vc;
- cell->pdata_size = sizeof(*davinci_vc);
-
- ret = mfd_add_devices(&pdev->dev, pdev->id, davinci_vc->cells,
- DAVINCI_VC_CELLS, NULL, 0, NULL);
- if (ret != 0) {
- dev_err(&pdev->dev, "fail to register client devices\n");
- goto fail;
- }
-
- return 0;
-
-fail:
- clk_disable(davinci_vc->clk);
-
- return ret;
-}
-
-static int davinci_vc_remove(struct platform_device *pdev)
-{
- struct davinci_vc *davinci_vc = platform_get_drvdata(pdev);
-
- mfd_remove_devices(&pdev->dev);
-
- clk_disable(davinci_vc->clk);
-
- return 0;
-}
-
-static struct platform_driver davinci_vc_driver = {
- .driver = {
- .name = "davinci_voicecodec",
- },
- .remove = davinci_vc_remove,
-};
-
-module_platform_driver_probe(davinci_vc_driver, davinci_vc_probe);
-
-MODULE_AUTHOR("Miguel Aguilar");
-MODULE_DESCRIPTION("Texas Instruments DaVinci Voice Codec Core Interface");
-MODULE_LICENSE("GPL");
--
2.29.2
^ permalink raw reply related [flat|nested] 48+ messages in thread* Re: [PATCH 10/14] mfd: remove davinci voicecodec driver
2022-10-19 15:29 ` [PATCH 10/14] mfd: remove davinci voicecodec driver Arnd Bergmann
@ 2022-10-20 11:35 ` Bartosz Golaszewski
2022-10-31 15:17 ` Lee Jones
1 sibling, 0 replies; 48+ messages in thread
From: Bartosz Golaszewski @ 2022-10-20 11:35 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Sekhar Nori, linux-arm-kernel, Lee Jones, linux-kernel,
Kevin Hilman, Arnd Bergmann, Hans de Goede, Andy Shevchenko
On Wed, Oct 19, 2022 at 5:37 PM Arnd Bergmann <arnd@kernel.org> wrote:
>
> From: Arnd Bergmann <arnd@arndb.de>
>
> The ASoC davinci voicecodec support is no longer used after
> the removal of the dm3xx SoC platform, so the MFD driver is never
> selected.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 10/14] mfd: remove davinci voicecodec driver
2022-10-19 15:29 ` [PATCH 10/14] mfd: remove davinci voicecodec driver Arnd Bergmann
2022-10-20 11:35 ` Bartosz Golaszewski
@ 2022-10-31 15:17 ` Lee Jones
1 sibling, 0 replies; 48+ messages in thread
From: Lee Jones @ 2022-10-31 15:17 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Sekhar Nori, Bartosz Golaszewski, linux-arm-kernel, linux-kernel,
Kevin Hilman, Arnd Bergmann, Hans de Goede, Andy Shevchenko
On Wed, 19 Oct 2022, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> The ASoC davinci voicecodec support is no longer used after
> the removal of the dm3xx SoC platform, so the MFD driver is never
> selected.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
> drivers/mfd/Kconfig | 5 --
> drivers/mfd/Makefile | 2 -
> drivers/mfd/davinci_voicecodec.c | 136 -------------------------------
> 3 files changed, 143 deletions(-)
> delete mode 100644 drivers/mfd/davinci_voicecodec.c
Applied, thanks.
--
Lee Jones [李琼斯]
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH 11/14] pata: remove palmchip bk3710 driver
2022-10-19 15:29 [PATCH 00/14] ARM: remove unused davinci board & drivers Arnd Bergmann
` (9 preceding siblings ...)
2022-10-19 15:29 ` [PATCH 10/14] mfd: remove davinci voicecodec driver Arnd Bergmann
@ 2022-10-19 15:29 ` Arnd Bergmann
2022-10-19 23:17 ` Damien Le Moal
` (3 more replies)
2022-10-19 15:29 ` [PATCH 12/14] irqchip: remove davinci aintc driver Arnd Bergmann
` (5 subsequent siblings)
16 siblings, 4 replies; 48+ messages in thread
From: Arnd Bergmann @ 2022-10-19 15:29 UTC (permalink / raw)
To: Sekhar Nori, Bartosz Golaszewski, linux-arm-kernel, Damien Le Moal
Cc: linux-kernel, Kevin Hilman, Arnd Bergmann, Sergey Shtylyov,
Hannes Reinecke, linux-ide
From: Arnd Bergmann <arnd@arndb.de>
This device was used only on the davinci dm644x platform that
is now gone, and no references to the device remain in the
kernel.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
drivers/ata/Kconfig | 10 -
drivers/ata/Makefile | 1 -
drivers/ata/pata_bk3710.c | 380 --------------------------------------
3 files changed, 391 deletions(-)
delete mode 100644 drivers/ata/pata_bk3710.c
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 36833a862998..2986fc9c797e 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -609,16 +609,6 @@ config PATA_ATP867X
If unsure, say N.
-config PATA_BK3710
- tristate "Palmchip BK3710 PATA support"
- depends on ARCH_DAVINCI || COMPILE_TEST
- select PATA_TIMINGS
- help
- This option enables support for the integrated IDE controller on
- the TI DaVinci SoC.
-
- If unsure, say N.
-
config PATA_CMD64X
tristate "CMD64x PATA support"
depends on PCI
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 34623365d9a6..d2e36d367274 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -54,7 +54,6 @@ obj-$(CONFIG_PATA_AMD) += pata_amd.o
obj-$(CONFIG_PATA_ARTOP) += pata_artop.o
obj-$(CONFIG_PATA_ATIIXP) += pata_atiixp.o
obj-$(CONFIG_PATA_ATP867X) += pata_atp867x.o
-obj-$(CONFIG_PATA_BK3710) += pata_bk3710.o
obj-$(CONFIG_PATA_CMD64X) += pata_cmd64x.o
obj-$(CONFIG_PATA_CS5520) += pata_cs5520.o
obj-$(CONFIG_PATA_CS5530) += pata_cs5530.o
diff --git a/drivers/ata/pata_bk3710.c b/drivers/ata/pata_bk3710.c
deleted file mode 100644
index fad95cfecced..000000000000
--- a/drivers/ata/pata_bk3710.c
+++ /dev/null
@@ -1,380 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-
-/*
- * Palmchip BK3710 PATA controller driver
- *
- * Copyright (c) 2017 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * Based on palm_bk3710.c:
- *
- * Copyright (C) 2006 Texas Instruments.
- * Copyright (C) 2007 MontaVista Software, Inc., <source@mvista.com>
- */
-
-#include <linux/ata.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/kernel.h>
-#include <linux/libata.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/types.h>
-
-#define DRV_NAME "pata_bk3710"
-
-#define BK3710_TF_OFFSET 0x1F0
-#define BK3710_CTL_OFFSET 0x3F6
-
-#define BK3710_BMISP 0x02
-#define BK3710_IDETIMP 0x40
-#define BK3710_UDMACTL 0x48
-#define BK3710_MISCCTL 0x50
-#define BK3710_REGSTB 0x54
-#define BK3710_REGRCVR 0x58
-#define BK3710_DATSTB 0x5C
-#define BK3710_DATRCVR 0x60
-#define BK3710_DMASTB 0x64
-#define BK3710_DMARCVR 0x68
-#define BK3710_UDMASTB 0x6C
-#define BK3710_UDMATRP 0x70
-#define BK3710_UDMAENV 0x74
-#define BK3710_IORDYTMP 0x78
-
-static struct scsi_host_template pata_bk3710_sht = {
- ATA_BMDMA_SHT(DRV_NAME),
-};
-
-static unsigned int ideclk_period; /* in nanoseconds */
-
-struct pata_bk3710_udmatiming {
- unsigned int rptime; /* tRP -- Ready to pause time (nsec) */
- unsigned int cycletime; /* tCYCTYP2/2 -- avg Cycle Time (nsec) */
- /* tENV is always a minimum of 20 nsec */
-};
-
-static const struct pata_bk3710_udmatiming pata_bk3710_udmatimings[6] = {
- { 160, 240 / 2 }, /* UDMA Mode 0 */
- { 125, 160 / 2 }, /* UDMA Mode 1 */
- { 100, 120 / 2 }, /* UDMA Mode 2 */
- { 100, 90 / 2 }, /* UDMA Mode 3 */
- { 100, 60 / 2 }, /* UDMA Mode 4 */
- { 85, 40 / 2 }, /* UDMA Mode 5 */
-};
-
-static void pata_bk3710_setudmamode(void __iomem *base, unsigned int dev,
- unsigned int mode)
-{
- u32 val32;
- u16 val16;
- u8 tenv, trp, t0;
-
- /* DMA Data Setup */
- t0 = DIV_ROUND_UP(pata_bk3710_udmatimings[mode].cycletime,
- ideclk_period) - 1;
- tenv = DIV_ROUND_UP(20, ideclk_period) - 1;
- trp = DIV_ROUND_UP(pata_bk3710_udmatimings[mode].rptime,
- ideclk_period) - 1;
-
- /* udmastb Ultra DMA Access Strobe Width */
- val32 = ioread32(base + BK3710_UDMASTB) & (0xFF << (dev ? 0 : 8));
- val32 |= t0 << (dev ? 8 : 0);
- iowrite32(val32, base + BK3710_UDMASTB);
-
- /* udmatrp Ultra DMA Ready to Pause Time */
- val32 = ioread32(base + BK3710_UDMATRP) & (0xFF << (dev ? 0 : 8));
- val32 |= trp << (dev ? 8 : 0);
- iowrite32(val32, base + BK3710_UDMATRP);
-
- /* udmaenv Ultra DMA envelop Time */
- val32 = ioread32(base + BK3710_UDMAENV) & (0xFF << (dev ? 0 : 8));
- val32 |= tenv << (dev ? 8 : 0);
- iowrite32(val32, base + BK3710_UDMAENV);
-
- /* Enable UDMA for Device */
- val16 = ioread16(base + BK3710_UDMACTL) | (1 << dev);
- iowrite16(val16, base + BK3710_UDMACTL);
-}
-
-static void pata_bk3710_setmwdmamode(void __iomem *base, unsigned int dev,
- unsigned short min_cycle,
- unsigned int mode)
-{
- const struct ata_timing *t;
- int cycletime;
- u32 val32;
- u16 val16;
- u8 td, tkw, t0;
-
- t = ata_timing_find_mode(mode);
- cycletime = max_t(int, t->cycle, min_cycle);
-
- /* DMA Data Setup */
- t0 = DIV_ROUND_UP(cycletime, ideclk_period);
- td = DIV_ROUND_UP(t->active, ideclk_period);
- tkw = t0 - td - 1;
- td--;
-
- val32 = ioread32(base + BK3710_DMASTB) & (0xFF << (dev ? 0 : 8));
- val32 |= td << (dev ? 8 : 0);
- iowrite32(val32, base + BK3710_DMASTB);
-
- val32 = ioread32(base + BK3710_DMARCVR) & (0xFF << (dev ? 0 : 8));
- val32 |= tkw << (dev ? 8 : 0);
- iowrite32(val32, base + BK3710_DMARCVR);
-
- /* Disable UDMA for Device */
- val16 = ioread16(base + BK3710_UDMACTL) & ~(1 << dev);
- iowrite16(val16, base + BK3710_UDMACTL);
-}
-
-static void pata_bk3710_set_dmamode(struct ata_port *ap,
- struct ata_device *adev)
-{
- void __iomem *base = (void __iomem *)ap->ioaddr.bmdma_addr;
- int is_slave = adev->devno;
- const u8 xferspeed = adev->dma_mode;
-
- if (xferspeed >= XFER_UDMA_0)
- pata_bk3710_setudmamode(base, is_slave,
- xferspeed - XFER_UDMA_0);
- else
- pata_bk3710_setmwdmamode(base, is_slave,
- adev->id[ATA_ID_EIDE_DMA_MIN],
- xferspeed);
-}
-
-static void pata_bk3710_setpiomode(void __iomem *base, struct ata_device *pair,
- unsigned int dev, unsigned int cycletime,
- unsigned int mode)
-{
- const struct ata_timing *t;
- u32 val32;
- u8 t2, t2i, t0;
-
- t = ata_timing_find_mode(XFER_PIO_0 + mode);
-
- /* PIO Data Setup */
- t0 = DIV_ROUND_UP(cycletime, ideclk_period);
- t2 = DIV_ROUND_UP(t->active, ideclk_period);
-
- t2i = t0 - t2 - 1;
- t2--;
-
- val32 = ioread32(base + BK3710_DATSTB) & (0xFF << (dev ? 0 : 8));
- val32 |= t2 << (dev ? 8 : 0);
- iowrite32(val32, base + BK3710_DATSTB);
-
- val32 = ioread32(base + BK3710_DATRCVR) & (0xFF << (dev ? 0 : 8));
- val32 |= t2i << (dev ? 8 : 0);
- iowrite32(val32, base + BK3710_DATRCVR);
-
- /* FIXME: this is broken also in the old driver */
- if (pair) {
- u8 mode2 = pair->pio_mode - XFER_PIO_0;
-
- if (mode2 < mode)
- mode = mode2;
- }
-
- /* TASKFILE Setup */
- t0 = DIV_ROUND_UP(t->cyc8b, ideclk_period);
- t2 = DIV_ROUND_UP(t->act8b, ideclk_period);
-
- t2i = t0 - t2 - 1;
- t2--;
-
- val32 = ioread32(base + BK3710_REGSTB) & (0xFF << (dev ? 0 : 8));
- val32 |= t2 << (dev ? 8 : 0);
- iowrite32(val32, base + BK3710_REGSTB);
-
- val32 = ioread32(base + BK3710_REGRCVR) & (0xFF << (dev ? 0 : 8));
- val32 |= t2i << (dev ? 8 : 0);
- iowrite32(val32, base + BK3710_REGRCVR);
-}
-
-static void pata_bk3710_set_piomode(struct ata_port *ap,
- struct ata_device *adev)
-{
- void __iomem *base = (void __iomem *)ap->ioaddr.bmdma_addr;
- struct ata_device *pair = ata_dev_pair(adev);
- const struct ata_timing *t = ata_timing_find_mode(adev->pio_mode);
- const u16 *id = adev->id;
- unsigned int cycle_time = 0;
- int is_slave = adev->devno;
- const u8 pio = adev->pio_mode - XFER_PIO_0;
-
- if (id[ATA_ID_FIELD_VALID] & 2) {
- if (ata_id_has_iordy(id))
- cycle_time = id[ATA_ID_EIDE_PIO_IORDY];
- else
- cycle_time = id[ATA_ID_EIDE_PIO];
-
- /* conservative "downgrade" for all pre-ATA2 drives */
- if (pio < 3 && cycle_time < t->cycle)
- cycle_time = 0; /* use standard timing */
- }
-
- if (!cycle_time)
- cycle_time = t->cycle;
-
- pata_bk3710_setpiomode(base, pair, is_slave, cycle_time, pio);
-}
-
-static void pata_bk3710_chipinit(void __iomem *base)
-{
- /*
- * REVISIT: the ATA reset signal needs to be managed through a
- * GPIO, which means it should come from platform_data. Until
- * we get and use such information, we have to trust that things
- * have been reset before we get here.
- */
-
- /*
- * Program the IDETIMP Register Value based on the following assumptions
- *
- * (ATA_IDETIMP_IDEEN , ENABLE ) |
- * (ATA_IDETIMP_PREPOST1 , DISABLE) |
- * (ATA_IDETIMP_PREPOST0 , DISABLE) |
- *
- * DM6446 silicon rev 2.1 and earlier have no observed net benefit
- * from enabling prefetch/postwrite.
- */
- iowrite16(BIT(15), base + BK3710_IDETIMP);
-
- /*
- * UDMACTL Ultra-ATA DMA Control
- * (ATA_UDMACTL_UDMAP1 , 0 ) |
- * (ATA_UDMACTL_UDMAP0 , 0 )
- *
- */
- iowrite16(0, base + BK3710_UDMACTL);
-
- /*
- * MISCCTL Miscellaneous Conrol Register
- * (ATA_MISCCTL_HWNHLD1P , 1 cycle)
- * (ATA_MISCCTL_HWNHLD0P , 1 cycle)
- * (ATA_MISCCTL_TIMORIDE , 1)
- */
- iowrite32(0x001, base + BK3710_MISCCTL);
-
- /*
- * IORDYTMP IORDY Timer for Primary Register
- * (ATA_IORDYTMP_IORDYTMP , DISABLE)
- */
- iowrite32(0, base + BK3710_IORDYTMP);
-
- /*
- * Configure BMISP Register
- * (ATA_BMISP_DMAEN1 , DISABLE ) |
- * (ATA_BMISP_DMAEN0 , DISABLE ) |
- * (ATA_BMISP_IORDYINT , CLEAR) |
- * (ATA_BMISP_INTRSTAT , CLEAR) |
- * (ATA_BMISP_DMAERROR , CLEAR)
- */
- iowrite16(0xE, base + BK3710_BMISP);
-
- pata_bk3710_setpiomode(base, NULL, 0, 600, 0);
- pata_bk3710_setpiomode(base, NULL, 1, 600, 0);
-}
-
-static struct ata_port_operations pata_bk3710_ports_ops = {
- .inherits = &ata_bmdma_port_ops,
- .cable_detect = ata_cable_80wire,
-
- .set_piomode = pata_bk3710_set_piomode,
- .set_dmamode = pata_bk3710_set_dmamode,
-};
-
-static int __init pata_bk3710_probe(struct platform_device *pdev)
-{
- struct clk *clk;
- struct resource *mem;
- struct ata_host *host;
- struct ata_port *ap;
- void __iomem *base;
- unsigned long rate;
- int irq;
-
- clk = devm_clk_get(&pdev->dev, NULL);
- if (IS_ERR(clk))
- return -ENODEV;
-
- clk_enable(clk);
- rate = clk_get_rate(clk);
- if (!rate)
- return -EINVAL;
-
- /* NOTE: round *down* to meet minimum timings; we count in clocks */
- ideclk_period = 1000000000UL / rate;
-
- mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-
- irq = platform_get_irq(pdev, 0);
- if (irq < 0) {
- pr_err(DRV_NAME ": failed to get IRQ resource\n");
- return irq;
- }
-
- base = devm_ioremap_resource(&pdev->dev, mem);
- if (IS_ERR(base))
- return PTR_ERR(base);
-
- /* configure the Palmchip controller */
- pata_bk3710_chipinit(base);
-
- /* allocate host */
- host = ata_host_alloc(&pdev->dev, 1);
- if (!host)
- return -ENOMEM;
- ap = host->ports[0];
-
- ap->ops = &pata_bk3710_ports_ops;
- ap->pio_mask = ATA_PIO4;
- ap->mwdma_mask = ATA_MWDMA2;
- ap->udma_mask = rate < 100000000 ? ATA_UDMA4 : ATA_UDMA5;
- ap->flags |= ATA_FLAG_SLAVE_POSS;
-
- ap->ioaddr.data_addr = base + BK3710_TF_OFFSET;
- ap->ioaddr.error_addr = base + BK3710_TF_OFFSET + 1;
- ap->ioaddr.feature_addr = base + BK3710_TF_OFFSET + 1;
- ap->ioaddr.nsect_addr = base + BK3710_TF_OFFSET + 2;
- ap->ioaddr.lbal_addr = base + BK3710_TF_OFFSET + 3;
- ap->ioaddr.lbam_addr = base + BK3710_TF_OFFSET + 4;
- ap->ioaddr.lbah_addr = base + BK3710_TF_OFFSET + 5;
- ap->ioaddr.device_addr = base + BK3710_TF_OFFSET + 6;
- ap->ioaddr.status_addr = base + BK3710_TF_OFFSET + 7;
- ap->ioaddr.command_addr = base + BK3710_TF_OFFSET + 7;
-
- ap->ioaddr.altstatus_addr = base + BK3710_CTL_OFFSET;
- ap->ioaddr.ctl_addr = base + BK3710_CTL_OFFSET;
-
- ap->ioaddr.bmdma_addr = base;
-
- ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx",
- (unsigned long)base + BK3710_TF_OFFSET,
- (unsigned long)base + BK3710_CTL_OFFSET);
-
- /* activate */
- return ata_host_activate(host, irq, ata_sff_interrupt, 0,
- &pata_bk3710_sht);
-}
-
-/* work with hotplug and coldplug */
-MODULE_ALIAS("platform:palm_bk3710");
-
-static struct platform_driver pata_bk3710_driver = {
- .driver = {
- .name = "palm_bk3710",
- },
-};
-
-static int __init pata_bk3710_init(void)
-{
- return platform_driver_probe(&pata_bk3710_driver, pata_bk3710_probe);
-}
-
-module_init(pata_bk3710_init);
-MODULE_LICENSE("GPL v2");
--
2.29.2
^ permalink raw reply related [flat|nested] 48+ messages in thread* Re: [PATCH 11/14] pata: remove palmchip bk3710 driver
2022-10-19 15:29 ` [PATCH 11/14] pata: remove palmchip bk3710 driver Arnd Bergmann
@ 2022-10-19 23:17 ` Damien Le Moal
2022-10-20 7:09 ` Arnd Bergmann
2022-10-20 11:02 ` Sergey Shtylyov
` (2 subsequent siblings)
3 siblings, 1 reply; 48+ messages in thread
From: Damien Le Moal @ 2022-10-19 23:17 UTC (permalink / raw)
To: Arnd Bergmann, Sekhar Nori, Bartosz Golaszewski, linux-arm-kernel
Cc: linux-kernel, Kevin Hilman, Arnd Bergmann, Sergey Shtylyov,
Hannes Reinecke, linux-ide
On 10/20/22 00:29, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> This device was used only on the davinci dm644x platform that
> is now gone, and no references to the device remain in the
> kernel.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Great, one less pata/ide driver !
I can queue this in ata tree. I do have some changes in ata Kconfig queued
already, but they should not conflict.
Cheers.
> ---
> drivers/ata/Kconfig | 10 -
> drivers/ata/Makefile | 1 -
> drivers/ata/pata_bk3710.c | 380 --------------------------------------
> 3 files changed, 391 deletions(-)
> delete mode 100644 drivers/ata/pata_bk3710.c
>
> diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
> index 36833a862998..2986fc9c797e 100644
> --- a/drivers/ata/Kconfig
> +++ b/drivers/ata/Kconfig
> @@ -609,16 +609,6 @@ config PATA_ATP867X
>
> If unsure, say N.
>
> -config PATA_BK3710
> - tristate "Palmchip BK3710 PATA support"
> - depends on ARCH_DAVINCI || COMPILE_TEST
> - select PATA_TIMINGS
> - help
> - This option enables support for the integrated IDE controller on
> - the TI DaVinci SoC.
> -
> - If unsure, say N.
> -
> config PATA_CMD64X
> tristate "CMD64x PATA support"
> depends on PCI
> diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
> index 34623365d9a6..d2e36d367274 100644
> --- a/drivers/ata/Makefile
> +++ b/drivers/ata/Makefile
> @@ -54,7 +54,6 @@ obj-$(CONFIG_PATA_AMD) += pata_amd.o
> obj-$(CONFIG_PATA_ARTOP) += pata_artop.o
> obj-$(CONFIG_PATA_ATIIXP) += pata_atiixp.o
> obj-$(CONFIG_PATA_ATP867X) += pata_atp867x.o
> -obj-$(CONFIG_PATA_BK3710) += pata_bk3710.o
> obj-$(CONFIG_PATA_CMD64X) += pata_cmd64x.o
> obj-$(CONFIG_PATA_CS5520) += pata_cs5520.o
> obj-$(CONFIG_PATA_CS5530) += pata_cs5530.o
> diff --git a/drivers/ata/pata_bk3710.c b/drivers/ata/pata_bk3710.c
> deleted file mode 100644
> index fad95cfecced..000000000000
> --- a/drivers/ata/pata_bk3710.c
> +++ /dev/null
> @@ -1,380 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0
> -
> -/*
> - * Palmchip BK3710 PATA controller driver
> - *
> - * Copyright (c) 2017 Samsung Electronics Co., Ltd.
> - * http://www.samsung.com
> - *
> - * Based on palm_bk3710.c:
> - *
> - * Copyright (C) 2006 Texas Instruments.
> - * Copyright (C) 2007 MontaVista Software, Inc., <source@mvista.com>
> - */
> -
> -#include <linux/ata.h>
> -#include <linux/clk.h>
> -#include <linux/delay.h>
> -#include <linux/init.h>
> -#include <linux/ioport.h>
> -#include <linux/kernel.h>
> -#include <linux/libata.h>
> -#include <linux/module.h>
> -#include <linux/platform_device.h>
> -#include <linux/types.h>
> -
> -#define DRV_NAME "pata_bk3710"
> -
> -#define BK3710_TF_OFFSET 0x1F0
> -#define BK3710_CTL_OFFSET 0x3F6
> -
> -#define BK3710_BMISP 0x02
> -#define BK3710_IDETIMP 0x40
> -#define BK3710_UDMACTL 0x48
> -#define BK3710_MISCCTL 0x50
> -#define BK3710_REGSTB 0x54
> -#define BK3710_REGRCVR 0x58
> -#define BK3710_DATSTB 0x5C
> -#define BK3710_DATRCVR 0x60
> -#define BK3710_DMASTB 0x64
> -#define BK3710_DMARCVR 0x68
> -#define BK3710_UDMASTB 0x6C
> -#define BK3710_UDMATRP 0x70
> -#define BK3710_UDMAENV 0x74
> -#define BK3710_IORDYTMP 0x78
> -
> -static struct scsi_host_template pata_bk3710_sht = {
> - ATA_BMDMA_SHT(DRV_NAME),
> -};
> -
> -static unsigned int ideclk_period; /* in nanoseconds */
> -
> -struct pata_bk3710_udmatiming {
> - unsigned int rptime; /* tRP -- Ready to pause time (nsec) */
> - unsigned int cycletime; /* tCYCTYP2/2 -- avg Cycle Time (nsec) */
> - /* tENV is always a minimum of 20 nsec */
> -};
> -
> -static const struct pata_bk3710_udmatiming pata_bk3710_udmatimings[6] = {
> - { 160, 240 / 2 }, /* UDMA Mode 0 */
> - { 125, 160 / 2 }, /* UDMA Mode 1 */
> - { 100, 120 / 2 }, /* UDMA Mode 2 */
> - { 100, 90 / 2 }, /* UDMA Mode 3 */
> - { 100, 60 / 2 }, /* UDMA Mode 4 */
> - { 85, 40 / 2 }, /* UDMA Mode 5 */
> -};
> -
> -static void pata_bk3710_setudmamode(void __iomem *base, unsigned int dev,
> - unsigned int mode)
> -{
> - u32 val32;
> - u16 val16;
> - u8 tenv, trp, t0;
> -
> - /* DMA Data Setup */
> - t0 = DIV_ROUND_UP(pata_bk3710_udmatimings[mode].cycletime,
> - ideclk_period) - 1;
> - tenv = DIV_ROUND_UP(20, ideclk_period) - 1;
> - trp = DIV_ROUND_UP(pata_bk3710_udmatimings[mode].rptime,
> - ideclk_period) - 1;
> -
> - /* udmastb Ultra DMA Access Strobe Width */
> - val32 = ioread32(base + BK3710_UDMASTB) & (0xFF << (dev ? 0 : 8));
> - val32 |= t0 << (dev ? 8 : 0);
> - iowrite32(val32, base + BK3710_UDMASTB);
> -
> - /* udmatrp Ultra DMA Ready to Pause Time */
> - val32 = ioread32(base + BK3710_UDMATRP) & (0xFF << (dev ? 0 : 8));
> - val32 |= trp << (dev ? 8 : 0);
> - iowrite32(val32, base + BK3710_UDMATRP);
> -
> - /* udmaenv Ultra DMA envelop Time */
> - val32 = ioread32(base + BK3710_UDMAENV) & (0xFF << (dev ? 0 : 8));
> - val32 |= tenv << (dev ? 8 : 0);
> - iowrite32(val32, base + BK3710_UDMAENV);
> -
> - /* Enable UDMA for Device */
> - val16 = ioread16(base + BK3710_UDMACTL) | (1 << dev);
> - iowrite16(val16, base + BK3710_UDMACTL);
> -}
> -
> -static void pata_bk3710_setmwdmamode(void __iomem *base, unsigned int dev,
> - unsigned short min_cycle,
> - unsigned int mode)
> -{
> - const struct ata_timing *t;
> - int cycletime;
> - u32 val32;
> - u16 val16;
> - u8 td, tkw, t0;
> -
> - t = ata_timing_find_mode(mode);
> - cycletime = max_t(int, t->cycle, min_cycle);
> -
> - /* DMA Data Setup */
> - t0 = DIV_ROUND_UP(cycletime, ideclk_period);
> - td = DIV_ROUND_UP(t->active, ideclk_period);
> - tkw = t0 - td - 1;
> - td--;
> -
> - val32 = ioread32(base + BK3710_DMASTB) & (0xFF << (dev ? 0 : 8));
> - val32 |= td << (dev ? 8 : 0);
> - iowrite32(val32, base + BK3710_DMASTB);
> -
> - val32 = ioread32(base + BK3710_DMARCVR) & (0xFF << (dev ? 0 : 8));
> - val32 |= tkw << (dev ? 8 : 0);
> - iowrite32(val32, base + BK3710_DMARCVR);
> -
> - /* Disable UDMA for Device */
> - val16 = ioread16(base + BK3710_UDMACTL) & ~(1 << dev);
> - iowrite16(val16, base + BK3710_UDMACTL);
> -}
> -
> -static void pata_bk3710_set_dmamode(struct ata_port *ap,
> - struct ata_device *adev)
> -{
> - void __iomem *base = (void __iomem *)ap->ioaddr.bmdma_addr;
> - int is_slave = adev->devno;
> - const u8 xferspeed = adev->dma_mode;
> -
> - if (xferspeed >= XFER_UDMA_0)
> - pata_bk3710_setudmamode(base, is_slave,
> - xferspeed - XFER_UDMA_0);
> - else
> - pata_bk3710_setmwdmamode(base, is_slave,
> - adev->id[ATA_ID_EIDE_DMA_MIN],
> - xferspeed);
> -}
> -
> -static void pata_bk3710_setpiomode(void __iomem *base, struct ata_device *pair,
> - unsigned int dev, unsigned int cycletime,
> - unsigned int mode)
> -{
> - const struct ata_timing *t;
> - u32 val32;
> - u8 t2, t2i, t0;
> -
> - t = ata_timing_find_mode(XFER_PIO_0 + mode);
> -
> - /* PIO Data Setup */
> - t0 = DIV_ROUND_UP(cycletime, ideclk_period);
> - t2 = DIV_ROUND_UP(t->active, ideclk_period);
> -
> - t2i = t0 - t2 - 1;
> - t2--;
> -
> - val32 = ioread32(base + BK3710_DATSTB) & (0xFF << (dev ? 0 : 8));
> - val32 |= t2 << (dev ? 8 : 0);
> - iowrite32(val32, base + BK3710_DATSTB);
> -
> - val32 = ioread32(base + BK3710_DATRCVR) & (0xFF << (dev ? 0 : 8));
> - val32 |= t2i << (dev ? 8 : 0);
> - iowrite32(val32, base + BK3710_DATRCVR);
> -
> - /* FIXME: this is broken also in the old driver */
> - if (pair) {
> - u8 mode2 = pair->pio_mode - XFER_PIO_0;
> -
> - if (mode2 < mode)
> - mode = mode2;
> - }
> -
> - /* TASKFILE Setup */
> - t0 = DIV_ROUND_UP(t->cyc8b, ideclk_period);
> - t2 = DIV_ROUND_UP(t->act8b, ideclk_period);
> -
> - t2i = t0 - t2 - 1;
> - t2--;
> -
> - val32 = ioread32(base + BK3710_REGSTB) & (0xFF << (dev ? 0 : 8));
> - val32 |= t2 << (dev ? 8 : 0);
> - iowrite32(val32, base + BK3710_REGSTB);
> -
> - val32 = ioread32(base + BK3710_REGRCVR) & (0xFF << (dev ? 0 : 8));
> - val32 |= t2i << (dev ? 8 : 0);
> - iowrite32(val32, base + BK3710_REGRCVR);
> -}
> -
> -static void pata_bk3710_set_piomode(struct ata_port *ap,
> - struct ata_device *adev)
> -{
> - void __iomem *base = (void __iomem *)ap->ioaddr.bmdma_addr;
> - struct ata_device *pair = ata_dev_pair(adev);
> - const struct ata_timing *t = ata_timing_find_mode(adev->pio_mode);
> - const u16 *id = adev->id;
> - unsigned int cycle_time = 0;
> - int is_slave = adev->devno;
> - const u8 pio = adev->pio_mode - XFER_PIO_0;
> -
> - if (id[ATA_ID_FIELD_VALID] & 2) {
> - if (ata_id_has_iordy(id))
> - cycle_time = id[ATA_ID_EIDE_PIO_IORDY];
> - else
> - cycle_time = id[ATA_ID_EIDE_PIO];
> -
> - /* conservative "downgrade" for all pre-ATA2 drives */
> - if (pio < 3 && cycle_time < t->cycle)
> - cycle_time = 0; /* use standard timing */
> - }
> -
> - if (!cycle_time)
> - cycle_time = t->cycle;
> -
> - pata_bk3710_setpiomode(base, pair, is_slave, cycle_time, pio);
> -}
> -
> -static void pata_bk3710_chipinit(void __iomem *base)
> -{
> - /*
> - * REVISIT: the ATA reset signal needs to be managed through a
> - * GPIO, which means it should come from platform_data. Until
> - * we get and use such information, we have to trust that things
> - * have been reset before we get here.
> - */
> -
> - /*
> - * Program the IDETIMP Register Value based on the following assumptions
> - *
> - * (ATA_IDETIMP_IDEEN , ENABLE ) |
> - * (ATA_IDETIMP_PREPOST1 , DISABLE) |
> - * (ATA_IDETIMP_PREPOST0 , DISABLE) |
> - *
> - * DM6446 silicon rev 2.1 and earlier have no observed net benefit
> - * from enabling prefetch/postwrite.
> - */
> - iowrite16(BIT(15), base + BK3710_IDETIMP);
> -
> - /*
> - * UDMACTL Ultra-ATA DMA Control
> - * (ATA_UDMACTL_UDMAP1 , 0 ) |
> - * (ATA_UDMACTL_UDMAP0 , 0 )
> - *
> - */
> - iowrite16(0, base + BK3710_UDMACTL);
> -
> - /*
> - * MISCCTL Miscellaneous Conrol Register
> - * (ATA_MISCCTL_HWNHLD1P , 1 cycle)
> - * (ATA_MISCCTL_HWNHLD0P , 1 cycle)
> - * (ATA_MISCCTL_TIMORIDE , 1)
> - */
> - iowrite32(0x001, base + BK3710_MISCCTL);
> -
> - /*
> - * IORDYTMP IORDY Timer for Primary Register
> - * (ATA_IORDYTMP_IORDYTMP , DISABLE)
> - */
> - iowrite32(0, base + BK3710_IORDYTMP);
> -
> - /*
> - * Configure BMISP Register
> - * (ATA_BMISP_DMAEN1 , DISABLE ) |
> - * (ATA_BMISP_DMAEN0 , DISABLE ) |
> - * (ATA_BMISP_IORDYINT , CLEAR) |
> - * (ATA_BMISP_INTRSTAT , CLEAR) |
> - * (ATA_BMISP_DMAERROR , CLEAR)
> - */
> - iowrite16(0xE, base + BK3710_BMISP);
> -
> - pata_bk3710_setpiomode(base, NULL, 0, 600, 0);
> - pata_bk3710_setpiomode(base, NULL, 1, 600, 0);
> -}
> -
> -static struct ata_port_operations pata_bk3710_ports_ops = {
> - .inherits = &ata_bmdma_port_ops,
> - .cable_detect = ata_cable_80wire,
> -
> - .set_piomode = pata_bk3710_set_piomode,
> - .set_dmamode = pata_bk3710_set_dmamode,
> -};
> -
> -static int __init pata_bk3710_probe(struct platform_device *pdev)
> -{
> - struct clk *clk;
> - struct resource *mem;
> - struct ata_host *host;
> - struct ata_port *ap;
> - void __iomem *base;
> - unsigned long rate;
> - int irq;
> -
> - clk = devm_clk_get(&pdev->dev, NULL);
> - if (IS_ERR(clk))
> - return -ENODEV;
> -
> - clk_enable(clk);
> - rate = clk_get_rate(clk);
> - if (!rate)
> - return -EINVAL;
> -
> - /* NOTE: round *down* to meet minimum timings; we count in clocks */
> - ideclk_period = 1000000000UL / rate;
> -
> - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> -
> - irq = platform_get_irq(pdev, 0);
> - if (irq < 0) {
> - pr_err(DRV_NAME ": failed to get IRQ resource\n");
> - return irq;
> - }
> -
> - base = devm_ioremap_resource(&pdev->dev, mem);
> - if (IS_ERR(base))
> - return PTR_ERR(base);
> -
> - /* configure the Palmchip controller */
> - pata_bk3710_chipinit(base);
> -
> - /* allocate host */
> - host = ata_host_alloc(&pdev->dev, 1);
> - if (!host)
> - return -ENOMEM;
> - ap = host->ports[0];
> -
> - ap->ops = &pata_bk3710_ports_ops;
> - ap->pio_mask = ATA_PIO4;
> - ap->mwdma_mask = ATA_MWDMA2;
> - ap->udma_mask = rate < 100000000 ? ATA_UDMA4 : ATA_UDMA5;
> - ap->flags |= ATA_FLAG_SLAVE_POSS;
> -
> - ap->ioaddr.data_addr = base + BK3710_TF_OFFSET;
> - ap->ioaddr.error_addr = base + BK3710_TF_OFFSET + 1;
> - ap->ioaddr.feature_addr = base + BK3710_TF_OFFSET + 1;
> - ap->ioaddr.nsect_addr = base + BK3710_TF_OFFSET + 2;
> - ap->ioaddr.lbal_addr = base + BK3710_TF_OFFSET + 3;
> - ap->ioaddr.lbam_addr = base + BK3710_TF_OFFSET + 4;
> - ap->ioaddr.lbah_addr = base + BK3710_TF_OFFSET + 5;
> - ap->ioaddr.device_addr = base + BK3710_TF_OFFSET + 6;
> - ap->ioaddr.status_addr = base + BK3710_TF_OFFSET + 7;
> - ap->ioaddr.command_addr = base + BK3710_TF_OFFSET + 7;
> -
> - ap->ioaddr.altstatus_addr = base + BK3710_CTL_OFFSET;
> - ap->ioaddr.ctl_addr = base + BK3710_CTL_OFFSET;
> -
> - ap->ioaddr.bmdma_addr = base;
> -
> - ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx",
> - (unsigned long)base + BK3710_TF_OFFSET,
> - (unsigned long)base + BK3710_CTL_OFFSET);
> -
> - /* activate */
> - return ata_host_activate(host, irq, ata_sff_interrupt, 0,
> - &pata_bk3710_sht);
> -}
> -
> -/* work with hotplug and coldplug */
> -MODULE_ALIAS("platform:palm_bk3710");
> -
> -static struct platform_driver pata_bk3710_driver = {
> - .driver = {
> - .name = "palm_bk3710",
> - },
> -};
> -
> -static int __init pata_bk3710_init(void)
> -{
> - return platform_driver_probe(&pata_bk3710_driver, pata_bk3710_probe);
> -}
> -
> -module_init(pata_bk3710_init);
> -MODULE_LICENSE("GPL v2");
--
Damien Le Moal
Western Digital Research
^ permalink raw reply [flat|nested] 48+ messages in thread* Re: [PATCH 11/14] pata: remove palmchip bk3710 driver
2022-10-19 23:17 ` Damien Le Moal
@ 2022-10-20 7:09 ` Arnd Bergmann
0 siblings, 0 replies; 48+ messages in thread
From: Arnd Bergmann @ 2022-10-20 7:09 UTC (permalink / raw)
To: Damien Le Moal, Arnd Bergmann, Sekhar Nori, Bartosz Golaszewski,
linux-arm-kernel
Cc: linux-kernel, Kevin Hilman, Sergey Shtylyov, Hannes Reinecke, linux-ide
On Thu, Oct 20, 2022, at 01:17, Damien Le Moal wrote:
> On 10/20/22 00:29, Arnd Bergmann wrote:
>> From: Arnd Bergmann <arnd@arndb.de>
>>
>> This device was used only on the davinci dm644x platform that
>> is now gone, and no references to the device remain in the
>> kernel.
>>
>> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
>
> Great, one less pata/ide driver !
> I can queue this in ata tree. I do have some changes in ata Kconfig queued
> already, but they should not conflict.
I have two more patches coming today: the palmld and samsung_cf drivers.
You can apply all three as they come in, otherwise I'll
just keep them in my tree along with the arch/arm/ boardfile
removal.
Arnd
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 11/14] pata: remove palmchip bk3710 driver
2022-10-19 15:29 ` [PATCH 11/14] pata: remove palmchip bk3710 driver Arnd Bergmann
2022-10-19 23:17 ` Damien Le Moal
@ 2022-10-20 11:02 ` Sergey Shtylyov
2022-10-20 11:18 ` Bartosz Golaszewski
2022-10-20 23:03 ` Damien Le Moal
3 siblings, 0 replies; 48+ messages in thread
From: Sergey Shtylyov @ 2022-10-20 11:02 UTC (permalink / raw)
To: Arnd Bergmann, Sekhar Nori, Bartosz Golaszewski,
linux-arm-kernel, Damien Le Moal
Cc: linux-kernel, Kevin Hilman, Arnd Bergmann, Hannes Reinecke, linux-ide
On 10/19/22 6:29 PM, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> This device was used only on the davinci dm644x platform that
Well, DM646x too but...
> is now gone, and no references to the device remain in the
> kernel.
... in fact, I'm not seeing davinci_init_ide() called anywhere... :-/
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Sergey Shtylyov <s.shtylyov@omp.ru>
[...]
MBR, Sergey
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 11/14] pata: remove palmchip bk3710 driver
2022-10-19 15:29 ` [PATCH 11/14] pata: remove palmchip bk3710 driver Arnd Bergmann
2022-10-19 23:17 ` Damien Le Moal
2022-10-20 11:02 ` Sergey Shtylyov
@ 2022-10-20 11:18 ` Bartosz Golaszewski
2022-10-20 23:03 ` Damien Le Moal
3 siblings, 0 replies; 48+ messages in thread
From: Bartosz Golaszewski @ 2022-10-20 11:18 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Sekhar Nori, linux-arm-kernel, Damien Le Moal, linux-kernel,
Kevin Hilman, Arnd Bergmann, Sergey Shtylyov, Hannes Reinecke,
linux-ide
On Wed, Oct 19, 2022 at 5:38 PM Arnd Bergmann <arnd@kernel.org> wrote:
>
> From: Arnd Bergmann <arnd@arndb.de>
>
> This device was used only on the davinci dm644x platform that
> is now gone, and no references to the device remain in the
> kernel.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 11/14] pata: remove palmchip bk3710 driver
2022-10-19 15:29 ` [PATCH 11/14] pata: remove palmchip bk3710 driver Arnd Bergmann
` (2 preceding siblings ...)
2022-10-20 11:18 ` Bartosz Golaszewski
@ 2022-10-20 23:03 ` Damien Le Moal
3 siblings, 0 replies; 48+ messages in thread
From: Damien Le Moal @ 2022-10-20 23:03 UTC (permalink / raw)
To: Arnd Bergmann, Sekhar Nori, Bartosz Golaszewski, linux-arm-kernel
Cc: linux-kernel, Kevin Hilman, Arnd Bergmann, Sergey Shtylyov,
Hannes Reinecke, linux-ide
On 10/20/22 00:29, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> This device was used only on the davinci dm644x platform that
> is now gone, and no references to the device remain in the
> kernel.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Applied to libata tree for-6.2 branch (and for-next).
Note that I fixed-up the patch title to:
ata: remove palmchip pata_bk3710 driver
Thanks !
> ---
> drivers/ata/Kconfig | 10 -
> drivers/ata/Makefile | 1 -
> drivers/ata/pata_bk3710.c | 380 --------------------------------------
> 3 files changed, 391 deletions(-)
> delete mode 100644 drivers/ata/pata_bk3710.c
>
> diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
> index 36833a862998..2986fc9c797e 100644
> --- a/drivers/ata/Kconfig
> +++ b/drivers/ata/Kconfig
> @@ -609,16 +609,6 @@ config PATA_ATP867X
>
> If unsure, say N.
>
> -config PATA_BK3710
> - tristate "Palmchip BK3710 PATA support"
> - depends on ARCH_DAVINCI || COMPILE_TEST
> - select PATA_TIMINGS
> - help
> - This option enables support for the integrated IDE controller on
> - the TI DaVinci SoC.
> -
> - If unsure, say N.
> -
> config PATA_CMD64X
> tristate "CMD64x PATA support"
> depends on PCI
> diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
> index 34623365d9a6..d2e36d367274 100644
> --- a/drivers/ata/Makefile
> +++ b/drivers/ata/Makefile
> @@ -54,7 +54,6 @@ obj-$(CONFIG_PATA_AMD) += pata_amd.o
> obj-$(CONFIG_PATA_ARTOP) += pata_artop.o
> obj-$(CONFIG_PATA_ATIIXP) += pata_atiixp.o
> obj-$(CONFIG_PATA_ATP867X) += pata_atp867x.o
> -obj-$(CONFIG_PATA_BK3710) += pata_bk3710.o
> obj-$(CONFIG_PATA_CMD64X) += pata_cmd64x.o
> obj-$(CONFIG_PATA_CS5520) += pata_cs5520.o
> obj-$(CONFIG_PATA_CS5530) += pata_cs5530.o
> diff --git a/drivers/ata/pata_bk3710.c b/drivers/ata/pata_bk3710.c
> deleted file mode 100644
> index fad95cfecced..000000000000
> --- a/drivers/ata/pata_bk3710.c
> +++ /dev/null
> @@ -1,380 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0
> -
> -/*
> - * Palmchip BK3710 PATA controller driver
> - *
> - * Copyright (c) 2017 Samsung Electronics Co., Ltd.
> - * http://www.samsung.com
> - *
> - * Based on palm_bk3710.c:
> - *
> - * Copyright (C) 2006 Texas Instruments.
> - * Copyright (C) 2007 MontaVista Software, Inc., <source@mvista.com>
> - */
> -
> -#include <linux/ata.h>
> -#include <linux/clk.h>
> -#include <linux/delay.h>
> -#include <linux/init.h>
> -#include <linux/ioport.h>
> -#include <linux/kernel.h>
> -#include <linux/libata.h>
> -#include <linux/module.h>
> -#include <linux/platform_device.h>
> -#include <linux/types.h>
> -
> -#define DRV_NAME "pata_bk3710"
> -
> -#define BK3710_TF_OFFSET 0x1F0
> -#define BK3710_CTL_OFFSET 0x3F6
> -
> -#define BK3710_BMISP 0x02
> -#define BK3710_IDETIMP 0x40
> -#define BK3710_UDMACTL 0x48
> -#define BK3710_MISCCTL 0x50
> -#define BK3710_REGSTB 0x54
> -#define BK3710_REGRCVR 0x58
> -#define BK3710_DATSTB 0x5C
> -#define BK3710_DATRCVR 0x60
> -#define BK3710_DMASTB 0x64
> -#define BK3710_DMARCVR 0x68
> -#define BK3710_UDMASTB 0x6C
> -#define BK3710_UDMATRP 0x70
> -#define BK3710_UDMAENV 0x74
> -#define BK3710_IORDYTMP 0x78
> -
> -static struct scsi_host_template pata_bk3710_sht = {
> - ATA_BMDMA_SHT(DRV_NAME),
> -};
> -
> -static unsigned int ideclk_period; /* in nanoseconds */
> -
> -struct pata_bk3710_udmatiming {
> - unsigned int rptime; /* tRP -- Ready to pause time (nsec) */
> - unsigned int cycletime; /* tCYCTYP2/2 -- avg Cycle Time (nsec) */
> - /* tENV is always a minimum of 20 nsec */
> -};
> -
> -static const struct pata_bk3710_udmatiming pata_bk3710_udmatimings[6] = {
> - { 160, 240 / 2 }, /* UDMA Mode 0 */
> - { 125, 160 / 2 }, /* UDMA Mode 1 */
> - { 100, 120 / 2 }, /* UDMA Mode 2 */
> - { 100, 90 / 2 }, /* UDMA Mode 3 */
> - { 100, 60 / 2 }, /* UDMA Mode 4 */
> - { 85, 40 / 2 }, /* UDMA Mode 5 */
> -};
> -
> -static void pata_bk3710_setudmamode(void __iomem *base, unsigned int dev,
> - unsigned int mode)
> -{
> - u32 val32;
> - u16 val16;
> - u8 tenv, trp, t0;
> -
> - /* DMA Data Setup */
> - t0 = DIV_ROUND_UP(pata_bk3710_udmatimings[mode].cycletime,
> - ideclk_period) - 1;
> - tenv = DIV_ROUND_UP(20, ideclk_period) - 1;
> - trp = DIV_ROUND_UP(pata_bk3710_udmatimings[mode].rptime,
> - ideclk_period) - 1;
> -
> - /* udmastb Ultra DMA Access Strobe Width */
> - val32 = ioread32(base + BK3710_UDMASTB) & (0xFF << (dev ? 0 : 8));
> - val32 |= t0 << (dev ? 8 : 0);
> - iowrite32(val32, base + BK3710_UDMASTB);
> -
> - /* udmatrp Ultra DMA Ready to Pause Time */
> - val32 = ioread32(base + BK3710_UDMATRP) & (0xFF << (dev ? 0 : 8));
> - val32 |= trp << (dev ? 8 : 0);
> - iowrite32(val32, base + BK3710_UDMATRP);
> -
> - /* udmaenv Ultra DMA envelop Time */
> - val32 = ioread32(base + BK3710_UDMAENV) & (0xFF << (dev ? 0 : 8));
> - val32 |= tenv << (dev ? 8 : 0);
> - iowrite32(val32, base + BK3710_UDMAENV);
> -
> - /* Enable UDMA for Device */
> - val16 = ioread16(base + BK3710_UDMACTL) | (1 << dev);
> - iowrite16(val16, base + BK3710_UDMACTL);
> -}
> -
> -static void pata_bk3710_setmwdmamode(void __iomem *base, unsigned int dev,
> - unsigned short min_cycle,
> - unsigned int mode)
> -{
> - const struct ata_timing *t;
> - int cycletime;
> - u32 val32;
> - u16 val16;
> - u8 td, tkw, t0;
> -
> - t = ata_timing_find_mode(mode);
> - cycletime = max_t(int, t->cycle, min_cycle);
> -
> - /* DMA Data Setup */
> - t0 = DIV_ROUND_UP(cycletime, ideclk_period);
> - td = DIV_ROUND_UP(t->active, ideclk_period);
> - tkw = t0 - td - 1;
> - td--;
> -
> - val32 = ioread32(base + BK3710_DMASTB) & (0xFF << (dev ? 0 : 8));
> - val32 |= td << (dev ? 8 : 0);
> - iowrite32(val32, base + BK3710_DMASTB);
> -
> - val32 = ioread32(base + BK3710_DMARCVR) & (0xFF << (dev ? 0 : 8));
> - val32 |= tkw << (dev ? 8 : 0);
> - iowrite32(val32, base + BK3710_DMARCVR);
> -
> - /* Disable UDMA for Device */
> - val16 = ioread16(base + BK3710_UDMACTL) & ~(1 << dev);
> - iowrite16(val16, base + BK3710_UDMACTL);
> -}
> -
> -static void pata_bk3710_set_dmamode(struct ata_port *ap,
> - struct ata_device *adev)
> -{
> - void __iomem *base = (void __iomem *)ap->ioaddr.bmdma_addr;
> - int is_slave = adev->devno;
> - const u8 xferspeed = adev->dma_mode;
> -
> - if (xferspeed >= XFER_UDMA_0)
> - pata_bk3710_setudmamode(base, is_slave,
> - xferspeed - XFER_UDMA_0);
> - else
> - pata_bk3710_setmwdmamode(base, is_slave,
> - adev->id[ATA_ID_EIDE_DMA_MIN],
> - xferspeed);
> -}
> -
> -static void pata_bk3710_setpiomode(void __iomem *base, struct ata_device *pair,
> - unsigned int dev, unsigned int cycletime,
> - unsigned int mode)
> -{
> - const struct ata_timing *t;
> - u32 val32;
> - u8 t2, t2i, t0;
> -
> - t = ata_timing_find_mode(XFER_PIO_0 + mode);
> -
> - /* PIO Data Setup */
> - t0 = DIV_ROUND_UP(cycletime, ideclk_period);
> - t2 = DIV_ROUND_UP(t->active, ideclk_period);
> -
> - t2i = t0 - t2 - 1;
> - t2--;
> -
> - val32 = ioread32(base + BK3710_DATSTB) & (0xFF << (dev ? 0 : 8));
> - val32 |= t2 << (dev ? 8 : 0);
> - iowrite32(val32, base + BK3710_DATSTB);
> -
> - val32 = ioread32(base + BK3710_DATRCVR) & (0xFF << (dev ? 0 : 8));
> - val32 |= t2i << (dev ? 8 : 0);
> - iowrite32(val32, base + BK3710_DATRCVR);
> -
> - /* FIXME: this is broken also in the old driver */
> - if (pair) {
> - u8 mode2 = pair->pio_mode - XFER_PIO_0;
> -
> - if (mode2 < mode)
> - mode = mode2;
> - }
> -
> - /* TASKFILE Setup */
> - t0 = DIV_ROUND_UP(t->cyc8b, ideclk_period);
> - t2 = DIV_ROUND_UP(t->act8b, ideclk_period);
> -
> - t2i = t0 - t2 - 1;
> - t2--;
> -
> - val32 = ioread32(base + BK3710_REGSTB) & (0xFF << (dev ? 0 : 8));
> - val32 |= t2 << (dev ? 8 : 0);
> - iowrite32(val32, base + BK3710_REGSTB);
> -
> - val32 = ioread32(base + BK3710_REGRCVR) & (0xFF << (dev ? 0 : 8));
> - val32 |= t2i << (dev ? 8 : 0);
> - iowrite32(val32, base + BK3710_REGRCVR);
> -}
> -
> -static void pata_bk3710_set_piomode(struct ata_port *ap,
> - struct ata_device *adev)
> -{
> - void __iomem *base = (void __iomem *)ap->ioaddr.bmdma_addr;
> - struct ata_device *pair = ata_dev_pair(adev);
> - const struct ata_timing *t = ata_timing_find_mode(adev->pio_mode);
> - const u16 *id = adev->id;
> - unsigned int cycle_time = 0;
> - int is_slave = adev->devno;
> - const u8 pio = adev->pio_mode - XFER_PIO_0;
> -
> - if (id[ATA_ID_FIELD_VALID] & 2) {
> - if (ata_id_has_iordy(id))
> - cycle_time = id[ATA_ID_EIDE_PIO_IORDY];
> - else
> - cycle_time = id[ATA_ID_EIDE_PIO];
> -
> - /* conservative "downgrade" for all pre-ATA2 drives */
> - if (pio < 3 && cycle_time < t->cycle)
> - cycle_time = 0; /* use standard timing */
> - }
> -
> - if (!cycle_time)
> - cycle_time = t->cycle;
> -
> - pata_bk3710_setpiomode(base, pair, is_slave, cycle_time, pio);
> -}
> -
> -static void pata_bk3710_chipinit(void __iomem *base)
> -{
> - /*
> - * REVISIT: the ATA reset signal needs to be managed through a
> - * GPIO, which means it should come from platform_data. Until
> - * we get and use such information, we have to trust that things
> - * have been reset before we get here.
> - */
> -
> - /*
> - * Program the IDETIMP Register Value based on the following assumptions
> - *
> - * (ATA_IDETIMP_IDEEN , ENABLE ) |
> - * (ATA_IDETIMP_PREPOST1 , DISABLE) |
> - * (ATA_IDETIMP_PREPOST0 , DISABLE) |
> - *
> - * DM6446 silicon rev 2.1 and earlier have no observed net benefit
> - * from enabling prefetch/postwrite.
> - */
> - iowrite16(BIT(15), base + BK3710_IDETIMP);
> -
> - /*
> - * UDMACTL Ultra-ATA DMA Control
> - * (ATA_UDMACTL_UDMAP1 , 0 ) |
> - * (ATA_UDMACTL_UDMAP0 , 0 )
> - *
> - */
> - iowrite16(0, base + BK3710_UDMACTL);
> -
> - /*
> - * MISCCTL Miscellaneous Conrol Register
> - * (ATA_MISCCTL_HWNHLD1P , 1 cycle)
> - * (ATA_MISCCTL_HWNHLD0P , 1 cycle)
> - * (ATA_MISCCTL_TIMORIDE , 1)
> - */
> - iowrite32(0x001, base + BK3710_MISCCTL);
> -
> - /*
> - * IORDYTMP IORDY Timer for Primary Register
> - * (ATA_IORDYTMP_IORDYTMP , DISABLE)
> - */
> - iowrite32(0, base + BK3710_IORDYTMP);
> -
> - /*
> - * Configure BMISP Register
> - * (ATA_BMISP_DMAEN1 , DISABLE ) |
> - * (ATA_BMISP_DMAEN0 , DISABLE ) |
> - * (ATA_BMISP_IORDYINT , CLEAR) |
> - * (ATA_BMISP_INTRSTAT , CLEAR) |
> - * (ATA_BMISP_DMAERROR , CLEAR)
> - */
> - iowrite16(0xE, base + BK3710_BMISP);
> -
> - pata_bk3710_setpiomode(base, NULL, 0, 600, 0);
> - pata_bk3710_setpiomode(base, NULL, 1, 600, 0);
> -}
> -
> -static struct ata_port_operations pata_bk3710_ports_ops = {
> - .inherits = &ata_bmdma_port_ops,
> - .cable_detect = ata_cable_80wire,
> -
> - .set_piomode = pata_bk3710_set_piomode,
> - .set_dmamode = pata_bk3710_set_dmamode,
> -};
> -
> -static int __init pata_bk3710_probe(struct platform_device *pdev)
> -{
> - struct clk *clk;
> - struct resource *mem;
> - struct ata_host *host;
> - struct ata_port *ap;
> - void __iomem *base;
> - unsigned long rate;
> - int irq;
> -
> - clk = devm_clk_get(&pdev->dev, NULL);
> - if (IS_ERR(clk))
> - return -ENODEV;
> -
> - clk_enable(clk);
> - rate = clk_get_rate(clk);
> - if (!rate)
> - return -EINVAL;
> -
> - /* NOTE: round *down* to meet minimum timings; we count in clocks */
> - ideclk_period = 1000000000UL / rate;
> -
> - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> -
> - irq = platform_get_irq(pdev, 0);
> - if (irq < 0) {
> - pr_err(DRV_NAME ": failed to get IRQ resource\n");
> - return irq;
> - }
> -
> - base = devm_ioremap_resource(&pdev->dev, mem);
> - if (IS_ERR(base))
> - return PTR_ERR(base);
> -
> - /* configure the Palmchip controller */
> - pata_bk3710_chipinit(base);
> -
> - /* allocate host */
> - host = ata_host_alloc(&pdev->dev, 1);
> - if (!host)
> - return -ENOMEM;
> - ap = host->ports[0];
> -
> - ap->ops = &pata_bk3710_ports_ops;
> - ap->pio_mask = ATA_PIO4;
> - ap->mwdma_mask = ATA_MWDMA2;
> - ap->udma_mask = rate < 100000000 ? ATA_UDMA4 : ATA_UDMA5;
> - ap->flags |= ATA_FLAG_SLAVE_POSS;
> -
> - ap->ioaddr.data_addr = base + BK3710_TF_OFFSET;
> - ap->ioaddr.error_addr = base + BK3710_TF_OFFSET + 1;
> - ap->ioaddr.feature_addr = base + BK3710_TF_OFFSET + 1;
> - ap->ioaddr.nsect_addr = base + BK3710_TF_OFFSET + 2;
> - ap->ioaddr.lbal_addr = base + BK3710_TF_OFFSET + 3;
> - ap->ioaddr.lbam_addr = base + BK3710_TF_OFFSET + 4;
> - ap->ioaddr.lbah_addr = base + BK3710_TF_OFFSET + 5;
> - ap->ioaddr.device_addr = base + BK3710_TF_OFFSET + 6;
> - ap->ioaddr.status_addr = base + BK3710_TF_OFFSET + 7;
> - ap->ioaddr.command_addr = base + BK3710_TF_OFFSET + 7;
> -
> - ap->ioaddr.altstatus_addr = base + BK3710_CTL_OFFSET;
> - ap->ioaddr.ctl_addr = base + BK3710_CTL_OFFSET;
> -
> - ap->ioaddr.bmdma_addr = base;
> -
> - ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx",
> - (unsigned long)base + BK3710_TF_OFFSET,
> - (unsigned long)base + BK3710_CTL_OFFSET);
> -
> - /* activate */
> - return ata_host_activate(host, irq, ata_sff_interrupt, 0,
> - &pata_bk3710_sht);
> -}
> -
> -/* work with hotplug and coldplug */
> -MODULE_ALIAS("platform:palm_bk3710");
> -
> -static struct platform_driver pata_bk3710_driver = {
> - .driver = {
> - .name = "palm_bk3710",
> - },
> -};
> -
> -static int __init pata_bk3710_init(void)
> -{
> - return platform_driver_probe(&pata_bk3710_driver, pata_bk3710_probe);
> -}
> -
> -module_init(pata_bk3710_init);
> -MODULE_LICENSE("GPL v2");
--
Damien Le Moal
Western Digital Research
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH 12/14] irqchip: remove davinci aintc driver
2022-10-19 15:29 [PATCH 00/14] ARM: remove unused davinci board & drivers Arnd Bergmann
` (10 preceding siblings ...)
2022-10-19 15:29 ` [PATCH 11/14] pata: remove palmchip bk3710 driver Arnd Bergmann
@ 2022-10-19 15:29 ` Arnd Bergmann
2022-10-20 11:33 ` Bartosz Golaszewski
2022-10-19 15:29 ` [PATCH 13/14] staging: media: remove davinci vpfe_capture driver Arnd Bergmann
` (4 subsequent siblings)
16 siblings, 1 reply; 48+ messages in thread
From: Arnd Bergmann @ 2022-10-19 15:29 UTC (permalink / raw)
To: Sekhar Nori, Bartosz Golaszewski, linux-arm-kernel,
Thomas Gleixner, Marc Zyngier
Cc: linux-kernel, Kevin Hilman, Arnd Bergmann
From: Arnd Bergmann <arnd@arndb.de>
The aintc driver was used on Davinci DM3xx and DM64xx SoCs, all of
which got dropped from Linux, so this driver is orphaned as well.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
drivers/irqchip/Kconfig | 5 -
drivers/irqchip/Makefile | 1 -
drivers/irqchip/irq-davinci-aintc.c | 163 ----------------------------
3 files changed, 169 deletions(-)
delete mode 100644 drivers/irqchip/irq-davinci-aintc.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 7ef9f5e696d3..c9bb2ccf4044 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -136,11 +136,6 @@ config BRCMSTB_L2_IRQ
select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
-config DAVINCI_AINTC
- bool
- select GENERIC_IRQ_CHIP
- select IRQ_DOMAIN
-
config DAVINCI_CP_INTC
bool
select GENERIC_IRQ_CHIP
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 87b49a10962c..ffd945fe71aa 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -8,7 +8,6 @@ obj-$(CONFIG_ATH79) += irq-ath79-misc.o
obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
obj-$(CONFIG_ARCH_ACTIONS) += irq-owl-sirq.o
-obj-$(CONFIG_DAVINCI_AINTC) += irq-davinci-aintc.o
obj-$(CONFIG_DAVINCI_CP_INTC) += irq-davinci-cp-intc.o
obj-$(CONFIG_EXYNOS_IRQ_COMBINER) += exynos-combiner.o
obj-$(CONFIG_FARADAY_FTINTC010) += irq-ftintc010.o
diff --git a/drivers/irqchip/irq-davinci-aintc.c b/drivers/irqchip/irq-davinci-aintc.c
deleted file mode 100644
index 123eb7bfc117..000000000000
--- a/drivers/irqchip/irq-davinci-aintc.c
+++ /dev/null
@@ -1,163 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-//
-// Copyright (C) 2006, 2019 Texas Instruments.
-//
-// Interrupt handler for DaVinci boards.
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/irqchip/irq-davinci-aintc.h>
-#include <linux/io.h>
-#include <linux/irqdomain.h>
-
-#include <asm/exception.h>
-
-#define DAVINCI_AINTC_FIQ_REG0 0x00
-#define DAVINCI_AINTC_FIQ_REG1 0x04
-#define DAVINCI_AINTC_IRQ_REG0 0x08
-#define DAVINCI_AINTC_IRQ_REG1 0x0c
-#define DAVINCI_AINTC_IRQ_IRQENTRY 0x14
-#define DAVINCI_AINTC_IRQ_ENT_REG0 0x18
-#define DAVINCI_AINTC_IRQ_ENT_REG1 0x1c
-#define DAVINCI_AINTC_IRQ_INCTL_REG 0x20
-#define DAVINCI_AINTC_IRQ_EABASE_REG 0x24
-#define DAVINCI_AINTC_IRQ_INTPRI0_REG 0x30
-#define DAVINCI_AINTC_IRQ_INTPRI7_REG 0x4c
-
-static void __iomem *davinci_aintc_base;
-static struct irq_domain *davinci_aintc_irq_domain;
-
-static inline void davinci_aintc_writel(unsigned long value, int offset)
-{
- writel_relaxed(value, davinci_aintc_base + offset);
-}
-
-static inline unsigned long davinci_aintc_readl(int offset)
-{
- return readl_relaxed(davinci_aintc_base + offset);
-}
-
-static __init void
-davinci_aintc_setup_gc(void __iomem *base,
- unsigned int irq_start, unsigned int num)
-{
- struct irq_chip_generic *gc;
- struct irq_chip_type *ct;
-
- gc = irq_get_domain_generic_chip(davinci_aintc_irq_domain, irq_start);
- gc->reg_base = base;
- gc->irq_base = irq_start;
-
- ct = gc->chip_types;
- ct->chip.irq_ack = irq_gc_ack_set_bit;
- ct->chip.irq_mask = irq_gc_mask_clr_bit;
- ct->chip.irq_unmask = irq_gc_mask_set_bit;
-
- ct->regs.ack = DAVINCI_AINTC_IRQ_REG0;
- ct->regs.mask = DAVINCI_AINTC_IRQ_ENT_REG0;
- irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
- IRQ_NOREQUEST | IRQ_NOPROBE, 0);
-}
-
-static asmlinkage void __exception_irq_entry
-davinci_aintc_handle_irq(struct pt_regs *regs)
-{
- int irqnr = davinci_aintc_readl(DAVINCI_AINTC_IRQ_IRQENTRY);
-
- /*
- * Use the formula for entry vector index generation from section
- * 8.3.3 of the manual.
- */
- irqnr >>= 2;
- irqnr -= 1;
-
- generic_handle_domain_irq(davinci_aintc_irq_domain, irqnr);
-}
-
-/* ARM Interrupt Controller Initialization */
-void __init davinci_aintc_init(const struct davinci_aintc_config *config)
-{
- unsigned int irq_off, reg_off, prio, shift;
- void __iomem *req;
- int ret, irq_base;
- const u8 *prios;
-
- req = request_mem_region(config->reg.start,
- resource_size(&config->reg),
- "davinci-cp-intc");
- if (!req) {
- pr_err("%s: register range busy\n", __func__);
- return;
- }
-
- davinci_aintc_base = ioremap(config->reg.start,
- resource_size(&config->reg));
- if (!davinci_aintc_base) {
- pr_err("%s: unable to ioremap register range\n", __func__);
- return;
- }
-
- /* Clear all interrupt requests */
- davinci_aintc_writel(~0x0, DAVINCI_AINTC_FIQ_REG0);
- davinci_aintc_writel(~0x0, DAVINCI_AINTC_FIQ_REG1);
- davinci_aintc_writel(~0x0, DAVINCI_AINTC_IRQ_REG0);
- davinci_aintc_writel(~0x0, DAVINCI_AINTC_IRQ_REG1);
-
- /* Disable all interrupts */
- davinci_aintc_writel(0x0, DAVINCI_AINTC_IRQ_ENT_REG0);
- davinci_aintc_writel(0x0, DAVINCI_AINTC_IRQ_ENT_REG1);
-
- /* Interrupts disabled immediately, IRQ entry reflects all */
- davinci_aintc_writel(0x0, DAVINCI_AINTC_IRQ_INCTL_REG);
-
- /* we don't use the hardware vector table, just its entry addresses */
- davinci_aintc_writel(0, DAVINCI_AINTC_IRQ_EABASE_REG);
-
- /* Clear all interrupt requests */
- davinci_aintc_writel(~0x0, DAVINCI_AINTC_FIQ_REG0);
- davinci_aintc_writel(~0x0, DAVINCI_AINTC_FIQ_REG1);
- davinci_aintc_writel(~0x0, DAVINCI_AINTC_IRQ_REG0);
- davinci_aintc_writel(~0x0, DAVINCI_AINTC_IRQ_REG1);
-
- prios = config->prios;
- for (reg_off = DAVINCI_AINTC_IRQ_INTPRI0_REG;
- reg_off <= DAVINCI_AINTC_IRQ_INTPRI7_REG; reg_off += 4) {
- for (shift = 0, prio = 0; shift < 32; shift += 4, prios++)
- prio |= (*prios & 0x07) << shift;
- davinci_aintc_writel(prio, reg_off);
- }
-
- irq_base = irq_alloc_descs(-1, 0, config->num_irqs, 0);
- if (irq_base < 0) {
- pr_err("%s: unable to allocate interrupt descriptors: %d\n",
- __func__, irq_base);
- return;
- }
-
- davinci_aintc_irq_domain = irq_domain_add_legacy(NULL,
- config->num_irqs, irq_base, 0,
- &irq_domain_simple_ops, NULL);
- if (!davinci_aintc_irq_domain) {
- pr_err("%s: unable to create interrupt domain\n", __func__);
- return;
- }
-
- ret = irq_alloc_domain_generic_chips(davinci_aintc_irq_domain, 32, 1,
- "AINTC", handle_edge_irq,
- IRQ_NOREQUEST | IRQ_NOPROBE, 0, 0);
- if (ret) {
- pr_err("%s: unable to allocate generic irq chips for domain\n",
- __func__);
- return;
- }
-
- for (irq_off = 0, reg_off = 0;
- irq_off < config->num_irqs;
- irq_off += 32, reg_off += 0x04)
- davinci_aintc_setup_gc(davinci_aintc_base + reg_off,
- irq_base + irq_off, 32);
-
- set_handle_irq(davinci_aintc_handle_irq);
-}
--
2.29.2
^ permalink raw reply related [flat|nested] 48+ messages in thread* Re: [PATCH 12/14] irqchip: remove davinci aintc driver
2022-10-19 15:29 ` [PATCH 12/14] irqchip: remove davinci aintc driver Arnd Bergmann
@ 2022-10-20 11:33 ` Bartosz Golaszewski
0 siblings, 0 replies; 48+ messages in thread
From: Bartosz Golaszewski @ 2022-10-20 11:33 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Sekhar Nori, linux-arm-kernel, Thomas Gleixner, Marc Zyngier,
linux-kernel, Kevin Hilman, Arnd Bergmann
On Wed, Oct 19, 2022 at 5:38 PM Arnd Bergmann <arnd@kernel.org> wrote:
>
> From: Arnd Bergmann <arnd@arndb.de>
>
> The aintc driver was used on Davinci DM3xx and DM64xx SoCs, all of
> which got dropped from Linux, so this driver is orphaned as well.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH 13/14] staging: media: remove davinci vpfe_capture driver
2022-10-19 15:29 [PATCH 00/14] ARM: remove unused davinci board & drivers Arnd Bergmann
` (11 preceding siblings ...)
2022-10-19 15:29 ` [PATCH 12/14] irqchip: remove davinci aintc driver Arnd Bergmann
@ 2022-10-19 15:29 ` Arnd Bergmann
2022-10-20 15:39 ` Greg Kroah-Hartman
` (2 more replies)
2022-10-19 15:29 ` [PATCH 14/14] media: davinci: remove vpbe support Arnd Bergmann
` (3 subsequent siblings)
16 siblings, 3 replies; 48+ messages in thread
From: Arnd Bergmann @ 2022-10-19 15:29 UTC (permalink / raw)
To: Sekhar Nori, Bartosz Golaszewski, linux-arm-kernel,
Mauro Carvalho Chehab, Greg Kroah-Hartman, Lad, Prabhakar
Cc: linux-kernel, Kevin Hilman, Arnd Bergmann, linux-media, linux-staging
From: Arnd Bergmann <arnd@arndb.de>
This driver was for the davinci dm644x and dm3xx platforms that are
now removed from the kernel, so there are no more users.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
MAINTAINERS | 1 -
drivers/staging/media/Kconfig | 1 -
drivers/staging/media/Makefile | 1 -
.../media/deprecated/vpfe_capture/Kconfig | 58 -
.../media/deprecated/vpfe_capture/Makefile | 4 -
.../media/deprecated/vpfe_capture/TODO | 7 -
.../deprecated/vpfe_capture/ccdc_hw_device.h | 80 -
.../deprecated/vpfe_capture/dm355_ccdc.c | 934 --------
.../deprecated/vpfe_capture/dm355_ccdc.h | 308 ---
.../deprecated/vpfe_capture/dm355_ccdc_regs.h | 297 ---
.../deprecated/vpfe_capture/dm644x_ccdc.c | 879 --------
.../deprecated/vpfe_capture/dm644x_ccdc.h | 171 --
.../vpfe_capture/dm644x_ccdc_regs.h | 140 --
.../media/deprecated/vpfe_capture/isif.c | 1127 ----------
.../media/deprecated/vpfe_capture/isif.h | 518 -----
.../media/deprecated/vpfe_capture/isif_regs.h | 256 ---
.../deprecated/vpfe_capture/vpfe_capture.c | 1902 -----------------
include/media/davinci/vpfe_capture.h | 177 --
18 files changed, 6861 deletions(-)
delete mode 100644 drivers/staging/media/deprecated/vpfe_capture/Kconfig
delete mode 100644 drivers/staging/media/deprecated/vpfe_capture/Makefile
delete mode 100644 drivers/staging/media/deprecated/vpfe_capture/TODO
delete mode 100644 drivers/staging/media/deprecated/vpfe_capture/ccdc_hw_device.h
delete mode 100644 drivers/staging/media/deprecated/vpfe_capture/dm355_ccdc.c
delete mode 100644 drivers/staging/media/deprecated/vpfe_capture/dm355_ccdc.h
delete mode 100644 drivers/staging/media/deprecated/vpfe_capture/dm355_ccdc_regs.h
delete mode 100644 drivers/staging/media/deprecated/vpfe_capture/dm644x_ccdc.c
delete mode 100644 drivers/staging/media/deprecated/vpfe_capture/dm644x_ccdc.h
delete mode 100644 drivers/staging/media/deprecated/vpfe_capture/dm644x_ccdc_regs.h
delete mode 100644 drivers/staging/media/deprecated/vpfe_capture/isif.c
delete mode 100644 drivers/staging/media/deprecated/vpfe_capture/isif.h
delete mode 100644 drivers/staging/media/deprecated/vpfe_capture/isif_regs.h
delete mode 100644 drivers/staging/media/deprecated/vpfe_capture/vpfe_capture.c
delete mode 100644 include/media/davinci/vpfe_capture.h
diff --git a/MAINTAINERS b/MAINTAINERS
index bb3e20381128..5f18c0264e98 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20491,7 +20491,6 @@ W: https://linuxtv.org
Q: http://patchwork.linuxtv.org/project/linux-media/list/
T: git git://linuxtv.org/mhadli/v4l-dvb-davinci_devices.git
F: drivers/media/platform/ti/davinci/
-F: drivers/staging/media/deprecated/vpfe_capture/
F: include/media/davinci/
TI ENHANCED CAPTURE (eCAP) DRIVER
diff --git a/drivers/staging/media/Kconfig b/drivers/staging/media/Kconfig
index d4f03b203ae5..ddab8e0a0809 100644
--- a/drivers/staging/media/Kconfig
+++ b/drivers/staging/media/Kconfig
@@ -57,7 +57,6 @@ source "drivers/staging/media/deprecated/meye/Kconfig"
source "drivers/staging/media/deprecated/saa7146/Kconfig"
source "drivers/staging/media/deprecated/stkwebcam/Kconfig"
source "drivers/staging/media/deprecated/tm6000/Kconfig"
-source "drivers/staging/media/deprecated/vpfe_capture/Kconfig"
source "drivers/staging/media/deprecated/zr364xx/Kconfig"
endif
diff --git a/drivers/staging/media/Makefile b/drivers/staging/media/Makefile
index a387692b84f2..38e6cdfea29c 100644
--- a/drivers/staging/media/Makefile
+++ b/drivers/staging/media/Makefile
@@ -14,5 +14,4 @@ obj-$(CONFIG_VIDEO_IPU3_IMGU) += ipu3/
obj-$(CONFIG_VIDEO_TM6000) += deprecated/tm6000/
obj-$(CONFIG_VIDEO_VIU) += deprecated/fsl-viu/
obj-$(CONFIG_USB_ZR364XX) += deprecated/zr364xx/
-obj-y += deprecated/vpfe_capture/
obj-y += deprecated/saa7146/
diff --git a/drivers/staging/media/deprecated/vpfe_capture/Kconfig b/drivers/staging/media/deprecated/vpfe_capture/Kconfig
deleted file mode 100644
index 10250e7e566b..000000000000
--- a/drivers/staging/media/deprecated/vpfe_capture/Kconfig
+++ /dev/null
@@ -1,58 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-config VIDEO_DM6446_CCDC
- tristate "TI DM6446 CCDC video capture driver"
- depends on V4L_PLATFORM_DRIVERS
- depends on VIDEO_DEV
- depends on ARCH_DAVINCI || COMPILE_TEST
- depends on I2C
- select VIDEOBUF_DMA_CONTIG
- help
- Enables DaVinci CCD hw module. DaVinci CCDC hw interfaces
- with decoder modules such as TVP5146 over BT656 or
- sensor module such as MT9T001 over a raw interface. This
- module configures the interface and CCDC/ISIF to do
- video frame capture from slave decoders.
-
- This driver is deprecated and is scheduled for removal by
- the beginning of 2023. See the TODO file for more information.
-
- To compile this driver as a module, choose M here. There will
- be two modules called vpfe_capture.ko and dm644x_ccdc.ko
-
-config VIDEO_DM355_CCDC
- tristate "TI DM355 CCDC video capture driver"
- depends on V4L_PLATFORM_DRIVERS
- depends on VIDEO_DEV
- depends on ARCH_DAVINCI || COMPILE_TEST
- depends on I2C
- select VIDEOBUF_DMA_CONTIG
- help
- Enables DM355 CCD hw module. DM355 CCDC hw interfaces
- with decoder modules such as TVP5146 over BT656 or
- sensor module such as MT9T001 over a raw interface. This
- module configures the interface and CCDC/ISIF to do
- video frame capture from a slave decoders
-
- This driver is deprecated and is scheduled for removal by
- the beginning of 2023. See the TODO file for more information.
-
- To compile this driver as a module, choose M here. There will
- be two modules called vpfe_capture.ko and dm355_ccdc.ko
-
-config VIDEO_DM365_ISIF
- tristate "TI DM365 ISIF video capture driver"
- depends on V4L_PLATFORM_DRIVERS
- depends on VIDEO_DEV
- depends on ARCH_DAVINCI || COMPILE_TEST
- depends on I2C
- select VIDEOBUF_DMA_CONTIG
- help
- Enables ISIF hw module. This is the hardware module for
- configuring ISIF in VPFE to capture Raw Bayer RGB data from
- a image sensor or YUV data from a YUV source.
-
- This driver is deprecated and is scheduled for removal by
- the beginning of 2023. See the TODO file for more information.
-
- To compile this driver as a module, choose M here. There will
- be two modules called vpfe_capture.ko and isif.ko
diff --git a/drivers/staging/media/deprecated/vpfe_capture/Makefile b/drivers/staging/media/deprecated/vpfe_capture/Makefile
deleted file mode 100644
index 609e8dc09ce7..000000000000
--- a/drivers/staging/media/deprecated/vpfe_capture/Makefile
+++ /dev/null
@@ -1,4 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_VIDEO_DM6446_CCDC) += vpfe_capture.o dm644x_ccdc.o
-obj-$(CONFIG_VIDEO_DM355_CCDC) += vpfe_capture.o dm355_ccdc.o
-obj-$(CONFIG_VIDEO_DM365_ISIF) += vpfe_capture.o isif.o
diff --git a/drivers/staging/media/deprecated/vpfe_capture/TODO b/drivers/staging/media/deprecated/vpfe_capture/TODO
deleted file mode 100644
index ce654d7337af..000000000000
--- a/drivers/staging/media/deprecated/vpfe_capture/TODO
+++ /dev/null
@@ -1,7 +0,0 @@
-These are one of the few drivers still not using the vb2
-framework, so these drivers are now deprecated with the intent of
-removing them altogether by the beginning of 2023.
-
-In order to keep these drivers they have to be converted to vb2.
-If someone is interested in doing this work, then contact the
-linux-media mailinglist (https://linuxtv.org/lists.php).
diff --git a/drivers/staging/media/deprecated/vpfe_capture/ccdc_hw_device.h b/drivers/staging/media/deprecated/vpfe_capture/ccdc_hw_device.h
deleted file mode 100644
index a545052a95a9..000000000000
--- a/drivers/staging/media/deprecated/vpfe_capture/ccdc_hw_device.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright (C) 2008-2009 Texas Instruments Inc
- *
- * ccdc device API
- */
-#ifndef _CCDC_HW_DEVICE_H
-#define _CCDC_HW_DEVICE_H
-
-#ifdef __KERNEL__
-#include <linux/videodev2.h>
-#include <linux/device.h>
-#include <media/davinci/vpfe_types.h>
-#include <media/davinci/ccdc_types.h>
-
-/*
- * ccdc hw operations
- */
-struct ccdc_hw_ops {
- /* Pointer to initialize function to initialize ccdc device */
- int (*open) (struct device *dev);
- /* Pointer to deinitialize function */
- int (*close) (struct device *dev);
- /* set ccdc base address */
- void (*set_ccdc_base)(void *base, int size);
- /* Pointer to function to enable or disable ccdc */
- void (*enable) (int en);
- /* reset sbl. only for 6446 */
- void (*reset) (void);
- /* enable output to sdram */
- void (*enable_out_to_sdram) (int en);
- /* Pointer to function to set hw parameters */
- int (*set_hw_if_params) (struct vpfe_hw_if_param *param);
- /* get interface parameters */
- int (*get_hw_if_params) (struct vpfe_hw_if_param *param);
- /* Pointer to function to configure ccdc */
- int (*configure) (void);
-
- /* Pointer to function to set buffer type */
- int (*set_buftype) (enum ccdc_buftype buf_type);
- /* Pointer to function to get buffer type */
- enum ccdc_buftype (*get_buftype) (void);
- /* Pointer to function to set frame format */
- int (*set_frame_format) (enum ccdc_frmfmt frm_fmt);
- /* Pointer to function to get frame format */
- enum ccdc_frmfmt (*get_frame_format) (void);
- /* enumerate hw pix formats */
- int (*enum_pix)(u32 *hw_pix, int i);
- /* Pointer to function to set buffer type */
- u32 (*get_pixel_format) (void);
- /* Pointer to function to get pixel format. */
- int (*set_pixel_format) (u32 pixfmt);
- /* Pointer to function to set image window */
- int (*set_image_window) (struct v4l2_rect *win);
- /* Pointer to function to set image window */
- void (*get_image_window) (struct v4l2_rect *win);
- /* Pointer to function to get line length */
- unsigned int (*get_line_length) (void);
-
- /* Pointer to function to set frame buffer address */
- void (*setfbaddr) (unsigned long addr);
- /* Pointer to function to get field id */
- int (*getfid) (void);
-};
-
-struct ccdc_hw_device {
- /* ccdc device name */
- char name[32];
- /* module owner */
- struct module *owner;
- /* hw ops */
- struct ccdc_hw_ops hw_ops;
-};
-
-/* Used by CCDC module to register & unregister with vpfe capture driver */
-int vpfe_register_ccdc_device(const struct ccdc_hw_device *dev);
-void vpfe_unregister_ccdc_device(const struct ccdc_hw_device *dev);
-
-#endif
-#endif
diff --git a/drivers/staging/media/deprecated/vpfe_capture/dm355_ccdc.c b/drivers/staging/media/deprecated/vpfe_capture/dm355_ccdc.c
deleted file mode 100644
index da8db53e9498..000000000000
--- a/drivers/staging/media/deprecated/vpfe_capture/dm355_ccdc.c
+++ /dev/null
@@ -1,934 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright (C) 2005-2009 Texas Instruments Inc
- *
- * CCDC hardware module for DM355
- * ------------------------------
- *
- * This module is for configuring DM355 CCD controller of VPFE to capture
- * Raw yuv or Bayer RGB data from a decoder. CCDC has several modules
- * such as Defect Pixel Correction, Color Space Conversion etc to
- * pre-process the Bayer RGB data, before writing it to SDRAM.
- *
- * TODO: 1) Raw bayer parameter settings and bayer capture
- * 2) Split module parameter structure to module specific ioctl structs
- * 3) add support for lense shading correction
- * 4) investigate if enum used for user space type definition
- * to be replaced by #defines or integer
- */
-#include <linux/platform_device.h>
-#include <linux/uaccess.h>
-#include <linux/videodev2.h>
-#include <linux/err.h>
-#include <linux/module.h>
-
-#include "dm355_ccdc.h"
-#include <media/davinci/vpss.h>
-
-#include "dm355_ccdc_regs.h"
-#include "ccdc_hw_device.h"
-
-MODULE_LICENSE("GPL");
-MODULE_DESCRIPTION("CCDC Driver for DM355");
-MODULE_AUTHOR("Texas Instruments");
-
-static struct ccdc_oper_config {
- struct device *dev;
- /* CCDC interface type */
- enum vpfe_hw_if_type if_type;
- /* Raw Bayer configuration */
- struct ccdc_params_raw bayer;
- /* YCbCr configuration */
- struct ccdc_params_ycbcr ycbcr;
- /* ccdc base address */
- void __iomem *base_addr;
-} ccdc_cfg = {
- /* Raw configurations */
- .bayer = {
- .pix_fmt = CCDC_PIXFMT_RAW,
- .frm_fmt = CCDC_FRMFMT_PROGRESSIVE,
- .win = CCDC_WIN_VGA,
- .fid_pol = VPFE_PINPOL_POSITIVE,
- .vd_pol = VPFE_PINPOL_POSITIVE,
- .hd_pol = VPFE_PINPOL_POSITIVE,
- .gain = {
- .r_ye = 256,
- .gb_g = 256,
- .gr_cy = 256,
- .b_mg = 256
- },
- .config_params = {
- .datasft = 2,
- .mfilt1 = CCDC_NO_MEDIAN_FILTER1,
- .mfilt2 = CCDC_NO_MEDIAN_FILTER2,
- .alaw = {
- .gamma_wd = 2,
- },
- .blk_clamp = {
- .sample_pixel = 1,
- .dc_sub = 25
- },
- .col_pat_field0 = {
- .olop = CCDC_GREEN_BLUE,
- .olep = CCDC_BLUE,
- .elop = CCDC_RED,
- .elep = CCDC_GREEN_RED
- },
- .col_pat_field1 = {
- .olop = CCDC_GREEN_BLUE,
- .olep = CCDC_BLUE,
- .elop = CCDC_RED,
- .elep = CCDC_GREEN_RED
- },
- },
- },
- /* YCbCr configuration */
- .ycbcr = {
- .win = CCDC_WIN_PAL,
- .pix_fmt = CCDC_PIXFMT_YCBCR_8BIT,
- .frm_fmt = CCDC_FRMFMT_INTERLACED,
- .fid_pol = VPFE_PINPOL_POSITIVE,
- .vd_pol = VPFE_PINPOL_POSITIVE,
- .hd_pol = VPFE_PINPOL_POSITIVE,
- .bt656_enable = 1,
- .pix_order = CCDC_PIXORDER_CBYCRY,
- .buf_type = CCDC_BUFTYPE_FLD_INTERLEAVED
- },
-};
-
-
-/* Raw Bayer formats */
-static u32 ccdc_raw_bayer_pix_formats[] =
- {V4L2_PIX_FMT_SBGGR8, V4L2_PIX_FMT_SBGGR16};
-
-/* Raw YUV formats */
-static u32 ccdc_raw_yuv_pix_formats[] =
- {V4L2_PIX_FMT_UYVY, V4L2_PIX_FMT_YUYV};
-
-/* register access routines */
-static inline u32 regr(u32 offset)
-{
- return __raw_readl(ccdc_cfg.base_addr + offset);
-}
-
-static inline void regw(u32 val, u32 offset)
-{
- __raw_writel(val, ccdc_cfg.base_addr + offset);
-}
-
-static void ccdc_enable(int en)
-{
- unsigned int temp;
- temp = regr(SYNCEN);
- temp &= (~CCDC_SYNCEN_VDHDEN_MASK);
- temp |= (en & CCDC_SYNCEN_VDHDEN_MASK);
- regw(temp, SYNCEN);
-}
-
-static void ccdc_enable_output_to_sdram(int en)
-{
- unsigned int temp;
- temp = regr(SYNCEN);
- temp &= (~(CCDC_SYNCEN_WEN_MASK));
- temp |= ((en << CCDC_SYNCEN_WEN_SHIFT) & CCDC_SYNCEN_WEN_MASK);
- regw(temp, SYNCEN);
-}
-
-static void ccdc_config_gain_offset(void)
-{
- /* configure gain */
- regw(ccdc_cfg.bayer.gain.r_ye, RYEGAIN);
- regw(ccdc_cfg.bayer.gain.gr_cy, GRCYGAIN);
- regw(ccdc_cfg.bayer.gain.gb_g, GBGGAIN);
- regw(ccdc_cfg.bayer.gain.b_mg, BMGGAIN);
- /* configure offset */
- regw(ccdc_cfg.bayer.ccdc_offset, OFFSET);
-}
-
-/*
- * ccdc_restore_defaults()
- * This function restore power on defaults in the ccdc registers
- */
-static int ccdc_restore_defaults(void)
-{
- int i;
-
- dev_dbg(ccdc_cfg.dev, "\nstarting ccdc_restore_defaults...");
- /* set all registers to zero */
- for (i = 0; i <= CCDC_REG_LAST; i += 4)
- regw(0, i);
-
- /* now override the values with power on defaults in registers */
- regw(MODESET_DEFAULT, MODESET);
- /* no culling support */
- regw(CULH_DEFAULT, CULH);
- regw(CULV_DEFAULT, CULV);
- /* Set default Gain and Offset */
- ccdc_cfg.bayer.gain.r_ye = GAIN_DEFAULT;
- ccdc_cfg.bayer.gain.gb_g = GAIN_DEFAULT;
- ccdc_cfg.bayer.gain.gr_cy = GAIN_DEFAULT;
- ccdc_cfg.bayer.gain.b_mg = GAIN_DEFAULT;
- ccdc_config_gain_offset();
- regw(OUTCLIP_DEFAULT, OUTCLIP);
- regw(LSCCFG2_DEFAULT, LSCCFG2);
- /* select ccdc input */
- if (vpss_select_ccdc_source(VPSS_CCDCIN)) {
- dev_dbg(ccdc_cfg.dev, "\ncouldn't select ccdc input source");
- return -EFAULT;
- }
- /* select ccdc clock */
- if (vpss_enable_clock(VPSS_CCDC_CLOCK, 1) < 0) {
- dev_dbg(ccdc_cfg.dev, "\ncouldn't enable ccdc clock");
- return -EFAULT;
- }
- dev_dbg(ccdc_cfg.dev, "\nEnd of ccdc_restore_defaults...");
- return 0;
-}
-
-static int ccdc_open(struct device *device)
-{
- return ccdc_restore_defaults();
-}
-
-static int ccdc_close(struct device *device)
-{
- /* disable clock */
- vpss_enable_clock(VPSS_CCDC_CLOCK, 0);
- /* do nothing for now */
- return 0;
-}
-/*
- * ccdc_setwin()
- * This function will configure the window size to
- * be capture in CCDC reg.
- */
-static void ccdc_setwin(struct v4l2_rect *image_win,
- enum ccdc_frmfmt frm_fmt, int ppc)
-{
- int horz_start, horz_nr_pixels;
- int vert_start, vert_nr_lines;
- int mid_img = 0;
-
- dev_dbg(ccdc_cfg.dev, "\nStarting ccdc_setwin...");
-
- /*
- * ppc - per pixel count. indicates how many pixels per cell
- * output to SDRAM. example, for ycbcr, it is one y and one c, so 2.
- * raw capture this is 1
- */
- horz_start = image_win->left << (ppc - 1);
- horz_nr_pixels = ((image_win->width) << (ppc - 1)) - 1;
-
- /* Writing the horizontal info into the registers */
- regw(horz_start, SPH);
- regw(horz_nr_pixels, NPH);
- vert_start = image_win->top;
-
- if (frm_fmt == CCDC_FRMFMT_INTERLACED) {
- vert_nr_lines = (image_win->height >> 1) - 1;
- vert_start >>= 1;
- /* Since first line doesn't have any data */
- vert_start += 1;
- /* configure VDINT0 and VDINT1 */
- regw(vert_start, VDINT0);
- } else {
- /* Since first line doesn't have any data */
- vert_start += 1;
- vert_nr_lines = image_win->height - 1;
- /* configure VDINT0 and VDINT1 */
- mid_img = vert_start + (image_win->height / 2);
- regw(vert_start, VDINT0);
- regw(mid_img, VDINT1);
- }
- regw(vert_start & CCDC_START_VER_ONE_MASK, SLV0);
- regw(vert_start & CCDC_START_VER_TWO_MASK, SLV1);
- regw(vert_nr_lines & CCDC_NUM_LINES_VER, NLV);
- dev_dbg(ccdc_cfg.dev, "\nEnd of ccdc_setwin...");
-}
-
-/* This function will configure CCDC for YCbCr video capture */
-static void ccdc_config_ycbcr(void)
-{
- struct ccdc_params_ycbcr *params = &ccdc_cfg.ycbcr;
- u32 temp;
-
- /* first set the CCDC power on defaults values in all registers */
- dev_dbg(ccdc_cfg.dev, "\nStarting ccdc_config_ycbcr...");
- ccdc_restore_defaults();
-
- /* configure pixel format & video frame format */
- temp = (((params->pix_fmt & CCDC_INPUT_MODE_MASK) <<
- CCDC_INPUT_MODE_SHIFT) |
- ((params->frm_fmt & CCDC_FRM_FMT_MASK) <<
- CCDC_FRM_FMT_SHIFT));
-
- /* setup BT.656 sync mode */
- if (params->bt656_enable) {
- regw(CCDC_REC656IF_BT656_EN, REC656IF);
- /*
- * configure the FID, VD, HD pin polarity fld,hd pol positive,
- * vd negative, 8-bit pack mode
- */
- temp |= CCDC_VD_POL_NEGATIVE;
- } else { /* y/c external sync mode */
- temp |= (((params->fid_pol & CCDC_FID_POL_MASK) <<
- CCDC_FID_POL_SHIFT) |
- ((params->hd_pol & CCDC_HD_POL_MASK) <<
- CCDC_HD_POL_SHIFT) |
- ((params->vd_pol & CCDC_VD_POL_MASK) <<
- CCDC_VD_POL_SHIFT));
- }
-
- /* pack the data to 8-bit */
- temp |= CCDC_DATA_PACK_ENABLE;
-
- regw(temp, MODESET);
-
- /* configure video window */
- ccdc_setwin(¶ms->win, params->frm_fmt, 2);
-
- /* configure the order of y cb cr in SD-RAM */
- temp = (params->pix_order << CCDC_Y8POS_SHIFT);
- temp |= CCDC_LATCH_ON_VSYNC_DISABLE | CCDC_CCDCFG_FIDMD_NO_LATCH_VSYNC;
- regw(temp, CCDCFG);
-
- /*
- * configure the horizontal line offset. This is done by rounding up
- * width to a multiple of 16 pixels and multiply by two to account for
- * y:cb:cr 4:2:2 data
- */
- regw(((params->win.width * 2 + 31) >> 5), HSIZE);
-
- /* configure the memory line offset */
- if (params->buf_type == CCDC_BUFTYPE_FLD_INTERLEAVED) {
- /* two fields are interleaved in memory */
- regw(CCDC_SDOFST_FIELD_INTERLEAVED, SDOFST);
- }
-
- dev_dbg(ccdc_cfg.dev, "\nEnd of ccdc_config_ycbcr...\n");
-}
-
-/*
- * ccdc_config_black_clamp()
- * configure parameters for Optical Black Clamp
- */
-static void ccdc_config_black_clamp(struct ccdc_black_clamp *bclamp)
-{
- u32 val;
-
- if (!bclamp->b_clamp_enable) {
- /* configure DCSub */
- regw(bclamp->dc_sub & CCDC_BLK_DC_SUB_MASK, DCSUB);
- regw(0x0000, CLAMP);
- return;
- }
- /* Enable the Black clamping, set sample lines and pixels */
- val = (bclamp->start_pixel & CCDC_BLK_ST_PXL_MASK) |
- ((bclamp->sample_pixel & CCDC_BLK_SAMPLE_LN_MASK) <<
- CCDC_BLK_SAMPLE_LN_SHIFT) | CCDC_BLK_CLAMP_ENABLE;
- regw(val, CLAMP);
-
- /* If Black clamping is enable then make dcsub 0 */
- val = (bclamp->sample_ln & CCDC_NUM_LINE_CALC_MASK)
- << CCDC_NUM_LINE_CALC_SHIFT;
- regw(val, DCSUB);
-}
-
-/*
- * ccdc_config_black_compense()
- * configure parameters for Black Compensation
- */
-static void ccdc_config_black_compense(struct ccdc_black_compensation *bcomp)
-{
- u32 val;
-
- val = (bcomp->b & CCDC_BLK_COMP_MASK) |
- ((bcomp->gb & CCDC_BLK_COMP_MASK) <<
- CCDC_BLK_COMP_GB_COMP_SHIFT);
- regw(val, BLKCMP1);
-
- val = ((bcomp->gr & CCDC_BLK_COMP_MASK) <<
- CCDC_BLK_COMP_GR_COMP_SHIFT) |
- ((bcomp->r & CCDC_BLK_COMP_MASK) <<
- CCDC_BLK_COMP_R_COMP_SHIFT);
- regw(val, BLKCMP0);
-}
-
-/*
- * ccdc_write_dfc_entry()
- * write an entry in the dfc table.
- */
-static int ccdc_write_dfc_entry(int index, struct ccdc_vertical_dft *dfc)
-{
-/* TODO This is to be re-visited and adjusted */
-#define DFC_WRITE_WAIT_COUNT 1000
- u32 val, count = DFC_WRITE_WAIT_COUNT;
-
- regw(dfc->dft_corr_vert[index], DFCMEM0);
- regw(dfc->dft_corr_horz[index], DFCMEM1);
- regw(dfc->dft_corr_sub1[index], DFCMEM2);
- regw(dfc->dft_corr_sub2[index], DFCMEM3);
- regw(dfc->dft_corr_sub3[index], DFCMEM4);
- /* set WR bit to write */
- val = regr(DFCMEMCTL) | CCDC_DFCMEMCTL_DFCMWR_MASK;
- regw(val, DFCMEMCTL);
-
- /*
- * Assume, it is very short. If we get an error, we need to
- * adjust this value
- */
- while (regr(DFCMEMCTL) & CCDC_DFCMEMCTL_DFCMWR_MASK)
- count--;
- /*
- * TODO We expect the count to be non-zero to be successful. Adjust
- * the count if write requires more time
- */
-
- if (count) {
- dev_err(ccdc_cfg.dev, "defect table write timeout !!!\n");
- return -1;
- }
- return 0;
-}
-
-/*
- * ccdc_config_vdfc()
- * configure parameters for Vertical Defect Correction
- */
-static int ccdc_config_vdfc(struct ccdc_vertical_dft *dfc)
-{
- u32 val;
- int i;
-
- /* Configure General Defect Correction. The table used is from IPIPE */
- val = dfc->gen_dft_en & CCDC_DFCCTL_GDFCEN_MASK;
-
- /* Configure Vertical Defect Correction if needed */
- if (!dfc->ver_dft_en) {
- /* Enable only General Defect Correction */
- regw(val, DFCCTL);
- return 0;
- }
-
- if (dfc->table_size > CCDC_DFT_TABLE_SIZE)
- return -EINVAL;
-
- val |= CCDC_DFCCTL_VDFC_DISABLE;
- val |= (dfc->dft_corr_ctl.vdfcsl & CCDC_DFCCTL_VDFCSL_MASK) <<
- CCDC_DFCCTL_VDFCSL_SHIFT;
- val |= (dfc->dft_corr_ctl.vdfcuda & CCDC_DFCCTL_VDFCUDA_MASK) <<
- CCDC_DFCCTL_VDFCUDA_SHIFT;
- val |= (dfc->dft_corr_ctl.vdflsft & CCDC_DFCCTL_VDFLSFT_MASK) <<
- CCDC_DFCCTL_VDFLSFT_SHIFT;
- regw(val , DFCCTL);
-
- /* clear address ptr to offset 0 */
- val = CCDC_DFCMEMCTL_DFCMARST_MASK << CCDC_DFCMEMCTL_DFCMARST_SHIFT;
-
- /* write defect table entries */
- for (i = 0; i < dfc->table_size; i++) {
- /* increment address for non zero index */
- if (i != 0)
- val = CCDC_DFCMEMCTL_INC_ADDR;
- regw(val, DFCMEMCTL);
- if (ccdc_write_dfc_entry(i, dfc) < 0)
- return -EFAULT;
- }
-
- /* update saturation level and enable dfc */
- regw(dfc->saturation_ctl & CCDC_VDC_DFCVSAT_MASK, DFCVSAT);
- val = regr(DFCCTL) | (CCDC_DFCCTL_VDFCEN_MASK <<
- CCDC_DFCCTL_VDFCEN_SHIFT);
- regw(val, DFCCTL);
- return 0;
-}
-
-/*
- * ccdc_config_csc()
- * configure parameters for color space conversion
- * Each register CSCM0-7 has two values in S8Q5 format.
- */
-static void ccdc_config_csc(struct ccdc_csc *csc)
-{
- u32 val1 = 0, val2;
- int i;
-
- if (!csc->enable)
- return;
-
- /* Enable the CSC sub-module */
- regw(CCDC_CSC_ENABLE, CSCCTL);
-
- /* Converting the co-eff as per the format of the register */
- for (i = 0; i < CCDC_CSC_COEFF_TABLE_SIZE; i++) {
- if ((i % 2) == 0) {
- /* CSCM - LSB */
- val1 = (csc->coeff[i].integer &
- CCDC_CSC_COEF_INTEG_MASK)
- << CCDC_CSC_COEF_INTEG_SHIFT;
- /*
- * convert decimal part to binary. Use 2 decimal
- * precision, user values range from .00 - 0.99
- */
- val1 |= (((csc->coeff[i].decimal &
- CCDC_CSC_COEF_DECIMAL_MASK) *
- CCDC_CSC_DEC_MAX) / 100);
- } else {
-
- /* CSCM - MSB */
- val2 = (csc->coeff[i].integer &
- CCDC_CSC_COEF_INTEG_MASK)
- << CCDC_CSC_COEF_INTEG_SHIFT;
- val2 |= (((csc->coeff[i].decimal &
- CCDC_CSC_COEF_DECIMAL_MASK) *
- CCDC_CSC_DEC_MAX) / 100);
- val2 <<= CCDC_CSCM_MSB_SHIFT;
- val2 |= val1;
- regw(val2, (CSCM0 + ((i - 1) << 1)));
- }
- }
-}
-
-/*
- * ccdc_config_color_patterns()
- * configure parameters for color patterns
- */
-static void ccdc_config_color_patterns(struct ccdc_col_pat *pat0,
- struct ccdc_col_pat *pat1)
-{
- u32 val;
-
- val = (pat0->olop | (pat0->olep << 2) | (pat0->elop << 4) |
- (pat0->elep << 6) | (pat1->olop << 8) | (pat1->olep << 10) |
- (pat1->elop << 12) | (pat1->elep << 14));
- regw(val, COLPTN);
-}
-
-/* This function will configure CCDC for Raw mode image capture */
-static int ccdc_config_raw(void)
-{
- struct ccdc_params_raw *params = &ccdc_cfg.bayer;
- struct ccdc_config_params_raw *config_params =
- &ccdc_cfg.bayer.config_params;
- unsigned int val;
-
- dev_dbg(ccdc_cfg.dev, "\nStarting ccdc_config_raw...");
-
- /* restore power on defaults to register */
- ccdc_restore_defaults();
-
- /* CCDCFG register:
- * set CCD Not to swap input since input is RAW data
- * set FID detection function to Latch at V-Sync
- * set WENLOG - ccdc valid area to AND
- * set TRGSEL to WENBIT
- * set EXTRG to DISABLE
- * disable latching function on VSYNC - shadowed registers
- */
- regw(CCDC_YCINSWP_RAW | CCDC_CCDCFG_FIDMD_LATCH_VSYNC |
- CCDC_CCDCFG_WENLOG_AND | CCDC_CCDCFG_TRGSEL_WEN |
- CCDC_CCDCFG_EXTRG_DISABLE | CCDC_LATCH_ON_VSYNC_DISABLE, CCDCFG);
-
- /*
- * Set VDHD direction to input, input type to raw input
- * normal data polarity, do not use external WEN
- */
- val = (CCDC_VDHDOUT_INPUT | CCDC_RAW_IP_MODE | CCDC_DATAPOL_NORMAL |
- CCDC_EXWEN_DISABLE);
-
- /*
- * Configure the vertical sync polarity (MODESET.VDPOL), horizontal
- * sync polarity (MODESET.HDPOL), field id polarity (MODESET.FLDPOL),
- * frame format(progressive or interlace), & pixel format (Input mode)
- */
- val |= (((params->vd_pol & CCDC_VD_POL_MASK) << CCDC_VD_POL_SHIFT) |
- ((params->hd_pol & CCDC_HD_POL_MASK) << CCDC_HD_POL_SHIFT) |
- ((params->fid_pol & CCDC_FID_POL_MASK) << CCDC_FID_POL_SHIFT) |
- ((params->frm_fmt & CCDC_FRM_FMT_MASK) << CCDC_FRM_FMT_SHIFT) |
- ((params->pix_fmt & CCDC_PIX_FMT_MASK) << CCDC_PIX_FMT_SHIFT));
-
- /* set pack for alaw compression */
- if ((config_params->data_sz == CCDC_DATA_8BITS) ||
- config_params->alaw.enable)
- val |= CCDC_DATA_PACK_ENABLE;
-
- /* Configure for LPF */
- if (config_params->lpf_enable)
- val |= (config_params->lpf_enable & CCDC_LPF_MASK) <<
- CCDC_LPF_SHIFT;
-
- /* Configure the data shift */
- val |= (config_params->datasft & CCDC_DATASFT_MASK) <<
- CCDC_DATASFT_SHIFT;
- regw(val , MODESET);
- dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to MODESET...\n", val);
-
- /* Configure the Median Filter threshold */
- regw((config_params->med_filt_thres) & CCDC_MED_FILT_THRESH, MEDFILT);
-
- /* Configure GAMMAWD register. defaur 11-2, and Mosaic cfa pattern */
- val = CCDC_GAMMA_BITS_11_2 << CCDC_GAMMAWD_INPUT_SHIFT |
- CCDC_CFA_MOSAIC;
-
- /* Enable and configure aLaw register if needed */
- if (config_params->alaw.enable) {
- val |= (CCDC_ALAW_ENABLE |
- ((config_params->alaw.gamma_wd &
- CCDC_ALAW_GAMMA_WD_MASK) <<
- CCDC_GAMMAWD_INPUT_SHIFT));
- }
-
- /* Configure Median filter1 & filter2 */
- val |= ((config_params->mfilt1 << CCDC_MFILT1_SHIFT) |
- (config_params->mfilt2 << CCDC_MFILT2_SHIFT));
-
- regw(val, GAMMAWD);
- dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to GAMMAWD...\n", val);
-
- /* configure video window */
- ccdc_setwin(¶ms->win, params->frm_fmt, 1);
-
- /* Optical Clamp Averaging */
- ccdc_config_black_clamp(&config_params->blk_clamp);
-
- /* Black level compensation */
- ccdc_config_black_compense(&config_params->blk_comp);
-
- /* Vertical Defect Correction if needed */
- if (ccdc_config_vdfc(&config_params->vertical_dft) < 0)
- return -EFAULT;
-
- /* color space conversion */
- ccdc_config_csc(&config_params->csc);
-
- /* color pattern */
- ccdc_config_color_patterns(&config_params->col_pat_field0,
- &config_params->col_pat_field1);
-
- /* Configure the Gain & offset control */
- ccdc_config_gain_offset();
-
- dev_dbg(ccdc_cfg.dev, "\nWriting %x to COLPTN...\n", val);
-
- /* Configure DATAOFST register */
- val = (config_params->data_offset.horz_offset & CCDC_DATAOFST_MASK) <<
- CCDC_DATAOFST_H_SHIFT;
- val |= (config_params->data_offset.vert_offset & CCDC_DATAOFST_MASK) <<
- CCDC_DATAOFST_V_SHIFT;
- regw(val, DATAOFST);
-
- /* configuring HSIZE register */
- val = (params->horz_flip_enable & CCDC_HSIZE_FLIP_MASK) <<
- CCDC_HSIZE_FLIP_SHIFT;
-
- /* If pack 8 is enable then 1 pixel will take 1 byte */
- if ((config_params->data_sz == CCDC_DATA_8BITS) ||
- config_params->alaw.enable) {
- val |= (((params->win.width) + 31) >> 5) &
- CCDC_HSIZE_VAL_MASK;
-
- /* adjust to multiple of 32 */
- dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to HSIZE...\n",
- (((params->win.width) + 31) >> 5) &
- CCDC_HSIZE_VAL_MASK);
- } else {
- /* else one pixel will take 2 byte */
- val |= (((params->win.width * 2) + 31) >> 5) &
- CCDC_HSIZE_VAL_MASK;
-
- dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to HSIZE...\n",
- (((params->win.width * 2) + 31) >> 5) &
- CCDC_HSIZE_VAL_MASK);
- }
- regw(val, HSIZE);
-
- /* Configure SDOFST register */
- if (params->frm_fmt == CCDC_FRMFMT_INTERLACED) {
- if (params->image_invert_enable) {
- /* For interlace inverse mode */
- regw(CCDC_SDOFST_INTERLACE_INVERSE, SDOFST);
- dev_dbg(ccdc_cfg.dev, "\nWriting %x to SDOFST...\n",
- CCDC_SDOFST_INTERLACE_INVERSE);
- } else {
- /* For interlace non inverse mode */
- regw(CCDC_SDOFST_INTERLACE_NORMAL, SDOFST);
- dev_dbg(ccdc_cfg.dev, "\nWriting %x to SDOFST...\n",
- CCDC_SDOFST_INTERLACE_NORMAL);
- }
- } else if (params->frm_fmt == CCDC_FRMFMT_PROGRESSIVE) {
- if (params->image_invert_enable) {
- /* For progessive inverse mode */
- regw(CCDC_SDOFST_PROGRESSIVE_INVERSE, SDOFST);
- dev_dbg(ccdc_cfg.dev, "\nWriting %x to SDOFST...\n",
- CCDC_SDOFST_PROGRESSIVE_INVERSE);
- } else {
- /* For progessive non inverse mode */
- regw(CCDC_SDOFST_PROGRESSIVE_NORMAL, SDOFST);
- dev_dbg(ccdc_cfg.dev, "\nWriting %x to SDOFST...\n",
- CCDC_SDOFST_PROGRESSIVE_NORMAL);
- }
- }
- dev_dbg(ccdc_cfg.dev, "\nend of ccdc_config_raw...");
- return 0;
-}
-
-static int ccdc_configure(void)
-{
- if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
- return ccdc_config_raw();
- else
- ccdc_config_ycbcr();
- return 0;
-}
-
-static int ccdc_set_buftype(enum ccdc_buftype buf_type)
-{
- if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
- ccdc_cfg.bayer.buf_type = buf_type;
- else
- ccdc_cfg.ycbcr.buf_type = buf_type;
- return 0;
-}
-static enum ccdc_buftype ccdc_get_buftype(void)
-{
- if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
- return ccdc_cfg.bayer.buf_type;
- return ccdc_cfg.ycbcr.buf_type;
-}
-
-static int ccdc_enum_pix(u32 *pix, int i)
-{
- int ret = -EINVAL;
- if (ccdc_cfg.if_type == VPFE_RAW_BAYER) {
- if (i < ARRAY_SIZE(ccdc_raw_bayer_pix_formats)) {
- *pix = ccdc_raw_bayer_pix_formats[i];
- ret = 0;
- }
- } else {
- if (i < ARRAY_SIZE(ccdc_raw_yuv_pix_formats)) {
- *pix = ccdc_raw_yuv_pix_formats[i];
- ret = 0;
- }
- }
- return ret;
-}
-
-static int ccdc_set_pixel_format(u32 pixfmt)
-{
- struct ccdc_a_law *alaw = &ccdc_cfg.bayer.config_params.alaw;
-
- if (ccdc_cfg.if_type == VPFE_RAW_BAYER) {
- ccdc_cfg.bayer.pix_fmt = CCDC_PIXFMT_RAW;
- if (pixfmt == V4L2_PIX_FMT_SBGGR8)
- alaw->enable = 1;
- else if (pixfmt != V4L2_PIX_FMT_SBGGR16)
- return -EINVAL;
- } else {
- if (pixfmt == V4L2_PIX_FMT_YUYV)
- ccdc_cfg.ycbcr.pix_order = CCDC_PIXORDER_YCBYCR;
- else if (pixfmt == V4L2_PIX_FMT_UYVY)
- ccdc_cfg.ycbcr.pix_order = CCDC_PIXORDER_CBYCRY;
- else
- return -EINVAL;
- }
- return 0;
-}
-static u32 ccdc_get_pixel_format(void)
-{
- struct ccdc_a_law *alaw = &ccdc_cfg.bayer.config_params.alaw;
- u32 pixfmt;
-
- if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
- if (alaw->enable)
- pixfmt = V4L2_PIX_FMT_SBGGR8;
- else
- pixfmt = V4L2_PIX_FMT_SBGGR16;
- else {
- if (ccdc_cfg.ycbcr.pix_order == CCDC_PIXORDER_YCBYCR)
- pixfmt = V4L2_PIX_FMT_YUYV;
- else
- pixfmt = V4L2_PIX_FMT_UYVY;
- }
- return pixfmt;
-}
-static int ccdc_set_image_window(struct v4l2_rect *win)
-{
- if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
- ccdc_cfg.bayer.win = *win;
- else
- ccdc_cfg.ycbcr.win = *win;
- return 0;
-}
-
-static void ccdc_get_image_window(struct v4l2_rect *win)
-{
- if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
- *win = ccdc_cfg.bayer.win;
- else
- *win = ccdc_cfg.ycbcr.win;
-}
-
-static unsigned int ccdc_get_line_length(void)
-{
- struct ccdc_config_params_raw *config_params =
- &ccdc_cfg.bayer.config_params;
- unsigned int len;
-
- if (ccdc_cfg.if_type == VPFE_RAW_BAYER) {
- if ((config_params->alaw.enable) ||
- (config_params->data_sz == CCDC_DATA_8BITS))
- len = ccdc_cfg.bayer.win.width;
- else
- len = ccdc_cfg.bayer.win.width * 2;
- } else
- len = ccdc_cfg.ycbcr.win.width * 2;
- return ALIGN(len, 32);
-}
-
-static int ccdc_set_frame_format(enum ccdc_frmfmt frm_fmt)
-{
- if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
- ccdc_cfg.bayer.frm_fmt = frm_fmt;
- else
- ccdc_cfg.ycbcr.frm_fmt = frm_fmt;
- return 0;
-}
-
-static enum ccdc_frmfmt ccdc_get_frame_format(void)
-{
- if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
- return ccdc_cfg.bayer.frm_fmt;
- else
- return ccdc_cfg.ycbcr.frm_fmt;
-}
-
-static int ccdc_getfid(void)
-{
- return (regr(MODESET) >> 15) & 1;
-}
-
-/* misc operations */
-static inline void ccdc_setfbaddr(unsigned long addr)
-{
- regw((addr >> 21) & 0x007f, STADRH);
- regw((addr >> 5) & 0x0ffff, STADRL);
-}
-
-static int ccdc_set_hw_if_params(struct vpfe_hw_if_param *params)
-{
- ccdc_cfg.if_type = params->if_type;
-
- switch (params->if_type) {
- case VPFE_BT656:
- case VPFE_YCBCR_SYNC_16:
- case VPFE_YCBCR_SYNC_8:
- ccdc_cfg.ycbcr.vd_pol = params->vdpol;
- ccdc_cfg.ycbcr.hd_pol = params->hdpol;
- break;
- default:
- /* TODO add support for raw bayer here */
- return -EINVAL;
- }
- return 0;
-}
-
-static const struct ccdc_hw_device ccdc_hw_dev = {
- .name = "DM355 CCDC",
- .owner = THIS_MODULE,
- .hw_ops = {
- .open = ccdc_open,
- .close = ccdc_close,
- .enable = ccdc_enable,
- .enable_out_to_sdram = ccdc_enable_output_to_sdram,
- .set_hw_if_params = ccdc_set_hw_if_params,
- .configure = ccdc_configure,
- .set_buftype = ccdc_set_buftype,
- .get_buftype = ccdc_get_buftype,
- .enum_pix = ccdc_enum_pix,
- .set_pixel_format = ccdc_set_pixel_format,
- .get_pixel_format = ccdc_get_pixel_format,
- .set_frame_format = ccdc_set_frame_format,
- .get_frame_format = ccdc_get_frame_format,
- .set_image_window = ccdc_set_image_window,
- .get_image_window = ccdc_get_image_window,
- .get_line_length = ccdc_get_line_length,
- .setfbaddr = ccdc_setfbaddr,
- .getfid = ccdc_getfid,
- },
-};
-
-static int dm355_ccdc_probe(struct platform_device *pdev)
-{
- void (*setup_pinmux)(void);
- struct resource *res;
- int status = 0;
-
- /*
- * first try to register with vpfe. If not correct platform, then we
- * don't have to iomap
- */
- status = vpfe_register_ccdc_device(&ccdc_hw_dev);
- if (status < 0)
- return status;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!res) {
- status = -ENODEV;
- goto fail_nores;
- }
-
- res = request_mem_region(res->start, resource_size(res), res->name);
- if (!res) {
- status = -EBUSY;
- goto fail_nores;
- }
-
- ccdc_cfg.base_addr = ioremap(res->start, resource_size(res));
- if (!ccdc_cfg.base_addr) {
- status = -ENOMEM;
- goto fail_nomem;
- }
-
- /* Platform data holds setup_pinmux function ptr */
- if (NULL == pdev->dev.platform_data) {
- status = -ENODEV;
- goto fail_nomap;
- }
- setup_pinmux = pdev->dev.platform_data;
- /*
- * setup Mux configuration for ccdc which may be different for
- * different SoCs using this CCDC
- */
- setup_pinmux();
- ccdc_cfg.dev = &pdev->dev;
- printk(KERN_NOTICE "%s is registered with vpfe.\n", ccdc_hw_dev.name);
- return 0;
-fail_nomap:
- iounmap(ccdc_cfg.base_addr);
-fail_nomem:
- release_mem_region(res->start, resource_size(res));
-fail_nores:
- vpfe_unregister_ccdc_device(&ccdc_hw_dev);
- return status;
-}
-
-static int dm355_ccdc_remove(struct platform_device *pdev)
-{
- struct resource *res;
-
- iounmap(ccdc_cfg.base_addr);
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- release_mem_region(res->start, resource_size(res));
- vpfe_unregister_ccdc_device(&ccdc_hw_dev);
- return 0;
-}
-
-static struct platform_driver dm355_ccdc_driver = {
- .driver = {
- .name = "dm355_ccdc",
- },
- .remove = dm355_ccdc_remove,
- .probe = dm355_ccdc_probe,
-};
-
-module_platform_driver(dm355_ccdc_driver);
diff --git a/drivers/staging/media/deprecated/vpfe_capture/dm355_ccdc.h b/drivers/staging/media/deprecated/vpfe_capture/dm355_ccdc.h
deleted file mode 100644
index 1f3d00aa46d1..000000000000
--- a/drivers/staging/media/deprecated/vpfe_capture/dm355_ccdc.h
+++ /dev/null
@@ -1,308 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright (C) 2005-2009 Texas Instruments Inc
- */
-#ifndef _DM355_CCDC_H
-#define _DM355_CCDC_H
-#include <media/davinci/ccdc_types.h>
-#include <media/davinci/vpfe_types.h>
-
-/* enum for No of pixel per line to be avg. in Black Clamping */
-enum ccdc_sample_length {
- CCDC_SAMPLE_1PIXELS,
- CCDC_SAMPLE_2PIXELS,
- CCDC_SAMPLE_4PIXELS,
- CCDC_SAMPLE_8PIXELS,
- CCDC_SAMPLE_16PIXELS
-};
-
-/* enum for No of lines in Black Clamping */
-enum ccdc_sample_line {
- CCDC_SAMPLE_1LINES,
- CCDC_SAMPLE_2LINES,
- CCDC_SAMPLE_4LINES,
- CCDC_SAMPLE_8LINES,
- CCDC_SAMPLE_16LINES
-};
-
-/* enum for Alaw gamma width */
-enum ccdc_gamma_width {
- CCDC_GAMMA_BITS_13_4,
- CCDC_GAMMA_BITS_12_3,
- CCDC_GAMMA_BITS_11_2,
- CCDC_GAMMA_BITS_10_1,
- CCDC_GAMMA_BITS_09_0
-};
-
-enum ccdc_colpats {
- CCDC_RED,
- CCDC_GREEN_RED,
- CCDC_GREEN_BLUE,
- CCDC_BLUE
-};
-
-struct ccdc_col_pat {
- enum ccdc_colpats olop;
- enum ccdc_colpats olep;
- enum ccdc_colpats elop;
- enum ccdc_colpats elep;
-};
-
-enum ccdc_datasft {
- CCDC_DATA_NO_SHIFT,
- CCDC_DATA_SHIFT_1BIT,
- CCDC_DATA_SHIFT_2BIT,
- CCDC_DATA_SHIFT_3BIT,
- CCDC_DATA_SHIFT_4BIT,
- CCDC_DATA_SHIFT_5BIT,
- CCDC_DATA_SHIFT_6BIT
-};
-
-enum ccdc_data_size {
- CCDC_DATA_16BITS,
- CCDC_DATA_15BITS,
- CCDC_DATA_14BITS,
- CCDC_DATA_13BITS,
- CCDC_DATA_12BITS,
- CCDC_DATA_11BITS,
- CCDC_DATA_10BITS,
- CCDC_DATA_8BITS
-};
-enum ccdc_mfilt1 {
- CCDC_NO_MEDIAN_FILTER1,
- CCDC_AVERAGE_FILTER1,
- CCDC_MEDIAN_FILTER1
-};
-
-enum ccdc_mfilt2 {
- CCDC_NO_MEDIAN_FILTER2,
- CCDC_AVERAGE_FILTER2,
- CCDC_MEDIAN_FILTER2
-};
-
-/* structure for ALaw */
-struct ccdc_a_law {
- /* Enable/disable A-Law */
- unsigned char enable;
- /* Gamma Width Input */
- enum ccdc_gamma_width gamma_wd;
-};
-
-/* structure for Black Clamping */
-struct ccdc_black_clamp {
- /* only if bClampEnable is TRUE */
- unsigned char b_clamp_enable;
- /* only if bClampEnable is TRUE */
- enum ccdc_sample_length sample_pixel;
- /* only if bClampEnable is TRUE */
- enum ccdc_sample_line sample_ln;
- /* only if bClampEnable is TRUE */
- unsigned short start_pixel;
- /* only if bClampEnable is FALSE */
- unsigned short sgain;
- unsigned short dc_sub;
-};
-
-/* structure for Black Level Compensation */
-struct ccdc_black_compensation {
- /* Constant value to subtract from Red component */
- unsigned char r;
- /* Constant value to subtract from Gr component */
- unsigned char gr;
- /* Constant value to subtract from Blue component */
- unsigned char b;
- /* Constant value to subtract from Gb component */
- unsigned char gb;
-};
-
-struct ccdc_float {
- int integer;
- unsigned int decimal;
-};
-
-#define CCDC_CSC_COEFF_TABLE_SIZE 16
-/* structure for color space converter */
-struct ccdc_csc {
- unsigned char enable;
- /*
- * S8Q5. Use 2 decimal precision, user values range from -3.00 to 3.99.
- * example - to use 1.03, set integer part as 1, and decimal part as 3
- * to use -1.03, set integer part as -1 and decimal part as 3
- */
- struct ccdc_float coeff[CCDC_CSC_COEFF_TABLE_SIZE];
-};
-
-/* Structures for Vertical Defect Correction*/
-enum ccdc_vdf_csl {
- CCDC_VDF_NORMAL,
- CCDC_VDF_HORZ_INTERPOL_SAT,
- CCDC_VDF_HORZ_INTERPOL
-};
-
-enum ccdc_vdf_cuda {
- CCDC_VDF_WHOLE_LINE_CORRECT,
- CCDC_VDF_UPPER_DISABLE
-};
-
-enum ccdc_dfc_mwr {
- CCDC_DFC_MWR_WRITE_COMPLETE,
- CCDC_DFC_WRITE_REG
-};
-
-enum ccdc_dfc_mrd {
- CCDC_DFC_READ_COMPLETE,
- CCDC_DFC_READ_REG
-};
-
-enum ccdc_dfc_ma_rst {
- CCDC_DFC_INCR_ADDR,
- CCDC_DFC_CLR_ADDR
-};
-
-enum ccdc_dfc_mclr {
- CCDC_DFC_CLEAR_COMPLETE,
- CCDC_DFC_CLEAR
-};
-
-struct ccdc_dft_corr_ctl {
- enum ccdc_vdf_csl vdfcsl;
- enum ccdc_vdf_cuda vdfcuda;
- unsigned int vdflsft;
-};
-
-struct ccdc_dft_corr_mem_ctl {
- enum ccdc_dfc_mwr dfcmwr;
- enum ccdc_dfc_mrd dfcmrd;
- enum ccdc_dfc_ma_rst dfcmarst;
- enum ccdc_dfc_mclr dfcmclr;
-};
-
-#define CCDC_DFT_TABLE_SIZE 16
-/*
- * Main Structure for vertical defect correction. Vertical defect
- * correction can correct up to 16 defects if defects less than 16
- * then pad the rest with 0
- */
-struct ccdc_vertical_dft {
- unsigned char ver_dft_en;
- unsigned char gen_dft_en;
- unsigned int saturation_ctl;
- struct ccdc_dft_corr_ctl dft_corr_ctl;
- struct ccdc_dft_corr_mem_ctl dft_corr_mem_ctl;
- int table_size;
- unsigned int dft_corr_horz[CCDC_DFT_TABLE_SIZE];
- unsigned int dft_corr_vert[CCDC_DFT_TABLE_SIZE];
- unsigned int dft_corr_sub1[CCDC_DFT_TABLE_SIZE];
- unsigned int dft_corr_sub2[CCDC_DFT_TABLE_SIZE];
- unsigned int dft_corr_sub3[CCDC_DFT_TABLE_SIZE];
-};
-
-struct ccdc_data_offset {
- unsigned char horz_offset;
- unsigned char vert_offset;
-};
-
-/*
- * Structure for CCDC configuration parameters for raw capture mode passed
- * by application
- */
-struct ccdc_config_params_raw {
- /* data shift to be applied before storing */
- enum ccdc_datasft datasft;
- /* data size value from 8 to 16 bits */
- enum ccdc_data_size data_sz;
- /* median filter for sdram */
- enum ccdc_mfilt1 mfilt1;
- enum ccdc_mfilt2 mfilt2;
- /* low pass filter enable/disable */
- unsigned char lpf_enable;
- /* Threshold of median filter */
- int med_filt_thres;
- /*
- * horz and vertical data offset. Applicable for defect correction
- * and lsc
- */
- struct ccdc_data_offset data_offset;
- /* Structure for Optional A-Law */
- struct ccdc_a_law alaw;
- /* Structure for Optical Black Clamp */
- struct ccdc_black_clamp blk_clamp;
- /* Structure for Black Compensation */
- struct ccdc_black_compensation blk_comp;
- /* structure for vertical Defect Correction Module Configuration */
- struct ccdc_vertical_dft vertical_dft;
- /* structure for color space converter Module Configuration */
- struct ccdc_csc csc;
- /* color patters for bayer capture */
- struct ccdc_col_pat col_pat_field0;
- struct ccdc_col_pat col_pat_field1;
-};
-
-#ifdef __KERNEL__
-#include <linux/io.h>
-
-#define CCDC_WIN_PAL {0, 0, 720, 576}
-#define CCDC_WIN_VGA {0, 0, 640, 480}
-
-struct ccdc_params_ycbcr {
- /* pixel format */
- enum ccdc_pixfmt pix_fmt;
- /* progressive or interlaced frame */
- enum ccdc_frmfmt frm_fmt;
- /* video window */
- struct v4l2_rect win;
- /* field id polarity */
- enum vpfe_pin_pol fid_pol;
- /* vertical sync polarity */
- enum vpfe_pin_pol vd_pol;
- /* horizontal sync polarity */
- enum vpfe_pin_pol hd_pol;
- /* enable BT.656 embedded sync mode */
- int bt656_enable;
- /* cb:y:cr:y or y:cb:y:cr in memory */
- enum ccdc_pixorder pix_order;
- /* interleaved or separated fields */
- enum ccdc_buftype buf_type;
-};
-
-/* Gain applied to Raw Bayer data */
-struct ccdc_gain {
- unsigned short r_ye;
- unsigned short gr_cy;
- unsigned short gb_g;
- unsigned short b_mg;
-};
-
-/* Structure for CCDC configuration parameters for raw capture mode */
-struct ccdc_params_raw {
- /* pixel format */
- enum ccdc_pixfmt pix_fmt;
- /* progressive or interlaced frame */
- enum ccdc_frmfmt frm_fmt;
- /* video window */
- struct v4l2_rect win;
- /* field id polarity */
- enum vpfe_pin_pol fid_pol;
- /* vertical sync polarity */
- enum vpfe_pin_pol vd_pol;
- /* horizontal sync polarity */
- enum vpfe_pin_pol hd_pol;
- /* interleaved or separated fields */
- enum ccdc_buftype buf_type;
- /* Gain values */
- struct ccdc_gain gain;
- /* offset */
- unsigned int ccdc_offset;
- /* horizontal flip enable */
- unsigned char horz_flip_enable;
- /*
- * enable to store the image in inverse order in memory
- * (bottom to top)
- */
- unsigned char image_invert_enable;
- /* Configurable part of raw data */
- struct ccdc_config_params_raw config_params;
-};
-
-#endif
-#endif /* DM355_CCDC_H */
diff --git a/drivers/staging/media/deprecated/vpfe_capture/dm355_ccdc_regs.h b/drivers/staging/media/deprecated/vpfe_capture/dm355_ccdc_regs.h
deleted file mode 100644
index eb381f075245..000000000000
--- a/drivers/staging/media/deprecated/vpfe_capture/dm355_ccdc_regs.h
+++ /dev/null
@@ -1,297 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright (C) 2005-2009 Texas Instruments Inc
- */
-#ifndef _DM355_CCDC_REGS_H
-#define _DM355_CCDC_REGS_H
-
-/**************************************************************************\
-* Register OFFSET Definitions
-\**************************************************************************/
-#define SYNCEN 0x00
-#define MODESET 0x04
-#define HDWIDTH 0x08
-#define VDWIDTH 0x0c
-#define PPLN 0x10
-#define LPFR 0x14
-#define SPH 0x18
-#define NPH 0x1c
-#define SLV0 0x20
-#define SLV1 0x24
-#define NLV 0x28
-#define CULH 0x2c
-#define CULV 0x30
-#define HSIZE 0x34
-#define SDOFST 0x38
-#define STADRH 0x3c
-#define STADRL 0x40
-#define CLAMP 0x44
-#define DCSUB 0x48
-#define COLPTN 0x4c
-#define BLKCMP0 0x50
-#define BLKCMP1 0x54
-#define MEDFILT 0x58
-#define RYEGAIN 0x5c
-#define GRCYGAIN 0x60
-#define GBGGAIN 0x64
-#define BMGGAIN 0x68
-#define OFFSET 0x6c
-#define OUTCLIP 0x70
-#define VDINT0 0x74
-#define VDINT1 0x78
-#define RSV0 0x7c
-#define GAMMAWD 0x80
-#define REC656IF 0x84
-#define CCDCFG 0x88
-#define FMTCFG 0x8c
-#define FMTPLEN 0x90
-#define FMTSPH 0x94
-#define FMTLNH 0x98
-#define FMTSLV 0x9c
-#define FMTLNV 0xa0
-#define FMTRLEN 0xa4
-#define FMTHCNT 0xa8
-#define FMT_ADDR_PTR_B 0xac
-#define FMT_ADDR_PTR(i) (FMT_ADDR_PTR_B + (i * 4))
-#define FMTPGM_VF0 0xcc
-#define FMTPGM_VF1 0xd0
-#define FMTPGM_AP0 0xd4
-#define FMTPGM_AP1 0xd8
-#define FMTPGM_AP2 0xdc
-#define FMTPGM_AP3 0xe0
-#define FMTPGM_AP4 0xe4
-#define FMTPGM_AP5 0xe8
-#define FMTPGM_AP6 0xec
-#define FMTPGM_AP7 0xf0
-#define LSCCFG1 0xf4
-#define LSCCFG2 0xf8
-#define LSCH0 0xfc
-#define LSCV0 0x100
-#define LSCKH 0x104
-#define LSCKV 0x108
-#define LSCMEMCTL 0x10c
-#define LSCMEMD 0x110
-#define LSCMEMQ 0x114
-#define DFCCTL 0x118
-#define DFCVSAT 0x11c
-#define DFCMEMCTL 0x120
-#define DFCMEM0 0x124
-#define DFCMEM1 0x128
-#define DFCMEM2 0x12c
-#define DFCMEM3 0x130
-#define DFCMEM4 0x134
-#define CSCCTL 0x138
-#define CSCM0 0x13c
-#define CSCM1 0x140
-#define CSCM2 0x144
-#define CSCM3 0x148
-#define CSCM4 0x14c
-#define CSCM5 0x150
-#define CSCM6 0x154
-#define CSCM7 0x158
-#define DATAOFST 0x15c
-#define CCDC_REG_LAST DATAOFST
-/**************************************************************
-* Define for various register bit mask and shifts for CCDC
-*
-**************************************************************/
-#define CCDC_RAW_IP_MODE 0
-#define CCDC_VDHDOUT_INPUT 0
-#define CCDC_YCINSWP_RAW (0 << 4)
-#define CCDC_EXWEN_DISABLE 0
-#define CCDC_DATAPOL_NORMAL 0
-#define CCDC_CCDCFG_FIDMD_LATCH_VSYNC 0
-#define CCDC_CCDCFG_FIDMD_NO_LATCH_VSYNC (1 << 6)
-#define CCDC_CCDCFG_WENLOG_AND 0
-#define CCDC_CCDCFG_TRGSEL_WEN 0
-#define CCDC_CCDCFG_EXTRG_DISABLE 0
-#define CCDC_CFA_MOSAIC 0
-#define CCDC_Y8POS_SHIFT 11
-
-#define CCDC_VDC_DFCVSAT_MASK 0x3fff
-#define CCDC_DATAOFST_MASK 0x0ff
-#define CCDC_DATAOFST_H_SHIFT 0
-#define CCDC_DATAOFST_V_SHIFT 8
-#define CCDC_GAMMAWD_CFA_MASK 1
-#define CCDC_GAMMAWD_CFA_SHIFT 5
-#define CCDC_GAMMAWD_INPUT_SHIFT 2
-#define CCDC_FID_POL_MASK 1
-#define CCDC_FID_POL_SHIFT 4
-#define CCDC_HD_POL_MASK 1
-#define CCDC_HD_POL_SHIFT 3
-#define CCDC_VD_POL_MASK 1
-#define CCDC_VD_POL_SHIFT 2
-#define CCDC_VD_POL_NEGATIVE (1 << 2)
-#define CCDC_FRM_FMT_MASK 1
-#define CCDC_FRM_FMT_SHIFT 7
-#define CCDC_DATA_SZ_MASK 7
-#define CCDC_DATA_SZ_SHIFT 8
-#define CCDC_VDHDOUT_MASK 1
-#define CCDC_VDHDOUT_SHIFT 0
-#define CCDC_EXWEN_MASK 1
-#define CCDC_EXWEN_SHIFT 5
-#define CCDC_INPUT_MODE_MASK 3
-#define CCDC_INPUT_MODE_SHIFT 12
-#define CCDC_PIX_FMT_MASK 3
-#define CCDC_PIX_FMT_SHIFT 12
-#define CCDC_DATAPOL_MASK 1
-#define CCDC_DATAPOL_SHIFT 6
-#define CCDC_WEN_ENABLE (1 << 1)
-#define CCDC_VDHDEN_ENABLE (1 << 16)
-#define CCDC_LPF_ENABLE (1 << 14)
-#define CCDC_ALAW_ENABLE 1
-#define CCDC_ALAW_GAMMA_WD_MASK 7
-#define CCDC_REC656IF_BT656_EN 3
-
-#define CCDC_FMTCFG_FMTMODE_MASK 3
-#define CCDC_FMTCFG_FMTMODE_SHIFT 1
-#define CCDC_FMTCFG_LNUM_MASK 3
-#define CCDC_FMTCFG_LNUM_SHIFT 4
-#define CCDC_FMTCFG_ADDRINC_MASK 7
-#define CCDC_FMTCFG_ADDRINC_SHIFT 8
-
-#define CCDC_CCDCFG_FIDMD_SHIFT 6
-#define CCDC_CCDCFG_WENLOG_SHIFT 8
-#define CCDC_CCDCFG_TRGSEL_SHIFT 9
-#define CCDC_CCDCFG_EXTRG_SHIFT 10
-#define CCDC_CCDCFG_MSBINVI_SHIFT 13
-
-#define CCDC_HSIZE_FLIP_SHIFT 12
-#define CCDC_HSIZE_FLIP_MASK 1
-#define CCDC_HSIZE_VAL_MASK 0xFFF
-#define CCDC_SDOFST_FIELD_INTERLEAVED 0x249
-#define CCDC_SDOFST_INTERLACE_INVERSE 0x4B6D
-#define CCDC_SDOFST_INTERLACE_NORMAL 0x0B6D
-#define CCDC_SDOFST_PROGRESSIVE_INVERSE 0x4000
-#define CCDC_SDOFST_PROGRESSIVE_NORMAL 0
-#define CCDC_START_PX_HOR_MASK 0x7FFF
-#define CCDC_NUM_PX_HOR_MASK 0x7FFF
-#define CCDC_START_VER_ONE_MASK 0x7FFF
-#define CCDC_START_VER_TWO_MASK 0x7FFF
-#define CCDC_NUM_LINES_VER 0x7FFF
-
-#define CCDC_BLK_CLAMP_ENABLE (1 << 15)
-#define CCDC_BLK_SGAIN_MASK 0x1F
-#define CCDC_BLK_ST_PXL_MASK 0x1FFF
-#define CCDC_BLK_SAMPLE_LN_MASK 3
-#define CCDC_BLK_SAMPLE_LN_SHIFT 13
-
-#define CCDC_NUM_LINE_CALC_MASK 3
-#define CCDC_NUM_LINE_CALC_SHIFT 14
-
-#define CCDC_BLK_DC_SUB_MASK 0x3FFF
-#define CCDC_BLK_COMP_MASK 0xFF
-#define CCDC_BLK_COMP_GB_COMP_SHIFT 8
-#define CCDC_BLK_COMP_GR_COMP_SHIFT 0
-#define CCDC_BLK_COMP_R_COMP_SHIFT 8
-#define CCDC_LATCH_ON_VSYNC_DISABLE (1 << 15)
-#define CCDC_LATCH_ON_VSYNC_ENABLE (0 << 15)
-#define CCDC_FPC_ENABLE (1 << 15)
-#define CCDC_FPC_FPC_NUM_MASK 0x7FFF
-#define CCDC_DATA_PACK_ENABLE (1 << 11)
-#define CCDC_FMT_HORZ_FMTLNH_MASK 0x1FFF
-#define CCDC_FMT_HORZ_FMTSPH_MASK 0x1FFF
-#define CCDC_FMT_HORZ_FMTSPH_SHIFT 16
-#define CCDC_FMT_VERT_FMTLNV_MASK 0x1FFF
-#define CCDC_FMT_VERT_FMTSLV_MASK 0x1FFF
-#define CCDC_FMT_VERT_FMTSLV_SHIFT 16
-#define CCDC_VP_OUT_VERT_NUM_MASK 0x3FFF
-#define CCDC_VP_OUT_VERT_NUM_SHIFT 17
-#define CCDC_VP_OUT_HORZ_NUM_MASK 0x1FFF
-#define CCDC_VP_OUT_HORZ_NUM_SHIFT 4
-#define CCDC_VP_OUT_HORZ_ST_MASK 0xF
-
-#define CCDC_CSC_COEF_INTEG_MASK 7
-#define CCDC_CSC_COEF_DECIMAL_MASK 0x1f
-#define CCDC_CSC_COEF_INTEG_SHIFT 5
-#define CCDC_CSCM_MSB_SHIFT 8
-#define CCDC_CSC_ENABLE 1
-#define CCDC_CSC_DEC_MAX 32
-
-#define CCDC_MFILT1_SHIFT 10
-#define CCDC_MFILT2_SHIFT 8
-#define CCDC_MED_FILT_THRESH 0x3FFF
-#define CCDC_LPF_MASK 1
-#define CCDC_LPF_SHIFT 14
-#define CCDC_OFFSET_MASK 0x3FF
-#define CCDC_DATASFT_MASK 7
-#define CCDC_DATASFT_SHIFT 8
-
-#define CCDC_DF_ENABLE 1
-
-#define CCDC_FMTPLEN_P0_MASK 0xF
-#define CCDC_FMTPLEN_P1_MASK 0xF
-#define CCDC_FMTPLEN_P2_MASK 7
-#define CCDC_FMTPLEN_P3_MASK 7
-#define CCDC_FMTPLEN_P0_SHIFT 0
-#define CCDC_FMTPLEN_P1_SHIFT 4
-#define CCDC_FMTPLEN_P2_SHIFT 8
-#define CCDC_FMTPLEN_P3_SHIFT 12
-
-#define CCDC_FMTSPH_MASK 0x1FFF
-#define CCDC_FMTLNH_MASK 0x1FFF
-#define CCDC_FMTSLV_MASK 0x1FFF
-#define CCDC_FMTLNV_MASK 0x7FFF
-#define CCDC_FMTRLEN_MASK 0x1FFF
-#define CCDC_FMTHCNT_MASK 0x1FFF
-
-#define CCDC_ADP_INIT_MASK 0x1FFF
-#define CCDC_ADP_LINE_SHIFT 13
-#define CCDC_ADP_LINE_MASK 3
-#define CCDC_FMTPGN_APTR_MASK 7
-
-#define CCDC_DFCCTL_GDFCEN_MASK 1
-#define CCDC_DFCCTL_VDFCEN_MASK 1
-#define CCDC_DFCCTL_VDFC_DISABLE (0 << 4)
-#define CCDC_DFCCTL_VDFCEN_SHIFT 4
-#define CCDC_DFCCTL_VDFCSL_MASK 3
-#define CCDC_DFCCTL_VDFCSL_SHIFT 5
-#define CCDC_DFCCTL_VDFCUDA_MASK 1
-#define CCDC_DFCCTL_VDFCUDA_SHIFT 7
-#define CCDC_DFCCTL_VDFLSFT_MASK 3
-#define CCDC_DFCCTL_VDFLSFT_SHIFT 8
-#define CCDC_DFCMEMCTL_DFCMARST_MASK 1
-#define CCDC_DFCMEMCTL_DFCMARST_SHIFT 2
-#define CCDC_DFCMEMCTL_DFCMWR_MASK 1
-#define CCDC_DFCMEMCTL_DFCMWR_SHIFT 0
-#define CCDC_DFCMEMCTL_INC_ADDR (0 << 2)
-
-#define CCDC_LSCCFG_GFTSF_MASK 7
-#define CCDC_LSCCFG_GFTSF_SHIFT 1
-#define CCDC_LSCCFG_GFTINV_MASK 0xf
-#define CCDC_LSCCFG_GFTINV_SHIFT 4
-#define CCDC_LSC_GFTABLE_SEL_MASK 3
-#define CCDC_LSC_GFTABLE_EPEL_SHIFT 8
-#define CCDC_LSC_GFTABLE_OPEL_SHIFT 10
-#define CCDC_LSC_GFTABLE_EPOL_SHIFT 12
-#define CCDC_LSC_GFTABLE_OPOL_SHIFT 14
-#define CCDC_LSC_GFMODE_MASK 3
-#define CCDC_LSC_GFMODE_SHIFT 4
-#define CCDC_LSC_DISABLE 0
-#define CCDC_LSC_ENABLE 1
-#define CCDC_LSC_TABLE1_SLC 0
-#define CCDC_LSC_TABLE2_SLC 1
-#define CCDC_LSC_TABLE3_SLC 2
-#define CCDC_LSC_MEMADDR_RESET (1 << 2)
-#define CCDC_LSC_MEMADDR_INCR (0 << 2)
-#define CCDC_LSC_FRAC_MASK_T1 0xFF
-#define CCDC_LSC_INT_MASK 3
-#define CCDC_LSC_FRAC_MASK 0x3FFF
-#define CCDC_LSC_CENTRE_MASK 0x3FFF
-#define CCDC_LSC_COEF_MASK 0xff
-#define CCDC_LSC_COEFL_SHIFT 0
-#define CCDC_LSC_COEFU_SHIFT 8
-#define CCDC_GAIN_MASK 0x7FF
-#define CCDC_SYNCEN_VDHDEN_MASK (1 << 0)
-#define CCDC_SYNCEN_WEN_MASK (1 << 1)
-#define CCDC_SYNCEN_WEN_SHIFT 1
-
-/* Power on Defaults in hardware */
-#define MODESET_DEFAULT 0x200
-#define CULH_DEFAULT 0xFFFF
-#define CULV_DEFAULT 0xFF
-#define GAIN_DEFAULT 256
-#define OUTCLIP_DEFAULT 0x3FFF
-#define LSCCFG2_DEFAULT 0xE
-
-#endif
diff --git a/drivers/staging/media/deprecated/vpfe_capture/dm644x_ccdc.c b/drivers/staging/media/deprecated/vpfe_capture/dm644x_ccdc.c
deleted file mode 100644
index 4a93e5ad6415..000000000000
--- a/drivers/staging/media/deprecated/vpfe_capture/dm644x_ccdc.c
+++ /dev/null
@@ -1,879 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright (C) 2006-2009 Texas Instruments Inc
- *
- * CCDC hardware module for DM6446
- * ------------------------------
- *
- * This module is for configuring CCD controller of DM6446 VPFE to capture
- * Raw yuv or Bayer RGB data from a decoder. CCDC has several modules
- * such as Defect Pixel Correction, Color Space Conversion etc to
- * pre-process the Raw Bayer RGB data, before writing it to SDRAM.
- * This file is named DM644x so that other variants such DM6443
- * may be supported using the same module.
- *
- * TODO: Test Raw bayer parameter settings and bayer capture
- * Split module parameter structure to module specific ioctl structs
- * investigate if enum used for user space type definition
- * to be replaced by #defines or integer
- */
-#include <linux/platform_device.h>
-#include <linux/uaccess.h>
-#include <linux/videodev2.h>
-#include <linux/gfp.h>
-#include <linux/err.h>
-#include <linux/module.h>
-
-#include "dm644x_ccdc.h"
-#include <media/davinci/vpss.h>
-
-#include "dm644x_ccdc_regs.h"
-#include "ccdc_hw_device.h"
-
-MODULE_LICENSE("GPL");
-MODULE_DESCRIPTION("CCDC Driver for DM6446");
-MODULE_AUTHOR("Texas Instruments");
-
-static struct ccdc_oper_config {
- struct device *dev;
- /* CCDC interface type */
- enum vpfe_hw_if_type if_type;
- /* Raw Bayer configuration */
- struct ccdc_params_raw bayer;
- /* YCbCr configuration */
- struct ccdc_params_ycbcr ycbcr;
- /* ccdc base address */
- void __iomem *base_addr;
-} ccdc_cfg = {
- /* Raw configurations */
- .bayer = {
- .pix_fmt = CCDC_PIXFMT_RAW,
- .frm_fmt = CCDC_FRMFMT_PROGRESSIVE,
- .win = CCDC_WIN_VGA,
- .fid_pol = VPFE_PINPOL_POSITIVE,
- .vd_pol = VPFE_PINPOL_POSITIVE,
- .hd_pol = VPFE_PINPOL_POSITIVE,
- .config_params = {
- .data_sz = CCDC_DATA_10BITS,
- },
- },
- .ycbcr = {
- .pix_fmt = CCDC_PIXFMT_YCBCR_8BIT,
- .frm_fmt = CCDC_FRMFMT_INTERLACED,
- .win = CCDC_WIN_PAL,
- .fid_pol = VPFE_PINPOL_POSITIVE,
- .vd_pol = VPFE_PINPOL_POSITIVE,
- .hd_pol = VPFE_PINPOL_POSITIVE,
- .bt656_enable = 1,
- .pix_order = CCDC_PIXORDER_CBYCRY,
- .buf_type = CCDC_BUFTYPE_FLD_INTERLEAVED
- },
-};
-
-#define CCDC_MAX_RAW_YUV_FORMATS 2
-
-/* Raw Bayer formats */
-static u32 ccdc_raw_bayer_pix_formats[] =
- {V4L2_PIX_FMT_SBGGR8, V4L2_PIX_FMT_SBGGR16};
-
-/* Raw YUV formats */
-static u32 ccdc_raw_yuv_pix_formats[] =
- {V4L2_PIX_FMT_UYVY, V4L2_PIX_FMT_YUYV};
-
-/* CCDC Save/Restore context */
-static u32 ccdc_ctx[CCDC_REG_END / sizeof(u32)];
-
-/* register access routines */
-static inline u32 regr(u32 offset)
-{
- return __raw_readl(ccdc_cfg.base_addr + offset);
-}
-
-static inline void regw(u32 val, u32 offset)
-{
- __raw_writel(val, ccdc_cfg.base_addr + offset);
-}
-
-static void ccdc_enable(int flag)
-{
- regw(flag, CCDC_PCR);
-}
-
-static void ccdc_enable_vport(int flag)
-{
- if (flag)
- /* enable video port */
- regw(CCDC_ENABLE_VIDEO_PORT, CCDC_FMTCFG);
- else
- regw(CCDC_DISABLE_VIDEO_PORT, CCDC_FMTCFG);
-}
-
-/*
- * ccdc_setwin()
- * This function will configure the window size
- * to be capture in CCDC reg
- */
-static void ccdc_setwin(struct v4l2_rect *image_win,
- enum ccdc_frmfmt frm_fmt,
- int ppc)
-{
- int horz_start, horz_nr_pixels;
- int vert_start, vert_nr_lines;
- int val = 0, mid_img = 0;
-
- dev_dbg(ccdc_cfg.dev, "\nStarting ccdc_setwin...");
- /*
- * ppc - per pixel count. indicates how many pixels per cell
- * output to SDRAM. example, for ycbcr, it is one y and one c, so 2.
- * raw capture this is 1
- */
- horz_start = image_win->left << (ppc - 1);
- horz_nr_pixels = (image_win->width << (ppc - 1)) - 1;
- regw((horz_start << CCDC_HORZ_INFO_SPH_SHIFT) | horz_nr_pixels,
- CCDC_HORZ_INFO);
-
- vert_start = image_win->top;
-
- if (frm_fmt == CCDC_FRMFMT_INTERLACED) {
- vert_nr_lines = (image_win->height >> 1) - 1;
- vert_start >>= 1;
- /* Since first line doesn't have any data */
- vert_start += 1;
- /* configure VDINT0 */
- val = (vert_start << CCDC_VDINT_VDINT0_SHIFT);
- regw(val, CCDC_VDINT);
-
- } else {
- /* Since first line doesn't have any data */
- vert_start += 1;
- vert_nr_lines = image_win->height - 1;
- /*
- * configure VDINT0 and VDINT1. VDINT1 will be at half
- * of image height
- */
- mid_img = vert_start + (image_win->height / 2);
- val = (vert_start << CCDC_VDINT_VDINT0_SHIFT) |
- (mid_img & CCDC_VDINT_VDINT1_MASK);
- regw(val, CCDC_VDINT);
-
- }
- regw((vert_start << CCDC_VERT_START_SLV0_SHIFT) | vert_start,
- CCDC_VERT_START);
- regw(vert_nr_lines, CCDC_VERT_LINES);
- dev_dbg(ccdc_cfg.dev, "\nEnd of ccdc_setwin...");
-}
-
-static void ccdc_readregs(void)
-{
- unsigned int val = 0;
-
- val = regr(CCDC_ALAW);
- dev_notice(ccdc_cfg.dev, "\nReading 0x%x to ALAW...\n", val);
- val = regr(CCDC_CLAMP);
- dev_notice(ccdc_cfg.dev, "\nReading 0x%x to CLAMP...\n", val);
- val = regr(CCDC_DCSUB);
- dev_notice(ccdc_cfg.dev, "\nReading 0x%x to DCSUB...\n", val);
- val = regr(CCDC_BLKCMP);
- dev_notice(ccdc_cfg.dev, "\nReading 0x%x to BLKCMP...\n", val);
- val = regr(CCDC_FPC_ADDR);
- dev_notice(ccdc_cfg.dev, "\nReading 0x%x to FPC_ADDR...\n", val);
- val = regr(CCDC_FPC);
- dev_notice(ccdc_cfg.dev, "\nReading 0x%x to FPC...\n", val);
- val = regr(CCDC_FMTCFG);
- dev_notice(ccdc_cfg.dev, "\nReading 0x%x to FMTCFG...\n", val);
- val = regr(CCDC_COLPTN);
- dev_notice(ccdc_cfg.dev, "\nReading 0x%x to COLPTN...\n", val);
- val = regr(CCDC_FMT_HORZ);
- dev_notice(ccdc_cfg.dev, "\nReading 0x%x to FMT_HORZ...\n", val);
- val = regr(CCDC_FMT_VERT);
- dev_notice(ccdc_cfg.dev, "\nReading 0x%x to FMT_VERT...\n", val);
- val = regr(CCDC_HSIZE_OFF);
- dev_notice(ccdc_cfg.dev, "\nReading 0x%x to HSIZE_OFF...\n", val);
- val = regr(CCDC_SDOFST);
- dev_notice(ccdc_cfg.dev, "\nReading 0x%x to SDOFST...\n", val);
- val = regr(CCDC_VP_OUT);
- dev_notice(ccdc_cfg.dev, "\nReading 0x%x to VP_OUT...\n", val);
- val = regr(CCDC_SYN_MODE);
- dev_notice(ccdc_cfg.dev, "\nReading 0x%x to SYN_MODE...\n", val);
- val = regr(CCDC_HORZ_INFO);
- dev_notice(ccdc_cfg.dev, "\nReading 0x%x to HORZ_INFO...\n", val);
- val = regr(CCDC_VERT_START);
- dev_notice(ccdc_cfg.dev, "\nReading 0x%x to VERT_START...\n", val);
- val = regr(CCDC_VERT_LINES);
- dev_notice(ccdc_cfg.dev, "\nReading 0x%x to VERT_LINES...\n", val);
-}
-
-static int ccdc_close(struct device *dev)
-{
- return 0;
-}
-
-/*
- * ccdc_restore_defaults()
- * This function will write defaults to all CCDC registers
- */
-static void ccdc_restore_defaults(void)
-{
- int i;
-
- /* disable CCDC */
- ccdc_enable(0);
- /* set all registers to default value */
- for (i = 4; i <= 0x94; i += 4)
- regw(0, i);
- regw(CCDC_NO_CULLING, CCDC_CULLING);
- regw(CCDC_GAMMA_BITS_11_2, CCDC_ALAW);
-}
-
-static int ccdc_open(struct device *device)
-{
- ccdc_restore_defaults();
- if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
- ccdc_enable_vport(1);
- return 0;
-}
-
-static void ccdc_sbl_reset(void)
-{
- vpss_clear_wbl_overflow(VPSS_PCR_CCDC_WBL_O);
-}
-
-/*
- * ccdc_config_ycbcr()
- * This function will configure CCDC for YCbCr video capture
- */
-static void ccdc_config_ycbcr(void)
-{
- struct ccdc_params_ycbcr *params = &ccdc_cfg.ycbcr;
- u32 syn_mode;
-
- dev_dbg(ccdc_cfg.dev, "\nStarting ccdc_config_ycbcr...");
- /*
- * first restore the CCDC registers to default values
- * This is important since we assume default values to be set in
- * a lot of registers that we didn't touch
- */
- ccdc_restore_defaults();
-
- /*
- * configure pixel format, frame format, configure video frame
- * format, enable output to SDRAM, enable internal timing generator
- * and 8bit pack mode
- */
- syn_mode = (((params->pix_fmt & CCDC_SYN_MODE_INPMOD_MASK) <<
- CCDC_SYN_MODE_INPMOD_SHIFT) |
- ((params->frm_fmt & CCDC_SYN_FLDMODE_MASK) <<
- CCDC_SYN_FLDMODE_SHIFT) | CCDC_VDHDEN_ENABLE |
- CCDC_WEN_ENABLE | CCDC_DATA_PACK_ENABLE);
-
- /* setup BT.656 sync mode */
- if (params->bt656_enable) {
- regw(CCDC_REC656IF_BT656_EN, CCDC_REC656IF);
-
- /*
- * configure the FID, VD, HD pin polarity,
- * fld,hd pol positive, vd negative, 8-bit data
- */
- syn_mode |= CCDC_SYN_MODE_VD_POL_NEGATIVE;
- if (ccdc_cfg.if_type == VPFE_BT656_10BIT)
- syn_mode |= CCDC_SYN_MODE_10BITS;
- else
- syn_mode |= CCDC_SYN_MODE_8BITS;
- } else {
- /* y/c external sync mode */
- syn_mode |= (((params->fid_pol & CCDC_FID_POL_MASK) <<
- CCDC_FID_POL_SHIFT) |
- ((params->hd_pol & CCDC_HD_POL_MASK) <<
- CCDC_HD_POL_SHIFT) |
- ((params->vd_pol & CCDC_VD_POL_MASK) <<
- CCDC_VD_POL_SHIFT));
- }
- regw(syn_mode, CCDC_SYN_MODE);
-
- /* configure video window */
- ccdc_setwin(¶ms->win, params->frm_fmt, 2);
-
- /*
- * configure the order of y cb cr in SDRAM, and disable latch
- * internal register on vsync
- */
- if (ccdc_cfg.if_type == VPFE_BT656_10BIT)
- regw((params->pix_order << CCDC_CCDCFG_Y8POS_SHIFT) |
- CCDC_LATCH_ON_VSYNC_DISABLE | CCDC_CCDCFG_BW656_10BIT,
- CCDC_CCDCFG);
- else
- regw((params->pix_order << CCDC_CCDCFG_Y8POS_SHIFT) |
- CCDC_LATCH_ON_VSYNC_DISABLE, CCDC_CCDCFG);
-
- /*
- * configure the horizontal line offset. This should be a
- * on 32 byte boundary. So clear LSB 5 bits
- */
- regw(((params->win.width * 2 + 31) & ~0x1f), CCDC_HSIZE_OFF);
-
- /* configure the memory line offset */
- if (params->buf_type == CCDC_BUFTYPE_FLD_INTERLEAVED)
- /* two fields are interleaved in memory */
- regw(CCDC_SDOFST_FIELD_INTERLEAVED, CCDC_SDOFST);
-
- ccdc_sbl_reset();
- dev_dbg(ccdc_cfg.dev, "\nEnd of ccdc_config_ycbcr...\n");
-}
-
-static void ccdc_config_black_clamp(struct ccdc_black_clamp *bclamp)
-{
- u32 val;
-
- if (!bclamp->enable) {
- /* configure DCSub */
- val = (bclamp->dc_sub) & CCDC_BLK_DC_SUB_MASK;
- regw(val, CCDC_DCSUB);
- dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to DCSUB...\n", val);
- regw(CCDC_CLAMP_DEFAULT_VAL, CCDC_CLAMP);
- dev_dbg(ccdc_cfg.dev, "\nWriting 0x0000 to CLAMP...\n");
- return;
- }
- /*
- * Configure gain, Start pixel, No of line to be avg,
- * No of pixel/line to be avg, & Enable the Black clamping
- */
- val = ((bclamp->sgain & CCDC_BLK_SGAIN_MASK) |
- ((bclamp->start_pixel & CCDC_BLK_ST_PXL_MASK) <<
- CCDC_BLK_ST_PXL_SHIFT) |
- ((bclamp->sample_ln & CCDC_BLK_SAMPLE_LINE_MASK) <<
- CCDC_BLK_SAMPLE_LINE_SHIFT) |
- ((bclamp->sample_pixel & CCDC_BLK_SAMPLE_LN_MASK) <<
- CCDC_BLK_SAMPLE_LN_SHIFT) | CCDC_BLK_CLAMP_ENABLE);
- regw(val, CCDC_CLAMP);
- dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to CLAMP...\n", val);
- /* If Black clamping is enable then make dcsub 0 */
- regw(CCDC_DCSUB_DEFAULT_VAL, CCDC_DCSUB);
- dev_dbg(ccdc_cfg.dev, "\nWriting 0x00000000 to DCSUB...\n");
-}
-
-static void ccdc_config_black_compense(struct ccdc_black_compensation *bcomp)
-{
- u32 val;
-
- val = ((bcomp->b & CCDC_BLK_COMP_MASK) |
- ((bcomp->gb & CCDC_BLK_COMP_MASK) <<
- CCDC_BLK_COMP_GB_COMP_SHIFT) |
- ((bcomp->gr & CCDC_BLK_COMP_MASK) <<
- CCDC_BLK_COMP_GR_COMP_SHIFT) |
- ((bcomp->r & CCDC_BLK_COMP_MASK) <<
- CCDC_BLK_COMP_R_COMP_SHIFT));
- regw(val, CCDC_BLKCMP);
-}
-
-/*
- * ccdc_config_raw()
- * This function will configure CCDC for Raw capture mode
- */
-static void ccdc_config_raw(void)
-{
- struct ccdc_params_raw *params = &ccdc_cfg.bayer;
- struct ccdc_config_params_raw *config_params =
- &ccdc_cfg.bayer.config_params;
- unsigned int syn_mode = 0;
- unsigned int val;
-
- dev_dbg(ccdc_cfg.dev, "\nStarting ccdc_config_raw...");
-
- /* Reset CCDC */
- ccdc_restore_defaults();
-
- /* Disable latching function registers on VSYNC */
- regw(CCDC_LATCH_ON_VSYNC_DISABLE, CCDC_CCDCFG);
-
- /*
- * Configure the vertical sync polarity(SYN_MODE.VDPOL),
- * horizontal sync polarity (SYN_MODE.HDPOL), frame id polarity
- * (SYN_MODE.FLDPOL), frame format(progressive or interlace),
- * data size(SYNMODE.DATSIZ), &pixel format (Input mode), output
- * SDRAM, enable internal timing generator
- */
- syn_mode =
- (((params->vd_pol & CCDC_VD_POL_MASK) << CCDC_VD_POL_SHIFT) |
- ((params->hd_pol & CCDC_HD_POL_MASK) << CCDC_HD_POL_SHIFT) |
- ((params->fid_pol & CCDC_FID_POL_MASK) << CCDC_FID_POL_SHIFT) |
- ((params->frm_fmt & CCDC_FRM_FMT_MASK) << CCDC_FRM_FMT_SHIFT) |
- ((config_params->data_sz & CCDC_DATA_SZ_MASK) <<
- CCDC_DATA_SZ_SHIFT) |
- ((params->pix_fmt & CCDC_PIX_FMT_MASK) << CCDC_PIX_FMT_SHIFT) |
- CCDC_WEN_ENABLE | CCDC_VDHDEN_ENABLE);
-
- /* Enable and configure aLaw register if needed */
- if (config_params->alaw.enable) {
- val = ((config_params->alaw.gamma_wd &
- CCDC_ALAW_GAMMA_WD_MASK) | CCDC_ALAW_ENABLE);
- regw(val, CCDC_ALAW);
- dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to ALAW...\n", val);
- }
-
- /* Configure video window */
- ccdc_setwin(¶ms->win, params->frm_fmt, CCDC_PPC_RAW);
-
- /* Configure Black Clamp */
- ccdc_config_black_clamp(&config_params->blk_clamp);
-
- /* Configure Black level compensation */
- ccdc_config_black_compense(&config_params->blk_comp);
-
- /* If data size is 8 bit then pack the data */
- if ((config_params->data_sz == CCDC_DATA_8BITS) ||
- config_params->alaw.enable)
- syn_mode |= CCDC_DATA_PACK_ENABLE;
-
- /* disable video port */
- val = CCDC_DISABLE_VIDEO_PORT;
-
- if (config_params->data_sz == CCDC_DATA_8BITS)
- val |= (CCDC_DATA_10BITS & CCDC_FMTCFG_VPIN_MASK)
- << CCDC_FMTCFG_VPIN_SHIFT;
- else
- val |= (config_params->data_sz & CCDC_FMTCFG_VPIN_MASK)
- << CCDC_FMTCFG_VPIN_SHIFT;
- /* Write value in FMTCFG */
- regw(val, CCDC_FMTCFG);
-
- dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to FMTCFG...\n", val);
- /* Configure the color pattern according to mt9t001 sensor */
- regw(CCDC_COLPTN_VAL, CCDC_COLPTN);
-
- dev_dbg(ccdc_cfg.dev, "\nWriting 0xBB11BB11 to COLPTN...\n");
- /*
- * Configure Data formatter(Video port) pixel selection
- * (FMT_HORZ, FMT_VERT)
- */
- val = ((params->win.left & CCDC_FMT_HORZ_FMTSPH_MASK) <<
- CCDC_FMT_HORZ_FMTSPH_SHIFT) |
- (params->win.width & CCDC_FMT_HORZ_FMTLNH_MASK);
- regw(val, CCDC_FMT_HORZ);
-
- dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to FMT_HORZ...\n", val);
- val = (params->win.top & CCDC_FMT_VERT_FMTSLV_MASK)
- << CCDC_FMT_VERT_FMTSLV_SHIFT;
- if (params->frm_fmt == CCDC_FRMFMT_PROGRESSIVE)
- val |= (params->win.height) & CCDC_FMT_VERT_FMTLNV_MASK;
- else
- val |= (params->win.height >> 1) & CCDC_FMT_VERT_FMTLNV_MASK;
-
- dev_dbg(ccdc_cfg.dev, "\nparams->win.height 0x%x ...\n",
- params->win.height);
- regw(val, CCDC_FMT_VERT);
-
- dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to FMT_VERT...\n", val);
-
- dev_dbg(ccdc_cfg.dev, "\nbelow regw(val, FMT_VERT)...");
-
- /*
- * Configure Horizontal offset register. If pack 8 is enabled then
- * 1 pixel will take 1 byte
- */
- if ((config_params->data_sz == CCDC_DATA_8BITS) ||
- config_params->alaw.enable)
- regw((params->win.width + CCDC_32BYTE_ALIGN_VAL) &
- CCDC_HSIZE_OFF_MASK, CCDC_HSIZE_OFF);
- else
- /* else one pixel will take 2 byte */
- regw(((params->win.width * CCDC_TWO_BYTES_PER_PIXEL) +
- CCDC_32BYTE_ALIGN_VAL) & CCDC_HSIZE_OFF_MASK,
- CCDC_HSIZE_OFF);
-
- /* Set value for SDOFST */
- if (params->frm_fmt == CCDC_FRMFMT_INTERLACED) {
- if (params->image_invert_enable) {
- /* For intelace inverse mode */
- regw(CCDC_INTERLACED_IMAGE_INVERT, CCDC_SDOFST);
- dev_dbg(ccdc_cfg.dev, "\nWriting 0x4B6D to SDOFST..\n");
- }
-
- else {
- /* For intelace non inverse mode */
- regw(CCDC_INTERLACED_NO_IMAGE_INVERT, CCDC_SDOFST);
- dev_dbg(ccdc_cfg.dev, "\nWriting 0x0249 to SDOFST..\n");
- }
- } else if (params->frm_fmt == CCDC_FRMFMT_PROGRESSIVE) {
- regw(CCDC_PROGRESSIVE_NO_IMAGE_INVERT, CCDC_SDOFST);
- dev_dbg(ccdc_cfg.dev, "\nWriting 0x0000 to SDOFST...\n");
- }
-
- /*
- * Configure video port pixel selection (VPOUT)
- * Here -1 is to make the height value less than FMT_VERT.FMTLNV
- */
- if (params->frm_fmt == CCDC_FRMFMT_PROGRESSIVE)
- val = (((params->win.height - 1) & CCDC_VP_OUT_VERT_NUM_MASK))
- << CCDC_VP_OUT_VERT_NUM_SHIFT;
- else
- val =
- ((((params->win.height >> CCDC_INTERLACED_HEIGHT_SHIFT) -
- 1) & CCDC_VP_OUT_VERT_NUM_MASK)) <<
- CCDC_VP_OUT_VERT_NUM_SHIFT;
-
- val |= ((((params->win.width))) & CCDC_VP_OUT_HORZ_NUM_MASK)
- << CCDC_VP_OUT_HORZ_NUM_SHIFT;
- val |= (params->win.left) & CCDC_VP_OUT_HORZ_ST_MASK;
- regw(val, CCDC_VP_OUT);
-
- dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to VP_OUT...\n", val);
- regw(syn_mode, CCDC_SYN_MODE);
- dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to SYN_MODE...\n", syn_mode);
-
- ccdc_sbl_reset();
- dev_dbg(ccdc_cfg.dev, "\nend of ccdc_config_raw...");
- ccdc_readregs();
-}
-
-static int ccdc_configure(void)
-{
- if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
- ccdc_config_raw();
- else
- ccdc_config_ycbcr();
- return 0;
-}
-
-static int ccdc_set_buftype(enum ccdc_buftype buf_type)
-{
- if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
- ccdc_cfg.bayer.buf_type = buf_type;
- else
- ccdc_cfg.ycbcr.buf_type = buf_type;
- return 0;
-}
-
-static enum ccdc_buftype ccdc_get_buftype(void)
-{
- if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
- return ccdc_cfg.bayer.buf_type;
- return ccdc_cfg.ycbcr.buf_type;
-}
-
-static int ccdc_enum_pix(u32 *pix, int i)
-{
- int ret = -EINVAL;
- if (ccdc_cfg.if_type == VPFE_RAW_BAYER) {
- if (i < ARRAY_SIZE(ccdc_raw_bayer_pix_formats)) {
- *pix = ccdc_raw_bayer_pix_formats[i];
- ret = 0;
- }
- } else {
- if (i < ARRAY_SIZE(ccdc_raw_yuv_pix_formats)) {
- *pix = ccdc_raw_yuv_pix_formats[i];
- ret = 0;
- }
- }
- return ret;
-}
-
-static int ccdc_set_pixel_format(u32 pixfmt)
-{
- if (ccdc_cfg.if_type == VPFE_RAW_BAYER) {
- ccdc_cfg.bayer.pix_fmt = CCDC_PIXFMT_RAW;
- if (pixfmt == V4L2_PIX_FMT_SBGGR8)
- ccdc_cfg.bayer.config_params.alaw.enable = 1;
- else if (pixfmt != V4L2_PIX_FMT_SBGGR16)
- return -EINVAL;
- } else {
- if (pixfmt == V4L2_PIX_FMT_YUYV)
- ccdc_cfg.ycbcr.pix_order = CCDC_PIXORDER_YCBYCR;
- else if (pixfmt == V4L2_PIX_FMT_UYVY)
- ccdc_cfg.ycbcr.pix_order = CCDC_PIXORDER_CBYCRY;
- else
- return -EINVAL;
- }
- return 0;
-}
-
-static u32 ccdc_get_pixel_format(void)
-{
- struct ccdc_a_law *alaw = &ccdc_cfg.bayer.config_params.alaw;
- u32 pixfmt;
-
- if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
- if (alaw->enable)
- pixfmt = V4L2_PIX_FMT_SBGGR8;
- else
- pixfmt = V4L2_PIX_FMT_SBGGR16;
- else {
- if (ccdc_cfg.ycbcr.pix_order == CCDC_PIXORDER_YCBYCR)
- pixfmt = V4L2_PIX_FMT_YUYV;
- else
- pixfmt = V4L2_PIX_FMT_UYVY;
- }
- return pixfmt;
-}
-
-static int ccdc_set_image_window(struct v4l2_rect *win)
-{
- if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
- ccdc_cfg.bayer.win = *win;
- else
- ccdc_cfg.ycbcr.win = *win;
- return 0;
-}
-
-static void ccdc_get_image_window(struct v4l2_rect *win)
-{
- if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
- *win = ccdc_cfg.bayer.win;
- else
- *win = ccdc_cfg.ycbcr.win;
-}
-
-static unsigned int ccdc_get_line_length(void)
-{
- struct ccdc_config_params_raw *config_params =
- &ccdc_cfg.bayer.config_params;
- unsigned int len;
-
- if (ccdc_cfg.if_type == VPFE_RAW_BAYER) {
- if ((config_params->alaw.enable) ||
- (config_params->data_sz == CCDC_DATA_8BITS))
- len = ccdc_cfg.bayer.win.width;
- else
- len = ccdc_cfg.bayer.win.width * 2;
- } else
- len = ccdc_cfg.ycbcr.win.width * 2;
- return ALIGN(len, 32);
-}
-
-static int ccdc_set_frame_format(enum ccdc_frmfmt frm_fmt)
-{
- if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
- ccdc_cfg.bayer.frm_fmt = frm_fmt;
- else
- ccdc_cfg.ycbcr.frm_fmt = frm_fmt;
- return 0;
-}
-
-static enum ccdc_frmfmt ccdc_get_frame_format(void)
-{
- if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
- return ccdc_cfg.bayer.frm_fmt;
- else
- return ccdc_cfg.ycbcr.frm_fmt;
-}
-
-static int ccdc_getfid(void)
-{
- return (regr(CCDC_SYN_MODE) >> 15) & 1;
-}
-
-/* misc operations */
-static inline void ccdc_setfbaddr(unsigned long addr)
-{
- regw(addr & 0xffffffe0, CCDC_SDR_ADDR);
-}
-
-static int ccdc_set_hw_if_params(struct vpfe_hw_if_param *params)
-{
- ccdc_cfg.if_type = params->if_type;
-
- switch (params->if_type) {
- case VPFE_BT656:
- case VPFE_YCBCR_SYNC_16:
- case VPFE_YCBCR_SYNC_8:
- case VPFE_BT656_10BIT:
- ccdc_cfg.ycbcr.vd_pol = params->vdpol;
- ccdc_cfg.ycbcr.hd_pol = params->hdpol;
- break;
- default:
- /* TODO add support for raw bayer here */
- return -EINVAL;
- }
- return 0;
-}
-
-static void ccdc_save_context(void)
-{
- ccdc_ctx[CCDC_PCR >> 2] = regr(CCDC_PCR);
- ccdc_ctx[CCDC_SYN_MODE >> 2] = regr(CCDC_SYN_MODE);
- ccdc_ctx[CCDC_HD_VD_WID >> 2] = regr(CCDC_HD_VD_WID);
- ccdc_ctx[CCDC_PIX_LINES >> 2] = regr(CCDC_PIX_LINES);
- ccdc_ctx[CCDC_HORZ_INFO >> 2] = regr(CCDC_HORZ_INFO);
- ccdc_ctx[CCDC_VERT_START >> 2] = regr(CCDC_VERT_START);
- ccdc_ctx[CCDC_VERT_LINES >> 2] = regr(CCDC_VERT_LINES);
- ccdc_ctx[CCDC_CULLING >> 2] = regr(CCDC_CULLING);
- ccdc_ctx[CCDC_HSIZE_OFF >> 2] = regr(CCDC_HSIZE_OFF);
- ccdc_ctx[CCDC_SDOFST >> 2] = regr(CCDC_SDOFST);
- ccdc_ctx[CCDC_SDR_ADDR >> 2] = regr(CCDC_SDR_ADDR);
- ccdc_ctx[CCDC_CLAMP >> 2] = regr(CCDC_CLAMP);
- ccdc_ctx[CCDC_DCSUB >> 2] = regr(CCDC_DCSUB);
- ccdc_ctx[CCDC_COLPTN >> 2] = regr(CCDC_COLPTN);
- ccdc_ctx[CCDC_BLKCMP >> 2] = regr(CCDC_BLKCMP);
- ccdc_ctx[CCDC_FPC >> 2] = regr(CCDC_FPC);
- ccdc_ctx[CCDC_FPC_ADDR >> 2] = regr(CCDC_FPC_ADDR);
- ccdc_ctx[CCDC_VDINT >> 2] = regr(CCDC_VDINT);
- ccdc_ctx[CCDC_ALAW >> 2] = regr(CCDC_ALAW);
- ccdc_ctx[CCDC_REC656IF >> 2] = regr(CCDC_REC656IF);
- ccdc_ctx[CCDC_CCDCFG >> 2] = regr(CCDC_CCDCFG);
- ccdc_ctx[CCDC_FMTCFG >> 2] = regr(CCDC_FMTCFG);
- ccdc_ctx[CCDC_FMT_HORZ >> 2] = regr(CCDC_FMT_HORZ);
- ccdc_ctx[CCDC_FMT_VERT >> 2] = regr(CCDC_FMT_VERT);
- ccdc_ctx[CCDC_FMT_ADDR0 >> 2] = regr(CCDC_FMT_ADDR0);
- ccdc_ctx[CCDC_FMT_ADDR1 >> 2] = regr(CCDC_FMT_ADDR1);
- ccdc_ctx[CCDC_FMT_ADDR2 >> 2] = regr(CCDC_FMT_ADDR2);
- ccdc_ctx[CCDC_FMT_ADDR3 >> 2] = regr(CCDC_FMT_ADDR3);
- ccdc_ctx[CCDC_FMT_ADDR4 >> 2] = regr(CCDC_FMT_ADDR4);
- ccdc_ctx[CCDC_FMT_ADDR5 >> 2] = regr(CCDC_FMT_ADDR5);
- ccdc_ctx[CCDC_FMT_ADDR6 >> 2] = regr(CCDC_FMT_ADDR6);
- ccdc_ctx[CCDC_FMT_ADDR7 >> 2] = regr(CCDC_FMT_ADDR7);
- ccdc_ctx[CCDC_PRGEVEN_0 >> 2] = regr(CCDC_PRGEVEN_0);
- ccdc_ctx[CCDC_PRGEVEN_1 >> 2] = regr(CCDC_PRGEVEN_1);
- ccdc_ctx[CCDC_PRGODD_0 >> 2] = regr(CCDC_PRGODD_0);
- ccdc_ctx[CCDC_PRGODD_1 >> 2] = regr(CCDC_PRGODD_1);
- ccdc_ctx[CCDC_VP_OUT >> 2] = regr(CCDC_VP_OUT);
-}
-
-static void ccdc_restore_context(void)
-{
- regw(ccdc_ctx[CCDC_SYN_MODE >> 2], CCDC_SYN_MODE);
- regw(ccdc_ctx[CCDC_HD_VD_WID >> 2], CCDC_HD_VD_WID);
- regw(ccdc_ctx[CCDC_PIX_LINES >> 2], CCDC_PIX_LINES);
- regw(ccdc_ctx[CCDC_HORZ_INFO >> 2], CCDC_HORZ_INFO);
- regw(ccdc_ctx[CCDC_VERT_START >> 2], CCDC_VERT_START);
- regw(ccdc_ctx[CCDC_VERT_LINES >> 2], CCDC_VERT_LINES);
- regw(ccdc_ctx[CCDC_CULLING >> 2], CCDC_CULLING);
- regw(ccdc_ctx[CCDC_HSIZE_OFF >> 2], CCDC_HSIZE_OFF);
- regw(ccdc_ctx[CCDC_SDOFST >> 2], CCDC_SDOFST);
- regw(ccdc_ctx[CCDC_SDR_ADDR >> 2], CCDC_SDR_ADDR);
- regw(ccdc_ctx[CCDC_CLAMP >> 2], CCDC_CLAMP);
- regw(ccdc_ctx[CCDC_DCSUB >> 2], CCDC_DCSUB);
- regw(ccdc_ctx[CCDC_COLPTN >> 2], CCDC_COLPTN);
- regw(ccdc_ctx[CCDC_BLKCMP >> 2], CCDC_BLKCMP);
- regw(ccdc_ctx[CCDC_FPC >> 2], CCDC_FPC);
- regw(ccdc_ctx[CCDC_FPC_ADDR >> 2], CCDC_FPC_ADDR);
- regw(ccdc_ctx[CCDC_VDINT >> 2], CCDC_VDINT);
- regw(ccdc_ctx[CCDC_ALAW >> 2], CCDC_ALAW);
- regw(ccdc_ctx[CCDC_REC656IF >> 2], CCDC_REC656IF);
- regw(ccdc_ctx[CCDC_CCDCFG >> 2], CCDC_CCDCFG);
- regw(ccdc_ctx[CCDC_FMTCFG >> 2], CCDC_FMTCFG);
- regw(ccdc_ctx[CCDC_FMT_HORZ >> 2], CCDC_FMT_HORZ);
- regw(ccdc_ctx[CCDC_FMT_VERT >> 2], CCDC_FMT_VERT);
- regw(ccdc_ctx[CCDC_FMT_ADDR0 >> 2], CCDC_FMT_ADDR0);
- regw(ccdc_ctx[CCDC_FMT_ADDR1 >> 2], CCDC_FMT_ADDR1);
- regw(ccdc_ctx[CCDC_FMT_ADDR2 >> 2], CCDC_FMT_ADDR2);
- regw(ccdc_ctx[CCDC_FMT_ADDR3 >> 2], CCDC_FMT_ADDR3);
- regw(ccdc_ctx[CCDC_FMT_ADDR4 >> 2], CCDC_FMT_ADDR4);
- regw(ccdc_ctx[CCDC_FMT_ADDR5 >> 2], CCDC_FMT_ADDR5);
- regw(ccdc_ctx[CCDC_FMT_ADDR6 >> 2], CCDC_FMT_ADDR6);
- regw(ccdc_ctx[CCDC_FMT_ADDR7 >> 2], CCDC_FMT_ADDR7);
- regw(ccdc_ctx[CCDC_PRGEVEN_0 >> 2], CCDC_PRGEVEN_0);
- regw(ccdc_ctx[CCDC_PRGEVEN_1 >> 2], CCDC_PRGEVEN_1);
- regw(ccdc_ctx[CCDC_PRGODD_0 >> 2], CCDC_PRGODD_0);
- regw(ccdc_ctx[CCDC_PRGODD_1 >> 2], CCDC_PRGODD_1);
- regw(ccdc_ctx[CCDC_VP_OUT >> 2], CCDC_VP_OUT);
- regw(ccdc_ctx[CCDC_PCR >> 2], CCDC_PCR);
-}
-static const struct ccdc_hw_device ccdc_hw_dev = {
- .name = "DM6446 CCDC",
- .owner = THIS_MODULE,
- .hw_ops = {
- .open = ccdc_open,
- .close = ccdc_close,
- .reset = ccdc_sbl_reset,
- .enable = ccdc_enable,
- .set_hw_if_params = ccdc_set_hw_if_params,
- .configure = ccdc_configure,
- .set_buftype = ccdc_set_buftype,
- .get_buftype = ccdc_get_buftype,
- .enum_pix = ccdc_enum_pix,
- .set_pixel_format = ccdc_set_pixel_format,
- .get_pixel_format = ccdc_get_pixel_format,
- .set_frame_format = ccdc_set_frame_format,
- .get_frame_format = ccdc_get_frame_format,
- .set_image_window = ccdc_set_image_window,
- .get_image_window = ccdc_get_image_window,
- .get_line_length = ccdc_get_line_length,
- .setfbaddr = ccdc_setfbaddr,
- .getfid = ccdc_getfid,
- },
-};
-
-static int dm644x_ccdc_probe(struct platform_device *pdev)
-{
- struct resource *res;
- int status = 0;
-
- /*
- * first try to register with vpfe. If not correct platform, then we
- * don't have to iomap
- */
- status = vpfe_register_ccdc_device(&ccdc_hw_dev);
- if (status < 0)
- return status;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!res) {
- status = -ENODEV;
- goto fail_nores;
- }
-
- res = request_mem_region(res->start, resource_size(res), res->name);
- if (!res) {
- status = -EBUSY;
- goto fail_nores;
- }
-
- ccdc_cfg.base_addr = ioremap(res->start, resource_size(res));
- if (!ccdc_cfg.base_addr) {
- status = -ENOMEM;
- goto fail_nomem;
- }
-
- ccdc_cfg.dev = &pdev->dev;
- printk(KERN_NOTICE "%s is registered with vpfe.\n", ccdc_hw_dev.name);
- return 0;
-fail_nomem:
- release_mem_region(res->start, resource_size(res));
-fail_nores:
- vpfe_unregister_ccdc_device(&ccdc_hw_dev);
- return status;
-}
-
-static int dm644x_ccdc_remove(struct platform_device *pdev)
-{
- struct resource *res;
-
- iounmap(ccdc_cfg.base_addr);
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- release_mem_region(res->start, resource_size(res));
- vpfe_unregister_ccdc_device(&ccdc_hw_dev);
- return 0;
-}
-
-static int dm644x_ccdc_suspend(struct device *dev)
-{
- /* Save CCDC context */
- ccdc_save_context();
- /* Disable CCDC */
- ccdc_enable(0);
-
- return 0;
-}
-
-static int dm644x_ccdc_resume(struct device *dev)
-{
- /* Restore CCDC context */
- ccdc_restore_context();
-
- return 0;
-}
-
-static const struct dev_pm_ops dm644x_ccdc_pm_ops = {
- .suspend = dm644x_ccdc_suspend,
- .resume = dm644x_ccdc_resume,
-};
-
-static struct platform_driver dm644x_ccdc_driver = {
- .driver = {
- .name = "dm644x_ccdc",
- .pm = &dm644x_ccdc_pm_ops,
- },
- .remove = dm644x_ccdc_remove,
- .probe = dm644x_ccdc_probe,
-};
-
-module_platform_driver(dm644x_ccdc_driver);
diff --git a/drivers/staging/media/deprecated/vpfe_capture/dm644x_ccdc.h b/drivers/staging/media/deprecated/vpfe_capture/dm644x_ccdc.h
deleted file mode 100644
index c20dba3d76d6..000000000000
--- a/drivers/staging/media/deprecated/vpfe_capture/dm644x_ccdc.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright (C) 2006-2009 Texas Instruments Inc
- */
-#ifndef _DM644X_CCDC_H
-#define _DM644X_CCDC_H
-#include <media/davinci/ccdc_types.h>
-#include <media/davinci/vpfe_types.h>
-
-/* enum for No of pixel per line to be avg. in Black Clamping*/
-enum ccdc_sample_length {
- CCDC_SAMPLE_1PIXELS,
- CCDC_SAMPLE_2PIXELS,
- CCDC_SAMPLE_4PIXELS,
- CCDC_SAMPLE_8PIXELS,
- CCDC_SAMPLE_16PIXELS
-};
-
-/* enum for No of lines in Black Clamping */
-enum ccdc_sample_line {
- CCDC_SAMPLE_1LINES,
- CCDC_SAMPLE_2LINES,
- CCDC_SAMPLE_4LINES,
- CCDC_SAMPLE_8LINES,
- CCDC_SAMPLE_16LINES
-};
-
-/* enum for Alaw gamma width */
-enum ccdc_gamma_width {
- CCDC_GAMMA_BITS_15_6, /* use bits 15-6 for gamma */
- CCDC_GAMMA_BITS_14_5,
- CCDC_GAMMA_BITS_13_4,
- CCDC_GAMMA_BITS_12_3,
- CCDC_GAMMA_BITS_11_2,
- CCDC_GAMMA_BITS_10_1,
- CCDC_GAMMA_BITS_09_0 /* use bits 9-0 for gamma */
-};
-
-/* returns the highest bit used for the gamma */
-static inline u8 ccdc_gamma_width_max_bit(enum ccdc_gamma_width width)
-{
- return 15 - width;
-}
-
-enum ccdc_data_size {
- CCDC_DATA_16BITS,
- CCDC_DATA_15BITS,
- CCDC_DATA_14BITS,
- CCDC_DATA_13BITS,
- CCDC_DATA_12BITS,
- CCDC_DATA_11BITS,
- CCDC_DATA_10BITS,
- CCDC_DATA_8BITS
-};
-
-/* returns the highest bit used for this data size */
-static inline u8 ccdc_data_size_max_bit(enum ccdc_data_size sz)
-{
- return sz == CCDC_DATA_8BITS ? 7 : 15 - sz;
-}
-
-/* structure for ALaw */
-struct ccdc_a_law {
- /* Enable/disable A-Law */
- unsigned char enable;
- /* Gamma Width Input */
- enum ccdc_gamma_width gamma_wd;
-};
-
-/* structure for Black Clamping */
-struct ccdc_black_clamp {
- unsigned char enable;
- /* only if bClampEnable is TRUE */
- enum ccdc_sample_length sample_pixel;
- /* only if bClampEnable is TRUE */
- enum ccdc_sample_line sample_ln;
- /* only if bClampEnable is TRUE */
- unsigned short start_pixel;
- /* only if bClampEnable is TRUE */
- unsigned short sgain;
- /* only if bClampEnable is FALSE */
- unsigned short dc_sub;
-};
-
-/* structure for Black Level Compensation */
-struct ccdc_black_compensation {
- /* Constant value to subtract from Red component */
- char r;
- /* Constant value to subtract from Gr component */
- char gr;
- /* Constant value to subtract from Blue component */
- char b;
- /* Constant value to subtract from Gb component */
- char gb;
-};
-
-/* Structure for CCDC configuration parameters for raw capture mode passed
- * by application
- */
-struct ccdc_config_params_raw {
- /* data size value from 8 to 16 bits */
- enum ccdc_data_size data_sz;
- /* Structure for Optional A-Law */
- struct ccdc_a_law alaw;
- /* Structure for Optical Black Clamp */
- struct ccdc_black_clamp blk_clamp;
- /* Structure for Black Compensation */
- struct ccdc_black_compensation blk_comp;
-};
-
-
-#ifdef __KERNEL__
-#include <linux/io.h>
-/* Define to enable/disable video port */
-#define FP_NUM_BYTES 4
-/* Define for extra pixel/line and extra lines/frame */
-#define NUM_EXTRAPIXELS 8
-#define NUM_EXTRALINES 8
-
-/* settings for commonly used video formats */
-#define CCDC_WIN_PAL {0, 0, 720, 576}
-/* ntsc square pixel */
-#define CCDC_WIN_VGA {0, 0, (640 + NUM_EXTRAPIXELS), (480 + NUM_EXTRALINES)}
-
-/* Structure for CCDC configuration parameters for raw capture mode */
-struct ccdc_params_raw {
- /* pixel format */
- enum ccdc_pixfmt pix_fmt;
- /* progressive or interlaced frame */
- enum ccdc_frmfmt frm_fmt;
- /* video window */
- struct v4l2_rect win;
- /* field id polarity */
- enum vpfe_pin_pol fid_pol;
- /* vertical sync polarity */
- enum vpfe_pin_pol vd_pol;
- /* horizontal sync polarity */
- enum vpfe_pin_pol hd_pol;
- /* interleaved or separated fields */
- enum ccdc_buftype buf_type;
- /*
- * enable to store the image in inverse
- * order in memory(bottom to top)
- */
- unsigned char image_invert_enable;
- /* configurable parameters */
- struct ccdc_config_params_raw config_params;
-};
-
-struct ccdc_params_ycbcr {
- /* pixel format */
- enum ccdc_pixfmt pix_fmt;
- /* progressive or interlaced frame */
- enum ccdc_frmfmt frm_fmt;
- /* video window */
- struct v4l2_rect win;
- /* field id polarity */
- enum vpfe_pin_pol fid_pol;
- /* vertical sync polarity */
- enum vpfe_pin_pol vd_pol;
- /* horizontal sync polarity */
- enum vpfe_pin_pol hd_pol;
- /* enable BT.656 embedded sync mode */
- int bt656_enable;
- /* cb:y:cr:y or y:cb:y:cr in memory */
- enum ccdc_pixorder pix_order;
- /* interleaved or separated fields */
- enum ccdc_buftype buf_type;
-};
-#endif
-#endif /* _DM644X_CCDC_H */
diff --git a/drivers/staging/media/deprecated/vpfe_capture/dm644x_ccdc_regs.h b/drivers/staging/media/deprecated/vpfe_capture/dm644x_ccdc_regs.h
deleted file mode 100644
index c4894f6a254e..000000000000
--- a/drivers/staging/media/deprecated/vpfe_capture/dm644x_ccdc_regs.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright (C) 2006-2009 Texas Instruments Inc
- */
-#ifndef _DM644X_CCDC_REGS_H
-#define _DM644X_CCDC_REGS_H
-
-/**************************************************************************\
-* Register OFFSET Definitions
-\**************************************************************************/
-#define CCDC_PID 0x0
-#define CCDC_PCR 0x4
-#define CCDC_SYN_MODE 0x8
-#define CCDC_HD_VD_WID 0xc
-#define CCDC_PIX_LINES 0x10
-#define CCDC_HORZ_INFO 0x14
-#define CCDC_VERT_START 0x18
-#define CCDC_VERT_LINES 0x1c
-#define CCDC_CULLING 0x20
-#define CCDC_HSIZE_OFF 0x24
-#define CCDC_SDOFST 0x28
-#define CCDC_SDR_ADDR 0x2c
-#define CCDC_CLAMP 0x30
-#define CCDC_DCSUB 0x34
-#define CCDC_COLPTN 0x38
-#define CCDC_BLKCMP 0x3c
-#define CCDC_FPC 0x40
-#define CCDC_FPC_ADDR 0x44
-#define CCDC_VDINT 0x48
-#define CCDC_ALAW 0x4c
-#define CCDC_REC656IF 0x50
-#define CCDC_CCDCFG 0x54
-#define CCDC_FMTCFG 0x58
-#define CCDC_FMT_HORZ 0x5c
-#define CCDC_FMT_VERT 0x60
-#define CCDC_FMT_ADDR0 0x64
-#define CCDC_FMT_ADDR1 0x68
-#define CCDC_FMT_ADDR2 0x6c
-#define CCDC_FMT_ADDR3 0x70
-#define CCDC_FMT_ADDR4 0x74
-#define CCDC_FMT_ADDR5 0x78
-#define CCDC_FMT_ADDR6 0x7c
-#define CCDC_FMT_ADDR7 0x80
-#define CCDC_PRGEVEN_0 0x84
-#define CCDC_PRGEVEN_1 0x88
-#define CCDC_PRGODD_0 0x8c
-#define CCDC_PRGODD_1 0x90
-#define CCDC_VP_OUT 0x94
-#define CCDC_REG_END 0x98
-
-/***************************************************************
-* Define for various register bit mask and shifts for CCDC
-****************************************************************/
-#define CCDC_FID_POL_MASK 1
-#define CCDC_FID_POL_SHIFT 4
-#define CCDC_HD_POL_MASK 1
-#define CCDC_HD_POL_SHIFT 3
-#define CCDC_VD_POL_MASK 1
-#define CCDC_VD_POL_SHIFT 2
-#define CCDC_HSIZE_OFF_MASK 0xffffffe0
-#define CCDC_32BYTE_ALIGN_VAL 31
-#define CCDC_FRM_FMT_MASK 0x1
-#define CCDC_FRM_FMT_SHIFT 7
-#define CCDC_DATA_SZ_MASK 7
-#define CCDC_DATA_SZ_SHIFT 8
-#define CCDC_PIX_FMT_MASK 3
-#define CCDC_PIX_FMT_SHIFT 12
-#define CCDC_VP2SDR_DISABLE 0xFFFBFFFF
-#define CCDC_WEN_ENABLE BIT(17)
-#define CCDC_SDR2RSZ_DISABLE 0xFFF7FFFF
-#define CCDC_VDHDEN_ENABLE BIT(16)
-#define CCDC_LPF_ENABLE BIT(14)
-#define CCDC_ALAW_ENABLE BIT(3)
-#define CCDC_ALAW_GAMMA_WD_MASK 7
-#define CCDC_BLK_CLAMP_ENABLE BIT(31)
-#define CCDC_BLK_SGAIN_MASK 0x1F
-#define CCDC_BLK_ST_PXL_MASK 0x7FFF
-#define CCDC_BLK_ST_PXL_SHIFT 10
-#define CCDC_BLK_SAMPLE_LN_MASK 7
-#define CCDC_BLK_SAMPLE_LN_SHIFT 28
-#define CCDC_BLK_SAMPLE_LINE_MASK 7
-#define CCDC_BLK_SAMPLE_LINE_SHIFT 25
-#define CCDC_BLK_DC_SUB_MASK 0x03FFF
-#define CCDC_BLK_COMP_MASK 0xFF
-#define CCDC_BLK_COMP_GB_COMP_SHIFT 8
-#define CCDC_BLK_COMP_GR_COMP_SHIFT 16
-#define CCDC_BLK_COMP_R_COMP_SHIFT 24
-#define CCDC_LATCH_ON_VSYNC_DISABLE BIT(15)
-#define CCDC_FPC_ENABLE BIT(15)
-#define CCDC_FPC_DISABLE 0
-#define CCDC_FPC_FPC_NUM_MASK 0x7FFF
-#define CCDC_DATA_PACK_ENABLE BIT(11)
-#define CCDC_FMTCFG_VPIN_MASK 7
-#define CCDC_FMTCFG_VPIN_SHIFT 12
-#define CCDC_FMT_HORZ_FMTLNH_MASK 0x1FFF
-#define CCDC_FMT_HORZ_FMTSPH_MASK 0x1FFF
-#define CCDC_FMT_HORZ_FMTSPH_SHIFT 16
-#define CCDC_FMT_VERT_FMTLNV_MASK 0x1FFF
-#define CCDC_FMT_VERT_FMTSLV_MASK 0x1FFF
-#define CCDC_FMT_VERT_FMTSLV_SHIFT 16
-#define CCDC_VP_OUT_VERT_NUM_MASK 0x3FFF
-#define CCDC_VP_OUT_VERT_NUM_SHIFT 17
-#define CCDC_VP_OUT_HORZ_NUM_MASK 0x1FFF
-#define CCDC_VP_OUT_HORZ_NUM_SHIFT 4
-#define CCDC_VP_OUT_HORZ_ST_MASK 0xF
-#define CCDC_HORZ_INFO_SPH_SHIFT 16
-#define CCDC_VERT_START_SLV0_SHIFT 16
-#define CCDC_VDINT_VDINT0_SHIFT 16
-#define CCDC_VDINT_VDINT1_MASK 0xFFFF
-#define CCDC_PPC_RAW 1
-#define CCDC_DCSUB_DEFAULT_VAL 0
-#define CCDC_CLAMP_DEFAULT_VAL 0
-#define CCDC_ENABLE_VIDEO_PORT 0x8000
-#define CCDC_DISABLE_VIDEO_PORT 0
-#define CCDC_COLPTN_VAL 0xBB11BB11
-#define CCDC_TWO_BYTES_PER_PIXEL 2
-#define CCDC_INTERLACED_IMAGE_INVERT 0x4B6D
-#define CCDC_INTERLACED_NO_IMAGE_INVERT 0x0249
-#define CCDC_PROGRESSIVE_IMAGE_INVERT 0x4000
-#define CCDC_PROGRESSIVE_NO_IMAGE_INVERT 0
-#define CCDC_INTERLACED_HEIGHT_SHIFT 1
-#define CCDC_SYN_MODE_INPMOD_SHIFT 12
-#define CCDC_SYN_MODE_INPMOD_MASK 3
-#define CCDC_SYN_MODE_8BITS (7 << 8)
-#define CCDC_SYN_MODE_10BITS (6 << 8)
-#define CCDC_SYN_MODE_11BITS (5 << 8)
-#define CCDC_SYN_MODE_12BITS (4 << 8)
-#define CCDC_SYN_MODE_13BITS (3 << 8)
-#define CCDC_SYN_MODE_14BITS (2 << 8)
-#define CCDC_SYN_MODE_15BITS (1 << 8)
-#define CCDC_SYN_MODE_16BITS (0 << 8)
-#define CCDC_SYN_FLDMODE_MASK 1
-#define CCDC_SYN_FLDMODE_SHIFT 7
-#define CCDC_REC656IF_BT656_EN 3
-#define CCDC_SYN_MODE_VD_POL_NEGATIVE BIT(2)
-#define CCDC_CCDCFG_Y8POS_SHIFT 11
-#define CCDC_CCDCFG_BW656_10BIT BIT(5)
-#define CCDC_SDOFST_FIELD_INTERLEAVED 0x249
-#define CCDC_NO_CULLING 0xffff00ff
-#endif
diff --git a/drivers/staging/media/deprecated/vpfe_capture/isif.c b/drivers/staging/media/deprecated/vpfe_capture/isif.c
deleted file mode 100644
index 4059891c2824..000000000000
--- a/drivers/staging/media/deprecated/vpfe_capture/isif.c
+++ /dev/null
@@ -1,1127 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright (C) 2008-2009 Texas Instruments Inc
- *
- * Image Sensor Interface (ISIF) driver
- *
- * This driver is for configuring the ISIF IP available on DM365 or any other
- * TI SoCs. This is used for capturing yuv or bayer video or image data
- * from a decoder or sensor. This IP is similar to the CCDC IP on DM355
- * and DM6446, but with enhanced or additional ip blocks. The driver
- * configures the ISIF upon commands from the vpfe bridge driver through
- * ccdc_hw_device interface.
- *
- * TODO: 1) Raw bayer parameter settings and bayer capture
- * 2) Add support for control ioctl
- */
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/uaccess.h>
-#include <linux/io.h>
-#include <linux/videodev2.h>
-#include <linux/err.h>
-#include <linux/module.h>
-
-#include "isif.h"
-#include <media/davinci/vpss.h>
-
-#include "isif_regs.h"
-#include "ccdc_hw_device.h"
-
-/* Defaults for module configuration parameters */
-static const struct isif_config_params_raw isif_config_defaults = {
- .linearize = {
- .en = 0,
- .corr_shft = ISIF_NO_SHIFT,
- .scale_fact = {1, 0},
- },
- .df_csc = {
- .df_or_csc = 0,
- .csc = {
- .en = 0,
- },
- },
- .dfc = {
- .en = 0,
- },
- .bclamp = {
- .en = 0,
- },
- .gain_offset = {
- .gain = {
- .r_ye = {1, 0},
- .gr_cy = {1, 0},
- .gb_g = {1, 0},
- .b_mg = {1, 0},
- },
- },
- .culling = {
- .hcpat_odd = 0xff,
- .hcpat_even = 0xff,
- .vcpat = 0xff,
- },
- .compress = {
- .alg = ISIF_ALAW,
- },
-};
-
-/* ISIF operation configuration */
-static struct isif_oper_config {
- struct device *dev;
- enum vpfe_hw_if_type if_type;
- struct isif_ycbcr_config ycbcr;
- struct isif_params_raw bayer;
- enum isif_data_pack data_pack;
- /* ISIF base address */
- void __iomem *base_addr;
- /* ISIF Linear Table 0 */
- void __iomem *linear_tbl0_addr;
- /* ISIF Linear Table 1 */
- void __iomem *linear_tbl1_addr;
-} isif_cfg = {
- .ycbcr = {
- .pix_fmt = CCDC_PIXFMT_YCBCR_8BIT,
- .frm_fmt = CCDC_FRMFMT_INTERLACED,
- .win = ISIF_WIN_NTSC,
- .fid_pol = VPFE_PINPOL_POSITIVE,
- .vd_pol = VPFE_PINPOL_POSITIVE,
- .hd_pol = VPFE_PINPOL_POSITIVE,
- .pix_order = CCDC_PIXORDER_CBYCRY,
- .buf_type = CCDC_BUFTYPE_FLD_INTERLEAVED,
- },
- .bayer = {
- .pix_fmt = CCDC_PIXFMT_RAW,
- .frm_fmt = CCDC_FRMFMT_PROGRESSIVE,
- .win = ISIF_WIN_VGA,
- .fid_pol = VPFE_PINPOL_POSITIVE,
- .vd_pol = VPFE_PINPOL_POSITIVE,
- .hd_pol = VPFE_PINPOL_POSITIVE,
- .gain = {
- .r_ye = {1, 0},
- .gr_cy = {1, 0},
- .gb_g = {1, 0},
- .b_mg = {1, 0},
- },
- .cfa_pat = ISIF_CFA_PAT_MOSAIC,
- .data_msb = ISIF_BIT_MSB_11,
- .config_params = {
- .data_shift = ISIF_NO_SHIFT,
- .col_pat_field0 = {
- .olop = ISIF_GREEN_BLUE,
- .olep = ISIF_BLUE,
- .elop = ISIF_RED,
- .elep = ISIF_GREEN_RED,
- },
- .col_pat_field1 = {
- .olop = ISIF_GREEN_BLUE,
- .olep = ISIF_BLUE,
- .elop = ISIF_RED,
- .elep = ISIF_GREEN_RED,
- },
- .test_pat_gen = 0,
- },
- },
- .data_pack = ISIF_DATA_PACK8,
-};
-
-/* Raw Bayer formats */
-static const u32 isif_raw_bayer_pix_formats[] = {
- V4L2_PIX_FMT_SBGGR8, V4L2_PIX_FMT_SBGGR16};
-
-/* Raw YUV formats */
-static const u32 isif_raw_yuv_pix_formats[] = {
- V4L2_PIX_FMT_UYVY, V4L2_PIX_FMT_YUYV};
-
-/* register access routines */
-static inline u32 regr(u32 offset)
-{
- return __raw_readl(isif_cfg.base_addr + offset);
-}
-
-static inline void regw(u32 val, u32 offset)
-{
- __raw_writel(val, isif_cfg.base_addr + offset);
-}
-
-/* reg_modify() - read, modify and write register */
-static inline u32 reg_modify(u32 mask, u32 val, u32 offset)
-{
- u32 new_val = (regr(offset) & ~mask) | (val & mask);
-
- regw(new_val, offset);
- return new_val;
-}
-
-static inline void regw_lin_tbl(u32 val, u32 offset, int i)
-{
- if (!i)
- __raw_writel(val, isif_cfg.linear_tbl0_addr + offset);
- else
- __raw_writel(val, isif_cfg.linear_tbl1_addr + offset);
-}
-
-static void isif_disable_all_modules(void)
-{
- /* disable BC */
- regw(0, CLAMPCFG);
- /* disable vdfc */
- regw(0, DFCCTL);
- /* disable CSC */
- regw(0, CSCCTL);
- /* disable linearization */
- regw(0, LINCFG0);
- /* disable other modules here as they are supported */
-}
-
-static void isif_enable(int en)
-{
- if (!en) {
- /* Before disable isif, disable all ISIF modules */
- isif_disable_all_modules();
- /*
- * wait for next VD. Assume lowest scan rate is 12 Hz. So
- * 100 msec delay is good enough
- */
- msleep(100);
- }
- reg_modify(ISIF_SYNCEN_VDHDEN_MASK, en, SYNCEN);
-}
-
-static void isif_enable_output_to_sdram(int en)
-{
- reg_modify(ISIF_SYNCEN_WEN_MASK, en << ISIF_SYNCEN_WEN_SHIFT, SYNCEN);
-}
-
-static void isif_config_culling(struct isif_cul *cul)
-{
- u32 val;
-
- /* Horizontal pattern */
- val = (cul->hcpat_even << CULL_PAT_EVEN_LINE_SHIFT) | cul->hcpat_odd;
- regw(val, CULH);
-
- /* vertical pattern */
- regw(cul->vcpat, CULV);
-
- /* LPF */
- reg_modify(ISIF_LPF_MASK << ISIF_LPF_SHIFT,
- cul->en_lpf << ISIF_LPF_SHIFT, MODESET);
-}
-
-static void isif_config_gain_offset(void)
-{
- struct isif_gain_offsets_adj *gain_off_p =
- &isif_cfg.bayer.config_params.gain_offset;
- u32 val;
-
- val = (!!gain_off_p->gain_sdram_en << GAIN_SDRAM_EN_SHIFT) |
- (!!gain_off_p->gain_ipipe_en << GAIN_IPIPE_EN_SHIFT) |
- (!!gain_off_p->gain_h3a_en << GAIN_H3A_EN_SHIFT) |
- (!!gain_off_p->offset_sdram_en << OFST_SDRAM_EN_SHIFT) |
- (!!gain_off_p->offset_ipipe_en << OFST_IPIPE_EN_SHIFT) |
- (!!gain_off_p->offset_h3a_en << OFST_H3A_EN_SHIFT);
-
- reg_modify(GAIN_OFFSET_EN_MASK, val, CGAMMAWD);
-
- val = (gain_off_p->gain.r_ye.integer << GAIN_INTEGER_SHIFT) |
- gain_off_p->gain.r_ye.decimal;
- regw(val, CRGAIN);
-
- val = (gain_off_p->gain.gr_cy.integer << GAIN_INTEGER_SHIFT) |
- gain_off_p->gain.gr_cy.decimal;
- regw(val, CGRGAIN);
-
- val = (gain_off_p->gain.gb_g.integer << GAIN_INTEGER_SHIFT) |
- gain_off_p->gain.gb_g.decimal;
- regw(val, CGBGAIN);
-
- val = (gain_off_p->gain.b_mg.integer << GAIN_INTEGER_SHIFT) |
- gain_off_p->gain.b_mg.decimal;
- regw(val, CBGAIN);
-
- regw(gain_off_p->offset, COFSTA);
-}
-
-static void isif_restore_defaults(void)
-{
- enum vpss_ccdc_source_sel source = VPSS_CCDCIN;
-
- dev_dbg(isif_cfg.dev, "\nstarting isif_restore_defaults...");
- isif_cfg.bayer.config_params = isif_config_defaults;
- /* Enable clock to ISIF, IPIPEIF and BL */
- vpss_enable_clock(VPSS_CCDC_CLOCK, 1);
- vpss_enable_clock(VPSS_IPIPEIF_CLOCK, 1);
- vpss_enable_clock(VPSS_BL_CLOCK, 1);
- /* Set default offset and gain */
- isif_config_gain_offset();
- vpss_select_ccdc_source(source);
- dev_dbg(isif_cfg.dev, "\nEnd of isif_restore_defaults...");
-}
-
-static int isif_open(struct device *device)
-{
- isif_restore_defaults();
- return 0;
-}
-
-/* This function will configure the window size to be capture in ISIF reg */
-static void isif_setwin(struct v4l2_rect *image_win,
- enum ccdc_frmfmt frm_fmt, int ppc)
-{
- int horz_start, horz_nr_pixels;
- int vert_start, vert_nr_lines;
- int mid_img = 0;
-
- dev_dbg(isif_cfg.dev, "\nStarting isif_setwin...");
- /*
- * ppc - per pixel count. indicates how many pixels per cell
- * output to SDRAM. example, for ycbcr, it is one y and one c, so 2.
- * raw capture this is 1
- */
- horz_start = image_win->left << (ppc - 1);
- horz_nr_pixels = ((image_win->width) << (ppc - 1)) - 1;
-
- /* Writing the horizontal info into the registers */
- regw(horz_start & START_PX_HOR_MASK, SPH);
- regw(horz_nr_pixels & NUM_PX_HOR_MASK, LNH);
- vert_start = image_win->top;
-
- if (frm_fmt == CCDC_FRMFMT_INTERLACED) {
- vert_nr_lines = (image_win->height >> 1) - 1;
- vert_start >>= 1;
- /* To account for VD since line 0 doesn't have any data */
- vert_start += 1;
- } else {
- /* To account for VD since line 0 doesn't have any data */
- vert_start += 1;
- vert_nr_lines = image_win->height - 1;
- /* configure VDINT0 and VDINT1 */
- mid_img = vert_start + (image_win->height / 2);
- regw(mid_img, VDINT1);
- }
-
- regw(0, VDINT0);
- regw(vert_start & START_VER_ONE_MASK, SLV0);
- regw(vert_start & START_VER_TWO_MASK, SLV1);
- regw(vert_nr_lines & NUM_LINES_VER, LNV);
-}
-
-static void isif_config_bclamp(struct isif_black_clamp *bc)
-{
- u32 val;
-
- /*
- * DC Offset is always added to image data irrespective of bc enable
- * status
- */
- regw(bc->dc_offset, CLDCOFST);
-
- if (bc->en) {
- val = bc->bc_mode_color << ISIF_BC_MODE_COLOR_SHIFT;
-
- /* Enable BC and horizontal clamp calculation parameters */
- val = val | 1 | (bc->horz.mode << ISIF_HORZ_BC_MODE_SHIFT);
-
- regw(val, CLAMPCFG);
-
- if (bc->horz.mode != ISIF_HORZ_BC_DISABLE) {
- /*
- * Window count for calculation
- * Base window selection
- * pixel limit
- * Horizontal size of window
- * vertical size of the window
- * Horizontal start position of the window
- * Vertical start position of the window
- */
- val = bc->horz.win_count_calc |
- ((!!bc->horz.base_win_sel_calc) <<
- ISIF_HORZ_BC_WIN_SEL_SHIFT) |
- ((!!bc->horz.clamp_pix_limit) <<
- ISIF_HORZ_BC_PIX_LIMIT_SHIFT) |
- (bc->horz.win_h_sz_calc <<
- ISIF_HORZ_BC_WIN_H_SIZE_SHIFT) |
- (bc->horz.win_v_sz_calc <<
- ISIF_HORZ_BC_WIN_V_SIZE_SHIFT);
- regw(val, CLHWIN0);
-
- regw(bc->horz.win_start_h_calc, CLHWIN1);
- regw(bc->horz.win_start_v_calc, CLHWIN2);
- }
-
- /* vertical clamp calculation parameters */
-
- /* Reset clamp value sel for previous line */
- val |=
- (bc->vert.reset_val_sel << ISIF_VERT_BC_RST_VAL_SEL_SHIFT) |
- (bc->vert.line_ave_coef << ISIF_VERT_BC_LINE_AVE_COEF_SHIFT);
- regw(val, CLVWIN0);
-
- /* Optical Black horizontal start position */
- regw(bc->vert.ob_start_h, CLVWIN1);
- /* Optical Black vertical start position */
- regw(bc->vert.ob_start_v, CLVWIN2);
- /* Optical Black vertical size for calculation */
- regw(bc->vert.ob_v_sz_calc, CLVWIN3);
- /* Vertical start position for BC subtraction */
- regw(bc->vert_start_sub, CLSV);
- }
-}
-
-static void isif_config_linearization(struct isif_linearize *linearize)
-{
- u32 val, i;
-
- if (!linearize->en) {
- regw(0, LINCFG0);
- return;
- }
-
- /* shift value for correction & enable linearization (set lsb) */
- val = (linearize->corr_shft << ISIF_LIN_CORRSFT_SHIFT) | 1;
- regw(val, LINCFG0);
-
- /* Scale factor */
- val = ((!!linearize->scale_fact.integer) <<
- ISIF_LIN_SCALE_FACT_INTEG_SHIFT) |
- linearize->scale_fact.decimal;
- regw(val, LINCFG1);
-
- for (i = 0; i < ISIF_LINEAR_TAB_SIZE; i++) {
- if (i % 2)
- regw_lin_tbl(linearize->table[i], ((i >> 1) << 2), 1);
- else
- regw_lin_tbl(linearize->table[i], ((i >> 1) << 2), 0);
- }
-}
-
-static int isif_config_dfc(struct isif_dfc *vdfc)
-{
- /* initialize retries to loop for max ~ 250 usec */
- u32 val, count, retries = loops_per_jiffy / (4000/HZ);
- int i;
-
- if (!vdfc->en)
- return 0;
-
- /* Correction mode */
- val = (vdfc->corr_mode << ISIF_VDFC_CORR_MOD_SHIFT);
-
- /* Correct whole line or partial */
- if (vdfc->corr_whole_line)
- val |= 1 << ISIF_VDFC_CORR_WHOLE_LN_SHIFT;
-
- /* level shift value */
- val |= vdfc->def_level_shift << ISIF_VDFC_LEVEL_SHFT_SHIFT;
-
- regw(val, DFCCTL);
-
- /* Defect saturation level */
- regw(vdfc->def_sat_level, VDFSATLV);
-
- regw(vdfc->table[0].pos_vert, DFCMEM0);
- regw(vdfc->table[0].pos_horz, DFCMEM1);
- if (vdfc->corr_mode == ISIF_VDFC_NORMAL ||
- vdfc->corr_mode == ISIF_VDFC_HORZ_INTERPOL_IF_SAT) {
- regw(vdfc->table[0].level_at_pos, DFCMEM2);
- regw(vdfc->table[0].level_up_pixels, DFCMEM3);
- regw(vdfc->table[0].level_low_pixels, DFCMEM4);
- }
-
- /* set DFCMARST and set DFCMWR */
- val = regr(DFCMEMCTL) | (1 << ISIF_DFCMEMCTL_DFCMARST_SHIFT) | 1;
- regw(val, DFCMEMCTL);
-
- count = retries;
- while (count && (regr(DFCMEMCTL) & 0x1))
- count--;
-
- if (!count) {
- dev_dbg(isif_cfg.dev, "defect table write timeout !!!\n");
- return -1;
- }
-
- for (i = 1; i < vdfc->num_vdefects; i++) {
- regw(vdfc->table[i].pos_vert, DFCMEM0);
- regw(vdfc->table[i].pos_horz, DFCMEM1);
- if (vdfc->corr_mode == ISIF_VDFC_NORMAL ||
- vdfc->corr_mode == ISIF_VDFC_HORZ_INTERPOL_IF_SAT) {
- regw(vdfc->table[i].level_at_pos, DFCMEM2);
- regw(vdfc->table[i].level_up_pixels, DFCMEM3);
- regw(vdfc->table[i].level_low_pixels, DFCMEM4);
- }
- val = regr(DFCMEMCTL);
- /* clear DFCMARST and set DFCMWR */
- val &= ~BIT(ISIF_DFCMEMCTL_DFCMARST_SHIFT);
- val |= 1;
- regw(val, DFCMEMCTL);
-
- count = retries;
- while (count && (regr(DFCMEMCTL) & 0x1))
- count--;
-
- if (!count) {
- dev_err(isif_cfg.dev,
- "defect table write timeout !!!\n");
- return -1;
- }
- }
- if (vdfc->num_vdefects < ISIF_VDFC_TABLE_SIZE) {
- /* Extra cycle needed */
- regw(0, DFCMEM0);
- regw(0x1FFF, DFCMEM1);
- regw(1, DFCMEMCTL);
- }
-
- /* enable VDFC */
- reg_modify((1 << ISIF_VDFC_EN_SHIFT), (1 << ISIF_VDFC_EN_SHIFT),
- DFCCTL);
- return 0;
-}
-
-static void isif_config_csc(struct isif_df_csc *df_csc)
-{
- u32 val1 = 0, val2 = 0, i;
-
- if (!df_csc->csc.en) {
- regw(0, CSCCTL);
- return;
- }
- for (i = 0; i < ISIF_CSC_NUM_COEFF; i++) {
- if ((i % 2) == 0) {
- /* CSCM - LSB */
- val1 = (df_csc->csc.coeff[i].integer <<
- ISIF_CSC_COEF_INTEG_SHIFT) |
- df_csc->csc.coeff[i].decimal;
- } else {
-
- /* CSCM - MSB */
- val2 = (df_csc->csc.coeff[i].integer <<
- ISIF_CSC_COEF_INTEG_SHIFT) |
- df_csc->csc.coeff[i].decimal;
- val2 <<= ISIF_CSCM_MSB_SHIFT;
- val2 |= val1;
- regw(val2, (CSCM0 + ((i - 1) << 1)));
- }
- }
-
- /* program the active area */
- regw(df_csc->start_pix, FMTSPH);
- /*
- * one extra pixel as required for CSC. Actually number of
- * pixel - 1 should be configured in this register. So we
- * need to subtract 1 before writing to FMTSPH, but we will
- * not do this since csc requires one extra pixel
- */
- regw(df_csc->num_pixels, FMTLNH);
- regw(df_csc->start_line, FMTSLV);
- /*
- * one extra line as required for CSC. See reason documented for
- * num_pixels
- */
- regw(df_csc->num_lines, FMTLNV);
-
- /* Enable CSC */
- regw(1, CSCCTL);
-}
-
-static int isif_config_raw(void)
-{
- struct isif_params_raw *params = &isif_cfg.bayer;
- struct isif_config_params_raw *module_params =
- &isif_cfg.bayer.config_params;
- struct vpss_pg_frame_size frame_size;
- struct vpss_sync_pol sync;
- u32 val;
-
- dev_dbg(isif_cfg.dev, "\nStarting isif_config_raw..\n");
-
- /*
- * Configure CCDCFG register:-
- * Set CCD Not to swap input since input is RAW data
- * Set FID detection function to Latch at V-Sync
- * Set WENLOG - isif valid area
- * Set TRGSEL
- * Set EXTRG
- * Packed to 8 or 16 bits
- */
-
- val = ISIF_YCINSWP_RAW | ISIF_CCDCFG_FIDMD_LATCH_VSYNC |
- ISIF_CCDCFG_WENLOG_AND | ISIF_CCDCFG_TRGSEL_WEN |
- ISIF_CCDCFG_EXTRG_DISABLE | isif_cfg.data_pack;
-
- dev_dbg(isif_cfg.dev, "Writing 0x%x to ...CCDCFG \n", val);
- regw(val, CCDCFG);
-
- /*
- * Configure the vertical sync polarity(MODESET.VDPOL)
- * Configure the horizontal sync polarity (MODESET.HDPOL)
- * Configure frame id polarity (MODESET.FLDPOL)
- * Configure data polarity
- * Configure External WEN Selection
- * Configure frame format(progressive or interlace)
- * Configure pixel format (Input mode)
- * Configure the data shift
- */
-
- val = ISIF_VDHDOUT_INPUT | (params->vd_pol << ISIF_VD_POL_SHIFT) |
- (params->hd_pol << ISIF_HD_POL_SHIFT) |
- (params->fid_pol << ISIF_FID_POL_SHIFT) |
- (ISIF_DATAPOL_NORMAL << ISIF_DATAPOL_SHIFT) |
- (ISIF_EXWEN_DISABLE << ISIF_EXWEN_SHIFT) |
- (params->frm_fmt << ISIF_FRM_FMT_SHIFT) |
- (params->pix_fmt << ISIF_INPUT_SHIFT) |
- (params->config_params.data_shift << ISIF_DATASFT_SHIFT);
-
- regw(val, MODESET);
- dev_dbg(isif_cfg.dev, "Writing 0x%x to MODESET...\n", val);
-
- /*
- * Configure GAMMAWD register
- * CFA pattern setting
- */
- val = params->cfa_pat << ISIF_GAMMAWD_CFA_SHIFT;
-
- /* Gamma msb */
- if (module_params->compress.alg == ISIF_ALAW)
- val |= ISIF_ALAW_ENABLE;
-
- val |= (params->data_msb << ISIF_ALAW_GAMMA_WD_SHIFT);
- regw(val, CGAMMAWD);
-
- /* Configure DPCM compression settings */
- if (module_params->compress.alg == ISIF_DPCM) {
- val = BIT(ISIF_DPCM_EN_SHIFT) |
- (module_params->compress.pred <<
- ISIF_DPCM_PREDICTOR_SHIFT);
- }
-
- regw(val, MISC);
-
- /* Configure Gain & Offset */
- isif_config_gain_offset();
-
- /* Configure Color pattern */
- val = (params->config_params.col_pat_field0.olop) |
- (params->config_params.col_pat_field0.olep << 2) |
- (params->config_params.col_pat_field0.elop << 4) |
- (params->config_params.col_pat_field0.elep << 6) |
- (params->config_params.col_pat_field1.olop << 8) |
- (params->config_params.col_pat_field1.olep << 10) |
- (params->config_params.col_pat_field1.elop << 12) |
- (params->config_params.col_pat_field1.elep << 14);
- regw(val, CCOLP);
- dev_dbg(isif_cfg.dev, "Writing %x to CCOLP ...\n", val);
-
- /* Configure HSIZE register */
- val = (!!params->horz_flip_en) << ISIF_HSIZE_FLIP_SHIFT;
-
- /* calculate line offset in 32 bytes based on pack value */
- if (isif_cfg.data_pack == ISIF_PACK_8BIT)
- val |= ((params->win.width + 31) >> 5);
- else if (isif_cfg.data_pack == ISIF_PACK_12BIT)
- val |= (((params->win.width +
- (params->win.width >> 2)) + 31) >> 5);
- else
- val |= (((params->win.width * 2) + 31) >> 5);
- regw(val, HSIZE);
-
- /* Configure SDOFST register */
- if (params->frm_fmt == CCDC_FRMFMT_INTERLACED) {
- if (params->image_invert_en) {
- /* For interlace inverse mode */
- regw(0x4B6D, SDOFST);
- dev_dbg(isif_cfg.dev, "Writing 0x4B6D to SDOFST...\n");
- } else {
- /* For interlace non inverse mode */
- regw(0x0B6D, SDOFST);
- dev_dbg(isif_cfg.dev, "Writing 0x0B6D to SDOFST...\n");
- }
- } else if (params->frm_fmt == CCDC_FRMFMT_PROGRESSIVE) {
- if (params->image_invert_en) {
- /* For progressive inverse mode */
- regw(0x4000, SDOFST);
- dev_dbg(isif_cfg.dev, "Writing 0x4000 to SDOFST...\n");
- } else {
- /* For progressive non inverse mode */
- regw(0x0000, SDOFST);
- dev_dbg(isif_cfg.dev, "Writing 0x0000 to SDOFST...\n");
- }
- }
-
- /* Configure video window */
- isif_setwin(¶ms->win, params->frm_fmt, 1);
-
- /* Configure Black Clamp */
- isif_config_bclamp(&module_params->bclamp);
-
- /* Configure Vertical Defection Pixel Correction */
- if (isif_config_dfc(&module_params->dfc) < 0)
- return -EFAULT;
-
- if (!module_params->df_csc.df_or_csc)
- /* Configure Color Space Conversion */
- isif_config_csc(&module_params->df_csc);
-
- isif_config_linearization(&module_params->linearize);
-
- /* Configure Culling */
- isif_config_culling(&module_params->culling);
-
- /* Configure horizontal and vertical offsets(DFC,LSC,Gain) */
- regw(module_params->horz_offset, DATAHOFST);
- regw(module_params->vert_offset, DATAVOFST);
-
- /* Setup test pattern if enabled */
- if (params->config_params.test_pat_gen) {
- /* Use the HD/VD pol settings from user */
- sync.ccdpg_hdpol = params->hd_pol;
- sync.ccdpg_vdpol = params->vd_pol;
- dm365_vpss_set_sync_pol(sync);
- frame_size.hlpfr = isif_cfg.bayer.win.width;
- frame_size.pplen = isif_cfg.bayer.win.height;
- dm365_vpss_set_pg_frame_size(frame_size);
- vpss_select_ccdc_source(VPSS_PGLPBK);
- }
-
- dev_dbg(isif_cfg.dev, "\nEnd of isif_config_ycbcr...\n");
- return 0;
-}
-
-static int isif_set_buftype(enum ccdc_buftype buf_type)
-{
- if (isif_cfg.if_type == VPFE_RAW_BAYER)
- isif_cfg.bayer.buf_type = buf_type;
- else
- isif_cfg.ycbcr.buf_type = buf_type;
-
- return 0;
-
-}
-static enum ccdc_buftype isif_get_buftype(void)
-{
- if (isif_cfg.if_type == VPFE_RAW_BAYER)
- return isif_cfg.bayer.buf_type;
-
- return isif_cfg.ycbcr.buf_type;
-}
-
-static int isif_enum_pix(u32 *pix, int i)
-{
- int ret = -EINVAL;
-
- if (isif_cfg.if_type == VPFE_RAW_BAYER) {
- if (i < ARRAY_SIZE(isif_raw_bayer_pix_formats)) {
- *pix = isif_raw_bayer_pix_formats[i];
- ret = 0;
- }
- } else {
- if (i < ARRAY_SIZE(isif_raw_yuv_pix_formats)) {
- *pix = isif_raw_yuv_pix_formats[i];
- ret = 0;
- }
- }
-
- return ret;
-}
-
-static int isif_set_pixel_format(unsigned int pixfmt)
-{
- if (isif_cfg.if_type == VPFE_RAW_BAYER) {
- if (pixfmt == V4L2_PIX_FMT_SBGGR8) {
- if ((isif_cfg.bayer.config_params.compress.alg !=
- ISIF_ALAW) &&
- (isif_cfg.bayer.config_params.compress.alg !=
- ISIF_DPCM)) {
- dev_dbg(isif_cfg.dev,
- "Either configure A-Law or DPCM\n");
- return -EINVAL;
- }
- isif_cfg.data_pack = ISIF_PACK_8BIT;
- } else if (pixfmt == V4L2_PIX_FMT_SBGGR16) {
- isif_cfg.bayer.config_params.compress.alg =
- ISIF_NO_COMPRESSION;
- isif_cfg.data_pack = ISIF_PACK_16BIT;
- } else
- return -EINVAL;
- isif_cfg.bayer.pix_fmt = CCDC_PIXFMT_RAW;
- } else {
- if (pixfmt == V4L2_PIX_FMT_YUYV)
- isif_cfg.ycbcr.pix_order = CCDC_PIXORDER_YCBYCR;
- else if (pixfmt == V4L2_PIX_FMT_UYVY)
- isif_cfg.ycbcr.pix_order = CCDC_PIXORDER_CBYCRY;
- else
- return -EINVAL;
- isif_cfg.data_pack = ISIF_PACK_8BIT;
- }
- return 0;
-}
-
-static u32 isif_get_pixel_format(void)
-{
- u32 pixfmt;
-
- if (isif_cfg.if_type == VPFE_RAW_BAYER)
- if (isif_cfg.bayer.config_params.compress.alg == ISIF_ALAW ||
- isif_cfg.bayer.config_params.compress.alg == ISIF_DPCM)
- pixfmt = V4L2_PIX_FMT_SBGGR8;
- else
- pixfmt = V4L2_PIX_FMT_SBGGR16;
- else {
- if (isif_cfg.ycbcr.pix_order == CCDC_PIXORDER_YCBYCR)
- pixfmt = V4L2_PIX_FMT_YUYV;
- else
- pixfmt = V4L2_PIX_FMT_UYVY;
- }
- return pixfmt;
-}
-
-static int isif_set_image_window(struct v4l2_rect *win)
-{
- if (isif_cfg.if_type == VPFE_RAW_BAYER) {
- isif_cfg.bayer.win.top = win->top;
- isif_cfg.bayer.win.left = win->left;
- isif_cfg.bayer.win.width = win->width;
- isif_cfg.bayer.win.height = win->height;
- } else {
- isif_cfg.ycbcr.win.top = win->top;
- isif_cfg.ycbcr.win.left = win->left;
- isif_cfg.ycbcr.win.width = win->width;
- isif_cfg.ycbcr.win.height = win->height;
- }
- return 0;
-}
-
-static void isif_get_image_window(struct v4l2_rect *win)
-{
- if (isif_cfg.if_type == VPFE_RAW_BAYER)
- *win = isif_cfg.bayer.win;
- else
- *win = isif_cfg.ycbcr.win;
-}
-
-static unsigned int isif_get_line_length(void)
-{
- unsigned int len;
-
- if (isif_cfg.if_type == VPFE_RAW_BAYER) {
- if (isif_cfg.data_pack == ISIF_PACK_8BIT)
- len = ((isif_cfg.bayer.win.width));
- else if (isif_cfg.data_pack == ISIF_PACK_12BIT)
- len = (((isif_cfg.bayer.win.width * 2) +
- (isif_cfg.bayer.win.width >> 2)));
- else
- len = (((isif_cfg.bayer.win.width * 2)));
- } else
- len = (((isif_cfg.ycbcr.win.width * 2)));
- return ALIGN(len, 32);
-}
-
-static int isif_set_frame_format(enum ccdc_frmfmt frm_fmt)
-{
- if (isif_cfg.if_type == VPFE_RAW_BAYER)
- isif_cfg.bayer.frm_fmt = frm_fmt;
- else
- isif_cfg.ycbcr.frm_fmt = frm_fmt;
- return 0;
-}
-static enum ccdc_frmfmt isif_get_frame_format(void)
-{
- if (isif_cfg.if_type == VPFE_RAW_BAYER)
- return isif_cfg.bayer.frm_fmt;
- return isif_cfg.ycbcr.frm_fmt;
-}
-
-static int isif_getfid(void)
-{
- return (regr(MODESET) >> 15) & 0x1;
-}
-
-/* misc operations */
-static void isif_setfbaddr(unsigned long addr)
-{
- regw((addr >> 21) & 0x07ff, CADU);
- regw((addr >> 5) & 0x0ffff, CADL);
-}
-
-static int isif_set_hw_if_params(struct vpfe_hw_if_param *params)
-{
- isif_cfg.if_type = params->if_type;
-
- switch (params->if_type) {
- case VPFE_BT656:
- case VPFE_BT656_10BIT:
- case VPFE_YCBCR_SYNC_8:
- isif_cfg.ycbcr.pix_fmt = CCDC_PIXFMT_YCBCR_8BIT;
- isif_cfg.ycbcr.pix_order = CCDC_PIXORDER_CBYCRY;
- break;
- case VPFE_BT1120:
- case VPFE_YCBCR_SYNC_16:
- isif_cfg.ycbcr.pix_fmt = CCDC_PIXFMT_YCBCR_16BIT;
- isif_cfg.ycbcr.pix_order = CCDC_PIXORDER_CBYCRY;
- break;
- case VPFE_RAW_BAYER:
- isif_cfg.bayer.pix_fmt = CCDC_PIXFMT_RAW;
- break;
- default:
- dev_dbg(isif_cfg.dev, "Invalid interface type\n");
- return -EINVAL;
- }
-
- return 0;
-}
-
-/* This function will configure ISIF for YCbCr parameters. */
-static int isif_config_ycbcr(void)
-{
- struct isif_ycbcr_config *params = &isif_cfg.ycbcr;
- u32 modeset = 0, ccdcfg = 0;
-
- dev_dbg(isif_cfg.dev, "\nStarting isif_config_ycbcr...");
-
- /* configure pixel format or input mode */
- modeset = modeset | (params->pix_fmt << ISIF_INPUT_SHIFT) |
- (params->frm_fmt << ISIF_FRM_FMT_SHIFT) |
- (params->fid_pol << ISIF_FID_POL_SHIFT) |
- (params->hd_pol << ISIF_HD_POL_SHIFT) |
- (params->vd_pol << ISIF_VD_POL_SHIFT);
-
- /* pack the data to 8-bit ISIFCFG */
- switch (isif_cfg.if_type) {
- case VPFE_BT656:
- if (params->pix_fmt != CCDC_PIXFMT_YCBCR_8BIT) {
- dev_dbg(isif_cfg.dev, "Invalid pix_fmt(input mode)\n");
- return -EINVAL;
- }
- modeset |= (VPFE_PINPOL_NEGATIVE << ISIF_VD_POL_SHIFT);
- regw(3, REC656IF);
- ccdcfg = ccdcfg | ISIF_DATA_PACK8 | ISIF_YCINSWP_YCBCR;
- break;
- case VPFE_BT656_10BIT:
- if (params->pix_fmt != CCDC_PIXFMT_YCBCR_8BIT) {
- dev_dbg(isif_cfg.dev, "Invalid pix_fmt(input mode)\n");
- return -EINVAL;
- }
- /* setup BT.656, embedded sync */
- regw(3, REC656IF);
- /* enable 10 bit mode in ccdcfg */
- ccdcfg = ccdcfg | ISIF_DATA_PACK8 | ISIF_YCINSWP_YCBCR |
- ISIF_BW656_ENABLE;
- break;
- case VPFE_BT1120:
- if (params->pix_fmt != CCDC_PIXFMT_YCBCR_16BIT) {
- dev_dbg(isif_cfg.dev, "Invalid pix_fmt(input mode)\n");
- return -EINVAL;
- }
- regw(3, REC656IF);
- break;
-
- case VPFE_YCBCR_SYNC_8:
- ccdcfg |= ISIF_DATA_PACK8;
- ccdcfg |= ISIF_YCINSWP_YCBCR;
- if (params->pix_fmt != CCDC_PIXFMT_YCBCR_8BIT) {
- dev_dbg(isif_cfg.dev, "Invalid pix_fmt(input mode)\n");
- return -EINVAL;
- }
- break;
- case VPFE_YCBCR_SYNC_16:
- if (params->pix_fmt != CCDC_PIXFMT_YCBCR_16BIT) {
- dev_dbg(isif_cfg.dev, "Invalid pix_fmt(input mode)\n");
- return -EINVAL;
- }
- break;
- default:
- /* should never come here */
- dev_dbg(isif_cfg.dev, "Invalid interface type\n");
- return -EINVAL;
- }
-
- regw(modeset, MODESET);
-
- /* Set up pix order */
- ccdcfg |= params->pix_order << ISIF_PIX_ORDER_SHIFT;
-
- regw(ccdcfg, CCDCFG);
-
- /* configure video window */
- if ((isif_cfg.if_type == VPFE_BT1120) ||
- (isif_cfg.if_type == VPFE_YCBCR_SYNC_16))
- isif_setwin(¶ms->win, params->frm_fmt, 1);
- else
- isif_setwin(¶ms->win, params->frm_fmt, 2);
-
- /*
- * configure the horizontal line offset
- * this is done by rounding up width to a multiple of 16 pixels
- * and multiply by two to account for y:cb:cr 4:2:2 data
- */
- regw(((((params->win.width * 2) + 31) & 0xffffffe0) >> 5), HSIZE);
-
- /* configure the memory line offset */
- if ((params->frm_fmt == CCDC_FRMFMT_INTERLACED) &&
- (params->buf_type == CCDC_BUFTYPE_FLD_INTERLEAVED))
- /* two fields are interleaved in memory */
- regw(0x00000249, SDOFST);
-
- return 0;
-}
-
-static int isif_configure(void)
-{
- if (isif_cfg.if_type == VPFE_RAW_BAYER)
- return isif_config_raw();
- return isif_config_ycbcr();
-}
-
-static int isif_close(struct device *device)
-{
- /* copy defaults to module params */
- isif_cfg.bayer.config_params = isif_config_defaults;
- return 0;
-}
-
-static const struct ccdc_hw_device isif_hw_dev = {
- .name = "ISIF",
- .owner = THIS_MODULE,
- .hw_ops = {
- .open = isif_open,
- .close = isif_close,
- .enable = isif_enable,
- .enable_out_to_sdram = isif_enable_output_to_sdram,
- .set_hw_if_params = isif_set_hw_if_params,
- .configure = isif_configure,
- .set_buftype = isif_set_buftype,
- .get_buftype = isif_get_buftype,
- .enum_pix = isif_enum_pix,
- .set_pixel_format = isif_set_pixel_format,
- .get_pixel_format = isif_get_pixel_format,
- .set_frame_format = isif_set_frame_format,
- .get_frame_format = isif_get_frame_format,
- .set_image_window = isif_set_image_window,
- .get_image_window = isif_get_image_window,
- .get_line_length = isif_get_line_length,
- .setfbaddr = isif_setfbaddr,
- .getfid = isif_getfid,
- },
-};
-
-static int isif_probe(struct platform_device *pdev)
-{
- void (*setup_pinmux)(void);
- struct resource *res;
- void __iomem *addr;
- int status = 0, i;
-
- /* Platform data holds setup_pinmux function ptr */
- if (!pdev->dev.platform_data)
- return -ENODEV;
-
- /*
- * first try to register with vpfe. If not correct platform, then we
- * don't have to iomap
- */
- status = vpfe_register_ccdc_device(&isif_hw_dev);
- if (status < 0)
- return status;
-
- setup_pinmux = pdev->dev.platform_data;
- /*
- * setup Mux configuration for ccdc which may be different for
- * different SoCs using this CCDC
- */
- setup_pinmux();
-
- i = 0;
- /* Get the ISIF base address, linearization table0 and table1 addr. */
- while (i < 3) {
- res = platform_get_resource(pdev, IORESOURCE_MEM, i);
- if (!res) {
- status = -ENODEV;
- goto fail_nobase_res;
- }
- res = request_mem_region(res->start, resource_size(res),
- res->name);
- if (!res) {
- status = -EBUSY;
- goto fail_nobase_res;
- }
- addr = ioremap(res->start, resource_size(res));
- if (!addr) {
- status = -ENOMEM;
- goto fail_base_iomap;
- }
- switch (i) {
- case 0:
- /* ISIF base address */
- isif_cfg.base_addr = addr;
- break;
- case 1:
- /* ISIF linear tbl0 address */
- isif_cfg.linear_tbl0_addr = addr;
- break;
- default:
- /* ISIF linear tbl0 address */
- isif_cfg.linear_tbl1_addr = addr;
- break;
- }
- i++;
- }
- isif_cfg.dev = &pdev->dev;
-
- printk(KERN_NOTICE "%s is registered with vpfe.\n",
- isif_hw_dev.name);
- return 0;
-fail_base_iomap:
- release_mem_region(res->start, resource_size(res));
- i--;
-fail_nobase_res:
- if (isif_cfg.base_addr) {
- iounmap(isif_cfg.base_addr);
- isif_cfg.base_addr = NULL;
- }
- if (isif_cfg.linear_tbl0_addr) {
- iounmap(isif_cfg.linear_tbl0_addr);
- isif_cfg.linear_tbl0_addr = NULL;
- }
-
- while (i >= 0) {
- res = platform_get_resource(pdev, IORESOURCE_MEM, i);
- if (res)
- release_mem_region(res->start, resource_size(res));
- i--;
- }
- vpfe_unregister_ccdc_device(&isif_hw_dev);
- return status;
-}
-
-static int isif_remove(struct platform_device *pdev)
-{
- struct resource *res;
- int i = 0;
-
- iounmap(isif_cfg.base_addr);
- isif_cfg.base_addr = NULL;
- iounmap(isif_cfg.linear_tbl0_addr);
- isif_cfg.linear_tbl0_addr = NULL;
- iounmap(isif_cfg.linear_tbl1_addr);
- isif_cfg.linear_tbl1_addr = NULL;
- while (i < 3) {
- res = platform_get_resource(pdev, IORESOURCE_MEM, i);
- release_mem_region(res->start, resource_size(res));
- i++;
- }
- vpfe_unregister_ccdc_device(&isif_hw_dev);
- return 0;
-}
-
-static struct platform_driver isif_driver = {
- .driver = {
- .name = "isif",
- },
- .remove = isif_remove,
- .probe = isif_probe,
-};
-
-module_platform_driver(isif_driver);
-
-MODULE_LICENSE("GPL");
diff --git a/drivers/staging/media/deprecated/vpfe_capture/isif.h b/drivers/staging/media/deprecated/vpfe_capture/isif.h
deleted file mode 100644
index 8369acd26e7e..000000000000
--- a/drivers/staging/media/deprecated/vpfe_capture/isif.h
+++ /dev/null
@@ -1,518 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright (C) 2008-2009 Texas Instruments Inc
- *
- * isif header file
- */
-#ifndef _ISIF_H
-#define _ISIF_H
-
-#include <media/davinci/ccdc_types.h>
-#include <media/davinci/vpfe_types.h>
-
-/* isif float type S8Q8/U8Q8 */
-struct isif_float_8 {
- /* 8 bit integer part */
- __u8 integer;
- /* 8 bit decimal part */
- __u8 decimal;
-};
-
-/* isif float type U16Q16/S16Q16 */
-struct isif_float_16 {
- /* 16 bit integer part */
- __u16 integer;
- /* 16 bit decimal part */
- __u16 decimal;
-};
-
-/************************************************************************
- * Vertical Defect Correction parameters
- ***********************************************************************/
-/* Defect Correction (DFC) table entry */
-struct isif_vdfc_entry {
- /* vertical position of defect */
- __u16 pos_vert;
- /* horizontal position of defect */
- __u16 pos_horz;
- /*
- * Defect level of Vertical line defect position. This is subtracted
- * from the data at the defect position
- */
- __u8 level_at_pos;
- /*
- * Defect level of the pixels upper than the vertical line defect.
- * This is subtracted from the data
- */
- __u8 level_up_pixels;
- /*
- * Defect level of the pixels lower than the vertical line defect.
- * This is subtracted from the data
- */
- __u8 level_low_pixels;
-};
-
-#define ISIF_VDFC_TABLE_SIZE 8
-struct isif_dfc {
- /* enable vertical defect correction */
- __u8 en;
- /* Defect level subtraction. Just fed through if saturating */
-#define ISIF_VDFC_NORMAL 0
- /*
- * Defect level subtraction. Horizontal interpolation ((i-2)+(i+2))/2
- * if data saturating
- */
-#define ISIF_VDFC_HORZ_INTERPOL_IF_SAT 1
- /* Horizontal interpolation (((i-2)+(i+2))/2) */
-#define ISIF_VDFC_HORZ_INTERPOL 2
- /* one of the vertical defect correction modes above */
- __u8 corr_mode;
- /* 0 - whole line corrected, 1 - not pixels upper than the defect */
- __u8 corr_whole_line;
-#define ISIF_VDFC_NO_SHIFT 0
-#define ISIF_VDFC_SHIFT_1 1
-#define ISIF_VDFC_SHIFT_2 2
-#define ISIF_VDFC_SHIFT_3 3
-#define ISIF_VDFC_SHIFT_4 4
- /*
- * defect level shift value. level_at_pos, level_upper_pos,
- * and level_lower_pos can be shifted up by this value. Choose
- * one of the values above
- */
- __u8 def_level_shift;
- /* defect saturation level */
- __u16 def_sat_level;
- /* number of vertical defects. Max is ISIF_VDFC_TABLE_SIZE */
- __u16 num_vdefects;
- /* VDFC table ptr */
- struct isif_vdfc_entry table[ISIF_VDFC_TABLE_SIZE];
-};
-
-struct isif_horz_bclamp {
-
- /* Horizontal clamp disabled. Only vertical clamp value is subtracted */
-#define ISIF_HORZ_BC_DISABLE 0
- /*
- * Horizontal clamp value is calculated and subtracted from image data
- * along with vertical clamp value
- */
-#define ISIF_HORZ_BC_CLAMP_CALC_ENABLED 1
- /*
- * Horizontal clamp value calculated from previous image is subtracted
- * from image data along with vertical clamp value.
- */
-#define ISIF_HORZ_BC_CLAMP_NOT_UPDATED 2
- /* horizontal clamp mode. One of the values above */
- __u8 mode;
- /*
- * pixel value limit enable.
- * 0 - limit disabled
- * 1 - pixel value limited to 1023
- */
- __u8 clamp_pix_limit;
- /* Select Most left window for bc calculation */
-#define ISIF_SEL_MOST_LEFT_WIN 0
- /* Select Most right window for bc calculation */
-#define ISIF_SEL_MOST_RIGHT_WIN 1
- /* Select most left or right window for clamp val calculation */
- __u8 base_win_sel_calc;
- /* Window count per color for calculation. range 1-32 */
- __u8 win_count_calc;
- /* Window start position - horizontal for calculation. 0 - 8191 */
- __u16 win_start_h_calc;
- /* Window start position - vertical for calculation 0 - 8191 */
- __u16 win_start_v_calc;
-#define ISIF_HORZ_BC_SZ_H_2PIXELS 0
-#define ISIF_HORZ_BC_SZ_H_4PIXELS 1
-#define ISIF_HORZ_BC_SZ_H_8PIXELS 2
-#define ISIF_HORZ_BC_SZ_H_16PIXELS 3
- /* Width of the sample window in pixels for calculation */
- __u8 win_h_sz_calc;
-#define ISIF_HORZ_BC_SZ_V_32PIXELS 0
-#define ISIF_HORZ_BC_SZ_V_64PIXELS 1
-#define ISIF_HORZ_BC_SZ_V_128PIXELS 2
-#define ISIF_HORZ_BC_SZ_V_256PIXELS 3
- /* Height of the sample window in pixels for calculation */
- __u8 win_v_sz_calc;
-};
-
-/************************************************************************
- * Black Clamp parameters
- ***********************************************************************/
-struct isif_vert_bclamp {
- /* Reset value used is the clamp value calculated */
-#define ISIF_VERT_BC_USE_HORZ_CLAMP_VAL 0
- /* Reset value used is reset_clamp_val configured */
-#define ISIF_VERT_BC_USE_CONFIG_CLAMP_VAL 1
- /* No update, previous image value is used */
-#define ISIF_VERT_BC_NO_UPDATE 2
- /*
- * Reset value selector for vertical clamp calculation. Use one of
- * the above values
- */
- __u8 reset_val_sel;
- /* U8Q8. Line average coefficient used in vertical clamp calculation */
- __u8 line_ave_coef;
- /* Height of the optical black region for calculation */
- __u16 ob_v_sz_calc;
- /* Optical black region start position - horizontal. 0 - 8191 */
- __u16 ob_start_h;
- /* Optical black region start position - vertical 0 - 8191 */
- __u16 ob_start_v;
-};
-
-struct isif_black_clamp {
- /*
- * This offset value is added irrespective of the clamp enable status.
- * S13
- */
- __u16 dc_offset;
- /*
- * Enable black/digital clamp value to be subtracted from the image data
- */
- __u8 en;
- /*
- * black clamp mode. same/separate clamp for 4 colors
- * 0 - disable - same clamp value for all colors
- * 1 - clamp value calculated separately for all colors
- */
- __u8 bc_mode_color;
- /* Vertical start position for bc subtraction */
- __u16 vert_start_sub;
- /* Black clamp for horizontal direction */
- struct isif_horz_bclamp horz;
- /* Black clamp for vertical direction */
- struct isif_vert_bclamp vert;
-};
-
-/*************************************************************************
-** Color Space Conversion (CSC)
-*************************************************************************/
-#define ISIF_CSC_NUM_COEFF 16
-struct isif_color_space_conv {
- /* Enable color space conversion */
- __u8 en;
- /*
- * csc coefficient table. S8Q5, M00 at index 0, M01 at index 1, and
- * so forth
- */
- struct isif_float_8 coeff[ISIF_CSC_NUM_COEFF];
-};
-
-
-/*************************************************************************
-** Black Compensation parameters
-*************************************************************************/
-struct isif_black_comp {
- /* Comp for Red */
- __s8 r_comp;
- /* Comp for Gr */
- __s8 gr_comp;
- /* Comp for Blue */
- __s8 b_comp;
- /* Comp for Gb */
- __s8 gb_comp;
-};
-
-/*************************************************************************
-** Gain parameters
-*************************************************************************/
-struct isif_gain {
- /* Gain for Red or ye */
- struct isif_float_16 r_ye;
- /* Gain for Gr or cy */
- struct isif_float_16 gr_cy;
- /* Gain for Gb or g */
- struct isif_float_16 gb_g;
- /* Gain for Blue or mg */
- struct isif_float_16 b_mg;
-};
-
-#define ISIF_LINEAR_TAB_SIZE 192
-/*************************************************************************
-** Linearization parameters
-*************************************************************************/
-struct isif_linearize {
- /* Enable or Disable linearization of data */
- __u8 en;
- /* Shift value applied */
- __u8 corr_shft;
- /* scale factor applied U11Q10 */
- struct isif_float_16 scale_fact;
- /* Size of the linear table */
- __u16 table[ISIF_LINEAR_TAB_SIZE];
-};
-
-/* Color patterns */
-#define ISIF_RED 0
-#define ISIF_GREEN_RED 1
-#define ISIF_GREEN_BLUE 2
-#define ISIF_BLUE 3
-struct isif_col_pat {
- __u8 olop;
- __u8 olep;
- __u8 elop;
- __u8 elep;
-};
-
-/*************************************************************************
-** Data formatter parameters
-*************************************************************************/
-struct isif_fmtplen {
- /*
- * number of program entries for SET0, range 1 - 16
- * when fmtmode is ISIF_SPLIT, 1 - 8 when fmtmode is
- * ISIF_COMBINE
- */
- __u16 plen0;
- /*
- * number of program entries for SET1, range 1 - 16
- * when fmtmode is ISIF_SPLIT, 1 - 8 when fmtmode is
- * ISIF_COMBINE
- */
- __u16 plen1;
- /**
- * number of program entries for SET2, range 1 - 16
- * when fmtmode is ISIF_SPLIT, 1 - 8 when fmtmode is
- * ISIF_COMBINE
- */
- __u16 plen2;
- /**
- * number of program entries for SET3, range 1 - 16
- * when fmtmode is ISIF_SPLIT, 1 - 8 when fmtmode is
- * ISIF_COMBINE
- */
- __u16 plen3;
-};
-
-struct isif_fmt_cfg {
-#define ISIF_SPLIT 0
-#define ISIF_COMBINE 1
- /* Split or combine or line alternate */
- __u8 fmtmode;
- /* enable or disable line alternating mode */
- __u8 ln_alter_en;
-#define ISIF_1LINE 0
-#define ISIF_2LINES 1
-#define ISIF_3LINES 2
-#define ISIF_4LINES 3
- /* Split/combine line number */
- __u8 lnum;
- /* Address increment Range 1 - 16 */
- __u8 addrinc;
-};
-
-struct isif_fmt_addr_ptr {
- /* Initial address */
- __u32 init_addr;
- /* output line number */
-#define ISIF_1STLINE 0
-#define ISIF_2NDLINE 1
-#define ISIF_3RDLINE 2
-#define ISIF_4THLINE 3
- __u8 out_line;
-};
-
-struct isif_fmtpgm_ap {
- /* program address pointer */
- __u8 pgm_aptr;
- /* program address increment or decrement */
- __u8 pgmupdt;
-};
-
-struct isif_data_formatter {
- /* Enable/Disable data formatter */
- __u8 en;
- /* data formatter configuration */
- struct isif_fmt_cfg cfg;
- /* Formatter program entries length */
- struct isif_fmtplen plen;
- /* first pixel in a line fed to formatter */
- __u16 fmtrlen;
- /* HD interval for output line. Only valid when split line */
- __u16 fmthcnt;
- /* formatter address pointers */
- struct isif_fmt_addr_ptr fmtaddr_ptr[16];
- /* program enable/disable */
- __u8 pgm_en[32];
- /* program address pointers */
- struct isif_fmtpgm_ap fmtpgm_ap[32];
-};
-
-struct isif_df_csc {
- /* Color Space Conversion configuration, 0 - csc, 1 - df */
- __u8 df_or_csc;
- /* csc configuration valid if df_or_csc is 0 */
- struct isif_color_space_conv csc;
- /* data formatter configuration valid if df_or_csc is 1 */
- struct isif_data_formatter df;
- /* start pixel in a line at the input */
- __u32 start_pix;
- /* number of pixels in input line */
- __u32 num_pixels;
- /* start line at the input */
- __u32 start_line;
- /* number of lines at the input */
- __u32 num_lines;
-};
-
-struct isif_gain_offsets_adj {
- /* Gain adjustment per color */
- struct isif_gain gain;
- /* Offset adjustment */
- __u16 offset;
- /* Enable or Disable Gain adjustment for SDRAM data */
- __u8 gain_sdram_en;
- /* Enable or Disable Gain adjustment for IPIPE data */
- __u8 gain_ipipe_en;
- /* Enable or Disable Gain adjustment for H3A data */
- __u8 gain_h3a_en;
- /* Enable or Disable Gain adjustment for SDRAM data */
- __u8 offset_sdram_en;
- /* Enable or Disable Gain adjustment for IPIPE data */
- __u8 offset_ipipe_en;
- /* Enable or Disable Gain adjustment for H3A data */
- __u8 offset_h3a_en;
-};
-
-struct isif_cul {
- /* Horizontal Cull pattern for odd lines */
- __u8 hcpat_odd;
- /* Horizontal Cull pattern for even lines */
- __u8 hcpat_even;
- /* Vertical Cull pattern */
- __u8 vcpat;
- /* Enable or disable lpf. Apply when cull is enabled */
- __u8 en_lpf;
-};
-
-struct isif_compress {
-#define ISIF_ALAW 0
-#define ISIF_DPCM 1
-#define ISIF_NO_COMPRESSION 2
- /* Compression Algorithm used */
- __u8 alg;
- /* Choose Predictor1 for DPCM compression */
-#define ISIF_DPCM_PRED1 0
- /* Choose Predictor2 for DPCM compression */
-#define ISIF_DPCM_PRED2 1
- /* Predictor for DPCM compression */
- __u8 pred;
-};
-
-/* all the stuff in this struct will be provided by userland */
-struct isif_config_params_raw {
- /* Linearization parameters for image sensor data input */
- struct isif_linearize linearize;
- /* Data formatter or CSC */
- struct isif_df_csc df_csc;
- /* Defect Pixel Correction (DFC) configuration */
- struct isif_dfc dfc;
- /* Black/Digital Clamp configuration */
- struct isif_black_clamp bclamp;
- /* Gain, offset adjustments */
- struct isif_gain_offsets_adj gain_offset;
- /* Culling */
- struct isif_cul culling;
- /* A-Law and DPCM compression options */
- struct isif_compress compress;
- /* horizontal offset for Gain/LSC/DFC */
- __u16 horz_offset;
- /* vertical offset for Gain/LSC/DFC */
- __u16 vert_offset;
- /* color pattern for field 0 */
- struct isif_col_pat col_pat_field0;
- /* color pattern for field 1 */
- struct isif_col_pat col_pat_field1;
-#define ISIF_NO_SHIFT 0
-#define ISIF_1BIT_SHIFT 1
-#define ISIF_2BIT_SHIFT 2
-#define ISIF_3BIT_SHIFT 3
-#define ISIF_4BIT_SHIFT 4
-#define ISIF_5BIT_SHIFT 5
-#define ISIF_6BIT_SHIFT 6
- /* Data shift applied before storing to SDRAM */
- __u8 data_shift;
- /* enable input test pattern generation */
- __u8 test_pat_gen;
-};
-
-#ifdef __KERNEL__
-struct isif_ycbcr_config {
- /* isif pixel format */
- enum ccdc_pixfmt pix_fmt;
- /* isif frame format */
- enum ccdc_frmfmt frm_fmt;
- /* ISIF crop window */
- struct v4l2_rect win;
- /* field polarity */
- enum vpfe_pin_pol fid_pol;
- /* interface VD polarity */
- enum vpfe_pin_pol vd_pol;
- /* interface HD polarity */
- enum vpfe_pin_pol hd_pol;
- /* isif pix order. Only used for ycbcr capture */
- enum ccdc_pixorder pix_order;
- /* isif buffer type. Only used for ycbcr capture */
- enum ccdc_buftype buf_type;
-};
-
-/* MSB of image data connected to sensor port */
-enum isif_data_msb {
- ISIF_BIT_MSB_15,
- ISIF_BIT_MSB_14,
- ISIF_BIT_MSB_13,
- ISIF_BIT_MSB_12,
- ISIF_BIT_MSB_11,
- ISIF_BIT_MSB_10,
- ISIF_BIT_MSB_9,
- ISIF_BIT_MSB_8,
- ISIF_BIT_MSB_7
-};
-
-enum isif_cfa_pattern {
- ISIF_CFA_PAT_MOSAIC,
- ISIF_CFA_PAT_STRIPE
-};
-
-struct isif_params_raw {
- /* isif pixel format */
- enum ccdc_pixfmt pix_fmt;
- /* isif frame format */
- enum ccdc_frmfmt frm_fmt;
- /* video window */
- struct v4l2_rect win;
- /* field polarity */
- enum vpfe_pin_pol fid_pol;
- /* interface VD polarity */
- enum vpfe_pin_pol vd_pol;
- /* interface HD polarity */
- enum vpfe_pin_pol hd_pol;
- /* buffer type. Applicable for interlaced mode */
- enum ccdc_buftype buf_type;
- /* Gain values */
- struct isif_gain gain;
- /* cfa pattern */
- enum isif_cfa_pattern cfa_pat;
- /* Data MSB position */
- enum isif_data_msb data_msb;
- /* Enable horizontal flip */
- unsigned char horz_flip_en;
- /* Enable image invert vertically */
- unsigned char image_invert_en;
-
- /* all the userland defined stuff*/
- struct isif_config_params_raw config_params;
-};
-
-enum isif_data_pack {
- ISIF_PACK_16BIT,
- ISIF_PACK_12BIT,
- ISIF_PACK_8BIT
-};
-
-#define ISIF_WIN_NTSC {0, 0, 720, 480}
-#define ISIF_WIN_VGA {0, 0, 640, 480}
-
-#endif
-#endif
diff --git a/drivers/staging/media/deprecated/vpfe_capture/isif_regs.h b/drivers/staging/media/deprecated/vpfe_capture/isif_regs.h
deleted file mode 100644
index d68d38841ae7..000000000000
--- a/drivers/staging/media/deprecated/vpfe_capture/isif_regs.h
+++ /dev/null
@@ -1,256 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright (C) 2008-2009 Texas Instruments Inc
- */
-#ifndef _ISIF_REGS_H
-#define _ISIF_REGS_H
-
-/* ISIF registers relative offsets */
-#define SYNCEN 0x00
-#define MODESET 0x04
-#define HDW 0x08
-#define VDW 0x0c
-#define PPLN 0x10
-#define LPFR 0x14
-#define SPH 0x18
-#define LNH 0x1c
-#define SLV0 0x20
-#define SLV1 0x24
-#define LNV 0x28
-#define CULH 0x2c
-#define CULV 0x30
-#define HSIZE 0x34
-#define SDOFST 0x38
-#define CADU 0x3c
-#define CADL 0x40
-#define LINCFG0 0x44
-#define LINCFG1 0x48
-#define CCOLP 0x4c
-#define CRGAIN 0x50
-#define CGRGAIN 0x54
-#define CGBGAIN 0x58
-#define CBGAIN 0x5c
-#define COFSTA 0x60
-#define FLSHCFG0 0x64
-#define FLSHCFG1 0x68
-#define FLSHCFG2 0x6c
-#define VDINT0 0x70
-#define VDINT1 0x74
-#define VDINT2 0x78
-#define MISC 0x7c
-#define CGAMMAWD 0x80
-#define REC656IF 0x84
-#define CCDCFG 0x88
-/*****************************************************
-* Defect Correction registers
-*****************************************************/
-#define DFCCTL 0x8c
-#define VDFSATLV 0x90
-#define DFCMEMCTL 0x94
-#define DFCMEM0 0x98
-#define DFCMEM1 0x9c
-#define DFCMEM2 0xa0
-#define DFCMEM3 0xa4
-#define DFCMEM4 0xa8
-/****************************************************
-* Black Clamp registers
-****************************************************/
-#define CLAMPCFG 0xac
-#define CLDCOFST 0xb0
-#define CLSV 0xb4
-#define CLHWIN0 0xb8
-#define CLHWIN1 0xbc
-#define CLHWIN2 0xc0
-#define CLVRV 0xc4
-#define CLVWIN0 0xc8
-#define CLVWIN1 0xcc
-#define CLVWIN2 0xd0
-#define CLVWIN3 0xd4
-/****************************************************
-* Lense Shading Correction
-****************************************************/
-#define DATAHOFST 0xd8
-#define DATAVOFST 0xdc
-#define LSCHVAL 0xe0
-#define LSCVVAL 0xe4
-#define TWODLSCCFG 0xe8
-#define TWODLSCOFST 0xec
-#define TWODLSCINI 0xf0
-#define TWODLSCGRBU 0xf4
-#define TWODLSCGRBL 0xf8
-#define TWODLSCGROF 0xfc
-#define TWODLSCORBU 0x100
-#define TWODLSCORBL 0x104
-#define TWODLSCOROF 0x108
-#define TWODLSCIRQEN 0x10c
-#define TWODLSCIRQST 0x110
-/****************************************************
-* Data formatter
-****************************************************/
-#define FMTCFG 0x114
-#define FMTPLEN 0x118
-#define FMTSPH 0x11c
-#define FMTLNH 0x120
-#define FMTSLV 0x124
-#define FMTLNV 0x128
-#define FMTRLEN 0x12c
-#define FMTHCNT 0x130
-#define FMTAPTR_BASE 0x134
-/* Below macro for addresses FMTAPTR0 - FMTAPTR15 */
-#define FMTAPTR(i) (FMTAPTR_BASE + (i * 4))
-#define FMTPGMVF0 0x174
-#define FMTPGMVF1 0x178
-#define FMTPGMAPU0 0x17c
-#define FMTPGMAPU1 0x180
-#define FMTPGMAPS0 0x184
-#define FMTPGMAPS1 0x188
-#define FMTPGMAPS2 0x18c
-#define FMTPGMAPS3 0x190
-#define FMTPGMAPS4 0x194
-#define FMTPGMAPS5 0x198
-#define FMTPGMAPS6 0x19c
-#define FMTPGMAPS7 0x1a0
-/************************************************
-* Color Space Converter
-************************************************/
-#define CSCCTL 0x1a4
-#define CSCM0 0x1a8
-#define CSCM1 0x1ac
-#define CSCM2 0x1b0
-#define CSCM3 0x1b4
-#define CSCM4 0x1b8
-#define CSCM5 0x1bc
-#define CSCM6 0x1c0
-#define CSCM7 0x1c4
-#define OBWIN0 0x1c8
-#define OBWIN1 0x1cc
-#define OBWIN2 0x1d0
-#define OBWIN3 0x1d4
-#define OBVAL0 0x1d8
-#define OBVAL1 0x1dc
-#define OBVAL2 0x1e0
-#define OBVAL3 0x1e4
-#define OBVAL4 0x1e8
-#define OBVAL5 0x1ec
-#define OBVAL6 0x1f0
-#define OBVAL7 0x1f4
-#define CLKCTL 0x1f8
-
-/* Masks & Shifts below */
-#define START_PX_HOR_MASK 0x7FFF
-#define NUM_PX_HOR_MASK 0x7FFF
-#define START_VER_ONE_MASK 0x7FFF
-#define START_VER_TWO_MASK 0x7FFF
-#define NUM_LINES_VER 0x7FFF
-
-/* gain - offset masks */
-#define GAIN_INTEGER_SHIFT 9
-#define OFFSET_MASK 0xFFF
-#define GAIN_SDRAM_EN_SHIFT 12
-#define GAIN_IPIPE_EN_SHIFT 13
-#define GAIN_H3A_EN_SHIFT 14
-#define OFST_SDRAM_EN_SHIFT 8
-#define OFST_IPIPE_EN_SHIFT 9
-#define OFST_H3A_EN_SHIFT 10
-#define GAIN_OFFSET_EN_MASK 0x7700
-
-/* Culling */
-#define CULL_PAT_EVEN_LINE_SHIFT 8
-
-/* CCDCFG register */
-#define ISIF_YCINSWP_RAW (0x00 << 4)
-#define ISIF_YCINSWP_YCBCR (0x01 << 4)
-#define ISIF_CCDCFG_FIDMD_LATCH_VSYNC (0x00 << 6)
-#define ISIF_CCDCFG_WENLOG_AND (0x00 << 8)
-#define ISIF_CCDCFG_TRGSEL_WEN (0x00 << 9)
-#define ISIF_CCDCFG_EXTRG_DISABLE (0x00 << 10)
-#define ISIF_LATCH_ON_VSYNC_DISABLE (0x01 << 15)
-#define ISIF_LATCH_ON_VSYNC_ENABLE (0x00 << 15)
-#define ISIF_DATA_PACK_MASK 3
-#define ISIF_DATA_PACK16 0
-#define ISIF_DATA_PACK12 1
-#define ISIF_DATA_PACK8 2
-#define ISIF_PIX_ORDER_SHIFT 11
-#define ISIF_BW656_ENABLE (0x01 << 5)
-
-/* MODESET registers */
-#define ISIF_VDHDOUT_INPUT (0x00 << 0)
-#define ISIF_INPUT_SHIFT 12
-#define ISIF_RAW_INPUT_MODE 0
-#define ISIF_FID_POL_SHIFT 4
-#define ISIF_HD_POL_SHIFT 3
-#define ISIF_VD_POL_SHIFT 2
-#define ISIF_DATAPOL_NORMAL 0
-#define ISIF_DATAPOL_SHIFT 6
-#define ISIF_EXWEN_DISABLE 0
-#define ISIF_EXWEN_SHIFT 5
-#define ISIF_FRM_FMT_SHIFT 7
-#define ISIF_DATASFT_SHIFT 8
-#define ISIF_LPF_SHIFT 14
-#define ISIF_LPF_MASK 1
-
-/* GAMMAWD registers */
-#define ISIF_ALAW_GAMMA_WD_MASK 0xF
-#define ISIF_ALAW_GAMMA_WD_SHIFT 1
-#define ISIF_ALAW_ENABLE 1
-#define ISIF_GAMMAWD_CFA_SHIFT 5
-
-/* HSIZE registers */
-#define ISIF_HSIZE_FLIP_MASK 1
-#define ISIF_HSIZE_FLIP_SHIFT 12
-
-/* MISC registers */
-#define ISIF_DPCM_EN_SHIFT 12
-#define ISIF_DPCM_PREDICTOR_SHIFT 13
-
-/* Black clamp related */
-#define ISIF_BC_MODE_COLOR_SHIFT 4
-#define ISIF_HORZ_BC_MODE_SHIFT 1
-#define ISIF_HORZ_BC_WIN_SEL_SHIFT 5
-#define ISIF_HORZ_BC_PIX_LIMIT_SHIFT 6
-#define ISIF_HORZ_BC_WIN_H_SIZE_SHIFT 8
-#define ISIF_HORZ_BC_WIN_V_SIZE_SHIFT 12
-#define ISIF_VERT_BC_RST_VAL_SEL_SHIFT 4
-#define ISIF_VERT_BC_LINE_AVE_COEF_SHIFT 8
-
-/* VDFC registers */
-#define ISIF_VDFC_EN_SHIFT 4
-#define ISIF_VDFC_CORR_MOD_SHIFT 5
-#define ISIF_VDFC_CORR_WHOLE_LN_SHIFT 7
-#define ISIF_VDFC_LEVEL_SHFT_SHIFT 8
-#define ISIF_VDFC_POS_MASK 0x1FFF
-#define ISIF_DFCMEMCTL_DFCMARST_SHIFT 2
-
-/* CSC registers */
-#define ISIF_CSC_COEF_INTEG_MASK 7
-#define ISIF_CSC_COEF_DECIMAL_MASK 0x1f
-#define ISIF_CSC_COEF_INTEG_SHIFT 5
-#define ISIF_CSCM_MSB_SHIFT 8
-#define ISIF_DF_CSC_SPH_MASK 0x1FFF
-#define ISIF_DF_CSC_LNH_MASK 0x1FFF
-#define ISIF_DF_CSC_SLV_MASK 0x1FFF
-#define ISIF_DF_CSC_LNV_MASK 0x1FFF
-#define ISIF_DF_NUMLINES 0x7FFF
-#define ISIF_DF_NUMPIX 0x1FFF
-
-/* Offsets for LSC/DFC/Gain */
-#define ISIF_DATA_H_OFFSET_MASK 0x1FFF
-#define ISIF_DATA_V_OFFSET_MASK 0x1FFF
-
-/* Linearization */
-#define ISIF_LIN_CORRSFT_SHIFT 4
-#define ISIF_LIN_SCALE_FACT_INTEG_SHIFT 10
-
-
-/* Pattern registers */
-#define ISIF_PG_EN (1 << 3)
-#define ISIF_SEL_PG_SRC (3 << 4)
-#define ISIF_PG_VD_POL_SHIFT 0
-#define ISIF_PG_HD_POL_SHIFT 1
-
-/*random other junk*/
-#define ISIF_SYNCEN_VDHDEN_MASK (1 << 0)
-#define ISIF_SYNCEN_WEN_MASK (1 << 1)
-#define ISIF_SYNCEN_WEN_SHIFT 1
-
-#endif
diff --git a/drivers/staging/media/deprecated/vpfe_capture/vpfe_capture.c b/drivers/staging/media/deprecated/vpfe_capture/vpfe_capture.c
deleted file mode 100644
index 0a2226b321d7..000000000000
--- a/drivers/staging/media/deprecated/vpfe_capture/vpfe_capture.c
+++ /dev/null
@@ -1,1902 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright (C) 2008-2009 Texas Instruments Inc
- *
- * Driver name : VPFE Capture driver
- * VPFE Capture driver allows applications to capture and stream video
- * frames on DaVinci SoCs (DM6446, DM355 etc) from a YUV source such as
- * TVP5146 or Raw Bayer RGB image data from an image sensor
- * such as Microns' MT9T001, MT9T031 etc.
- *
- * These SoCs have, in common, a Video Processing Subsystem (VPSS) that
- * consists of a Video Processing Front End (VPFE) for capturing
- * video/raw image data and Video Processing Back End (VPBE) for displaying
- * YUV data through an in-built analog encoder or Digital LCD port. This
- * driver is for capture through VPFE. A typical EVM using these SoCs have
- * following high level configuration.
- *
- * decoder(TVP5146/ YUV/
- * MT9T001) --> Raw Bayer RGB ---> MUX -> VPFE (CCDC/ISIF)
- * data input | |
- * V |
- * SDRAM |
- * V
- * Image Processor
- * |
- * V
- * SDRAM
- * The data flow happens from a decoder connected to the VPFE over a
- * YUV embedded (BT.656/BT.1120) or separate sync or raw bayer rgb interface
- * and to the input of VPFE through an optional MUX (if more inputs are
- * to be interfaced on the EVM). The input data is first passed through
- * CCDC (CCD Controller, a.k.a Image Sensor Interface, ISIF). The CCDC
- * does very little or no processing on YUV data and does pre-process Raw
- * Bayer RGB data through modules such as Defect Pixel Correction (DFC)
- * Color Space Conversion (CSC), data gain/offset etc. After this, data
- * can be written to SDRAM or can be connected to the image processing
- * block such as IPIPE (on DM355 only).
- *
- * Features supported
- * - MMAP IO
- * - Capture using TVP5146 over BT.656
- * - support for interfacing decoders using sub device model
- * - Work with DM355 or DM6446 CCDC to do Raw Bayer RGB/YUV
- * data capture to SDRAM.
- * TODO list
- * - Support multiple REQBUF after open
- * - Support for de-allocating buffers through REQBUF
- * - Support for Raw Bayer RGB capture
- * - Support for chaining Image Processor
- * - Support for static allocation of buffers
- * - Support for USERPTR IO
- * - Support for STREAMON before QBUF
- * - Support for control ioctls
- */
-#include <linux/module.h>
-#include <linux/slab.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <media/v4l2-common.h>
-#include <linux/io.h>
-#include <media/davinci/vpfe_capture.h>
-#include "ccdc_hw_device.h"
-
-static int debug;
-static u32 numbuffers = 3;
-static u32 bufsize = (720 * 576 * 2);
-
-module_param(numbuffers, uint, S_IRUGO);
-module_param(bufsize, uint, S_IRUGO);
-module_param(debug, int, 0644);
-
-MODULE_PARM_DESC(numbuffers, "buffer count (default:3)");
-MODULE_PARM_DESC(bufsize, "buffer size in bytes (default:720 x 576 x 2)");
-MODULE_PARM_DESC(debug, "Debug level 0-1");
-
-MODULE_DESCRIPTION("VPFE Video for Linux Capture Driver");
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Texas Instruments");
-
-/* standard information */
-struct vpfe_standard {
- v4l2_std_id std_id;
- unsigned int width;
- unsigned int height;
- struct v4l2_fract pixelaspect;
- /* 0 - progressive, 1 - interlaced */
- int frame_format;
-};
-
-/* ccdc configuration */
-struct ccdc_config {
- /* This make sure vpfe is probed and ready to go */
- int vpfe_probed;
- /* name of ccdc device */
- char name[32];
-};
-
-/* data structures */
-static struct vpfe_config_params config_params = {
- .min_numbuffers = 3,
- .numbuffers = 3,
- .min_bufsize = 720 * 480 * 2,
- .device_bufsize = 720 * 576 * 2,
-};
-
-/* ccdc device registered */
-static const struct ccdc_hw_device *ccdc_dev;
-/* lock for accessing ccdc information */
-static DEFINE_MUTEX(ccdc_lock);
-/* ccdc configuration */
-static struct ccdc_config *ccdc_cfg;
-
-static const struct vpfe_standard vpfe_standards[] = {
- {V4L2_STD_525_60, 720, 480, {11, 10}, 1},
- {V4L2_STD_625_50, 720, 576, {54, 59}, 1},
-};
-
-/* Used when raw Bayer image from ccdc is directly captured to SDRAM */
-static const struct vpfe_pixel_format vpfe_pix_fmts[] = {
- {
- .pixelformat = V4L2_PIX_FMT_SBGGR8,
- .bpp = 1,
- },
- {
- .pixelformat = V4L2_PIX_FMT_SBGGR16,
- .bpp = 2,
- },
- {
- .pixelformat = V4L2_PIX_FMT_SGRBG10DPCM8,
- .bpp = 1,
- },
- {
- .pixelformat = V4L2_PIX_FMT_UYVY,
- .bpp = 2,
- },
- {
- .pixelformat = V4L2_PIX_FMT_YUYV,
- .bpp = 2,
- },
- {
- .pixelformat = V4L2_PIX_FMT_NV12,
- .bpp = 1,
- },
-};
-
-/*
- * vpfe_lookup_pix_format()
- * lookup an entry in the vpfe pix format table based on pix_format
- */
-static const struct vpfe_pixel_format *vpfe_lookup_pix_format(u32 pix_format)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(vpfe_pix_fmts); i++) {
- if (pix_format == vpfe_pix_fmts[i].pixelformat)
- return &vpfe_pix_fmts[i];
- }
- return NULL;
-}
-
-/*
- * vpfe_register_ccdc_device. CCDC module calls this to
- * register with vpfe capture
- */
-int vpfe_register_ccdc_device(const struct ccdc_hw_device *dev)
-{
- int ret = 0;
- printk(KERN_NOTICE "vpfe_register_ccdc_device: %s\n", dev->name);
-
- if (!dev->hw_ops.open ||
- !dev->hw_ops.enable ||
- !dev->hw_ops.set_hw_if_params ||
- !dev->hw_ops.configure ||
- !dev->hw_ops.set_buftype ||
- !dev->hw_ops.get_buftype ||
- !dev->hw_ops.enum_pix ||
- !dev->hw_ops.set_frame_format ||
- !dev->hw_ops.get_frame_format ||
- !dev->hw_ops.get_pixel_format ||
- !dev->hw_ops.set_pixel_format ||
- !dev->hw_ops.set_image_window ||
- !dev->hw_ops.get_image_window ||
- !dev->hw_ops.get_line_length ||
- !dev->hw_ops.getfid)
- return -EINVAL;
-
- mutex_lock(&ccdc_lock);
- if (!ccdc_cfg) {
- /*
- * TODO. Will this ever happen? if so, we need to fix it.
- * Probably we need to add the request to a linked list and
- * walk through it during vpfe probe
- */
- printk(KERN_ERR "vpfe capture not initialized\n");
- ret = -EFAULT;
- goto unlock;
- }
-
- if (strcmp(dev->name, ccdc_cfg->name)) {
- /* ignore this ccdc */
- ret = -EINVAL;
- goto unlock;
- }
-
- if (ccdc_dev) {
- printk(KERN_ERR "ccdc already registered\n");
- ret = -EINVAL;
- goto unlock;
- }
-
- ccdc_dev = dev;
-unlock:
- mutex_unlock(&ccdc_lock);
- return ret;
-}
-EXPORT_SYMBOL(vpfe_register_ccdc_device);
-
-/*
- * vpfe_unregister_ccdc_device. CCDC module calls this to
- * unregister with vpfe capture
- */
-void vpfe_unregister_ccdc_device(const struct ccdc_hw_device *dev)
-{
- if (!dev) {
- printk(KERN_ERR "invalid ccdc device ptr\n");
- return;
- }
-
- printk(KERN_NOTICE "vpfe_unregister_ccdc_device, dev->name = %s\n",
- dev->name);
-
- if (strcmp(dev->name, ccdc_cfg->name)) {
- /* ignore this ccdc */
- return;
- }
-
- mutex_lock(&ccdc_lock);
- ccdc_dev = NULL;
- mutex_unlock(&ccdc_lock);
-}
-EXPORT_SYMBOL(vpfe_unregister_ccdc_device);
-
-/*
- * vpfe_config_ccdc_image_format()
- * For a pix format, configure ccdc to setup the capture
- */
-static int vpfe_config_ccdc_image_format(struct vpfe_device *vpfe_dev)
-{
- enum ccdc_frmfmt frm_fmt = CCDC_FRMFMT_INTERLACED;
- int ret = 0;
-
- if (ccdc_dev->hw_ops.set_pixel_format(
- vpfe_dev->fmt.fmt.pix.pixelformat) < 0) {
- v4l2_err(&vpfe_dev->v4l2_dev,
- "couldn't set pix format in ccdc\n");
- return -EINVAL;
- }
- /* configure the image window */
- ccdc_dev->hw_ops.set_image_window(&vpfe_dev->crop);
-
- switch (vpfe_dev->fmt.fmt.pix.field) {
- case V4L2_FIELD_INTERLACED:
- /* do nothing, since it is default */
- ret = ccdc_dev->hw_ops.set_buftype(
- CCDC_BUFTYPE_FLD_INTERLEAVED);
- break;
- case V4L2_FIELD_NONE:
- frm_fmt = CCDC_FRMFMT_PROGRESSIVE;
- /* buffer type only applicable for interlaced scan */
- break;
- case V4L2_FIELD_SEQ_TB:
- ret = ccdc_dev->hw_ops.set_buftype(
- CCDC_BUFTYPE_FLD_SEPARATED);
- break;
- default:
- return -EINVAL;
- }
-
- /* set the frame format */
- if (!ret)
- ret = ccdc_dev->hw_ops.set_frame_format(frm_fmt);
- return ret;
-}
-/*
- * vpfe_config_image_format()
- * For a given standard, this functions sets up the default
- * pix format & crop values in the vpfe device and ccdc. It first
- * starts with defaults based values from the standard table.
- * It then checks if sub device supports get_fmt and then override the
- * values based on that.Sets crop values to match with scan resolution
- * starting at 0,0. It calls vpfe_config_ccdc_image_format() set the
- * values in ccdc
- */
-static int vpfe_config_image_format(struct vpfe_device *vpfe_dev,
- v4l2_std_id std_id)
-{
- struct vpfe_subdev_info *sdinfo = vpfe_dev->current_subdev;
- struct v4l2_subdev_format fmt = {
- .which = V4L2_SUBDEV_FORMAT_ACTIVE,
- };
- struct v4l2_mbus_framefmt *mbus_fmt = &fmt.format;
- struct v4l2_pix_format *pix = &vpfe_dev->fmt.fmt.pix;
- int i, ret;
-
- for (i = 0; i < ARRAY_SIZE(vpfe_standards); i++) {
- if (vpfe_standards[i].std_id & std_id) {
- vpfe_dev->std_info.active_pixels =
- vpfe_standards[i].width;
- vpfe_dev->std_info.active_lines =
- vpfe_standards[i].height;
- vpfe_dev->std_info.frame_format =
- vpfe_standards[i].frame_format;
- vpfe_dev->std_index = i;
- break;
- }
- }
-
- if (i == ARRAY_SIZE(vpfe_standards)) {
- v4l2_err(&vpfe_dev->v4l2_dev, "standard not supported\n");
- return -EINVAL;
- }
-
- vpfe_dev->crop.top = 0;
- vpfe_dev->crop.left = 0;
- vpfe_dev->crop.width = vpfe_dev->std_info.active_pixels;
- vpfe_dev->crop.height = vpfe_dev->std_info.active_lines;
- pix->width = vpfe_dev->crop.width;
- pix->height = vpfe_dev->crop.height;
-
- /* first field and frame format based on standard frame format */
- if (vpfe_dev->std_info.frame_format) {
- pix->field = V4L2_FIELD_INTERLACED;
- /* assume V4L2_PIX_FMT_UYVY as default */
- pix->pixelformat = V4L2_PIX_FMT_UYVY;
- v4l2_fill_mbus_format(mbus_fmt, pix,
- MEDIA_BUS_FMT_YUYV10_2X10);
- } else {
- pix->field = V4L2_FIELD_NONE;
- /* assume V4L2_PIX_FMT_SBGGR8 */
- pix->pixelformat = V4L2_PIX_FMT_SBGGR8;
- v4l2_fill_mbus_format(mbus_fmt, pix,
- MEDIA_BUS_FMT_SBGGR8_1X8);
- }
-
- /* if sub device supports get_fmt, override the defaults */
- ret = v4l2_device_call_until_err(&vpfe_dev->v4l2_dev,
- sdinfo->grp_id, pad, get_fmt, NULL, &fmt);
-
- if (ret && ret != -ENOIOCTLCMD) {
- v4l2_err(&vpfe_dev->v4l2_dev,
- "error in getting get_fmt from sub device\n");
- return ret;
- }
- v4l2_fill_pix_format(pix, mbus_fmt);
- pix->bytesperline = pix->width * 2;
- pix->sizeimage = pix->bytesperline * pix->height;
-
- /* Sets the values in CCDC */
- ret = vpfe_config_ccdc_image_format(vpfe_dev);
- if (ret)
- return ret;
-
- /* Update the values of sizeimage and bytesperline */
- pix->bytesperline = ccdc_dev->hw_ops.get_line_length();
- pix->sizeimage = pix->bytesperline * pix->height;
-
- return 0;
-}
-
-static int vpfe_initialize_device(struct vpfe_device *vpfe_dev)
-{
- int ret;
-
- /* set first input of current subdevice as the current input */
- vpfe_dev->current_input = 0;
-
- /* set default standard */
- vpfe_dev->std_index = 0;
-
- /* Configure the default format information */
- ret = vpfe_config_image_format(vpfe_dev,
- vpfe_standards[vpfe_dev->std_index].std_id);
- if (ret)
- return ret;
-
- /* now open the ccdc device to initialize it */
- mutex_lock(&ccdc_lock);
- if (!ccdc_dev) {
- v4l2_err(&vpfe_dev->v4l2_dev, "ccdc device not registered\n");
- ret = -ENODEV;
- goto unlock;
- }
-
- if (!try_module_get(ccdc_dev->owner)) {
- v4l2_err(&vpfe_dev->v4l2_dev, "Couldn't lock ccdc module\n");
- ret = -ENODEV;
- goto unlock;
- }
- ret = ccdc_dev->hw_ops.open(vpfe_dev->pdev);
- if (!ret)
- vpfe_dev->initialized = 1;
-
- /* Clear all VPFE/CCDC interrupts */
- if (vpfe_dev->cfg->clr_intr)
- vpfe_dev->cfg->clr_intr(-1);
-
-unlock:
- mutex_unlock(&ccdc_lock);
- return ret;
-}
-
-/*
- * vpfe_open : It creates object of file handle structure and
- * stores it in private_data member of filepointer
- */
-static int vpfe_open(struct file *file)
-{
- struct vpfe_device *vpfe_dev = video_drvdata(file);
- struct video_device *vdev = video_devdata(file);
- struct vpfe_fh *fh;
-
- v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_open\n");
-
- if (!vpfe_dev->cfg->num_subdevs) {
- v4l2_err(&vpfe_dev->v4l2_dev, "No decoder registered\n");
- return -ENODEV;
- }
-
- /* Allocate memory for the file handle object */
- fh = kmalloc(sizeof(*fh), GFP_KERNEL);
- if (!fh)
- return -ENOMEM;
-
- /* store pointer to fh in private_data member of file */
- file->private_data = fh;
- fh->vpfe_dev = vpfe_dev;
- v4l2_fh_init(&fh->fh, vdev);
- mutex_lock(&vpfe_dev->lock);
- /* If decoder is not initialized. initialize it */
- if (!vpfe_dev->initialized) {
- if (vpfe_initialize_device(vpfe_dev)) {
- mutex_unlock(&vpfe_dev->lock);
- v4l2_fh_exit(&fh->fh);
- kfree(fh);
- return -ENODEV;
- }
- }
- /* Increment device usrs counter */
- vpfe_dev->usrs++;
- /* Set io_allowed member to false */
- fh->io_allowed = 0;
- v4l2_fh_add(&fh->fh);
- mutex_unlock(&vpfe_dev->lock);
- return 0;
-}
-
-static void vpfe_schedule_next_buffer(struct vpfe_device *vpfe_dev)
-{
- unsigned long addr;
-
- vpfe_dev->next_frm = list_entry(vpfe_dev->dma_queue.next,
- struct videobuf_buffer, queue);
- list_del(&vpfe_dev->next_frm->queue);
- vpfe_dev->next_frm->state = VIDEOBUF_ACTIVE;
- addr = videobuf_to_dma_contig(vpfe_dev->next_frm);
-
- ccdc_dev->hw_ops.setfbaddr(addr);
-}
-
-static void vpfe_schedule_bottom_field(struct vpfe_device *vpfe_dev)
-{
- unsigned long addr;
-
- addr = videobuf_to_dma_contig(vpfe_dev->cur_frm);
- addr += vpfe_dev->field_off;
- ccdc_dev->hw_ops.setfbaddr(addr);
-}
-
-static void vpfe_process_buffer_complete(struct vpfe_device *vpfe_dev)
-{
- vpfe_dev->cur_frm->ts = ktime_get_ns();
- vpfe_dev->cur_frm->state = VIDEOBUF_DONE;
- vpfe_dev->cur_frm->size = vpfe_dev->fmt.fmt.pix.sizeimage;
- wake_up_interruptible(&vpfe_dev->cur_frm->done);
- vpfe_dev->cur_frm = vpfe_dev->next_frm;
-}
-
-/* ISR for VINT0*/
-static irqreturn_t vpfe_isr(int irq, void *dev_id)
-{
- struct vpfe_device *vpfe_dev = dev_id;
- enum v4l2_field field;
- int fid;
-
- v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "\nStarting vpfe_isr...\n");
- field = vpfe_dev->fmt.fmt.pix.field;
-
- /* if streaming not started, don't do anything */
- if (!vpfe_dev->started)
- goto clear_intr;
-
- /* only for 6446 this will be applicable */
- if (ccdc_dev->hw_ops.reset)
- ccdc_dev->hw_ops.reset();
-
- if (field == V4L2_FIELD_NONE) {
- /* handle progressive frame capture */
- v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev,
- "frame format is progressive...\n");
- if (vpfe_dev->cur_frm != vpfe_dev->next_frm)
- vpfe_process_buffer_complete(vpfe_dev);
- goto clear_intr;
- }
-
- /* interlaced or TB capture check which field we are in hardware */
- fid = ccdc_dev->hw_ops.getfid();
-
- /* switch the software maintained field id */
- vpfe_dev->field_id ^= 1;
- v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "field id = %x:%x.\n",
- fid, vpfe_dev->field_id);
- if (fid == vpfe_dev->field_id) {
- /* we are in-sync here,continue */
- if (fid == 0) {
- /*
- * One frame is just being captured. If the next frame
- * is available, release the current frame and move on
- */
- if (vpfe_dev->cur_frm != vpfe_dev->next_frm)
- vpfe_process_buffer_complete(vpfe_dev);
- /*
- * based on whether the two fields are stored
- * interleavely or separately in memory, reconfigure
- * the CCDC memory address
- */
- if (field == V4L2_FIELD_SEQ_TB)
- vpfe_schedule_bottom_field(vpfe_dev);
- goto clear_intr;
- }
- /*
- * if one field is just being captured configure
- * the next frame get the next frame from the empty
- * queue if no frame is available hold on to the
- * current buffer
- */
- spin_lock(&vpfe_dev->dma_queue_lock);
- if (!list_empty(&vpfe_dev->dma_queue) &&
- vpfe_dev->cur_frm == vpfe_dev->next_frm)
- vpfe_schedule_next_buffer(vpfe_dev);
- spin_unlock(&vpfe_dev->dma_queue_lock);
- } else if (fid == 0) {
- /*
- * out of sync. Recover from any hardware out-of-sync.
- * May loose one frame
- */
- vpfe_dev->field_id = fid;
- }
-clear_intr:
- if (vpfe_dev->cfg->clr_intr)
- vpfe_dev->cfg->clr_intr(irq);
-
- return IRQ_HANDLED;
-}
-
-/* vdint1_isr - isr handler for VINT1 interrupt */
-static irqreturn_t vdint1_isr(int irq, void *dev_id)
-{
- struct vpfe_device *vpfe_dev = dev_id;
-
- v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "\nInside vdint1_isr...\n");
-
- /* if streaming not started, don't do anything */
- if (!vpfe_dev->started) {
- if (vpfe_dev->cfg->clr_intr)
- vpfe_dev->cfg->clr_intr(irq);
- return IRQ_HANDLED;
- }
-
- spin_lock(&vpfe_dev->dma_queue_lock);
- if ((vpfe_dev->fmt.fmt.pix.field == V4L2_FIELD_NONE) &&
- !list_empty(&vpfe_dev->dma_queue) &&
- vpfe_dev->cur_frm == vpfe_dev->next_frm)
- vpfe_schedule_next_buffer(vpfe_dev);
- spin_unlock(&vpfe_dev->dma_queue_lock);
-
- if (vpfe_dev->cfg->clr_intr)
- vpfe_dev->cfg->clr_intr(irq);
-
- return IRQ_HANDLED;
-}
-
-static void vpfe_detach_irq(struct vpfe_device *vpfe_dev)
-{
- enum ccdc_frmfmt frame_format;
-
- frame_format = ccdc_dev->hw_ops.get_frame_format();
- if (frame_format == CCDC_FRMFMT_PROGRESSIVE)
- free_irq(vpfe_dev->ccdc_irq1, vpfe_dev);
-}
-
-static int vpfe_attach_irq(struct vpfe_device *vpfe_dev)
-{
- enum ccdc_frmfmt frame_format;
-
- frame_format = ccdc_dev->hw_ops.get_frame_format();
- if (frame_format == CCDC_FRMFMT_PROGRESSIVE) {
- return request_irq(vpfe_dev->ccdc_irq1, vdint1_isr,
- 0, "vpfe_capture1",
- vpfe_dev);
- }
- return 0;
-}
-
-/* vpfe_stop_ccdc_capture: stop streaming in ccdc/isif */
-static void vpfe_stop_ccdc_capture(struct vpfe_device *vpfe_dev)
-{
- vpfe_dev->started = 0;
- ccdc_dev->hw_ops.enable(0);
- if (ccdc_dev->hw_ops.enable_out_to_sdram)
- ccdc_dev->hw_ops.enable_out_to_sdram(0);
-}
-
-/*
- * vpfe_release : This function deletes buffer queue, frees the
- * buffers and the vpfe file handle
- */
-static int vpfe_release(struct file *file)
-{
- struct vpfe_device *vpfe_dev = video_drvdata(file);
- struct vpfe_fh *fh = file->private_data;
- struct vpfe_subdev_info *sdinfo;
- int ret;
-
- v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_release\n");
-
- /* Get the device lock */
- mutex_lock(&vpfe_dev->lock);
- /* if this instance is doing IO */
- if (fh->io_allowed) {
- if (vpfe_dev->started) {
- sdinfo = vpfe_dev->current_subdev;
- ret = v4l2_device_call_until_err(&vpfe_dev->v4l2_dev,
- sdinfo->grp_id,
- video, s_stream, 0);
- if (ret && (ret != -ENOIOCTLCMD))
- v4l2_err(&vpfe_dev->v4l2_dev,
- "stream off failed in subdev\n");
- vpfe_stop_ccdc_capture(vpfe_dev);
- vpfe_detach_irq(vpfe_dev);
- videobuf_streamoff(&vpfe_dev->buffer_queue);
- }
- vpfe_dev->io_usrs = 0;
- vpfe_dev->numbuffers = config_params.numbuffers;
- videobuf_stop(&vpfe_dev->buffer_queue);
- videobuf_mmap_free(&vpfe_dev->buffer_queue);
- }
-
- /* Decrement device usrs counter */
- vpfe_dev->usrs--;
- v4l2_fh_del(&fh->fh);
- v4l2_fh_exit(&fh->fh);
- /* If this is the last file handle */
- if (!vpfe_dev->usrs) {
- vpfe_dev->initialized = 0;
- if (ccdc_dev->hw_ops.close)
- ccdc_dev->hw_ops.close(vpfe_dev->pdev);
- module_put(ccdc_dev->owner);
- }
- mutex_unlock(&vpfe_dev->lock);
- file->private_data = NULL;
- /* Free memory allocated to file handle object */
- kfree(fh);
- return 0;
-}
-
-/*
- * vpfe_mmap : It is used to map kernel space buffers
- * into user spaces
- */
-static int vpfe_mmap(struct file *file, struct vm_area_struct *vma)
-{
- /* Get the device object and file handle object */
- struct vpfe_device *vpfe_dev = video_drvdata(file);
-
- v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_mmap\n");
-
- return videobuf_mmap_mapper(&vpfe_dev->buffer_queue, vma);
-}
-
-/*
- * vpfe_poll: It is used for select/poll system call
- */
-static __poll_t vpfe_poll(struct file *file, poll_table *wait)
-{
- struct vpfe_device *vpfe_dev = video_drvdata(file);
-
- v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_poll\n");
-
- if (vpfe_dev->started)
- return videobuf_poll_stream(file,
- &vpfe_dev->buffer_queue, wait);
- return 0;
-}
-
-/* vpfe capture driver file operations */
-static const struct v4l2_file_operations vpfe_fops = {
- .owner = THIS_MODULE,
- .open = vpfe_open,
- .release = vpfe_release,
- .unlocked_ioctl = video_ioctl2,
- .mmap = vpfe_mmap,
- .poll = vpfe_poll
-};
-
-/*
- * vpfe_check_format()
- * This function adjust the input pixel format as per hardware
- * capabilities and update the same in pixfmt.
- * Following algorithm used :-
- *
- * If given pixformat is not in the vpfe list of pix formats or not
- * supported by the hardware, current value of pixformat in the device
- * is used
- * If given field is not supported, then current field is used. If field
- * is different from current, then it is matched with that from sub device.
- * Minimum height is 2 lines for interlaced or tb field and 1 line for
- * progressive. Maximum height is clamped to active active lines of scan
- * Minimum width is 32 bytes in memory and width is clamped to active
- * pixels of scan.
- * bytesperline is a multiple of 32.
- */
-static const struct vpfe_pixel_format *
- vpfe_check_format(struct vpfe_device *vpfe_dev,
- struct v4l2_pix_format *pixfmt)
-{
- u32 min_height = 1, min_width = 32, max_width, max_height;
- const struct vpfe_pixel_format *vpfe_pix_fmt;
- u32 pix;
- int temp, found;
-
- vpfe_pix_fmt = vpfe_lookup_pix_format(pixfmt->pixelformat);
- if (!vpfe_pix_fmt) {
- /*
- * use current pixel format in the vpfe device. We
- * will find this pix format in the table
- */
- pixfmt->pixelformat = vpfe_dev->fmt.fmt.pix.pixelformat;
- vpfe_pix_fmt = vpfe_lookup_pix_format(pixfmt->pixelformat);
- }
-
- /* check if hw supports it */
- temp = 0;
- found = 0;
- while (ccdc_dev->hw_ops.enum_pix(&pix, temp) >= 0) {
- if (vpfe_pix_fmt->pixelformat == pix) {
- found = 1;
- break;
- }
- temp++;
- }
-
- if (!found) {
- /* use current pixel format */
- pixfmt->pixelformat = vpfe_dev->fmt.fmt.pix.pixelformat;
- /*
- * Since this is currently used in the vpfe device, we
- * will find this pix format in the table
- */
- vpfe_pix_fmt = vpfe_lookup_pix_format(pixfmt->pixelformat);
- }
-
- /* check what field format is supported */
- if (pixfmt->field == V4L2_FIELD_ANY) {
- /* if field is any, use current value as default */
- pixfmt->field = vpfe_dev->fmt.fmt.pix.field;
- }
-
- /*
- * if field is not same as current field in the vpfe device
- * try matching the field with the sub device field
- */
- if (vpfe_dev->fmt.fmt.pix.field != pixfmt->field) {
- /*
- * If field value is not in the supported fields, use current
- * field used in the device as default
- */
- switch (pixfmt->field) {
- case V4L2_FIELD_INTERLACED:
- case V4L2_FIELD_SEQ_TB:
- /* if sub device is supporting progressive, use that */
- if (!vpfe_dev->std_info.frame_format)
- pixfmt->field = V4L2_FIELD_NONE;
- break;
- case V4L2_FIELD_NONE:
- if (vpfe_dev->std_info.frame_format)
- pixfmt->field = V4L2_FIELD_INTERLACED;
- break;
-
- default:
- /* use current field as default */
- pixfmt->field = vpfe_dev->fmt.fmt.pix.field;
- break;
- }
- }
-
- /* Now adjust image resolutions supported */
- if (pixfmt->field == V4L2_FIELD_INTERLACED ||
- pixfmt->field == V4L2_FIELD_SEQ_TB)
- min_height = 2;
-
- max_width = vpfe_dev->std_info.active_pixels;
- max_height = vpfe_dev->std_info.active_lines;
- min_width /= vpfe_pix_fmt->bpp;
-
- v4l2_info(&vpfe_dev->v4l2_dev, "width = %d, height = %d, bpp = %d\n",
- pixfmt->width, pixfmt->height, vpfe_pix_fmt->bpp);
-
- pixfmt->width = clamp((pixfmt->width), min_width, max_width);
- pixfmt->height = clamp((pixfmt->height), min_height, max_height);
-
- /* If interlaced, adjust height to be a multiple of 2 */
- if (pixfmt->field == V4L2_FIELD_INTERLACED)
- pixfmt->height &= (~1);
- /*
- * recalculate bytesperline and sizeimage since width
- * and height might have changed
- */
- pixfmt->bytesperline = (((pixfmt->width * vpfe_pix_fmt->bpp) + 31)
- & ~31);
- if (pixfmt->pixelformat == V4L2_PIX_FMT_NV12)
- pixfmt->sizeimage =
- pixfmt->bytesperline * pixfmt->height +
- ((pixfmt->bytesperline * pixfmt->height) >> 1);
- else
- pixfmt->sizeimage = pixfmt->bytesperline * pixfmt->height;
-
- v4l2_info(&vpfe_dev->v4l2_dev, "adjusted width = %d, height = %d, bpp = %d, bytesperline = %d, sizeimage = %d\n",
- pixfmt->width, pixfmt->height, vpfe_pix_fmt->bpp,
- pixfmt->bytesperline, pixfmt->sizeimage);
- return vpfe_pix_fmt;
-}
-
-static int vpfe_querycap(struct file *file, void *priv,
- struct v4l2_capability *cap)
-{
- struct vpfe_device *vpfe_dev = video_drvdata(file);
-
- v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_querycap\n");
-
- strscpy(cap->driver, CAPTURE_DRV_NAME, sizeof(cap->driver));
- strscpy(cap->bus_info, "VPFE", sizeof(cap->bus_info));
- strscpy(cap->card, vpfe_dev->cfg->card_name, sizeof(cap->card));
- return 0;
-}
-
-static int vpfe_g_fmt_vid_cap(struct file *file, void *priv,
- struct v4l2_format *fmt)
-{
- struct vpfe_device *vpfe_dev = video_drvdata(file);
-
- v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_g_fmt_vid_cap\n");
- /* Fill in the information about format */
- *fmt = vpfe_dev->fmt;
- return 0;
-}
-
-static int vpfe_enum_fmt_vid_cap(struct file *file, void *priv,
- struct v4l2_fmtdesc *fmt)
-{
- struct vpfe_device *vpfe_dev = video_drvdata(file);
- const struct vpfe_pixel_format *pix_fmt;
- u32 pix;
-
- v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_enum_fmt_vid_cap\n");
-
- if (ccdc_dev->hw_ops.enum_pix(&pix, fmt->index) < 0)
- return -EINVAL;
-
- /* Fill in the information about format */
- pix_fmt = vpfe_lookup_pix_format(pix);
- if (pix_fmt) {
- fmt->pixelformat = pix_fmt->pixelformat;
- return 0;
- }
- return -EINVAL;
-}
-
-static int vpfe_s_fmt_vid_cap(struct file *file, void *priv,
- struct v4l2_format *fmt)
-{
- struct vpfe_device *vpfe_dev = video_drvdata(file);
- const struct vpfe_pixel_format *pix_fmts;
- int ret;
-
- v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_s_fmt_vid_cap\n");
-
- /* If streaming is started, return error */
- if (vpfe_dev->started) {
- v4l2_err(&vpfe_dev->v4l2_dev, "Streaming is started\n");
- return -EBUSY;
- }
-
- /* Check for valid frame format */
- pix_fmts = vpfe_check_format(vpfe_dev, &fmt->fmt.pix);
- if (!pix_fmts)
- return -EINVAL;
-
- /* store the pixel format in the device object */
- ret = mutex_lock_interruptible(&vpfe_dev->lock);
- if (ret)
- return ret;
-
- /* First detach any IRQ if currently attached */
- vpfe_detach_irq(vpfe_dev);
- vpfe_dev->fmt = *fmt;
- /* set image capture parameters in the ccdc */
- ret = vpfe_config_ccdc_image_format(vpfe_dev);
- mutex_unlock(&vpfe_dev->lock);
- return ret;
-}
-
-static int vpfe_try_fmt_vid_cap(struct file *file, void *priv,
- struct v4l2_format *f)
-{
- struct vpfe_device *vpfe_dev = video_drvdata(file);
- const struct vpfe_pixel_format *pix_fmts;
-
- v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_try_fmt_vid_cap\n");
-
- pix_fmts = vpfe_check_format(vpfe_dev, &f->fmt.pix);
- if (!pix_fmts)
- return -EINVAL;
- return 0;
-}
-
-/*
- * vpfe_get_subdev_input_index - Get subdev index and subdev input index for a
- * given app input index
- */
-static int vpfe_get_subdev_input_index(struct vpfe_device *vpfe_dev,
- int *subdev_index,
- int *subdev_input_index,
- int app_input_index)
-{
- struct vpfe_config *cfg = vpfe_dev->cfg;
- struct vpfe_subdev_info *sdinfo;
- int i, j = 0;
-
- for (i = 0; i < cfg->num_subdevs; i++) {
- sdinfo = &cfg->sub_devs[i];
- if (app_input_index < (j + sdinfo->num_inputs)) {
- *subdev_index = i;
- *subdev_input_index = app_input_index - j;
- return 0;
- }
- j += sdinfo->num_inputs;
- }
- return -EINVAL;
-}
-
-/*
- * vpfe_get_app_input - Get app input index for a given subdev input index
- * driver stores the input index of the current sub device and translate it
- * when application request the current input
- */
-static int vpfe_get_app_input_index(struct vpfe_device *vpfe_dev,
- int *app_input_index)
-{
- struct vpfe_config *cfg = vpfe_dev->cfg;
- struct vpfe_subdev_info *sdinfo;
- int i, j = 0;
-
- for (i = 0; i < cfg->num_subdevs; i++) {
- sdinfo = &cfg->sub_devs[i];
- if (!strcmp(sdinfo->name, vpfe_dev->current_subdev->name)) {
- if (vpfe_dev->current_input >= sdinfo->num_inputs)
- return -1;
- *app_input_index = j + vpfe_dev->current_input;
- return 0;
- }
- j += sdinfo->num_inputs;
- }
- return -EINVAL;
-}
-
-static int vpfe_enum_input(struct file *file, void *priv,
- struct v4l2_input *inp)
-{
- struct vpfe_device *vpfe_dev = video_drvdata(file);
- struct vpfe_subdev_info *sdinfo;
- int subdev, index ;
-
- v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_enum_input\n");
-
- if (vpfe_get_subdev_input_index(vpfe_dev,
- &subdev,
- &index,
- inp->index) < 0) {
- v4l2_err(&vpfe_dev->v4l2_dev, "input information not found for the subdev\n");
- return -EINVAL;
- }
- sdinfo = &vpfe_dev->cfg->sub_devs[subdev];
- *inp = sdinfo->inputs[index];
- return 0;
-}
-
-static int vpfe_g_input(struct file *file, void *priv, unsigned int *index)
-{
- struct vpfe_device *vpfe_dev = video_drvdata(file);
-
- v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_g_input\n");
-
- return vpfe_get_app_input_index(vpfe_dev, index);
-}
-
-
-static int vpfe_s_input(struct file *file, void *priv, unsigned int index)
-{
- struct vpfe_device *vpfe_dev = video_drvdata(file);
- struct v4l2_subdev *sd;
- struct vpfe_subdev_info *sdinfo;
- int subdev_index, inp_index;
- struct vpfe_route *route;
- u32 input, output;
- int ret;
-
- v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_s_input\n");
-
- ret = mutex_lock_interruptible(&vpfe_dev->lock);
- if (ret)
- return ret;
-
- /*
- * If streaming is started return device busy
- * error
- */
- if (vpfe_dev->started) {
- v4l2_err(&vpfe_dev->v4l2_dev, "Streaming is on\n");
- ret = -EBUSY;
- goto unlock_out;
- }
- ret = vpfe_get_subdev_input_index(vpfe_dev,
- &subdev_index,
- &inp_index,
- index);
- if (ret < 0) {
- v4l2_err(&vpfe_dev->v4l2_dev, "invalid input index\n");
- goto unlock_out;
- }
-
- sdinfo = &vpfe_dev->cfg->sub_devs[subdev_index];
- sd = vpfe_dev->sd[subdev_index];
- route = &sdinfo->routes[inp_index];
- if (route && sdinfo->can_route) {
- input = route->input;
- output = route->output;
- } else {
- input = 0;
- output = 0;
- }
-
- if (sd)
- ret = v4l2_subdev_call(sd, video, s_routing, input, output, 0);
-
- if (ret) {
- v4l2_err(&vpfe_dev->v4l2_dev,
- "vpfe_doioctl:error in setting input in decoder\n");
- ret = -EINVAL;
- goto unlock_out;
- }
- vpfe_dev->current_subdev = sdinfo;
- if (sd)
- vpfe_dev->v4l2_dev.ctrl_handler = sd->ctrl_handler;
- vpfe_dev->current_input = index;
- vpfe_dev->std_index = 0;
-
- /* set the bus/interface parameter for the sub device in ccdc */
- ret = ccdc_dev->hw_ops.set_hw_if_params(&sdinfo->ccdc_if_params);
- if (ret)
- goto unlock_out;
-
- /* set the default image parameters in the device */
- ret = vpfe_config_image_format(vpfe_dev,
- vpfe_standards[vpfe_dev->std_index].std_id);
-unlock_out:
- mutex_unlock(&vpfe_dev->lock);
- return ret;
-}
-
-static int vpfe_querystd(struct file *file, void *priv, v4l2_std_id *std_id)
-{
- struct vpfe_device *vpfe_dev = video_drvdata(file);
- struct vpfe_subdev_info *sdinfo;
- int ret;
-
- v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_querystd\n");
-
- ret = mutex_lock_interruptible(&vpfe_dev->lock);
- sdinfo = vpfe_dev->current_subdev;
- if (ret)
- return ret;
- /* Call querystd function of decoder device */
- ret = v4l2_device_call_until_err(&vpfe_dev->v4l2_dev, sdinfo->grp_id,
- video, querystd, std_id);
- mutex_unlock(&vpfe_dev->lock);
- return ret;
-}
-
-static int vpfe_s_std(struct file *file, void *priv, v4l2_std_id std_id)
-{
- struct vpfe_device *vpfe_dev = video_drvdata(file);
- struct vpfe_subdev_info *sdinfo;
- int ret;
-
- v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_s_std\n");
-
- /* Call decoder driver function to set the standard */
- ret = mutex_lock_interruptible(&vpfe_dev->lock);
- if (ret)
- return ret;
-
- sdinfo = vpfe_dev->current_subdev;
- /* If streaming is started, return device busy error */
- if (vpfe_dev->started) {
- v4l2_err(&vpfe_dev->v4l2_dev, "streaming is started\n");
- ret = -EBUSY;
- goto unlock_out;
- }
-
- ret = v4l2_device_call_until_err(&vpfe_dev->v4l2_dev, sdinfo->grp_id,
- video, s_std, std_id);
- if (ret < 0) {
- v4l2_err(&vpfe_dev->v4l2_dev, "Failed to set standard\n");
- goto unlock_out;
- }
- ret = vpfe_config_image_format(vpfe_dev, std_id);
-
-unlock_out:
- mutex_unlock(&vpfe_dev->lock);
- return ret;
-}
-
-static int vpfe_g_std(struct file *file, void *priv, v4l2_std_id *std_id)
-{
- struct vpfe_device *vpfe_dev = video_drvdata(file);
-
- v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_g_std\n");
-
- *std_id = vpfe_standards[vpfe_dev->std_index].std_id;
- return 0;
-}
-/*
- * Videobuf operations
- */
-static int vpfe_videobuf_setup(struct videobuf_queue *vq,
- unsigned int *count,
- unsigned int *size)
-{
- struct vpfe_fh *fh = vq->priv_data;
- struct vpfe_device *vpfe_dev = fh->vpfe_dev;
-
- v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_buffer_setup\n");
- *size = vpfe_dev->fmt.fmt.pix.sizeimage;
- if (vpfe_dev->memory == V4L2_MEMORY_MMAP &&
- vpfe_dev->fmt.fmt.pix.sizeimage > config_params.device_bufsize)
- *size = config_params.device_bufsize;
-
- if (*count < config_params.min_numbuffers)
- *count = config_params.min_numbuffers;
- v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev,
- "count=%d, size=%d\n", *count, *size);
- return 0;
-}
-
-static int vpfe_videobuf_prepare(struct videobuf_queue *vq,
- struct videobuf_buffer *vb,
- enum v4l2_field field)
-{
- struct vpfe_fh *fh = vq->priv_data;
- struct vpfe_device *vpfe_dev = fh->vpfe_dev;
- unsigned long addr;
- int ret;
-
- v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_buffer_prepare\n");
-
- /* If buffer is not initialized, initialize it */
- if (VIDEOBUF_NEEDS_INIT == vb->state) {
- vb->width = vpfe_dev->fmt.fmt.pix.width;
- vb->height = vpfe_dev->fmt.fmt.pix.height;
- vb->size = vpfe_dev->fmt.fmt.pix.sizeimage;
- vb->field = field;
-
- ret = videobuf_iolock(vq, vb, NULL);
- if (ret < 0)
- return ret;
-
- addr = videobuf_to_dma_contig(vb);
- /* Make sure user addresses are aligned to 32 bytes */
- if (!ALIGN(addr, 32))
- return -EINVAL;
-
- vb->state = VIDEOBUF_PREPARED;
- }
- return 0;
-}
-
-static void vpfe_videobuf_queue(struct videobuf_queue *vq,
- struct videobuf_buffer *vb)
-{
- /* Get the file handle object and device object */
- struct vpfe_fh *fh = vq->priv_data;
- struct vpfe_device *vpfe_dev = fh->vpfe_dev;
- unsigned long flags;
-
- v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_buffer_queue\n");
-
- /* add the buffer to the DMA queue */
- spin_lock_irqsave(&vpfe_dev->dma_queue_lock, flags);
- list_add_tail(&vb->queue, &vpfe_dev->dma_queue);
- spin_unlock_irqrestore(&vpfe_dev->dma_queue_lock, flags);
-
- /* Change state of the buffer */
- vb->state = VIDEOBUF_QUEUED;
-}
-
-static void vpfe_videobuf_release(struct videobuf_queue *vq,
- struct videobuf_buffer *vb)
-{
- struct vpfe_fh *fh = vq->priv_data;
- struct vpfe_device *vpfe_dev = fh->vpfe_dev;
- unsigned long flags;
-
- v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_videobuf_release\n");
-
- /*
- * We need to flush the buffer from the dma queue since
- * they are de-allocated
- */
- spin_lock_irqsave(&vpfe_dev->dma_queue_lock, flags);
- INIT_LIST_HEAD(&vpfe_dev->dma_queue);
- spin_unlock_irqrestore(&vpfe_dev->dma_queue_lock, flags);
- videobuf_dma_contig_free(vq, vb);
- vb->state = VIDEOBUF_NEEDS_INIT;
-}
-
-static const struct videobuf_queue_ops vpfe_videobuf_qops = {
- .buf_setup = vpfe_videobuf_setup,
- .buf_prepare = vpfe_videobuf_prepare,
- .buf_queue = vpfe_videobuf_queue,
- .buf_release = vpfe_videobuf_release,
-};
-
-/*
- * vpfe_reqbufs. currently support REQBUF only once opening
- * the device.
- */
-static int vpfe_reqbufs(struct file *file, void *priv,
- struct v4l2_requestbuffers *req_buf)
-{
- struct vpfe_device *vpfe_dev = video_drvdata(file);
- struct vpfe_fh *fh = file->private_data;
- int ret;
-
- v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_reqbufs\n");
-
- if (V4L2_BUF_TYPE_VIDEO_CAPTURE != req_buf->type) {
- v4l2_err(&vpfe_dev->v4l2_dev, "Invalid buffer type\n");
- return -EINVAL;
- }
-
- ret = mutex_lock_interruptible(&vpfe_dev->lock);
- if (ret)
- return ret;
-
- if (vpfe_dev->io_usrs != 0) {
- v4l2_err(&vpfe_dev->v4l2_dev, "Only one IO user allowed\n");
- ret = -EBUSY;
- goto unlock_out;
- }
-
- vpfe_dev->memory = req_buf->memory;
- videobuf_queue_dma_contig_init(&vpfe_dev->buffer_queue,
- &vpfe_videobuf_qops,
- vpfe_dev->pdev,
- &vpfe_dev->irqlock,
- req_buf->type,
- vpfe_dev->fmt.fmt.pix.field,
- sizeof(struct videobuf_buffer),
- fh, NULL);
-
- fh->io_allowed = 1;
- vpfe_dev->io_usrs = 1;
- INIT_LIST_HEAD(&vpfe_dev->dma_queue);
- ret = videobuf_reqbufs(&vpfe_dev->buffer_queue, req_buf);
-unlock_out:
- mutex_unlock(&vpfe_dev->lock);
- return ret;
-}
-
-static int vpfe_querybuf(struct file *file, void *priv,
- struct v4l2_buffer *buf)
-{
- struct vpfe_device *vpfe_dev = video_drvdata(file);
-
- v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_querybuf\n");
-
- if (V4L2_BUF_TYPE_VIDEO_CAPTURE != buf->type) {
- v4l2_err(&vpfe_dev->v4l2_dev, "Invalid buf type\n");
- return -EINVAL;
- }
-
- if (vpfe_dev->memory != V4L2_MEMORY_MMAP) {
- v4l2_err(&vpfe_dev->v4l2_dev, "Invalid memory\n");
- return -EINVAL;
- }
- /* Call videobuf_querybuf to get information */
- return videobuf_querybuf(&vpfe_dev->buffer_queue, buf);
-}
-
-static int vpfe_qbuf(struct file *file, void *priv,
- struct v4l2_buffer *p)
-{
- struct vpfe_device *vpfe_dev = video_drvdata(file);
- struct vpfe_fh *fh = file->private_data;
-
- v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_qbuf\n");
-
- if (V4L2_BUF_TYPE_VIDEO_CAPTURE != p->type) {
- v4l2_err(&vpfe_dev->v4l2_dev, "Invalid buf type\n");
- return -EINVAL;
- }
-
- /*
- * If this file handle is not allowed to do IO,
- * return error
- */
- if (!fh->io_allowed) {
- v4l2_err(&vpfe_dev->v4l2_dev, "fh->io_allowed\n");
- return -EACCES;
- }
- return videobuf_qbuf(&vpfe_dev->buffer_queue, p);
-}
-
-static int vpfe_dqbuf(struct file *file, void *priv,
- struct v4l2_buffer *buf)
-{
- struct vpfe_device *vpfe_dev = video_drvdata(file);
-
- v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_dqbuf\n");
-
- if (V4L2_BUF_TYPE_VIDEO_CAPTURE != buf->type) {
- v4l2_err(&vpfe_dev->v4l2_dev, "Invalid buf type\n");
- return -EINVAL;
- }
- return videobuf_dqbuf(&vpfe_dev->buffer_queue,
- buf, file->f_flags & O_NONBLOCK);
-}
-
-/*
- * vpfe_calculate_offsets : This function calculates buffers offset
- * for top and bottom field
- */
-static void vpfe_calculate_offsets(struct vpfe_device *vpfe_dev)
-{
- struct v4l2_rect image_win;
-
- v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_calculate_offsets\n");
-
- ccdc_dev->hw_ops.get_image_window(&image_win);
- vpfe_dev->field_off = image_win.height * image_win.width;
-}
-
-/* vpfe_start_ccdc_capture: start streaming in ccdc/isif */
-static void vpfe_start_ccdc_capture(struct vpfe_device *vpfe_dev)
-{
- ccdc_dev->hw_ops.enable(1);
- if (ccdc_dev->hw_ops.enable_out_to_sdram)
- ccdc_dev->hw_ops.enable_out_to_sdram(1);
- vpfe_dev->started = 1;
-}
-
-/*
- * vpfe_streamon. Assume the DMA queue is not empty.
- * application is expected to call QBUF before calling
- * this ioctl. If not, driver returns error
- */
-static int vpfe_streamon(struct file *file, void *priv,
- enum v4l2_buf_type buf_type)
-{
- struct vpfe_device *vpfe_dev = video_drvdata(file);
- struct vpfe_fh *fh = file->private_data;
- struct vpfe_subdev_info *sdinfo;
- unsigned long addr;
- int ret;
-
- v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_streamon\n");
-
- if (V4L2_BUF_TYPE_VIDEO_CAPTURE != buf_type) {
- v4l2_err(&vpfe_dev->v4l2_dev, "Invalid buf type\n");
- return -EINVAL;
- }
-
- /* If file handle is not allowed IO, return error */
- if (!fh->io_allowed) {
- v4l2_err(&vpfe_dev->v4l2_dev, "fh->io_allowed\n");
- return -EACCES;
- }
-
- sdinfo = vpfe_dev->current_subdev;
- ret = v4l2_device_call_until_err(&vpfe_dev->v4l2_dev, sdinfo->grp_id,
- video, s_stream, 1);
-
- if (ret && (ret != -ENOIOCTLCMD)) {
- v4l2_err(&vpfe_dev->v4l2_dev, "stream on failed in subdev\n");
- return -EINVAL;
- }
-
- /* If buffer queue is empty, return error */
- if (list_empty(&vpfe_dev->buffer_queue.stream)) {
- v4l2_err(&vpfe_dev->v4l2_dev, "buffer queue is empty\n");
- return -EIO;
- }
-
- /* Call videobuf_streamon to start streaming * in videobuf */
- ret = videobuf_streamon(&vpfe_dev->buffer_queue);
- if (ret)
- return ret;
-
-
- ret = mutex_lock_interruptible(&vpfe_dev->lock);
- if (ret)
- goto streamoff;
- /* Get the next frame from the buffer queue */
- vpfe_dev->next_frm = list_entry(vpfe_dev->dma_queue.next,
- struct videobuf_buffer, queue);
- vpfe_dev->cur_frm = vpfe_dev->next_frm;
- /* Remove buffer from the buffer queue */
- list_del(&vpfe_dev->cur_frm->queue);
- /* Mark state of the current frame to active */
- vpfe_dev->cur_frm->state = VIDEOBUF_ACTIVE;
- /* Initialize field_id and started member */
- vpfe_dev->field_id = 0;
- addr = videobuf_to_dma_contig(vpfe_dev->cur_frm);
-
- /* Calculate field offset */
- vpfe_calculate_offsets(vpfe_dev);
-
- if (vpfe_attach_irq(vpfe_dev) < 0) {
- v4l2_err(&vpfe_dev->v4l2_dev,
- "Error in attaching interrupt handle\n");
- ret = -EFAULT;
- goto unlock_out;
- }
- if (ccdc_dev->hw_ops.configure() < 0) {
- v4l2_err(&vpfe_dev->v4l2_dev,
- "Error in configuring ccdc\n");
- ret = -EINVAL;
- goto unlock_out;
- }
- ccdc_dev->hw_ops.setfbaddr((unsigned long)(addr));
- vpfe_start_ccdc_capture(vpfe_dev);
- mutex_unlock(&vpfe_dev->lock);
- return ret;
-unlock_out:
- mutex_unlock(&vpfe_dev->lock);
-streamoff:
- videobuf_streamoff(&vpfe_dev->buffer_queue);
- return ret;
-}
-
-static int vpfe_streamoff(struct file *file, void *priv,
- enum v4l2_buf_type buf_type)
-{
- struct vpfe_device *vpfe_dev = video_drvdata(file);
- struct vpfe_fh *fh = file->private_data;
- struct vpfe_subdev_info *sdinfo;
- int ret;
-
- v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_streamoff\n");
-
- if (V4L2_BUF_TYPE_VIDEO_CAPTURE != buf_type) {
- v4l2_err(&vpfe_dev->v4l2_dev, "Invalid buf type\n");
- return -EINVAL;
- }
-
- /* If io is allowed for this file handle, return error */
- if (!fh->io_allowed) {
- v4l2_err(&vpfe_dev->v4l2_dev, "fh->io_allowed\n");
- return -EACCES;
- }
-
- /* If streaming is not started, return error */
- if (!vpfe_dev->started) {
- v4l2_err(&vpfe_dev->v4l2_dev, "device started\n");
- return -EINVAL;
- }
-
- ret = mutex_lock_interruptible(&vpfe_dev->lock);
- if (ret)
- return ret;
-
- vpfe_stop_ccdc_capture(vpfe_dev);
- vpfe_detach_irq(vpfe_dev);
-
- sdinfo = vpfe_dev->current_subdev;
- ret = v4l2_device_call_until_err(&vpfe_dev->v4l2_dev, sdinfo->grp_id,
- video, s_stream, 0);
-
- if (ret && (ret != -ENOIOCTLCMD))
- v4l2_err(&vpfe_dev->v4l2_dev, "stream off failed in subdev\n");
- ret = videobuf_streamoff(&vpfe_dev->buffer_queue);
- mutex_unlock(&vpfe_dev->lock);
- return ret;
-}
-
-static int vpfe_g_pixelaspect(struct file *file, void *priv,
- int type, struct v4l2_fract *f)
-{
- struct vpfe_device *vpfe_dev = video_drvdata(file);
-
- v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_g_pixelaspect\n");
-
- if (type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
- return -EINVAL;
- /* If std_index is invalid, then just return (== 1:1 aspect) */
- if (vpfe_dev->std_index >= ARRAY_SIZE(vpfe_standards))
- return 0;
-
- *f = vpfe_standards[vpfe_dev->std_index].pixelaspect;
- return 0;
-}
-
-static int vpfe_g_selection(struct file *file, void *priv,
- struct v4l2_selection *sel)
-{
- struct vpfe_device *vpfe_dev = video_drvdata(file);
-
- v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_g_selection\n");
-
- if (sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
- return -EINVAL;
-
- switch (sel->target) {
- case V4L2_SEL_TGT_CROP:
- sel->r = vpfe_dev->crop;
- break;
- case V4L2_SEL_TGT_CROP_DEFAULT:
- case V4L2_SEL_TGT_CROP_BOUNDS:
- sel->r.width = vpfe_standards[vpfe_dev->std_index].width;
- sel->r.height = vpfe_standards[vpfe_dev->std_index].height;
- break;
- default:
- return -EINVAL;
- }
- return 0;
-}
-
-static int vpfe_s_selection(struct file *file, void *priv,
- struct v4l2_selection *sel)
-{
- struct vpfe_device *vpfe_dev = video_drvdata(file);
- struct v4l2_rect rect = sel->r;
- int ret;
-
- v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_s_selection\n");
-
- if (sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE ||
- sel->target != V4L2_SEL_TGT_CROP)
- return -EINVAL;
-
- if (vpfe_dev->started) {
- /* make sure streaming is not started */
- v4l2_err(&vpfe_dev->v4l2_dev,
- "Cannot change crop when streaming is ON\n");
- return -EBUSY;
- }
-
- ret = mutex_lock_interruptible(&vpfe_dev->lock);
- if (ret)
- return ret;
-
- if (rect.top < 0 || rect.left < 0) {
- v4l2_err(&vpfe_dev->v4l2_dev,
- "doesn't support negative values for top & left\n");
- ret = -EINVAL;
- goto unlock_out;
- }
-
- /* adjust the width to 16 pixel boundary */
- rect.width = ((rect.width + 15) & ~0xf);
-
- /* make sure parameters are valid */
- if ((rect.left + rect.width >
- vpfe_dev->std_info.active_pixels) ||
- (rect.top + rect.height >
- vpfe_dev->std_info.active_lines)) {
- v4l2_err(&vpfe_dev->v4l2_dev, "Error in S_SELECTION params\n");
- ret = -EINVAL;
- goto unlock_out;
- }
- ccdc_dev->hw_ops.set_image_window(&rect);
- vpfe_dev->fmt.fmt.pix.width = rect.width;
- vpfe_dev->fmt.fmt.pix.height = rect.height;
- vpfe_dev->fmt.fmt.pix.bytesperline =
- ccdc_dev->hw_ops.get_line_length();
- vpfe_dev->fmt.fmt.pix.sizeimage =
- vpfe_dev->fmt.fmt.pix.bytesperline *
- vpfe_dev->fmt.fmt.pix.height;
- vpfe_dev->crop = rect;
- sel->r = rect;
-unlock_out:
- mutex_unlock(&vpfe_dev->lock);
- return ret;
-}
-
-/* vpfe capture ioctl operations */
-static const struct v4l2_ioctl_ops vpfe_ioctl_ops = {
- .vidioc_querycap = vpfe_querycap,
- .vidioc_g_fmt_vid_cap = vpfe_g_fmt_vid_cap,
- .vidioc_enum_fmt_vid_cap = vpfe_enum_fmt_vid_cap,
- .vidioc_s_fmt_vid_cap = vpfe_s_fmt_vid_cap,
- .vidioc_try_fmt_vid_cap = vpfe_try_fmt_vid_cap,
- .vidioc_enum_input = vpfe_enum_input,
- .vidioc_g_input = vpfe_g_input,
- .vidioc_s_input = vpfe_s_input,
- .vidioc_querystd = vpfe_querystd,
- .vidioc_s_std = vpfe_s_std,
- .vidioc_g_std = vpfe_g_std,
- .vidioc_reqbufs = vpfe_reqbufs,
- .vidioc_querybuf = vpfe_querybuf,
- .vidioc_qbuf = vpfe_qbuf,
- .vidioc_dqbuf = vpfe_dqbuf,
- .vidioc_streamon = vpfe_streamon,
- .vidioc_streamoff = vpfe_streamoff,
- .vidioc_g_pixelaspect = vpfe_g_pixelaspect,
- .vidioc_g_selection = vpfe_g_selection,
- .vidioc_s_selection = vpfe_s_selection,
-};
-
-static struct vpfe_device *vpfe_initialize(void)
-{
- struct vpfe_device *vpfe_dev;
-
- /* Default number of buffers should be 3 */
- if ((numbuffers > 0) &&
- (numbuffers < config_params.min_numbuffers))
- numbuffers = config_params.min_numbuffers;
-
- /*
- * Set buffer size to min buffers size if invalid buffer size is
- * given
- */
- if (bufsize < config_params.min_bufsize)
- bufsize = config_params.min_bufsize;
-
- config_params.numbuffers = numbuffers;
-
- if (numbuffers)
- config_params.device_bufsize = bufsize;
-
- /* Allocate memory for device objects */
- vpfe_dev = kzalloc(sizeof(*vpfe_dev), GFP_KERNEL);
-
- return vpfe_dev;
-}
-
-/*
- * vpfe_probe : This function creates device entries by register
- * itself to the V4L2 driver and initializes fields of each
- * device objects
- */
-static int vpfe_probe(struct platform_device *pdev)
-{
- struct vpfe_subdev_info *sdinfo;
- struct vpfe_config *vpfe_cfg;
- struct resource *res1;
- struct vpfe_device *vpfe_dev;
- struct i2c_adapter *i2c_adap;
- struct video_device *vfd;
- int ret, i, j;
- int num_subdevs = 0;
-
- /* Get the pointer to the device object */
- vpfe_dev = vpfe_initialize();
-
- if (!vpfe_dev) {
- v4l2_err(pdev->dev.driver,
- "Failed to allocate memory for vpfe_dev\n");
- return -ENOMEM;
- }
-
- vpfe_dev->pdev = &pdev->dev;
-
- if (!pdev->dev.platform_data) {
- v4l2_err(pdev->dev.driver, "Unable to get vpfe config\n");
- ret = -ENODEV;
- goto probe_free_dev_mem;
- }
-
- vpfe_cfg = pdev->dev.platform_data;
- vpfe_dev->cfg = vpfe_cfg;
- if (!vpfe_cfg->ccdc || !vpfe_cfg->card_name || !vpfe_cfg->sub_devs) {
- v4l2_err(pdev->dev.driver, "null ptr in vpfe_cfg\n");
- ret = -ENOENT;
- goto probe_free_dev_mem;
- }
-
- /* Allocate memory for ccdc configuration */
- ccdc_cfg = kmalloc(sizeof(*ccdc_cfg), GFP_KERNEL);
- if (!ccdc_cfg) {
- ret = -ENOMEM;
- goto probe_free_dev_mem;
- }
-
- mutex_lock(&ccdc_lock);
-
- strscpy(ccdc_cfg->name, vpfe_cfg->ccdc, sizeof(ccdc_cfg->name));
- /* Get VINT0 irq resource */
- res1 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
- if (!res1) {
- v4l2_err(pdev->dev.driver,
- "Unable to get interrupt for VINT0\n");
- ret = -ENODEV;
- goto probe_free_ccdc_cfg_mem;
- }
- vpfe_dev->ccdc_irq0 = res1->start;
-
- /* Get VINT1 irq resource */
- res1 = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
- if (!res1) {
- v4l2_err(pdev->dev.driver,
- "Unable to get interrupt for VINT1\n");
- ret = -ENODEV;
- goto probe_free_ccdc_cfg_mem;
- }
- vpfe_dev->ccdc_irq1 = res1->start;
-
- ret = request_irq(vpfe_dev->ccdc_irq0, vpfe_isr, 0,
- "vpfe_capture0", vpfe_dev);
-
- if (0 != ret) {
- v4l2_err(pdev->dev.driver, "Unable to request interrupt\n");
- goto probe_free_ccdc_cfg_mem;
- }
-
- vfd = &vpfe_dev->video_dev;
- /* Initialize field of video device */
- vfd->release = video_device_release_empty;
- vfd->fops = &vpfe_fops;
- vfd->ioctl_ops = &vpfe_ioctl_ops;
- vfd->tvnorms = 0;
- vfd->v4l2_dev = &vpfe_dev->v4l2_dev;
- vfd->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
- snprintf(vfd->name, sizeof(vfd->name),
- "%s_V%d.%d.%d",
- CAPTURE_DRV_NAME,
- (VPFE_CAPTURE_VERSION_CODE >> 16) & 0xff,
- (VPFE_CAPTURE_VERSION_CODE >> 8) & 0xff,
- (VPFE_CAPTURE_VERSION_CODE) & 0xff);
-
- ret = v4l2_device_register(&pdev->dev, &vpfe_dev->v4l2_dev);
- if (ret) {
- v4l2_err(pdev->dev.driver,
- "Unable to register v4l2 device.\n");
- goto probe_out_release_irq;
- }
- v4l2_info(&vpfe_dev->v4l2_dev, "v4l2 device registered\n");
- spin_lock_init(&vpfe_dev->irqlock);
- spin_lock_init(&vpfe_dev->dma_queue_lock);
- mutex_init(&vpfe_dev->lock);
-
- /* Initialize field of the device objects */
- vpfe_dev->numbuffers = config_params.numbuffers;
-
- /* register video device */
- v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev,
- "trying to register vpfe device.\n");
- v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev,
- "video_dev=%p\n", &vpfe_dev->video_dev);
- vpfe_dev->fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
- ret = video_register_device(&vpfe_dev->video_dev,
- VFL_TYPE_VIDEO, -1);
-
- if (ret) {
- v4l2_err(pdev->dev.driver,
- "Unable to register video device.\n");
- goto probe_out_v4l2_unregister;
- }
-
- v4l2_info(&vpfe_dev->v4l2_dev, "video device registered\n");
- /* set the driver data in platform device */
- platform_set_drvdata(pdev, vpfe_dev);
- /* set driver private data */
- video_set_drvdata(&vpfe_dev->video_dev, vpfe_dev);
- i2c_adap = i2c_get_adapter(vpfe_cfg->i2c_adapter_id);
- num_subdevs = vpfe_cfg->num_subdevs;
- vpfe_dev->sd = kmalloc_array(num_subdevs,
- sizeof(*vpfe_dev->sd),
- GFP_KERNEL);
- if (!vpfe_dev->sd) {
- ret = -ENOMEM;
- goto probe_out_video_unregister;
- }
-
- for (i = 0; i < num_subdevs; i++) {
- struct v4l2_input *inps;
-
- sdinfo = &vpfe_cfg->sub_devs[i];
-
- /* Load up the subdevice */
- vpfe_dev->sd[i] =
- v4l2_i2c_new_subdev_board(&vpfe_dev->v4l2_dev,
- i2c_adap,
- &sdinfo->board_info,
- NULL);
- if (vpfe_dev->sd[i]) {
- v4l2_info(&vpfe_dev->v4l2_dev,
- "v4l2 sub device %s registered\n",
- sdinfo->name);
- vpfe_dev->sd[i]->grp_id = sdinfo->grp_id;
- /* update tvnorms from the sub devices */
- for (j = 0; j < sdinfo->num_inputs; j++) {
- inps = &sdinfo->inputs[j];
- vfd->tvnorms |= inps->std;
- }
- } else {
- v4l2_info(&vpfe_dev->v4l2_dev,
- "v4l2 sub device %s register fails\n",
- sdinfo->name);
- ret = -ENXIO;
- goto probe_sd_out;
- }
- }
-
- /* set first sub device as current one */
- vpfe_dev->current_subdev = &vpfe_cfg->sub_devs[0];
- vpfe_dev->v4l2_dev.ctrl_handler = vpfe_dev->sd[0]->ctrl_handler;
-
- /* We have at least one sub device to work with */
- mutex_unlock(&ccdc_lock);
- return 0;
-
-probe_sd_out:
- kfree(vpfe_dev->sd);
-probe_out_video_unregister:
- video_unregister_device(&vpfe_dev->video_dev);
-probe_out_v4l2_unregister:
- v4l2_device_unregister(&vpfe_dev->v4l2_dev);
-probe_out_release_irq:
- free_irq(vpfe_dev->ccdc_irq0, vpfe_dev);
-probe_free_ccdc_cfg_mem:
- kfree(ccdc_cfg);
- mutex_unlock(&ccdc_lock);
-probe_free_dev_mem:
- kfree(vpfe_dev);
- return ret;
-}
-
-/*
- * vpfe_remove : It un-register device from V4L2 driver
- */
-static int vpfe_remove(struct platform_device *pdev)
-{
- struct vpfe_device *vpfe_dev = platform_get_drvdata(pdev);
-
- v4l2_info(pdev->dev.driver, "vpfe_remove\n");
-
- free_irq(vpfe_dev->ccdc_irq0, vpfe_dev);
- kfree(vpfe_dev->sd);
- v4l2_device_unregister(&vpfe_dev->v4l2_dev);
- video_unregister_device(&vpfe_dev->video_dev);
- kfree(vpfe_dev);
- kfree(ccdc_cfg);
- return 0;
-}
-
-static int vpfe_suspend(struct device *dev)
-{
- return 0;
-}
-
-static int vpfe_resume(struct device *dev)
-{
- return 0;
-}
-
-static const struct dev_pm_ops vpfe_dev_pm_ops = {
- .suspend = vpfe_suspend,
- .resume = vpfe_resume,
-};
-
-static struct platform_driver vpfe_driver = {
- .driver = {
- .name = CAPTURE_DRV_NAME,
- .pm = &vpfe_dev_pm_ops,
- },
- .probe = vpfe_probe,
- .remove = vpfe_remove,
-};
-
-module_platform_driver(vpfe_driver);
diff --git a/include/media/davinci/vpfe_capture.h b/include/media/davinci/vpfe_capture.h
deleted file mode 100644
index 4ad53031e2f7..000000000000
--- a/include/media/davinci/vpfe_capture.h
+++ /dev/null
@@ -1,177 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright (C) 2008-2009 Texas Instruments Inc
- */
-
-#ifndef _VPFE_CAPTURE_H
-#define _VPFE_CAPTURE_H
-
-#ifdef __KERNEL__
-
-/* Header files */
-#include <media/v4l2-dev.h>
-#include <linux/videodev2.h>
-#include <linux/clk.h>
-#include <linux/i2c.h>
-#include <media/v4l2-fh.h>
-#include <media/v4l2-ioctl.h>
-#include <media/v4l2-device.h>
-#include <media/videobuf-dma-contig.h>
-#include <media/davinci/vpfe_types.h>
-
-#define VPFE_CAPTURE_NUM_DECODERS 5
-
-/* Macros */
-#define VPFE_MAJOR_RELEASE 0
-#define VPFE_MINOR_RELEASE 0
-#define VPFE_BUILD 1
-#define VPFE_CAPTURE_VERSION_CODE ((VPFE_MAJOR_RELEASE << 16) | \
- (VPFE_MINOR_RELEASE << 8) | \
- VPFE_BUILD)
-
-#define CAPTURE_DRV_NAME "vpfe-capture"
-
-struct vpfe_pixel_format {
- u32 pixelformat;
- /* bytes per pixel */
- int bpp;
-};
-
-struct vpfe_std_info {
- int active_pixels;
- int active_lines;
- /* current frame format */
- int frame_format;
-};
-
-struct vpfe_route {
- u32 input;
- u32 output;
-};
-
-struct vpfe_subdev_info {
- /* Sub device name */
- char name[32];
- /* Sub device group id */
- int grp_id;
- /* Number of inputs supported */
- int num_inputs;
- /* inputs available at the sub device */
- struct v4l2_input *inputs;
- /* Sub dev routing information for each input */
- struct vpfe_route *routes;
- /* check if sub dev supports routing */
- int can_route;
- /* ccdc bus/interface configuration */
- struct vpfe_hw_if_param ccdc_if_params;
- /* i2c subdevice board info */
- struct i2c_board_info board_info;
-};
-
-struct vpfe_config {
- /* Number of sub devices connected to vpfe */
- int num_subdevs;
- /* i2c bus adapter no */
- int i2c_adapter_id;
- /* information about each subdev */
- struct vpfe_subdev_info *sub_devs;
- /* evm card info */
- char *card_name;
- /* ccdc name */
- char *ccdc;
- /* vpfe clock */
- struct clk *vpssclk;
- struct clk *slaveclk;
- /* Function for Clearing the interrupt */
- void (*clr_intr)(int vdint);
-};
-
-struct vpfe_device {
- /* V4l2 specific parameters */
- /* Identifies video device for this channel */
- struct video_device video_dev;
- /* sub devices */
- struct v4l2_subdev **sd;
- /* vpfe cfg */
- struct vpfe_config *cfg;
- /* V4l2 device */
- struct v4l2_device v4l2_dev;
- /* parent device */
- struct device *pdev;
- /* number of open instances of the channel */
- u32 usrs;
- /* Indicates id of the field which is being displayed */
- u32 field_id;
- /* flag to indicate whether decoder is initialized */
- u8 initialized;
- /* current interface type */
- struct vpfe_hw_if_param vpfe_if_params;
- /* ptr to currently selected sub device */
- struct vpfe_subdev_info *current_subdev;
- /* current input at the sub device */
- int current_input;
- /* Keeps track of the information about the standard */
- struct vpfe_std_info std_info;
- /* std index into std table */
- int std_index;
- /* CCDC IRQs used when CCDC/ISIF output to SDRAM */
- unsigned int ccdc_irq0;
- unsigned int ccdc_irq1;
- /* number of buffers in fbuffers */
- u32 numbuffers;
- /* List of buffer pointers for storing frames */
- u8 *fbuffers[VIDEO_MAX_FRAME];
- /* Pointer pointing to current v4l2_buffer */
- struct videobuf_buffer *cur_frm;
- /* Pointer pointing to next v4l2_buffer */
- struct videobuf_buffer *next_frm;
- /*
- * This field keeps track of type of buffer exchange mechanism
- * user has selected
- */
- enum v4l2_memory memory;
- /* Used to store pixel format */
- struct v4l2_format fmt;
- /*
- * used when IMP is chained to store the crop window which
- * is different from the image window
- */
- struct v4l2_rect crop;
- /* Buffer queue used in video-buf */
- struct videobuf_queue buffer_queue;
- /* Queue of filled frames */
- struct list_head dma_queue;
- /* Used in video-buf */
- spinlock_t irqlock;
- /* IRQ lock for DMA queue */
- spinlock_t dma_queue_lock;
- /* lock used to access this structure */
- struct mutex lock;
- /* number of users performing IO */
- u32 io_usrs;
- /* Indicates whether streaming started */
- u8 started;
- /*
- * offset where second field starts from the starting of the
- * buffer for field separated YCbCr formats
- */
- u32 field_off;
-};
-
-/* File handle structure */
-struct vpfe_fh {
- struct v4l2_fh fh;
- struct vpfe_device *vpfe_dev;
- /* Indicates whether this file handle is doing IO */
- u8 io_allowed;
-};
-
-struct vpfe_config_params {
- u8 min_numbuffers;
- u8 numbuffers;
- u32 min_bufsize;
- u32 device_bufsize;
-};
-
-#endif /* End of __KERNEL__ */
-#endif /* _DAVINCI_VPFE_H */
--
2.29.2
^ permalink raw reply related [flat|nested] 48+ messages in thread* Re: [PATCH 13/14] staging: media: remove davinci vpfe_capture driver
2022-10-19 15:29 ` [PATCH 13/14] staging: media: remove davinci vpfe_capture driver Arnd Bergmann
@ 2022-10-20 15:39 ` Greg Kroah-Hartman
2022-10-24 11:01 ` Hans Verkuil
2022-10-25 22:21 ` Lad, Prabhakar
2 siblings, 0 replies; 48+ messages in thread
From: Greg Kroah-Hartman @ 2022-10-20 15:39 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Sekhar Nori, Bartosz Golaszewski, linux-arm-kernel,
Mauro Carvalho Chehab, Lad, Prabhakar, linux-kernel,
Kevin Hilman, Arnd Bergmann, linux-media, linux-staging
On Wed, Oct 19, 2022 at 05:29:39PM +0200, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> This driver was for the davinci dm644x and dm3xx platforms that are
> now removed from the kernel, so there are no more users.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 13/14] staging: media: remove davinci vpfe_capture driver
2022-10-19 15:29 ` [PATCH 13/14] staging: media: remove davinci vpfe_capture driver Arnd Bergmann
2022-10-20 15:39 ` Greg Kroah-Hartman
@ 2022-10-24 11:01 ` Hans Verkuil
2022-10-25 22:21 ` Lad, Prabhakar
2 siblings, 0 replies; 48+ messages in thread
From: Hans Verkuil @ 2022-10-24 11:01 UTC (permalink / raw)
To: Arnd Bergmann, Sekhar Nori, Bartosz Golaszewski,
linux-arm-kernel, Mauro Carvalho Chehab, Greg Kroah-Hartman, Lad,
Prabhakar
Cc: linux-kernel, Kevin Hilman, Arnd Bergmann, linux-media, linux-staging
Hi Arnd,
On 10/19/22 17:29, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> This driver was for the davinci dm644x and dm3xx platforms that are
> now removed from the kernel, so there are no more users.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
As discussed on irc, it is best if you merge this to due dependencies on
arch/arm/mach-davinci/davinci.h.
Note that there is one more reference to vpfe_capture.h:
Documentation/userspace-api/ioctl/ioctl-number.rst:'V' C0 media/davinci/vpfe_capture.h conflict!
Feel free to fold that in this patch, or make a separate patch removing it.
If you make a separate patch, then you can add my Acked-by for that change.
Regards,
Hans
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 13/14] staging: media: remove davinci vpfe_capture driver
2022-10-19 15:29 ` [PATCH 13/14] staging: media: remove davinci vpfe_capture driver Arnd Bergmann
2022-10-20 15:39 ` Greg Kroah-Hartman
2022-10-24 11:01 ` Hans Verkuil
@ 2022-10-25 22:21 ` Lad, Prabhakar
2 siblings, 0 replies; 48+ messages in thread
From: Lad, Prabhakar @ 2022-10-25 22:21 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Sekhar Nori, Bartosz Golaszewski, linux-arm-kernel,
Mauro Carvalho Chehab, Greg Kroah-Hartman, linux-kernel,
Kevin Hilman, Arnd Bergmann, linux-media, linux-staging
On Wed, Oct 19, 2022 at 4:40 PM Arnd Bergmann <arnd@kernel.org> wrote:>
> From: Arnd Bergmann <arnd@arndb.de>
>
> This driver was for the davinci dm644x and dm3xx platforms that are
> now removed from the kernel, so there are no more users.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
> MAINTAINERS | 1 -
> drivers/staging/media/Kconfig | 1 -
> drivers/staging/media/Makefile | 1 -
> .../media/deprecated/vpfe_capture/Kconfig | 58 -
> .../media/deprecated/vpfe_capture/Makefile | 4 -
> .../media/deprecated/vpfe_capture/TODO | 7 -
> .../deprecated/vpfe_capture/ccdc_hw_device.h | 80 -
> .../deprecated/vpfe_capture/dm355_ccdc.c | 934 --------
> .../deprecated/vpfe_capture/dm355_ccdc.h | 308 ---
> .../deprecated/vpfe_capture/dm355_ccdc_regs.h | 297 ---
> .../deprecated/vpfe_capture/dm644x_ccdc.c | 879 --------
> .../deprecated/vpfe_capture/dm644x_ccdc.h | 171 --
> .../vpfe_capture/dm644x_ccdc_regs.h | 140 --
> .../media/deprecated/vpfe_capture/isif.c | 1127 ----------
> .../media/deprecated/vpfe_capture/isif.h | 518 -----
> .../media/deprecated/vpfe_capture/isif_regs.h | 256 ---
> .../deprecated/vpfe_capture/vpfe_capture.c | 1902 -----------------
> include/media/davinci/vpfe_capture.h | 177 --
> 18 files changed, 6861 deletions(-)
> delete mode 100644 drivers/staging/media/deprecated/vpfe_capture/Kconfig
> delete mode 100644 drivers/staging/media/deprecated/vpfe_capture/Makefile
> delete mode 100644 drivers/staging/media/deprecated/vpfe_capture/TODO
> delete mode 100644 drivers/staging/media/deprecated/vpfe_capture/ccdc_hw_device.h
> delete mode 100644 drivers/staging/media/deprecated/vpfe_capture/dm355_ccdc.c
> delete mode 100644 drivers/staging/media/deprecated/vpfe_capture/dm355_ccdc.h
> delete mode 100644 drivers/staging/media/deprecated/vpfe_capture/dm355_ccdc_regs.h
> delete mode 100644 drivers/staging/media/deprecated/vpfe_capture/dm644x_ccdc.c
> delete mode 100644 drivers/staging/media/deprecated/vpfe_capture/dm644x_ccdc.h
> delete mode 100644 drivers/staging/media/deprecated/vpfe_capture/dm644x_ccdc_regs.h
> delete mode 100644 drivers/staging/media/deprecated/vpfe_capture/isif.c
> delete mode 100644 drivers/staging/media/deprecated/vpfe_capture/isif.h
> delete mode 100644 drivers/staging/media/deprecated/vpfe_capture/isif_regs.h
> delete mode 100644 drivers/staging/media/deprecated/vpfe_capture/vpfe_capture.c
> delete mode 100644 include/media/davinci/vpfe_capture.h
>
Acked-by: Lad Prabhakar <prabhakar.csengg@gmail.com>
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH 14/14] media: davinci: remove vpbe support
2022-10-19 15:29 [PATCH 00/14] ARM: remove unused davinci board & drivers Arnd Bergmann
` (12 preceding siblings ...)
2022-10-19 15:29 ` [PATCH 13/14] staging: media: remove davinci vpfe_capture driver Arnd Bergmann
@ 2022-10-19 15:29 ` Arnd Bergmann
2022-10-24 11:03 ` Hans Verkuil
2022-10-25 22:22 ` Lad, Prabhakar
2022-10-19 15:39 ` [PATCH 00/14] ARM: remove unused davinci board & drivers Marc Zyngier
` (2 subsequent siblings)
16 siblings, 2 replies; 48+ messages in thread
From: Arnd Bergmann @ 2022-10-19 15:29 UTC (permalink / raw)
To: Sekhar Nori, Bartosz Golaszewski, linux-arm-kernel,
Mauro Carvalho Chehab, Lad, Prabhakar
Cc: linux-kernel, Kevin Hilman, Arnd Bergmann, Hans Verkuil, linux-media
From: Arnd Bergmann <arnd@arndb.de>
The davinci dm3xx/dm644x platforms are gone now, and the remaining
da8xx platforms do not use the vpbe driver, so the driver can be
removed as well.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
.../admin-guide/media/davinci-vpbe.rst | 65 -
.../admin-guide/media/platform-cardlist.rst | 1 -
.../admin-guide/media/v4l-drivers.rst | 1 -
.../media/drivers/davinci-vpbe-devel.rst | 39 -
.../driver-api/media/drivers/index.rst | 1 -
drivers/media/platform/ti/davinci/Kconfig | 16 -
drivers/media/platform/ti/davinci/Makefile | 3 -
drivers/media/platform/ti/davinci/vpbe.c | 840 ---------
.../media/platform/ti/davinci/vpbe_display.c | 1510 ----------------
drivers/media/platform/ti/davinci/vpbe_osd.c | 1582 -----------------
.../media/platform/ti/davinci/vpbe_osd_regs.h | 352 ----
drivers/media/platform/ti/davinci/vpbe_venc.c | 676 -------
.../platform/ti/davinci/vpbe_venc_regs.h | 165 --
drivers/media/platform/ti/davinci/vpss.c | 529 ------
include/media/davinci/vpbe.h | 184 --
include/media/davinci/vpbe_display.h | 122 --
include/media/davinci/vpbe_osd.h | 382 ----
include/media/davinci/vpbe_types.h | 74 -
include/media/davinci/vpbe_venc.h | 37 -
include/media/davinci/vpss.h | 111 --
20 files changed, 6690 deletions(-)
delete mode 100644 Documentation/admin-guide/media/davinci-vpbe.rst
delete mode 100644 Documentation/driver-api/media/drivers/davinci-vpbe-devel.rst
delete mode 100644 drivers/media/platform/ti/davinci/vpbe.c
delete mode 100644 drivers/media/platform/ti/davinci/vpbe_display.c
delete mode 100644 drivers/media/platform/ti/davinci/vpbe_osd.c
delete mode 100644 drivers/media/platform/ti/davinci/vpbe_osd_regs.h
delete mode 100644 drivers/media/platform/ti/davinci/vpbe_venc.c
delete mode 100644 drivers/media/platform/ti/davinci/vpbe_venc_regs.h
delete mode 100644 drivers/media/platform/ti/davinci/vpss.c
delete mode 100644 include/media/davinci/vpbe.h
delete mode 100644 include/media/davinci/vpbe_display.h
delete mode 100644 include/media/davinci/vpbe_osd.h
delete mode 100644 include/media/davinci/vpbe_types.h
delete mode 100644 include/media/davinci/vpbe_venc.h
delete mode 100644 include/media/davinci/vpss.h
diff --git a/Documentation/admin-guide/media/davinci-vpbe.rst b/Documentation/admin-guide/media/davinci-vpbe.rst
deleted file mode 100644
index 9e6360fd02db..000000000000
--- a/Documentation/admin-guide/media/davinci-vpbe.rst
+++ /dev/null
@@ -1,65 +0,0 @@
-.. SPDX-License-Identifier: GPL-2.0
-
-The VPBE V4L2 driver design
-===========================
-
-Functional partitioning
------------------------
-
-Consists of the following:
-
- 1. V4L2 display driver
-
- Implements creation of video2 and video3 device nodes and
- provides v4l2 device interface to manage VID0 and VID1 layers.
-
- 2. Display controller
-
- Loads up VENC, OSD and external encoders such as ths8200. It provides
- a set of API calls to V4L2 drivers to set the output/standards
- in the VENC or external sub devices. It also provides
- a device object to access the services from OSD subdevice
- using sub device ops. The connection of external encoders to VENC LCD
- controller port is done at init time based on default output and standard
- selection or at run time when application change the output through
- V4L2 IOCTLs.
-
- When connected to an external encoder, vpbe controller is also responsible
- for setting up the interface between VENC and external encoders based on
- board specific settings (specified in board-xxx-evm.c). This allows
- interfacing external encoders such as ths8200. The setup_if_config()
- is implemented for this as well as configure_venc() (part of the next patch)
- API to set timings in VENC for a specific display resolution. As of this
- patch series, the interconnection and enabling and setting of the external
- encoders is not present, and would be a part of the next patch series.
-
- 3. VENC subdevice module
-
- Responsible for setting outputs provided through internal DACs and also
- setting timings at LCD controller port when external encoders are connected
- at the port or LCD panel timings required. When external encoder/LCD panel
- is connected, the timings for a specific standard/preset is retrieved from
- the board specific table and the values are used to set the timings in
- venc using non-standard timing mode.
-
- Support LCD Panel displays using the VENC. For example to support a Logic
- PD display, it requires setting up the LCD controller port with a set of
- timings for the resolution supported and setting the dot clock. So we could
- add the available outputs as a board specific entry (i.e add the "LogicPD"
- output name to board-xxx-evm.c). A table of timings for various LCDs
- supported can be maintained in the board specific setup file to support
- various LCD displays.As of this patch a basic driver is present, and this
- support for external encoders and displays forms a part of the next
- patch series.
-
- 4. OSD module
-
- OSD module implements all OSD layer management and hardware specific
- features. The VPBE module interacts with the OSD for enabling and
- disabling appropriate features of the OSD.
-
-Current status
---------------
-
-A fully functional working version of the V4L2 driver is available. This
-driver has been tested with NTSC and PAL standards and buffer streaming.
diff --git a/Documentation/admin-guide/media/platform-cardlist.rst b/Documentation/admin-guide/media/platform-cardlist.rst
index ac73c4166d1e..8ef57cd13dec 100644
--- a/Documentation/admin-guide/media/platform-cardlist.rst
+++ b/Documentation/admin-guide/media/platform-cardlist.rst
@@ -73,7 +73,6 @@ via-camera VIAFB camera controller
video-mux Video Multiplexer
vpif_display TI DaVinci VPIF V4L2-Display
vpif_capture TI DaVinci VPIF video capture
-vpss TI DaVinci VPBE V4L2-Display
vsp1 Renesas VSP1 Video Processing Engine
xilinx-tpg Xilinx Video Test Pattern Generator
xilinx-video Xilinx Video IP (EXPERIMENTAL)
diff --git a/Documentation/admin-guide/media/v4l-drivers.rst b/Documentation/admin-guide/media/v4l-drivers.rst
index 9c7ebe2ca3bd..13f8a39366c9 100644
--- a/Documentation/admin-guide/media/v4l-drivers.rst
+++ b/Documentation/admin-guide/media/v4l-drivers.rst
@@ -13,7 +13,6 @@ Video4Linux (V4L) driver-specific documentation
cafe_ccic
cpia2
cx88
- davinci-vpbe
fimc
imx
imx7
diff --git a/Documentation/driver-api/media/drivers/davinci-vpbe-devel.rst b/Documentation/driver-api/media/drivers/davinci-vpbe-devel.rst
deleted file mode 100644
index 4e87bdbc7ae4..000000000000
--- a/Documentation/driver-api/media/drivers/davinci-vpbe-devel.rst
+++ /dev/null
@@ -1,39 +0,0 @@
-.. SPDX-License-Identifier: GPL-2.0
-
-The VPBE V4L2 driver design
-===========================
-
-File partitioning
------------------
-
- V4L2 display device driver
- drivers/media/platform/ti/davinci/vpbe_display.c
- drivers/media/platform/ti/davinci/vpbe_display.h
-
- VPBE display controller
- drivers/media/platform/ti/davinci/vpbe.c
- drivers/media/platform/ti/davinci/vpbe.h
-
- VPBE venc sub device driver
- drivers/media/platform/ti/davinci/vpbe_venc.c
- drivers/media/platform/ti/davinci/vpbe_venc.h
- drivers/media/platform/ti/davinci/vpbe_venc_regs.h
-
- VPBE osd driver
- drivers/media/platform/ti/davinci/vpbe_osd.c
- drivers/media/platform/ti/davinci/vpbe_osd.h
- drivers/media/platform/ti/davinci/vpbe_osd_regs.h
-
-To be done
-----------
-
-vpbe display controller
- - Add support for external encoders.
- - add support for selecting external encoder as default at probe time.
-
-vpbe venc sub device
- - add timings for supporting ths8200
- - add support for LogicPD LCD.
-
-FB drivers
- - Add support for fbdev drivers.- Ready and part of subsequent patches.
diff --git a/Documentation/driver-api/media/drivers/index.rst b/Documentation/driver-api/media/drivers/index.rst
index 32406490557c..3c17d48f83c0 100644
--- a/Documentation/driver-api/media/drivers/index.rst
+++ b/Documentation/driver-api/media/drivers/index.rst
@@ -16,7 +16,6 @@ Video4Linux (V4L) drivers
cpia2_devel
cx2341x-devel
cx88-devel
- davinci-vpbe-devel
fimc-devel
pvrusb2
pxa_camera
diff --git a/drivers/media/platform/ti/davinci/Kconfig b/drivers/media/platform/ti/davinci/Kconfig
index 96d4bed7fe9e..542a602e66be 100644
--- a/drivers/media/platform/ti/davinci/Kconfig
+++ b/drivers/media/platform/ti/davinci/Kconfig
@@ -31,19 +31,3 @@ config VIDEO_DAVINCI_VPIF_CAPTURE
To compile this driver as a module, choose M here. There will
be two modules called vpif.ko and vpif_capture.ko
-
-config VIDEO_DAVINCI_VPBE_DISPLAY
- tristate "TI DaVinci VPBE V4L2-Display driver"
- depends on V4L_PLATFORM_DRIVERS
- depends on VIDEO_DEV
- depends on ARCH_DAVINCI || COMPILE_TEST
- depends on I2C
- select VIDEOBUF2_DMA_CONTIG
- help
- Enables Davinci VPBE module used for display devices.
- This module is used for display on TI DM644x/DM365/DM355
- based display devices.
-
- To compile this driver as a module, choose M here. There will
- be five modules created called vpss.ko, vpbe.ko, vpbe_osd.ko,
- vpbe_venc.ko and vpbe_display.ko
diff --git a/drivers/media/platform/ti/davinci/Makefile b/drivers/media/platform/ti/davinci/Makefile
index b20a91653162..512f03369bae 100644
--- a/drivers/media/platform/ti/davinci/Makefile
+++ b/drivers/media/platform/ti/davinci/Makefile
@@ -7,6 +7,3 @@
obj-$(CONFIG_VIDEO_DAVINCI_VPIF_DISPLAY) += vpif.o vpif_display.o
#VPIF Capture driver
obj-$(CONFIG_VIDEO_DAVINCI_VPIF_CAPTURE) += vpif.o vpif_capture.o
-
-obj-$(CONFIG_VIDEO_DAVINCI_VPBE_DISPLAY) += vpss.o vpbe.o vpbe_osd.o \
- vpbe_venc.o vpbe_display.o
diff --git a/drivers/media/platform/ti/davinci/vpbe.c b/drivers/media/platform/ti/davinci/vpbe.c
deleted file mode 100644
index 509ecc84624e..000000000000
--- a/drivers/media/platform/ti/davinci/vpbe.c
+++ /dev/null
@@ -1,840 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2010 Texas Instruments Inc
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/errno.h>
-#include <linux/fs.h>
-#include <linux/string.h>
-#include <linux/wait.h>
-#include <linux/time.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-
-#include <media/v4l2-device.h>
-#include <media/davinci/vpbe_types.h>
-#include <media/davinci/vpbe.h>
-#include <media/davinci/vpss.h>
-#include <media/davinci/vpbe_venc.h>
-
-#define VPBE_DEFAULT_OUTPUT "Composite"
-#define VPBE_DEFAULT_MODE "ntsc"
-
-static char *def_output = VPBE_DEFAULT_OUTPUT;
-static char *def_mode = VPBE_DEFAULT_MODE;
-static int debug;
-
-module_param(def_output, charp, S_IRUGO);
-module_param(def_mode, charp, S_IRUGO);
-module_param(debug, int, 0644);
-
-MODULE_PARM_DESC(def_output, "vpbe output name (default:Composite)");
-MODULE_PARM_DESC(def_mode, "vpbe output mode name (default:ntsc");
-MODULE_PARM_DESC(debug, "Debug level 0-1");
-
-MODULE_DESCRIPTION("TI DMXXX VPBE Display controller");
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Texas Instruments");
-
-/**
- * vpbe_current_encoder_info - Get config info for current encoder
- * @vpbe_dev: vpbe device ptr
- *
- * Return ptr to current encoder config info
- */
-static struct encoder_config_info*
-vpbe_current_encoder_info(struct vpbe_device *vpbe_dev)
-{
- struct vpbe_config *cfg = vpbe_dev->cfg;
- int index = vpbe_dev->current_sd_index;
-
- return ((index == 0) ? &cfg->venc :
- &cfg->ext_encoders[index-1]);
-}
-
-/**
- * vpbe_find_encoder_sd_index - Given a name find encoder sd index
- *
- * @cfg: ptr to vpbe cfg
- * @index: index used by application
- *
- * Return sd index of the encoder
- */
-static int vpbe_find_encoder_sd_index(struct vpbe_config *cfg,
- int index)
-{
- char *encoder_name = cfg->outputs[index].subdev_name;
- int i;
-
- /* Venc is always first */
- if (!strcmp(encoder_name, cfg->venc.module_name))
- return 0;
-
- for (i = 0; i < cfg->num_ext_encoders; i++) {
- if (!strcmp(encoder_name,
- cfg->ext_encoders[i].module_name))
- return i+1;
- }
-
- return -EINVAL;
-}
-
-/**
- * vpbe_enum_outputs - enumerate outputs
- * @vpbe_dev: vpbe device ptr
- * @output: ptr to v4l2_output structure
- *
- * Enumerates the outputs available at the vpbe display
- * returns the status, -EINVAL if end of output list
- */
-static int vpbe_enum_outputs(struct vpbe_device *vpbe_dev,
- struct v4l2_output *output)
-{
- struct vpbe_config *cfg = vpbe_dev->cfg;
- unsigned int temp_index = output->index;
-
- if (temp_index >= cfg->num_outputs)
- return -EINVAL;
-
- *output = cfg->outputs[temp_index].output;
- output->index = temp_index;
-
- return 0;
-}
-
-static int vpbe_get_mode_info(struct vpbe_device *vpbe_dev, char *mode,
- int output_index)
-{
- struct vpbe_config *cfg = vpbe_dev->cfg;
- struct vpbe_enc_mode_info var;
- int curr_output = output_index;
- int i;
-
- if (!mode)
- return -EINVAL;
-
- for (i = 0; i < cfg->outputs[curr_output].num_modes; i++) {
- var = cfg->outputs[curr_output].modes[i];
- if (!strcmp(mode, var.name)) {
- vpbe_dev->current_timings = var;
- return 0;
- }
- }
-
- return -EINVAL;
-}
-
-static int vpbe_get_current_mode_info(struct vpbe_device *vpbe_dev,
- struct vpbe_enc_mode_info *mode_info)
-{
- if (!mode_info)
- return -EINVAL;
-
- *mode_info = vpbe_dev->current_timings;
-
- return 0;
-}
-
-/* Get std by std id */
-static int vpbe_get_std_info(struct vpbe_device *vpbe_dev,
- v4l2_std_id std_id)
-{
- struct vpbe_config *cfg = vpbe_dev->cfg;
- struct vpbe_enc_mode_info var;
- int curr_output = vpbe_dev->current_out_index;
- int i;
-
- for (i = 0; i < vpbe_dev->cfg->outputs[curr_output].num_modes; i++) {
- var = cfg->outputs[curr_output].modes[i];
- if ((var.timings_type & VPBE_ENC_STD) &&
- (var.std_id & std_id)) {
- vpbe_dev->current_timings = var;
- return 0;
- }
- }
-
- return -EINVAL;
-}
-
-static int vpbe_get_std_info_by_name(struct vpbe_device *vpbe_dev,
- char *std_name)
-{
- struct vpbe_config *cfg = vpbe_dev->cfg;
- struct vpbe_enc_mode_info var;
- int curr_output = vpbe_dev->current_out_index;
- int i;
-
- for (i = 0; i < vpbe_dev->cfg->outputs[curr_output].num_modes; i++) {
- var = cfg->outputs[curr_output].modes[i];
- if (!strcmp(var.name, std_name)) {
- vpbe_dev->current_timings = var;
- return 0;
- }
- }
-
- return -EINVAL;
-}
-
-/**
- * vpbe_set_output - Set output
- * @vpbe_dev: vpbe device ptr
- * @index: index of output
- *
- * Set vpbe output to the output specified by the index
- */
-static int vpbe_set_output(struct vpbe_device *vpbe_dev, int index)
-{
- struct encoder_config_info *curr_enc_info =
- vpbe_current_encoder_info(vpbe_dev);
- struct vpbe_config *cfg = vpbe_dev->cfg;
- struct venc_platform_data *venc_device = vpbe_dev->venc_device;
- int enc_out_index;
- int sd_index;
- int ret;
-
- if (index >= cfg->num_outputs)
- return -EINVAL;
-
- mutex_lock(&vpbe_dev->lock);
-
- sd_index = vpbe_dev->current_sd_index;
- enc_out_index = cfg->outputs[index].output.index;
- /*
- * Currently we switch the encoder based on output selected
- * by the application. If media controller is implemented later
- * there is will be an API added to setup_link between venc
- * and external encoder. So in that case below comparison always
- * match and encoder will not be switched. But if application
- * chose not to use media controller, then this provides current
- * way of switching encoder at the venc output.
- */
- if (strcmp(curr_enc_info->module_name,
- cfg->outputs[index].subdev_name)) {
- /* Need to switch the encoder at the output */
- sd_index = vpbe_find_encoder_sd_index(cfg, index);
- if (sd_index < 0) {
- ret = -EINVAL;
- goto unlock;
- }
-
- ret = venc_device->setup_if_config(cfg->outputs[index].if_params);
- if (ret)
- goto unlock;
- }
-
- /* Set output at the encoder */
- ret = v4l2_subdev_call(vpbe_dev->encoders[sd_index], video,
- s_routing, 0, enc_out_index, 0);
- if (ret)
- goto unlock;
-
- /*
- * It is assumed that venc or external encoder will set a default
- * mode in the sub device. For external encoder or LCD pannel output,
- * we also need to set up the lcd port for the required mode. So setup
- * the lcd port for the default mode that is configured in the board
- * arch/arm/mach-davinci/board-dm355-evm.setup file for the external
- * encoder.
- */
- ret = vpbe_get_mode_info(vpbe_dev,
- cfg->outputs[index].default_mode, index);
- if (!ret) {
- struct osd_state *osd_device = vpbe_dev->osd_device;
-
- osd_device->ops.set_left_margin(osd_device,
- vpbe_dev->current_timings.left_margin);
- osd_device->ops.set_top_margin(osd_device,
- vpbe_dev->current_timings.upper_margin);
- vpbe_dev->current_sd_index = sd_index;
- vpbe_dev->current_out_index = index;
- }
-unlock:
- mutex_unlock(&vpbe_dev->lock);
- return ret;
-}
-
-static int vpbe_set_default_output(struct vpbe_device *vpbe_dev)
-{
- struct vpbe_config *cfg = vpbe_dev->cfg;
- int i;
-
- for (i = 0; i < cfg->num_outputs; i++) {
- if (!strcmp(def_output,
- cfg->outputs[i].output.name)) {
- int ret = vpbe_set_output(vpbe_dev, i);
-
- if (!ret)
- vpbe_dev->current_out_index = i;
- return ret;
- }
- }
- return 0;
-}
-
-/**
- * vpbe_get_output - Get output
- * @vpbe_dev: vpbe device ptr
- *
- * return current vpbe output to the index
- */
-static unsigned int vpbe_get_output(struct vpbe_device *vpbe_dev)
-{
- return vpbe_dev->current_out_index;
-}
-
-/*
- * vpbe_s_dv_timings - Set the given preset timings in the encoder
- *
- * Sets the timings if supported by the current encoder. Return the status.
- * 0 - success & -EINVAL on error
- */
-static int vpbe_s_dv_timings(struct vpbe_device *vpbe_dev,
- struct v4l2_dv_timings *dv_timings)
-{
- struct vpbe_config *cfg = vpbe_dev->cfg;
- int out_index = vpbe_dev->current_out_index;
- struct vpbe_output *output = &cfg->outputs[out_index];
- int sd_index = vpbe_dev->current_sd_index;
- int ret, i;
-
-
- if (!(cfg->outputs[out_index].output.capabilities &
- V4L2_OUT_CAP_DV_TIMINGS))
- return -ENODATA;
-
- for (i = 0; i < output->num_modes; i++) {
- if (output->modes[i].timings_type == VPBE_ENC_DV_TIMINGS &&
- !memcmp(&output->modes[i].dv_timings,
- dv_timings, sizeof(*dv_timings)))
- break;
- }
- if (i >= output->num_modes)
- return -EINVAL;
- vpbe_dev->current_timings = output->modes[i];
- mutex_lock(&vpbe_dev->lock);
-
- ret = v4l2_subdev_call(vpbe_dev->encoders[sd_index], video,
- s_dv_timings, dv_timings);
- if (!ret && vpbe_dev->amp) {
- /* Call amplifier subdevice */
- ret = v4l2_subdev_call(vpbe_dev->amp, video,
- s_dv_timings, dv_timings);
- }
- /* set the lcd controller output for the given mode */
- if (!ret) {
- struct osd_state *osd_device = vpbe_dev->osd_device;
-
- osd_device->ops.set_left_margin(osd_device,
- vpbe_dev->current_timings.left_margin);
- osd_device->ops.set_top_margin(osd_device,
- vpbe_dev->current_timings.upper_margin);
- }
- mutex_unlock(&vpbe_dev->lock);
-
- return ret;
-}
-
-/*
- * vpbe_g_dv_timings - Get the timings in the current encoder
- *
- * Get the timings in the current encoder. Return the status. 0 - success
- * -EINVAL on error
- */
-static int vpbe_g_dv_timings(struct vpbe_device *vpbe_dev,
- struct v4l2_dv_timings *dv_timings)
-{
- struct vpbe_config *cfg = vpbe_dev->cfg;
- int out_index = vpbe_dev->current_out_index;
-
- if (!(cfg->outputs[out_index].output.capabilities &
- V4L2_OUT_CAP_DV_TIMINGS))
- return -ENODATA;
-
- if (vpbe_dev->current_timings.timings_type &
- VPBE_ENC_DV_TIMINGS) {
- *dv_timings = vpbe_dev->current_timings.dv_timings;
- return 0;
- }
-
- return -EINVAL;
-}
-
-/*
- * vpbe_enum_dv_timings - Enumerate the dv timings in the current encoder
- *
- * Get the timings in the current encoder. Return the status. 0 - success
- * -EINVAL on error
- */
-static int vpbe_enum_dv_timings(struct vpbe_device *vpbe_dev,
- struct v4l2_enum_dv_timings *timings)
-{
- struct vpbe_config *cfg = vpbe_dev->cfg;
- int out_index = vpbe_dev->current_out_index;
- struct vpbe_output *output = &cfg->outputs[out_index];
- int j = 0;
- int i;
-
- if (!(output->output.capabilities & V4L2_OUT_CAP_DV_TIMINGS))
- return -ENODATA;
-
- for (i = 0; i < output->num_modes; i++) {
- if (output->modes[i].timings_type == VPBE_ENC_DV_TIMINGS) {
- if (j == timings->index)
- break;
- j++;
- }
- }
-
- if (i == output->num_modes)
- return -EINVAL;
- timings->timings = output->modes[i].dv_timings;
- return 0;
-}
-
-/*
- * vpbe_s_std - Set the given standard in the encoder
- *
- * Sets the standard if supported by the current encoder. Return the status.
- * 0 - success & -EINVAL on error
- */
-static int vpbe_s_std(struct vpbe_device *vpbe_dev, v4l2_std_id std_id)
-{
- struct vpbe_config *cfg = vpbe_dev->cfg;
- int out_index = vpbe_dev->current_out_index;
- int sd_index = vpbe_dev->current_sd_index;
- int ret;
-
- if (!(cfg->outputs[out_index].output.capabilities &
- V4L2_OUT_CAP_STD))
- return -ENODATA;
-
- ret = vpbe_get_std_info(vpbe_dev, std_id);
- if (ret)
- return ret;
-
- mutex_lock(&vpbe_dev->lock);
-
- ret = v4l2_subdev_call(vpbe_dev->encoders[sd_index], video,
- s_std_output, std_id);
- /* set the lcd controller output for the given mode */
- if (!ret) {
- struct osd_state *osd_device = vpbe_dev->osd_device;
-
- osd_device->ops.set_left_margin(osd_device,
- vpbe_dev->current_timings.left_margin);
- osd_device->ops.set_top_margin(osd_device,
- vpbe_dev->current_timings.upper_margin);
- }
- mutex_unlock(&vpbe_dev->lock);
-
- return ret;
-}
-
-/*
- * vpbe_g_std - Get the standard in the current encoder
- *
- * Get the standard in the current encoder. Return the status. 0 - success
- * -EINVAL on error
- */
-static int vpbe_g_std(struct vpbe_device *vpbe_dev, v4l2_std_id *std_id)
-{
- struct vpbe_enc_mode_info *cur_timings = &vpbe_dev->current_timings;
- struct vpbe_config *cfg = vpbe_dev->cfg;
- int out_index = vpbe_dev->current_out_index;
-
- if (!(cfg->outputs[out_index].output.capabilities & V4L2_OUT_CAP_STD))
- return -ENODATA;
-
- if (cur_timings->timings_type & VPBE_ENC_STD) {
- *std_id = cur_timings->std_id;
- return 0;
- }
-
- return -EINVAL;
-}
-
-/*
- * vpbe_set_mode - Set mode in the current encoder using mode info
- *
- * Use the mode string to decide what timings to set in the encoder
- * This is typically useful when fbset command is used to change the current
- * timings by specifying a string to indicate the timings.
- */
-static int vpbe_set_mode(struct vpbe_device *vpbe_dev,
- struct vpbe_enc_mode_info *mode_info)
-{
- struct vpbe_enc_mode_info *preset_mode = NULL;
- struct vpbe_config *cfg = vpbe_dev->cfg;
- struct v4l2_dv_timings dv_timings;
- struct osd_state *osd_device;
- int out_index = vpbe_dev->current_out_index;
- int i;
-
- if (!mode_info || !mode_info->name)
- return -EINVAL;
-
- for (i = 0; i < cfg->outputs[out_index].num_modes; i++) {
- if (!strcmp(mode_info->name,
- cfg->outputs[out_index].modes[i].name)) {
- preset_mode = &cfg->outputs[out_index].modes[i];
- /*
- * it may be one of the 3 timings type. Check and
- * invoke right API
- */
- if (preset_mode->timings_type & VPBE_ENC_STD)
- return vpbe_s_std(vpbe_dev,
- preset_mode->std_id);
- if (preset_mode->timings_type &
- VPBE_ENC_DV_TIMINGS) {
- dv_timings =
- preset_mode->dv_timings;
- return vpbe_s_dv_timings(vpbe_dev, &dv_timings);
- }
- }
- }
-
- /* Only custom timing should reach here */
- if (!preset_mode)
- return -EINVAL;
-
- mutex_lock(&vpbe_dev->lock);
-
- osd_device = vpbe_dev->osd_device;
- vpbe_dev->current_timings = *preset_mode;
- osd_device->ops.set_left_margin(osd_device,
- vpbe_dev->current_timings.left_margin);
- osd_device->ops.set_top_margin(osd_device,
- vpbe_dev->current_timings.upper_margin);
-
- mutex_unlock(&vpbe_dev->lock);
- return 0;
-}
-
-static int vpbe_set_default_mode(struct vpbe_device *vpbe_dev)
-{
- int ret;
-
- ret = vpbe_get_std_info_by_name(vpbe_dev, def_mode);
- if (ret)
- return ret;
-
- /* set the default mode in the encoder */
- return vpbe_set_mode(vpbe_dev, &vpbe_dev->current_timings);
-}
-
-static int platform_device_get(struct device *dev, void *data)
-{
- struct platform_device *pdev = to_platform_device(dev);
- struct vpbe_device *vpbe_dev = data;
-
- if (strstr(pdev->name, "vpbe-osd"))
- vpbe_dev->osd_device = platform_get_drvdata(pdev);
- if (strstr(pdev->name, "vpbe-venc"))
- vpbe_dev->venc_device = dev_get_platdata(&pdev->dev);
-
- return 0;
-}
-
-/**
- * vpbe_initialize() - Initialize the vpbe display controller
- * @dev: Master and slave device ptr
- * @vpbe_dev: vpbe device ptr
- *
- * Master frame buffer device drivers calls this to initialize vpbe
- * display controller. This will then registers v4l2 device and the sub
- * devices and sets a current encoder sub device for display. v4l2 display
- * device driver is the master and frame buffer display device driver is
- * the slave. Frame buffer display driver checks the initialized during
- * probe and exit if not initialized. Returns status.
- */
-static int vpbe_initialize(struct device *dev, struct vpbe_device *vpbe_dev)
-{
- struct encoder_config_info *enc_info;
- struct amp_config_info *amp_info;
- struct v4l2_subdev **enc_subdev;
- struct osd_state *osd_device;
- struct i2c_adapter *i2c_adap;
- int num_encoders;
- int ret = 0;
- int err;
- int i;
-
- /*
- * v4l2 abd FBDev frame buffer devices will get the vpbe_dev pointer
- * from the platform device by iteration of platform drivers and
- * matching with device name
- */
- if (!vpbe_dev || !dev) {
- printk(KERN_ERR "Null device pointers.\n");
- return -ENODEV;
- }
-
- if (vpbe_dev->initialized)
- return 0;
-
- mutex_lock(&vpbe_dev->lock);
-
- if (strcmp(vpbe_dev->cfg->module_name, "dm644x-vpbe-display") != 0) {
- /* We have dac clock available for platform */
- vpbe_dev->dac_clk = clk_get(vpbe_dev->pdev, "vpss_dac");
- if (IS_ERR(vpbe_dev->dac_clk)) {
- ret = PTR_ERR(vpbe_dev->dac_clk);
- goto fail_mutex_unlock;
- }
- if (clk_prepare_enable(vpbe_dev->dac_clk)) {
- ret = -ENODEV;
- clk_put(vpbe_dev->dac_clk);
- goto fail_mutex_unlock;
- }
- }
-
- /* first enable vpss clocks */
- vpss_enable_clock(VPSS_VPBE_CLOCK, 1);
-
- /* First register a v4l2 device */
- ret = v4l2_device_register(dev, &vpbe_dev->v4l2_dev);
- if (ret) {
- v4l2_err(dev->driver,
- "Unable to register v4l2 device.\n");
- goto fail_clk_put;
- }
- v4l2_info(&vpbe_dev->v4l2_dev, "vpbe v4l2 device registered\n");
-
- err = bus_for_each_dev(&platform_bus_type, NULL, vpbe_dev,
- platform_device_get);
- if (err < 0) {
- ret = err;
- goto fail_dev_unregister;
- }
-
- vpbe_dev->venc = venc_sub_dev_init(&vpbe_dev->v4l2_dev,
- vpbe_dev->cfg->venc.module_name);
- /* register venc sub device */
- if (!vpbe_dev->venc) {
- v4l2_err(&vpbe_dev->v4l2_dev,
- "vpbe unable to init venc sub device\n");
- ret = -ENODEV;
- goto fail_dev_unregister;
- }
- /* initialize osd device */
- osd_device = vpbe_dev->osd_device;
- if (osd_device->ops.initialize) {
- err = osd_device->ops.initialize(osd_device);
- if (err) {
- v4l2_err(&vpbe_dev->v4l2_dev,
- "unable to initialize the OSD device");
- ret = -ENOMEM;
- goto fail_dev_unregister;
- }
- }
-
- /*
- * Register any external encoders that are configured. At index 0 we
- * store venc sd index.
- */
- num_encoders = vpbe_dev->cfg->num_ext_encoders + 1;
- vpbe_dev->encoders = kmalloc_array(num_encoders,
- sizeof(*vpbe_dev->encoders),
- GFP_KERNEL);
- if (!vpbe_dev->encoders) {
- ret = -ENOMEM;
- goto fail_dev_unregister;
- }
-
- i2c_adap = i2c_get_adapter(vpbe_dev->cfg->i2c_adapter_id);
- for (i = 0; i < (vpbe_dev->cfg->num_ext_encoders + 1); i++) {
- if (i == 0) {
- /* venc is at index 0 */
- enc_subdev = &vpbe_dev->encoders[i];
- *enc_subdev = vpbe_dev->venc;
- continue;
- }
- enc_info = &vpbe_dev->cfg->ext_encoders[i];
- if (enc_info->is_i2c) {
- enc_subdev = &vpbe_dev->encoders[i];
- *enc_subdev = v4l2_i2c_new_subdev_board(
- &vpbe_dev->v4l2_dev, i2c_adap,
- &enc_info->board_info, NULL);
- if (*enc_subdev)
- v4l2_info(&vpbe_dev->v4l2_dev,
- "v4l2 sub device %s registered\n",
- enc_info->module_name);
- else {
- v4l2_err(&vpbe_dev->v4l2_dev, "encoder %s failed to register",
- enc_info->module_name);
- ret = -ENODEV;
- goto fail_kfree_encoders;
- }
- } else
- v4l2_warn(&vpbe_dev->v4l2_dev, "non-i2c encoders currently not supported");
- }
- /* Add amplifier subdevice for dm365 */
- if ((strcmp(vpbe_dev->cfg->module_name, "dm365-vpbe-display") == 0) &&
- vpbe_dev->cfg->amp) {
- amp_info = vpbe_dev->cfg->amp;
- if (amp_info->is_i2c) {
- vpbe_dev->amp = v4l2_i2c_new_subdev_board(
- &vpbe_dev->v4l2_dev, i2c_adap,
- &_info->board_info, NULL);
- if (!vpbe_dev->amp) {
- v4l2_err(&vpbe_dev->v4l2_dev,
- "amplifier %s failed to register",
- amp_info->module_name);
- ret = -ENODEV;
- goto fail_kfree_encoders;
- }
- v4l2_info(&vpbe_dev->v4l2_dev,
- "v4l2 sub device %s registered\n",
- amp_info->module_name);
- } else {
- vpbe_dev->amp = NULL;
- v4l2_warn(&vpbe_dev->v4l2_dev, "non-i2c amplifiers currently not supported");
- }
- } else {
- vpbe_dev->amp = NULL;
- }
-
- /* set the current encoder and output to that of venc by default */
- vpbe_dev->current_sd_index = 0;
- vpbe_dev->current_out_index = 0;
-
- mutex_unlock(&vpbe_dev->lock);
-
- printk(KERN_NOTICE "Setting default output to %s\n", def_output);
- ret = vpbe_set_default_output(vpbe_dev);
- if (ret) {
- v4l2_err(&vpbe_dev->v4l2_dev, "Failed to set default output %s",
- def_output);
- goto fail_kfree_amp;
- }
-
- printk(KERN_NOTICE "Setting default mode to %s\n", def_mode);
- ret = vpbe_set_default_mode(vpbe_dev);
- if (ret) {
- v4l2_err(&vpbe_dev->v4l2_dev, "Failed to set default mode %s",
- def_mode);
- goto fail_kfree_amp;
- }
- vpbe_dev->initialized = 1;
- /* TBD handling of bootargs for default output and mode */
- return 0;
-
-fail_kfree_amp:
- mutex_lock(&vpbe_dev->lock);
- kfree(vpbe_dev->amp);
-fail_kfree_encoders:
- kfree(vpbe_dev->encoders);
-fail_dev_unregister:
- v4l2_device_unregister(&vpbe_dev->v4l2_dev);
-fail_clk_put:
- if (strcmp(vpbe_dev->cfg->module_name, "dm644x-vpbe-display") != 0) {
- clk_disable_unprepare(vpbe_dev->dac_clk);
- clk_put(vpbe_dev->dac_clk);
- }
-fail_mutex_unlock:
- mutex_unlock(&vpbe_dev->lock);
- return ret;
-}
-
-/**
- * vpbe_deinitialize() - de-initialize the vpbe display controller
- * @dev: Master and slave device ptr
- * @vpbe_dev: vpbe device ptr
- *
- * vpbe_master and slave frame buffer devices calls this to de-initialize
- * the display controller. It is called when master and slave device
- * driver modules are removed and no longer requires the display controller.
- */
-static void vpbe_deinitialize(struct device *dev, struct vpbe_device *vpbe_dev)
-{
- v4l2_device_unregister(&vpbe_dev->v4l2_dev);
- if (strcmp(vpbe_dev->cfg->module_name, "dm644x-vpbe-display") != 0) {
- clk_disable_unprepare(vpbe_dev->dac_clk);
- clk_put(vpbe_dev->dac_clk);
- }
-
- kfree(vpbe_dev->amp);
- kfree(vpbe_dev->encoders);
- vpbe_dev->initialized = 0;
- /* disable vpss clocks */
- vpss_enable_clock(VPSS_VPBE_CLOCK, 0);
-}
-
-static const struct vpbe_device_ops vpbe_dev_ops = {
- .enum_outputs = vpbe_enum_outputs,
- .set_output = vpbe_set_output,
- .get_output = vpbe_get_output,
- .s_dv_timings = vpbe_s_dv_timings,
- .g_dv_timings = vpbe_g_dv_timings,
- .enum_dv_timings = vpbe_enum_dv_timings,
- .s_std = vpbe_s_std,
- .g_std = vpbe_g_std,
- .initialize = vpbe_initialize,
- .deinitialize = vpbe_deinitialize,
- .get_mode_info = vpbe_get_current_mode_info,
- .set_mode = vpbe_set_mode,
-};
-
-static int vpbe_probe(struct platform_device *pdev)
-{
- struct vpbe_device *vpbe_dev;
- struct vpbe_config *cfg;
-
- if (!pdev->dev.platform_data) {
- v4l2_err(pdev->dev.driver, "No platform data\n");
- return -ENODEV;
- }
- cfg = pdev->dev.platform_data;
-
- if (!cfg->module_name[0] ||
- !cfg->osd.module_name[0] ||
- !cfg->venc.module_name[0]) {
- v4l2_err(pdev->dev.driver, "vpbe display module names not defined\n");
- return -EINVAL;
- }
-
- vpbe_dev = kzalloc(sizeof(*vpbe_dev), GFP_KERNEL);
- if (!vpbe_dev)
- return -ENOMEM;
-
- vpbe_dev->cfg = cfg;
- vpbe_dev->ops = vpbe_dev_ops;
- vpbe_dev->pdev = &pdev->dev;
-
- if (cfg->outputs->num_modes > 0)
- vpbe_dev->current_timings = vpbe_dev->cfg->outputs[0].modes[0];
- else {
- kfree(vpbe_dev);
- return -ENODEV;
- }
-
- /* set the driver data in platform device */
- platform_set_drvdata(pdev, vpbe_dev);
- mutex_init(&vpbe_dev->lock);
-
- return 0;
-}
-
-static int vpbe_remove(struct platform_device *device)
-{
- struct vpbe_device *vpbe_dev = platform_get_drvdata(device);
-
- kfree(vpbe_dev);
-
- return 0;
-}
-
-static struct platform_driver vpbe_driver = {
- .driver = {
- .name = "vpbe_controller",
- },
- .probe = vpbe_probe,
- .remove = vpbe_remove,
-};
-
-module_platform_driver(vpbe_driver);
diff --git a/drivers/media/platform/ti/davinci/vpbe_display.c b/drivers/media/platform/ti/davinci/vpbe_display.c
deleted file mode 100644
index 9ea70817538e..000000000000
--- a/drivers/media/platform/ti/davinci/vpbe_display.c
+++ /dev/null
@@ -1,1510 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/errno.h>
-#include <linux/interrupt.h>
-#include <linux/string.h>
-#include <linux/wait.h>
-#include <linux/time.h>
-#include <linux/platform_device.h>
-#include <linux/irq.h>
-#include <linux/mm.h>
-#include <linux/mutex.h>
-#include <linux/videodev2.h>
-#include <linux/slab.h>
-
-
-#include <media/v4l2-dev.h>
-#include <media/v4l2-common.h>
-#include <media/v4l2-ioctl.h>
-#include <media/v4l2-device.h>
-#include <media/davinci/vpbe_display.h>
-#include <media/davinci/vpbe_types.h>
-#include <media/davinci/vpbe.h>
-#include <media/davinci/vpbe_venc.h>
-#include <media/davinci/vpbe_osd.h>
-#include "vpbe_venc_regs.h"
-
-#define VPBE_DISPLAY_DRIVER "vpbe-v4l2"
-
-static int debug;
-
-#define VPBE_DEFAULT_NUM_BUFS 3
-
-module_param(debug, int, 0644);
-
-static int vpbe_set_osd_display_params(struct vpbe_display *disp_dev,
- struct vpbe_layer *layer);
-
-static int venc_is_second_field(struct vpbe_display *disp_dev)
-{
- struct vpbe_device *vpbe_dev = disp_dev->vpbe_dev;
- int ret, val;
-
- ret = v4l2_subdev_call(vpbe_dev->venc,
- core,
- command,
- VENC_GET_FLD,
- &val);
- if (ret < 0) {
- v4l2_err(&vpbe_dev->v4l2_dev,
- "Error in getting Field ID 0\n");
- return 1;
- }
- return val;
-}
-
-static void vpbe_isr_even_field(struct vpbe_display *disp_obj,
- struct vpbe_layer *layer)
-{
- if (layer->cur_frm == layer->next_frm)
- return;
-
- layer->cur_frm->vb.vb2_buf.timestamp = ktime_get_ns();
- vb2_buffer_done(&layer->cur_frm->vb.vb2_buf, VB2_BUF_STATE_DONE);
- /* Make cur_frm pointing to next_frm */
- layer->cur_frm = layer->next_frm;
-}
-
-static void vpbe_isr_odd_field(struct vpbe_display *disp_obj,
- struct vpbe_layer *layer)
-{
- struct osd_state *osd_device = disp_obj->osd_device;
- unsigned long addr;
-
- spin_lock(&disp_obj->dma_queue_lock);
- if (list_empty(&layer->dma_queue) ||
- (layer->cur_frm != layer->next_frm)) {
- spin_unlock(&disp_obj->dma_queue_lock);
- return;
- }
- /*
- * one field is displayed configure
- * the next frame if it is available
- * otherwise hold on current frame
- * Get next from the buffer queue
- */
- layer->next_frm = list_entry(layer->dma_queue.next,
- struct vpbe_disp_buffer, list);
- /* Remove that from the buffer queue */
- list_del(&layer->next_frm->list);
- spin_unlock(&disp_obj->dma_queue_lock);
- /* Mark state of the frame to active */
- layer->next_frm->vb.vb2_buf.state = VB2_BUF_STATE_ACTIVE;
- addr = vb2_dma_contig_plane_dma_addr(&layer->next_frm->vb.vb2_buf, 0);
- osd_device->ops.start_layer(osd_device,
- layer->layer_info.id,
- addr,
- disp_obj->cbcr_ofst);
-}
-
-/* interrupt service routine */
-static irqreturn_t venc_isr(int irq, void *arg)
-{
- struct vpbe_display *disp_dev = (struct vpbe_display *)arg;
- struct vpbe_layer *layer;
- static unsigned last_event;
- unsigned event = 0;
- int fid;
- int i;
-
- if (!arg || !disp_dev->dev[0])
- return IRQ_HANDLED;
-
- if (venc_is_second_field(disp_dev))
- event |= VENC_SECOND_FIELD;
- else
- event |= VENC_FIRST_FIELD;
-
- if (event == (last_event & ~VENC_END_OF_FRAME)) {
- /*
- * If the display is non-interlaced, then we need to flag the
- * end-of-frame event at every interrupt regardless of the
- * value of the FIDST bit. We can conclude that the display is
- * non-interlaced if the value of the FIDST bit is unchanged
- * from the previous interrupt.
- */
- event |= VENC_END_OF_FRAME;
- } else if (event == VENC_SECOND_FIELD) {
- /* end-of-frame for interlaced display */
- event |= VENC_END_OF_FRAME;
- }
- last_event = event;
-
- for (i = 0; i < VPBE_DISPLAY_MAX_DEVICES; i++) {
- layer = disp_dev->dev[i];
-
- if (!vb2_start_streaming_called(&layer->buffer_queue))
- continue;
-
- if (layer->layer_first_int) {
- layer->layer_first_int = 0;
- continue;
- }
- /* Check the field format */
- if ((V4L2_FIELD_NONE == layer->pix_fmt.field) &&
- (event & VENC_END_OF_FRAME)) {
- /* Progressive mode */
-
- vpbe_isr_even_field(disp_dev, layer);
- vpbe_isr_odd_field(disp_dev, layer);
- } else {
- /* Interlaced mode */
-
- layer->field_id ^= 1;
- if (event & VENC_FIRST_FIELD)
- fid = 0;
- else
- fid = 1;
-
- /*
- * If field id does not match with store
- * field id
- */
- if (fid != layer->field_id) {
- /* Make them in sync */
- layer->field_id = fid;
- continue;
- }
- /*
- * device field id and local field id are
- * in sync. If this is even field
- */
- if (0 == fid)
- vpbe_isr_even_field(disp_dev, layer);
- else /* odd field */
- vpbe_isr_odd_field(disp_dev, layer);
- }
- }
-
- return IRQ_HANDLED;
-}
-
-/*
- * vpbe_buffer_prepare()
- * This is the callback function called from vb2_qbuf() function
- * the buffer is prepared and user space virtual address is converted into
- * physical address
- */
-static int vpbe_buffer_prepare(struct vb2_buffer *vb)
-{
- struct vb2_queue *q = vb->vb2_queue;
- struct vpbe_layer *layer = vb2_get_drv_priv(q);
- struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev;
- unsigned long addr;
-
- v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev,
- "vpbe_buffer_prepare\n");
-
- vb2_set_plane_payload(vb, 0, layer->pix_fmt.sizeimage);
- if (vb2_get_plane_payload(vb, 0) > vb2_plane_size(vb, 0))
- return -EINVAL;
-
- addr = vb2_dma_contig_plane_dma_addr(vb, 0);
- if (!IS_ALIGNED(addr, 8)) {
- v4l2_err(&vpbe_dev->v4l2_dev,
- "buffer_prepare:offset is not aligned to 32 bytes\n");
- return -EINVAL;
- }
- return 0;
-}
-
-/*
- * vpbe_buffer_setup()
- * This function allocates memory for the buffers
- */
-static int
-vpbe_buffer_queue_setup(struct vb2_queue *vq,
- unsigned int *nbuffers, unsigned int *nplanes,
- unsigned int sizes[], struct device *alloc_devs[])
-
-{
- /* Get the file handle object and layer object */
- struct vpbe_layer *layer = vb2_get_drv_priv(vq);
- struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev;
-
- v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "vpbe_buffer_setup\n");
-
- /* Store number of buffers allocated in numbuffer member */
- if (vq->num_buffers + *nbuffers < VPBE_DEFAULT_NUM_BUFS)
- *nbuffers = VPBE_DEFAULT_NUM_BUFS - vq->num_buffers;
-
- if (*nplanes)
- return sizes[0] < layer->pix_fmt.sizeimage ? -EINVAL : 0;
-
- *nplanes = 1;
- sizes[0] = layer->pix_fmt.sizeimage;
-
- return 0;
-}
-
-/*
- * vpbe_buffer_queue()
- * This function adds the buffer to DMA queue
- */
-static void vpbe_buffer_queue(struct vb2_buffer *vb)
-{
- struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
- /* Get the file handle object and layer object */
- struct vpbe_disp_buffer *buf = container_of(vbuf,
- struct vpbe_disp_buffer, vb);
- struct vpbe_layer *layer = vb2_get_drv_priv(vb->vb2_queue);
- struct vpbe_display *disp = layer->disp_dev;
- struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev;
- unsigned long flags;
-
- v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev,
- "vpbe_buffer_queue\n");
-
- /* add the buffer to the DMA queue */
- spin_lock_irqsave(&disp->dma_queue_lock, flags);
- list_add_tail(&buf->list, &layer->dma_queue);
- spin_unlock_irqrestore(&disp->dma_queue_lock, flags);
-}
-
-static int vpbe_start_streaming(struct vb2_queue *vq, unsigned int count)
-{
- struct vpbe_layer *layer = vb2_get_drv_priv(vq);
- struct osd_state *osd_device = layer->disp_dev->osd_device;
- int ret;
-
- osd_device->ops.disable_layer(osd_device, layer->layer_info.id);
-
- /* Get the next frame from the buffer queue */
- layer->next_frm = layer->cur_frm = list_entry(layer->dma_queue.next,
- struct vpbe_disp_buffer, list);
- /* Remove buffer from the buffer queue */
- list_del(&layer->cur_frm->list);
- /* Mark state of the current frame to active */
- layer->cur_frm->vb.vb2_buf.state = VB2_BUF_STATE_ACTIVE;
- /* Initialize field_id and started member */
- layer->field_id = 0;
-
- /* Set parameters in OSD and VENC */
- ret = vpbe_set_osd_display_params(layer->disp_dev, layer);
- if (ret < 0) {
- struct vpbe_disp_buffer *buf, *tmp;
-
- vb2_buffer_done(&layer->cur_frm->vb.vb2_buf,
- VB2_BUF_STATE_QUEUED);
- list_for_each_entry_safe(buf, tmp, &layer->dma_queue, list) {
- list_del(&buf->list);
- vb2_buffer_done(&buf->vb.vb2_buf,
- VB2_BUF_STATE_QUEUED);
- }
-
- return ret;
- }
-
- /*
- * if request format is yuv420 semiplanar, need to
- * enable both video windows
- */
- layer->layer_first_int = 1;
-
- return ret;
-}
-
-static void vpbe_stop_streaming(struct vb2_queue *vq)
-{
- struct vpbe_layer *layer = vb2_get_drv_priv(vq);
- struct osd_state *osd_device = layer->disp_dev->osd_device;
- struct vpbe_display *disp = layer->disp_dev;
- unsigned long flags;
-
- if (!vb2_is_streaming(vq))
- return;
-
- osd_device->ops.disable_layer(osd_device, layer->layer_info.id);
-
- /* release all active buffers */
- spin_lock_irqsave(&disp->dma_queue_lock, flags);
- if (layer->cur_frm == layer->next_frm) {
- vb2_buffer_done(&layer->cur_frm->vb.vb2_buf,
- VB2_BUF_STATE_ERROR);
- } else {
- if (layer->cur_frm)
- vb2_buffer_done(&layer->cur_frm->vb.vb2_buf,
- VB2_BUF_STATE_ERROR);
- if (layer->next_frm)
- vb2_buffer_done(&layer->next_frm->vb.vb2_buf,
- VB2_BUF_STATE_ERROR);
- }
-
- while (!list_empty(&layer->dma_queue)) {
- layer->next_frm = list_entry(layer->dma_queue.next,
- struct vpbe_disp_buffer, list);
- list_del(&layer->next_frm->list);
- vb2_buffer_done(&layer->next_frm->vb.vb2_buf,
- VB2_BUF_STATE_ERROR);
- }
- spin_unlock_irqrestore(&disp->dma_queue_lock, flags);
-}
-
-static const struct vb2_ops video_qops = {
- .queue_setup = vpbe_buffer_queue_setup,
- .wait_prepare = vb2_ops_wait_prepare,
- .wait_finish = vb2_ops_wait_finish,
- .buf_prepare = vpbe_buffer_prepare,
- .start_streaming = vpbe_start_streaming,
- .stop_streaming = vpbe_stop_streaming,
- .buf_queue = vpbe_buffer_queue,
-};
-
-static
-struct vpbe_layer*
-_vpbe_display_get_other_win_layer(struct vpbe_display *disp_dev,
- struct vpbe_layer *layer)
-{
- enum vpbe_display_device_id thiswin, otherwin;
- thiswin = layer->device_id;
-
- otherwin = (thiswin == VPBE_DISPLAY_DEVICE_0) ?
- VPBE_DISPLAY_DEVICE_1 : VPBE_DISPLAY_DEVICE_0;
- return disp_dev->dev[otherwin];
-}
-
-static int vpbe_set_osd_display_params(struct vpbe_display *disp_dev,
- struct vpbe_layer *layer)
-{
- struct osd_layer_config *cfg = &layer->layer_info.config;
- struct osd_state *osd_device = disp_dev->osd_device;
- struct vpbe_device *vpbe_dev = disp_dev->vpbe_dev;
- unsigned long addr;
- int ret;
-
- addr = vb2_dma_contig_plane_dma_addr(&layer->cur_frm->vb.vb2_buf, 0);
- /* Set address in the display registers */
- osd_device->ops.start_layer(osd_device,
- layer->layer_info.id,
- addr,
- disp_dev->cbcr_ofst);
-
- ret = osd_device->ops.enable_layer(osd_device,
- layer->layer_info.id, 0);
- if (ret < 0) {
- v4l2_err(&vpbe_dev->v4l2_dev,
- "Error in enabling osd window layer 0\n");
- return -1;
- }
-
- /* Enable the window */
- layer->layer_info.enable = 1;
- if (cfg->pixfmt == PIXFMT_NV12) {
- struct vpbe_layer *otherlayer =
- _vpbe_display_get_other_win_layer(disp_dev, layer);
-
- ret = osd_device->ops.enable_layer(osd_device,
- otherlayer->layer_info.id, 1);
- if (ret < 0) {
- v4l2_err(&vpbe_dev->v4l2_dev,
- "Error in enabling osd window layer 1\n");
- return -1;
- }
- otherlayer->layer_info.enable = 1;
- }
- return 0;
-}
-
-static void
-vpbe_disp_calculate_scale_factor(struct vpbe_display *disp_dev,
- struct vpbe_layer *layer,
- int expected_xsize, int expected_ysize)
-{
- struct display_layer_info *layer_info = &layer->layer_info;
- struct v4l2_pix_format *pixfmt = &layer->pix_fmt;
- struct osd_layer_config *cfg = &layer->layer_info.config;
- struct vpbe_device *vpbe_dev = disp_dev->vpbe_dev;
- int calculated_xsize;
- int h_exp = 0;
- int v_exp = 0;
- int h_scale;
- int v_scale;
-
- v4l2_std_id standard_id = vpbe_dev->current_timings.std_id;
-
- /*
- * Application initially set the image format. Current display
- * size is obtained from the vpbe display controller. expected_xsize
- * and expected_ysize are set through S_SELECTION ioctl. Based on this,
- * driver will calculate the scale factors for vertical and
- * horizontal direction so that the image is displayed scaled
- * and expanded. Application uses expansion to display the image
- * in a square pixel. Otherwise it is displayed using displays
- * pixel aspect ratio.It is expected that application chooses
- * the crop coordinates for cropped or scaled display. if crop
- * size is less than the image size, it is displayed cropped or
- * it is displayed scaled and/or expanded.
- *
- * to begin with, set the crop window same as expected. Later we
- * will override with scaled window size
- */
-
- cfg->xsize = pixfmt->width;
- cfg->ysize = pixfmt->height;
- layer_info->h_zoom = ZOOM_X1; /* no horizontal zoom */
- layer_info->v_zoom = ZOOM_X1; /* no horizontal zoom */
- layer_info->h_exp = H_EXP_OFF; /* no horizontal zoom */
- layer_info->v_exp = V_EXP_OFF; /* no horizontal zoom */
-
- if (pixfmt->width < expected_xsize) {
- h_scale = vpbe_dev->current_timings.xres / pixfmt->width;
- if (h_scale < 2)
- h_scale = 1;
- else if (h_scale >= 4)
- h_scale = 4;
- else
- h_scale = 2;
- cfg->xsize *= h_scale;
- if (cfg->xsize < expected_xsize) {
- if ((standard_id & V4L2_STD_525_60) ||
- (standard_id & V4L2_STD_625_50)) {
- calculated_xsize = (cfg->xsize *
- VPBE_DISPLAY_H_EXP_RATIO_N) /
- VPBE_DISPLAY_H_EXP_RATIO_D;
- if (calculated_xsize <= expected_xsize) {
- h_exp = 1;
- cfg->xsize = calculated_xsize;
- }
- }
- }
- if (h_scale == 2)
- layer_info->h_zoom = ZOOM_X2;
- else if (h_scale == 4)
- layer_info->h_zoom = ZOOM_X4;
- if (h_exp)
- layer_info->h_exp = H_EXP_9_OVER_8;
- } else {
- /* no scaling, only cropping. Set display area to crop area */
- cfg->xsize = expected_xsize;
- }
-
- if (pixfmt->height < expected_ysize) {
- v_scale = expected_ysize / pixfmt->height;
- if (v_scale < 2)
- v_scale = 1;
- else if (v_scale >= 4)
- v_scale = 4;
- else
- v_scale = 2;
- cfg->ysize *= v_scale;
- if (cfg->ysize < expected_ysize) {
- if ((standard_id & V4L2_STD_625_50)) {
- calculated_xsize = (cfg->ysize *
- VPBE_DISPLAY_V_EXP_RATIO_N) /
- VPBE_DISPLAY_V_EXP_RATIO_D;
- if (calculated_xsize <= expected_ysize) {
- v_exp = 1;
- cfg->ysize = calculated_xsize;
- }
- }
- }
- if (v_scale == 2)
- layer_info->v_zoom = ZOOM_X2;
- else if (v_scale == 4)
- layer_info->v_zoom = ZOOM_X4;
- if (v_exp)
- layer_info->v_exp = V_EXP_6_OVER_5;
- } else {
- /* no scaling, only cropping. Set display area to crop area */
- cfg->ysize = expected_ysize;
- }
- v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev,
- "crop display xsize = %d, ysize = %d\n",
- cfg->xsize, cfg->ysize);
-}
-
-static void vpbe_disp_adj_position(struct vpbe_display *disp_dev,
- struct vpbe_layer *layer,
- int top, int left)
-{
- struct osd_layer_config *cfg = &layer->layer_info.config;
- struct vpbe_device *vpbe_dev = disp_dev->vpbe_dev;
-
- cfg->xpos = min((unsigned int)left,
- vpbe_dev->current_timings.xres - cfg->xsize);
- cfg->ypos = min((unsigned int)top,
- vpbe_dev->current_timings.yres - cfg->ysize);
-
- v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev,
- "new xpos = %d, ypos = %d\n",
- cfg->xpos, cfg->ypos);
-}
-
-static void vpbe_disp_check_window_params(struct vpbe_display *disp_dev,
- struct v4l2_rect *c)
-{
- struct vpbe_device *vpbe_dev = disp_dev->vpbe_dev;
-
- if ((c->width == 0) ||
- ((c->width + c->left) > vpbe_dev->current_timings.xres))
- c->width = vpbe_dev->current_timings.xres - c->left;
-
- if ((c->height == 0) || ((c->height + c->top) >
- vpbe_dev->current_timings.yres))
- c->height = vpbe_dev->current_timings.yres - c->top;
-
- /* window height must be even for interlaced display */
- if (vpbe_dev->current_timings.interlaced)
- c->height &= (~0x01);
-
-}
-
-/*
- * vpbe_try_format()
- * If user application provides width and height, and have bytesperline set
- * to zero, driver calculates bytesperline and sizeimage based on hardware
- * limits.
- */
-static int vpbe_try_format(struct vpbe_display *disp_dev,
- struct v4l2_pix_format *pixfmt, int check)
-{
- struct vpbe_device *vpbe_dev = disp_dev->vpbe_dev;
- int min_height = 1;
- int min_width = 32;
- int max_height;
- int max_width;
- int bpp;
-
- if ((pixfmt->pixelformat != V4L2_PIX_FMT_UYVY) &&
- (pixfmt->pixelformat != V4L2_PIX_FMT_NV12))
- /* choose default as V4L2_PIX_FMT_UYVY */
- pixfmt->pixelformat = V4L2_PIX_FMT_UYVY;
-
- /* Check the field format */
- if ((pixfmt->field != V4L2_FIELD_INTERLACED) &&
- (pixfmt->field != V4L2_FIELD_NONE)) {
- if (vpbe_dev->current_timings.interlaced)
- pixfmt->field = V4L2_FIELD_INTERLACED;
- else
- pixfmt->field = V4L2_FIELD_NONE;
- }
-
- if (pixfmt->field == V4L2_FIELD_INTERLACED)
- min_height = 2;
-
- if (pixfmt->pixelformat == V4L2_PIX_FMT_NV12)
- bpp = 1;
- else
- bpp = 2;
-
- max_width = vpbe_dev->current_timings.xres;
- max_height = vpbe_dev->current_timings.yres;
-
- min_width /= bpp;
-
- if (!pixfmt->width || (pixfmt->width < min_width) ||
- (pixfmt->width > max_width)) {
- pixfmt->width = vpbe_dev->current_timings.xres;
- }
-
- if (!pixfmt->height || (pixfmt->height < min_height) ||
- (pixfmt->height > max_height)) {
- pixfmt->height = vpbe_dev->current_timings.yres;
- }
-
- if (pixfmt->bytesperline < (pixfmt->width * bpp))
- pixfmt->bytesperline = pixfmt->width * bpp;
-
- /* Make the bytesperline 32 byte aligned */
- pixfmt->bytesperline = ((pixfmt->width * bpp + 31) & ~31);
-
- if (pixfmt->pixelformat == V4L2_PIX_FMT_NV12)
- pixfmt->sizeimage = pixfmt->bytesperline * pixfmt->height +
- (pixfmt->bytesperline * pixfmt->height >> 1);
- else
- pixfmt->sizeimage = pixfmt->bytesperline * pixfmt->height;
-
- return 0;
-}
-
-static int vpbe_display_querycap(struct file *file, void *priv,
- struct v4l2_capability *cap)
-{
- struct vpbe_layer *layer = video_drvdata(file);
- struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev;
-
- snprintf(cap->driver, sizeof(cap->driver), "%s",
- dev_name(vpbe_dev->pdev));
- strscpy(cap->card, vpbe_dev->cfg->module_name, sizeof(cap->card));
-
- return 0;
-}
-
-static int vpbe_display_s_selection(struct file *file, void *priv,
- struct v4l2_selection *sel)
-{
- struct vpbe_layer *layer = video_drvdata(file);
- struct vpbe_display *disp_dev = layer->disp_dev;
- struct vpbe_device *vpbe_dev = disp_dev->vpbe_dev;
- struct osd_layer_config *cfg = &layer->layer_info.config;
- struct osd_state *osd_device = disp_dev->osd_device;
- struct v4l2_rect rect = sel->r;
- int ret;
-
- v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev,
- "VIDIOC_S_SELECTION, layer id = %d\n", layer->device_id);
-
- if (sel->type != V4L2_BUF_TYPE_VIDEO_OUTPUT ||
- sel->target != V4L2_SEL_TGT_CROP)
- return -EINVAL;
-
- if (rect.top < 0)
- rect.top = 0;
- if (rect.left < 0)
- rect.left = 0;
-
- vpbe_disp_check_window_params(disp_dev, &rect);
-
- osd_device->ops.get_layer_config(osd_device,
- layer->layer_info.id, cfg);
-
- vpbe_disp_calculate_scale_factor(disp_dev, layer,
- rect.width,
- rect.height);
- vpbe_disp_adj_position(disp_dev, layer, rect.top,
- rect.left);
- ret = osd_device->ops.set_layer_config(osd_device,
- layer->layer_info.id, cfg);
- if (ret < 0) {
- v4l2_err(&vpbe_dev->v4l2_dev,
- "Error in set layer config:\n");
- return -EINVAL;
- }
-
- /* apply zooming and h or v expansion */
- osd_device->ops.set_zoom(osd_device,
- layer->layer_info.id,
- layer->layer_info.h_zoom,
- layer->layer_info.v_zoom);
- ret = osd_device->ops.set_vid_expansion(osd_device,
- layer->layer_info.h_exp,
- layer->layer_info.v_exp);
- if (ret < 0) {
- v4l2_err(&vpbe_dev->v4l2_dev,
- "Error in set vid expansion:\n");
- return -EINVAL;
- }
-
- if ((layer->layer_info.h_zoom != ZOOM_X1) ||
- (layer->layer_info.v_zoom != ZOOM_X1) ||
- (layer->layer_info.h_exp != H_EXP_OFF) ||
- (layer->layer_info.v_exp != V_EXP_OFF))
- /* Enable expansion filter */
- osd_device->ops.set_interpolation_filter(osd_device, 1);
- else
- osd_device->ops.set_interpolation_filter(osd_device, 0);
-
- sel->r = rect;
- return 0;
-}
-
-static int vpbe_display_g_selection(struct file *file, void *priv,
- struct v4l2_selection *sel)
-{
- struct vpbe_layer *layer = video_drvdata(file);
- struct osd_layer_config *cfg = &layer->layer_info.config;
- struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev;
- struct osd_state *osd_device = layer->disp_dev->osd_device;
- struct v4l2_rect *rect = &sel->r;
-
- v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev,
- "VIDIOC_G_SELECTION, layer id = %d\n",
- layer->device_id);
-
- if (sel->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
- return -EINVAL;
-
- switch (sel->target) {
- case V4L2_SEL_TGT_CROP:
- osd_device->ops.get_layer_config(osd_device,
- layer->layer_info.id, cfg);
- rect->top = cfg->ypos;
- rect->left = cfg->xpos;
- rect->width = cfg->xsize;
- rect->height = cfg->ysize;
- break;
- case V4L2_SEL_TGT_CROP_DEFAULT:
- case V4L2_SEL_TGT_CROP_BOUNDS:
- rect->left = 0;
- rect->top = 0;
- rect->width = vpbe_dev->current_timings.xres;
- rect->height = vpbe_dev->current_timings.yres;
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int vpbe_display_g_pixelaspect(struct file *file, void *priv,
- int type, struct v4l2_fract *f)
-{
- struct vpbe_layer *layer = video_drvdata(file);
- struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev;
-
- v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "VIDIOC_CROPCAP ioctl\n");
-
- if (type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
- return -EINVAL;
-
- *f = vpbe_dev->current_timings.aspect;
- return 0;
-}
-
-static int vpbe_display_g_fmt(struct file *file, void *priv,
- struct v4l2_format *fmt)
-{
- struct vpbe_layer *layer = video_drvdata(file);
- struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev;
-
- v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev,
- "VIDIOC_G_FMT, layer id = %d\n",
- layer->device_id);
-
- /* If buffer type is video output */
- if (V4L2_BUF_TYPE_VIDEO_OUTPUT != fmt->type) {
- v4l2_err(&vpbe_dev->v4l2_dev, "invalid type\n");
- return -EINVAL;
- }
- /* Fill in the information about format */
- fmt->fmt.pix = layer->pix_fmt;
-
- return 0;
-}
-
-static int vpbe_display_enum_fmt(struct file *file, void *priv,
- struct v4l2_fmtdesc *fmt)
-{
- struct vpbe_layer *layer = video_drvdata(file);
- struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev;
-
- v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev,
- "VIDIOC_ENUM_FMT, layer id = %d\n",
- layer->device_id);
- if (fmt->index > 1) {
- v4l2_err(&vpbe_dev->v4l2_dev, "Invalid format index\n");
- return -EINVAL;
- }
-
- /* Fill in the information about format */
- if (fmt->index == 0)
- fmt->pixelformat = V4L2_PIX_FMT_UYVY;
- else
- fmt->pixelformat = V4L2_PIX_FMT_NV12;
-
- return 0;
-}
-
-static int vpbe_display_s_fmt(struct file *file, void *priv,
- struct v4l2_format *fmt)
-{
- struct vpbe_layer *layer = video_drvdata(file);
- struct vpbe_display *disp_dev = layer->disp_dev;
- struct vpbe_device *vpbe_dev = disp_dev->vpbe_dev;
- struct osd_layer_config *cfg = &layer->layer_info.config;
- struct v4l2_pix_format *pixfmt = &fmt->fmt.pix;
- struct osd_state *osd_device = disp_dev->osd_device;
- int ret;
-
- v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev,
- "VIDIOC_S_FMT, layer id = %d\n",
- layer->device_id);
-
- if (vb2_is_busy(&layer->buffer_queue))
- return -EBUSY;
-
- if (V4L2_BUF_TYPE_VIDEO_OUTPUT != fmt->type) {
- v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "invalid type\n");
- return -EINVAL;
- }
- /* Check for valid pixel format */
- ret = vpbe_try_format(disp_dev, pixfmt, 1);
- if (ret)
- return ret;
-
- /* YUV420 is requested, check availability of the
- other video window */
-
- layer->pix_fmt = *pixfmt;
- if (pixfmt->pixelformat == V4L2_PIX_FMT_NV12) {
- struct vpbe_layer *otherlayer;
-
- otherlayer = _vpbe_display_get_other_win_layer(disp_dev, layer);
- /* if other layer is available, only
- * claim it, do not configure it
- */
- ret = osd_device->ops.request_layer(osd_device,
- otherlayer->layer_info.id);
- if (ret < 0) {
- v4l2_err(&vpbe_dev->v4l2_dev,
- "Display Manager failed to allocate layer\n");
- return -EBUSY;
- }
- }
-
- /* Get osd layer config */
- osd_device->ops.get_layer_config(osd_device,
- layer->layer_info.id, cfg);
- /* Store the pixel format in the layer object */
- cfg->xsize = pixfmt->width;
- cfg->ysize = pixfmt->height;
- cfg->line_length = pixfmt->bytesperline;
- cfg->ypos = 0;
- cfg->xpos = 0;
- cfg->interlaced = vpbe_dev->current_timings.interlaced;
-
- if (V4L2_PIX_FMT_UYVY == pixfmt->pixelformat)
- cfg->pixfmt = PIXFMT_YCBCRI;
-
- /* Change of the default pixel format for both video windows */
- if (V4L2_PIX_FMT_NV12 == pixfmt->pixelformat) {
- struct vpbe_layer *otherlayer;
- cfg->pixfmt = PIXFMT_NV12;
- otherlayer = _vpbe_display_get_other_win_layer(disp_dev,
- layer);
- otherlayer->layer_info.config.pixfmt = PIXFMT_NV12;
- }
-
- /* Set the layer config in the osd window */
- ret = osd_device->ops.set_layer_config(osd_device,
- layer->layer_info.id, cfg);
- if (ret < 0) {
- v4l2_err(&vpbe_dev->v4l2_dev,
- "Error in S_FMT params:\n");
- return -EINVAL;
- }
-
- /* Readback and fill the local copy of current pix format */
- osd_device->ops.get_layer_config(osd_device,
- layer->layer_info.id, cfg);
-
- return 0;
-}
-
-static int vpbe_display_try_fmt(struct file *file, void *priv,
- struct v4l2_format *fmt)
-{
- struct vpbe_layer *layer = video_drvdata(file);
- struct vpbe_display *disp_dev = layer->disp_dev;
- struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev;
- struct v4l2_pix_format *pixfmt = &fmt->fmt.pix;
-
- v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "VIDIOC_TRY_FMT\n");
-
- if (V4L2_BUF_TYPE_VIDEO_OUTPUT != fmt->type) {
- v4l2_err(&vpbe_dev->v4l2_dev, "invalid type\n");
- return -EINVAL;
- }
-
- /* Check for valid field format */
- return vpbe_try_format(disp_dev, pixfmt, 0);
-
-}
-
-/*
- * vpbe_display_s_std - Set the given standard in the encoder
- *
- * Sets the standard if supported by the current encoder. Return the status.
- * 0 - success & -EINVAL on error
- */
-static int vpbe_display_s_std(struct file *file, void *priv,
- v4l2_std_id std_id)
-{
- struct vpbe_layer *layer = video_drvdata(file);
- struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev;
- int ret;
-
- v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "VIDIOC_S_STD\n");
-
- if (vb2_is_busy(&layer->buffer_queue))
- return -EBUSY;
-
- if (vpbe_dev->ops.s_std) {
- ret = vpbe_dev->ops.s_std(vpbe_dev, std_id);
- if (ret) {
- v4l2_err(&vpbe_dev->v4l2_dev,
- "Failed to set standard for sub devices\n");
- return -EINVAL;
- }
- } else {
- return -EINVAL;
- }
-
- return 0;
-}
-
-/*
- * vpbe_display_g_std - Get the standard in the current encoder
- *
- * Get the standard in the current encoder. Return the status. 0 - success
- * -EINVAL on error
- */
-static int vpbe_display_g_std(struct file *file, void *priv,
- v4l2_std_id *std_id)
-{
- struct vpbe_layer *layer = video_drvdata(file);
- struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev;
-
- v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "VIDIOC_G_STD\n");
-
- /* Get the standard from the current encoder */
- if (vpbe_dev->current_timings.timings_type & VPBE_ENC_STD) {
- *std_id = vpbe_dev->current_timings.std_id;
- return 0;
- }
-
- return -EINVAL;
-}
-
-/*
- * vpbe_display_enum_output - enumerate outputs
- *
- * Enumerates the outputs available at the vpbe display
- * returns the status, -EINVAL if end of output list
- */
-static int vpbe_display_enum_output(struct file *file, void *priv,
- struct v4l2_output *output)
-{
- struct vpbe_layer *layer = video_drvdata(file);
- struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev;
- int ret;
-
- v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "VIDIOC_ENUM_OUTPUT\n");
-
- /* Enumerate outputs */
- if (!vpbe_dev->ops.enum_outputs)
- return -EINVAL;
-
- ret = vpbe_dev->ops.enum_outputs(vpbe_dev, output);
- if (ret) {
- v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev,
- "Failed to enumerate outputs\n");
- return -EINVAL;
- }
-
- return 0;
-}
-
-/*
- * vpbe_display_s_output - Set output to
- * the output specified by the index
- */
-static int vpbe_display_s_output(struct file *file, void *priv,
- unsigned int i)
-{
- struct vpbe_layer *layer = video_drvdata(file);
- struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev;
- int ret;
-
- v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "VIDIOC_S_OUTPUT\n");
-
- if (vb2_is_busy(&layer->buffer_queue))
- return -EBUSY;
-
- if (!vpbe_dev->ops.set_output)
- return -EINVAL;
-
- ret = vpbe_dev->ops.set_output(vpbe_dev, i);
- if (ret) {
- v4l2_err(&vpbe_dev->v4l2_dev,
- "Failed to set output for sub devices\n");
- return -EINVAL;
- }
-
- return 0;
-}
-
-/*
- * vpbe_display_g_output - Get output from subdevice
- * for a given by the index
- */
-static int vpbe_display_g_output(struct file *file, void *priv,
- unsigned int *i)
-{
- struct vpbe_layer *layer = video_drvdata(file);
- struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev;
-
- v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "VIDIOC_G_OUTPUT\n");
- /* Get the standard from the current encoder */
- *i = vpbe_dev->current_out_index;
-
- return 0;
-}
-
-/*
- * vpbe_display_enum_dv_timings - Enumerate the dv timings
- *
- * enum the timings in the current encoder. Return the status. 0 - success
- * -EINVAL on error
- */
-static int
-vpbe_display_enum_dv_timings(struct file *file, void *priv,
- struct v4l2_enum_dv_timings *timings)
-{
- struct vpbe_layer *layer = video_drvdata(file);
- struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev;
- int ret;
-
- v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "VIDIOC_ENUM_DV_TIMINGS\n");
-
- /* Enumerate outputs */
- if (!vpbe_dev->ops.enum_dv_timings)
- return -EINVAL;
-
- ret = vpbe_dev->ops.enum_dv_timings(vpbe_dev, timings);
- if (ret) {
- v4l2_err(&vpbe_dev->v4l2_dev,
- "Failed to enumerate dv timings info\n");
- return -EINVAL;
- }
-
- return 0;
-}
-
-/*
- * vpbe_display_s_dv_timings - Set the dv timings
- *
- * Set the timings in the current encoder. Return the status. 0 - success
- * -EINVAL on error
- */
-static int
-vpbe_display_s_dv_timings(struct file *file, void *priv,
- struct v4l2_dv_timings *timings)
-{
- struct vpbe_layer *layer = video_drvdata(file);
- struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev;
- int ret;
-
- v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "VIDIOC_S_DV_TIMINGS\n");
-
- if (vb2_is_busy(&layer->buffer_queue))
- return -EBUSY;
-
- /* Set the given standard in the encoder */
- if (!vpbe_dev->ops.s_dv_timings)
- return -EINVAL;
-
- ret = vpbe_dev->ops.s_dv_timings(vpbe_dev, timings);
- if (ret) {
- v4l2_err(&vpbe_dev->v4l2_dev,
- "Failed to set the dv timings info\n");
- return -EINVAL;
- }
-
- return 0;
-}
-
-/*
- * vpbe_display_g_dv_timings - Set the dv timings
- *
- * Get the timings in the current encoder. Return the status. 0 - success
- * -EINVAL on error
- */
-static int
-vpbe_display_g_dv_timings(struct file *file, void *priv,
- struct v4l2_dv_timings *dv_timings)
-{
- struct vpbe_layer *layer = video_drvdata(file);
- struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev;
-
- v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "VIDIOC_G_DV_TIMINGS\n");
-
- /* Get the given standard in the encoder */
-
- if (vpbe_dev->current_timings.timings_type &
- VPBE_ENC_DV_TIMINGS) {
- *dv_timings = vpbe_dev->current_timings.dv_timings;
- } else {
- return -EINVAL;
- }
-
- return 0;
-}
-
-/*
- * vpbe_display_open()
- * It creates object of file handle structure and stores it in private_data
- * member of filepointer
- */
-static int vpbe_display_open(struct file *file)
-{
- struct vpbe_layer *layer = video_drvdata(file);
- struct vpbe_display *disp_dev = layer->disp_dev;
- struct vpbe_device *vpbe_dev = disp_dev->vpbe_dev;
- struct osd_state *osd_device = disp_dev->osd_device;
- int err;
-
- /* creating context for file descriptor */
- err = v4l2_fh_open(file);
- if (err) {
- v4l2_err(&vpbe_dev->v4l2_dev, "v4l2_fh_open failed\n");
- return err;
- }
-
- /* leaving if layer is already initialized */
- if (!v4l2_fh_is_singular_file(file))
- return err;
-
- if (!layer->usrs) {
- if (mutex_lock_interruptible(&layer->opslock))
- return -ERESTARTSYS;
- /* First claim the layer for this device */
- err = osd_device->ops.request_layer(osd_device,
- layer->layer_info.id);
- mutex_unlock(&layer->opslock);
- if (err < 0) {
- /* Couldn't get layer */
- v4l2_err(&vpbe_dev->v4l2_dev,
- "Display Manager failed to allocate layer\n");
- v4l2_fh_release(file);
- return -EINVAL;
- }
- }
- /* Increment layer usrs counter */
- layer->usrs++;
- v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev,
- "vpbe display device opened successfully\n");
- return 0;
-}
-
-/*
- * vpbe_display_release()
- * This function deletes buffer queue, frees the buffers and the davinci
- * display file * handle
- */
-static int vpbe_display_release(struct file *file)
-{
- struct vpbe_layer *layer = video_drvdata(file);
- struct osd_layer_config *cfg = &layer->layer_info.config;
- struct vpbe_display *disp_dev = layer->disp_dev;
- struct vpbe_device *vpbe_dev = disp_dev->vpbe_dev;
- struct osd_state *osd_device = disp_dev->osd_device;
-
- v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "vpbe_display_release\n");
-
- mutex_lock(&layer->opslock);
-
- osd_device->ops.disable_layer(osd_device,
- layer->layer_info.id);
- /* Decrement layer usrs counter */
- layer->usrs--;
- /* If this file handle has initialize encoder device, reset it */
- if (!layer->usrs) {
- if (cfg->pixfmt == PIXFMT_NV12) {
- struct vpbe_layer *otherlayer;
- otherlayer =
- _vpbe_display_get_other_win_layer(disp_dev, layer);
- osd_device->ops.disable_layer(osd_device,
- otherlayer->layer_info.id);
- osd_device->ops.release_layer(osd_device,
- otherlayer->layer_info.id);
- }
- osd_device->ops.disable_layer(osd_device,
- layer->layer_info.id);
- osd_device->ops.release_layer(osd_device,
- layer->layer_info.id);
- }
-
- _vb2_fop_release(file, NULL);
- mutex_unlock(&layer->opslock);
-
- disp_dev->cbcr_ofst = 0;
-
- return 0;
-}
-
-/* vpbe capture ioctl operations */
-static const struct v4l2_ioctl_ops vpbe_ioctl_ops = {
- .vidioc_querycap = vpbe_display_querycap,
- .vidioc_g_fmt_vid_out = vpbe_display_g_fmt,
- .vidioc_enum_fmt_vid_out = vpbe_display_enum_fmt,
- .vidioc_s_fmt_vid_out = vpbe_display_s_fmt,
- .vidioc_try_fmt_vid_out = vpbe_display_try_fmt,
-
- .vidioc_reqbufs = vb2_ioctl_reqbufs,
- .vidioc_create_bufs = vb2_ioctl_create_bufs,
- .vidioc_querybuf = vb2_ioctl_querybuf,
- .vidioc_qbuf = vb2_ioctl_qbuf,
- .vidioc_dqbuf = vb2_ioctl_dqbuf,
- .vidioc_streamon = vb2_ioctl_streamon,
- .vidioc_streamoff = vb2_ioctl_streamoff,
- .vidioc_expbuf = vb2_ioctl_expbuf,
-
- .vidioc_g_pixelaspect = vpbe_display_g_pixelaspect,
- .vidioc_g_selection = vpbe_display_g_selection,
- .vidioc_s_selection = vpbe_display_s_selection,
-
- .vidioc_s_std = vpbe_display_s_std,
- .vidioc_g_std = vpbe_display_g_std,
-
- .vidioc_enum_output = vpbe_display_enum_output,
- .vidioc_s_output = vpbe_display_s_output,
- .vidioc_g_output = vpbe_display_g_output,
-
- .vidioc_s_dv_timings = vpbe_display_s_dv_timings,
- .vidioc_g_dv_timings = vpbe_display_g_dv_timings,
- .vidioc_enum_dv_timings = vpbe_display_enum_dv_timings,
-};
-
-static const struct v4l2_file_operations vpbe_fops = {
- .owner = THIS_MODULE,
- .open = vpbe_display_open,
- .release = vpbe_display_release,
- .unlocked_ioctl = video_ioctl2,
- .mmap = vb2_fop_mmap,
- .poll = vb2_fop_poll,
-};
-
-static int vpbe_device_get(struct device *dev, void *data)
-{
- struct platform_device *pdev = to_platform_device(dev);
- struct vpbe_display *vpbe_disp = data;
-
- if (strcmp("vpbe_controller", pdev->name) == 0)
- vpbe_disp->vpbe_dev = platform_get_drvdata(pdev);
-
- if (strstr(pdev->name, "vpbe-osd"))
- vpbe_disp->osd_device = platform_get_drvdata(pdev);
-
- return 0;
-}
-
-static int init_vpbe_layer(int i, struct vpbe_display *disp_dev,
- struct platform_device *pdev)
-{
- struct vpbe_layer *vpbe_display_layer = NULL;
- struct video_device *vbd = NULL;
-
- /* Allocate memory for four plane display objects */
- disp_dev->dev[i] = kzalloc(sizeof(*disp_dev->dev[i]), GFP_KERNEL);
- if (!disp_dev->dev[i])
- return -ENOMEM;
-
- spin_lock_init(&disp_dev->dev[i]->irqlock);
- mutex_init(&disp_dev->dev[i]->opslock);
-
- /* Get the pointer to the layer object */
- vpbe_display_layer = disp_dev->dev[i];
- vbd = &vpbe_display_layer->video_dev;
- /* Initialize field of video device */
- vbd->release = video_device_release_empty;
- vbd->fops = &vpbe_fops;
- vbd->ioctl_ops = &vpbe_ioctl_ops;
- vbd->minor = -1;
- vbd->v4l2_dev = &disp_dev->vpbe_dev->v4l2_dev;
- vbd->lock = &vpbe_display_layer->opslock;
- vbd->vfl_dir = VFL_DIR_TX;
- vbd->device_caps = V4L2_CAP_VIDEO_OUTPUT | V4L2_CAP_STREAMING;
-
- if (disp_dev->vpbe_dev->current_timings.timings_type &
- VPBE_ENC_STD)
- vbd->tvnorms = (V4L2_STD_525_60 | V4L2_STD_625_50);
-
- snprintf(vbd->name, sizeof(vbd->name),
- "DaVinci_VPBE Display_DRIVER_V%d.%d.%d",
- (VPBE_DISPLAY_VERSION_CODE >> 16) & 0xff,
- (VPBE_DISPLAY_VERSION_CODE >> 8) & 0xff,
- (VPBE_DISPLAY_VERSION_CODE) & 0xff);
-
- vpbe_display_layer->device_id = i;
-
- vpbe_display_layer->layer_info.id =
- ((i == VPBE_DISPLAY_DEVICE_0) ? WIN_VID0 : WIN_VID1);
-
-
- return 0;
-}
-
-static int register_device(struct vpbe_layer *vpbe_display_layer,
- struct vpbe_display *disp_dev,
- struct platform_device *pdev)
-{
- int err;
-
- v4l2_info(&disp_dev->vpbe_dev->v4l2_dev,
- "Trying to register VPBE display device.\n");
- v4l2_info(&disp_dev->vpbe_dev->v4l2_dev,
- "layer=%p,layer->video_dev=%p\n",
- vpbe_display_layer,
- &vpbe_display_layer->video_dev);
-
- vpbe_display_layer->video_dev.queue = &vpbe_display_layer->buffer_queue;
- err = video_register_device(&vpbe_display_layer->video_dev,
- VFL_TYPE_VIDEO,
- -1);
- if (err)
- return -ENODEV;
-
- vpbe_display_layer->disp_dev = disp_dev;
- /* set the driver data in platform device */
- platform_set_drvdata(pdev, disp_dev);
- video_set_drvdata(&vpbe_display_layer->video_dev,
- vpbe_display_layer);
-
- return 0;
-}
-
-
-
-/*
- * vpbe_display_probe()
- * This function creates device entries by register itself to the V4L2 driver
- * and initializes fields of each layer objects
- */
-static int vpbe_display_probe(struct platform_device *pdev)
-{
- struct vpbe_display *disp_dev;
- struct v4l2_device *v4l2_dev;
- struct resource *res = NULL;
- struct vb2_queue *q;
- int k;
- int i;
- int err;
- int irq;
-
- printk(KERN_DEBUG "vpbe_display_probe\n");
- /* Allocate memory for vpbe_display */
- disp_dev = devm_kzalloc(&pdev->dev, sizeof(*disp_dev), GFP_KERNEL);
- if (!disp_dev)
- return -ENOMEM;
-
- spin_lock_init(&disp_dev->dma_queue_lock);
- /*
- * Scan all the platform devices to find the vpbe
- * controller device and get the vpbe_dev object
- */
- err = bus_for_each_dev(&platform_bus_type, NULL, disp_dev,
- vpbe_device_get);
- if (err < 0)
- return err;
-
- v4l2_dev = &disp_dev->vpbe_dev->v4l2_dev;
- /* Initialize the vpbe display controller */
- if (disp_dev->vpbe_dev->ops.initialize) {
- err = disp_dev->vpbe_dev->ops.initialize(&pdev->dev,
- disp_dev->vpbe_dev);
- if (err) {
- v4l2_err(v4l2_dev, "Error initing vpbe\n");
- err = -ENOMEM;
- goto probe_out;
- }
- }
-
- for (i = 0; i < VPBE_DISPLAY_MAX_DEVICES; i++) {
- if (init_vpbe_layer(i, disp_dev, pdev)) {
- err = -ENODEV;
- goto probe_out;
- }
- }
-
- res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
- if (!res) {
- v4l2_err(v4l2_dev, "Unable to get VENC interrupt resource\n");
- err = -ENODEV;
- goto probe_out;
- }
-
- irq = res->start;
- err = devm_request_irq(&pdev->dev, irq, venc_isr, 0,
- VPBE_DISPLAY_DRIVER, disp_dev);
- if (err) {
- v4l2_err(v4l2_dev, "VPBE IRQ request failed\n");
- goto probe_out;
- }
-
- for (i = 0; i < VPBE_DISPLAY_MAX_DEVICES; i++) {
- /* initialize vb2 queue */
- q = &disp_dev->dev[i]->buffer_queue;
- memset(q, 0, sizeof(*q));
- q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
- q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
- q->drv_priv = disp_dev->dev[i];
- q->ops = &video_qops;
- q->mem_ops = &vb2_dma_contig_memops;
- q->buf_struct_size = sizeof(struct vpbe_disp_buffer);
- q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
- q->min_buffers_needed = 1;
- q->lock = &disp_dev->dev[i]->opslock;
- q->dev = disp_dev->vpbe_dev->pdev;
- err = vb2_queue_init(q);
- if (err) {
- v4l2_err(v4l2_dev, "vb2_queue_init() failed\n");
- goto probe_out;
- }
-
- INIT_LIST_HEAD(&disp_dev->dev[i]->dma_queue);
-
- if (register_device(disp_dev->dev[i], disp_dev, pdev)) {
- err = -ENODEV;
- goto probe_out;
- }
- }
-
- v4l2_dbg(1, debug, v4l2_dev,
- "Successfully completed the probing of vpbe v4l2 device\n");
-
- return 0;
-
-probe_out:
- for (k = 0; k < VPBE_DISPLAY_MAX_DEVICES; k++) {
- /* Unregister video device */
- if (disp_dev->dev[k]) {
- video_unregister_device(&disp_dev->dev[k]->video_dev);
- kfree(disp_dev->dev[k]);
- }
- }
- return err;
-}
-
-/*
- * vpbe_display_remove()
- * It un-register hardware layer from V4L2 driver
- */
-static int vpbe_display_remove(struct platform_device *pdev)
-{
- struct vpbe_layer *vpbe_display_layer;
- struct vpbe_display *disp_dev = platform_get_drvdata(pdev);
- struct vpbe_device *vpbe_dev = disp_dev->vpbe_dev;
- int i;
-
- v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "vpbe_display_remove\n");
-
- /* deinitialize the vpbe display controller */
- if (vpbe_dev->ops.deinitialize)
- vpbe_dev->ops.deinitialize(&pdev->dev, vpbe_dev);
- /* un-register device */
- for (i = 0; i < VPBE_DISPLAY_MAX_DEVICES; i++) {
- /* Get the pointer to the layer object */
- vpbe_display_layer = disp_dev->dev[i];
- /* Unregister video device */
- video_unregister_device(&vpbe_display_layer->video_dev);
-
- }
- for (i = 0; i < VPBE_DISPLAY_MAX_DEVICES; i++) {
- kfree(disp_dev->dev[i]);
- disp_dev->dev[i] = NULL;
- }
-
- return 0;
-}
-
-static struct platform_driver vpbe_display_driver = {
- .driver = {
- .name = VPBE_DISPLAY_DRIVER,
- .bus = &platform_bus_type,
- },
- .probe = vpbe_display_probe,
- .remove = vpbe_display_remove,
-};
-
-module_platform_driver(vpbe_display_driver);
-
-MODULE_DESCRIPTION("TI DM644x/DM355/DM365 VPBE Display controller");
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Texas Instruments");
diff --git a/drivers/media/platform/ti/davinci/vpbe_osd.c b/drivers/media/platform/ti/davinci/vpbe_osd.c
deleted file mode 100644
index 32f7ef547c82..000000000000
--- a/drivers/media/platform/ti/davinci/vpbe_osd.c
+++ /dev/null
@@ -1,1582 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2007-2010 Texas Instruments Inc
- * Copyright (C) 2007 MontaVista Software, Inc.
- *
- * Andy Lowe (alowe@mvista.com), MontaVista Software
- * - Initial version
- * Murali Karicheri (mkaricheri@gmail.com), Texas Instruments Ltd.
- * - ported to sub device interface
- */
-#include <linux/module.h>
-#include <linux/mod_devicetable.h>
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/clk.h>
-#include <linux/slab.h>
-
-#include <media/davinci/vpss.h>
-#include <media/v4l2-device.h>
-#include <media/davinci/vpbe_types.h>
-#include <media/davinci/vpbe_osd.h>
-
-#include <linux/io.h>
-#include "vpbe_osd_regs.h"
-
-#define MODULE_NAME "davinci-vpbe-osd"
-
-static const struct platform_device_id vpbe_osd_devtype[] = {
- {
- .name = DM644X_VPBE_OSD_SUBDEV_NAME,
- .driver_data = VPBE_VERSION_1,
- }, {
- .name = DM365_VPBE_OSD_SUBDEV_NAME,
- .driver_data = VPBE_VERSION_2,
- }, {
- .name = DM355_VPBE_OSD_SUBDEV_NAME,
- .driver_data = VPBE_VERSION_3,
- },
- {
- /* sentinel */
- }
-};
-
-MODULE_DEVICE_TABLE(platform, vpbe_osd_devtype);
-
-/* register access routines */
-static inline u32 __always_unused osd_read(struct osd_state *sd, u32 offset)
-{
- struct osd_state *osd = sd;
-
- return readl(osd->osd_base + offset);
-}
-
-static inline u32 osd_write(struct osd_state *sd, u32 val, u32 offset)
-{
- struct osd_state *osd = sd;
-
- writel(val, osd->osd_base + offset);
-
- return val;
-}
-
-static inline u32 osd_set(struct osd_state *sd, u32 mask, u32 offset)
-{
- struct osd_state *osd = sd;
-
- void __iomem *addr = osd->osd_base + offset;
- u32 val = readl(addr) | mask;
-
- writel(val, addr);
-
- return val;
-}
-
-static inline u32 osd_clear(struct osd_state *sd, u32 mask, u32 offset)
-{
- struct osd_state *osd = sd;
-
- void __iomem *addr = osd->osd_base + offset;
- u32 val = readl(addr) & ~mask;
-
- writel(val, addr);
-
- return val;
-}
-
-static inline u32 osd_modify(struct osd_state *sd, u32 mask, u32 val,
- u32 offset)
-{
- struct osd_state *osd = sd;
-
- void __iomem *addr = osd->osd_base + offset;
- u32 new_val = (readl(addr) & ~mask) | (val & mask);
-
- writel(new_val, addr);
-
- return new_val;
-}
-
-/* define some macros for layer and pixfmt classification */
-#define is_osd_win(layer) (((layer) == WIN_OSD0) || ((layer) == WIN_OSD1))
-#define is_vid_win(layer) (((layer) == WIN_VID0) || ((layer) == WIN_VID1))
-#define is_rgb_pixfmt(pixfmt) \
- (((pixfmt) == PIXFMT_RGB565) || ((pixfmt) == PIXFMT_RGB888))
-#define is_yc_pixfmt(pixfmt) \
- (((pixfmt) == PIXFMT_YCBCRI) || ((pixfmt) == PIXFMT_YCRCBI) || \
- ((pixfmt) == PIXFMT_NV12))
-#define MAX_WIN_SIZE OSD_VIDWIN0XP_V0X
-#define MAX_LINE_LENGTH (OSD_VIDWIN0OFST_V0LO << 5)
-
-/**
- * _osd_dm6446_vid0_pingpong() - field inversion fix for DM6446
- * @sd: ptr to struct osd_state
- * @field_inversion: inversion flag
- * @fb_base_phys: frame buffer address
- * @lconfig: ptr to layer config
- *
- * This routine implements a workaround for the field signal inversion silicon
- * erratum described in Advisory 1.3.8 for the DM6446. The fb_base_phys and
- * lconfig parameters apply to the vid0 window. This routine should be called
- * whenever the vid0 layer configuration or start address is modified, or when
- * the OSD field inversion setting is modified.
- * Returns: 1 if the ping-pong buffers need to be toggled in the vsync isr, or
- * 0 otherwise
- */
-static int _osd_dm6446_vid0_pingpong(struct osd_state *sd,
- int field_inversion,
- unsigned long fb_base_phys,
- const struct osd_layer_config *lconfig)
-{
- struct osd_platform_data *pdata;
-
- pdata = (struct osd_platform_data *)sd->dev->platform_data;
- if (pdata != NULL && pdata->field_inv_wa_enable) {
-
- if (!field_inversion || !lconfig->interlaced) {
- osd_write(sd, fb_base_phys & ~0x1F, OSD_VIDWIN0ADR);
- osd_write(sd, fb_base_phys & ~0x1F, OSD_PPVWIN0ADR);
- osd_modify(sd, OSD_MISCCTL_PPSW | OSD_MISCCTL_PPRV, 0,
- OSD_MISCCTL);
- return 0;
- } else {
- unsigned miscctl = OSD_MISCCTL_PPRV;
-
- osd_write(sd,
- (fb_base_phys & ~0x1F) - lconfig->line_length,
- OSD_VIDWIN0ADR);
- osd_write(sd,
- (fb_base_phys & ~0x1F) + lconfig->line_length,
- OSD_PPVWIN0ADR);
- osd_modify(sd,
- OSD_MISCCTL_PPSW | OSD_MISCCTL_PPRV, miscctl,
- OSD_MISCCTL);
-
- return 1;
- }
- }
-
- return 0;
-}
-
-static void _osd_set_field_inversion(struct osd_state *sd, int enable)
-{
- unsigned fsinv = 0;
-
- if (enable)
- fsinv = OSD_MODE_FSINV;
-
- osd_modify(sd, OSD_MODE_FSINV, fsinv, OSD_MODE);
-}
-
-static void _osd_set_blink_attribute(struct osd_state *sd, int enable,
- enum osd_blink_interval blink)
-{
- u32 osdatrmd = 0;
-
- if (enable) {
- osdatrmd |= OSD_OSDATRMD_BLNK;
- osdatrmd |= blink << OSD_OSDATRMD_BLNKINT_SHIFT;
- }
- /* caller must ensure that OSD1 is configured in attribute mode */
- osd_modify(sd, OSD_OSDATRMD_BLNKINT | OSD_OSDATRMD_BLNK, osdatrmd,
- OSD_OSDATRMD);
-}
-
-static void _osd_set_rom_clut(struct osd_state *sd,
- enum osd_rom_clut rom_clut)
-{
- if (rom_clut == ROM_CLUT0)
- osd_clear(sd, OSD_MISCCTL_RSEL, OSD_MISCCTL);
- else
- osd_set(sd, OSD_MISCCTL_RSEL, OSD_MISCCTL);
-}
-
-static void _osd_set_palette_map(struct osd_state *sd,
- enum osd_win_layer osdwin,
- unsigned char pixel_value,
- unsigned char clut_index,
- enum osd_pix_format pixfmt)
-{
- static const int map_2bpp[] = { 0, 5, 10, 15 };
- static const int map_1bpp[] = { 0, 15 };
- int bmp_offset;
- int bmp_shift;
- int bmp_mask;
- int bmp_reg;
-
- switch (pixfmt) {
- case PIXFMT_1BPP:
- bmp_reg = map_1bpp[pixel_value & 0x1];
- break;
- case PIXFMT_2BPP:
- bmp_reg = map_2bpp[pixel_value & 0x3];
- break;
- case PIXFMT_4BPP:
- bmp_reg = pixel_value & 0xf;
- break;
- default:
- return;
- }
-
- switch (osdwin) {
- case OSDWIN_OSD0:
- bmp_offset = OSD_W0BMP01 + (bmp_reg >> 1) * sizeof(u32);
- break;
- case OSDWIN_OSD1:
- bmp_offset = OSD_W1BMP01 + (bmp_reg >> 1) * sizeof(u32);
- break;
- default:
- return;
- }
-
- if (bmp_reg & 1) {
- bmp_shift = 8;
- bmp_mask = 0xff << 8;
- } else {
- bmp_shift = 0;
- bmp_mask = 0xff;
- }
-
- osd_modify(sd, bmp_mask, clut_index << bmp_shift, bmp_offset);
-}
-
-static void _osd_set_rec601_attenuation(struct osd_state *sd,
- enum osd_win_layer osdwin, int enable)
-{
- switch (osdwin) {
- case OSDWIN_OSD0:
- osd_modify(sd, OSD_OSDWIN0MD_ATN0E,
- enable ? OSD_OSDWIN0MD_ATN0E : 0,
- OSD_OSDWIN0MD);
- if (sd->vpbe_type == VPBE_VERSION_1)
- osd_modify(sd, OSD_OSDWIN0MD_ATN0E,
- enable ? OSD_OSDWIN0MD_ATN0E : 0,
- OSD_OSDWIN0MD);
- else if ((sd->vpbe_type == VPBE_VERSION_3) ||
- (sd->vpbe_type == VPBE_VERSION_2))
- osd_modify(sd, OSD_EXTMODE_ATNOSD0EN,
- enable ? OSD_EXTMODE_ATNOSD0EN : 0,
- OSD_EXTMODE);
- break;
- case OSDWIN_OSD1:
- osd_modify(sd, OSD_OSDWIN1MD_ATN1E,
- enable ? OSD_OSDWIN1MD_ATN1E : 0,
- OSD_OSDWIN1MD);
- if (sd->vpbe_type == VPBE_VERSION_1)
- osd_modify(sd, OSD_OSDWIN1MD_ATN1E,
- enable ? OSD_OSDWIN1MD_ATN1E : 0,
- OSD_OSDWIN1MD);
- else if ((sd->vpbe_type == VPBE_VERSION_3) ||
- (sd->vpbe_type == VPBE_VERSION_2))
- osd_modify(sd, OSD_EXTMODE_ATNOSD1EN,
- enable ? OSD_EXTMODE_ATNOSD1EN : 0,
- OSD_EXTMODE);
- break;
- }
-}
-
-static void _osd_set_blending_factor(struct osd_state *sd,
- enum osd_win_layer osdwin,
- enum osd_blending_factor blend)
-{
- switch (osdwin) {
- case OSDWIN_OSD0:
- osd_modify(sd, OSD_OSDWIN0MD_BLND0,
- blend << OSD_OSDWIN0MD_BLND0_SHIFT, OSD_OSDWIN0MD);
- break;
- case OSDWIN_OSD1:
- osd_modify(sd, OSD_OSDWIN1MD_BLND1,
- blend << OSD_OSDWIN1MD_BLND1_SHIFT, OSD_OSDWIN1MD);
- break;
- }
-}
-
-static void _osd_enable_rgb888_pixblend(struct osd_state *sd,
- enum osd_win_layer osdwin)
-{
-
- osd_modify(sd, OSD_MISCCTL_BLDSEL, 0, OSD_MISCCTL);
- switch (osdwin) {
- case OSDWIN_OSD0:
- osd_modify(sd, OSD_EXTMODE_OSD0BLDCHR,
- OSD_EXTMODE_OSD0BLDCHR, OSD_EXTMODE);
- break;
- case OSDWIN_OSD1:
- osd_modify(sd, OSD_EXTMODE_OSD1BLDCHR,
- OSD_EXTMODE_OSD1BLDCHR, OSD_EXTMODE);
- break;
- }
-}
-
-static void _osd_enable_color_key(struct osd_state *sd,
- enum osd_win_layer osdwin,
- unsigned colorkey,
- enum osd_pix_format pixfmt)
-{
- switch (pixfmt) {
- case PIXFMT_1BPP:
- case PIXFMT_2BPP:
- case PIXFMT_4BPP:
- case PIXFMT_8BPP:
- if (sd->vpbe_type == VPBE_VERSION_3) {
- switch (osdwin) {
- case OSDWIN_OSD0:
- osd_modify(sd, OSD_TRANSPBMPIDX_BMP0,
- colorkey <<
- OSD_TRANSPBMPIDX_BMP0_SHIFT,
- OSD_TRANSPBMPIDX);
- break;
- case OSDWIN_OSD1:
- osd_modify(sd, OSD_TRANSPBMPIDX_BMP1,
- colorkey <<
- OSD_TRANSPBMPIDX_BMP1_SHIFT,
- OSD_TRANSPBMPIDX);
- break;
- }
- }
- break;
- case PIXFMT_RGB565:
- if (sd->vpbe_type == VPBE_VERSION_1)
- osd_write(sd, colorkey & OSD_TRANSPVAL_RGBTRANS,
- OSD_TRANSPVAL);
- else if (sd->vpbe_type == VPBE_VERSION_3)
- osd_write(sd, colorkey & OSD_TRANSPVALL_RGBL,
- OSD_TRANSPVALL);
- break;
- case PIXFMT_YCBCRI:
- case PIXFMT_YCRCBI:
- if (sd->vpbe_type == VPBE_VERSION_3)
- osd_modify(sd, OSD_TRANSPVALU_Y, colorkey,
- OSD_TRANSPVALU);
- break;
- case PIXFMT_RGB888:
- if (sd->vpbe_type == VPBE_VERSION_3) {
- osd_write(sd, colorkey & OSD_TRANSPVALL_RGBL,
- OSD_TRANSPVALL);
- osd_modify(sd, OSD_TRANSPVALU_RGBU, colorkey >> 16,
- OSD_TRANSPVALU);
- }
- break;
- default:
- break;
- }
-
- switch (osdwin) {
- case OSDWIN_OSD0:
- osd_set(sd, OSD_OSDWIN0MD_TE0, OSD_OSDWIN0MD);
- break;
- case OSDWIN_OSD1:
- osd_set(sd, OSD_OSDWIN1MD_TE1, OSD_OSDWIN1MD);
- break;
- }
-}
-
-static void _osd_disable_color_key(struct osd_state *sd,
- enum osd_win_layer osdwin)
-{
- switch (osdwin) {
- case OSDWIN_OSD0:
- osd_clear(sd, OSD_OSDWIN0MD_TE0, OSD_OSDWIN0MD);
- break;
- case OSDWIN_OSD1:
- osd_clear(sd, OSD_OSDWIN1MD_TE1, OSD_OSDWIN1MD);
- break;
- }
-}
-
-static void _osd_set_osd_clut(struct osd_state *sd,
- enum osd_win_layer osdwin,
- enum osd_clut clut)
-{
- u32 winmd = 0;
-
- switch (osdwin) {
- case OSDWIN_OSD0:
- if (clut == RAM_CLUT)
- winmd |= OSD_OSDWIN0MD_CLUTS0;
- osd_modify(sd, OSD_OSDWIN0MD_CLUTS0, winmd, OSD_OSDWIN0MD);
- break;
- case OSDWIN_OSD1:
- if (clut == RAM_CLUT)
- winmd |= OSD_OSDWIN1MD_CLUTS1;
- osd_modify(sd, OSD_OSDWIN1MD_CLUTS1, winmd, OSD_OSDWIN1MD);
- break;
- }
-}
-
-static void _osd_set_zoom(struct osd_state *sd, enum osd_layer layer,
- enum osd_zoom_factor h_zoom,
- enum osd_zoom_factor v_zoom)
-{
- u32 winmd = 0;
-
- switch (layer) {
- case WIN_OSD0:
- winmd |= (h_zoom << OSD_OSDWIN0MD_OHZ0_SHIFT);
- winmd |= (v_zoom << OSD_OSDWIN0MD_OVZ0_SHIFT);
- osd_modify(sd, OSD_OSDWIN0MD_OHZ0 | OSD_OSDWIN0MD_OVZ0, winmd,
- OSD_OSDWIN0MD);
- break;
- case WIN_VID0:
- winmd |= (h_zoom << OSD_VIDWINMD_VHZ0_SHIFT);
- winmd |= (v_zoom << OSD_VIDWINMD_VVZ0_SHIFT);
- osd_modify(sd, OSD_VIDWINMD_VHZ0 | OSD_VIDWINMD_VVZ0, winmd,
- OSD_VIDWINMD);
- break;
- case WIN_OSD1:
- winmd |= (h_zoom << OSD_OSDWIN1MD_OHZ1_SHIFT);
- winmd |= (v_zoom << OSD_OSDWIN1MD_OVZ1_SHIFT);
- osd_modify(sd, OSD_OSDWIN1MD_OHZ1 | OSD_OSDWIN1MD_OVZ1, winmd,
- OSD_OSDWIN1MD);
- break;
- case WIN_VID1:
- winmd |= (h_zoom << OSD_VIDWINMD_VHZ1_SHIFT);
- winmd |= (v_zoom << OSD_VIDWINMD_VVZ1_SHIFT);
- osd_modify(sd, OSD_VIDWINMD_VHZ1 | OSD_VIDWINMD_VVZ1, winmd,
- OSD_VIDWINMD);
- break;
- }
-}
-
-static void _osd_disable_layer(struct osd_state *sd, enum osd_layer layer)
-{
- switch (layer) {
- case WIN_OSD0:
- osd_clear(sd, OSD_OSDWIN0MD_OACT0, OSD_OSDWIN0MD);
- break;
- case WIN_VID0:
- osd_clear(sd, OSD_VIDWINMD_ACT0, OSD_VIDWINMD);
- break;
- case WIN_OSD1:
- /* disable attribute mode as well as disabling the window */
- osd_clear(sd, OSD_OSDWIN1MD_OASW | OSD_OSDWIN1MD_OACT1,
- OSD_OSDWIN1MD);
- break;
- case WIN_VID1:
- osd_clear(sd, OSD_VIDWINMD_ACT1, OSD_VIDWINMD);
- break;
- }
-}
-
-static void osd_disable_layer(struct osd_state *sd, enum osd_layer layer)
-{
- struct osd_state *osd = sd;
- struct osd_window_state *win = &osd->win[layer];
- unsigned long flags;
-
- spin_lock_irqsave(&osd->lock, flags);
-
- if (!win->is_enabled) {
- spin_unlock_irqrestore(&osd->lock, flags);
- return;
- }
- win->is_enabled = 0;
-
- _osd_disable_layer(sd, layer);
-
- spin_unlock_irqrestore(&osd->lock, flags);
-}
-
-static void _osd_enable_attribute_mode(struct osd_state *sd)
-{
- /* enable attribute mode for OSD1 */
- osd_set(sd, OSD_OSDWIN1MD_OASW, OSD_OSDWIN1MD);
-}
-
-static void _osd_enable_layer(struct osd_state *sd, enum osd_layer layer)
-{
- switch (layer) {
- case WIN_OSD0:
- osd_set(sd, OSD_OSDWIN0MD_OACT0, OSD_OSDWIN0MD);
- break;
- case WIN_VID0:
- osd_set(sd, OSD_VIDWINMD_ACT0, OSD_VIDWINMD);
- break;
- case WIN_OSD1:
- /* enable OSD1 and disable attribute mode */
- osd_modify(sd, OSD_OSDWIN1MD_OASW | OSD_OSDWIN1MD_OACT1,
- OSD_OSDWIN1MD_OACT1, OSD_OSDWIN1MD);
- break;
- case WIN_VID1:
- osd_set(sd, OSD_VIDWINMD_ACT1, OSD_VIDWINMD);
- break;
- }
-}
-
-static int osd_enable_layer(struct osd_state *sd, enum osd_layer layer,
- int otherwin)
-{
- struct osd_state *osd = sd;
- struct osd_window_state *win = &osd->win[layer];
- struct osd_layer_config *cfg = &win->lconfig;
- unsigned long flags;
-
- spin_lock_irqsave(&osd->lock, flags);
-
- /*
- * use otherwin flag to know this is the other vid window
- * in YUV420 mode, if is, skip this check
- */
- if (!otherwin && (!win->is_allocated ||
- !win->fb_base_phys ||
- !cfg->line_length ||
- !cfg->xsize ||
- !cfg->ysize)) {
- spin_unlock_irqrestore(&osd->lock, flags);
- return -1;
- }
-
- if (win->is_enabled) {
- spin_unlock_irqrestore(&osd->lock, flags);
- return 0;
- }
- win->is_enabled = 1;
-
- if (cfg->pixfmt != PIXFMT_OSD_ATTR)
- _osd_enable_layer(sd, layer);
- else {
- _osd_enable_attribute_mode(sd);
- _osd_set_blink_attribute(sd, osd->is_blinking, osd->blink);
- }
-
- spin_unlock_irqrestore(&osd->lock, flags);
-
- return 0;
-}
-
-#define OSD_SRC_ADDR_HIGH4 0x7800000
-#define OSD_SRC_ADDR_HIGH7 0x7F0000
-#define OSD_SRCADD_OFSET_SFT 23
-#define OSD_SRCADD_ADD_SFT 16
-#define OSD_WINADL_MASK 0xFFFF
-#define OSD_WINOFST_MASK 0x1000
-#define VPBE_REG_BASE 0x80000000
-
-static void _osd_start_layer(struct osd_state *sd, enum osd_layer layer,
- unsigned long fb_base_phys,
- unsigned long cbcr_ofst)
-{
-
- if (sd->vpbe_type == VPBE_VERSION_1) {
- switch (layer) {
- case WIN_OSD0:
- osd_write(sd, fb_base_phys & ~0x1F, OSD_OSDWIN0ADR);
- break;
- case WIN_VID0:
- osd_write(sd, fb_base_phys & ~0x1F, OSD_VIDWIN0ADR);
- break;
- case WIN_OSD1:
- osd_write(sd, fb_base_phys & ~0x1F, OSD_OSDWIN1ADR);
- break;
- case WIN_VID1:
- osd_write(sd, fb_base_phys & ~0x1F, OSD_VIDWIN1ADR);
- break;
- }
- } else if (sd->vpbe_type == VPBE_VERSION_3) {
- unsigned long fb_offset_32 =
- (fb_base_phys - VPBE_REG_BASE) >> 5;
-
- switch (layer) {
- case WIN_OSD0:
- osd_modify(sd, OSD_OSDWINADH_O0AH,
- fb_offset_32 >> (OSD_SRCADD_ADD_SFT -
- OSD_OSDWINADH_O0AH_SHIFT),
- OSD_OSDWINADH);
- osd_write(sd, fb_offset_32 & OSD_OSDWIN0ADL_O0AL,
- OSD_OSDWIN0ADL);
- break;
- case WIN_VID0:
- osd_modify(sd, OSD_VIDWINADH_V0AH,
- fb_offset_32 >> (OSD_SRCADD_ADD_SFT -
- OSD_VIDWINADH_V0AH_SHIFT),
- OSD_VIDWINADH);
- osd_write(sd, fb_offset_32 & OSD_VIDWIN0ADL_V0AL,
- OSD_VIDWIN0ADL);
- break;
- case WIN_OSD1:
- osd_modify(sd, OSD_OSDWINADH_O1AH,
- fb_offset_32 >> (OSD_SRCADD_ADD_SFT -
- OSD_OSDWINADH_O1AH_SHIFT),
- OSD_OSDWINADH);
- osd_write(sd, fb_offset_32 & OSD_OSDWIN1ADL_O1AL,
- OSD_OSDWIN1ADL);
- break;
- case WIN_VID1:
- osd_modify(sd, OSD_VIDWINADH_V1AH,
- fb_offset_32 >> (OSD_SRCADD_ADD_SFT -
- OSD_VIDWINADH_V1AH_SHIFT),
- OSD_VIDWINADH);
- osd_write(sd, fb_offset_32 & OSD_VIDWIN1ADL_V1AL,
- OSD_VIDWIN1ADL);
- break;
- }
- } else if (sd->vpbe_type == VPBE_VERSION_2) {
- struct osd_window_state *win = &sd->win[layer];
- unsigned long fb_offset_32, cbcr_offset_32;
-
- fb_offset_32 = fb_base_phys - VPBE_REG_BASE;
- if (cbcr_ofst)
- cbcr_offset_32 = cbcr_ofst;
- else
- cbcr_offset_32 = win->lconfig.line_length *
- win->lconfig.ysize;
- cbcr_offset_32 += fb_offset_32;
- fb_offset_32 = fb_offset_32 >> 5;
- cbcr_offset_32 = cbcr_offset_32 >> 5;
- /*
- * DM365: start address is 27-bit long address b26 - b23 are
- * in offset register b12 - b9, and * bit 26 has to be '1'
- */
- if (win->lconfig.pixfmt == PIXFMT_NV12) {
- switch (layer) {
- case WIN_VID0:
- case WIN_VID1:
- /* Y is in VID0 */
- osd_modify(sd, OSD_VIDWIN0OFST_V0AH,
- ((fb_offset_32 & OSD_SRC_ADDR_HIGH4) >>
- (OSD_SRCADD_OFSET_SFT -
- OSD_WINOFST_AH_SHIFT)) |
- OSD_WINOFST_MASK, OSD_VIDWIN0OFST);
- osd_modify(sd, OSD_VIDWINADH_V0AH,
- (fb_offset_32 & OSD_SRC_ADDR_HIGH7) >>
- (OSD_SRCADD_ADD_SFT -
- OSD_VIDWINADH_V0AH_SHIFT),
- OSD_VIDWINADH);
- osd_write(sd, fb_offset_32 & OSD_WINADL_MASK,
- OSD_VIDWIN0ADL);
- /* CbCr is in VID1 */
- osd_modify(sd, OSD_VIDWIN1OFST_V1AH,
- ((cbcr_offset_32 &
- OSD_SRC_ADDR_HIGH4) >>
- (OSD_SRCADD_OFSET_SFT -
- OSD_WINOFST_AH_SHIFT)) |
- OSD_WINOFST_MASK, OSD_VIDWIN1OFST);
- osd_modify(sd, OSD_VIDWINADH_V1AH,
- (cbcr_offset_32 &
- OSD_SRC_ADDR_HIGH7) >>
- (OSD_SRCADD_ADD_SFT -
- OSD_VIDWINADH_V1AH_SHIFT),
- OSD_VIDWINADH);
- osd_write(sd, cbcr_offset_32 & OSD_WINADL_MASK,
- OSD_VIDWIN1ADL);
- break;
- default:
- break;
- }
- }
-
- switch (layer) {
- case WIN_OSD0:
- osd_modify(sd, OSD_OSDWIN0OFST_O0AH,
- ((fb_offset_32 & OSD_SRC_ADDR_HIGH4) >>
- (OSD_SRCADD_OFSET_SFT -
- OSD_WINOFST_AH_SHIFT)) | OSD_WINOFST_MASK,
- OSD_OSDWIN0OFST);
- osd_modify(sd, OSD_OSDWINADH_O0AH,
- (fb_offset_32 & OSD_SRC_ADDR_HIGH7) >>
- (OSD_SRCADD_ADD_SFT -
- OSD_OSDWINADH_O0AH_SHIFT), OSD_OSDWINADH);
- osd_write(sd, fb_offset_32 & OSD_WINADL_MASK,
- OSD_OSDWIN0ADL);
- break;
- case WIN_VID0:
- if (win->lconfig.pixfmt != PIXFMT_NV12) {
- osd_modify(sd, OSD_VIDWIN0OFST_V0AH,
- ((fb_offset_32 & OSD_SRC_ADDR_HIGH4) >>
- (OSD_SRCADD_OFSET_SFT -
- OSD_WINOFST_AH_SHIFT)) |
- OSD_WINOFST_MASK, OSD_VIDWIN0OFST);
- osd_modify(sd, OSD_VIDWINADH_V0AH,
- (fb_offset_32 & OSD_SRC_ADDR_HIGH7) >>
- (OSD_SRCADD_ADD_SFT -
- OSD_VIDWINADH_V0AH_SHIFT),
- OSD_VIDWINADH);
- osd_write(sd, fb_offset_32 & OSD_WINADL_MASK,
- OSD_VIDWIN0ADL);
- }
- break;
- case WIN_OSD1:
- osd_modify(sd, OSD_OSDWIN1OFST_O1AH,
- ((fb_offset_32 & OSD_SRC_ADDR_HIGH4) >>
- (OSD_SRCADD_OFSET_SFT -
- OSD_WINOFST_AH_SHIFT)) | OSD_WINOFST_MASK,
- OSD_OSDWIN1OFST);
- osd_modify(sd, OSD_OSDWINADH_O1AH,
- (fb_offset_32 & OSD_SRC_ADDR_HIGH7) >>
- (OSD_SRCADD_ADD_SFT -
- OSD_OSDWINADH_O1AH_SHIFT),
- OSD_OSDWINADH);
- osd_write(sd, fb_offset_32 & OSD_WINADL_MASK,
- OSD_OSDWIN1ADL);
- break;
- case WIN_VID1:
- if (win->lconfig.pixfmt != PIXFMT_NV12) {
- osd_modify(sd, OSD_VIDWIN1OFST_V1AH,
- ((fb_offset_32 & OSD_SRC_ADDR_HIGH4) >>
- (OSD_SRCADD_OFSET_SFT -
- OSD_WINOFST_AH_SHIFT)) |
- OSD_WINOFST_MASK, OSD_VIDWIN1OFST);
- osd_modify(sd, OSD_VIDWINADH_V1AH,
- (fb_offset_32 & OSD_SRC_ADDR_HIGH7) >>
- (OSD_SRCADD_ADD_SFT -
- OSD_VIDWINADH_V1AH_SHIFT),
- OSD_VIDWINADH);
- osd_write(sd, fb_offset_32 & OSD_WINADL_MASK,
- OSD_VIDWIN1ADL);
- }
- break;
- }
- }
-}
-
-static void osd_start_layer(struct osd_state *sd, enum osd_layer layer,
- unsigned long fb_base_phys,
- unsigned long cbcr_ofst)
-{
- struct osd_state *osd = sd;
- struct osd_window_state *win = &osd->win[layer];
- struct osd_layer_config *cfg = &win->lconfig;
- unsigned long flags;
-
- spin_lock_irqsave(&osd->lock, flags);
-
- win->fb_base_phys = fb_base_phys & ~0x1F;
- _osd_start_layer(sd, layer, fb_base_phys, cbcr_ofst);
-
- if (layer == WIN_VID0) {
- osd->pingpong =
- _osd_dm6446_vid0_pingpong(sd, osd->field_inversion,
- win->fb_base_phys,
- cfg);
- }
-
- spin_unlock_irqrestore(&osd->lock, flags);
-}
-
-static void osd_get_layer_config(struct osd_state *sd, enum osd_layer layer,
- struct osd_layer_config *lconfig)
-{
- struct osd_state *osd = sd;
- struct osd_window_state *win = &osd->win[layer];
- unsigned long flags;
-
- spin_lock_irqsave(&osd->lock, flags);
-
- *lconfig = win->lconfig;
-
- spin_unlock_irqrestore(&osd->lock, flags);
-}
-
-/**
- * try_layer_config() - Try a specific configuration for the layer
- * @sd: ptr to struct osd_state
- * @layer: layer to configure
- * @lconfig: layer configuration to try
- *
- * If the requested lconfig is completely rejected and the value of lconfig on
- * exit is the current lconfig, then try_layer_config() returns 1. Otherwise,
- * try_layer_config() returns 0. A return value of 0 does not necessarily mean
- * that the value of lconfig on exit is identical to the value of lconfig on
- * entry, but merely that it represents a change from the current lconfig.
- */
-static int try_layer_config(struct osd_state *sd, enum osd_layer layer,
- struct osd_layer_config *lconfig)
-{
- struct osd_state *osd = sd;
- struct osd_window_state *win = &osd->win[layer];
- int bad_config = 0;
-
- /* verify that the pixel format is compatible with the layer */
- switch (lconfig->pixfmt) {
- case PIXFMT_1BPP:
- case PIXFMT_2BPP:
- case PIXFMT_4BPP:
- case PIXFMT_8BPP:
- case PIXFMT_RGB565:
- if (osd->vpbe_type == VPBE_VERSION_1)
- bad_config = !is_vid_win(layer);
- break;
- case PIXFMT_YCBCRI:
- case PIXFMT_YCRCBI:
- bad_config = !is_vid_win(layer);
- break;
- case PIXFMT_RGB888:
- if (osd->vpbe_type == VPBE_VERSION_1)
- bad_config = !is_vid_win(layer);
- else if ((osd->vpbe_type == VPBE_VERSION_3) ||
- (osd->vpbe_type == VPBE_VERSION_2))
- bad_config = !is_osd_win(layer);
- break;
- case PIXFMT_NV12:
- if (osd->vpbe_type != VPBE_VERSION_2)
- bad_config = 1;
- else
- bad_config = is_osd_win(layer);
- break;
- case PIXFMT_OSD_ATTR:
- bad_config = (layer != WIN_OSD1);
- break;
- default:
- bad_config = 1;
- break;
- }
- if (bad_config) {
- /*
- * The requested pixel format is incompatible with the layer,
- * so keep the current layer configuration.
- */
- *lconfig = win->lconfig;
- return bad_config;
- }
-
- /* DM6446: */
- /* only one OSD window at a time can use RGB pixel formats */
- if ((osd->vpbe_type == VPBE_VERSION_1) &&
- is_osd_win(layer) && is_rgb_pixfmt(lconfig->pixfmt)) {
- enum osd_pix_format pixfmt;
-
- if (layer == WIN_OSD0)
- pixfmt = osd->win[WIN_OSD1].lconfig.pixfmt;
- else
- pixfmt = osd->win[WIN_OSD0].lconfig.pixfmt;
-
- if (is_rgb_pixfmt(pixfmt)) {
- /*
- * The other OSD window is already configured for an
- * RGB, so keep the current layer configuration.
- */
- *lconfig = win->lconfig;
- return 1;
- }
- }
-
- /* DM6446: only one video window at a time can use RGB888 */
- if ((osd->vpbe_type == VPBE_VERSION_1) && is_vid_win(layer) &&
- lconfig->pixfmt == PIXFMT_RGB888) {
- enum osd_pix_format pixfmt;
-
- if (layer == WIN_VID0)
- pixfmt = osd->win[WIN_VID1].lconfig.pixfmt;
- else
- pixfmt = osd->win[WIN_VID0].lconfig.pixfmt;
-
- if (pixfmt == PIXFMT_RGB888) {
- /*
- * The other video window is already configured for
- * RGB888, so keep the current layer configuration.
- */
- *lconfig = win->lconfig;
- return 1;
- }
- }
-
- /* window dimensions must be non-zero */
- if (!lconfig->line_length || !lconfig->xsize || !lconfig->ysize) {
- *lconfig = win->lconfig;
- return 1;
- }
-
- /* round line_length up to a multiple of 32 */
- lconfig->line_length = ((lconfig->line_length + 31) / 32) * 32;
- lconfig->line_length =
- min(lconfig->line_length, (unsigned)MAX_LINE_LENGTH);
- lconfig->xsize = min(lconfig->xsize, (unsigned)MAX_WIN_SIZE);
- lconfig->ysize = min(lconfig->ysize, (unsigned)MAX_WIN_SIZE);
- lconfig->xpos = min(lconfig->xpos, (unsigned)MAX_WIN_SIZE);
- lconfig->ypos = min(lconfig->ypos, (unsigned)MAX_WIN_SIZE);
- lconfig->interlaced = (lconfig->interlaced != 0);
- if (lconfig->interlaced) {
- /* ysize and ypos must be even for interlaced displays */
- lconfig->ysize &= ~1;
- lconfig->ypos &= ~1;
- }
-
- return 0;
-}
-
-static void _osd_disable_vid_rgb888(struct osd_state *sd)
-{
- /*
- * The DM6446 supports RGB888 pixel format in a single video window.
- * This routine disables RGB888 pixel format for both video windows.
- * The caller must ensure that neither video window is currently
- * configured for RGB888 pixel format.
- */
- if (sd->vpbe_type == VPBE_VERSION_1)
- osd_clear(sd, OSD_MISCCTL_RGBEN, OSD_MISCCTL);
-}
-
-static void _osd_enable_vid_rgb888(struct osd_state *sd,
- enum osd_layer layer)
-{
- /*
- * The DM6446 supports RGB888 pixel format in a single video window.
- * This routine enables RGB888 pixel format for the specified video
- * window. The caller must ensure that the other video window is not
- * currently configured for RGB888 pixel format, as this routine will
- * disable RGB888 pixel format for the other window.
- */
- if (sd->vpbe_type == VPBE_VERSION_1) {
- if (layer == WIN_VID0)
- osd_modify(sd, OSD_MISCCTL_RGBEN | OSD_MISCCTL_RGBWIN,
- OSD_MISCCTL_RGBEN, OSD_MISCCTL);
- else if (layer == WIN_VID1)
- osd_modify(sd, OSD_MISCCTL_RGBEN | OSD_MISCCTL_RGBWIN,
- OSD_MISCCTL_RGBEN | OSD_MISCCTL_RGBWIN,
- OSD_MISCCTL);
- }
-}
-
-static void _osd_set_cbcr_order(struct osd_state *sd,
- enum osd_pix_format pixfmt)
-{
- /*
- * The caller must ensure that all windows using YC pixfmt use the same
- * Cb/Cr order.
- */
- if (pixfmt == PIXFMT_YCBCRI)
- osd_clear(sd, OSD_MODE_CS, OSD_MODE);
- else if (pixfmt == PIXFMT_YCRCBI)
- osd_set(sd, OSD_MODE_CS, OSD_MODE);
-}
-
-static void _osd_set_layer_config(struct osd_state *sd, enum osd_layer layer,
- const struct osd_layer_config *lconfig)
-{
- u32 winmd = 0, winmd_mask = 0, bmw = 0;
-
- _osd_set_cbcr_order(sd, lconfig->pixfmt);
-
- switch (layer) {
- case WIN_OSD0:
- if (sd->vpbe_type == VPBE_VERSION_1) {
- winmd_mask |= OSD_OSDWIN0MD_RGB0E;
- if (lconfig->pixfmt == PIXFMT_RGB565)
- winmd |= OSD_OSDWIN0MD_RGB0E;
- } else if ((sd->vpbe_type == VPBE_VERSION_3) ||
- (sd->vpbe_type == VPBE_VERSION_2)) {
- winmd_mask |= OSD_OSDWIN0MD_BMP0MD;
- switch (lconfig->pixfmt) {
- case PIXFMT_RGB565:
- winmd |= (1 <<
- OSD_OSDWIN0MD_BMP0MD_SHIFT);
- break;
- case PIXFMT_RGB888:
- winmd |= (2 << OSD_OSDWIN0MD_BMP0MD_SHIFT);
- _osd_enable_rgb888_pixblend(sd, OSDWIN_OSD0);
- break;
- case PIXFMT_YCBCRI:
- case PIXFMT_YCRCBI:
- winmd |= (3 << OSD_OSDWIN0MD_BMP0MD_SHIFT);
- break;
- default:
- break;
- }
- }
-
- winmd_mask |= OSD_OSDWIN0MD_BMW0 | OSD_OSDWIN0MD_OFF0;
-
- switch (lconfig->pixfmt) {
- case PIXFMT_1BPP:
- bmw = 0;
- break;
- case PIXFMT_2BPP:
- bmw = 1;
- break;
- case PIXFMT_4BPP:
- bmw = 2;
- break;
- case PIXFMT_8BPP:
- bmw = 3;
- break;
- default:
- break;
- }
- winmd |= (bmw << OSD_OSDWIN0MD_BMW0_SHIFT);
-
- if (lconfig->interlaced)
- winmd |= OSD_OSDWIN0MD_OFF0;
-
- osd_modify(sd, winmd_mask, winmd, OSD_OSDWIN0MD);
- osd_write(sd, lconfig->line_length >> 5, OSD_OSDWIN0OFST);
- osd_write(sd, lconfig->xpos, OSD_OSDWIN0XP);
- osd_write(sd, lconfig->xsize, OSD_OSDWIN0XL);
- if (lconfig->interlaced) {
- osd_write(sd, lconfig->ypos >> 1, OSD_OSDWIN0YP);
- osd_write(sd, lconfig->ysize >> 1, OSD_OSDWIN0YL);
- } else {
- osd_write(sd, lconfig->ypos, OSD_OSDWIN0YP);
- osd_write(sd, lconfig->ysize, OSD_OSDWIN0YL);
- }
- break;
- case WIN_VID0:
- winmd_mask |= OSD_VIDWINMD_VFF0;
- if (lconfig->interlaced)
- winmd |= OSD_VIDWINMD_VFF0;
-
- osd_modify(sd, winmd_mask, winmd, OSD_VIDWINMD);
- osd_write(sd, lconfig->line_length >> 5, OSD_VIDWIN0OFST);
- osd_write(sd, lconfig->xpos, OSD_VIDWIN0XP);
- osd_write(sd, lconfig->xsize, OSD_VIDWIN0XL);
- /*
- * For YUV420P format the register contents are
- * duplicated in both VID registers
- */
- if ((sd->vpbe_type == VPBE_VERSION_2) &&
- (lconfig->pixfmt == PIXFMT_NV12)) {
- /* other window also */
- if (lconfig->interlaced) {
- winmd_mask |= OSD_VIDWINMD_VFF1;
- winmd |= OSD_VIDWINMD_VFF1;
- osd_modify(sd, winmd_mask, winmd,
- OSD_VIDWINMD);
- }
-
- osd_modify(sd, OSD_MISCCTL_S420D,
- OSD_MISCCTL_S420D, OSD_MISCCTL);
- osd_write(sd, lconfig->line_length >> 5,
- OSD_VIDWIN1OFST);
- osd_write(sd, lconfig->xpos, OSD_VIDWIN1XP);
- osd_write(sd, lconfig->xsize, OSD_VIDWIN1XL);
- /*
- * if NV21 pixfmt and line length not 32B
- * aligned (e.g. NTSC), Need to set window
- * X pixel size to be 32B aligned as well
- */
- if (lconfig->xsize % 32) {
- osd_write(sd,
- ((lconfig->xsize + 31) & ~31),
- OSD_VIDWIN1XL);
- osd_write(sd,
- ((lconfig->xsize + 31) & ~31),
- OSD_VIDWIN0XL);
- }
- } else if ((sd->vpbe_type == VPBE_VERSION_2) &&
- (lconfig->pixfmt != PIXFMT_NV12)) {
- osd_modify(sd, OSD_MISCCTL_S420D, ~OSD_MISCCTL_S420D,
- OSD_MISCCTL);
- }
-
- if (lconfig->interlaced) {
- osd_write(sd, lconfig->ypos >> 1, OSD_VIDWIN0YP);
- osd_write(sd, lconfig->ysize >> 1, OSD_VIDWIN0YL);
- if ((sd->vpbe_type == VPBE_VERSION_2) &&
- lconfig->pixfmt == PIXFMT_NV12) {
- osd_write(sd, lconfig->ypos >> 1,
- OSD_VIDWIN1YP);
- osd_write(sd, lconfig->ysize >> 1,
- OSD_VIDWIN1YL);
- }
- } else {
- osd_write(sd, lconfig->ypos, OSD_VIDWIN0YP);
- osd_write(sd, lconfig->ysize, OSD_VIDWIN0YL);
- if ((sd->vpbe_type == VPBE_VERSION_2) &&
- lconfig->pixfmt == PIXFMT_NV12) {
- osd_write(sd, lconfig->ypos, OSD_VIDWIN1YP);
- osd_write(sd, lconfig->ysize, OSD_VIDWIN1YL);
- }
- }
- break;
- case WIN_OSD1:
- /*
- * The caller must ensure that OSD1 is disabled prior to
- * switching from a normal mode to attribute mode or from
- * attribute mode to a normal mode.
- */
- if (lconfig->pixfmt == PIXFMT_OSD_ATTR) {
- if (sd->vpbe_type == VPBE_VERSION_1) {
- winmd_mask |= OSD_OSDWIN1MD_ATN1E |
- OSD_OSDWIN1MD_RGB1E | OSD_OSDWIN1MD_CLUTS1 |
- OSD_OSDWIN1MD_BLND1 | OSD_OSDWIN1MD_TE1;
- } else {
- winmd_mask |= OSD_OSDWIN1MD_BMP1MD |
- OSD_OSDWIN1MD_CLUTS1 | OSD_OSDWIN1MD_BLND1 |
- OSD_OSDWIN1MD_TE1;
- }
- } else {
- if (sd->vpbe_type == VPBE_VERSION_1) {
- winmd_mask |= OSD_OSDWIN1MD_RGB1E;
- if (lconfig->pixfmt == PIXFMT_RGB565)
- winmd |= OSD_OSDWIN1MD_RGB1E;
- } else if ((sd->vpbe_type == VPBE_VERSION_3)
- || (sd->vpbe_type == VPBE_VERSION_2)) {
- winmd_mask |= OSD_OSDWIN1MD_BMP1MD;
- switch (lconfig->pixfmt) {
- case PIXFMT_RGB565:
- winmd |=
- (1 << OSD_OSDWIN1MD_BMP1MD_SHIFT);
- break;
- case PIXFMT_RGB888:
- winmd |=
- (2 << OSD_OSDWIN1MD_BMP1MD_SHIFT);
- _osd_enable_rgb888_pixblend(sd,
- OSDWIN_OSD1);
- break;
- case PIXFMT_YCBCRI:
- case PIXFMT_YCRCBI:
- winmd |=
- (3 << OSD_OSDWIN1MD_BMP1MD_SHIFT);
- break;
- default:
- break;
- }
- }
-
- winmd_mask |= OSD_OSDWIN1MD_BMW1;
- switch (lconfig->pixfmt) {
- case PIXFMT_1BPP:
- bmw = 0;
- break;
- case PIXFMT_2BPP:
- bmw = 1;
- break;
- case PIXFMT_4BPP:
- bmw = 2;
- break;
- case PIXFMT_8BPP:
- bmw = 3;
- break;
- default:
- break;
- }
- winmd |= (bmw << OSD_OSDWIN1MD_BMW1_SHIFT);
- }
-
- winmd_mask |= OSD_OSDWIN1MD_OFF1;
- if (lconfig->interlaced)
- winmd |= OSD_OSDWIN1MD_OFF1;
-
- osd_modify(sd, winmd_mask, winmd, OSD_OSDWIN1MD);
- osd_write(sd, lconfig->line_length >> 5, OSD_OSDWIN1OFST);
- osd_write(sd, lconfig->xpos, OSD_OSDWIN1XP);
- osd_write(sd, lconfig->xsize, OSD_OSDWIN1XL);
- if (lconfig->interlaced) {
- osd_write(sd, lconfig->ypos >> 1, OSD_OSDWIN1YP);
- osd_write(sd, lconfig->ysize >> 1, OSD_OSDWIN1YL);
- } else {
- osd_write(sd, lconfig->ypos, OSD_OSDWIN1YP);
- osd_write(sd, lconfig->ysize, OSD_OSDWIN1YL);
- }
- break;
- case WIN_VID1:
- winmd_mask |= OSD_VIDWINMD_VFF1;
- if (lconfig->interlaced)
- winmd |= OSD_VIDWINMD_VFF1;
-
- osd_modify(sd, winmd_mask, winmd, OSD_VIDWINMD);
- osd_write(sd, lconfig->line_length >> 5, OSD_VIDWIN1OFST);
- osd_write(sd, lconfig->xpos, OSD_VIDWIN1XP);
- osd_write(sd, lconfig->xsize, OSD_VIDWIN1XL);
- /*
- * For YUV420P format the register contents are
- * duplicated in both VID registers
- */
- if (sd->vpbe_type == VPBE_VERSION_2) {
- if (lconfig->pixfmt == PIXFMT_NV12) {
- /* other window also */
- if (lconfig->interlaced) {
- winmd_mask |= OSD_VIDWINMD_VFF0;
- winmd |= OSD_VIDWINMD_VFF0;
- osd_modify(sd, winmd_mask, winmd,
- OSD_VIDWINMD);
- }
- osd_modify(sd, OSD_MISCCTL_S420D,
- OSD_MISCCTL_S420D, OSD_MISCCTL);
- osd_write(sd, lconfig->line_length >> 5,
- OSD_VIDWIN0OFST);
- osd_write(sd, lconfig->xpos, OSD_VIDWIN0XP);
- osd_write(sd, lconfig->xsize, OSD_VIDWIN0XL);
- } else {
- osd_modify(sd, OSD_MISCCTL_S420D,
- ~OSD_MISCCTL_S420D, OSD_MISCCTL);
- }
- }
-
- if (lconfig->interlaced) {
- osd_write(sd, lconfig->ypos >> 1, OSD_VIDWIN1YP);
- osd_write(sd, lconfig->ysize >> 1, OSD_VIDWIN1YL);
- if ((sd->vpbe_type == VPBE_VERSION_2) &&
- lconfig->pixfmt == PIXFMT_NV12) {
- osd_write(sd, lconfig->ypos >> 1,
- OSD_VIDWIN0YP);
- osd_write(sd, lconfig->ysize >> 1,
- OSD_VIDWIN0YL);
- }
- } else {
- osd_write(sd, lconfig->ypos, OSD_VIDWIN1YP);
- osd_write(sd, lconfig->ysize, OSD_VIDWIN1YL);
- if ((sd->vpbe_type == VPBE_VERSION_2) &&
- lconfig->pixfmt == PIXFMT_NV12) {
- osd_write(sd, lconfig->ypos, OSD_VIDWIN0YP);
- osd_write(sd, lconfig->ysize, OSD_VIDWIN0YL);
- }
- }
- break;
- }
-}
-
-static int osd_set_layer_config(struct osd_state *sd, enum osd_layer layer,
- struct osd_layer_config *lconfig)
-{
- struct osd_state *osd = sd;
- struct osd_window_state *win = &osd->win[layer];
- struct osd_layer_config *cfg = &win->lconfig;
- unsigned long flags;
- int reject_config;
-
- spin_lock_irqsave(&osd->lock, flags);
-
- reject_config = try_layer_config(sd, layer, lconfig);
- if (reject_config) {
- spin_unlock_irqrestore(&osd->lock, flags);
- return reject_config;
- }
-
- /* update the current Cb/Cr order */
- if (is_yc_pixfmt(lconfig->pixfmt))
- osd->yc_pixfmt = lconfig->pixfmt;
-
- /*
- * If we are switching OSD1 from normal mode to attribute mode or from
- * attribute mode to normal mode, then we must disable the window.
- */
- if (layer == WIN_OSD1) {
- if (((lconfig->pixfmt == PIXFMT_OSD_ATTR) &&
- (cfg->pixfmt != PIXFMT_OSD_ATTR)) ||
- ((lconfig->pixfmt != PIXFMT_OSD_ATTR) &&
- (cfg->pixfmt == PIXFMT_OSD_ATTR))) {
- win->is_enabled = 0;
- _osd_disable_layer(sd, layer);
- }
- }
-
- _osd_set_layer_config(sd, layer, lconfig);
-
- if (layer == WIN_OSD1) {
- struct osd_osdwin_state *osdwin_state =
- &osd->osdwin[OSDWIN_OSD1];
-
- if ((lconfig->pixfmt != PIXFMT_OSD_ATTR) &&
- (cfg->pixfmt == PIXFMT_OSD_ATTR)) {
- /*
- * We just switched OSD1 from attribute mode to normal
- * mode, so we must initialize the CLUT select, the
- * blend factor, transparency colorkey enable, and
- * attenuation enable (DM6446 only) bits in the
- * OSDWIN1MD register.
- */
- _osd_set_osd_clut(sd, OSDWIN_OSD1,
- osdwin_state->clut);
- _osd_set_blending_factor(sd, OSDWIN_OSD1,
- osdwin_state->blend);
- if (osdwin_state->colorkey_blending) {
- _osd_enable_color_key(sd, OSDWIN_OSD1,
- osdwin_state->
- colorkey,
- lconfig->pixfmt);
- } else
- _osd_disable_color_key(sd, OSDWIN_OSD1);
- _osd_set_rec601_attenuation(sd, OSDWIN_OSD1,
- osdwin_state->
- rec601_attenuation);
- } else if ((lconfig->pixfmt == PIXFMT_OSD_ATTR) &&
- (cfg->pixfmt != PIXFMT_OSD_ATTR)) {
- /*
- * We just switched OSD1 from normal mode to attribute
- * mode, so we must initialize the blink enable and
- * blink interval bits in the OSDATRMD register.
- */
- _osd_set_blink_attribute(sd, osd->is_blinking,
- osd->blink);
- }
- }
-
- /*
- * If we just switched to a 1-, 2-, or 4-bits-per-pixel bitmap format
- * then configure a default palette map.
- */
- if ((lconfig->pixfmt != cfg->pixfmt) &&
- ((lconfig->pixfmt == PIXFMT_1BPP) ||
- (lconfig->pixfmt == PIXFMT_2BPP) ||
- (lconfig->pixfmt == PIXFMT_4BPP))) {
- enum osd_win_layer osdwin =
- ((layer == WIN_OSD0) ? OSDWIN_OSD0 : OSDWIN_OSD1);
- struct osd_osdwin_state *osdwin_state =
- &osd->osdwin[osdwin];
- unsigned char clut_index;
- unsigned char clut_entries = 0;
-
- switch (lconfig->pixfmt) {
- case PIXFMT_1BPP:
- clut_entries = 2;
- break;
- case PIXFMT_2BPP:
- clut_entries = 4;
- break;
- case PIXFMT_4BPP:
- clut_entries = 16;
- break;
- default:
- break;
- }
- /*
- * The default palette map maps the pixel value to the clut
- * index, i.e. pixel value 0 maps to clut entry 0, pixel value
- * 1 maps to clut entry 1, etc.
- */
- for (clut_index = 0; clut_index < 16; clut_index++) {
- osdwin_state->palette_map[clut_index] = clut_index;
- if (clut_index < clut_entries) {
- _osd_set_palette_map(sd, osdwin, clut_index,
- clut_index,
- lconfig->pixfmt);
- }
- }
- }
-
- *cfg = *lconfig;
- /* DM6446: configure the RGB888 enable and window selection */
- if (osd->win[WIN_VID0].lconfig.pixfmt == PIXFMT_RGB888)
- _osd_enable_vid_rgb888(sd, WIN_VID0);
- else if (osd->win[WIN_VID1].lconfig.pixfmt == PIXFMT_RGB888)
- _osd_enable_vid_rgb888(sd, WIN_VID1);
- else
- _osd_disable_vid_rgb888(sd);
-
- if (layer == WIN_VID0) {
- osd->pingpong =
- _osd_dm6446_vid0_pingpong(sd, osd->field_inversion,
- win->fb_base_phys,
- cfg);
- }
-
- spin_unlock_irqrestore(&osd->lock, flags);
-
- return 0;
-}
-
-static void osd_init_layer(struct osd_state *sd, enum osd_layer layer)
-{
- struct osd_state *osd = sd;
- struct osd_window_state *win = &osd->win[layer];
- enum osd_win_layer osdwin;
- struct osd_osdwin_state *osdwin_state;
- struct osd_layer_config *cfg = &win->lconfig;
- unsigned long flags;
-
- spin_lock_irqsave(&osd->lock, flags);
-
- win->is_enabled = 0;
- _osd_disable_layer(sd, layer);
-
- win->h_zoom = ZOOM_X1;
- win->v_zoom = ZOOM_X1;
- _osd_set_zoom(sd, layer, win->h_zoom, win->v_zoom);
-
- win->fb_base_phys = 0;
- _osd_start_layer(sd, layer, win->fb_base_phys, 0);
-
- cfg->line_length = 0;
- cfg->xsize = 0;
- cfg->ysize = 0;
- cfg->xpos = 0;
- cfg->ypos = 0;
- cfg->interlaced = 0;
- switch (layer) {
- case WIN_OSD0:
- case WIN_OSD1:
- osdwin = (layer == WIN_OSD0) ? OSDWIN_OSD0 : OSDWIN_OSD1;
- osdwin_state = &osd->osdwin[osdwin];
- /*
- * Other code relies on the fact that OSD windows default to a
- * bitmap pixel format when they are deallocated, so don't
- * change this default pixel format.
- */
- cfg->pixfmt = PIXFMT_8BPP;
- _osd_set_layer_config(sd, layer, cfg);
- osdwin_state->clut = RAM_CLUT;
- _osd_set_osd_clut(sd, osdwin, osdwin_state->clut);
- osdwin_state->colorkey_blending = 0;
- _osd_disable_color_key(sd, osdwin);
- osdwin_state->blend = OSD_8_VID_0;
- _osd_set_blending_factor(sd, osdwin, osdwin_state->blend);
- osdwin_state->rec601_attenuation = 0;
- _osd_set_rec601_attenuation(sd, osdwin,
- osdwin_state->
- rec601_attenuation);
- if (osdwin == OSDWIN_OSD1) {
- osd->is_blinking = 0;
- osd->blink = BLINK_X1;
- }
- break;
- case WIN_VID0:
- case WIN_VID1:
- cfg->pixfmt = osd->yc_pixfmt;
- _osd_set_layer_config(sd, layer, cfg);
- break;
- }
-
- spin_unlock_irqrestore(&osd->lock, flags);
-}
-
-static void osd_release_layer(struct osd_state *sd, enum osd_layer layer)
-{
- struct osd_state *osd = sd;
- struct osd_window_state *win = &osd->win[layer];
- unsigned long flags;
-
- spin_lock_irqsave(&osd->lock, flags);
-
- if (!win->is_allocated) {
- spin_unlock_irqrestore(&osd->lock, flags);
- return;
- }
-
- spin_unlock_irqrestore(&osd->lock, flags);
- osd_init_layer(sd, layer);
- spin_lock_irqsave(&osd->lock, flags);
-
- win->is_allocated = 0;
-
- spin_unlock_irqrestore(&osd->lock, flags);
-}
-
-static int osd_request_layer(struct osd_state *sd, enum osd_layer layer)
-{
- struct osd_state *osd = sd;
- struct osd_window_state *win = &osd->win[layer];
- unsigned long flags;
-
- spin_lock_irqsave(&osd->lock, flags);
-
- if (win->is_allocated) {
- spin_unlock_irqrestore(&osd->lock, flags);
- return -1;
- }
- win->is_allocated = 1;
-
- spin_unlock_irqrestore(&osd->lock, flags);
-
- return 0;
-}
-
-static void _osd_init(struct osd_state *sd)
-{
- osd_write(sd, 0, OSD_MODE);
- osd_write(sd, 0, OSD_VIDWINMD);
- osd_write(sd, 0, OSD_OSDWIN0MD);
- osd_write(sd, 0, OSD_OSDWIN1MD);
- osd_write(sd, 0, OSD_RECTCUR);
- osd_write(sd, 0, OSD_MISCCTL);
- if (sd->vpbe_type == VPBE_VERSION_3) {
- osd_write(sd, 0, OSD_VBNDRY);
- osd_write(sd, 0, OSD_EXTMODE);
- osd_write(sd, OSD_MISCCTL_DMANG, OSD_MISCCTL);
- }
-}
-
-static void osd_set_left_margin(struct osd_state *sd, u32 val)
-{
- osd_write(sd, val, OSD_BASEPX);
-}
-
-static void osd_set_top_margin(struct osd_state *sd, u32 val)
-{
- osd_write(sd, val, OSD_BASEPY);
-}
-
-static int osd_initialize(struct osd_state *osd)
-{
- if (osd == NULL)
- return -ENODEV;
- _osd_init(osd);
-
- /* set default Cb/Cr order */
- osd->yc_pixfmt = PIXFMT_YCBCRI;
-
- if (osd->vpbe_type == VPBE_VERSION_3) {
- /*
- * ROM CLUT1 on the DM355 is similar (identical?) to ROM CLUT0
- * on the DM6446, so make ROM_CLUT1 the default on the DM355.
- */
- osd->rom_clut = ROM_CLUT1;
- }
-
- _osd_set_field_inversion(osd, osd->field_inversion);
- _osd_set_rom_clut(osd, osd->rom_clut);
-
- osd_init_layer(osd, WIN_OSD0);
- osd_init_layer(osd, WIN_VID0);
- osd_init_layer(osd, WIN_OSD1);
- osd_init_layer(osd, WIN_VID1);
-
- return 0;
-}
-
-static const struct vpbe_osd_ops osd_ops = {
- .initialize = osd_initialize,
- .request_layer = osd_request_layer,
- .release_layer = osd_release_layer,
- .enable_layer = osd_enable_layer,
- .disable_layer = osd_disable_layer,
- .set_layer_config = osd_set_layer_config,
- .get_layer_config = osd_get_layer_config,
- .start_layer = osd_start_layer,
- .set_left_margin = osd_set_left_margin,
- .set_top_margin = osd_set_top_margin,
-};
-
-static int osd_probe(struct platform_device *pdev)
-{
- const struct platform_device_id *pdev_id;
- struct osd_state *osd;
- struct resource *res;
-
- pdev_id = platform_get_device_id(pdev);
- if (!pdev_id)
- return -EINVAL;
-
- osd = devm_kzalloc(&pdev->dev, sizeof(struct osd_state), GFP_KERNEL);
- if (osd == NULL)
- return -ENOMEM;
-
-
- osd->dev = &pdev->dev;
- osd->vpbe_type = pdev_id->driver_data;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- osd->osd_base = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(osd->osd_base))
- return PTR_ERR(osd->osd_base);
-
- osd->osd_base_phys = res->start;
- osd->osd_size = resource_size(res);
- spin_lock_init(&osd->lock);
- osd->ops = osd_ops;
- platform_set_drvdata(pdev, osd);
- dev_notice(osd->dev, "OSD sub device probe success\n");
-
- return 0;
-}
-
-static int osd_remove(struct platform_device *pdev)
-{
- return 0;
-}
-
-static struct platform_driver osd_driver = {
- .probe = osd_probe,
- .remove = osd_remove,
- .driver = {
- .name = MODULE_NAME,
- },
- .id_table = vpbe_osd_devtype
-};
-
-module_platform_driver(osd_driver);
-
-MODULE_LICENSE("GPL");
-MODULE_DESCRIPTION("DaVinci OSD Manager Driver");
-MODULE_AUTHOR("Texas Instruments");
diff --git a/drivers/media/platform/ti/davinci/vpbe_osd_regs.h b/drivers/media/platform/ti/davinci/vpbe_osd_regs.h
deleted file mode 100644
index cecd5991d4c5..000000000000
--- a/drivers/media/platform/ti/davinci/vpbe_osd_regs.h
+++ /dev/null
@@ -1,352 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2006-2010 Texas Instruments Inc
- */
-#ifndef _VPBE_OSD_REGS_H
-#define _VPBE_OSD_REGS_H
-
-/* VPBE Global Registers */
-#define VPBE_PID 0x0
-#define VPBE_PCR 0x4
-
-/* VPSS CLock Registers */
-#define VPSSCLK_PID 0x00
-#define VPSSCLK_CLKCTRL 0x04
-
-/* VPSS Buffer Logic Registers */
-#define VPSSBL_PID 0x00
-#define VPSSBL_PCR 0x04
-#define VPSSBL_BCR 0x08
-#define VPSSBL_INTSTAT 0x0C
-#define VPSSBL_INTSEL 0x10
-#define VPSSBL_EVTSEL 0x14
-#define VPSSBL_MEMCTRL 0x18
-#define VPSSBL_CCDCMUX 0x1C
-
-/* DM365 ISP5 system configuration */
-#define ISP5_PID 0x0
-#define ISP5_PCCR 0x4
-#define ISP5_BCR 0x8
-#define ISP5_INTSTAT 0xC
-#define ISP5_INTSEL1 0x10
-#define ISP5_INTSEL2 0x14
-#define ISP5_INTSEL3 0x18
-#define ISP5_EVTSEL 0x1c
-#define ISP5_CCDCMUX 0x20
-
-/* VPBE On-Screen Display Subsystem Registers (OSD) */
-#define OSD_MODE 0x00
-#define OSD_VIDWINMD 0x04
-#define OSD_OSDWIN0MD 0x08
-#define OSD_OSDWIN1MD 0x0C
-#define OSD_OSDATRMD 0x0C
-#define OSD_RECTCUR 0x10
-#define OSD_VIDWIN0OFST 0x18
-#define OSD_VIDWIN1OFST 0x1C
-#define OSD_OSDWIN0OFST 0x20
-#define OSD_OSDWIN1OFST 0x24
-#define OSD_VIDWINADH 0x28
-#define OSD_VIDWIN0ADL 0x2C
-#define OSD_VIDWIN0ADR 0x2C
-#define OSD_VIDWIN1ADL 0x30
-#define OSD_VIDWIN1ADR 0x30
-#define OSD_OSDWINADH 0x34
-#define OSD_OSDWIN0ADL 0x38
-#define OSD_OSDWIN0ADR 0x38
-#define OSD_OSDWIN1ADL 0x3C
-#define OSD_OSDWIN1ADR 0x3C
-#define OSD_BASEPX 0x40
-#define OSD_BASEPY 0x44
-#define OSD_VIDWIN0XP 0x48
-#define OSD_VIDWIN0YP 0x4C
-#define OSD_VIDWIN0XL 0x50
-#define OSD_VIDWIN0YL 0x54
-#define OSD_VIDWIN1XP 0x58
-#define OSD_VIDWIN1YP 0x5C
-#define OSD_VIDWIN1XL 0x60
-#define OSD_VIDWIN1YL 0x64
-#define OSD_OSDWIN0XP 0x68
-#define OSD_OSDWIN0YP 0x6C
-#define OSD_OSDWIN0XL 0x70
-#define OSD_OSDWIN0YL 0x74
-#define OSD_OSDWIN1XP 0x78
-#define OSD_OSDWIN1YP 0x7C
-#define OSD_OSDWIN1XL 0x80
-#define OSD_OSDWIN1YL 0x84
-#define OSD_CURXP 0x88
-#define OSD_CURYP 0x8C
-#define OSD_CURXL 0x90
-#define OSD_CURYL 0x94
-#define OSD_W0BMP01 0xA0
-#define OSD_W0BMP23 0xA4
-#define OSD_W0BMP45 0xA8
-#define OSD_W0BMP67 0xAC
-#define OSD_W0BMP89 0xB0
-#define OSD_W0BMPAB 0xB4
-#define OSD_W0BMPCD 0xB8
-#define OSD_W0BMPEF 0xBC
-#define OSD_W1BMP01 0xC0
-#define OSD_W1BMP23 0xC4
-#define OSD_W1BMP45 0xC8
-#define OSD_W1BMP67 0xCC
-#define OSD_W1BMP89 0xD0
-#define OSD_W1BMPAB 0xD4
-#define OSD_W1BMPCD 0xD8
-#define OSD_W1BMPEF 0xDC
-#define OSD_VBNDRY 0xE0
-#define OSD_EXTMODE 0xE4
-#define OSD_MISCCTL 0xE8
-#define OSD_CLUTRAMYCB 0xEC
-#define OSD_CLUTRAMCR 0xF0
-#define OSD_TRANSPVAL 0xF4
-#define OSD_TRANSPVALL 0xF4
-#define OSD_TRANSPVALU 0xF8
-#define OSD_TRANSPBMPIDX 0xFC
-#define OSD_PPVWIN0ADR 0xFC
-
-/* bit definitions */
-#define VPBE_PCR_VENC_DIV (1 << 1)
-#define VPBE_PCR_CLK_OFF (1 << 0)
-
-#define VPSSBL_INTSTAT_HSSIINT (1 << 14)
-#define VPSSBL_INTSTAT_CFALDINT (1 << 13)
-#define VPSSBL_INTSTAT_IPIPE_INT5 (1 << 12)
-#define VPSSBL_INTSTAT_IPIPE_INT4 (1 << 11)
-#define VPSSBL_INTSTAT_IPIPE_INT3 (1 << 10)
-#define VPSSBL_INTSTAT_IPIPE_INT2 (1 << 9)
-#define VPSSBL_INTSTAT_IPIPE_INT1 (1 << 8)
-#define VPSSBL_INTSTAT_IPIPE_INT0 (1 << 7)
-#define VPSSBL_INTSTAT_IPIPEIFINT (1 << 6)
-#define VPSSBL_INTSTAT_OSDINT (1 << 5)
-#define VPSSBL_INTSTAT_VENCINT (1 << 4)
-#define VPSSBL_INTSTAT_H3AINT (1 << 3)
-#define VPSSBL_INTSTAT_CCDC_VDINT2 (1 << 2)
-#define VPSSBL_INTSTAT_CCDC_VDINT1 (1 << 1)
-#define VPSSBL_INTSTAT_CCDC_VDINT0 (1 << 0)
-
-/* DM365 ISP5 bit definitions */
-#define ISP5_INTSTAT_VENCINT (1 << 21)
-#define ISP5_INTSTAT_OSDINT (1 << 20)
-
-/* VMOD TVTYP options for HDMD=0 */
-#define SDTV_NTSC 0
-#define SDTV_PAL 1
-/* VMOD TVTYP options for HDMD=1 */
-#define HDTV_525P 0
-#define HDTV_625P 1
-#define HDTV_1080I 2
-#define HDTV_720P 3
-
-#define OSD_MODE_CS (1 << 15)
-#define OSD_MODE_OVRSZ (1 << 14)
-#define OSD_MODE_OHRSZ (1 << 13)
-#define OSD_MODE_EF (1 << 12)
-#define OSD_MODE_VVRSZ (1 << 11)
-#define OSD_MODE_VHRSZ (1 << 10)
-#define OSD_MODE_FSINV (1 << 9)
-#define OSD_MODE_BCLUT (1 << 8)
-#define OSD_MODE_CABG_SHIFT 0
-#define OSD_MODE_CABG (0xff << 0)
-
-#define OSD_VIDWINMD_VFINV (1 << 15)
-#define OSD_VIDWINMD_V1EFC (1 << 14)
-#define OSD_VIDWINMD_VHZ1_SHIFT 12
-#define OSD_VIDWINMD_VHZ1 (3 << 12)
-#define OSD_VIDWINMD_VVZ1_SHIFT 10
-#define OSD_VIDWINMD_VVZ1 (3 << 10)
-#define OSD_VIDWINMD_VFF1 (1 << 9)
-#define OSD_VIDWINMD_ACT1 (1 << 8)
-#define OSD_VIDWINMD_V0EFC (1 << 6)
-#define OSD_VIDWINMD_VHZ0_SHIFT 4
-#define OSD_VIDWINMD_VHZ0 (3 << 4)
-#define OSD_VIDWINMD_VVZ0_SHIFT 2
-#define OSD_VIDWINMD_VVZ0 (3 << 2)
-#define OSD_VIDWINMD_VFF0 (1 << 1)
-#define OSD_VIDWINMD_ACT0 (1 << 0)
-
-#define OSD_OSDWIN0MD_ATN0E (1 << 14)
-#define OSD_OSDWIN0MD_RGB0E (1 << 13)
-#define OSD_OSDWIN0MD_BMP0MD_SHIFT 13
-#define OSD_OSDWIN0MD_BMP0MD (3 << 13)
-#define OSD_OSDWIN0MD_CLUTS0 (1 << 12)
-#define OSD_OSDWIN0MD_OHZ0_SHIFT 10
-#define OSD_OSDWIN0MD_OHZ0 (3 << 10)
-#define OSD_OSDWIN0MD_OVZ0_SHIFT 8
-#define OSD_OSDWIN0MD_OVZ0 (3 << 8)
-#define OSD_OSDWIN0MD_BMW0_SHIFT 6
-#define OSD_OSDWIN0MD_BMW0 (3 << 6)
-#define OSD_OSDWIN0MD_BLND0_SHIFT 3
-#define OSD_OSDWIN0MD_BLND0 (7 << 3)
-#define OSD_OSDWIN0MD_TE0 (1 << 2)
-#define OSD_OSDWIN0MD_OFF0 (1 << 1)
-#define OSD_OSDWIN0MD_OACT0 (1 << 0)
-
-#define OSD_OSDWIN1MD_OASW (1 << 15)
-#define OSD_OSDWIN1MD_ATN1E (1 << 14)
-#define OSD_OSDWIN1MD_RGB1E (1 << 13)
-#define OSD_OSDWIN1MD_BMP1MD_SHIFT 13
-#define OSD_OSDWIN1MD_BMP1MD (3 << 13)
-#define OSD_OSDWIN1MD_CLUTS1 (1 << 12)
-#define OSD_OSDWIN1MD_OHZ1_SHIFT 10
-#define OSD_OSDWIN1MD_OHZ1 (3 << 10)
-#define OSD_OSDWIN1MD_OVZ1_SHIFT 8
-#define OSD_OSDWIN1MD_OVZ1 (3 << 8)
-#define OSD_OSDWIN1MD_BMW1_SHIFT 6
-#define OSD_OSDWIN1MD_BMW1 (3 << 6)
-#define OSD_OSDWIN1MD_BLND1_SHIFT 3
-#define OSD_OSDWIN1MD_BLND1 (7 << 3)
-#define OSD_OSDWIN1MD_TE1 (1 << 2)
-#define OSD_OSDWIN1MD_OFF1 (1 << 1)
-#define OSD_OSDWIN1MD_OACT1 (1 << 0)
-
-#define OSD_OSDATRMD_OASW (1 << 15)
-#define OSD_OSDATRMD_OHZA_SHIFT 10
-#define OSD_OSDATRMD_OHZA (3 << 10)
-#define OSD_OSDATRMD_OVZA_SHIFT 8
-#define OSD_OSDATRMD_OVZA (3 << 8)
-#define OSD_OSDATRMD_BLNKINT_SHIFT 6
-#define OSD_OSDATRMD_BLNKINT (3 << 6)
-#define OSD_OSDATRMD_OFFA (1 << 1)
-#define OSD_OSDATRMD_BLNK (1 << 0)
-
-#define OSD_RECTCUR_RCAD_SHIFT 8
-#define OSD_RECTCUR_RCAD (0xff << 8)
-#define OSD_RECTCUR_CLUTSR (1 << 7)
-#define OSD_RECTCUR_RCHW_SHIFT 4
-#define OSD_RECTCUR_RCHW (7 << 4)
-#define OSD_RECTCUR_RCVW_SHIFT 1
-#define OSD_RECTCUR_RCVW (7 << 1)
-#define OSD_RECTCUR_RCACT (1 << 0)
-
-#define OSD_VIDWIN0OFST_V0LO (0x1ff << 0)
-
-#define OSD_VIDWIN1OFST_V1LO (0x1ff << 0)
-
-#define OSD_OSDWIN0OFST_O0LO (0x1ff << 0)
-
-#define OSD_OSDWIN1OFST_O1LO (0x1ff << 0)
-
-#define OSD_WINOFST_AH_SHIFT 9
-
-#define OSD_VIDWIN0OFST_V0AH (0xf << 9)
-#define OSD_VIDWIN1OFST_V1AH (0xf << 9)
-#define OSD_OSDWIN0OFST_O0AH (0xf << 9)
-#define OSD_OSDWIN1OFST_O1AH (0xf << 9)
-
-#define OSD_VIDWINADH_V1AH_SHIFT 8
-#define OSD_VIDWINADH_V1AH (0x7f << 8)
-#define OSD_VIDWINADH_V0AH_SHIFT 0
-#define OSD_VIDWINADH_V0AH (0x7f << 0)
-
-#define OSD_VIDWIN0ADL_V0AL (0xffff << 0)
-
-#define OSD_VIDWIN1ADL_V1AL (0xffff << 0)
-
-#define OSD_OSDWINADH_O1AH_SHIFT 8
-#define OSD_OSDWINADH_O1AH (0x7f << 8)
-#define OSD_OSDWINADH_O0AH_SHIFT 0
-#define OSD_OSDWINADH_O0AH (0x7f << 0)
-
-#define OSD_OSDWIN0ADL_O0AL (0xffff << 0)
-
-#define OSD_OSDWIN1ADL_O1AL (0xffff << 0)
-
-#define OSD_BASEPX_BPX (0x3ff << 0)
-
-#define OSD_BASEPY_BPY (0x1ff << 0)
-
-#define OSD_VIDWIN0XP_V0X (0x7ff << 0)
-
-#define OSD_VIDWIN0YP_V0Y (0x7ff << 0)
-
-#define OSD_VIDWIN0XL_V0W (0x7ff << 0)
-
-#define OSD_VIDWIN0YL_V0H (0x7ff << 0)
-
-#define OSD_VIDWIN1XP_V1X (0x7ff << 0)
-
-#define OSD_VIDWIN1YP_V1Y (0x7ff << 0)
-
-#define OSD_VIDWIN1XL_V1W (0x7ff << 0)
-
-#define OSD_VIDWIN1YL_V1H (0x7ff << 0)
-
-#define OSD_OSDWIN0XP_W0X (0x7ff << 0)
-
-#define OSD_OSDWIN0YP_W0Y (0x7ff << 0)
-
-#define OSD_OSDWIN0XL_W0W (0x7ff << 0)
-
-#define OSD_OSDWIN0YL_W0H (0x7ff << 0)
-
-#define OSD_OSDWIN1XP_W1X (0x7ff << 0)
-
-#define OSD_OSDWIN1YP_W1Y (0x7ff << 0)
-
-#define OSD_OSDWIN1XL_W1W (0x7ff << 0)
-
-#define OSD_OSDWIN1YL_W1H (0x7ff << 0)
-
-#define OSD_CURXP_RCSX (0x7ff << 0)
-
-#define OSD_CURYP_RCSY (0x7ff << 0)
-
-#define OSD_CURXL_RCSW (0x7ff << 0)
-
-#define OSD_CURYL_RCSH (0x7ff << 0)
-
-#define OSD_EXTMODE_EXPMDSEL (1 << 15)
-#define OSD_EXTMODE_SCRNHEXP_SHIFT 13
-#define OSD_EXTMODE_SCRNHEXP (3 << 13)
-#define OSD_EXTMODE_SCRNVEXP (1 << 12)
-#define OSD_EXTMODE_OSD1BLDCHR (1 << 11)
-#define OSD_EXTMODE_OSD0BLDCHR (1 << 10)
-#define OSD_EXTMODE_ATNOSD1EN (1 << 9)
-#define OSD_EXTMODE_ATNOSD0EN (1 << 8)
-#define OSD_EXTMODE_OSDHRSZ15 (1 << 7)
-#define OSD_EXTMODE_VIDHRSZ15 (1 << 6)
-#define OSD_EXTMODE_ZMFILV1HEN (1 << 5)
-#define OSD_EXTMODE_ZMFILV1VEN (1 << 4)
-#define OSD_EXTMODE_ZMFILV0HEN (1 << 3)
-#define OSD_EXTMODE_ZMFILV0VEN (1 << 2)
-#define OSD_EXTMODE_EXPFILHEN (1 << 1)
-#define OSD_EXTMODE_EXPFILVEN (1 << 0)
-
-#define OSD_MISCCTL_BLDSEL (1 << 15)
-#define OSD_MISCCTL_S420D (1 << 14)
-#define OSD_MISCCTL_BMAPT (1 << 13)
-#define OSD_MISCCTL_DM365M (1 << 12)
-#define OSD_MISCCTL_RGBEN (1 << 7)
-#define OSD_MISCCTL_RGBWIN (1 << 6)
-#define OSD_MISCCTL_DMANG (1 << 6)
-#define OSD_MISCCTL_TMON (1 << 5)
-#define OSD_MISCCTL_RSEL (1 << 4)
-#define OSD_MISCCTL_CPBSY (1 << 3)
-#define OSD_MISCCTL_PPSW (1 << 2)
-#define OSD_MISCCTL_PPRV (1 << 1)
-
-#define OSD_CLUTRAMYCB_Y_SHIFT 8
-#define OSD_CLUTRAMYCB_Y (0xff << 8)
-#define OSD_CLUTRAMYCB_CB_SHIFT 0
-#define OSD_CLUTRAMYCB_CB (0xff << 0)
-
-#define OSD_CLUTRAMCR_CR_SHIFT 8
-#define OSD_CLUTRAMCR_CR (0xff << 8)
-#define OSD_CLUTRAMCR_CADDR_SHIFT 0
-#define OSD_CLUTRAMCR_CADDR (0xff << 0)
-
-#define OSD_TRANSPVAL_RGBTRANS (0xffff << 0)
-
-#define OSD_TRANSPVALL_RGBL (0xffff << 0)
-
-#define OSD_TRANSPVALU_Y_SHIFT 8
-#define OSD_TRANSPVALU_Y (0xff << 8)
-#define OSD_TRANSPVALU_RGBU_SHIFT 0
-#define OSD_TRANSPVALU_RGBU (0xff << 0)
-
-#define OSD_TRANSPBMPIDX_BMP1_SHIFT 8
-#define OSD_TRANSPBMPIDX_BMP1 (0xff << 8)
-#define OSD_TRANSPBMPIDX_BMP0_SHIFT 0
-#define OSD_TRANSPBMPIDX_BMP0 0xff
-
-#endif /* _DAVINCI_VPBE_H_ */
diff --git a/drivers/media/platform/ti/davinci/vpbe_venc.c b/drivers/media/platform/ti/davinci/vpbe_venc.c
deleted file mode 100644
index 4c8e31de12b1..000000000000
--- a/drivers/media/platform/ti/davinci/vpbe_venc.c
+++ /dev/null
@@ -1,676 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2010 Texas Instruments Inc
- */
-#include <linux/module.h>
-#include <linux/mod_devicetable.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/ctype.h>
-#include <linux/delay.h>
-#include <linux/device.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/videodev2.h>
-#include <linux/slab.h>
-
-#include <linux/platform_data/i2c-davinci.h>
-
-#include <linux/io.h>
-
-#include <media/davinci/vpbe_types.h>
-#include <media/davinci/vpbe_venc.h>
-#include <media/davinci/vpss.h>
-#include <media/v4l2-device.h>
-
-#include "vpbe_venc_regs.h"
-
-#define MODULE_NAME "davinci-vpbe-venc"
-
-static const struct platform_device_id vpbe_venc_devtype[] = {
- {
- .name = DM644X_VPBE_VENC_SUBDEV_NAME,
- .driver_data = VPBE_VERSION_1,
- }, {
- .name = DM365_VPBE_VENC_SUBDEV_NAME,
- .driver_data = VPBE_VERSION_2,
- }, {
- .name = DM355_VPBE_VENC_SUBDEV_NAME,
- .driver_data = VPBE_VERSION_3,
- },
- {
- /* sentinel */
- }
-};
-
-MODULE_DEVICE_TABLE(platform, vpbe_venc_devtype);
-
-static int debug = 2;
-module_param(debug, int, 0644);
-MODULE_PARM_DESC(debug, "Debug level 0-2");
-
-struct venc_state {
- struct v4l2_subdev sd;
- struct venc_callback *callback;
- struct venc_platform_data *pdata;
- struct device *pdev;
- u32 output;
- v4l2_std_id std;
- spinlock_t lock;
- void __iomem *venc_base;
- void __iomem *vdaccfg_reg;
- enum vpbe_version venc_type;
-};
-
-static inline struct venc_state *to_state(struct v4l2_subdev *sd)
-{
- return container_of(sd, struct venc_state, sd);
-}
-
-static inline u32 venc_read(struct v4l2_subdev *sd, u32 offset)
-{
- struct venc_state *venc = to_state(sd);
-
- return readl(venc->venc_base + offset);
-}
-
-static inline u32 venc_write(struct v4l2_subdev *sd, u32 offset, u32 val)
-{
- struct venc_state *venc = to_state(sd);
-
- writel(val, (venc->venc_base + offset));
-
- return val;
-}
-
-static inline u32 venc_modify(struct v4l2_subdev *sd, u32 offset,
- u32 val, u32 mask)
-{
- u32 new_val = (venc_read(sd, offset) & ~mask) | (val & mask);
-
- venc_write(sd, offset, new_val);
-
- return new_val;
-}
-
-static inline u32 vdaccfg_write(struct v4l2_subdev *sd, u32 val)
-{
- struct venc_state *venc = to_state(sd);
-
- writel(val, venc->vdaccfg_reg);
-
- val = readl(venc->vdaccfg_reg);
-
- return val;
-}
-
-#define VDAC_COMPONENT 0x543
-#define VDAC_S_VIDEO 0x210
-/* This function sets the dac of the VPBE for various outputs
- */
-static int venc_set_dac(struct v4l2_subdev *sd, u32 out_index)
-{
- switch (out_index) {
- case 0:
- v4l2_dbg(debug, 1, sd, "Setting output to Composite\n");
- venc_write(sd, VENC_DACSEL, 0);
- break;
- case 1:
- v4l2_dbg(debug, 1, sd, "Setting output to Component\n");
- venc_write(sd, VENC_DACSEL, VDAC_COMPONENT);
- break;
- case 2:
- v4l2_dbg(debug, 1, sd, "Setting output to S-video\n");
- venc_write(sd, VENC_DACSEL, VDAC_S_VIDEO);
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-static void venc_enabledigitaloutput(struct v4l2_subdev *sd, int benable)
-{
- struct venc_state *venc = to_state(sd);
-
- v4l2_dbg(debug, 2, sd, "venc_enabledigitaloutput\n");
-
- if (benable) {
- venc_write(sd, VENC_VMOD, 0);
- venc_write(sd, VENC_CVBS, 0);
- venc_write(sd, VENC_LCDOUT, 0);
- venc_write(sd, VENC_HSPLS, 0);
- venc_write(sd, VENC_HSTART, 0);
- venc_write(sd, VENC_HVALID, 0);
- venc_write(sd, VENC_HINT, 0);
- venc_write(sd, VENC_VSPLS, 0);
- venc_write(sd, VENC_VSTART, 0);
- venc_write(sd, VENC_VVALID, 0);
- venc_write(sd, VENC_VINT, 0);
- venc_write(sd, VENC_YCCCTL, 0);
- venc_write(sd, VENC_DACSEL, 0);
-
- } else {
- venc_write(sd, VENC_VMOD, 0);
- /* disable VCLK output pin enable */
- venc_write(sd, VENC_VIDCTL, 0x141);
-
- /* Disable output sync pins */
- venc_write(sd, VENC_SYNCCTL, 0);
-
- /* Disable DCLOCK */
- venc_write(sd, VENC_DCLKCTL, 0);
- venc_write(sd, VENC_DRGBX1, 0x0000057C);
-
- /* Disable LCD output control (accepting default polarity) */
- venc_write(sd, VENC_LCDOUT, 0);
- if (venc->venc_type != VPBE_VERSION_3)
- venc_write(sd, VENC_CMPNT, 0x100);
- venc_write(sd, VENC_HSPLS, 0);
- venc_write(sd, VENC_HINT, 0);
- venc_write(sd, VENC_HSTART, 0);
- venc_write(sd, VENC_HVALID, 0);
-
- venc_write(sd, VENC_VSPLS, 0);
- venc_write(sd, VENC_VINT, 0);
- venc_write(sd, VENC_VSTART, 0);
- venc_write(sd, VENC_VVALID, 0);
-
- venc_write(sd, VENC_HSDLY, 0);
- venc_write(sd, VENC_VSDLY, 0);
-
- venc_write(sd, VENC_YCCCTL, 0);
- venc_write(sd, VENC_VSTARTA, 0);
-
- /* Set OSD clock and OSD Sync Adavance registers */
- venc_write(sd, VENC_OSDCLK0, 1);
- venc_write(sd, VENC_OSDCLK1, 2);
- }
-}
-
-static void
-venc_enable_vpss_clock(int venc_type,
- enum vpbe_enc_timings_type type,
- unsigned int pclock)
-{
- if (venc_type == VPBE_VERSION_1)
- return;
-
- if (venc_type == VPBE_VERSION_2 && (type == VPBE_ENC_STD || (type ==
- VPBE_ENC_DV_TIMINGS && pclock <= 27000000))) {
- vpss_enable_clock(VPSS_VENC_CLOCK_SEL, 1);
- vpss_enable_clock(VPSS_VPBE_CLOCK, 1);
- return;
- }
-
- if (venc_type == VPBE_VERSION_3 && type == VPBE_ENC_STD)
- vpss_enable_clock(VPSS_VENC_CLOCK_SEL, 0);
-}
-
-#define VDAC_CONFIG_SD_V3 0x0E21A6B6
-#define VDAC_CONFIG_SD_V2 0x081141CF
-/*
- * setting NTSC mode
- */
-static int venc_set_ntsc(struct v4l2_subdev *sd)
-{
- struct venc_state *venc = to_state(sd);
- struct venc_platform_data *pdata = venc->pdata;
-
- v4l2_dbg(debug, 2, sd, "venc_set_ntsc\n");
-
- /* Setup clock at VPSS & VENC for SD */
- vpss_enable_clock(VPSS_VENC_CLOCK_SEL, 1);
- if (pdata->setup_clock(VPBE_ENC_STD, V4L2_STD_525_60) < 0)
- return -EINVAL;
-
- venc_enable_vpss_clock(venc->venc_type, VPBE_ENC_STD, V4L2_STD_525_60);
- venc_enabledigitaloutput(sd, 0);
-
- if (venc->venc_type == VPBE_VERSION_3) {
- venc_write(sd, VENC_CLKCTL, 0x01);
- venc_write(sd, VENC_VIDCTL, 0);
- vdaccfg_write(sd, VDAC_CONFIG_SD_V3);
- } else if (venc->venc_type == VPBE_VERSION_2) {
- venc_write(sd, VENC_CLKCTL, 0x01);
- venc_write(sd, VENC_VIDCTL, 0);
- vdaccfg_write(sd, VDAC_CONFIG_SD_V2);
- } else {
- /* to set VENC CLK DIV to 1 - final clock is 54 MHz */
- venc_modify(sd, VENC_VIDCTL, 0, 1 << 1);
- /* Set REC656 Mode */
- venc_write(sd, VENC_YCCCTL, 0x1);
- venc_modify(sd, VENC_VDPRO, 0, VENC_VDPRO_DAFRQ);
- venc_modify(sd, VENC_VDPRO, 0, VENC_VDPRO_DAUPS);
- }
-
- venc_write(sd, VENC_VMOD, 0);
- venc_modify(sd, VENC_VMOD, (1 << VENC_VMOD_VIE_SHIFT),
- VENC_VMOD_VIE);
- venc_modify(sd, VENC_VMOD, (0 << VENC_VMOD_VMD), VENC_VMOD_VMD);
- venc_modify(sd, VENC_VMOD, (0 << VENC_VMOD_TVTYP_SHIFT),
- VENC_VMOD_TVTYP);
- venc_write(sd, VENC_DACTST, 0x0);
- venc_modify(sd, VENC_VMOD, VENC_VMOD_VENC, VENC_VMOD_VENC);
-
- return 0;
-}
-
-/*
- * setting PAL mode
- */
-static int venc_set_pal(struct v4l2_subdev *sd)
-{
- struct venc_state *venc = to_state(sd);
-
- v4l2_dbg(debug, 2, sd, "venc_set_pal\n");
-
- /* Setup clock at VPSS & VENC for SD */
- vpss_enable_clock(VPSS_VENC_CLOCK_SEL, 1);
- if (venc->pdata->setup_clock(VPBE_ENC_STD, V4L2_STD_625_50) < 0)
- return -EINVAL;
-
- venc_enable_vpss_clock(venc->venc_type, VPBE_ENC_STD, V4L2_STD_625_50);
- venc_enabledigitaloutput(sd, 0);
-
- if (venc->venc_type == VPBE_VERSION_3) {
- venc_write(sd, VENC_CLKCTL, 0x1);
- venc_write(sd, VENC_VIDCTL, 0);
- vdaccfg_write(sd, VDAC_CONFIG_SD_V3);
- } else if (venc->venc_type == VPBE_VERSION_2) {
- venc_write(sd, VENC_CLKCTL, 0x1);
- venc_write(sd, VENC_VIDCTL, 0);
- vdaccfg_write(sd, VDAC_CONFIG_SD_V2);
- } else {
- /* to set VENC CLK DIV to 1 - final clock is 54 MHz */
- venc_modify(sd, VENC_VIDCTL, 0, 1 << 1);
- /* Set REC656 Mode */
- venc_write(sd, VENC_YCCCTL, 0x1);
- }
-
- venc_modify(sd, VENC_SYNCCTL, 1 << VENC_SYNCCTL_OVD_SHIFT,
- VENC_SYNCCTL_OVD);
- venc_write(sd, VENC_VMOD, 0);
- venc_modify(sd, VENC_VMOD,
- (1 << VENC_VMOD_VIE_SHIFT),
- VENC_VMOD_VIE);
- venc_modify(sd, VENC_VMOD,
- (0 << VENC_VMOD_VMD), VENC_VMOD_VMD);
- venc_modify(sd, VENC_VMOD,
- (1 << VENC_VMOD_TVTYP_SHIFT),
- VENC_VMOD_TVTYP);
- venc_write(sd, VENC_DACTST, 0x0);
- venc_modify(sd, VENC_VMOD, VENC_VMOD_VENC, VENC_VMOD_VENC);
-
- return 0;
-}
-
-#define VDAC_CONFIG_HD_V2 0x081141EF
-/*
- * venc_set_480p59_94
- *
- * This function configures the video encoder to EDTV(525p) component setting.
- */
-static int venc_set_480p59_94(struct v4l2_subdev *sd)
-{
- struct venc_state *venc = to_state(sd);
- struct venc_platform_data *pdata = venc->pdata;
-
- v4l2_dbg(debug, 2, sd, "venc_set_480p59_94\n");
- if (venc->venc_type != VPBE_VERSION_1 &&
- venc->venc_type != VPBE_VERSION_2)
- return -EINVAL;
-
- /* Setup clock at VPSS & VENC for SD */
- if (pdata->setup_clock(VPBE_ENC_DV_TIMINGS, 27000000) < 0)
- return -EINVAL;
-
- venc_enable_vpss_clock(venc->venc_type, VPBE_ENC_DV_TIMINGS, 27000000);
- venc_enabledigitaloutput(sd, 0);
-
- if (venc->venc_type == VPBE_VERSION_2)
- vdaccfg_write(sd, VDAC_CONFIG_HD_V2);
- venc_write(sd, VENC_OSDCLK0, 0);
- venc_write(sd, VENC_OSDCLK1, 1);
-
- if (venc->venc_type == VPBE_VERSION_1) {
- venc_modify(sd, VENC_VDPRO, VENC_VDPRO_DAFRQ,
- VENC_VDPRO_DAFRQ);
- venc_modify(sd, VENC_VDPRO, VENC_VDPRO_DAUPS,
- VENC_VDPRO_DAUPS);
- }
-
- venc_write(sd, VENC_VMOD, 0);
- venc_modify(sd, VENC_VMOD, (1 << VENC_VMOD_VIE_SHIFT),
- VENC_VMOD_VIE);
- venc_modify(sd, VENC_VMOD, VENC_VMOD_HDMD, VENC_VMOD_HDMD);
- venc_modify(sd, VENC_VMOD, (HDTV_525P << VENC_VMOD_TVTYP_SHIFT),
- VENC_VMOD_TVTYP);
- venc_modify(sd, VENC_VMOD, VENC_VMOD_VDMD_YCBCR8 <<
- VENC_VMOD_VDMD_SHIFT, VENC_VMOD_VDMD);
-
- venc_modify(sd, VENC_VMOD, VENC_VMOD_VENC, VENC_VMOD_VENC);
-
- return 0;
-}
-
-/*
- * venc_set_625p
- *
- * This function configures the video encoder to HDTV(625p) component setting
- */
-static int venc_set_576p50(struct v4l2_subdev *sd)
-{
- struct venc_state *venc = to_state(sd);
- struct venc_platform_data *pdata = venc->pdata;
-
- v4l2_dbg(debug, 2, sd, "venc_set_576p50\n");
-
- if (venc->venc_type != VPBE_VERSION_1 &&
- venc->venc_type != VPBE_VERSION_2)
- return -EINVAL;
- /* Setup clock at VPSS & VENC for SD */
- if (pdata->setup_clock(VPBE_ENC_DV_TIMINGS, 27000000) < 0)
- return -EINVAL;
-
- venc_enable_vpss_clock(venc->venc_type, VPBE_ENC_DV_TIMINGS, 27000000);
- venc_enabledigitaloutput(sd, 0);
-
- if (venc->venc_type == VPBE_VERSION_2)
- vdaccfg_write(sd, VDAC_CONFIG_HD_V2);
-
- venc_write(sd, VENC_OSDCLK0, 0);
- venc_write(sd, VENC_OSDCLK1, 1);
-
- if (venc->venc_type == VPBE_VERSION_1) {
- venc_modify(sd, VENC_VDPRO, VENC_VDPRO_DAFRQ,
- VENC_VDPRO_DAFRQ);
- venc_modify(sd, VENC_VDPRO, VENC_VDPRO_DAUPS,
- VENC_VDPRO_DAUPS);
- }
-
- venc_write(sd, VENC_VMOD, 0);
- venc_modify(sd, VENC_VMOD, (1 << VENC_VMOD_VIE_SHIFT),
- VENC_VMOD_VIE);
- venc_modify(sd, VENC_VMOD, VENC_VMOD_HDMD, VENC_VMOD_HDMD);
- venc_modify(sd, VENC_VMOD, (HDTV_625P << VENC_VMOD_TVTYP_SHIFT),
- VENC_VMOD_TVTYP);
-
- venc_modify(sd, VENC_VMOD, VENC_VMOD_VDMD_YCBCR8 <<
- VENC_VMOD_VDMD_SHIFT, VENC_VMOD_VDMD);
- venc_modify(sd, VENC_VMOD, VENC_VMOD_VENC, VENC_VMOD_VENC);
-
- return 0;
-}
-
-/*
- * venc_set_720p60_internal - Setup 720p60 in venc for dm365 only
- */
-static int venc_set_720p60_internal(struct v4l2_subdev *sd)
-{
- struct venc_state *venc = to_state(sd);
- struct venc_platform_data *pdata = venc->pdata;
-
- if (pdata->setup_clock(VPBE_ENC_DV_TIMINGS, 74250000) < 0)
- return -EINVAL;
-
- venc_enable_vpss_clock(venc->venc_type, VPBE_ENC_DV_TIMINGS, 74250000);
- venc_enabledigitaloutput(sd, 0);
-
- venc_write(sd, VENC_OSDCLK0, 0);
- venc_write(sd, VENC_OSDCLK1, 1);
-
- venc_write(sd, VENC_VMOD, 0);
- /* DM365 component HD mode */
- venc_modify(sd, VENC_VMOD, (1 << VENC_VMOD_VIE_SHIFT),
- VENC_VMOD_VIE);
- venc_modify(sd, VENC_VMOD, VENC_VMOD_HDMD, VENC_VMOD_HDMD);
- venc_modify(sd, VENC_VMOD, (HDTV_720P << VENC_VMOD_TVTYP_SHIFT),
- VENC_VMOD_TVTYP);
- venc_modify(sd, VENC_VMOD, VENC_VMOD_VENC, VENC_VMOD_VENC);
- venc_write(sd, VENC_XHINTVL, 0);
- return 0;
-}
-
-/*
- * venc_set_1080i30_internal - Setup 1080i30 in venc for dm365 only
- */
-static int venc_set_1080i30_internal(struct v4l2_subdev *sd)
-{
- struct venc_state *venc = to_state(sd);
- struct venc_platform_data *pdata = venc->pdata;
-
- if (pdata->setup_clock(VPBE_ENC_DV_TIMINGS, 74250000) < 0)
- return -EINVAL;
-
- venc_enable_vpss_clock(venc->venc_type, VPBE_ENC_DV_TIMINGS, 74250000);
- venc_enabledigitaloutput(sd, 0);
-
- venc_write(sd, VENC_OSDCLK0, 0);
- venc_write(sd, VENC_OSDCLK1, 1);
-
-
- venc_write(sd, VENC_VMOD, 0);
- /* DM365 component HD mode */
- venc_modify(sd, VENC_VMOD, (1 << VENC_VMOD_VIE_SHIFT),
- VENC_VMOD_VIE);
- venc_modify(sd, VENC_VMOD, VENC_VMOD_HDMD, VENC_VMOD_HDMD);
- venc_modify(sd, VENC_VMOD, (HDTV_1080I << VENC_VMOD_TVTYP_SHIFT),
- VENC_VMOD_TVTYP);
- venc_modify(sd, VENC_VMOD, VENC_VMOD_VENC, VENC_VMOD_VENC);
- venc_write(sd, VENC_XHINTVL, 0);
- return 0;
-}
-
-static int venc_s_std_output(struct v4l2_subdev *sd, v4l2_std_id norm)
-{
- v4l2_dbg(debug, 1, sd, "venc_s_std_output\n");
-
- if (norm & V4L2_STD_525_60)
- return venc_set_ntsc(sd);
- else if (norm & V4L2_STD_625_50)
- return venc_set_pal(sd);
-
- return -EINVAL;
-}
-
-static int venc_s_dv_timings(struct v4l2_subdev *sd,
- struct v4l2_dv_timings *dv_timings)
-{
- struct venc_state *venc = to_state(sd);
- u32 height = dv_timings->bt.height;
- int ret;
-
- v4l2_dbg(debug, 1, sd, "venc_s_dv_timings\n");
-
- if (height == 576)
- return venc_set_576p50(sd);
- else if (height == 480)
- return venc_set_480p59_94(sd);
- else if ((height == 720) &&
- (venc->venc_type == VPBE_VERSION_2)) {
- /* TBD setup internal 720p mode here */
- ret = venc_set_720p60_internal(sd);
- /* for DM365 VPBE, there is DAC inside */
- vdaccfg_write(sd, VDAC_CONFIG_HD_V2);
- return ret;
- } else if ((height == 1080) &&
- (venc->venc_type == VPBE_VERSION_2)) {
- /* TBD setup internal 1080i mode here */
- ret = venc_set_1080i30_internal(sd);
- /* for DM365 VPBE, there is DAC inside */
- vdaccfg_write(sd, VDAC_CONFIG_HD_V2);
- return ret;
- }
- return -EINVAL;
-}
-
-static int venc_s_routing(struct v4l2_subdev *sd, u32 input, u32 output,
- u32 config)
-{
- struct venc_state *venc = to_state(sd);
- int ret;
-
- v4l2_dbg(debug, 1, sd, "venc_s_routing\n");
-
- ret = venc_set_dac(sd, output);
- if (!ret)
- venc->output = output;
-
- return ret;
-}
-
-static long venc_command(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
-{
- u32 val;
-
- switch (cmd) {
- case VENC_GET_FLD:
- val = venc_read(sd, VENC_VSTAT);
- *((int *)arg) = ((val & VENC_VSTAT_FIDST) ==
- VENC_VSTAT_FIDST);
- break;
- default:
- v4l2_err(sd, "Wrong IOCTL cmd\n");
- break;
- }
-
- return 0;
-}
-
-static const struct v4l2_subdev_core_ops venc_core_ops = {
- .command = venc_command,
-};
-
-static const struct v4l2_subdev_video_ops venc_video_ops = {
- .s_routing = venc_s_routing,
- .s_std_output = venc_s_std_output,
- .s_dv_timings = venc_s_dv_timings,
-};
-
-static const struct v4l2_subdev_ops venc_ops = {
- .core = &venc_core_ops,
- .video = &venc_video_ops,
-};
-
-static int venc_initialize(struct v4l2_subdev *sd)
-{
- struct venc_state *venc = to_state(sd);
- int ret;
-
- /* Set default to output to composite and std to NTSC */
- venc->output = 0;
- venc->std = V4L2_STD_525_60;
-
- ret = venc_s_routing(sd, 0, venc->output, 0);
- if (ret < 0) {
- v4l2_err(sd, "Error setting output during init\n");
- return -EINVAL;
- }
-
- ret = venc_s_std_output(sd, venc->std);
- if (ret < 0) {
- v4l2_err(sd, "Error setting std during init\n");
- return -EINVAL;
- }
-
- return ret;
-}
-
-static int venc_device_get(struct device *dev, void *data)
-{
- struct platform_device *pdev = to_platform_device(dev);
- struct venc_state **venc = data;
-
- if (strstr(pdev->name, "vpbe-venc") != NULL)
- *venc = platform_get_drvdata(pdev);
-
- return 0;
-}
-
-struct v4l2_subdev *venc_sub_dev_init(struct v4l2_device *v4l2_dev,
- const char *venc_name)
-{
- struct venc_state *venc = NULL;
-
- bus_for_each_dev(&platform_bus_type, NULL, &venc,
- venc_device_get);
- if (venc == NULL)
- return NULL;
-
- v4l2_subdev_init(&venc->sd, &venc_ops);
-
- strscpy(venc->sd.name, venc_name, sizeof(venc->sd.name));
- if (v4l2_device_register_subdev(v4l2_dev, &venc->sd) < 0) {
- v4l2_err(v4l2_dev,
- "vpbe unable to register venc sub device\n");
- return NULL;
- }
- if (venc_initialize(&venc->sd)) {
- v4l2_err(v4l2_dev,
- "vpbe venc initialization failed\n");
- return NULL;
- }
-
- return &venc->sd;
-}
-EXPORT_SYMBOL(venc_sub_dev_init);
-
-static int venc_probe(struct platform_device *pdev)
-{
- const struct platform_device_id *pdev_id;
- struct venc_state *venc;
-
- if (!pdev->dev.platform_data) {
- dev_err(&pdev->dev, "No platform data for VENC sub device");
- return -EINVAL;
- }
-
- pdev_id = platform_get_device_id(pdev);
- if (!pdev_id)
- return -EINVAL;
-
- venc = devm_kzalloc(&pdev->dev, sizeof(struct venc_state), GFP_KERNEL);
- if (venc == NULL)
- return -ENOMEM;
-
- venc->venc_type = pdev_id->driver_data;
- venc->pdev = &pdev->dev;
- venc->pdata = pdev->dev.platform_data;
-
- venc->venc_base = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(venc->venc_base))
- return PTR_ERR(venc->venc_base);
-
- if (venc->venc_type != VPBE_VERSION_1) {
- venc->vdaccfg_reg = devm_platform_ioremap_resource(pdev, 1);
- if (IS_ERR(venc->vdaccfg_reg))
- return PTR_ERR(venc->vdaccfg_reg);
- }
- spin_lock_init(&venc->lock);
- platform_set_drvdata(pdev, venc);
- dev_notice(venc->pdev, "VENC sub device probe success\n");
-
- return 0;
-}
-
-static int venc_remove(struct platform_device *pdev)
-{
- return 0;
-}
-
-static struct platform_driver venc_driver = {
- .probe = venc_probe,
- .remove = venc_remove,
- .driver = {
- .name = MODULE_NAME,
- },
- .id_table = vpbe_venc_devtype
-};
-
-module_platform_driver(venc_driver);
-
-MODULE_LICENSE("GPL");
-MODULE_DESCRIPTION("VPBE VENC Driver");
-MODULE_AUTHOR("Texas Instruments");
diff --git a/drivers/media/platform/ti/davinci/vpbe_venc_regs.h b/drivers/media/platform/ti/davinci/vpbe_venc_regs.h
deleted file mode 100644
index 29d8fc3af662..000000000000
--- a/drivers/media/platform/ti/davinci/vpbe_venc_regs.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2006-2010 Texas Instruments Inc
- */
-#ifndef _VPBE_VENC_REGS_H
-#define _VPBE_VENC_REGS_H
-
-/* VPBE Video Encoder / Digital LCD Subsystem Registers (VENC) */
-#define VENC_VMOD 0x00
-#define VENC_VIDCTL 0x04
-#define VENC_VDPRO 0x08
-#define VENC_SYNCCTL 0x0C
-#define VENC_HSPLS 0x10
-#define VENC_VSPLS 0x14
-#define VENC_HINT 0x18
-#define VENC_HSTART 0x1C
-#define VENC_HVALID 0x20
-#define VENC_VINT 0x24
-#define VENC_VSTART 0x28
-#define VENC_VVALID 0x2C
-#define VENC_HSDLY 0x30
-#define VENC_VSDLY 0x34
-#define VENC_YCCCTL 0x38
-#define VENC_RGBCTL 0x3C
-#define VENC_RGBCLP 0x40
-#define VENC_LINECTL 0x44
-#define VENC_CULLLINE 0x48
-#define VENC_LCDOUT 0x4C
-#define VENC_BRTS 0x50
-#define VENC_BRTW 0x54
-#define VENC_ACCTL 0x58
-#define VENC_PWMP 0x5C
-#define VENC_PWMW 0x60
-#define VENC_DCLKCTL 0x64
-#define VENC_DCLKPTN0 0x68
-#define VENC_DCLKPTN1 0x6C
-#define VENC_DCLKPTN2 0x70
-#define VENC_DCLKPTN3 0x74
-#define VENC_DCLKPTN0A 0x78
-#define VENC_DCLKPTN1A 0x7C
-#define VENC_DCLKPTN2A 0x80
-#define VENC_DCLKPTN3A 0x84
-#define VENC_DCLKHS 0x88
-#define VENC_DCLKHSA 0x8C
-#define VENC_DCLKHR 0x90
-#define VENC_DCLKVS 0x94
-#define VENC_DCLKVR 0x98
-#define VENC_CAPCTL 0x9C
-#define VENC_CAPDO 0xA0
-#define VENC_CAPDE 0xA4
-#define VENC_ATR0 0xA8
-#define VENC_ATR1 0xAC
-#define VENC_ATR2 0xB0
-#define VENC_VSTAT 0xB8
-#define VENC_RAMADR 0xBC
-#define VENC_RAMPORT 0xC0
-#define VENC_DACTST 0xC4
-#define VENC_YCOLVL 0xC8
-#define VENC_SCPROG 0xCC
-#define VENC_CVBS 0xDC
-#define VENC_CMPNT 0xE0
-#define VENC_ETMG0 0xE4
-#define VENC_ETMG1 0xE8
-#define VENC_ETMG2 0xEC
-#define VENC_ETMG3 0xF0
-#define VENC_DACSEL 0xF4
-#define VENC_ARGBX0 0x100
-#define VENC_ARGBX1 0x104
-#define VENC_ARGBX2 0x108
-#define VENC_ARGBX3 0x10C
-#define VENC_ARGBX4 0x110
-#define VENC_DRGBX0 0x114
-#define VENC_DRGBX1 0x118
-#define VENC_DRGBX2 0x11C
-#define VENC_DRGBX3 0x120
-#define VENC_DRGBX4 0x124
-#define VENC_VSTARTA 0x128
-#define VENC_OSDCLK0 0x12C
-#define VENC_OSDCLK1 0x130
-#define VENC_HVLDCL0 0x134
-#define VENC_HVLDCL1 0x138
-#define VENC_OSDHADV 0x13C
-#define VENC_CLKCTL 0x140
-#define VENC_GAMCTL 0x144
-#define VENC_XHINTVL 0x174
-
-/* bit definitions */
-#define VPBE_PCR_VENC_DIV (1 << 1)
-#define VPBE_PCR_CLK_OFF (1 << 0)
-
-#define VENC_VMOD_VDMD_SHIFT 12
-#define VENC_VMOD_VDMD_YCBCR16 0
-#define VENC_VMOD_VDMD_YCBCR8 1
-#define VENC_VMOD_VDMD_RGB666 2
-#define VENC_VMOD_VDMD_RGB8 3
-#define VENC_VMOD_VDMD_EPSON 4
-#define VENC_VMOD_VDMD_CASIO 5
-#define VENC_VMOD_VDMD_UDISPQVGA 6
-#define VENC_VMOD_VDMD_STNLCD 7
-#define VENC_VMOD_VIE_SHIFT 1
-#define VENC_VMOD_VDMD (7 << 12)
-#define VENC_VMOD_ITLCL (1 << 11)
-#define VENC_VMOD_ITLC (1 << 10)
-#define VENC_VMOD_NSIT (1 << 9)
-#define VENC_VMOD_HDMD (1 << 8)
-#define VENC_VMOD_TVTYP_SHIFT 6
-#define VENC_VMOD_TVTYP (3 << 6)
-#define VENC_VMOD_SLAVE (1 << 5)
-#define VENC_VMOD_VMD (1 << 4)
-#define VENC_VMOD_BLNK (1 << 3)
-#define VENC_VMOD_VIE (1 << 1)
-#define VENC_VMOD_VENC (1 << 0)
-
-/* VMOD TVTYP options for HDMD=0 */
-#define SDTV_NTSC 0
-#define SDTV_PAL 1
-/* VMOD TVTYP options for HDMD=1 */
-#define HDTV_525P 0
-#define HDTV_625P 1
-#define HDTV_1080I 2
-#define HDTV_720P 3
-
-#define VENC_VIDCTL_VCLKP (1 << 14)
-#define VENC_VIDCTL_VCLKE_SHIFT 13
-#define VENC_VIDCTL_VCLKE (1 << 13)
-#define VENC_VIDCTL_VCLKZ_SHIFT 12
-#define VENC_VIDCTL_VCLKZ (1 << 12)
-#define VENC_VIDCTL_SYDIR_SHIFT 8
-#define VENC_VIDCTL_SYDIR (1 << 8)
-#define VENC_VIDCTL_DOMD_SHIFT 4
-#define VENC_VIDCTL_DOMD (3 << 4)
-#define VENC_VIDCTL_YCDIR_SHIFT 0
-#define VENC_VIDCTL_YCDIR (1 << 0)
-
-#define VENC_VDPRO_ATYCC_SHIFT 5
-#define VENC_VDPRO_ATYCC (1 << 5)
-#define VENC_VDPRO_ATCOM_SHIFT 4
-#define VENC_VDPRO_ATCOM (1 << 4)
-#define VENC_VDPRO_DAFRQ (1 << 3)
-#define VENC_VDPRO_DAUPS (1 << 2)
-#define VENC_VDPRO_CUPS (1 << 1)
-#define VENC_VDPRO_YUPS (1 << 0)
-
-#define VENC_SYNCCTL_VPL_SHIFT 3
-#define VENC_SYNCCTL_VPL (1 << 3)
-#define VENC_SYNCCTL_HPL_SHIFT 2
-#define VENC_SYNCCTL_HPL (1 << 2)
-#define VENC_SYNCCTL_SYEV_SHIFT 1
-#define VENC_SYNCCTL_SYEV (1 << 1)
-#define VENC_SYNCCTL_SYEH_SHIFT 0
-#define VENC_SYNCCTL_SYEH (1 << 0)
-#define VENC_SYNCCTL_OVD_SHIFT 14
-#define VENC_SYNCCTL_OVD (1 << 14)
-
-#define VENC_DCLKCTL_DCKEC_SHIFT 11
-#define VENC_DCLKCTL_DCKEC (1 << 11)
-#define VENC_DCLKCTL_DCKPW_SHIFT 0
-#define VENC_DCLKCTL_DCKPW (0x3f << 0)
-
-#define VENC_VSTAT_FIDST (1 << 4)
-
-#define VENC_CMPNT_MRGB_SHIFT 14
-#define VENC_CMPNT_MRGB (1 << 14)
-
-#endif /* _VPBE_VENC_REGS_H */
diff --git a/drivers/media/platform/ti/davinci/vpss.c b/drivers/media/platform/ti/davinci/vpss.c
deleted file mode 100644
index d15b991ab17c..000000000000
--- a/drivers/media/platform/ti/davinci/vpss.c
+++ /dev/null
@@ -1,529 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright (C) 2009 Texas Instruments.
- *
- * common vpss system module platform driver for all video drivers.
- */
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/pm_runtime.h>
-#include <linux/err.h>
-
-#include <media/davinci/vpss.h>
-
-MODULE_LICENSE("GPL");
-MODULE_DESCRIPTION("VPSS Driver");
-MODULE_AUTHOR("Texas Instruments");
-
-/* DM644x defines */
-#define DM644X_SBL_PCR_VPSS (4)
-
-#define DM355_VPSSBL_INTSEL 0x10
-#define DM355_VPSSBL_EVTSEL 0x14
-/* vpss BL register offsets */
-#define DM355_VPSSBL_CCDCMUX 0x1c
-/* vpss CLK register offsets */
-#define DM355_VPSSCLK_CLKCTRL 0x04
-/* masks and shifts */
-#define VPSS_HSSISEL_SHIFT 4
-/*
- * VDINT0 - vpss_int0, VDINT1 - vpss_int1, H3A - vpss_int4,
- * IPIPE_INT1_SDR - vpss_int5
- */
-#define DM355_VPSSBL_INTSEL_DEFAULT 0xff83ff10
-/* VENCINT - vpss_int8 */
-#define DM355_VPSSBL_EVTSEL_DEFAULT 0x4
-
-#define DM365_ISP5_PCCR 0x04
-#define DM365_ISP5_PCCR_BL_CLK_ENABLE BIT(0)
-#define DM365_ISP5_PCCR_ISIF_CLK_ENABLE BIT(1)
-#define DM365_ISP5_PCCR_H3A_CLK_ENABLE BIT(2)
-#define DM365_ISP5_PCCR_RSZ_CLK_ENABLE BIT(3)
-#define DM365_ISP5_PCCR_IPIPE_CLK_ENABLE BIT(4)
-#define DM365_ISP5_PCCR_IPIPEIF_CLK_ENABLE BIT(5)
-#define DM365_ISP5_PCCR_RSV BIT(6)
-
-#define DM365_ISP5_BCR 0x08
-#define DM365_ISP5_BCR_ISIF_OUT_ENABLE BIT(1)
-
-#define DM365_ISP5_INTSEL1 0x10
-#define DM365_ISP5_INTSEL2 0x14
-#define DM365_ISP5_INTSEL3 0x18
-#define DM365_ISP5_CCDCMUX 0x20
-#define DM365_ISP5_PG_FRAME_SIZE 0x28
-#define DM365_VPBE_CLK_CTRL 0x00
-
-#define VPSS_CLK_CTRL 0x01c40044
-#define VPSS_CLK_CTRL_VENCCLKEN BIT(3)
-#define VPSS_CLK_CTRL_DACCLKEN BIT(4)
-
-/*
- * vpss interrupts. VDINT0 - vpss_int0, VDINT1 - vpss_int1,
- * AF - vpss_int3
- */
-#define DM365_ISP5_INTSEL1_DEFAULT 0x0b1f0100
-/* AEW - vpss_int6, RSZ_INT_DMA - vpss_int5 */
-#define DM365_ISP5_INTSEL2_DEFAULT 0x1f0a0f1f
-/* VENC - vpss_int8 */
-#define DM365_ISP5_INTSEL3_DEFAULT 0x00000015
-
-/* masks and shifts for DM365*/
-#define DM365_CCDC_PG_VD_POL_SHIFT 0
-#define DM365_CCDC_PG_HD_POL_SHIFT 1
-
-#define CCD_SRC_SEL_MASK (BIT_MASK(5) | BIT_MASK(4))
-#define CCD_SRC_SEL_SHIFT 4
-
-/* Different SoC platforms supported by this driver */
-enum vpss_platform_type {
- DM644X,
- DM355,
- DM365,
-};
-
-/*
- * vpss operations. Depends on platform. Not all functions are available
- * on all platforms. The api, first check if a function is available before
- * invoking it. In the probe, the function ptrs are initialized based on
- * vpss name. vpss name can be "dm355_vpss", "dm644x_vpss" etc.
- */
-struct vpss_hw_ops {
- /* enable clock */
- int (*enable_clock)(enum vpss_clock_sel clock_sel, int en);
- /* select input to ccdc */
- void (*select_ccdc_source)(enum vpss_ccdc_source_sel src_sel);
- /* clear wbl overflow bit */
- int (*clear_wbl_overflow)(enum vpss_wbl_sel wbl_sel);
- /* set sync polarity */
- void (*set_sync_pol)(struct vpss_sync_pol);
- /* set the PG_FRAME_SIZE register*/
- void (*set_pg_frame_size)(struct vpss_pg_frame_size);
- /* check and clear interrupt if occurred */
- int (*dma_complete_interrupt)(void);
-};
-
-/* vpss configuration */
-struct vpss_oper_config {
- __iomem void *vpss_regs_base0;
- __iomem void *vpss_regs_base1;
- __iomem void *vpss_regs_base2;
- enum vpss_platform_type platform;
- spinlock_t vpss_lock;
- struct vpss_hw_ops hw_ops;
-};
-
-static struct vpss_oper_config oper_cfg;
-
-/* register access routines */
-static inline u32 bl_regr(u32 offset)
-{
- return __raw_readl(oper_cfg.vpss_regs_base0 + offset);
-}
-
-static inline void bl_regw(u32 val, u32 offset)
-{
- __raw_writel(val, oper_cfg.vpss_regs_base0 + offset);
-}
-
-static inline u32 vpss_regr(u32 offset)
-{
- return __raw_readl(oper_cfg.vpss_regs_base1 + offset);
-}
-
-static inline void vpss_regw(u32 val, u32 offset)
-{
- __raw_writel(val, oper_cfg.vpss_regs_base1 + offset);
-}
-
-/* For DM365 only */
-static inline u32 isp5_read(u32 offset)
-{
- return __raw_readl(oper_cfg.vpss_regs_base0 + offset);
-}
-
-/* For DM365 only */
-static inline void isp5_write(u32 val, u32 offset)
-{
- __raw_writel(val, oper_cfg.vpss_regs_base0 + offset);
-}
-
-static void dm365_select_ccdc_source(enum vpss_ccdc_source_sel src_sel)
-{
- u32 temp = isp5_read(DM365_ISP5_CCDCMUX) & ~CCD_SRC_SEL_MASK;
-
- /* if we are using pattern generator, enable it */
- if (src_sel == VPSS_PGLPBK || src_sel == VPSS_CCDCPG)
- temp |= 0x08;
-
- temp |= (src_sel << CCD_SRC_SEL_SHIFT);
- isp5_write(temp, DM365_ISP5_CCDCMUX);
-}
-
-static void dm355_select_ccdc_source(enum vpss_ccdc_source_sel src_sel)
-{
- bl_regw(src_sel << VPSS_HSSISEL_SHIFT, DM355_VPSSBL_CCDCMUX);
-}
-
-int vpss_dma_complete_interrupt(void)
-{
- if (!oper_cfg.hw_ops.dma_complete_interrupt)
- return 2;
- return oper_cfg.hw_ops.dma_complete_interrupt();
-}
-EXPORT_SYMBOL(vpss_dma_complete_interrupt);
-
-int vpss_select_ccdc_source(enum vpss_ccdc_source_sel src_sel)
-{
- if (!oper_cfg.hw_ops.select_ccdc_source)
- return -EINVAL;
-
- oper_cfg.hw_ops.select_ccdc_source(src_sel);
- return 0;
-}
-EXPORT_SYMBOL(vpss_select_ccdc_source);
-
-static int dm644x_clear_wbl_overflow(enum vpss_wbl_sel wbl_sel)
-{
- u32 mask = 1, val;
-
- if (wbl_sel < VPSS_PCR_AEW_WBL_0 ||
- wbl_sel > VPSS_PCR_CCDC_WBL_O)
- return -EINVAL;
-
- /* writing a 0 clear the overflow */
- mask = ~(mask << wbl_sel);
- val = bl_regr(DM644X_SBL_PCR_VPSS) & mask;
- bl_regw(val, DM644X_SBL_PCR_VPSS);
- return 0;
-}
-
-void vpss_set_sync_pol(struct vpss_sync_pol sync)
-{
- if (!oper_cfg.hw_ops.set_sync_pol)
- return;
-
- oper_cfg.hw_ops.set_sync_pol(sync);
-}
-EXPORT_SYMBOL(vpss_set_sync_pol);
-
-int vpss_clear_wbl_overflow(enum vpss_wbl_sel wbl_sel)
-{
- if (!oper_cfg.hw_ops.clear_wbl_overflow)
- return -EINVAL;
-
- return oper_cfg.hw_ops.clear_wbl_overflow(wbl_sel);
-}
-EXPORT_SYMBOL(vpss_clear_wbl_overflow);
-
-/*
- * dm355_enable_clock - Enable VPSS Clock
- * @clock_sel: Clock to be enabled/disabled
- * @en: enable/disable flag
- *
- * This is called to enable or disable a vpss clock
- */
-static int dm355_enable_clock(enum vpss_clock_sel clock_sel, int en)
-{
- unsigned long flags;
- u32 utemp, mask = 0x1, shift = 0;
-
- switch (clock_sel) {
- case VPSS_VPBE_CLOCK:
- /* nothing since lsb */
- break;
- case VPSS_VENC_CLOCK_SEL:
- shift = 2;
- break;
- case VPSS_CFALD_CLOCK:
- shift = 3;
- break;
- case VPSS_H3A_CLOCK:
- shift = 4;
- break;
- case VPSS_IPIPE_CLOCK:
- shift = 5;
- break;
- case VPSS_CCDC_CLOCK:
- shift = 6;
- break;
- default:
- printk(KERN_ERR "dm355_enable_clock: Invalid selector: %d\n",
- clock_sel);
- return -EINVAL;
- }
-
- spin_lock_irqsave(&oper_cfg.vpss_lock, flags);
- utemp = vpss_regr(DM355_VPSSCLK_CLKCTRL);
- if (!en)
- utemp &= ~(mask << shift);
- else
- utemp |= (mask << shift);
-
- vpss_regw(utemp, DM355_VPSSCLK_CLKCTRL);
- spin_unlock_irqrestore(&oper_cfg.vpss_lock, flags);
- return 0;
-}
-
-static int dm365_enable_clock(enum vpss_clock_sel clock_sel, int en)
-{
- unsigned long flags;
- u32 utemp, mask = 0x1, shift = 0, offset = DM365_ISP5_PCCR;
- u32 (*read)(u32 offset) = isp5_read;
- void(*write)(u32 val, u32 offset) = isp5_write;
-
- switch (clock_sel) {
- case VPSS_BL_CLOCK:
- break;
- case VPSS_CCDC_CLOCK:
- shift = 1;
- break;
- case VPSS_H3A_CLOCK:
- shift = 2;
- break;
- case VPSS_RSZ_CLOCK:
- shift = 3;
- break;
- case VPSS_IPIPE_CLOCK:
- shift = 4;
- break;
- case VPSS_IPIPEIF_CLOCK:
- shift = 5;
- break;
- case VPSS_PCLK_INTERNAL:
- shift = 6;
- break;
- case VPSS_PSYNC_CLOCK_SEL:
- shift = 7;
- break;
- case VPSS_VPBE_CLOCK:
- read = vpss_regr;
- write = vpss_regw;
- offset = DM365_VPBE_CLK_CTRL;
- break;
- case VPSS_VENC_CLOCK_SEL:
- shift = 2;
- read = vpss_regr;
- write = vpss_regw;
- offset = DM365_VPBE_CLK_CTRL;
- break;
- case VPSS_LDC_CLOCK:
- shift = 3;
- read = vpss_regr;
- write = vpss_regw;
- offset = DM365_VPBE_CLK_CTRL;
- break;
- case VPSS_FDIF_CLOCK:
- shift = 4;
- read = vpss_regr;
- write = vpss_regw;
- offset = DM365_VPBE_CLK_CTRL;
- break;
- case VPSS_OSD_CLOCK_SEL:
- shift = 6;
- read = vpss_regr;
- write = vpss_regw;
- offset = DM365_VPBE_CLK_CTRL;
- break;
- case VPSS_LDC_CLOCK_SEL:
- shift = 7;
- read = vpss_regr;
- write = vpss_regw;
- offset = DM365_VPBE_CLK_CTRL;
- break;
- default:
- printk(KERN_ERR "dm365_enable_clock: Invalid selector: %d\n",
- clock_sel);
- return -1;
- }
-
- spin_lock_irqsave(&oper_cfg.vpss_lock, flags);
- utemp = read(offset);
- if (!en) {
- mask = ~mask;
- utemp &= (mask << shift);
- } else
- utemp |= (mask << shift);
-
- write(utemp, offset);
- spin_unlock_irqrestore(&oper_cfg.vpss_lock, flags);
-
- return 0;
-}
-
-int vpss_enable_clock(enum vpss_clock_sel clock_sel, int en)
-{
- if (!oper_cfg.hw_ops.enable_clock)
- return -EINVAL;
-
- return oper_cfg.hw_ops.enable_clock(clock_sel, en);
-}
-EXPORT_SYMBOL(vpss_enable_clock);
-
-void dm365_vpss_set_sync_pol(struct vpss_sync_pol sync)
-{
- int val = 0;
- val = isp5_read(DM365_ISP5_CCDCMUX);
-
- val |= (sync.ccdpg_hdpol << DM365_CCDC_PG_HD_POL_SHIFT);
- val |= (sync.ccdpg_vdpol << DM365_CCDC_PG_VD_POL_SHIFT);
-
- isp5_write(val, DM365_ISP5_CCDCMUX);
-}
-EXPORT_SYMBOL(dm365_vpss_set_sync_pol);
-
-void vpss_set_pg_frame_size(struct vpss_pg_frame_size frame_size)
-{
- if (!oper_cfg.hw_ops.set_pg_frame_size)
- return;
-
- oper_cfg.hw_ops.set_pg_frame_size(frame_size);
-}
-EXPORT_SYMBOL(vpss_set_pg_frame_size);
-
-void dm365_vpss_set_pg_frame_size(struct vpss_pg_frame_size frame_size)
-{
- int current_reg = ((frame_size.hlpfr >> 1) - 1) << 16;
-
- current_reg |= (frame_size.pplen - 1);
- isp5_write(current_reg, DM365_ISP5_PG_FRAME_SIZE);
-}
-EXPORT_SYMBOL(dm365_vpss_set_pg_frame_size);
-
-static int vpss_probe(struct platform_device *pdev)
-{
- char *platform_name;
-
- if (!pdev->dev.platform_data) {
- dev_err(&pdev->dev, "no platform data\n");
- return -ENOENT;
- }
-
- platform_name = pdev->dev.platform_data;
- if (!strcmp(platform_name, "dm355_vpss"))
- oper_cfg.platform = DM355;
- else if (!strcmp(platform_name, "dm365_vpss"))
- oper_cfg.platform = DM365;
- else if (!strcmp(platform_name, "dm644x_vpss"))
- oper_cfg.platform = DM644X;
- else {
- dev_err(&pdev->dev, "vpss driver not supported on this platform\n");
- return -ENODEV;
- }
-
- dev_info(&pdev->dev, "%s vpss probed\n", platform_name);
- oper_cfg.vpss_regs_base0 = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(oper_cfg.vpss_regs_base0))
- return PTR_ERR(oper_cfg.vpss_regs_base0);
-
- if (oper_cfg.platform == DM355 || oper_cfg.platform == DM365) {
- oper_cfg.vpss_regs_base1 = devm_platform_ioremap_resource(pdev, 1);
- if (IS_ERR(oper_cfg.vpss_regs_base1))
- return PTR_ERR(oper_cfg.vpss_regs_base1);
- }
-
- if (oper_cfg.platform == DM355) {
- oper_cfg.hw_ops.enable_clock = dm355_enable_clock;
- oper_cfg.hw_ops.select_ccdc_source = dm355_select_ccdc_source;
- /* Setup vpss interrupts */
- bl_regw(DM355_VPSSBL_INTSEL_DEFAULT, DM355_VPSSBL_INTSEL);
- bl_regw(DM355_VPSSBL_EVTSEL_DEFAULT, DM355_VPSSBL_EVTSEL);
- } else if (oper_cfg.platform == DM365) {
- oper_cfg.hw_ops.enable_clock = dm365_enable_clock;
- oper_cfg.hw_ops.select_ccdc_source = dm365_select_ccdc_source;
- /* Setup vpss interrupts */
- isp5_write((isp5_read(DM365_ISP5_PCCR) |
- DM365_ISP5_PCCR_BL_CLK_ENABLE |
- DM365_ISP5_PCCR_ISIF_CLK_ENABLE |
- DM365_ISP5_PCCR_H3A_CLK_ENABLE |
- DM365_ISP5_PCCR_RSZ_CLK_ENABLE |
- DM365_ISP5_PCCR_IPIPE_CLK_ENABLE |
- DM365_ISP5_PCCR_IPIPEIF_CLK_ENABLE |
- DM365_ISP5_PCCR_RSV), DM365_ISP5_PCCR);
- isp5_write((isp5_read(DM365_ISP5_BCR) |
- DM365_ISP5_BCR_ISIF_OUT_ENABLE), DM365_ISP5_BCR);
- isp5_write(DM365_ISP5_INTSEL1_DEFAULT, DM365_ISP5_INTSEL1);
- isp5_write(DM365_ISP5_INTSEL2_DEFAULT, DM365_ISP5_INTSEL2);
- isp5_write(DM365_ISP5_INTSEL3_DEFAULT, DM365_ISP5_INTSEL3);
- } else
- oper_cfg.hw_ops.clear_wbl_overflow = dm644x_clear_wbl_overflow;
-
- pm_runtime_enable(&pdev->dev);
-
- pm_runtime_get(&pdev->dev);
-
- spin_lock_init(&oper_cfg.vpss_lock);
- dev_info(&pdev->dev, "%s vpss probe success\n", platform_name);
-
- return 0;
-}
-
-static int vpss_remove(struct platform_device *pdev)
-{
- pm_runtime_disable(&pdev->dev);
- return 0;
-}
-
-static int vpss_suspend(struct device *dev)
-{
- pm_runtime_put(dev);
- return 0;
-}
-
-static int vpss_resume(struct device *dev)
-{
- pm_runtime_get(dev);
- return 0;
-}
-
-static const struct dev_pm_ops vpss_pm_ops = {
- .suspend = vpss_suspend,
- .resume = vpss_resume,
-};
-
-static struct platform_driver vpss_driver = {
- .driver = {
- .name = "vpss",
- .pm = &vpss_pm_ops,
- },
- .remove = vpss_remove,
- .probe = vpss_probe,
-};
-
-static void vpss_exit(void)
-{
- platform_driver_unregister(&vpss_driver);
- iounmap(oper_cfg.vpss_regs_base2);
- release_mem_region(VPSS_CLK_CTRL, 4);
-}
-
-static int __init vpss_init(void)
-{
- int ret;
-
- if (!request_mem_region(VPSS_CLK_CTRL, 4, "vpss_clock_control"))
- return -EBUSY;
-
- oper_cfg.vpss_regs_base2 = ioremap(VPSS_CLK_CTRL, 4);
- if (unlikely(!oper_cfg.vpss_regs_base2)) {
- ret = -ENOMEM;
- goto err_ioremap;
- }
-
- writel(VPSS_CLK_CTRL_VENCCLKEN |
- VPSS_CLK_CTRL_DACCLKEN, oper_cfg.vpss_regs_base2);
-
- ret = platform_driver_register(&vpss_driver);
- if (ret)
- goto err_pd_register;
-
- return 0;
-
-err_pd_register:
- iounmap(oper_cfg.vpss_regs_base2);
-err_ioremap:
- release_mem_region(VPSS_CLK_CTRL, 4);
- return ret;
-}
-subsys_initcall(vpss_init);
-module_exit(vpss_exit);
diff --git a/include/media/davinci/vpbe.h b/include/media/davinci/vpbe.h
deleted file mode 100644
index e74a93475d21..000000000000
--- a/include/media/davinci/vpbe.h
+++ /dev/null
@@ -1,184 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2010 Texas Instruments Inc
- */
-#ifndef _VPBE_H
-#define _VPBE_H
-
-#include <linux/videodev2.h>
-#include <linux/i2c.h>
-
-#include <media/v4l2-dev.h>
-#include <media/v4l2-ioctl.h>
-#include <media/v4l2-device.h>
-#include <media/davinci/vpbe_osd.h>
-#include <media/davinci/vpbe_venc.h>
-#include <media/davinci/vpbe_types.h>
-
-/* OSD configuration info */
-struct osd_config_info {
- char module_name[32];
-};
-
-struct vpbe_output {
- struct v4l2_output output;
- /*
- * If output capabilities include dv_timings, list supported timings
- * below
- */
- char *subdev_name;
- /*
- * defualt_mode identifies the default timings set at the venc or
- * external encoder.
- */
- char *default_mode;
- /*
- * Fields below are used for supporting multiple modes. For example,
- * LCD panel might support different modes and they are listed here.
- * Similarly for supporting external encoders, lcd controller port
- * requires a set of non-standard timing values to be listed here for
- * each supported mode since venc is used in non-standard timing mode
- * for interfacing with external encoder similar to configuring lcd
- * panel timings
- */
- unsigned int num_modes;
- struct vpbe_enc_mode_info *modes;
- /*
- * Bus configuration goes here for external encoders. Some encoders
- * may require multiple interface types for each of the output. For
- * example, SD modes would use YCC8 where as HD mode would use YCC16.
- * Not sure if this is needed on a per mode basis instead of per
- * output basis. If per mode is needed, we may have to move this to
- * mode_info structure
- */
- u32 if_params;
-};
-
-/* encoder configuration info */
-struct encoder_config_info {
- char module_name[32];
- /* Is this an i2c device ? */
- unsigned int is_i2c:1;
- /* i2c subdevice board info */
- struct i2c_board_info board_info;
-};
-
-/*amplifier configuration info */
-struct amp_config_info {
- char module_name[32];
- /* Is this an i2c device ? */
- unsigned int is_i2c:1;
- /* i2c subdevice board info */
- struct i2c_board_info board_info;
-};
-
-/* structure for defining vpbe display subsystem components */
-struct vpbe_config {
- char module_name[32];
- /* i2c bus adapter no */
- int i2c_adapter_id;
- struct osd_config_info osd;
- struct encoder_config_info venc;
- /* external encoder information goes here */
- int num_ext_encoders;
- struct encoder_config_info *ext_encoders;
- /* amplifier information goes here */
- struct amp_config_info *amp;
- unsigned int num_outputs;
- /* Order is venc outputs followed by LCD and then external encoders */
- struct vpbe_output *outputs;
-};
-
-struct vpbe_device;
-
-struct vpbe_device_ops {
- /* Enumerate the outputs */
- int (*enum_outputs)(struct vpbe_device *vpbe_dev,
- struct v4l2_output *output);
-
- /* Set output to the given index */
- int (*set_output)(struct vpbe_device *vpbe_dev,
- int index);
-
- /* Get current output */
- unsigned int (*get_output)(struct vpbe_device *vpbe_dev);
-
- /* Set DV preset at current output */
- int (*s_dv_timings)(struct vpbe_device *vpbe_dev,
- struct v4l2_dv_timings *dv_timings);
-
- /* Get DV presets supported at the output */
- int (*g_dv_timings)(struct vpbe_device *vpbe_dev,
- struct v4l2_dv_timings *dv_timings);
-
- /* Enumerate the DV Presets supported at the output */
- int (*enum_dv_timings)(struct vpbe_device *vpbe_dev,
- struct v4l2_enum_dv_timings *timings_info);
-
- /* Set std at the output */
- int (*s_std)(struct vpbe_device *vpbe_dev, v4l2_std_id std_id);
-
- /* Get the current std at the output */
- int (*g_std)(struct vpbe_device *vpbe_dev, v4l2_std_id *std_id);
-
- /* initialize the device */
- int (*initialize)(struct device *dev, struct vpbe_device *vpbe_dev);
-
- /* De-initialize the device */
- void (*deinitialize)(struct device *dev, struct vpbe_device *vpbe_dev);
-
- /* Get the current mode info */
- int (*get_mode_info)(struct vpbe_device *vpbe_dev,
- struct vpbe_enc_mode_info*);
-
- /*
- * Set the current mode in the encoder. Alternate way of setting
- * standard or DV preset or custom timings in the encoder
- */
- int (*set_mode)(struct vpbe_device *vpbe_dev,
- struct vpbe_enc_mode_info*);
- /* Power management operations */
- int (*suspend)(struct vpbe_device *vpbe_dev);
- int (*resume)(struct vpbe_device *vpbe_dev);
-};
-
-/* struct for vpbe device */
-struct vpbe_device {
- /* V4l2 device */
- struct v4l2_device v4l2_dev;
- /* vpbe dispay controller cfg */
- struct vpbe_config *cfg;
- /* parent device */
- struct device *pdev;
- /* external encoder v4l2 sub devices */
- struct v4l2_subdev **encoders;
- /* current encoder index */
- int current_sd_index;
- /* external amplifier v4l2 subdevice */
- struct v4l2_subdev *amp;
- struct mutex lock;
- /* device initialized */
- int initialized;
- /* vpbe dac clock */
- struct clk *dac_clk;
- /* osd_device pointer */
- struct osd_state *osd_device;
- /* venc device pointer */
- struct venc_platform_data *venc_device;
- /*
- * fields below are accessed by users of vpbe_device. Not the
- * ones above
- */
-
- /* current output */
- int current_out_index;
- /* lock used by caller to do atomic operation on vpbe device */
- /* current timings set in the controller */
- struct vpbe_enc_mode_info current_timings;
- /* venc sub device */
- struct v4l2_subdev *venc;
- /* device operations below */
- struct vpbe_device_ops ops;
-};
-
-#endif
diff --git a/include/media/davinci/vpbe_display.h b/include/media/davinci/vpbe_display.h
deleted file mode 100644
index d8751ea926a2..000000000000
--- a/include/media/davinci/vpbe_display.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
- */
-#ifndef VPBE_DISPLAY_H
-#define VPBE_DISPLAY_H
-
-/* Header files */
-#include <linux/videodev2.h>
-#include <media/v4l2-common.h>
-#include <media/v4l2-fh.h>
-#include <media/videobuf2-v4l2.h>
-#include <media/videobuf2-dma-contig.h>
-#include <media/davinci/vpbe_types.h>
-#include <media/davinci/vpbe_osd.h>
-#include <media/davinci/vpbe.h>
-
-#define VPBE_DISPLAY_MAX_DEVICES 2
-
-enum vpbe_display_device_id {
- VPBE_DISPLAY_DEVICE_0,
- VPBE_DISPLAY_DEVICE_1
-};
-
-#define VPBE_DISPLAY_DRV_NAME "vpbe-display"
-
-#define VPBE_DISPLAY_MAJOR_RELEASE 1
-#define VPBE_DISPLAY_MINOR_RELEASE 0
-#define VPBE_DISPLAY_BUILD 1
-#define VPBE_DISPLAY_VERSION_CODE ((VPBE_DISPLAY_MAJOR_RELEASE << 16) | \
- (VPBE_DISPLAY_MINOR_RELEASE << 8) | \
- VPBE_DISPLAY_BUILD)
-
-#define VPBE_DISPLAY_VALID_FIELD(field) ((V4L2_FIELD_NONE == field) || \
- (V4L2_FIELD_ANY == field) || (V4L2_FIELD_INTERLACED == field))
-
-/* Exp ratio numerator and denominator constants */
-#define VPBE_DISPLAY_H_EXP_RATIO_N 9
-#define VPBE_DISPLAY_H_EXP_RATIO_D 8
-#define VPBE_DISPLAY_V_EXP_RATIO_N 6
-#define VPBE_DISPLAY_V_EXP_RATIO_D 5
-
-/* Zoom multiplication factor */
-#define VPBE_DISPLAY_ZOOM_4X 4
-#define VPBE_DISPLAY_ZOOM_2X 2
-
-/* Structures */
-struct display_layer_info {
- int enable;
- /* Layer ID used by Display Manager */
- enum osd_layer id;
- struct osd_layer_config config;
- enum osd_zoom_factor h_zoom;
- enum osd_zoom_factor v_zoom;
- enum osd_h_exp_ratio h_exp;
- enum osd_v_exp_ratio v_exp;
-};
-
-struct vpbe_disp_buffer {
- struct vb2_v4l2_buffer vb;
- struct list_head list;
-};
-
-/* vpbe display object structure */
-struct vpbe_layer {
- /* Pointer to the vpbe_display */
- struct vpbe_display *disp_dev;
- /* Pointer pointing to current v4l2_buffer */
- struct vpbe_disp_buffer *cur_frm;
- /* Pointer pointing to next v4l2_buffer */
- struct vpbe_disp_buffer *next_frm;
- /* vb2 specific parameters
- * Buffer queue used in vb2
- */
- struct vb2_queue buffer_queue;
- /* Queue of filled frames */
- struct list_head dma_queue;
- /* Used for video buffer handling */
- spinlock_t irqlock;
- /* V4l2 specific parameters */
- /* Identifies video device for this layer */
- struct video_device video_dev;
- /* Used to store pixel format */
- struct v4l2_pix_format pix_fmt;
- enum v4l2_field buf_field;
- /* Video layer configuration params */
- struct display_layer_info layer_info;
- /* vpbe specific parameters
- * enable window for display
- */
- unsigned char window_enable;
- /* number of open instances of the layer */
- unsigned int usrs;
- /* Indicates id of the field which is being displayed */
- unsigned int field_id;
- /* Identifies device object */
- enum vpbe_display_device_id device_id;
- /* facilitation of ioctl ops lock by v4l2*/
- struct mutex opslock;
- u8 layer_first_int;
-};
-
-/* vpbe device structure */
-struct vpbe_display {
- /* layer specific parameters */
- /* lock for isr updates to buf layers*/
- spinlock_t dma_queue_lock;
- /* C-Plane offset from start of y-plane */
- unsigned int cbcr_ofst;
- struct vpbe_layer *dev[VPBE_DISPLAY_MAX_DEVICES];
- struct vpbe_device *vpbe_dev;
- struct osd_state *osd_device;
-};
-
-struct buf_config_params {
- unsigned char min_numbuffers;
- unsigned char numbuffers[VPBE_DISPLAY_MAX_DEVICES];
- unsigned int min_bufsize[VPBE_DISPLAY_MAX_DEVICES];
- unsigned int layer_bufsize[VPBE_DISPLAY_MAX_DEVICES];
-};
-
-#endif /* VPBE_DISPLAY_H */
diff --git a/include/media/davinci/vpbe_osd.h b/include/media/davinci/vpbe_osd.h
deleted file mode 100644
index a4fc4f2a56fb..000000000000
--- a/include/media/davinci/vpbe_osd.h
+++ /dev/null
@@ -1,382 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2007-2009 Texas Instruments Inc
- * Copyright (C) 2007 MontaVista Software, Inc.
- *
- * Andy Lowe (alowe@mvista.com), MontaVista Software
- * - Initial version
- * Murali Karicheri (mkaricheri@gmail.com), Texas Instruments Ltd.
- * - ported to sub device interface
- */
-#ifndef _OSD_H
-#define _OSD_H
-
-#include <media/davinci/vpbe_types.h>
-
-#define DM644X_VPBE_OSD_SUBDEV_NAME "dm644x,vpbe-osd"
-#define DM365_VPBE_OSD_SUBDEV_NAME "dm365,vpbe-osd"
-#define DM355_VPBE_OSD_SUBDEV_NAME "dm355,vpbe-osd"
-
-/**
- * enum osd_layer
- * @WIN_OSD0: On-Screen Display Window 0
- * @WIN_VID0: Video Window 0
- * @WIN_OSD1: On-Screen Display Window 1
- * @WIN_VID1: Video Window 1
- *
- * Description:
- * An enumeration of the osd display layers.
- */
-enum osd_layer {
- WIN_OSD0,
- WIN_VID0,
- WIN_OSD1,
- WIN_VID1,
-};
-
-/**
- * enum osd_win_layer
- * @OSDWIN_OSD0: On-Screen Display Window 0
- * @OSDWIN_OSD1: On-Screen Display Window 1
- *
- * Description:
- * An enumeration of the OSD Window layers.
- */
-enum osd_win_layer {
- OSDWIN_OSD0,
- OSDWIN_OSD1,
-};
-
-/**
- * enum osd_pix_format
- * @PIXFMT_1BPP: 1-bit-per-pixel bitmap
- * @PIXFMT_2BPP: 2-bits-per-pixel bitmap
- * @PIXFMT_4BPP: 4-bits-per-pixel bitmap
- * @PIXFMT_8BPP: 8-bits-per-pixel bitmap
- * @PIXFMT_RGB565: 16-bits-per-pixel RGB565
- * @PIXFMT_YCBCRI: YUV 4:2:2
- * @PIXFMT_RGB888: 24-bits-per-pixel RGB888
- * @PIXFMT_YCRCBI: YUV 4:2:2 with chroma swap
- * @PIXFMT_NV12: YUV 4:2:0 planar
- * @PIXFMT_OSD_ATTR: OSD Attribute Window pixel format (4bpp)
- *
- * Description:
- * An enumeration of the DaVinci pixel formats.
- */
-enum osd_pix_format {
- PIXFMT_1BPP = 0,
- PIXFMT_2BPP,
- PIXFMT_4BPP,
- PIXFMT_8BPP,
- PIXFMT_RGB565,
- PIXFMT_YCBCRI,
- PIXFMT_RGB888,
- PIXFMT_YCRCBI,
- PIXFMT_NV12,
- PIXFMT_OSD_ATTR,
-};
-
-/**
- * enum osd_h_exp_ratio
- * @H_EXP_OFF: no expansion (1/1)
- * @H_EXP_9_OVER_8: 9/8 expansion ratio
- * @H_EXP_3_OVER_2: 3/2 expansion ratio
- *
- * Description:
- * An enumeration of the available horizontal expansion ratios.
- */
-enum osd_h_exp_ratio {
- H_EXP_OFF,
- H_EXP_9_OVER_8,
- H_EXP_3_OVER_2,
-};
-
-/**
- * enum osd_v_exp_ratio
- * @V_EXP_OFF: no expansion (1/1)
- * @V_EXP_6_OVER_5: 6/5 expansion ratio
- *
- * Description:
- * An enumeration of the available vertical expansion ratios.
- */
-enum osd_v_exp_ratio {
- V_EXP_OFF,
- V_EXP_6_OVER_5,
-};
-
-/**
- * enum osd_zoom_factor
- * @ZOOM_X1: no zoom (x1)
- * @ZOOM_X2: x2 zoom
- * @ZOOM_X4: x4 zoom
- *
- * Description:
- * An enumeration of the available zoom factors.
- */
-enum osd_zoom_factor {
- ZOOM_X1,
- ZOOM_X2,
- ZOOM_X4,
-};
-
-/**
- * enum osd_clut
- * @ROM_CLUT: ROM CLUT
- * @RAM_CLUT: RAM CLUT
- *
- * Description:
- * An enumeration of the available Color Lookup Tables (CLUTs).
- */
-enum osd_clut {
- ROM_CLUT,
- RAM_CLUT,
-};
-
-/**
- * enum osd_rom_clut
- * @ROM_CLUT0: Macintosh CLUT
- * @ROM_CLUT1: CLUT from DM270 and prior devices
- *
- * Description:
- * An enumeration of the ROM Color Lookup Table (CLUT) options.
- */
-enum osd_rom_clut {
- ROM_CLUT0,
- ROM_CLUT1,
-};
-
-/**
- * enum osd_blending_factor
- * @OSD_0_VID_8: OSD pixels are fully transparent
- * @OSD_1_VID_7: OSD pixels contribute 1/8, video pixels contribute 7/8
- * @OSD_2_VID_6: OSD pixels contribute 2/8, video pixels contribute 6/8
- * @OSD_3_VID_5: OSD pixels contribute 3/8, video pixels contribute 5/8
- * @OSD_4_VID_4: OSD pixels contribute 4/8, video pixels contribute 4/8
- * @OSD_5_VID_3: OSD pixels contribute 5/8, video pixels contribute 3/8
- * @OSD_6_VID_2: OSD pixels contribute 6/8, video pixels contribute 2/8
- * @OSD_8_VID_0: OSD pixels are fully opaque
- *
- * Description:
- * An enumeration of the DaVinci pixel blending factor options.
- */
-enum osd_blending_factor {
- OSD_0_VID_8,
- OSD_1_VID_7,
- OSD_2_VID_6,
- OSD_3_VID_5,
- OSD_4_VID_4,
- OSD_5_VID_3,
- OSD_6_VID_2,
- OSD_8_VID_0,
-};
-
-/**
- * enum osd_blink_interval
- * @BLINK_X1: blink interval is 1 vertical refresh cycle
- * @BLINK_X2: blink interval is 2 vertical refresh cycles
- * @BLINK_X3: blink interval is 3 vertical refresh cycles
- * @BLINK_X4: blink interval is 4 vertical refresh cycles
- *
- * Description:
- * An enumeration of the DaVinci pixel blinking interval options.
- */
-enum osd_blink_interval {
- BLINK_X1,
- BLINK_X2,
- BLINK_X3,
- BLINK_X4,
-};
-
-/**
- * enum osd_cursor_h_width
- * @H_WIDTH_1: horizontal line width is 1 pixel
- * @H_WIDTH_4: horizontal line width is 4 pixels
- * @H_WIDTH_8: horizontal line width is 8 pixels
- * @H_WIDTH_12: horizontal line width is 12 pixels
- * @H_WIDTH_16: horizontal line width is 16 pixels
- * @H_WIDTH_20: horizontal line width is 20 pixels
- * @H_WIDTH_24: horizontal line width is 24 pixels
- * @H_WIDTH_28: horizontal line width is 28 pixels
- */
-enum osd_cursor_h_width {
- H_WIDTH_1,
- H_WIDTH_4,
- H_WIDTH_8,
- H_WIDTH_12,
- H_WIDTH_16,
- H_WIDTH_20,
- H_WIDTH_24,
- H_WIDTH_28,
-};
-
-/**
- * enum osd_cursor_v_width
- * @V_WIDTH_1: vertical line width is 1 line
- * @V_WIDTH_2: vertical line width is 2 lines
- * @V_WIDTH_4: vertical line width is 4 lines
- * @V_WIDTH_6: vertical line width is 6 lines
- * @V_WIDTH_8: vertical line width is 8 lines
- * @V_WIDTH_10: vertical line width is 10 lines
- * @V_WIDTH_12: vertical line width is 12 lines
- * @V_WIDTH_14: vertical line width is 14 lines
- */
-enum osd_cursor_v_width {
- V_WIDTH_1,
- V_WIDTH_2,
- V_WIDTH_4,
- V_WIDTH_6,
- V_WIDTH_8,
- V_WIDTH_10,
- V_WIDTH_12,
- V_WIDTH_14,
-};
-
-/**
- * struct osd_cursor_config
- * @xsize: horizontal size in pixels
- * @ysize: vertical size in lines
- * @xpos: horizontal offset in pixels from the left edge of the display
- * @ypos: vertical offset in lines from the top of the display
- * @interlaced: Non-zero if the display is interlaced, or zero otherwise
- * @h_width: horizontal line width
- * @v_width: vertical line width
- * @clut: the CLUT selector (ROM or RAM) for the cursor color
- * @clut_index: an index into the CLUT for the cursor color
- *
- * Description:
- * A structure describing the configuration parameters of the hardware
- * rectangular cursor.
- */
-struct osd_cursor_config {
- unsigned xsize;
- unsigned ysize;
- unsigned xpos;
- unsigned ypos;
- int interlaced;
- enum osd_cursor_h_width h_width;
- enum osd_cursor_v_width v_width;
- enum osd_clut clut;
- unsigned char clut_index;
-};
-
-/**
- * struct osd_layer_config
- * @pixfmt: pixel format
- * @line_length: offset in bytes between start of each line in memory
- * @xsize: number of horizontal pixels displayed per line
- * @ysize: number of lines displayed
- * @xpos: horizontal offset in pixels from the left edge of the display
- * @ypos: vertical offset in lines from the top of the display
- * @interlaced: Non-zero if the display is interlaced, or zero otherwise
- *
- * Description:
- * A structure describing the configuration parameters of an On-Screen Display
- * (OSD) or video layer related to how the image is stored in memory.
- * @line_length must be a multiple of the cache line size (32 bytes).
- */
-struct osd_layer_config {
- enum osd_pix_format pixfmt;
- unsigned line_length;
- unsigned xsize;
- unsigned ysize;
- unsigned xpos;
- unsigned ypos;
- int interlaced;
-};
-
-/* parameters that apply on a per-window (OSD or video) basis */
-struct osd_window_state {
- int is_allocated;
- int is_enabled;
- unsigned long fb_base_phys;
- enum osd_zoom_factor h_zoom;
- enum osd_zoom_factor v_zoom;
- struct osd_layer_config lconfig;
-};
-
-/* parameters that apply on a per-OSD-window basis */
-struct osd_osdwin_state {
- enum osd_clut clut;
- enum osd_blending_factor blend;
- int colorkey_blending;
- unsigned colorkey;
- int rec601_attenuation;
- /* index is pixel value */
- unsigned char palette_map[16];
-};
-
-/* hardware rectangular cursor parameters */
-struct osd_cursor_state {
- int is_enabled;
- struct osd_cursor_config config;
-};
-
-struct osd_state;
-
-struct vpbe_osd_ops {
- int (*initialize)(struct osd_state *sd);
- int (*request_layer)(struct osd_state *sd, enum osd_layer layer);
- void (*release_layer)(struct osd_state *sd, enum osd_layer layer);
- int (*enable_layer)(struct osd_state *sd, enum osd_layer layer,
- int otherwin);
- void (*disable_layer)(struct osd_state *sd, enum osd_layer layer);
- int (*set_layer_config)(struct osd_state *sd, enum osd_layer layer,
- struct osd_layer_config *lconfig);
- void (*get_layer_config)(struct osd_state *sd, enum osd_layer layer,
- struct osd_layer_config *lconfig);
- void (*start_layer)(struct osd_state *sd, enum osd_layer layer,
- unsigned long fb_base_phys,
- unsigned long cbcr_ofst);
- void (*set_left_margin)(struct osd_state *sd, u32 val);
- void (*set_top_margin)(struct osd_state *sd, u32 val);
- void (*set_interpolation_filter)(struct osd_state *sd, int filter);
- int (*set_vid_expansion)(struct osd_state *sd,
- enum osd_h_exp_ratio h_exp,
- enum osd_v_exp_ratio v_exp);
- void (*get_vid_expansion)(struct osd_state *sd,
- enum osd_h_exp_ratio *h_exp,
- enum osd_v_exp_ratio *v_exp);
- void (*set_zoom)(struct osd_state *sd, enum osd_layer layer,
- enum osd_zoom_factor h_zoom,
- enum osd_zoom_factor v_zoom);
-};
-
-struct osd_state {
- enum vpbe_version vpbe_type;
- spinlock_t lock;
- struct device *dev;
- dma_addr_t osd_base_phys;
- void __iomem *osd_base;
- unsigned long osd_size;
- /* 1-->the isr will toggle the VID0 ping-pong buffer */
- int pingpong;
- int interpolation_filter;
- int field_inversion;
- enum osd_h_exp_ratio osd_h_exp;
- enum osd_v_exp_ratio osd_v_exp;
- enum osd_h_exp_ratio vid_h_exp;
- enum osd_v_exp_ratio vid_v_exp;
- enum osd_clut backg_clut;
- unsigned backg_clut_index;
- enum osd_rom_clut rom_clut;
- int is_blinking;
- /* attribute window blinking enabled */
- enum osd_blink_interval blink;
- /* YCbCrI or YCrCbI */
- enum osd_pix_format yc_pixfmt;
- /* columns are Y, Cb, Cr */
- unsigned char clut_ram[256][3];
- struct osd_cursor_state cursor;
- /* OSD0, VID0, OSD1, VID1 */
- struct osd_window_state win[4];
- /* OSD0, OSD1 */
- struct osd_osdwin_state osdwin[2];
- /* OSD device Operations */
- struct vpbe_osd_ops ops;
-};
-
-struct osd_platform_data {
- int field_inv_wa_enable;
-};
-
-#endif
diff --git a/include/media/davinci/vpbe_types.h b/include/media/davinci/vpbe_types.h
deleted file mode 100644
index 6015cda235cc..000000000000
--- a/include/media/davinci/vpbe_types.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2010 Texas Instruments Inc
- */
-#ifndef _VPBE_TYPES_H
-#define _VPBE_TYPES_H
-
-enum vpbe_version {
- VPBE_VERSION_1 = 1,
- VPBE_VERSION_2,
- VPBE_VERSION_3,
-};
-
-/* vpbe_timing_type - Timing types used in vpbe device */
-enum vpbe_enc_timings_type {
- VPBE_ENC_STD = 0x1,
- VPBE_ENC_DV_TIMINGS = 0x4,
- /* Used when set timings through FB device interface */
- VPBE_ENC_TIMINGS_INVALID = 0x8,
-};
-
-/*
- * struct vpbe_enc_mode_info
- * @name: ptr to name string of the standard, "NTSC", "PAL" etc
- * @std: standard or non-standard mode. 1 - standard, 0 - nonstandard
- * @interlaced: 1 - interlaced, 0 - non interlaced/progressive
- * @xres: x or horizontal resolution of the display
- * @yres: y or vertical resolution of the display
- * @fps: frame per second
- * @left_margin: left margin of the display
- * @right_margin: right margin of the display
- * @upper_margin: upper margin of the display
- * @lower_margin: lower margin of the display
- * @hsync_len: h-sync length
- * @vsync_len: v-sync length
- * @flags: bit field: bit usage is documented below
- *
- * Description:
- * Structure holding timing and resolution information of a standard.
- * Used by vpbe_device to set required non-standard timing in the
- * venc when lcd controller output is connected to a external encoder.
- * A table of timings is maintained in vpbe device to set this in
- * venc when external encoder is connected to lcd controller output.
- * Encoder may provide a g_dv_timings() API to override these values
- * as needed.
- *
- * Notes
- * ------
- * if_type should be used only by encoder manager and encoder.
- * flags usage
- * b0 (LSB) - hsync polarity, 0 - negative, 1 - positive
- * b1 - vsync polarity, 0 - negative, 1 - positive
- * b2 - field id polarity, 0 - negative, 1 - positive
- */
-struct vpbe_enc_mode_info {
- unsigned char *name;
- enum vpbe_enc_timings_type timings_type;
- v4l2_std_id std_id;
- struct v4l2_dv_timings dv_timings;
- unsigned int interlaced;
- unsigned int xres;
- unsigned int yres;
- struct v4l2_fract aspect;
- struct v4l2_fract fps;
- unsigned int left_margin;
- unsigned int right_margin;
- unsigned int upper_margin;
- unsigned int lower_margin;
- unsigned int hsync_len;
- unsigned int vsync_len;
- unsigned int flags;
-};
-
-#endif
diff --git a/include/media/davinci/vpbe_venc.h b/include/media/davinci/vpbe_venc.h
deleted file mode 100644
index 93cf6a5fb49d..000000000000
--- a/include/media/davinci/vpbe_venc.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2010 Texas Instruments Inc
- */
-#ifndef _VPBE_VENC_H
-#define _VPBE_VENC_H
-
-#include <media/v4l2-subdev.h>
-#include <media/davinci/vpbe_types.h>
-
-#define DM644X_VPBE_VENC_SUBDEV_NAME "dm644x,vpbe-venc"
-#define DM365_VPBE_VENC_SUBDEV_NAME "dm365,vpbe-venc"
-#define DM355_VPBE_VENC_SUBDEV_NAME "dm355,vpbe-venc"
-
-/* venc events */
-#define VENC_END_OF_FRAME BIT(0)
-#define VENC_FIRST_FIELD BIT(1)
-#define VENC_SECOND_FIELD BIT(2)
-
-struct venc_platform_data {
- int (*setup_pinmux)(u32 if_type, int field);
- int (*setup_clock)(enum vpbe_enc_timings_type type,
- unsigned int pixclock);
- int (*setup_if_config)(u32 pixcode);
- /* Number of LCD outputs supported */
- int num_lcd_outputs;
- struct vpbe_if_params *lcd_if_params;
-};
-
-enum venc_ioctls {
- VENC_GET_FLD = 1,
-};
-
-/* exported functions */
-struct v4l2_subdev *venc_sub_dev_init(struct v4l2_device *v4l2_dev,
- const char *venc_name);
-#endif
diff --git a/include/media/davinci/vpss.h b/include/media/davinci/vpss.h
deleted file mode 100644
index 315fa77e238c..000000000000
--- a/include/media/davinci/vpss.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright (C) 2009 Texas Instruments Inc
- *
- * vpss - video processing subsystem module header file.
- *
- * Include this header file if a driver needs to configure vpss system
- * module. It exports a set of library functions for video drivers to
- * configure vpss system module functions such as clock enable/disable,
- * vpss interrupt mux to arm, and other common vpss system module
- * functions.
- */
-#ifndef _VPSS_H
-#define _VPSS_H
-
-/* selector for ccdc input selection on DM355 */
-enum vpss_ccdc_source_sel {
- VPSS_CCDCIN,
- VPSS_HSSIIN,
- VPSS_PGLPBK, /* for DM365 only */
- VPSS_CCDCPG /* for DM365 only */
-};
-
-struct vpss_sync_pol {
- unsigned int ccdpg_hdpol:1;
- unsigned int ccdpg_vdpol:1;
-};
-
-struct vpss_pg_frame_size {
- short hlpfr;
- short pplen;
-};
-
-/* Used for enable/disable VPSS Clock */
-enum vpss_clock_sel {
- /* DM355/DM365 */
- VPSS_CCDC_CLOCK,
- VPSS_IPIPE_CLOCK,
- VPSS_H3A_CLOCK,
- VPSS_CFALD_CLOCK,
- /*
- * When using VPSS_VENC_CLOCK_SEL in vpss_enable_clock() api
- * following applies:-
- * en = 0 selects ENC_CLK
- * en = 1 selects ENC_CLK/2
- */
- VPSS_VENC_CLOCK_SEL,
- VPSS_VPBE_CLOCK,
- /* DM365 only clocks */
- VPSS_IPIPEIF_CLOCK,
- VPSS_RSZ_CLOCK,
- VPSS_BL_CLOCK,
- /*
- * When using VPSS_PCLK_INTERNAL in vpss_enable_clock() api
- * following applies:-
- * en = 0 disable internal PCLK
- * en = 1 enables internal PCLK
- */
- VPSS_PCLK_INTERNAL,
- /*
- * When using VPSS_PSYNC_CLOCK_SEL in vpss_enable_clock() api
- * following applies:-
- * en = 0 enables MMR clock
- * en = 1 enables VPSS clock
- */
- VPSS_PSYNC_CLOCK_SEL,
- VPSS_LDC_CLOCK_SEL,
- VPSS_OSD_CLOCK_SEL,
- VPSS_FDIF_CLOCK,
- VPSS_LDC_CLOCK
-};
-
-/* select input to ccdc on dm355 */
-int vpss_select_ccdc_source(enum vpss_ccdc_source_sel src_sel);
-/* enable/disable a vpss clock, 0 - success, -1 - failure */
-int vpss_enable_clock(enum vpss_clock_sel clock_sel, int en);
-/* set sync polarity, only for DM365*/
-void dm365_vpss_set_sync_pol(struct vpss_sync_pol);
-/* set the PG_FRAME_SIZE register, only for DM365 */
-void dm365_vpss_set_pg_frame_size(struct vpss_pg_frame_size);
-
-/* wbl reset for dm644x */
-enum vpss_wbl_sel {
- VPSS_PCR_AEW_WBL_0 = 16,
- VPSS_PCR_AF_WBL_0,
- VPSS_PCR_RSZ4_WBL_0,
- VPSS_PCR_RSZ3_WBL_0,
- VPSS_PCR_RSZ2_WBL_0,
- VPSS_PCR_RSZ1_WBL_0,
- VPSS_PCR_PREV_WBL_0,
- VPSS_PCR_CCDC_WBL_O,
-};
-/* clear wbl overflow flag for DM6446 */
-int vpss_clear_wbl_overflow(enum vpss_wbl_sel wbl_sel);
-
-/* set sync polarity*/
-void vpss_set_sync_pol(struct vpss_sync_pol sync);
-/* set the PG_FRAME_SIZE register */
-void vpss_set_pg_frame_size(struct vpss_pg_frame_size frame_size);
-/*
- * vpss_check_and_clear_interrupt - check and clear interrupt
- * @irq - common enumerator for IRQ
- *
- * Following return values used:-
- * 0 - interrupt occurred and cleared
- * 1 - interrupt not occurred
- * 2 - interrupt status not available
- */
-int vpss_dma_complete_interrupt(void);
-
-#endif
--
2.29.2
^ permalink raw reply related [flat|nested] 48+ messages in thread* Re: [PATCH 14/14] media: davinci: remove vpbe support
2022-10-19 15:29 ` [PATCH 14/14] media: davinci: remove vpbe support Arnd Bergmann
@ 2022-10-24 11:03 ` Hans Verkuil
2022-10-25 22:22 ` Lad, Prabhakar
1 sibling, 0 replies; 48+ messages in thread
From: Hans Verkuil @ 2022-10-24 11:03 UTC (permalink / raw)
To: Arnd Bergmann, Sekhar Nori, Bartosz Golaszewski,
linux-arm-kernel, Mauro Carvalho Chehab, Lad, Prabhakar
Cc: linux-kernel, Kevin Hilman, Arnd Bergmann, linux-media
Hi Arnd,
On 10/19/22 17:29, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> The davinci dm3xx/dm644x platforms are gone now, and the remaining
> da8xx platforms do not use the vpbe driver, so the driver can be
> removed as well.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
As discussed on irc, it is best if you merge this to due dependencies on
arch/arm/mach-davinci/davinci.h.
Regards,
Hans
> ---
> .../admin-guide/media/davinci-vpbe.rst | 65 -
> .../admin-guide/media/platform-cardlist.rst | 1 -
> .../admin-guide/media/v4l-drivers.rst | 1 -
> .../media/drivers/davinci-vpbe-devel.rst | 39 -
> .../driver-api/media/drivers/index.rst | 1 -
> drivers/media/platform/ti/davinci/Kconfig | 16 -
> drivers/media/platform/ti/davinci/Makefile | 3 -
> drivers/media/platform/ti/davinci/vpbe.c | 840 ---------
> .../media/platform/ti/davinci/vpbe_display.c | 1510 ----------------
> drivers/media/platform/ti/davinci/vpbe_osd.c | 1582 -----------------
> .../media/platform/ti/davinci/vpbe_osd_regs.h | 352 ----
> drivers/media/platform/ti/davinci/vpbe_venc.c | 676 -------
> .../platform/ti/davinci/vpbe_venc_regs.h | 165 --
> drivers/media/platform/ti/davinci/vpss.c | 529 ------
> include/media/davinci/vpbe.h | 184 --
> include/media/davinci/vpbe_display.h | 122 --
> include/media/davinci/vpbe_osd.h | 382 ----
> include/media/davinci/vpbe_types.h | 74 -
> include/media/davinci/vpbe_venc.h | 37 -
> include/media/davinci/vpss.h | 111 --
> 20 files changed, 6690 deletions(-)
> delete mode 100644 Documentation/admin-guide/media/davinci-vpbe.rst
> delete mode 100644 Documentation/driver-api/media/drivers/davinci-vpbe-devel.rst
> delete mode 100644 drivers/media/platform/ti/davinci/vpbe.c
> delete mode 100644 drivers/media/platform/ti/davinci/vpbe_display.c
> delete mode 100644 drivers/media/platform/ti/davinci/vpbe_osd.c
> delete mode 100644 drivers/media/platform/ti/davinci/vpbe_osd_regs.h
> delete mode 100644 drivers/media/platform/ti/davinci/vpbe_venc.c
> delete mode 100644 drivers/media/platform/ti/davinci/vpbe_venc_regs.h
> delete mode 100644 drivers/media/platform/ti/davinci/vpss.c
> delete mode 100644 include/media/davinci/vpbe.h
> delete mode 100644 include/media/davinci/vpbe_display.h
> delete mode 100644 include/media/davinci/vpbe_osd.h
> delete mode 100644 include/media/davinci/vpbe_types.h
> delete mode 100644 include/media/davinci/vpbe_venc.h
> delete mode 100644 include/media/davinci/vpss.h
>
> diff --git a/Documentation/admin-guide/media/davinci-vpbe.rst b/Documentation/admin-guide/media/davinci-vpbe.rst
> deleted file mode 100644
> index 9e6360fd02db..000000000000
> --- a/Documentation/admin-guide/media/davinci-vpbe.rst
> +++ /dev/null
> @@ -1,65 +0,0 @@
> -.. SPDX-License-Identifier: GPL-2.0
> -
> -The VPBE V4L2 driver design
> -===========================
> -
> -Functional partitioning
> ------------------------
> -
> -Consists of the following:
> -
> - 1. V4L2 display driver
> -
> - Implements creation of video2 and video3 device nodes and
> - provides v4l2 device interface to manage VID0 and VID1 layers.
> -
> - 2. Display controller
> -
> - Loads up VENC, OSD and external encoders such as ths8200. It provides
> - a set of API calls to V4L2 drivers to set the output/standards
> - in the VENC or external sub devices. It also provides
> - a device object to access the services from OSD subdevice
> - using sub device ops. The connection of external encoders to VENC LCD
> - controller port is done at init time based on default output and standard
> - selection or at run time when application change the output through
> - V4L2 IOCTLs.
> -
> - When connected to an external encoder, vpbe controller is also responsible
> - for setting up the interface between VENC and external encoders based on
> - board specific settings (specified in board-xxx-evm.c). This allows
> - interfacing external encoders such as ths8200. The setup_if_config()
> - is implemented for this as well as configure_venc() (part of the next patch)
> - API to set timings in VENC for a specific display resolution. As of this
> - patch series, the interconnection and enabling and setting of the external
> - encoders is not present, and would be a part of the next patch series.
> -
> - 3. VENC subdevice module
> -
> - Responsible for setting outputs provided through internal DACs and also
> - setting timings at LCD controller port when external encoders are connected
> - at the port or LCD panel timings required. When external encoder/LCD panel
> - is connected, the timings for a specific standard/preset is retrieved from
> - the board specific table and the values are used to set the timings in
> - venc using non-standard timing mode.
> -
> - Support LCD Panel displays using the VENC. For example to support a Logic
> - PD display, it requires setting up the LCD controller port with a set of
> - timings for the resolution supported and setting the dot clock. So we could
> - add the available outputs as a board specific entry (i.e add the "LogicPD"
> - output name to board-xxx-evm.c). A table of timings for various LCDs
> - supported can be maintained in the board specific setup file to support
> - various LCD displays.As of this patch a basic driver is present, and this
> - support for external encoders and displays forms a part of the next
> - patch series.
> -
> - 4. OSD module
> -
> - OSD module implements all OSD layer management and hardware specific
> - features. The VPBE module interacts with the OSD for enabling and
> - disabling appropriate features of the OSD.
> -
> -Current status
> ---------------
> -
> -A fully functional working version of the V4L2 driver is available. This
> -driver has been tested with NTSC and PAL standards and buffer streaming.
> diff --git a/Documentation/admin-guide/media/platform-cardlist.rst b/Documentation/admin-guide/media/platform-cardlist.rst
> index ac73c4166d1e..8ef57cd13dec 100644
> --- a/Documentation/admin-guide/media/platform-cardlist.rst
> +++ b/Documentation/admin-guide/media/platform-cardlist.rst
> @@ -73,7 +73,6 @@ via-camera VIAFB camera controller
> video-mux Video Multiplexer
> vpif_display TI DaVinci VPIF V4L2-Display
> vpif_capture TI DaVinci VPIF video capture
> -vpss TI DaVinci VPBE V4L2-Display
> vsp1 Renesas VSP1 Video Processing Engine
> xilinx-tpg Xilinx Video Test Pattern Generator
> xilinx-video Xilinx Video IP (EXPERIMENTAL)
> diff --git a/Documentation/admin-guide/media/v4l-drivers.rst b/Documentation/admin-guide/media/v4l-drivers.rst
> index 9c7ebe2ca3bd..13f8a39366c9 100644
> --- a/Documentation/admin-guide/media/v4l-drivers.rst
> +++ b/Documentation/admin-guide/media/v4l-drivers.rst
> @@ -13,7 +13,6 @@ Video4Linux (V4L) driver-specific documentation
> cafe_ccic
> cpia2
> cx88
> - davinci-vpbe
> fimc
> imx
> imx7
> diff --git a/Documentation/driver-api/media/drivers/davinci-vpbe-devel.rst b/Documentation/driver-api/media/drivers/davinci-vpbe-devel.rst
> deleted file mode 100644
> index 4e87bdbc7ae4..000000000000
> --- a/Documentation/driver-api/media/drivers/davinci-vpbe-devel.rst
> +++ /dev/null
> @@ -1,39 +0,0 @@
> -.. SPDX-License-Identifier: GPL-2.0
> -
> -The VPBE V4L2 driver design
> -===========================
> -
> -File partitioning
> ------------------
> -
> - V4L2 display device driver
> - drivers/media/platform/ti/davinci/vpbe_display.c
> - drivers/media/platform/ti/davinci/vpbe_display.h
> -
> - VPBE display controller
> - drivers/media/platform/ti/davinci/vpbe.c
> - drivers/media/platform/ti/davinci/vpbe.h
> -
> - VPBE venc sub device driver
> - drivers/media/platform/ti/davinci/vpbe_venc.c
> - drivers/media/platform/ti/davinci/vpbe_venc.h
> - drivers/media/platform/ti/davinci/vpbe_venc_regs.h
> -
> - VPBE osd driver
> - drivers/media/platform/ti/davinci/vpbe_osd.c
> - drivers/media/platform/ti/davinci/vpbe_osd.h
> - drivers/media/platform/ti/davinci/vpbe_osd_regs.h
> -
> -To be done
> -----------
> -
> -vpbe display controller
> - - Add support for external encoders.
> - - add support for selecting external encoder as default at probe time.
> -
> -vpbe venc sub device
> - - add timings for supporting ths8200
> - - add support for LogicPD LCD.
> -
> -FB drivers
> - - Add support for fbdev drivers.- Ready and part of subsequent patches.
> diff --git a/Documentation/driver-api/media/drivers/index.rst b/Documentation/driver-api/media/drivers/index.rst
> index 32406490557c..3c17d48f83c0 100644
> --- a/Documentation/driver-api/media/drivers/index.rst
> +++ b/Documentation/driver-api/media/drivers/index.rst
> @@ -16,7 +16,6 @@ Video4Linux (V4L) drivers
> cpia2_devel
> cx2341x-devel
> cx88-devel
> - davinci-vpbe-devel
> fimc-devel
> pvrusb2
> pxa_camera
> diff --git a/drivers/media/platform/ti/davinci/Kconfig b/drivers/media/platform/ti/davinci/Kconfig
> index 96d4bed7fe9e..542a602e66be 100644
> --- a/drivers/media/platform/ti/davinci/Kconfig
> +++ b/drivers/media/platform/ti/davinci/Kconfig
> @@ -31,19 +31,3 @@ config VIDEO_DAVINCI_VPIF_CAPTURE
>
> To compile this driver as a module, choose M here. There will
> be two modules called vpif.ko and vpif_capture.ko
> -
> -config VIDEO_DAVINCI_VPBE_DISPLAY
> - tristate "TI DaVinci VPBE V4L2-Display driver"
> - depends on V4L_PLATFORM_DRIVERS
> - depends on VIDEO_DEV
> - depends on ARCH_DAVINCI || COMPILE_TEST
> - depends on I2C
> - select VIDEOBUF2_DMA_CONTIG
> - help
> - Enables Davinci VPBE module used for display devices.
> - This module is used for display on TI DM644x/DM365/DM355
> - based display devices.
> -
> - To compile this driver as a module, choose M here. There will
> - be five modules created called vpss.ko, vpbe.ko, vpbe_osd.ko,
> - vpbe_venc.ko and vpbe_display.ko
> diff --git a/drivers/media/platform/ti/davinci/Makefile b/drivers/media/platform/ti/davinci/Makefile
> index b20a91653162..512f03369bae 100644
> --- a/drivers/media/platform/ti/davinci/Makefile
> +++ b/drivers/media/platform/ti/davinci/Makefile
> @@ -7,6 +7,3 @@
> obj-$(CONFIG_VIDEO_DAVINCI_VPIF_DISPLAY) += vpif.o vpif_display.o
> #VPIF Capture driver
> obj-$(CONFIG_VIDEO_DAVINCI_VPIF_CAPTURE) += vpif.o vpif_capture.o
> -
> -obj-$(CONFIG_VIDEO_DAVINCI_VPBE_DISPLAY) += vpss.o vpbe.o vpbe_osd.o \
> - vpbe_venc.o vpbe_display.o
> diff --git a/drivers/media/platform/ti/davinci/vpbe.c b/drivers/media/platform/ti/davinci/vpbe.c
> deleted file mode 100644
> index 509ecc84624e..000000000000
> --- a/drivers/media/platform/ti/davinci/vpbe.c
> +++ /dev/null
> @@ -1,840 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * Copyright (C) 2010 Texas Instruments Inc
> - */
> -#include <linux/kernel.h>
> -#include <linux/init.h>
> -#include <linux/module.h>
> -#include <linux/errno.h>
> -#include <linux/fs.h>
> -#include <linux/string.h>
> -#include <linux/wait.h>
> -#include <linux/time.h>
> -#include <linux/platform_device.h>
> -#include <linux/io.h>
> -#include <linux/slab.h>
> -#include <linux/clk.h>
> -#include <linux/err.h>
> -
> -#include <media/v4l2-device.h>
> -#include <media/davinci/vpbe_types.h>
> -#include <media/davinci/vpbe.h>
> -#include <media/davinci/vpss.h>
> -#include <media/davinci/vpbe_venc.h>
> -
> -#define VPBE_DEFAULT_OUTPUT "Composite"
> -#define VPBE_DEFAULT_MODE "ntsc"
> -
> -static char *def_output = VPBE_DEFAULT_OUTPUT;
> -static char *def_mode = VPBE_DEFAULT_MODE;
> -static int debug;
> -
> -module_param(def_output, charp, S_IRUGO);
> -module_param(def_mode, charp, S_IRUGO);
> -module_param(debug, int, 0644);
> -
> -MODULE_PARM_DESC(def_output, "vpbe output name (default:Composite)");
> -MODULE_PARM_DESC(def_mode, "vpbe output mode name (default:ntsc");
> -MODULE_PARM_DESC(debug, "Debug level 0-1");
> -
> -MODULE_DESCRIPTION("TI DMXXX VPBE Display controller");
> -MODULE_LICENSE("GPL");
> -MODULE_AUTHOR("Texas Instruments");
> -
> -/**
> - * vpbe_current_encoder_info - Get config info for current encoder
> - * @vpbe_dev: vpbe device ptr
> - *
> - * Return ptr to current encoder config info
> - */
> -static struct encoder_config_info*
> -vpbe_current_encoder_info(struct vpbe_device *vpbe_dev)
> -{
> - struct vpbe_config *cfg = vpbe_dev->cfg;
> - int index = vpbe_dev->current_sd_index;
> -
> - return ((index == 0) ? &cfg->venc :
> - &cfg->ext_encoders[index-1]);
> -}
> -
> -/**
> - * vpbe_find_encoder_sd_index - Given a name find encoder sd index
> - *
> - * @cfg: ptr to vpbe cfg
> - * @index: index used by application
> - *
> - * Return sd index of the encoder
> - */
> -static int vpbe_find_encoder_sd_index(struct vpbe_config *cfg,
> - int index)
> -{
> - char *encoder_name = cfg->outputs[index].subdev_name;
> - int i;
> -
> - /* Venc is always first */
> - if (!strcmp(encoder_name, cfg->venc.module_name))
> - return 0;
> -
> - for (i = 0; i < cfg->num_ext_encoders; i++) {
> - if (!strcmp(encoder_name,
> - cfg->ext_encoders[i].module_name))
> - return i+1;
> - }
> -
> - return -EINVAL;
> -}
> -
> -/**
> - * vpbe_enum_outputs - enumerate outputs
> - * @vpbe_dev: vpbe device ptr
> - * @output: ptr to v4l2_output structure
> - *
> - * Enumerates the outputs available at the vpbe display
> - * returns the status, -EINVAL if end of output list
> - */
> -static int vpbe_enum_outputs(struct vpbe_device *vpbe_dev,
> - struct v4l2_output *output)
> -{
> - struct vpbe_config *cfg = vpbe_dev->cfg;
> - unsigned int temp_index = output->index;
> -
> - if (temp_index >= cfg->num_outputs)
> - return -EINVAL;
> -
> - *output = cfg->outputs[temp_index].output;
> - output->index = temp_index;
> -
> - return 0;
> -}
> -
> -static int vpbe_get_mode_info(struct vpbe_device *vpbe_dev, char *mode,
> - int output_index)
> -{
> - struct vpbe_config *cfg = vpbe_dev->cfg;
> - struct vpbe_enc_mode_info var;
> - int curr_output = output_index;
> - int i;
> -
> - if (!mode)
> - return -EINVAL;
> -
> - for (i = 0; i < cfg->outputs[curr_output].num_modes; i++) {
> - var = cfg->outputs[curr_output].modes[i];
> - if (!strcmp(mode, var.name)) {
> - vpbe_dev->current_timings = var;
> - return 0;
> - }
> - }
> -
> - return -EINVAL;
> -}
> -
> -static int vpbe_get_current_mode_info(struct vpbe_device *vpbe_dev,
> - struct vpbe_enc_mode_info *mode_info)
> -{
> - if (!mode_info)
> - return -EINVAL;
> -
> - *mode_info = vpbe_dev->current_timings;
> -
> - return 0;
> -}
> -
> -/* Get std by std id */
> -static int vpbe_get_std_info(struct vpbe_device *vpbe_dev,
> - v4l2_std_id std_id)
> -{
> - struct vpbe_config *cfg = vpbe_dev->cfg;
> - struct vpbe_enc_mode_info var;
> - int curr_output = vpbe_dev->current_out_index;
> - int i;
> -
> - for (i = 0; i < vpbe_dev->cfg->outputs[curr_output].num_modes; i++) {
> - var = cfg->outputs[curr_output].modes[i];
> - if ((var.timings_type & VPBE_ENC_STD) &&
> - (var.std_id & std_id)) {
> - vpbe_dev->current_timings = var;
> - return 0;
> - }
> - }
> -
> - return -EINVAL;
> -}
> -
> -static int vpbe_get_std_info_by_name(struct vpbe_device *vpbe_dev,
> - char *std_name)
> -{
> - struct vpbe_config *cfg = vpbe_dev->cfg;
> - struct vpbe_enc_mode_info var;
> - int curr_output = vpbe_dev->current_out_index;
> - int i;
> -
> - for (i = 0; i < vpbe_dev->cfg->outputs[curr_output].num_modes; i++) {
> - var = cfg->outputs[curr_output].modes[i];
> - if (!strcmp(var.name, std_name)) {
> - vpbe_dev->current_timings = var;
> - return 0;
> - }
> - }
> -
> - return -EINVAL;
> -}
> -
> -/**
> - * vpbe_set_output - Set output
> - * @vpbe_dev: vpbe device ptr
> - * @index: index of output
> - *
> - * Set vpbe output to the output specified by the index
> - */
> -static int vpbe_set_output(struct vpbe_device *vpbe_dev, int index)
> -{
> - struct encoder_config_info *curr_enc_info =
> - vpbe_current_encoder_info(vpbe_dev);
> - struct vpbe_config *cfg = vpbe_dev->cfg;
> - struct venc_platform_data *venc_device = vpbe_dev->venc_device;
> - int enc_out_index;
> - int sd_index;
> - int ret;
> -
> - if (index >= cfg->num_outputs)
> - return -EINVAL;
> -
> - mutex_lock(&vpbe_dev->lock);
> -
> - sd_index = vpbe_dev->current_sd_index;
> - enc_out_index = cfg->outputs[index].output.index;
> - /*
> - * Currently we switch the encoder based on output selected
> - * by the application. If media controller is implemented later
> - * there is will be an API added to setup_link between venc
> - * and external encoder. So in that case below comparison always
> - * match and encoder will not be switched. But if application
> - * chose not to use media controller, then this provides current
> - * way of switching encoder at the venc output.
> - */
> - if (strcmp(curr_enc_info->module_name,
> - cfg->outputs[index].subdev_name)) {
> - /* Need to switch the encoder at the output */
> - sd_index = vpbe_find_encoder_sd_index(cfg, index);
> - if (sd_index < 0) {
> - ret = -EINVAL;
> - goto unlock;
> - }
> -
> - ret = venc_device->setup_if_config(cfg->outputs[index].if_params);
> - if (ret)
> - goto unlock;
> - }
> -
> - /* Set output at the encoder */
> - ret = v4l2_subdev_call(vpbe_dev->encoders[sd_index], video,
> - s_routing, 0, enc_out_index, 0);
> - if (ret)
> - goto unlock;
> -
> - /*
> - * It is assumed that venc or external encoder will set a default
> - * mode in the sub device. For external encoder or LCD pannel output,
> - * we also need to set up the lcd port for the required mode. So setup
> - * the lcd port for the default mode that is configured in the board
> - * arch/arm/mach-davinci/board-dm355-evm.setup file for the external
> - * encoder.
> - */
> - ret = vpbe_get_mode_info(vpbe_dev,
> - cfg->outputs[index].default_mode, index);
> - if (!ret) {
> - struct osd_state *osd_device = vpbe_dev->osd_device;
> -
> - osd_device->ops.set_left_margin(osd_device,
> - vpbe_dev->current_timings.left_margin);
> - osd_device->ops.set_top_margin(osd_device,
> - vpbe_dev->current_timings.upper_margin);
> - vpbe_dev->current_sd_index = sd_index;
> - vpbe_dev->current_out_index = index;
> - }
> -unlock:
> - mutex_unlock(&vpbe_dev->lock);
> - return ret;
> -}
> -
> -static int vpbe_set_default_output(struct vpbe_device *vpbe_dev)
> -{
> - struct vpbe_config *cfg = vpbe_dev->cfg;
> - int i;
> -
> - for (i = 0; i < cfg->num_outputs; i++) {
> - if (!strcmp(def_output,
> - cfg->outputs[i].output.name)) {
> - int ret = vpbe_set_output(vpbe_dev, i);
> -
> - if (!ret)
> - vpbe_dev->current_out_index = i;
> - return ret;
> - }
> - }
> - return 0;
> -}
> -
> -/**
> - * vpbe_get_output - Get output
> - * @vpbe_dev: vpbe device ptr
> - *
> - * return current vpbe output to the index
> - */
> -static unsigned int vpbe_get_output(struct vpbe_device *vpbe_dev)
> -{
> - return vpbe_dev->current_out_index;
> -}
> -
> -/*
> - * vpbe_s_dv_timings - Set the given preset timings in the encoder
> - *
> - * Sets the timings if supported by the current encoder. Return the status.
> - * 0 - success & -EINVAL on error
> - */
> -static int vpbe_s_dv_timings(struct vpbe_device *vpbe_dev,
> - struct v4l2_dv_timings *dv_timings)
> -{
> - struct vpbe_config *cfg = vpbe_dev->cfg;
> - int out_index = vpbe_dev->current_out_index;
> - struct vpbe_output *output = &cfg->outputs[out_index];
> - int sd_index = vpbe_dev->current_sd_index;
> - int ret, i;
> -
> -
> - if (!(cfg->outputs[out_index].output.capabilities &
> - V4L2_OUT_CAP_DV_TIMINGS))
> - return -ENODATA;
> -
> - for (i = 0; i < output->num_modes; i++) {
> - if (output->modes[i].timings_type == VPBE_ENC_DV_TIMINGS &&
> - !memcmp(&output->modes[i].dv_timings,
> - dv_timings, sizeof(*dv_timings)))
> - break;
> - }
> - if (i >= output->num_modes)
> - return -EINVAL;
> - vpbe_dev->current_timings = output->modes[i];
> - mutex_lock(&vpbe_dev->lock);
> -
> - ret = v4l2_subdev_call(vpbe_dev->encoders[sd_index], video,
> - s_dv_timings, dv_timings);
> - if (!ret && vpbe_dev->amp) {
> - /* Call amplifier subdevice */
> - ret = v4l2_subdev_call(vpbe_dev->amp, video,
> - s_dv_timings, dv_timings);
> - }
> - /* set the lcd controller output for the given mode */
> - if (!ret) {
> - struct osd_state *osd_device = vpbe_dev->osd_device;
> -
> - osd_device->ops.set_left_margin(osd_device,
> - vpbe_dev->current_timings.left_margin);
> - osd_device->ops.set_top_margin(osd_device,
> - vpbe_dev->current_timings.upper_margin);
> - }
> - mutex_unlock(&vpbe_dev->lock);
> -
> - return ret;
> -}
> -
> -/*
> - * vpbe_g_dv_timings - Get the timings in the current encoder
> - *
> - * Get the timings in the current encoder. Return the status. 0 - success
> - * -EINVAL on error
> - */
> -static int vpbe_g_dv_timings(struct vpbe_device *vpbe_dev,
> - struct v4l2_dv_timings *dv_timings)
> -{
> - struct vpbe_config *cfg = vpbe_dev->cfg;
> - int out_index = vpbe_dev->current_out_index;
> -
> - if (!(cfg->outputs[out_index].output.capabilities &
> - V4L2_OUT_CAP_DV_TIMINGS))
> - return -ENODATA;
> -
> - if (vpbe_dev->current_timings.timings_type &
> - VPBE_ENC_DV_TIMINGS) {
> - *dv_timings = vpbe_dev->current_timings.dv_timings;
> - return 0;
> - }
> -
> - return -EINVAL;
> -}
> -
> -/*
> - * vpbe_enum_dv_timings - Enumerate the dv timings in the current encoder
> - *
> - * Get the timings in the current encoder. Return the status. 0 - success
> - * -EINVAL on error
> - */
> -static int vpbe_enum_dv_timings(struct vpbe_device *vpbe_dev,
> - struct v4l2_enum_dv_timings *timings)
> -{
> - struct vpbe_config *cfg = vpbe_dev->cfg;
> - int out_index = vpbe_dev->current_out_index;
> - struct vpbe_output *output = &cfg->outputs[out_index];
> - int j = 0;
> - int i;
> -
> - if (!(output->output.capabilities & V4L2_OUT_CAP_DV_TIMINGS))
> - return -ENODATA;
> -
> - for (i = 0; i < output->num_modes; i++) {
> - if (output->modes[i].timings_type == VPBE_ENC_DV_TIMINGS) {
> - if (j == timings->index)
> - break;
> - j++;
> - }
> - }
> -
> - if (i == output->num_modes)
> - return -EINVAL;
> - timings->timings = output->modes[i].dv_timings;
> - return 0;
> -}
> -
> -/*
> - * vpbe_s_std - Set the given standard in the encoder
> - *
> - * Sets the standard if supported by the current encoder. Return the status.
> - * 0 - success & -EINVAL on error
> - */
> -static int vpbe_s_std(struct vpbe_device *vpbe_dev, v4l2_std_id std_id)
> -{
> - struct vpbe_config *cfg = vpbe_dev->cfg;
> - int out_index = vpbe_dev->current_out_index;
> - int sd_index = vpbe_dev->current_sd_index;
> - int ret;
> -
> - if (!(cfg->outputs[out_index].output.capabilities &
> - V4L2_OUT_CAP_STD))
> - return -ENODATA;
> -
> - ret = vpbe_get_std_info(vpbe_dev, std_id);
> - if (ret)
> - return ret;
> -
> - mutex_lock(&vpbe_dev->lock);
> -
> - ret = v4l2_subdev_call(vpbe_dev->encoders[sd_index], video,
> - s_std_output, std_id);
> - /* set the lcd controller output for the given mode */
> - if (!ret) {
> - struct osd_state *osd_device = vpbe_dev->osd_device;
> -
> - osd_device->ops.set_left_margin(osd_device,
> - vpbe_dev->current_timings.left_margin);
> - osd_device->ops.set_top_margin(osd_device,
> - vpbe_dev->current_timings.upper_margin);
> - }
> - mutex_unlock(&vpbe_dev->lock);
> -
> - return ret;
> -}
> -
> -/*
> - * vpbe_g_std - Get the standard in the current encoder
> - *
> - * Get the standard in the current encoder. Return the status. 0 - success
> - * -EINVAL on error
> - */
> -static int vpbe_g_std(struct vpbe_device *vpbe_dev, v4l2_std_id *std_id)
> -{
> - struct vpbe_enc_mode_info *cur_timings = &vpbe_dev->current_timings;
> - struct vpbe_config *cfg = vpbe_dev->cfg;
> - int out_index = vpbe_dev->current_out_index;
> -
> - if (!(cfg->outputs[out_index].output.capabilities & V4L2_OUT_CAP_STD))
> - return -ENODATA;
> -
> - if (cur_timings->timings_type & VPBE_ENC_STD) {
> - *std_id = cur_timings->std_id;
> - return 0;
> - }
> -
> - return -EINVAL;
> -}
> -
> -/*
> - * vpbe_set_mode - Set mode in the current encoder using mode info
> - *
> - * Use the mode string to decide what timings to set in the encoder
> - * This is typically useful when fbset command is used to change the current
> - * timings by specifying a string to indicate the timings.
> - */
> -static int vpbe_set_mode(struct vpbe_device *vpbe_dev,
> - struct vpbe_enc_mode_info *mode_info)
> -{
> - struct vpbe_enc_mode_info *preset_mode = NULL;
> - struct vpbe_config *cfg = vpbe_dev->cfg;
> - struct v4l2_dv_timings dv_timings;
> - struct osd_state *osd_device;
> - int out_index = vpbe_dev->current_out_index;
> - int i;
> -
> - if (!mode_info || !mode_info->name)
> - return -EINVAL;
> -
> - for (i = 0; i < cfg->outputs[out_index].num_modes; i++) {
> - if (!strcmp(mode_info->name,
> - cfg->outputs[out_index].modes[i].name)) {
> - preset_mode = &cfg->outputs[out_index].modes[i];
> - /*
> - * it may be one of the 3 timings type. Check and
> - * invoke right API
> - */
> - if (preset_mode->timings_type & VPBE_ENC_STD)
> - return vpbe_s_std(vpbe_dev,
> - preset_mode->std_id);
> - if (preset_mode->timings_type &
> - VPBE_ENC_DV_TIMINGS) {
> - dv_timings =
> - preset_mode->dv_timings;
> - return vpbe_s_dv_timings(vpbe_dev, &dv_timings);
> - }
> - }
> - }
> -
> - /* Only custom timing should reach here */
> - if (!preset_mode)
> - return -EINVAL;
> -
> - mutex_lock(&vpbe_dev->lock);
> -
> - osd_device = vpbe_dev->osd_device;
> - vpbe_dev->current_timings = *preset_mode;
> - osd_device->ops.set_left_margin(osd_device,
> - vpbe_dev->current_timings.left_margin);
> - osd_device->ops.set_top_margin(osd_device,
> - vpbe_dev->current_timings.upper_margin);
> -
> - mutex_unlock(&vpbe_dev->lock);
> - return 0;
> -}
> -
> -static int vpbe_set_default_mode(struct vpbe_device *vpbe_dev)
> -{
> - int ret;
> -
> - ret = vpbe_get_std_info_by_name(vpbe_dev, def_mode);
> - if (ret)
> - return ret;
> -
> - /* set the default mode in the encoder */
> - return vpbe_set_mode(vpbe_dev, &vpbe_dev->current_timings);
> -}
> -
> -static int platform_device_get(struct device *dev, void *data)
> -{
> - struct platform_device *pdev = to_platform_device(dev);
> - struct vpbe_device *vpbe_dev = data;
> -
> - if (strstr(pdev->name, "vpbe-osd"))
> - vpbe_dev->osd_device = platform_get_drvdata(pdev);
> - if (strstr(pdev->name, "vpbe-venc"))
> - vpbe_dev->venc_device = dev_get_platdata(&pdev->dev);
> -
> - return 0;
> -}
> -
> -/**
> - * vpbe_initialize() - Initialize the vpbe display controller
> - * @dev: Master and slave device ptr
> - * @vpbe_dev: vpbe device ptr
> - *
> - * Master frame buffer device drivers calls this to initialize vpbe
> - * display controller. This will then registers v4l2 device and the sub
> - * devices and sets a current encoder sub device for display. v4l2 display
> - * device driver is the master and frame buffer display device driver is
> - * the slave. Frame buffer display driver checks the initialized during
> - * probe and exit if not initialized. Returns status.
> - */
> -static int vpbe_initialize(struct device *dev, struct vpbe_device *vpbe_dev)
> -{
> - struct encoder_config_info *enc_info;
> - struct amp_config_info *amp_info;
> - struct v4l2_subdev **enc_subdev;
> - struct osd_state *osd_device;
> - struct i2c_adapter *i2c_adap;
> - int num_encoders;
> - int ret = 0;
> - int err;
> - int i;
> -
> - /*
> - * v4l2 abd FBDev frame buffer devices will get the vpbe_dev pointer
> - * from the platform device by iteration of platform drivers and
> - * matching with device name
> - */
> - if (!vpbe_dev || !dev) {
> - printk(KERN_ERR "Null device pointers.\n");
> - return -ENODEV;
> - }
> -
> - if (vpbe_dev->initialized)
> - return 0;
> -
> - mutex_lock(&vpbe_dev->lock);
> -
> - if (strcmp(vpbe_dev->cfg->module_name, "dm644x-vpbe-display") != 0) {
> - /* We have dac clock available for platform */
> - vpbe_dev->dac_clk = clk_get(vpbe_dev->pdev, "vpss_dac");
> - if (IS_ERR(vpbe_dev->dac_clk)) {
> - ret = PTR_ERR(vpbe_dev->dac_clk);
> - goto fail_mutex_unlock;
> - }
> - if (clk_prepare_enable(vpbe_dev->dac_clk)) {
> - ret = -ENODEV;
> - clk_put(vpbe_dev->dac_clk);
> - goto fail_mutex_unlock;
> - }
> - }
> -
> - /* first enable vpss clocks */
> - vpss_enable_clock(VPSS_VPBE_CLOCK, 1);
> -
> - /* First register a v4l2 device */
> - ret = v4l2_device_register(dev, &vpbe_dev->v4l2_dev);
> - if (ret) {
> - v4l2_err(dev->driver,
> - "Unable to register v4l2 device.\n");
> - goto fail_clk_put;
> - }
> - v4l2_info(&vpbe_dev->v4l2_dev, "vpbe v4l2 device registered\n");
> -
> - err = bus_for_each_dev(&platform_bus_type, NULL, vpbe_dev,
> - platform_device_get);
> - if (err < 0) {
> - ret = err;
> - goto fail_dev_unregister;
> - }
> -
> - vpbe_dev->venc = venc_sub_dev_init(&vpbe_dev->v4l2_dev,
> - vpbe_dev->cfg->venc.module_name);
> - /* register venc sub device */
> - if (!vpbe_dev->venc) {
> - v4l2_err(&vpbe_dev->v4l2_dev,
> - "vpbe unable to init venc sub device\n");
> - ret = -ENODEV;
> - goto fail_dev_unregister;
> - }
> - /* initialize osd device */
> - osd_device = vpbe_dev->osd_device;
> - if (osd_device->ops.initialize) {
> - err = osd_device->ops.initialize(osd_device);
> - if (err) {
> - v4l2_err(&vpbe_dev->v4l2_dev,
> - "unable to initialize the OSD device");
> - ret = -ENOMEM;
> - goto fail_dev_unregister;
> - }
> - }
> -
> - /*
> - * Register any external encoders that are configured. At index 0 we
> - * store venc sd index.
> - */
> - num_encoders = vpbe_dev->cfg->num_ext_encoders + 1;
> - vpbe_dev->encoders = kmalloc_array(num_encoders,
> - sizeof(*vpbe_dev->encoders),
> - GFP_KERNEL);
> - if (!vpbe_dev->encoders) {
> - ret = -ENOMEM;
> - goto fail_dev_unregister;
> - }
> -
> - i2c_adap = i2c_get_adapter(vpbe_dev->cfg->i2c_adapter_id);
> - for (i = 0; i < (vpbe_dev->cfg->num_ext_encoders + 1); i++) {
> - if (i == 0) {
> - /* venc is at index 0 */
> - enc_subdev = &vpbe_dev->encoders[i];
> - *enc_subdev = vpbe_dev->venc;
> - continue;
> - }
> - enc_info = &vpbe_dev->cfg->ext_encoders[i];
> - if (enc_info->is_i2c) {
> - enc_subdev = &vpbe_dev->encoders[i];
> - *enc_subdev = v4l2_i2c_new_subdev_board(
> - &vpbe_dev->v4l2_dev, i2c_adap,
> - &enc_info->board_info, NULL);
> - if (*enc_subdev)
> - v4l2_info(&vpbe_dev->v4l2_dev,
> - "v4l2 sub device %s registered\n",
> - enc_info->module_name);
> - else {
> - v4l2_err(&vpbe_dev->v4l2_dev, "encoder %s failed to register",
> - enc_info->module_name);
> - ret = -ENODEV;
> - goto fail_kfree_encoders;
> - }
> - } else
> - v4l2_warn(&vpbe_dev->v4l2_dev, "non-i2c encoders currently not supported");
> - }
> - /* Add amplifier subdevice for dm365 */
> - if ((strcmp(vpbe_dev->cfg->module_name, "dm365-vpbe-display") == 0) &&
> - vpbe_dev->cfg->amp) {
> - amp_info = vpbe_dev->cfg->amp;
> - if (amp_info->is_i2c) {
> - vpbe_dev->amp = v4l2_i2c_new_subdev_board(
> - &vpbe_dev->v4l2_dev, i2c_adap,
> - &_info->board_info, NULL);
> - if (!vpbe_dev->amp) {
> - v4l2_err(&vpbe_dev->v4l2_dev,
> - "amplifier %s failed to register",
> - amp_info->module_name);
> - ret = -ENODEV;
> - goto fail_kfree_encoders;
> - }
> - v4l2_info(&vpbe_dev->v4l2_dev,
> - "v4l2 sub device %s registered\n",
> - amp_info->module_name);
> - } else {
> - vpbe_dev->amp = NULL;
> - v4l2_warn(&vpbe_dev->v4l2_dev, "non-i2c amplifiers currently not supported");
> - }
> - } else {
> - vpbe_dev->amp = NULL;
> - }
> -
> - /* set the current encoder and output to that of venc by default */
> - vpbe_dev->current_sd_index = 0;
> - vpbe_dev->current_out_index = 0;
> -
> - mutex_unlock(&vpbe_dev->lock);
> -
> - printk(KERN_NOTICE "Setting default output to %s\n", def_output);
> - ret = vpbe_set_default_output(vpbe_dev);
> - if (ret) {
> - v4l2_err(&vpbe_dev->v4l2_dev, "Failed to set default output %s",
> - def_output);
> - goto fail_kfree_amp;
> - }
> -
> - printk(KERN_NOTICE "Setting default mode to %s\n", def_mode);
> - ret = vpbe_set_default_mode(vpbe_dev);
> - if (ret) {
> - v4l2_err(&vpbe_dev->v4l2_dev, "Failed to set default mode %s",
> - def_mode);
> - goto fail_kfree_amp;
> - }
> - vpbe_dev->initialized = 1;
> - /* TBD handling of bootargs for default output and mode */
> - return 0;
> -
> -fail_kfree_amp:
> - mutex_lock(&vpbe_dev->lock);
> - kfree(vpbe_dev->amp);
> -fail_kfree_encoders:
> - kfree(vpbe_dev->encoders);
> -fail_dev_unregister:
> - v4l2_device_unregister(&vpbe_dev->v4l2_dev);
> -fail_clk_put:
> - if (strcmp(vpbe_dev->cfg->module_name, "dm644x-vpbe-display") != 0) {
> - clk_disable_unprepare(vpbe_dev->dac_clk);
> - clk_put(vpbe_dev->dac_clk);
> - }
> -fail_mutex_unlock:
> - mutex_unlock(&vpbe_dev->lock);
> - return ret;
> -}
> -
> -/**
> - * vpbe_deinitialize() - de-initialize the vpbe display controller
> - * @dev: Master and slave device ptr
> - * @vpbe_dev: vpbe device ptr
> - *
> - * vpbe_master and slave frame buffer devices calls this to de-initialize
> - * the display controller. It is called when master and slave device
> - * driver modules are removed and no longer requires the display controller.
> - */
> -static void vpbe_deinitialize(struct device *dev, struct vpbe_device *vpbe_dev)
> -{
> - v4l2_device_unregister(&vpbe_dev->v4l2_dev);
> - if (strcmp(vpbe_dev->cfg->module_name, "dm644x-vpbe-display") != 0) {
> - clk_disable_unprepare(vpbe_dev->dac_clk);
> - clk_put(vpbe_dev->dac_clk);
> - }
> -
> - kfree(vpbe_dev->amp);
> - kfree(vpbe_dev->encoders);
> - vpbe_dev->initialized = 0;
> - /* disable vpss clocks */
> - vpss_enable_clock(VPSS_VPBE_CLOCK, 0);
> -}
> -
> -static const struct vpbe_device_ops vpbe_dev_ops = {
> - .enum_outputs = vpbe_enum_outputs,
> - .set_output = vpbe_set_output,
> - .get_output = vpbe_get_output,
> - .s_dv_timings = vpbe_s_dv_timings,
> - .g_dv_timings = vpbe_g_dv_timings,
> - .enum_dv_timings = vpbe_enum_dv_timings,
> - .s_std = vpbe_s_std,
> - .g_std = vpbe_g_std,
> - .initialize = vpbe_initialize,
> - .deinitialize = vpbe_deinitialize,
> - .get_mode_info = vpbe_get_current_mode_info,
> - .set_mode = vpbe_set_mode,
> -};
> -
> -static int vpbe_probe(struct platform_device *pdev)
> -{
> - struct vpbe_device *vpbe_dev;
> - struct vpbe_config *cfg;
> -
> - if (!pdev->dev.platform_data) {
> - v4l2_err(pdev->dev.driver, "No platform data\n");
> - return -ENODEV;
> - }
> - cfg = pdev->dev.platform_data;
> -
> - if (!cfg->module_name[0] ||
> - !cfg->osd.module_name[0] ||
> - !cfg->venc.module_name[0]) {
> - v4l2_err(pdev->dev.driver, "vpbe display module names not defined\n");
> - return -EINVAL;
> - }
> -
> - vpbe_dev = kzalloc(sizeof(*vpbe_dev), GFP_KERNEL);
> - if (!vpbe_dev)
> - return -ENOMEM;
> -
> - vpbe_dev->cfg = cfg;
> - vpbe_dev->ops = vpbe_dev_ops;
> - vpbe_dev->pdev = &pdev->dev;
> -
> - if (cfg->outputs->num_modes > 0)
> - vpbe_dev->current_timings = vpbe_dev->cfg->outputs[0].modes[0];
> - else {
> - kfree(vpbe_dev);
> - return -ENODEV;
> - }
> -
> - /* set the driver data in platform device */
> - platform_set_drvdata(pdev, vpbe_dev);
> - mutex_init(&vpbe_dev->lock);
> -
> - return 0;
> -}
> -
> -static int vpbe_remove(struct platform_device *device)
> -{
> - struct vpbe_device *vpbe_dev = platform_get_drvdata(device);
> -
> - kfree(vpbe_dev);
> -
> - return 0;
> -}
> -
> -static struct platform_driver vpbe_driver = {
> - .driver = {
> - .name = "vpbe_controller",
> - },
> - .probe = vpbe_probe,
> - .remove = vpbe_remove,
> -};
> -
> -module_platform_driver(vpbe_driver);
> diff --git a/drivers/media/platform/ti/davinci/vpbe_display.c b/drivers/media/platform/ti/davinci/vpbe_display.c
> deleted file mode 100644
> index 9ea70817538e..000000000000
> --- a/drivers/media/platform/ti/davinci/vpbe_display.c
> +++ /dev/null
> @@ -1,1510 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
> - */
> -#include <linux/kernel.h>
> -#include <linux/init.h>
> -#include <linux/module.h>
> -#include <linux/errno.h>
> -#include <linux/interrupt.h>
> -#include <linux/string.h>
> -#include <linux/wait.h>
> -#include <linux/time.h>
> -#include <linux/platform_device.h>
> -#include <linux/irq.h>
> -#include <linux/mm.h>
> -#include <linux/mutex.h>
> -#include <linux/videodev2.h>
> -#include <linux/slab.h>
> -
> -
> -#include <media/v4l2-dev.h>
> -#include <media/v4l2-common.h>
> -#include <media/v4l2-ioctl.h>
> -#include <media/v4l2-device.h>
> -#include <media/davinci/vpbe_display.h>
> -#include <media/davinci/vpbe_types.h>
> -#include <media/davinci/vpbe.h>
> -#include <media/davinci/vpbe_venc.h>
> -#include <media/davinci/vpbe_osd.h>
> -#include "vpbe_venc_regs.h"
> -
> -#define VPBE_DISPLAY_DRIVER "vpbe-v4l2"
> -
> -static int debug;
> -
> -#define VPBE_DEFAULT_NUM_BUFS 3
> -
> -module_param(debug, int, 0644);
> -
> -static int vpbe_set_osd_display_params(struct vpbe_display *disp_dev,
> - struct vpbe_layer *layer);
> -
> -static int venc_is_second_field(struct vpbe_display *disp_dev)
> -{
> - struct vpbe_device *vpbe_dev = disp_dev->vpbe_dev;
> - int ret, val;
> -
> - ret = v4l2_subdev_call(vpbe_dev->venc,
> - core,
> - command,
> - VENC_GET_FLD,
> - &val);
> - if (ret < 0) {
> - v4l2_err(&vpbe_dev->v4l2_dev,
> - "Error in getting Field ID 0\n");
> - return 1;
> - }
> - return val;
> -}
> -
> -static void vpbe_isr_even_field(struct vpbe_display *disp_obj,
> - struct vpbe_layer *layer)
> -{
> - if (layer->cur_frm == layer->next_frm)
> - return;
> -
> - layer->cur_frm->vb.vb2_buf.timestamp = ktime_get_ns();
> - vb2_buffer_done(&layer->cur_frm->vb.vb2_buf, VB2_BUF_STATE_DONE);
> - /* Make cur_frm pointing to next_frm */
> - layer->cur_frm = layer->next_frm;
> -}
> -
> -static void vpbe_isr_odd_field(struct vpbe_display *disp_obj,
> - struct vpbe_layer *layer)
> -{
> - struct osd_state *osd_device = disp_obj->osd_device;
> - unsigned long addr;
> -
> - spin_lock(&disp_obj->dma_queue_lock);
> - if (list_empty(&layer->dma_queue) ||
> - (layer->cur_frm != layer->next_frm)) {
> - spin_unlock(&disp_obj->dma_queue_lock);
> - return;
> - }
> - /*
> - * one field is displayed configure
> - * the next frame if it is available
> - * otherwise hold on current frame
> - * Get next from the buffer queue
> - */
> - layer->next_frm = list_entry(layer->dma_queue.next,
> - struct vpbe_disp_buffer, list);
> - /* Remove that from the buffer queue */
> - list_del(&layer->next_frm->list);
> - spin_unlock(&disp_obj->dma_queue_lock);
> - /* Mark state of the frame to active */
> - layer->next_frm->vb.vb2_buf.state = VB2_BUF_STATE_ACTIVE;
> - addr = vb2_dma_contig_plane_dma_addr(&layer->next_frm->vb.vb2_buf, 0);
> - osd_device->ops.start_layer(osd_device,
> - layer->layer_info.id,
> - addr,
> - disp_obj->cbcr_ofst);
> -}
> -
> -/* interrupt service routine */
> -static irqreturn_t venc_isr(int irq, void *arg)
> -{
> - struct vpbe_display *disp_dev = (struct vpbe_display *)arg;
> - struct vpbe_layer *layer;
> - static unsigned last_event;
> - unsigned event = 0;
> - int fid;
> - int i;
> -
> - if (!arg || !disp_dev->dev[0])
> - return IRQ_HANDLED;
> -
> - if (venc_is_second_field(disp_dev))
> - event |= VENC_SECOND_FIELD;
> - else
> - event |= VENC_FIRST_FIELD;
> -
> - if (event == (last_event & ~VENC_END_OF_FRAME)) {
> - /*
> - * If the display is non-interlaced, then we need to flag the
> - * end-of-frame event at every interrupt regardless of the
> - * value of the FIDST bit. We can conclude that the display is
> - * non-interlaced if the value of the FIDST bit is unchanged
> - * from the previous interrupt.
> - */
> - event |= VENC_END_OF_FRAME;
> - } else if (event == VENC_SECOND_FIELD) {
> - /* end-of-frame for interlaced display */
> - event |= VENC_END_OF_FRAME;
> - }
> - last_event = event;
> -
> - for (i = 0; i < VPBE_DISPLAY_MAX_DEVICES; i++) {
> - layer = disp_dev->dev[i];
> -
> - if (!vb2_start_streaming_called(&layer->buffer_queue))
> - continue;
> -
> - if (layer->layer_first_int) {
> - layer->layer_first_int = 0;
> - continue;
> - }
> - /* Check the field format */
> - if ((V4L2_FIELD_NONE == layer->pix_fmt.field) &&
> - (event & VENC_END_OF_FRAME)) {
> - /* Progressive mode */
> -
> - vpbe_isr_even_field(disp_dev, layer);
> - vpbe_isr_odd_field(disp_dev, layer);
> - } else {
> - /* Interlaced mode */
> -
> - layer->field_id ^= 1;
> - if (event & VENC_FIRST_FIELD)
> - fid = 0;
> - else
> - fid = 1;
> -
> - /*
> - * If field id does not match with store
> - * field id
> - */
> - if (fid != layer->field_id) {
> - /* Make them in sync */
> - layer->field_id = fid;
> - continue;
> - }
> - /*
> - * device field id and local field id are
> - * in sync. If this is even field
> - */
> - if (0 == fid)
> - vpbe_isr_even_field(disp_dev, layer);
> - else /* odd field */
> - vpbe_isr_odd_field(disp_dev, layer);
> - }
> - }
> -
> - return IRQ_HANDLED;
> -}
> -
> -/*
> - * vpbe_buffer_prepare()
> - * This is the callback function called from vb2_qbuf() function
> - * the buffer is prepared and user space virtual address is converted into
> - * physical address
> - */
> -static int vpbe_buffer_prepare(struct vb2_buffer *vb)
> -{
> - struct vb2_queue *q = vb->vb2_queue;
> - struct vpbe_layer *layer = vb2_get_drv_priv(q);
> - struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev;
> - unsigned long addr;
> -
> - v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev,
> - "vpbe_buffer_prepare\n");
> -
> - vb2_set_plane_payload(vb, 0, layer->pix_fmt.sizeimage);
> - if (vb2_get_plane_payload(vb, 0) > vb2_plane_size(vb, 0))
> - return -EINVAL;
> -
> - addr = vb2_dma_contig_plane_dma_addr(vb, 0);
> - if (!IS_ALIGNED(addr, 8)) {
> - v4l2_err(&vpbe_dev->v4l2_dev,
> - "buffer_prepare:offset is not aligned to 32 bytes\n");
> - return -EINVAL;
> - }
> - return 0;
> -}
> -
> -/*
> - * vpbe_buffer_setup()
> - * This function allocates memory for the buffers
> - */
> -static int
> -vpbe_buffer_queue_setup(struct vb2_queue *vq,
> - unsigned int *nbuffers, unsigned int *nplanes,
> - unsigned int sizes[], struct device *alloc_devs[])
> -
> -{
> - /* Get the file handle object and layer object */
> - struct vpbe_layer *layer = vb2_get_drv_priv(vq);
> - struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev;
> -
> - v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "vpbe_buffer_setup\n");
> -
> - /* Store number of buffers allocated in numbuffer member */
> - if (vq->num_buffers + *nbuffers < VPBE_DEFAULT_NUM_BUFS)
> - *nbuffers = VPBE_DEFAULT_NUM_BUFS - vq->num_buffers;
> -
> - if (*nplanes)
> - return sizes[0] < layer->pix_fmt.sizeimage ? -EINVAL : 0;
> -
> - *nplanes = 1;
> - sizes[0] = layer->pix_fmt.sizeimage;
> -
> - return 0;
> -}
> -
> -/*
> - * vpbe_buffer_queue()
> - * This function adds the buffer to DMA queue
> - */
> -static void vpbe_buffer_queue(struct vb2_buffer *vb)
> -{
> - struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
> - /* Get the file handle object and layer object */
> - struct vpbe_disp_buffer *buf = container_of(vbuf,
> - struct vpbe_disp_buffer, vb);
> - struct vpbe_layer *layer = vb2_get_drv_priv(vb->vb2_queue);
> - struct vpbe_display *disp = layer->disp_dev;
> - struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev;
> - unsigned long flags;
> -
> - v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev,
> - "vpbe_buffer_queue\n");
> -
> - /* add the buffer to the DMA queue */
> - spin_lock_irqsave(&disp->dma_queue_lock, flags);
> - list_add_tail(&buf->list, &layer->dma_queue);
> - spin_unlock_irqrestore(&disp->dma_queue_lock, flags);
> -}
> -
> -static int vpbe_start_streaming(struct vb2_queue *vq, unsigned int count)
> -{
> - struct vpbe_layer *layer = vb2_get_drv_priv(vq);
> - struct osd_state *osd_device = layer->disp_dev->osd_device;
> - int ret;
> -
> - osd_device->ops.disable_layer(osd_device, layer->layer_info.id);
> -
> - /* Get the next frame from the buffer queue */
> - layer->next_frm = layer->cur_frm = list_entry(layer->dma_queue.next,
> - struct vpbe_disp_buffer, list);
> - /* Remove buffer from the buffer queue */
> - list_del(&layer->cur_frm->list);
> - /* Mark state of the current frame to active */
> - layer->cur_frm->vb.vb2_buf.state = VB2_BUF_STATE_ACTIVE;
> - /* Initialize field_id and started member */
> - layer->field_id = 0;
> -
> - /* Set parameters in OSD and VENC */
> - ret = vpbe_set_osd_display_params(layer->disp_dev, layer);
> - if (ret < 0) {
> - struct vpbe_disp_buffer *buf, *tmp;
> -
> - vb2_buffer_done(&layer->cur_frm->vb.vb2_buf,
> - VB2_BUF_STATE_QUEUED);
> - list_for_each_entry_safe(buf, tmp, &layer->dma_queue, list) {
> - list_del(&buf->list);
> - vb2_buffer_done(&buf->vb.vb2_buf,
> - VB2_BUF_STATE_QUEUED);
> - }
> -
> - return ret;
> - }
> -
> - /*
> - * if request format is yuv420 semiplanar, need to
> - * enable both video windows
> - */
> - layer->layer_first_int = 1;
> -
> - return ret;
> -}
> -
> -static void vpbe_stop_streaming(struct vb2_queue *vq)
> -{
> - struct vpbe_layer *layer = vb2_get_drv_priv(vq);
> - struct osd_state *osd_device = layer->disp_dev->osd_device;
> - struct vpbe_display *disp = layer->disp_dev;
> - unsigned long flags;
> -
> - if (!vb2_is_streaming(vq))
> - return;
> -
> - osd_device->ops.disable_layer(osd_device, layer->layer_info.id);
> -
> - /* release all active buffers */
> - spin_lock_irqsave(&disp->dma_queue_lock, flags);
> - if (layer->cur_frm == layer->next_frm) {
> - vb2_buffer_done(&layer->cur_frm->vb.vb2_buf,
> - VB2_BUF_STATE_ERROR);
> - } else {
> - if (layer->cur_frm)
> - vb2_buffer_done(&layer->cur_frm->vb.vb2_buf,
> - VB2_BUF_STATE_ERROR);
> - if (layer->next_frm)
> - vb2_buffer_done(&layer->next_frm->vb.vb2_buf,
> - VB2_BUF_STATE_ERROR);
> - }
> -
> - while (!list_empty(&layer->dma_queue)) {
> - layer->next_frm = list_entry(layer->dma_queue.next,
> - struct vpbe_disp_buffer, list);
> - list_del(&layer->next_frm->list);
> - vb2_buffer_done(&layer->next_frm->vb.vb2_buf,
> - VB2_BUF_STATE_ERROR);
> - }
> - spin_unlock_irqrestore(&disp->dma_queue_lock, flags);
> -}
> -
> -static const struct vb2_ops video_qops = {
> - .queue_setup = vpbe_buffer_queue_setup,
> - .wait_prepare = vb2_ops_wait_prepare,
> - .wait_finish = vb2_ops_wait_finish,
> - .buf_prepare = vpbe_buffer_prepare,
> - .start_streaming = vpbe_start_streaming,
> - .stop_streaming = vpbe_stop_streaming,
> - .buf_queue = vpbe_buffer_queue,
> -};
> -
> -static
> -struct vpbe_layer*
> -_vpbe_display_get_other_win_layer(struct vpbe_display *disp_dev,
> - struct vpbe_layer *layer)
> -{
> - enum vpbe_display_device_id thiswin, otherwin;
> - thiswin = layer->device_id;
> -
> - otherwin = (thiswin == VPBE_DISPLAY_DEVICE_0) ?
> - VPBE_DISPLAY_DEVICE_1 : VPBE_DISPLAY_DEVICE_0;
> - return disp_dev->dev[otherwin];
> -}
> -
> -static int vpbe_set_osd_display_params(struct vpbe_display *disp_dev,
> - struct vpbe_layer *layer)
> -{
> - struct osd_layer_config *cfg = &layer->layer_info.config;
> - struct osd_state *osd_device = disp_dev->osd_device;
> - struct vpbe_device *vpbe_dev = disp_dev->vpbe_dev;
> - unsigned long addr;
> - int ret;
> -
> - addr = vb2_dma_contig_plane_dma_addr(&layer->cur_frm->vb.vb2_buf, 0);
> - /* Set address in the display registers */
> - osd_device->ops.start_layer(osd_device,
> - layer->layer_info.id,
> - addr,
> - disp_dev->cbcr_ofst);
> -
> - ret = osd_device->ops.enable_layer(osd_device,
> - layer->layer_info.id, 0);
> - if (ret < 0) {
> - v4l2_err(&vpbe_dev->v4l2_dev,
> - "Error in enabling osd window layer 0\n");
> - return -1;
> - }
> -
> - /* Enable the window */
> - layer->layer_info.enable = 1;
> - if (cfg->pixfmt == PIXFMT_NV12) {
> - struct vpbe_layer *otherlayer =
> - _vpbe_display_get_other_win_layer(disp_dev, layer);
> -
> - ret = osd_device->ops.enable_layer(osd_device,
> - otherlayer->layer_info.id, 1);
> - if (ret < 0) {
> - v4l2_err(&vpbe_dev->v4l2_dev,
> - "Error in enabling osd window layer 1\n");
> - return -1;
> - }
> - otherlayer->layer_info.enable = 1;
> - }
> - return 0;
> -}
> -
> -static void
> -vpbe_disp_calculate_scale_factor(struct vpbe_display *disp_dev,
> - struct vpbe_layer *layer,
> - int expected_xsize, int expected_ysize)
> -{
> - struct display_layer_info *layer_info = &layer->layer_info;
> - struct v4l2_pix_format *pixfmt = &layer->pix_fmt;
> - struct osd_layer_config *cfg = &layer->layer_info.config;
> - struct vpbe_device *vpbe_dev = disp_dev->vpbe_dev;
> - int calculated_xsize;
> - int h_exp = 0;
> - int v_exp = 0;
> - int h_scale;
> - int v_scale;
> -
> - v4l2_std_id standard_id = vpbe_dev->current_timings.std_id;
> -
> - /*
> - * Application initially set the image format. Current display
> - * size is obtained from the vpbe display controller. expected_xsize
> - * and expected_ysize are set through S_SELECTION ioctl. Based on this,
> - * driver will calculate the scale factors for vertical and
> - * horizontal direction so that the image is displayed scaled
> - * and expanded. Application uses expansion to display the image
> - * in a square pixel. Otherwise it is displayed using displays
> - * pixel aspect ratio.It is expected that application chooses
> - * the crop coordinates for cropped or scaled display. if crop
> - * size is less than the image size, it is displayed cropped or
> - * it is displayed scaled and/or expanded.
> - *
> - * to begin with, set the crop window same as expected. Later we
> - * will override with scaled window size
> - */
> -
> - cfg->xsize = pixfmt->width;
> - cfg->ysize = pixfmt->height;
> - layer_info->h_zoom = ZOOM_X1; /* no horizontal zoom */
> - layer_info->v_zoom = ZOOM_X1; /* no horizontal zoom */
> - layer_info->h_exp = H_EXP_OFF; /* no horizontal zoom */
> - layer_info->v_exp = V_EXP_OFF; /* no horizontal zoom */
> -
> - if (pixfmt->width < expected_xsize) {
> - h_scale = vpbe_dev->current_timings.xres / pixfmt->width;
> - if (h_scale < 2)
> - h_scale = 1;
> - else if (h_scale >= 4)
> - h_scale = 4;
> - else
> - h_scale = 2;
> - cfg->xsize *= h_scale;
> - if (cfg->xsize < expected_xsize) {
> - if ((standard_id & V4L2_STD_525_60) ||
> - (standard_id & V4L2_STD_625_50)) {
> - calculated_xsize = (cfg->xsize *
> - VPBE_DISPLAY_H_EXP_RATIO_N) /
> - VPBE_DISPLAY_H_EXP_RATIO_D;
> - if (calculated_xsize <= expected_xsize) {
> - h_exp = 1;
> - cfg->xsize = calculated_xsize;
> - }
> - }
> - }
> - if (h_scale == 2)
> - layer_info->h_zoom = ZOOM_X2;
> - else if (h_scale == 4)
> - layer_info->h_zoom = ZOOM_X4;
> - if (h_exp)
> - layer_info->h_exp = H_EXP_9_OVER_8;
> - } else {
> - /* no scaling, only cropping. Set display area to crop area */
> - cfg->xsize = expected_xsize;
> - }
> -
> - if (pixfmt->height < expected_ysize) {
> - v_scale = expected_ysize / pixfmt->height;
> - if (v_scale < 2)
> - v_scale = 1;
> - else if (v_scale >= 4)
> - v_scale = 4;
> - else
> - v_scale = 2;
> - cfg->ysize *= v_scale;
> - if (cfg->ysize < expected_ysize) {
> - if ((standard_id & V4L2_STD_625_50)) {
> - calculated_xsize = (cfg->ysize *
> - VPBE_DISPLAY_V_EXP_RATIO_N) /
> - VPBE_DISPLAY_V_EXP_RATIO_D;
> - if (calculated_xsize <= expected_ysize) {
> - v_exp = 1;
> - cfg->ysize = calculated_xsize;
> - }
> - }
> - }
> - if (v_scale == 2)
> - layer_info->v_zoom = ZOOM_X2;
> - else if (v_scale == 4)
> - layer_info->v_zoom = ZOOM_X4;
> - if (v_exp)
> - layer_info->v_exp = V_EXP_6_OVER_5;
> - } else {
> - /* no scaling, only cropping. Set display area to crop area */
> - cfg->ysize = expected_ysize;
> - }
> - v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev,
> - "crop display xsize = %d, ysize = %d\n",
> - cfg->xsize, cfg->ysize);
> -}
> -
> -static void vpbe_disp_adj_position(struct vpbe_display *disp_dev,
> - struct vpbe_layer *layer,
> - int top, int left)
> -{
> - struct osd_layer_config *cfg = &layer->layer_info.config;
> - struct vpbe_device *vpbe_dev = disp_dev->vpbe_dev;
> -
> - cfg->xpos = min((unsigned int)left,
> - vpbe_dev->current_timings.xres - cfg->xsize);
> - cfg->ypos = min((unsigned int)top,
> - vpbe_dev->current_timings.yres - cfg->ysize);
> -
> - v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev,
> - "new xpos = %d, ypos = %d\n",
> - cfg->xpos, cfg->ypos);
> -}
> -
> -static void vpbe_disp_check_window_params(struct vpbe_display *disp_dev,
> - struct v4l2_rect *c)
> -{
> - struct vpbe_device *vpbe_dev = disp_dev->vpbe_dev;
> -
> - if ((c->width == 0) ||
> - ((c->width + c->left) > vpbe_dev->current_timings.xres))
> - c->width = vpbe_dev->current_timings.xres - c->left;
> -
> - if ((c->height == 0) || ((c->height + c->top) >
> - vpbe_dev->current_timings.yres))
> - c->height = vpbe_dev->current_timings.yres - c->top;
> -
> - /* window height must be even for interlaced display */
> - if (vpbe_dev->current_timings.interlaced)
> - c->height &= (~0x01);
> -
> -}
> -
> -/*
> - * vpbe_try_format()
> - * If user application provides width and height, and have bytesperline set
> - * to zero, driver calculates bytesperline and sizeimage based on hardware
> - * limits.
> - */
> -static int vpbe_try_format(struct vpbe_display *disp_dev,
> - struct v4l2_pix_format *pixfmt, int check)
> -{
> - struct vpbe_device *vpbe_dev = disp_dev->vpbe_dev;
> - int min_height = 1;
> - int min_width = 32;
> - int max_height;
> - int max_width;
> - int bpp;
> -
> - if ((pixfmt->pixelformat != V4L2_PIX_FMT_UYVY) &&
> - (pixfmt->pixelformat != V4L2_PIX_FMT_NV12))
> - /* choose default as V4L2_PIX_FMT_UYVY */
> - pixfmt->pixelformat = V4L2_PIX_FMT_UYVY;
> -
> - /* Check the field format */
> - if ((pixfmt->field != V4L2_FIELD_INTERLACED) &&
> - (pixfmt->field != V4L2_FIELD_NONE)) {
> - if (vpbe_dev->current_timings.interlaced)
> - pixfmt->field = V4L2_FIELD_INTERLACED;
> - else
> - pixfmt->field = V4L2_FIELD_NONE;
> - }
> -
> - if (pixfmt->field == V4L2_FIELD_INTERLACED)
> - min_height = 2;
> -
> - if (pixfmt->pixelformat == V4L2_PIX_FMT_NV12)
> - bpp = 1;
> - else
> - bpp = 2;
> -
> - max_width = vpbe_dev->current_timings.xres;
> - max_height = vpbe_dev->current_timings.yres;
> -
> - min_width /= bpp;
> -
> - if (!pixfmt->width || (pixfmt->width < min_width) ||
> - (pixfmt->width > max_width)) {
> - pixfmt->width = vpbe_dev->current_timings.xres;
> - }
> -
> - if (!pixfmt->height || (pixfmt->height < min_height) ||
> - (pixfmt->height > max_height)) {
> - pixfmt->height = vpbe_dev->current_timings.yres;
> - }
> -
> - if (pixfmt->bytesperline < (pixfmt->width * bpp))
> - pixfmt->bytesperline = pixfmt->width * bpp;
> -
> - /* Make the bytesperline 32 byte aligned */
> - pixfmt->bytesperline = ((pixfmt->width * bpp + 31) & ~31);
> -
> - if (pixfmt->pixelformat == V4L2_PIX_FMT_NV12)
> - pixfmt->sizeimage = pixfmt->bytesperline * pixfmt->height +
> - (pixfmt->bytesperline * pixfmt->height >> 1);
> - else
> - pixfmt->sizeimage = pixfmt->bytesperline * pixfmt->height;
> -
> - return 0;
> -}
> -
> -static int vpbe_display_querycap(struct file *file, void *priv,
> - struct v4l2_capability *cap)
> -{
> - struct vpbe_layer *layer = video_drvdata(file);
> - struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev;
> -
> - snprintf(cap->driver, sizeof(cap->driver), "%s",
> - dev_name(vpbe_dev->pdev));
> - strscpy(cap->card, vpbe_dev->cfg->module_name, sizeof(cap->card));
> -
> - return 0;
> -}
> -
> -static int vpbe_display_s_selection(struct file *file, void *priv,
> - struct v4l2_selection *sel)
> -{
> - struct vpbe_layer *layer = video_drvdata(file);
> - struct vpbe_display *disp_dev = layer->disp_dev;
> - struct vpbe_device *vpbe_dev = disp_dev->vpbe_dev;
> - struct osd_layer_config *cfg = &layer->layer_info.config;
> - struct osd_state *osd_device = disp_dev->osd_device;
> - struct v4l2_rect rect = sel->r;
> - int ret;
> -
> - v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev,
> - "VIDIOC_S_SELECTION, layer id = %d\n", layer->device_id);
> -
> - if (sel->type != V4L2_BUF_TYPE_VIDEO_OUTPUT ||
> - sel->target != V4L2_SEL_TGT_CROP)
> - return -EINVAL;
> -
> - if (rect.top < 0)
> - rect.top = 0;
> - if (rect.left < 0)
> - rect.left = 0;
> -
> - vpbe_disp_check_window_params(disp_dev, &rect);
> -
> - osd_device->ops.get_layer_config(osd_device,
> - layer->layer_info.id, cfg);
> -
> - vpbe_disp_calculate_scale_factor(disp_dev, layer,
> - rect.width,
> - rect.height);
> - vpbe_disp_adj_position(disp_dev, layer, rect.top,
> - rect.left);
> - ret = osd_device->ops.set_layer_config(osd_device,
> - layer->layer_info.id, cfg);
> - if (ret < 0) {
> - v4l2_err(&vpbe_dev->v4l2_dev,
> - "Error in set layer config:\n");
> - return -EINVAL;
> - }
> -
> - /* apply zooming and h or v expansion */
> - osd_device->ops.set_zoom(osd_device,
> - layer->layer_info.id,
> - layer->layer_info.h_zoom,
> - layer->layer_info.v_zoom);
> - ret = osd_device->ops.set_vid_expansion(osd_device,
> - layer->layer_info.h_exp,
> - layer->layer_info.v_exp);
> - if (ret < 0) {
> - v4l2_err(&vpbe_dev->v4l2_dev,
> - "Error in set vid expansion:\n");
> - return -EINVAL;
> - }
> -
> - if ((layer->layer_info.h_zoom != ZOOM_X1) ||
> - (layer->layer_info.v_zoom != ZOOM_X1) ||
> - (layer->layer_info.h_exp != H_EXP_OFF) ||
> - (layer->layer_info.v_exp != V_EXP_OFF))
> - /* Enable expansion filter */
> - osd_device->ops.set_interpolation_filter(osd_device, 1);
> - else
> - osd_device->ops.set_interpolation_filter(osd_device, 0);
> -
> - sel->r = rect;
> - return 0;
> -}
> -
> -static int vpbe_display_g_selection(struct file *file, void *priv,
> - struct v4l2_selection *sel)
> -{
> - struct vpbe_layer *layer = video_drvdata(file);
> - struct osd_layer_config *cfg = &layer->layer_info.config;
> - struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev;
> - struct osd_state *osd_device = layer->disp_dev->osd_device;
> - struct v4l2_rect *rect = &sel->r;
> -
> - v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev,
> - "VIDIOC_G_SELECTION, layer id = %d\n",
> - layer->device_id);
> -
> - if (sel->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
> - return -EINVAL;
> -
> - switch (sel->target) {
> - case V4L2_SEL_TGT_CROP:
> - osd_device->ops.get_layer_config(osd_device,
> - layer->layer_info.id, cfg);
> - rect->top = cfg->ypos;
> - rect->left = cfg->xpos;
> - rect->width = cfg->xsize;
> - rect->height = cfg->ysize;
> - break;
> - case V4L2_SEL_TGT_CROP_DEFAULT:
> - case V4L2_SEL_TGT_CROP_BOUNDS:
> - rect->left = 0;
> - rect->top = 0;
> - rect->width = vpbe_dev->current_timings.xres;
> - rect->height = vpbe_dev->current_timings.yres;
> - break;
> - default:
> - return -EINVAL;
> - }
> -
> - return 0;
> -}
> -
> -static int vpbe_display_g_pixelaspect(struct file *file, void *priv,
> - int type, struct v4l2_fract *f)
> -{
> - struct vpbe_layer *layer = video_drvdata(file);
> - struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev;
> -
> - v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "VIDIOC_CROPCAP ioctl\n");
> -
> - if (type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
> - return -EINVAL;
> -
> - *f = vpbe_dev->current_timings.aspect;
> - return 0;
> -}
> -
> -static int vpbe_display_g_fmt(struct file *file, void *priv,
> - struct v4l2_format *fmt)
> -{
> - struct vpbe_layer *layer = video_drvdata(file);
> - struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev;
> -
> - v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev,
> - "VIDIOC_G_FMT, layer id = %d\n",
> - layer->device_id);
> -
> - /* If buffer type is video output */
> - if (V4L2_BUF_TYPE_VIDEO_OUTPUT != fmt->type) {
> - v4l2_err(&vpbe_dev->v4l2_dev, "invalid type\n");
> - return -EINVAL;
> - }
> - /* Fill in the information about format */
> - fmt->fmt.pix = layer->pix_fmt;
> -
> - return 0;
> -}
> -
> -static int vpbe_display_enum_fmt(struct file *file, void *priv,
> - struct v4l2_fmtdesc *fmt)
> -{
> - struct vpbe_layer *layer = video_drvdata(file);
> - struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev;
> -
> - v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev,
> - "VIDIOC_ENUM_FMT, layer id = %d\n",
> - layer->device_id);
> - if (fmt->index > 1) {
> - v4l2_err(&vpbe_dev->v4l2_dev, "Invalid format index\n");
> - return -EINVAL;
> - }
> -
> - /* Fill in the information about format */
> - if (fmt->index == 0)
> - fmt->pixelformat = V4L2_PIX_FMT_UYVY;
> - else
> - fmt->pixelformat = V4L2_PIX_FMT_NV12;
> -
> - return 0;
> -}
> -
> -static int vpbe_display_s_fmt(struct file *file, void *priv,
> - struct v4l2_format *fmt)
> -{
> - struct vpbe_layer *layer = video_drvdata(file);
> - struct vpbe_display *disp_dev = layer->disp_dev;
> - struct vpbe_device *vpbe_dev = disp_dev->vpbe_dev;
> - struct osd_layer_config *cfg = &layer->layer_info.config;
> - struct v4l2_pix_format *pixfmt = &fmt->fmt.pix;
> - struct osd_state *osd_device = disp_dev->osd_device;
> - int ret;
> -
> - v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev,
> - "VIDIOC_S_FMT, layer id = %d\n",
> - layer->device_id);
> -
> - if (vb2_is_busy(&layer->buffer_queue))
> - return -EBUSY;
> -
> - if (V4L2_BUF_TYPE_VIDEO_OUTPUT != fmt->type) {
> - v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "invalid type\n");
> - return -EINVAL;
> - }
> - /* Check for valid pixel format */
> - ret = vpbe_try_format(disp_dev, pixfmt, 1);
> - if (ret)
> - return ret;
> -
> - /* YUV420 is requested, check availability of the
> - other video window */
> -
> - layer->pix_fmt = *pixfmt;
> - if (pixfmt->pixelformat == V4L2_PIX_FMT_NV12) {
> - struct vpbe_layer *otherlayer;
> -
> - otherlayer = _vpbe_display_get_other_win_layer(disp_dev, layer);
> - /* if other layer is available, only
> - * claim it, do not configure it
> - */
> - ret = osd_device->ops.request_layer(osd_device,
> - otherlayer->layer_info.id);
> - if (ret < 0) {
> - v4l2_err(&vpbe_dev->v4l2_dev,
> - "Display Manager failed to allocate layer\n");
> - return -EBUSY;
> - }
> - }
> -
> - /* Get osd layer config */
> - osd_device->ops.get_layer_config(osd_device,
> - layer->layer_info.id, cfg);
> - /* Store the pixel format in the layer object */
> - cfg->xsize = pixfmt->width;
> - cfg->ysize = pixfmt->height;
> - cfg->line_length = pixfmt->bytesperline;
> - cfg->ypos = 0;
> - cfg->xpos = 0;
> - cfg->interlaced = vpbe_dev->current_timings.interlaced;
> -
> - if (V4L2_PIX_FMT_UYVY == pixfmt->pixelformat)
> - cfg->pixfmt = PIXFMT_YCBCRI;
> -
> - /* Change of the default pixel format for both video windows */
> - if (V4L2_PIX_FMT_NV12 == pixfmt->pixelformat) {
> - struct vpbe_layer *otherlayer;
> - cfg->pixfmt = PIXFMT_NV12;
> - otherlayer = _vpbe_display_get_other_win_layer(disp_dev,
> - layer);
> - otherlayer->layer_info.config.pixfmt = PIXFMT_NV12;
> - }
> -
> - /* Set the layer config in the osd window */
> - ret = osd_device->ops.set_layer_config(osd_device,
> - layer->layer_info.id, cfg);
> - if (ret < 0) {
> - v4l2_err(&vpbe_dev->v4l2_dev,
> - "Error in S_FMT params:\n");
> - return -EINVAL;
> - }
> -
> - /* Readback and fill the local copy of current pix format */
> - osd_device->ops.get_layer_config(osd_device,
> - layer->layer_info.id, cfg);
> -
> - return 0;
> -}
> -
> -static int vpbe_display_try_fmt(struct file *file, void *priv,
> - struct v4l2_format *fmt)
> -{
> - struct vpbe_layer *layer = video_drvdata(file);
> - struct vpbe_display *disp_dev = layer->disp_dev;
> - struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev;
> - struct v4l2_pix_format *pixfmt = &fmt->fmt.pix;
> -
> - v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "VIDIOC_TRY_FMT\n");
> -
> - if (V4L2_BUF_TYPE_VIDEO_OUTPUT != fmt->type) {
> - v4l2_err(&vpbe_dev->v4l2_dev, "invalid type\n");
> - return -EINVAL;
> - }
> -
> - /* Check for valid field format */
> - return vpbe_try_format(disp_dev, pixfmt, 0);
> -
> -}
> -
> -/*
> - * vpbe_display_s_std - Set the given standard in the encoder
> - *
> - * Sets the standard if supported by the current encoder. Return the status.
> - * 0 - success & -EINVAL on error
> - */
> -static int vpbe_display_s_std(struct file *file, void *priv,
> - v4l2_std_id std_id)
> -{
> - struct vpbe_layer *layer = video_drvdata(file);
> - struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev;
> - int ret;
> -
> - v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "VIDIOC_S_STD\n");
> -
> - if (vb2_is_busy(&layer->buffer_queue))
> - return -EBUSY;
> -
> - if (vpbe_dev->ops.s_std) {
> - ret = vpbe_dev->ops.s_std(vpbe_dev, std_id);
> - if (ret) {
> - v4l2_err(&vpbe_dev->v4l2_dev,
> - "Failed to set standard for sub devices\n");
> - return -EINVAL;
> - }
> - } else {
> - return -EINVAL;
> - }
> -
> - return 0;
> -}
> -
> -/*
> - * vpbe_display_g_std - Get the standard in the current encoder
> - *
> - * Get the standard in the current encoder. Return the status. 0 - success
> - * -EINVAL on error
> - */
> -static int vpbe_display_g_std(struct file *file, void *priv,
> - v4l2_std_id *std_id)
> -{
> - struct vpbe_layer *layer = video_drvdata(file);
> - struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev;
> -
> - v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "VIDIOC_G_STD\n");
> -
> - /* Get the standard from the current encoder */
> - if (vpbe_dev->current_timings.timings_type & VPBE_ENC_STD) {
> - *std_id = vpbe_dev->current_timings.std_id;
> - return 0;
> - }
> -
> - return -EINVAL;
> -}
> -
> -/*
> - * vpbe_display_enum_output - enumerate outputs
> - *
> - * Enumerates the outputs available at the vpbe display
> - * returns the status, -EINVAL if end of output list
> - */
> -static int vpbe_display_enum_output(struct file *file, void *priv,
> - struct v4l2_output *output)
> -{
> - struct vpbe_layer *layer = video_drvdata(file);
> - struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev;
> - int ret;
> -
> - v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "VIDIOC_ENUM_OUTPUT\n");
> -
> - /* Enumerate outputs */
> - if (!vpbe_dev->ops.enum_outputs)
> - return -EINVAL;
> -
> - ret = vpbe_dev->ops.enum_outputs(vpbe_dev, output);
> - if (ret) {
> - v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev,
> - "Failed to enumerate outputs\n");
> - return -EINVAL;
> - }
> -
> - return 0;
> -}
> -
> -/*
> - * vpbe_display_s_output - Set output to
> - * the output specified by the index
> - */
> -static int vpbe_display_s_output(struct file *file, void *priv,
> - unsigned int i)
> -{
> - struct vpbe_layer *layer = video_drvdata(file);
> - struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev;
> - int ret;
> -
> - v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "VIDIOC_S_OUTPUT\n");
> -
> - if (vb2_is_busy(&layer->buffer_queue))
> - return -EBUSY;
> -
> - if (!vpbe_dev->ops.set_output)
> - return -EINVAL;
> -
> - ret = vpbe_dev->ops.set_output(vpbe_dev, i);
> - if (ret) {
> - v4l2_err(&vpbe_dev->v4l2_dev,
> - "Failed to set output for sub devices\n");
> - return -EINVAL;
> - }
> -
> - return 0;
> -}
> -
> -/*
> - * vpbe_display_g_output - Get output from subdevice
> - * for a given by the index
> - */
> -static int vpbe_display_g_output(struct file *file, void *priv,
> - unsigned int *i)
> -{
> - struct vpbe_layer *layer = video_drvdata(file);
> - struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev;
> -
> - v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "VIDIOC_G_OUTPUT\n");
> - /* Get the standard from the current encoder */
> - *i = vpbe_dev->current_out_index;
> -
> - return 0;
> -}
> -
> -/*
> - * vpbe_display_enum_dv_timings - Enumerate the dv timings
> - *
> - * enum the timings in the current encoder. Return the status. 0 - success
> - * -EINVAL on error
> - */
> -static int
> -vpbe_display_enum_dv_timings(struct file *file, void *priv,
> - struct v4l2_enum_dv_timings *timings)
> -{
> - struct vpbe_layer *layer = video_drvdata(file);
> - struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev;
> - int ret;
> -
> - v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "VIDIOC_ENUM_DV_TIMINGS\n");
> -
> - /* Enumerate outputs */
> - if (!vpbe_dev->ops.enum_dv_timings)
> - return -EINVAL;
> -
> - ret = vpbe_dev->ops.enum_dv_timings(vpbe_dev, timings);
> - if (ret) {
> - v4l2_err(&vpbe_dev->v4l2_dev,
> - "Failed to enumerate dv timings info\n");
> - return -EINVAL;
> - }
> -
> - return 0;
> -}
> -
> -/*
> - * vpbe_display_s_dv_timings - Set the dv timings
> - *
> - * Set the timings in the current encoder. Return the status. 0 - success
> - * -EINVAL on error
> - */
> -static int
> -vpbe_display_s_dv_timings(struct file *file, void *priv,
> - struct v4l2_dv_timings *timings)
> -{
> - struct vpbe_layer *layer = video_drvdata(file);
> - struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev;
> - int ret;
> -
> - v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "VIDIOC_S_DV_TIMINGS\n");
> -
> - if (vb2_is_busy(&layer->buffer_queue))
> - return -EBUSY;
> -
> - /* Set the given standard in the encoder */
> - if (!vpbe_dev->ops.s_dv_timings)
> - return -EINVAL;
> -
> - ret = vpbe_dev->ops.s_dv_timings(vpbe_dev, timings);
> - if (ret) {
> - v4l2_err(&vpbe_dev->v4l2_dev,
> - "Failed to set the dv timings info\n");
> - return -EINVAL;
> - }
> -
> - return 0;
> -}
> -
> -/*
> - * vpbe_display_g_dv_timings - Set the dv timings
> - *
> - * Get the timings in the current encoder. Return the status. 0 - success
> - * -EINVAL on error
> - */
> -static int
> -vpbe_display_g_dv_timings(struct file *file, void *priv,
> - struct v4l2_dv_timings *dv_timings)
> -{
> - struct vpbe_layer *layer = video_drvdata(file);
> - struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev;
> -
> - v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "VIDIOC_G_DV_TIMINGS\n");
> -
> - /* Get the given standard in the encoder */
> -
> - if (vpbe_dev->current_timings.timings_type &
> - VPBE_ENC_DV_TIMINGS) {
> - *dv_timings = vpbe_dev->current_timings.dv_timings;
> - } else {
> - return -EINVAL;
> - }
> -
> - return 0;
> -}
> -
> -/*
> - * vpbe_display_open()
> - * It creates object of file handle structure and stores it in private_data
> - * member of filepointer
> - */
> -static int vpbe_display_open(struct file *file)
> -{
> - struct vpbe_layer *layer = video_drvdata(file);
> - struct vpbe_display *disp_dev = layer->disp_dev;
> - struct vpbe_device *vpbe_dev = disp_dev->vpbe_dev;
> - struct osd_state *osd_device = disp_dev->osd_device;
> - int err;
> -
> - /* creating context for file descriptor */
> - err = v4l2_fh_open(file);
> - if (err) {
> - v4l2_err(&vpbe_dev->v4l2_dev, "v4l2_fh_open failed\n");
> - return err;
> - }
> -
> - /* leaving if layer is already initialized */
> - if (!v4l2_fh_is_singular_file(file))
> - return err;
> -
> - if (!layer->usrs) {
> - if (mutex_lock_interruptible(&layer->opslock))
> - return -ERESTARTSYS;
> - /* First claim the layer for this device */
> - err = osd_device->ops.request_layer(osd_device,
> - layer->layer_info.id);
> - mutex_unlock(&layer->opslock);
> - if (err < 0) {
> - /* Couldn't get layer */
> - v4l2_err(&vpbe_dev->v4l2_dev,
> - "Display Manager failed to allocate layer\n");
> - v4l2_fh_release(file);
> - return -EINVAL;
> - }
> - }
> - /* Increment layer usrs counter */
> - layer->usrs++;
> - v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev,
> - "vpbe display device opened successfully\n");
> - return 0;
> -}
> -
> -/*
> - * vpbe_display_release()
> - * This function deletes buffer queue, frees the buffers and the davinci
> - * display file * handle
> - */
> -static int vpbe_display_release(struct file *file)
> -{
> - struct vpbe_layer *layer = video_drvdata(file);
> - struct osd_layer_config *cfg = &layer->layer_info.config;
> - struct vpbe_display *disp_dev = layer->disp_dev;
> - struct vpbe_device *vpbe_dev = disp_dev->vpbe_dev;
> - struct osd_state *osd_device = disp_dev->osd_device;
> -
> - v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "vpbe_display_release\n");
> -
> - mutex_lock(&layer->opslock);
> -
> - osd_device->ops.disable_layer(osd_device,
> - layer->layer_info.id);
> - /* Decrement layer usrs counter */
> - layer->usrs--;
> - /* If this file handle has initialize encoder device, reset it */
> - if (!layer->usrs) {
> - if (cfg->pixfmt == PIXFMT_NV12) {
> - struct vpbe_layer *otherlayer;
> - otherlayer =
> - _vpbe_display_get_other_win_layer(disp_dev, layer);
> - osd_device->ops.disable_layer(osd_device,
> - otherlayer->layer_info.id);
> - osd_device->ops.release_layer(osd_device,
> - otherlayer->layer_info.id);
> - }
> - osd_device->ops.disable_layer(osd_device,
> - layer->layer_info.id);
> - osd_device->ops.release_layer(osd_device,
> - layer->layer_info.id);
> - }
> -
> - _vb2_fop_release(file, NULL);
> - mutex_unlock(&layer->opslock);
> -
> - disp_dev->cbcr_ofst = 0;
> -
> - return 0;
> -}
> -
> -/* vpbe capture ioctl operations */
> -static const struct v4l2_ioctl_ops vpbe_ioctl_ops = {
> - .vidioc_querycap = vpbe_display_querycap,
> - .vidioc_g_fmt_vid_out = vpbe_display_g_fmt,
> - .vidioc_enum_fmt_vid_out = vpbe_display_enum_fmt,
> - .vidioc_s_fmt_vid_out = vpbe_display_s_fmt,
> - .vidioc_try_fmt_vid_out = vpbe_display_try_fmt,
> -
> - .vidioc_reqbufs = vb2_ioctl_reqbufs,
> - .vidioc_create_bufs = vb2_ioctl_create_bufs,
> - .vidioc_querybuf = vb2_ioctl_querybuf,
> - .vidioc_qbuf = vb2_ioctl_qbuf,
> - .vidioc_dqbuf = vb2_ioctl_dqbuf,
> - .vidioc_streamon = vb2_ioctl_streamon,
> - .vidioc_streamoff = vb2_ioctl_streamoff,
> - .vidioc_expbuf = vb2_ioctl_expbuf,
> -
> - .vidioc_g_pixelaspect = vpbe_display_g_pixelaspect,
> - .vidioc_g_selection = vpbe_display_g_selection,
> - .vidioc_s_selection = vpbe_display_s_selection,
> -
> - .vidioc_s_std = vpbe_display_s_std,
> - .vidioc_g_std = vpbe_display_g_std,
> -
> - .vidioc_enum_output = vpbe_display_enum_output,
> - .vidioc_s_output = vpbe_display_s_output,
> - .vidioc_g_output = vpbe_display_g_output,
> -
> - .vidioc_s_dv_timings = vpbe_display_s_dv_timings,
> - .vidioc_g_dv_timings = vpbe_display_g_dv_timings,
> - .vidioc_enum_dv_timings = vpbe_display_enum_dv_timings,
> -};
> -
> -static const struct v4l2_file_operations vpbe_fops = {
> - .owner = THIS_MODULE,
> - .open = vpbe_display_open,
> - .release = vpbe_display_release,
> - .unlocked_ioctl = video_ioctl2,
> - .mmap = vb2_fop_mmap,
> - .poll = vb2_fop_poll,
> -};
> -
> -static int vpbe_device_get(struct device *dev, void *data)
> -{
> - struct platform_device *pdev = to_platform_device(dev);
> - struct vpbe_display *vpbe_disp = data;
> -
> - if (strcmp("vpbe_controller", pdev->name) == 0)
> - vpbe_disp->vpbe_dev = platform_get_drvdata(pdev);
> -
> - if (strstr(pdev->name, "vpbe-osd"))
> - vpbe_disp->osd_device = platform_get_drvdata(pdev);
> -
> - return 0;
> -}
> -
> -static int init_vpbe_layer(int i, struct vpbe_display *disp_dev,
> - struct platform_device *pdev)
> -{
> - struct vpbe_layer *vpbe_display_layer = NULL;
> - struct video_device *vbd = NULL;
> -
> - /* Allocate memory for four plane display objects */
> - disp_dev->dev[i] = kzalloc(sizeof(*disp_dev->dev[i]), GFP_KERNEL);
> - if (!disp_dev->dev[i])
> - return -ENOMEM;
> -
> - spin_lock_init(&disp_dev->dev[i]->irqlock);
> - mutex_init(&disp_dev->dev[i]->opslock);
> -
> - /* Get the pointer to the layer object */
> - vpbe_display_layer = disp_dev->dev[i];
> - vbd = &vpbe_display_layer->video_dev;
> - /* Initialize field of video device */
> - vbd->release = video_device_release_empty;
> - vbd->fops = &vpbe_fops;
> - vbd->ioctl_ops = &vpbe_ioctl_ops;
> - vbd->minor = -1;
> - vbd->v4l2_dev = &disp_dev->vpbe_dev->v4l2_dev;
> - vbd->lock = &vpbe_display_layer->opslock;
> - vbd->vfl_dir = VFL_DIR_TX;
> - vbd->device_caps = V4L2_CAP_VIDEO_OUTPUT | V4L2_CAP_STREAMING;
> -
> - if (disp_dev->vpbe_dev->current_timings.timings_type &
> - VPBE_ENC_STD)
> - vbd->tvnorms = (V4L2_STD_525_60 | V4L2_STD_625_50);
> -
> - snprintf(vbd->name, sizeof(vbd->name),
> - "DaVinci_VPBE Display_DRIVER_V%d.%d.%d",
> - (VPBE_DISPLAY_VERSION_CODE >> 16) & 0xff,
> - (VPBE_DISPLAY_VERSION_CODE >> 8) & 0xff,
> - (VPBE_DISPLAY_VERSION_CODE) & 0xff);
> -
> - vpbe_display_layer->device_id = i;
> -
> - vpbe_display_layer->layer_info.id =
> - ((i == VPBE_DISPLAY_DEVICE_0) ? WIN_VID0 : WIN_VID1);
> -
> -
> - return 0;
> -}
> -
> -static int register_device(struct vpbe_layer *vpbe_display_layer,
> - struct vpbe_display *disp_dev,
> - struct platform_device *pdev)
> -{
> - int err;
> -
> - v4l2_info(&disp_dev->vpbe_dev->v4l2_dev,
> - "Trying to register VPBE display device.\n");
> - v4l2_info(&disp_dev->vpbe_dev->v4l2_dev,
> - "layer=%p,layer->video_dev=%p\n",
> - vpbe_display_layer,
> - &vpbe_display_layer->video_dev);
> -
> - vpbe_display_layer->video_dev.queue = &vpbe_display_layer->buffer_queue;
> - err = video_register_device(&vpbe_display_layer->video_dev,
> - VFL_TYPE_VIDEO,
> - -1);
> - if (err)
> - return -ENODEV;
> -
> - vpbe_display_layer->disp_dev = disp_dev;
> - /* set the driver data in platform device */
> - platform_set_drvdata(pdev, disp_dev);
> - video_set_drvdata(&vpbe_display_layer->video_dev,
> - vpbe_display_layer);
> -
> - return 0;
> -}
> -
> -
> -
> -/*
> - * vpbe_display_probe()
> - * This function creates device entries by register itself to the V4L2 driver
> - * and initializes fields of each layer objects
> - */
> -static int vpbe_display_probe(struct platform_device *pdev)
> -{
> - struct vpbe_display *disp_dev;
> - struct v4l2_device *v4l2_dev;
> - struct resource *res = NULL;
> - struct vb2_queue *q;
> - int k;
> - int i;
> - int err;
> - int irq;
> -
> - printk(KERN_DEBUG "vpbe_display_probe\n");
> - /* Allocate memory for vpbe_display */
> - disp_dev = devm_kzalloc(&pdev->dev, sizeof(*disp_dev), GFP_KERNEL);
> - if (!disp_dev)
> - return -ENOMEM;
> -
> - spin_lock_init(&disp_dev->dma_queue_lock);
> - /*
> - * Scan all the platform devices to find the vpbe
> - * controller device and get the vpbe_dev object
> - */
> - err = bus_for_each_dev(&platform_bus_type, NULL, disp_dev,
> - vpbe_device_get);
> - if (err < 0)
> - return err;
> -
> - v4l2_dev = &disp_dev->vpbe_dev->v4l2_dev;
> - /* Initialize the vpbe display controller */
> - if (disp_dev->vpbe_dev->ops.initialize) {
> - err = disp_dev->vpbe_dev->ops.initialize(&pdev->dev,
> - disp_dev->vpbe_dev);
> - if (err) {
> - v4l2_err(v4l2_dev, "Error initing vpbe\n");
> - err = -ENOMEM;
> - goto probe_out;
> - }
> - }
> -
> - for (i = 0; i < VPBE_DISPLAY_MAX_DEVICES; i++) {
> - if (init_vpbe_layer(i, disp_dev, pdev)) {
> - err = -ENODEV;
> - goto probe_out;
> - }
> - }
> -
> - res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
> - if (!res) {
> - v4l2_err(v4l2_dev, "Unable to get VENC interrupt resource\n");
> - err = -ENODEV;
> - goto probe_out;
> - }
> -
> - irq = res->start;
> - err = devm_request_irq(&pdev->dev, irq, venc_isr, 0,
> - VPBE_DISPLAY_DRIVER, disp_dev);
> - if (err) {
> - v4l2_err(v4l2_dev, "VPBE IRQ request failed\n");
> - goto probe_out;
> - }
> -
> - for (i = 0; i < VPBE_DISPLAY_MAX_DEVICES; i++) {
> - /* initialize vb2 queue */
> - q = &disp_dev->dev[i]->buffer_queue;
> - memset(q, 0, sizeof(*q));
> - q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
> - q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
> - q->drv_priv = disp_dev->dev[i];
> - q->ops = &video_qops;
> - q->mem_ops = &vb2_dma_contig_memops;
> - q->buf_struct_size = sizeof(struct vpbe_disp_buffer);
> - q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
> - q->min_buffers_needed = 1;
> - q->lock = &disp_dev->dev[i]->opslock;
> - q->dev = disp_dev->vpbe_dev->pdev;
> - err = vb2_queue_init(q);
> - if (err) {
> - v4l2_err(v4l2_dev, "vb2_queue_init() failed\n");
> - goto probe_out;
> - }
> -
> - INIT_LIST_HEAD(&disp_dev->dev[i]->dma_queue);
> -
> - if (register_device(disp_dev->dev[i], disp_dev, pdev)) {
> - err = -ENODEV;
> - goto probe_out;
> - }
> - }
> -
> - v4l2_dbg(1, debug, v4l2_dev,
> - "Successfully completed the probing of vpbe v4l2 device\n");
> -
> - return 0;
> -
> -probe_out:
> - for (k = 0; k < VPBE_DISPLAY_MAX_DEVICES; k++) {
> - /* Unregister video device */
> - if (disp_dev->dev[k]) {
> - video_unregister_device(&disp_dev->dev[k]->video_dev);
> - kfree(disp_dev->dev[k]);
> - }
> - }
> - return err;
> -}
> -
> -/*
> - * vpbe_display_remove()
> - * It un-register hardware layer from V4L2 driver
> - */
> -static int vpbe_display_remove(struct platform_device *pdev)
> -{
> - struct vpbe_layer *vpbe_display_layer;
> - struct vpbe_display *disp_dev = platform_get_drvdata(pdev);
> - struct vpbe_device *vpbe_dev = disp_dev->vpbe_dev;
> - int i;
> -
> - v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "vpbe_display_remove\n");
> -
> - /* deinitialize the vpbe display controller */
> - if (vpbe_dev->ops.deinitialize)
> - vpbe_dev->ops.deinitialize(&pdev->dev, vpbe_dev);
> - /* un-register device */
> - for (i = 0; i < VPBE_DISPLAY_MAX_DEVICES; i++) {
> - /* Get the pointer to the layer object */
> - vpbe_display_layer = disp_dev->dev[i];
> - /* Unregister video device */
> - video_unregister_device(&vpbe_display_layer->video_dev);
> -
> - }
> - for (i = 0; i < VPBE_DISPLAY_MAX_DEVICES; i++) {
> - kfree(disp_dev->dev[i]);
> - disp_dev->dev[i] = NULL;
> - }
> -
> - return 0;
> -}
> -
> -static struct platform_driver vpbe_display_driver = {
> - .driver = {
> - .name = VPBE_DISPLAY_DRIVER,
> - .bus = &platform_bus_type,
> - },
> - .probe = vpbe_display_probe,
> - .remove = vpbe_display_remove,
> -};
> -
> -module_platform_driver(vpbe_display_driver);
> -
> -MODULE_DESCRIPTION("TI DM644x/DM355/DM365 VPBE Display controller");
> -MODULE_LICENSE("GPL");
> -MODULE_AUTHOR("Texas Instruments");
> diff --git a/drivers/media/platform/ti/davinci/vpbe_osd.c b/drivers/media/platform/ti/davinci/vpbe_osd.c
> deleted file mode 100644
> index 32f7ef547c82..000000000000
> --- a/drivers/media/platform/ti/davinci/vpbe_osd.c
> +++ /dev/null
> @@ -1,1582 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * Copyright (C) 2007-2010 Texas Instruments Inc
> - * Copyright (C) 2007 MontaVista Software, Inc.
> - *
> - * Andy Lowe (alowe@mvista.com), MontaVista Software
> - * - Initial version
> - * Murali Karicheri (mkaricheri@gmail.com), Texas Instruments Ltd.
> - * - ported to sub device interface
> - */
> -#include <linux/module.h>
> -#include <linux/mod_devicetable.h>
> -#include <linux/kernel.h>
> -#include <linux/interrupt.h>
> -#include <linux/platform_device.h>
> -#include <linux/clk.h>
> -#include <linux/slab.h>
> -
> -#include <media/davinci/vpss.h>
> -#include <media/v4l2-device.h>
> -#include <media/davinci/vpbe_types.h>
> -#include <media/davinci/vpbe_osd.h>
> -
> -#include <linux/io.h>
> -#include "vpbe_osd_regs.h"
> -
> -#define MODULE_NAME "davinci-vpbe-osd"
> -
> -static const struct platform_device_id vpbe_osd_devtype[] = {
> - {
> - .name = DM644X_VPBE_OSD_SUBDEV_NAME,
> - .driver_data = VPBE_VERSION_1,
> - }, {
> - .name = DM365_VPBE_OSD_SUBDEV_NAME,
> - .driver_data = VPBE_VERSION_2,
> - }, {
> - .name = DM355_VPBE_OSD_SUBDEV_NAME,
> - .driver_data = VPBE_VERSION_3,
> - },
> - {
> - /* sentinel */
> - }
> -};
> -
> -MODULE_DEVICE_TABLE(platform, vpbe_osd_devtype);
> -
> -/* register access routines */
> -static inline u32 __always_unused osd_read(struct osd_state *sd, u32 offset)
> -{
> - struct osd_state *osd = sd;
> -
> - return readl(osd->osd_base + offset);
> -}
> -
> -static inline u32 osd_write(struct osd_state *sd, u32 val, u32 offset)
> -{
> - struct osd_state *osd = sd;
> -
> - writel(val, osd->osd_base + offset);
> -
> - return val;
> -}
> -
> -static inline u32 osd_set(struct osd_state *sd, u32 mask, u32 offset)
> -{
> - struct osd_state *osd = sd;
> -
> - void __iomem *addr = osd->osd_base + offset;
> - u32 val = readl(addr) | mask;
> -
> - writel(val, addr);
> -
> - return val;
> -}
> -
> -static inline u32 osd_clear(struct osd_state *sd, u32 mask, u32 offset)
> -{
> - struct osd_state *osd = sd;
> -
> - void __iomem *addr = osd->osd_base + offset;
> - u32 val = readl(addr) & ~mask;
> -
> - writel(val, addr);
> -
> - return val;
> -}
> -
> -static inline u32 osd_modify(struct osd_state *sd, u32 mask, u32 val,
> - u32 offset)
> -{
> - struct osd_state *osd = sd;
> -
> - void __iomem *addr = osd->osd_base + offset;
> - u32 new_val = (readl(addr) & ~mask) | (val & mask);
> -
> - writel(new_val, addr);
> -
> - return new_val;
> -}
> -
> -/* define some macros for layer and pixfmt classification */
> -#define is_osd_win(layer) (((layer) == WIN_OSD0) || ((layer) == WIN_OSD1))
> -#define is_vid_win(layer) (((layer) == WIN_VID0) || ((layer) == WIN_VID1))
> -#define is_rgb_pixfmt(pixfmt) \
> - (((pixfmt) == PIXFMT_RGB565) || ((pixfmt) == PIXFMT_RGB888))
> -#define is_yc_pixfmt(pixfmt) \
> - (((pixfmt) == PIXFMT_YCBCRI) || ((pixfmt) == PIXFMT_YCRCBI) || \
> - ((pixfmt) == PIXFMT_NV12))
> -#define MAX_WIN_SIZE OSD_VIDWIN0XP_V0X
> -#define MAX_LINE_LENGTH (OSD_VIDWIN0OFST_V0LO << 5)
> -
> -/**
> - * _osd_dm6446_vid0_pingpong() - field inversion fix for DM6446
> - * @sd: ptr to struct osd_state
> - * @field_inversion: inversion flag
> - * @fb_base_phys: frame buffer address
> - * @lconfig: ptr to layer config
> - *
> - * This routine implements a workaround for the field signal inversion silicon
> - * erratum described in Advisory 1.3.8 for the DM6446. The fb_base_phys and
> - * lconfig parameters apply to the vid0 window. This routine should be called
> - * whenever the vid0 layer configuration or start address is modified, or when
> - * the OSD field inversion setting is modified.
> - * Returns: 1 if the ping-pong buffers need to be toggled in the vsync isr, or
> - * 0 otherwise
> - */
> -static int _osd_dm6446_vid0_pingpong(struct osd_state *sd,
> - int field_inversion,
> - unsigned long fb_base_phys,
> - const struct osd_layer_config *lconfig)
> -{
> - struct osd_platform_data *pdata;
> -
> - pdata = (struct osd_platform_data *)sd->dev->platform_data;
> - if (pdata != NULL && pdata->field_inv_wa_enable) {
> -
> - if (!field_inversion || !lconfig->interlaced) {
> - osd_write(sd, fb_base_phys & ~0x1F, OSD_VIDWIN0ADR);
> - osd_write(sd, fb_base_phys & ~0x1F, OSD_PPVWIN0ADR);
> - osd_modify(sd, OSD_MISCCTL_PPSW | OSD_MISCCTL_PPRV, 0,
> - OSD_MISCCTL);
> - return 0;
> - } else {
> - unsigned miscctl = OSD_MISCCTL_PPRV;
> -
> - osd_write(sd,
> - (fb_base_phys & ~0x1F) - lconfig->line_length,
> - OSD_VIDWIN0ADR);
> - osd_write(sd,
> - (fb_base_phys & ~0x1F) + lconfig->line_length,
> - OSD_PPVWIN0ADR);
> - osd_modify(sd,
> - OSD_MISCCTL_PPSW | OSD_MISCCTL_PPRV, miscctl,
> - OSD_MISCCTL);
> -
> - return 1;
> - }
> - }
> -
> - return 0;
> -}
> -
> -static void _osd_set_field_inversion(struct osd_state *sd, int enable)
> -{
> - unsigned fsinv = 0;
> -
> - if (enable)
> - fsinv = OSD_MODE_FSINV;
> -
> - osd_modify(sd, OSD_MODE_FSINV, fsinv, OSD_MODE);
> -}
> -
> -static void _osd_set_blink_attribute(struct osd_state *sd, int enable,
> - enum osd_blink_interval blink)
> -{
> - u32 osdatrmd = 0;
> -
> - if (enable) {
> - osdatrmd |= OSD_OSDATRMD_BLNK;
> - osdatrmd |= blink << OSD_OSDATRMD_BLNKINT_SHIFT;
> - }
> - /* caller must ensure that OSD1 is configured in attribute mode */
> - osd_modify(sd, OSD_OSDATRMD_BLNKINT | OSD_OSDATRMD_BLNK, osdatrmd,
> - OSD_OSDATRMD);
> -}
> -
> -static void _osd_set_rom_clut(struct osd_state *sd,
> - enum osd_rom_clut rom_clut)
> -{
> - if (rom_clut == ROM_CLUT0)
> - osd_clear(sd, OSD_MISCCTL_RSEL, OSD_MISCCTL);
> - else
> - osd_set(sd, OSD_MISCCTL_RSEL, OSD_MISCCTL);
> -}
> -
> -static void _osd_set_palette_map(struct osd_state *sd,
> - enum osd_win_layer osdwin,
> - unsigned char pixel_value,
> - unsigned char clut_index,
> - enum osd_pix_format pixfmt)
> -{
> - static const int map_2bpp[] = { 0, 5, 10, 15 };
> - static const int map_1bpp[] = { 0, 15 };
> - int bmp_offset;
> - int bmp_shift;
> - int bmp_mask;
> - int bmp_reg;
> -
> - switch (pixfmt) {
> - case PIXFMT_1BPP:
> - bmp_reg = map_1bpp[pixel_value & 0x1];
> - break;
> - case PIXFMT_2BPP:
> - bmp_reg = map_2bpp[pixel_value & 0x3];
> - break;
> - case PIXFMT_4BPP:
> - bmp_reg = pixel_value & 0xf;
> - break;
> - default:
> - return;
> - }
> -
> - switch (osdwin) {
> - case OSDWIN_OSD0:
> - bmp_offset = OSD_W0BMP01 + (bmp_reg >> 1) * sizeof(u32);
> - break;
> - case OSDWIN_OSD1:
> - bmp_offset = OSD_W1BMP01 + (bmp_reg >> 1) * sizeof(u32);
> - break;
> - default:
> - return;
> - }
> -
> - if (bmp_reg & 1) {
> - bmp_shift = 8;
> - bmp_mask = 0xff << 8;
> - } else {
> - bmp_shift = 0;
> - bmp_mask = 0xff;
> - }
> -
> - osd_modify(sd, bmp_mask, clut_index << bmp_shift, bmp_offset);
> -}
> -
> -static void _osd_set_rec601_attenuation(struct osd_state *sd,
> - enum osd_win_layer osdwin, int enable)
> -{
> - switch (osdwin) {
> - case OSDWIN_OSD0:
> - osd_modify(sd, OSD_OSDWIN0MD_ATN0E,
> - enable ? OSD_OSDWIN0MD_ATN0E : 0,
> - OSD_OSDWIN0MD);
> - if (sd->vpbe_type == VPBE_VERSION_1)
> - osd_modify(sd, OSD_OSDWIN0MD_ATN0E,
> - enable ? OSD_OSDWIN0MD_ATN0E : 0,
> - OSD_OSDWIN0MD);
> - else if ((sd->vpbe_type == VPBE_VERSION_3) ||
> - (sd->vpbe_type == VPBE_VERSION_2))
> - osd_modify(sd, OSD_EXTMODE_ATNOSD0EN,
> - enable ? OSD_EXTMODE_ATNOSD0EN : 0,
> - OSD_EXTMODE);
> - break;
> - case OSDWIN_OSD1:
> - osd_modify(sd, OSD_OSDWIN1MD_ATN1E,
> - enable ? OSD_OSDWIN1MD_ATN1E : 0,
> - OSD_OSDWIN1MD);
> - if (sd->vpbe_type == VPBE_VERSION_1)
> - osd_modify(sd, OSD_OSDWIN1MD_ATN1E,
> - enable ? OSD_OSDWIN1MD_ATN1E : 0,
> - OSD_OSDWIN1MD);
> - else if ((sd->vpbe_type == VPBE_VERSION_3) ||
> - (sd->vpbe_type == VPBE_VERSION_2))
> - osd_modify(sd, OSD_EXTMODE_ATNOSD1EN,
> - enable ? OSD_EXTMODE_ATNOSD1EN : 0,
> - OSD_EXTMODE);
> - break;
> - }
> -}
> -
> -static void _osd_set_blending_factor(struct osd_state *sd,
> - enum osd_win_layer osdwin,
> - enum osd_blending_factor blend)
> -{
> - switch (osdwin) {
> - case OSDWIN_OSD0:
> - osd_modify(sd, OSD_OSDWIN0MD_BLND0,
> - blend << OSD_OSDWIN0MD_BLND0_SHIFT, OSD_OSDWIN0MD);
> - break;
> - case OSDWIN_OSD1:
> - osd_modify(sd, OSD_OSDWIN1MD_BLND1,
> - blend << OSD_OSDWIN1MD_BLND1_SHIFT, OSD_OSDWIN1MD);
> - break;
> - }
> -}
> -
> -static void _osd_enable_rgb888_pixblend(struct osd_state *sd,
> - enum osd_win_layer osdwin)
> -{
> -
> - osd_modify(sd, OSD_MISCCTL_BLDSEL, 0, OSD_MISCCTL);
> - switch (osdwin) {
> - case OSDWIN_OSD0:
> - osd_modify(sd, OSD_EXTMODE_OSD0BLDCHR,
> - OSD_EXTMODE_OSD0BLDCHR, OSD_EXTMODE);
> - break;
> - case OSDWIN_OSD1:
> - osd_modify(sd, OSD_EXTMODE_OSD1BLDCHR,
> - OSD_EXTMODE_OSD1BLDCHR, OSD_EXTMODE);
> - break;
> - }
> -}
> -
> -static void _osd_enable_color_key(struct osd_state *sd,
> - enum osd_win_layer osdwin,
> - unsigned colorkey,
> - enum osd_pix_format pixfmt)
> -{
> - switch (pixfmt) {
> - case PIXFMT_1BPP:
> - case PIXFMT_2BPP:
> - case PIXFMT_4BPP:
> - case PIXFMT_8BPP:
> - if (sd->vpbe_type == VPBE_VERSION_3) {
> - switch (osdwin) {
> - case OSDWIN_OSD0:
> - osd_modify(sd, OSD_TRANSPBMPIDX_BMP0,
> - colorkey <<
> - OSD_TRANSPBMPIDX_BMP0_SHIFT,
> - OSD_TRANSPBMPIDX);
> - break;
> - case OSDWIN_OSD1:
> - osd_modify(sd, OSD_TRANSPBMPIDX_BMP1,
> - colorkey <<
> - OSD_TRANSPBMPIDX_BMP1_SHIFT,
> - OSD_TRANSPBMPIDX);
> - break;
> - }
> - }
> - break;
> - case PIXFMT_RGB565:
> - if (sd->vpbe_type == VPBE_VERSION_1)
> - osd_write(sd, colorkey & OSD_TRANSPVAL_RGBTRANS,
> - OSD_TRANSPVAL);
> - else if (sd->vpbe_type == VPBE_VERSION_3)
> - osd_write(sd, colorkey & OSD_TRANSPVALL_RGBL,
> - OSD_TRANSPVALL);
> - break;
> - case PIXFMT_YCBCRI:
> - case PIXFMT_YCRCBI:
> - if (sd->vpbe_type == VPBE_VERSION_3)
> - osd_modify(sd, OSD_TRANSPVALU_Y, colorkey,
> - OSD_TRANSPVALU);
> - break;
> - case PIXFMT_RGB888:
> - if (sd->vpbe_type == VPBE_VERSION_3) {
> - osd_write(sd, colorkey & OSD_TRANSPVALL_RGBL,
> - OSD_TRANSPVALL);
> - osd_modify(sd, OSD_TRANSPVALU_RGBU, colorkey >> 16,
> - OSD_TRANSPVALU);
> - }
> - break;
> - default:
> - break;
> - }
> -
> - switch (osdwin) {
> - case OSDWIN_OSD0:
> - osd_set(sd, OSD_OSDWIN0MD_TE0, OSD_OSDWIN0MD);
> - break;
> - case OSDWIN_OSD1:
> - osd_set(sd, OSD_OSDWIN1MD_TE1, OSD_OSDWIN1MD);
> - break;
> - }
> -}
> -
> -static void _osd_disable_color_key(struct osd_state *sd,
> - enum osd_win_layer osdwin)
> -{
> - switch (osdwin) {
> - case OSDWIN_OSD0:
> - osd_clear(sd, OSD_OSDWIN0MD_TE0, OSD_OSDWIN0MD);
> - break;
> - case OSDWIN_OSD1:
> - osd_clear(sd, OSD_OSDWIN1MD_TE1, OSD_OSDWIN1MD);
> - break;
> - }
> -}
> -
> -static void _osd_set_osd_clut(struct osd_state *sd,
> - enum osd_win_layer osdwin,
> - enum osd_clut clut)
> -{
> - u32 winmd = 0;
> -
> - switch (osdwin) {
> - case OSDWIN_OSD0:
> - if (clut == RAM_CLUT)
> - winmd |= OSD_OSDWIN0MD_CLUTS0;
> - osd_modify(sd, OSD_OSDWIN0MD_CLUTS0, winmd, OSD_OSDWIN0MD);
> - break;
> - case OSDWIN_OSD1:
> - if (clut == RAM_CLUT)
> - winmd |= OSD_OSDWIN1MD_CLUTS1;
> - osd_modify(sd, OSD_OSDWIN1MD_CLUTS1, winmd, OSD_OSDWIN1MD);
> - break;
> - }
> -}
> -
> -static void _osd_set_zoom(struct osd_state *sd, enum osd_layer layer,
> - enum osd_zoom_factor h_zoom,
> - enum osd_zoom_factor v_zoom)
> -{
> - u32 winmd = 0;
> -
> - switch (layer) {
> - case WIN_OSD0:
> - winmd |= (h_zoom << OSD_OSDWIN0MD_OHZ0_SHIFT);
> - winmd |= (v_zoom << OSD_OSDWIN0MD_OVZ0_SHIFT);
> - osd_modify(sd, OSD_OSDWIN0MD_OHZ0 | OSD_OSDWIN0MD_OVZ0, winmd,
> - OSD_OSDWIN0MD);
> - break;
> - case WIN_VID0:
> - winmd |= (h_zoom << OSD_VIDWINMD_VHZ0_SHIFT);
> - winmd |= (v_zoom << OSD_VIDWINMD_VVZ0_SHIFT);
> - osd_modify(sd, OSD_VIDWINMD_VHZ0 | OSD_VIDWINMD_VVZ0, winmd,
> - OSD_VIDWINMD);
> - break;
> - case WIN_OSD1:
> - winmd |= (h_zoom << OSD_OSDWIN1MD_OHZ1_SHIFT);
> - winmd |= (v_zoom << OSD_OSDWIN1MD_OVZ1_SHIFT);
> - osd_modify(sd, OSD_OSDWIN1MD_OHZ1 | OSD_OSDWIN1MD_OVZ1, winmd,
> - OSD_OSDWIN1MD);
> - break;
> - case WIN_VID1:
> - winmd |= (h_zoom << OSD_VIDWINMD_VHZ1_SHIFT);
> - winmd |= (v_zoom << OSD_VIDWINMD_VVZ1_SHIFT);
> - osd_modify(sd, OSD_VIDWINMD_VHZ1 | OSD_VIDWINMD_VVZ1, winmd,
> - OSD_VIDWINMD);
> - break;
> - }
> -}
> -
> -static void _osd_disable_layer(struct osd_state *sd, enum osd_layer layer)
> -{
> - switch (layer) {
> - case WIN_OSD0:
> - osd_clear(sd, OSD_OSDWIN0MD_OACT0, OSD_OSDWIN0MD);
> - break;
> - case WIN_VID0:
> - osd_clear(sd, OSD_VIDWINMD_ACT0, OSD_VIDWINMD);
> - break;
> - case WIN_OSD1:
> - /* disable attribute mode as well as disabling the window */
> - osd_clear(sd, OSD_OSDWIN1MD_OASW | OSD_OSDWIN1MD_OACT1,
> - OSD_OSDWIN1MD);
> - break;
> - case WIN_VID1:
> - osd_clear(sd, OSD_VIDWINMD_ACT1, OSD_VIDWINMD);
> - break;
> - }
> -}
> -
> -static void osd_disable_layer(struct osd_state *sd, enum osd_layer layer)
> -{
> - struct osd_state *osd = sd;
> - struct osd_window_state *win = &osd->win[layer];
> - unsigned long flags;
> -
> - spin_lock_irqsave(&osd->lock, flags);
> -
> - if (!win->is_enabled) {
> - spin_unlock_irqrestore(&osd->lock, flags);
> - return;
> - }
> - win->is_enabled = 0;
> -
> - _osd_disable_layer(sd, layer);
> -
> - spin_unlock_irqrestore(&osd->lock, flags);
> -}
> -
> -static void _osd_enable_attribute_mode(struct osd_state *sd)
> -{
> - /* enable attribute mode for OSD1 */
> - osd_set(sd, OSD_OSDWIN1MD_OASW, OSD_OSDWIN1MD);
> -}
> -
> -static void _osd_enable_layer(struct osd_state *sd, enum osd_layer layer)
> -{
> - switch (layer) {
> - case WIN_OSD0:
> - osd_set(sd, OSD_OSDWIN0MD_OACT0, OSD_OSDWIN0MD);
> - break;
> - case WIN_VID0:
> - osd_set(sd, OSD_VIDWINMD_ACT0, OSD_VIDWINMD);
> - break;
> - case WIN_OSD1:
> - /* enable OSD1 and disable attribute mode */
> - osd_modify(sd, OSD_OSDWIN1MD_OASW | OSD_OSDWIN1MD_OACT1,
> - OSD_OSDWIN1MD_OACT1, OSD_OSDWIN1MD);
> - break;
> - case WIN_VID1:
> - osd_set(sd, OSD_VIDWINMD_ACT1, OSD_VIDWINMD);
> - break;
> - }
> -}
> -
> -static int osd_enable_layer(struct osd_state *sd, enum osd_layer layer,
> - int otherwin)
> -{
> - struct osd_state *osd = sd;
> - struct osd_window_state *win = &osd->win[layer];
> - struct osd_layer_config *cfg = &win->lconfig;
> - unsigned long flags;
> -
> - spin_lock_irqsave(&osd->lock, flags);
> -
> - /*
> - * use otherwin flag to know this is the other vid window
> - * in YUV420 mode, if is, skip this check
> - */
> - if (!otherwin && (!win->is_allocated ||
> - !win->fb_base_phys ||
> - !cfg->line_length ||
> - !cfg->xsize ||
> - !cfg->ysize)) {
> - spin_unlock_irqrestore(&osd->lock, flags);
> - return -1;
> - }
> -
> - if (win->is_enabled) {
> - spin_unlock_irqrestore(&osd->lock, flags);
> - return 0;
> - }
> - win->is_enabled = 1;
> -
> - if (cfg->pixfmt != PIXFMT_OSD_ATTR)
> - _osd_enable_layer(sd, layer);
> - else {
> - _osd_enable_attribute_mode(sd);
> - _osd_set_blink_attribute(sd, osd->is_blinking, osd->blink);
> - }
> -
> - spin_unlock_irqrestore(&osd->lock, flags);
> -
> - return 0;
> -}
> -
> -#define OSD_SRC_ADDR_HIGH4 0x7800000
> -#define OSD_SRC_ADDR_HIGH7 0x7F0000
> -#define OSD_SRCADD_OFSET_SFT 23
> -#define OSD_SRCADD_ADD_SFT 16
> -#define OSD_WINADL_MASK 0xFFFF
> -#define OSD_WINOFST_MASK 0x1000
> -#define VPBE_REG_BASE 0x80000000
> -
> -static void _osd_start_layer(struct osd_state *sd, enum osd_layer layer,
> - unsigned long fb_base_phys,
> - unsigned long cbcr_ofst)
> -{
> -
> - if (sd->vpbe_type == VPBE_VERSION_1) {
> - switch (layer) {
> - case WIN_OSD0:
> - osd_write(sd, fb_base_phys & ~0x1F, OSD_OSDWIN0ADR);
> - break;
> - case WIN_VID0:
> - osd_write(sd, fb_base_phys & ~0x1F, OSD_VIDWIN0ADR);
> - break;
> - case WIN_OSD1:
> - osd_write(sd, fb_base_phys & ~0x1F, OSD_OSDWIN1ADR);
> - break;
> - case WIN_VID1:
> - osd_write(sd, fb_base_phys & ~0x1F, OSD_VIDWIN1ADR);
> - break;
> - }
> - } else if (sd->vpbe_type == VPBE_VERSION_3) {
> - unsigned long fb_offset_32 =
> - (fb_base_phys - VPBE_REG_BASE) >> 5;
> -
> - switch (layer) {
> - case WIN_OSD0:
> - osd_modify(sd, OSD_OSDWINADH_O0AH,
> - fb_offset_32 >> (OSD_SRCADD_ADD_SFT -
> - OSD_OSDWINADH_O0AH_SHIFT),
> - OSD_OSDWINADH);
> - osd_write(sd, fb_offset_32 & OSD_OSDWIN0ADL_O0AL,
> - OSD_OSDWIN0ADL);
> - break;
> - case WIN_VID0:
> - osd_modify(sd, OSD_VIDWINADH_V0AH,
> - fb_offset_32 >> (OSD_SRCADD_ADD_SFT -
> - OSD_VIDWINADH_V0AH_SHIFT),
> - OSD_VIDWINADH);
> - osd_write(sd, fb_offset_32 & OSD_VIDWIN0ADL_V0AL,
> - OSD_VIDWIN0ADL);
> - break;
> - case WIN_OSD1:
> - osd_modify(sd, OSD_OSDWINADH_O1AH,
> - fb_offset_32 >> (OSD_SRCADD_ADD_SFT -
> - OSD_OSDWINADH_O1AH_SHIFT),
> - OSD_OSDWINADH);
> - osd_write(sd, fb_offset_32 & OSD_OSDWIN1ADL_O1AL,
> - OSD_OSDWIN1ADL);
> - break;
> - case WIN_VID1:
> - osd_modify(sd, OSD_VIDWINADH_V1AH,
> - fb_offset_32 >> (OSD_SRCADD_ADD_SFT -
> - OSD_VIDWINADH_V1AH_SHIFT),
> - OSD_VIDWINADH);
> - osd_write(sd, fb_offset_32 & OSD_VIDWIN1ADL_V1AL,
> - OSD_VIDWIN1ADL);
> - break;
> - }
> - } else if (sd->vpbe_type == VPBE_VERSION_2) {
> - struct osd_window_state *win = &sd->win[layer];
> - unsigned long fb_offset_32, cbcr_offset_32;
> -
> - fb_offset_32 = fb_base_phys - VPBE_REG_BASE;
> - if (cbcr_ofst)
> - cbcr_offset_32 = cbcr_ofst;
> - else
> - cbcr_offset_32 = win->lconfig.line_length *
> - win->lconfig.ysize;
> - cbcr_offset_32 += fb_offset_32;
> - fb_offset_32 = fb_offset_32 >> 5;
> - cbcr_offset_32 = cbcr_offset_32 >> 5;
> - /*
> - * DM365: start address is 27-bit long address b26 - b23 are
> - * in offset register b12 - b9, and * bit 26 has to be '1'
> - */
> - if (win->lconfig.pixfmt == PIXFMT_NV12) {
> - switch (layer) {
> - case WIN_VID0:
> - case WIN_VID1:
> - /* Y is in VID0 */
> - osd_modify(sd, OSD_VIDWIN0OFST_V0AH,
> - ((fb_offset_32 & OSD_SRC_ADDR_HIGH4) >>
> - (OSD_SRCADD_OFSET_SFT -
> - OSD_WINOFST_AH_SHIFT)) |
> - OSD_WINOFST_MASK, OSD_VIDWIN0OFST);
> - osd_modify(sd, OSD_VIDWINADH_V0AH,
> - (fb_offset_32 & OSD_SRC_ADDR_HIGH7) >>
> - (OSD_SRCADD_ADD_SFT -
> - OSD_VIDWINADH_V0AH_SHIFT),
> - OSD_VIDWINADH);
> - osd_write(sd, fb_offset_32 & OSD_WINADL_MASK,
> - OSD_VIDWIN0ADL);
> - /* CbCr is in VID1 */
> - osd_modify(sd, OSD_VIDWIN1OFST_V1AH,
> - ((cbcr_offset_32 &
> - OSD_SRC_ADDR_HIGH4) >>
> - (OSD_SRCADD_OFSET_SFT -
> - OSD_WINOFST_AH_SHIFT)) |
> - OSD_WINOFST_MASK, OSD_VIDWIN1OFST);
> - osd_modify(sd, OSD_VIDWINADH_V1AH,
> - (cbcr_offset_32 &
> - OSD_SRC_ADDR_HIGH7) >>
> - (OSD_SRCADD_ADD_SFT -
> - OSD_VIDWINADH_V1AH_SHIFT),
> - OSD_VIDWINADH);
> - osd_write(sd, cbcr_offset_32 & OSD_WINADL_MASK,
> - OSD_VIDWIN1ADL);
> - break;
> - default:
> - break;
> - }
> - }
> -
> - switch (layer) {
> - case WIN_OSD0:
> - osd_modify(sd, OSD_OSDWIN0OFST_O0AH,
> - ((fb_offset_32 & OSD_SRC_ADDR_HIGH4) >>
> - (OSD_SRCADD_OFSET_SFT -
> - OSD_WINOFST_AH_SHIFT)) | OSD_WINOFST_MASK,
> - OSD_OSDWIN0OFST);
> - osd_modify(sd, OSD_OSDWINADH_O0AH,
> - (fb_offset_32 & OSD_SRC_ADDR_HIGH7) >>
> - (OSD_SRCADD_ADD_SFT -
> - OSD_OSDWINADH_O0AH_SHIFT), OSD_OSDWINADH);
> - osd_write(sd, fb_offset_32 & OSD_WINADL_MASK,
> - OSD_OSDWIN0ADL);
> - break;
> - case WIN_VID0:
> - if (win->lconfig.pixfmt != PIXFMT_NV12) {
> - osd_modify(sd, OSD_VIDWIN0OFST_V0AH,
> - ((fb_offset_32 & OSD_SRC_ADDR_HIGH4) >>
> - (OSD_SRCADD_OFSET_SFT -
> - OSD_WINOFST_AH_SHIFT)) |
> - OSD_WINOFST_MASK, OSD_VIDWIN0OFST);
> - osd_modify(sd, OSD_VIDWINADH_V0AH,
> - (fb_offset_32 & OSD_SRC_ADDR_HIGH7) >>
> - (OSD_SRCADD_ADD_SFT -
> - OSD_VIDWINADH_V0AH_SHIFT),
> - OSD_VIDWINADH);
> - osd_write(sd, fb_offset_32 & OSD_WINADL_MASK,
> - OSD_VIDWIN0ADL);
> - }
> - break;
> - case WIN_OSD1:
> - osd_modify(sd, OSD_OSDWIN1OFST_O1AH,
> - ((fb_offset_32 & OSD_SRC_ADDR_HIGH4) >>
> - (OSD_SRCADD_OFSET_SFT -
> - OSD_WINOFST_AH_SHIFT)) | OSD_WINOFST_MASK,
> - OSD_OSDWIN1OFST);
> - osd_modify(sd, OSD_OSDWINADH_O1AH,
> - (fb_offset_32 & OSD_SRC_ADDR_HIGH7) >>
> - (OSD_SRCADD_ADD_SFT -
> - OSD_OSDWINADH_O1AH_SHIFT),
> - OSD_OSDWINADH);
> - osd_write(sd, fb_offset_32 & OSD_WINADL_MASK,
> - OSD_OSDWIN1ADL);
> - break;
> - case WIN_VID1:
> - if (win->lconfig.pixfmt != PIXFMT_NV12) {
> - osd_modify(sd, OSD_VIDWIN1OFST_V1AH,
> - ((fb_offset_32 & OSD_SRC_ADDR_HIGH4) >>
> - (OSD_SRCADD_OFSET_SFT -
> - OSD_WINOFST_AH_SHIFT)) |
> - OSD_WINOFST_MASK, OSD_VIDWIN1OFST);
> - osd_modify(sd, OSD_VIDWINADH_V1AH,
> - (fb_offset_32 & OSD_SRC_ADDR_HIGH7) >>
> - (OSD_SRCADD_ADD_SFT -
> - OSD_VIDWINADH_V1AH_SHIFT),
> - OSD_VIDWINADH);
> - osd_write(sd, fb_offset_32 & OSD_WINADL_MASK,
> - OSD_VIDWIN1ADL);
> - }
> - break;
> - }
> - }
> -}
> -
> -static void osd_start_layer(struct osd_state *sd, enum osd_layer layer,
> - unsigned long fb_base_phys,
> - unsigned long cbcr_ofst)
> -{
> - struct osd_state *osd = sd;
> - struct osd_window_state *win = &osd->win[layer];
> - struct osd_layer_config *cfg = &win->lconfig;
> - unsigned long flags;
> -
> - spin_lock_irqsave(&osd->lock, flags);
> -
> - win->fb_base_phys = fb_base_phys & ~0x1F;
> - _osd_start_layer(sd, layer, fb_base_phys, cbcr_ofst);
> -
> - if (layer == WIN_VID0) {
> - osd->pingpong =
> - _osd_dm6446_vid0_pingpong(sd, osd->field_inversion,
> - win->fb_base_phys,
> - cfg);
> - }
> -
> - spin_unlock_irqrestore(&osd->lock, flags);
> -}
> -
> -static void osd_get_layer_config(struct osd_state *sd, enum osd_layer layer,
> - struct osd_layer_config *lconfig)
> -{
> - struct osd_state *osd = sd;
> - struct osd_window_state *win = &osd->win[layer];
> - unsigned long flags;
> -
> - spin_lock_irqsave(&osd->lock, flags);
> -
> - *lconfig = win->lconfig;
> -
> - spin_unlock_irqrestore(&osd->lock, flags);
> -}
> -
> -/**
> - * try_layer_config() - Try a specific configuration for the layer
> - * @sd: ptr to struct osd_state
> - * @layer: layer to configure
> - * @lconfig: layer configuration to try
> - *
> - * If the requested lconfig is completely rejected and the value of lconfig on
> - * exit is the current lconfig, then try_layer_config() returns 1. Otherwise,
> - * try_layer_config() returns 0. A return value of 0 does not necessarily mean
> - * that the value of lconfig on exit is identical to the value of lconfig on
> - * entry, but merely that it represents a change from the current lconfig.
> - */
> -static int try_layer_config(struct osd_state *sd, enum osd_layer layer,
> - struct osd_layer_config *lconfig)
> -{
> - struct osd_state *osd = sd;
> - struct osd_window_state *win = &osd->win[layer];
> - int bad_config = 0;
> -
> - /* verify that the pixel format is compatible with the layer */
> - switch (lconfig->pixfmt) {
> - case PIXFMT_1BPP:
> - case PIXFMT_2BPP:
> - case PIXFMT_4BPP:
> - case PIXFMT_8BPP:
> - case PIXFMT_RGB565:
> - if (osd->vpbe_type == VPBE_VERSION_1)
> - bad_config = !is_vid_win(layer);
> - break;
> - case PIXFMT_YCBCRI:
> - case PIXFMT_YCRCBI:
> - bad_config = !is_vid_win(layer);
> - break;
> - case PIXFMT_RGB888:
> - if (osd->vpbe_type == VPBE_VERSION_1)
> - bad_config = !is_vid_win(layer);
> - else if ((osd->vpbe_type == VPBE_VERSION_3) ||
> - (osd->vpbe_type == VPBE_VERSION_2))
> - bad_config = !is_osd_win(layer);
> - break;
> - case PIXFMT_NV12:
> - if (osd->vpbe_type != VPBE_VERSION_2)
> - bad_config = 1;
> - else
> - bad_config = is_osd_win(layer);
> - break;
> - case PIXFMT_OSD_ATTR:
> - bad_config = (layer != WIN_OSD1);
> - break;
> - default:
> - bad_config = 1;
> - break;
> - }
> - if (bad_config) {
> - /*
> - * The requested pixel format is incompatible with the layer,
> - * so keep the current layer configuration.
> - */
> - *lconfig = win->lconfig;
> - return bad_config;
> - }
> -
> - /* DM6446: */
> - /* only one OSD window at a time can use RGB pixel formats */
> - if ((osd->vpbe_type == VPBE_VERSION_1) &&
> - is_osd_win(layer) && is_rgb_pixfmt(lconfig->pixfmt)) {
> - enum osd_pix_format pixfmt;
> -
> - if (layer == WIN_OSD0)
> - pixfmt = osd->win[WIN_OSD1].lconfig.pixfmt;
> - else
> - pixfmt = osd->win[WIN_OSD0].lconfig.pixfmt;
> -
> - if (is_rgb_pixfmt(pixfmt)) {
> - /*
> - * The other OSD window is already configured for an
> - * RGB, so keep the current layer configuration.
> - */
> - *lconfig = win->lconfig;
> - return 1;
> - }
> - }
> -
> - /* DM6446: only one video window at a time can use RGB888 */
> - if ((osd->vpbe_type == VPBE_VERSION_1) && is_vid_win(layer) &&
> - lconfig->pixfmt == PIXFMT_RGB888) {
> - enum osd_pix_format pixfmt;
> -
> - if (layer == WIN_VID0)
> - pixfmt = osd->win[WIN_VID1].lconfig.pixfmt;
> - else
> - pixfmt = osd->win[WIN_VID0].lconfig.pixfmt;
> -
> - if (pixfmt == PIXFMT_RGB888) {
> - /*
> - * The other video window is already configured for
> - * RGB888, so keep the current layer configuration.
> - */
> - *lconfig = win->lconfig;
> - return 1;
> - }
> - }
> -
> - /* window dimensions must be non-zero */
> - if (!lconfig->line_length || !lconfig->xsize || !lconfig->ysize) {
> - *lconfig = win->lconfig;
> - return 1;
> - }
> -
> - /* round line_length up to a multiple of 32 */
> - lconfig->line_length = ((lconfig->line_length + 31) / 32) * 32;
> - lconfig->line_length =
> - min(lconfig->line_length, (unsigned)MAX_LINE_LENGTH);
> - lconfig->xsize = min(lconfig->xsize, (unsigned)MAX_WIN_SIZE);
> - lconfig->ysize = min(lconfig->ysize, (unsigned)MAX_WIN_SIZE);
> - lconfig->xpos = min(lconfig->xpos, (unsigned)MAX_WIN_SIZE);
> - lconfig->ypos = min(lconfig->ypos, (unsigned)MAX_WIN_SIZE);
> - lconfig->interlaced = (lconfig->interlaced != 0);
> - if (lconfig->interlaced) {
> - /* ysize and ypos must be even for interlaced displays */
> - lconfig->ysize &= ~1;
> - lconfig->ypos &= ~1;
> - }
> -
> - return 0;
> -}
> -
> -static void _osd_disable_vid_rgb888(struct osd_state *sd)
> -{
> - /*
> - * The DM6446 supports RGB888 pixel format in a single video window.
> - * This routine disables RGB888 pixel format for both video windows.
> - * The caller must ensure that neither video window is currently
> - * configured for RGB888 pixel format.
> - */
> - if (sd->vpbe_type == VPBE_VERSION_1)
> - osd_clear(sd, OSD_MISCCTL_RGBEN, OSD_MISCCTL);
> -}
> -
> -static void _osd_enable_vid_rgb888(struct osd_state *sd,
> - enum osd_layer layer)
> -{
> - /*
> - * The DM6446 supports RGB888 pixel format in a single video window.
> - * This routine enables RGB888 pixel format for the specified video
> - * window. The caller must ensure that the other video window is not
> - * currently configured for RGB888 pixel format, as this routine will
> - * disable RGB888 pixel format for the other window.
> - */
> - if (sd->vpbe_type == VPBE_VERSION_1) {
> - if (layer == WIN_VID0)
> - osd_modify(sd, OSD_MISCCTL_RGBEN | OSD_MISCCTL_RGBWIN,
> - OSD_MISCCTL_RGBEN, OSD_MISCCTL);
> - else if (layer == WIN_VID1)
> - osd_modify(sd, OSD_MISCCTL_RGBEN | OSD_MISCCTL_RGBWIN,
> - OSD_MISCCTL_RGBEN | OSD_MISCCTL_RGBWIN,
> - OSD_MISCCTL);
> - }
> -}
> -
> -static void _osd_set_cbcr_order(struct osd_state *sd,
> - enum osd_pix_format pixfmt)
> -{
> - /*
> - * The caller must ensure that all windows using YC pixfmt use the same
> - * Cb/Cr order.
> - */
> - if (pixfmt == PIXFMT_YCBCRI)
> - osd_clear(sd, OSD_MODE_CS, OSD_MODE);
> - else if (pixfmt == PIXFMT_YCRCBI)
> - osd_set(sd, OSD_MODE_CS, OSD_MODE);
> -}
> -
> -static void _osd_set_layer_config(struct osd_state *sd, enum osd_layer layer,
> - const struct osd_layer_config *lconfig)
> -{
> - u32 winmd = 0, winmd_mask = 0, bmw = 0;
> -
> - _osd_set_cbcr_order(sd, lconfig->pixfmt);
> -
> - switch (layer) {
> - case WIN_OSD0:
> - if (sd->vpbe_type == VPBE_VERSION_1) {
> - winmd_mask |= OSD_OSDWIN0MD_RGB0E;
> - if (lconfig->pixfmt == PIXFMT_RGB565)
> - winmd |= OSD_OSDWIN0MD_RGB0E;
> - } else if ((sd->vpbe_type == VPBE_VERSION_3) ||
> - (sd->vpbe_type == VPBE_VERSION_2)) {
> - winmd_mask |= OSD_OSDWIN0MD_BMP0MD;
> - switch (lconfig->pixfmt) {
> - case PIXFMT_RGB565:
> - winmd |= (1 <<
> - OSD_OSDWIN0MD_BMP0MD_SHIFT);
> - break;
> - case PIXFMT_RGB888:
> - winmd |= (2 << OSD_OSDWIN0MD_BMP0MD_SHIFT);
> - _osd_enable_rgb888_pixblend(sd, OSDWIN_OSD0);
> - break;
> - case PIXFMT_YCBCRI:
> - case PIXFMT_YCRCBI:
> - winmd |= (3 << OSD_OSDWIN0MD_BMP0MD_SHIFT);
> - break;
> - default:
> - break;
> - }
> - }
> -
> - winmd_mask |= OSD_OSDWIN0MD_BMW0 | OSD_OSDWIN0MD_OFF0;
> -
> - switch (lconfig->pixfmt) {
> - case PIXFMT_1BPP:
> - bmw = 0;
> - break;
> - case PIXFMT_2BPP:
> - bmw = 1;
> - break;
> - case PIXFMT_4BPP:
> - bmw = 2;
> - break;
> - case PIXFMT_8BPP:
> - bmw = 3;
> - break;
> - default:
> - break;
> - }
> - winmd |= (bmw << OSD_OSDWIN0MD_BMW0_SHIFT);
> -
> - if (lconfig->interlaced)
> - winmd |= OSD_OSDWIN0MD_OFF0;
> -
> - osd_modify(sd, winmd_mask, winmd, OSD_OSDWIN0MD);
> - osd_write(sd, lconfig->line_length >> 5, OSD_OSDWIN0OFST);
> - osd_write(sd, lconfig->xpos, OSD_OSDWIN0XP);
> - osd_write(sd, lconfig->xsize, OSD_OSDWIN0XL);
> - if (lconfig->interlaced) {
> - osd_write(sd, lconfig->ypos >> 1, OSD_OSDWIN0YP);
> - osd_write(sd, lconfig->ysize >> 1, OSD_OSDWIN0YL);
> - } else {
> - osd_write(sd, lconfig->ypos, OSD_OSDWIN0YP);
> - osd_write(sd, lconfig->ysize, OSD_OSDWIN0YL);
> - }
> - break;
> - case WIN_VID0:
> - winmd_mask |= OSD_VIDWINMD_VFF0;
> - if (lconfig->interlaced)
> - winmd |= OSD_VIDWINMD_VFF0;
> -
> - osd_modify(sd, winmd_mask, winmd, OSD_VIDWINMD);
> - osd_write(sd, lconfig->line_length >> 5, OSD_VIDWIN0OFST);
> - osd_write(sd, lconfig->xpos, OSD_VIDWIN0XP);
> - osd_write(sd, lconfig->xsize, OSD_VIDWIN0XL);
> - /*
> - * For YUV420P format the register contents are
> - * duplicated in both VID registers
> - */
> - if ((sd->vpbe_type == VPBE_VERSION_2) &&
> - (lconfig->pixfmt == PIXFMT_NV12)) {
> - /* other window also */
> - if (lconfig->interlaced) {
> - winmd_mask |= OSD_VIDWINMD_VFF1;
> - winmd |= OSD_VIDWINMD_VFF1;
> - osd_modify(sd, winmd_mask, winmd,
> - OSD_VIDWINMD);
> - }
> -
> - osd_modify(sd, OSD_MISCCTL_S420D,
> - OSD_MISCCTL_S420D, OSD_MISCCTL);
> - osd_write(sd, lconfig->line_length >> 5,
> - OSD_VIDWIN1OFST);
> - osd_write(sd, lconfig->xpos, OSD_VIDWIN1XP);
> - osd_write(sd, lconfig->xsize, OSD_VIDWIN1XL);
> - /*
> - * if NV21 pixfmt and line length not 32B
> - * aligned (e.g. NTSC), Need to set window
> - * X pixel size to be 32B aligned as well
> - */
> - if (lconfig->xsize % 32) {
> - osd_write(sd,
> - ((lconfig->xsize + 31) & ~31),
> - OSD_VIDWIN1XL);
> - osd_write(sd,
> - ((lconfig->xsize + 31) & ~31),
> - OSD_VIDWIN0XL);
> - }
> - } else if ((sd->vpbe_type == VPBE_VERSION_2) &&
> - (lconfig->pixfmt != PIXFMT_NV12)) {
> - osd_modify(sd, OSD_MISCCTL_S420D, ~OSD_MISCCTL_S420D,
> - OSD_MISCCTL);
> - }
> -
> - if (lconfig->interlaced) {
> - osd_write(sd, lconfig->ypos >> 1, OSD_VIDWIN0YP);
> - osd_write(sd, lconfig->ysize >> 1, OSD_VIDWIN0YL);
> - if ((sd->vpbe_type == VPBE_VERSION_2) &&
> - lconfig->pixfmt == PIXFMT_NV12) {
> - osd_write(sd, lconfig->ypos >> 1,
> - OSD_VIDWIN1YP);
> - osd_write(sd, lconfig->ysize >> 1,
> - OSD_VIDWIN1YL);
> - }
> - } else {
> - osd_write(sd, lconfig->ypos, OSD_VIDWIN0YP);
> - osd_write(sd, lconfig->ysize, OSD_VIDWIN0YL);
> - if ((sd->vpbe_type == VPBE_VERSION_2) &&
> - lconfig->pixfmt == PIXFMT_NV12) {
> - osd_write(sd, lconfig->ypos, OSD_VIDWIN1YP);
> - osd_write(sd, lconfig->ysize, OSD_VIDWIN1YL);
> - }
> - }
> - break;
> - case WIN_OSD1:
> - /*
> - * The caller must ensure that OSD1 is disabled prior to
> - * switching from a normal mode to attribute mode or from
> - * attribute mode to a normal mode.
> - */
> - if (lconfig->pixfmt == PIXFMT_OSD_ATTR) {
> - if (sd->vpbe_type == VPBE_VERSION_1) {
> - winmd_mask |= OSD_OSDWIN1MD_ATN1E |
> - OSD_OSDWIN1MD_RGB1E | OSD_OSDWIN1MD_CLUTS1 |
> - OSD_OSDWIN1MD_BLND1 | OSD_OSDWIN1MD_TE1;
> - } else {
> - winmd_mask |= OSD_OSDWIN1MD_BMP1MD |
> - OSD_OSDWIN1MD_CLUTS1 | OSD_OSDWIN1MD_BLND1 |
> - OSD_OSDWIN1MD_TE1;
> - }
> - } else {
> - if (sd->vpbe_type == VPBE_VERSION_1) {
> - winmd_mask |= OSD_OSDWIN1MD_RGB1E;
> - if (lconfig->pixfmt == PIXFMT_RGB565)
> - winmd |= OSD_OSDWIN1MD_RGB1E;
> - } else if ((sd->vpbe_type == VPBE_VERSION_3)
> - || (sd->vpbe_type == VPBE_VERSION_2)) {
> - winmd_mask |= OSD_OSDWIN1MD_BMP1MD;
> - switch (lconfig->pixfmt) {
> - case PIXFMT_RGB565:
> - winmd |=
> - (1 << OSD_OSDWIN1MD_BMP1MD_SHIFT);
> - break;
> - case PIXFMT_RGB888:
> - winmd |=
> - (2 << OSD_OSDWIN1MD_BMP1MD_SHIFT);
> - _osd_enable_rgb888_pixblend(sd,
> - OSDWIN_OSD1);
> - break;
> - case PIXFMT_YCBCRI:
> - case PIXFMT_YCRCBI:
> - winmd |=
> - (3 << OSD_OSDWIN1MD_BMP1MD_SHIFT);
> - break;
> - default:
> - break;
> - }
> - }
> -
> - winmd_mask |= OSD_OSDWIN1MD_BMW1;
> - switch (lconfig->pixfmt) {
> - case PIXFMT_1BPP:
> - bmw = 0;
> - break;
> - case PIXFMT_2BPP:
> - bmw = 1;
> - break;
> - case PIXFMT_4BPP:
> - bmw = 2;
> - break;
> - case PIXFMT_8BPP:
> - bmw = 3;
> - break;
> - default:
> - break;
> - }
> - winmd |= (bmw << OSD_OSDWIN1MD_BMW1_SHIFT);
> - }
> -
> - winmd_mask |= OSD_OSDWIN1MD_OFF1;
> - if (lconfig->interlaced)
> - winmd |= OSD_OSDWIN1MD_OFF1;
> -
> - osd_modify(sd, winmd_mask, winmd, OSD_OSDWIN1MD);
> - osd_write(sd, lconfig->line_length >> 5, OSD_OSDWIN1OFST);
> - osd_write(sd, lconfig->xpos, OSD_OSDWIN1XP);
> - osd_write(sd, lconfig->xsize, OSD_OSDWIN1XL);
> - if (lconfig->interlaced) {
> - osd_write(sd, lconfig->ypos >> 1, OSD_OSDWIN1YP);
> - osd_write(sd, lconfig->ysize >> 1, OSD_OSDWIN1YL);
> - } else {
> - osd_write(sd, lconfig->ypos, OSD_OSDWIN1YP);
> - osd_write(sd, lconfig->ysize, OSD_OSDWIN1YL);
> - }
> - break;
> - case WIN_VID1:
> - winmd_mask |= OSD_VIDWINMD_VFF1;
> - if (lconfig->interlaced)
> - winmd |= OSD_VIDWINMD_VFF1;
> -
> - osd_modify(sd, winmd_mask, winmd, OSD_VIDWINMD);
> - osd_write(sd, lconfig->line_length >> 5, OSD_VIDWIN1OFST);
> - osd_write(sd, lconfig->xpos, OSD_VIDWIN1XP);
> - osd_write(sd, lconfig->xsize, OSD_VIDWIN1XL);
> - /*
> - * For YUV420P format the register contents are
> - * duplicated in both VID registers
> - */
> - if (sd->vpbe_type == VPBE_VERSION_2) {
> - if (lconfig->pixfmt == PIXFMT_NV12) {
> - /* other window also */
> - if (lconfig->interlaced) {
> - winmd_mask |= OSD_VIDWINMD_VFF0;
> - winmd |= OSD_VIDWINMD_VFF0;
> - osd_modify(sd, winmd_mask, winmd,
> - OSD_VIDWINMD);
> - }
> - osd_modify(sd, OSD_MISCCTL_S420D,
> - OSD_MISCCTL_S420D, OSD_MISCCTL);
> - osd_write(sd, lconfig->line_length >> 5,
> - OSD_VIDWIN0OFST);
> - osd_write(sd, lconfig->xpos, OSD_VIDWIN0XP);
> - osd_write(sd, lconfig->xsize, OSD_VIDWIN0XL);
> - } else {
> - osd_modify(sd, OSD_MISCCTL_S420D,
> - ~OSD_MISCCTL_S420D, OSD_MISCCTL);
> - }
> - }
> -
> - if (lconfig->interlaced) {
> - osd_write(sd, lconfig->ypos >> 1, OSD_VIDWIN1YP);
> - osd_write(sd, lconfig->ysize >> 1, OSD_VIDWIN1YL);
> - if ((sd->vpbe_type == VPBE_VERSION_2) &&
> - lconfig->pixfmt == PIXFMT_NV12) {
> - osd_write(sd, lconfig->ypos >> 1,
> - OSD_VIDWIN0YP);
> - osd_write(sd, lconfig->ysize >> 1,
> - OSD_VIDWIN0YL);
> - }
> - } else {
> - osd_write(sd, lconfig->ypos, OSD_VIDWIN1YP);
> - osd_write(sd, lconfig->ysize, OSD_VIDWIN1YL);
> - if ((sd->vpbe_type == VPBE_VERSION_2) &&
> - lconfig->pixfmt == PIXFMT_NV12) {
> - osd_write(sd, lconfig->ypos, OSD_VIDWIN0YP);
> - osd_write(sd, lconfig->ysize, OSD_VIDWIN0YL);
> - }
> - }
> - break;
> - }
> -}
> -
> -static int osd_set_layer_config(struct osd_state *sd, enum osd_layer layer,
> - struct osd_layer_config *lconfig)
> -{
> - struct osd_state *osd = sd;
> - struct osd_window_state *win = &osd->win[layer];
> - struct osd_layer_config *cfg = &win->lconfig;
> - unsigned long flags;
> - int reject_config;
> -
> - spin_lock_irqsave(&osd->lock, flags);
> -
> - reject_config = try_layer_config(sd, layer, lconfig);
> - if (reject_config) {
> - spin_unlock_irqrestore(&osd->lock, flags);
> - return reject_config;
> - }
> -
> - /* update the current Cb/Cr order */
> - if (is_yc_pixfmt(lconfig->pixfmt))
> - osd->yc_pixfmt = lconfig->pixfmt;
> -
> - /*
> - * If we are switching OSD1 from normal mode to attribute mode or from
> - * attribute mode to normal mode, then we must disable the window.
> - */
> - if (layer == WIN_OSD1) {
> - if (((lconfig->pixfmt == PIXFMT_OSD_ATTR) &&
> - (cfg->pixfmt != PIXFMT_OSD_ATTR)) ||
> - ((lconfig->pixfmt != PIXFMT_OSD_ATTR) &&
> - (cfg->pixfmt == PIXFMT_OSD_ATTR))) {
> - win->is_enabled = 0;
> - _osd_disable_layer(sd, layer);
> - }
> - }
> -
> - _osd_set_layer_config(sd, layer, lconfig);
> -
> - if (layer == WIN_OSD1) {
> - struct osd_osdwin_state *osdwin_state =
> - &osd->osdwin[OSDWIN_OSD1];
> -
> - if ((lconfig->pixfmt != PIXFMT_OSD_ATTR) &&
> - (cfg->pixfmt == PIXFMT_OSD_ATTR)) {
> - /*
> - * We just switched OSD1 from attribute mode to normal
> - * mode, so we must initialize the CLUT select, the
> - * blend factor, transparency colorkey enable, and
> - * attenuation enable (DM6446 only) bits in the
> - * OSDWIN1MD register.
> - */
> - _osd_set_osd_clut(sd, OSDWIN_OSD1,
> - osdwin_state->clut);
> - _osd_set_blending_factor(sd, OSDWIN_OSD1,
> - osdwin_state->blend);
> - if (osdwin_state->colorkey_blending) {
> - _osd_enable_color_key(sd, OSDWIN_OSD1,
> - osdwin_state->
> - colorkey,
> - lconfig->pixfmt);
> - } else
> - _osd_disable_color_key(sd, OSDWIN_OSD1);
> - _osd_set_rec601_attenuation(sd, OSDWIN_OSD1,
> - osdwin_state->
> - rec601_attenuation);
> - } else if ((lconfig->pixfmt == PIXFMT_OSD_ATTR) &&
> - (cfg->pixfmt != PIXFMT_OSD_ATTR)) {
> - /*
> - * We just switched OSD1 from normal mode to attribute
> - * mode, so we must initialize the blink enable and
> - * blink interval bits in the OSDATRMD register.
> - */
> - _osd_set_blink_attribute(sd, osd->is_blinking,
> - osd->blink);
> - }
> - }
> -
> - /*
> - * If we just switched to a 1-, 2-, or 4-bits-per-pixel bitmap format
> - * then configure a default palette map.
> - */
> - if ((lconfig->pixfmt != cfg->pixfmt) &&
> - ((lconfig->pixfmt == PIXFMT_1BPP) ||
> - (lconfig->pixfmt == PIXFMT_2BPP) ||
> - (lconfig->pixfmt == PIXFMT_4BPP))) {
> - enum osd_win_layer osdwin =
> - ((layer == WIN_OSD0) ? OSDWIN_OSD0 : OSDWIN_OSD1);
> - struct osd_osdwin_state *osdwin_state =
> - &osd->osdwin[osdwin];
> - unsigned char clut_index;
> - unsigned char clut_entries = 0;
> -
> - switch (lconfig->pixfmt) {
> - case PIXFMT_1BPP:
> - clut_entries = 2;
> - break;
> - case PIXFMT_2BPP:
> - clut_entries = 4;
> - break;
> - case PIXFMT_4BPP:
> - clut_entries = 16;
> - break;
> - default:
> - break;
> - }
> - /*
> - * The default palette map maps the pixel value to the clut
> - * index, i.e. pixel value 0 maps to clut entry 0, pixel value
> - * 1 maps to clut entry 1, etc.
> - */
> - for (clut_index = 0; clut_index < 16; clut_index++) {
> - osdwin_state->palette_map[clut_index] = clut_index;
> - if (clut_index < clut_entries) {
> - _osd_set_palette_map(sd, osdwin, clut_index,
> - clut_index,
> - lconfig->pixfmt);
> - }
> - }
> - }
> -
> - *cfg = *lconfig;
> - /* DM6446: configure the RGB888 enable and window selection */
> - if (osd->win[WIN_VID0].lconfig.pixfmt == PIXFMT_RGB888)
> - _osd_enable_vid_rgb888(sd, WIN_VID0);
> - else if (osd->win[WIN_VID1].lconfig.pixfmt == PIXFMT_RGB888)
> - _osd_enable_vid_rgb888(sd, WIN_VID1);
> - else
> - _osd_disable_vid_rgb888(sd);
> -
> - if (layer == WIN_VID0) {
> - osd->pingpong =
> - _osd_dm6446_vid0_pingpong(sd, osd->field_inversion,
> - win->fb_base_phys,
> - cfg);
> - }
> -
> - spin_unlock_irqrestore(&osd->lock, flags);
> -
> - return 0;
> -}
> -
> -static void osd_init_layer(struct osd_state *sd, enum osd_layer layer)
> -{
> - struct osd_state *osd = sd;
> - struct osd_window_state *win = &osd->win[layer];
> - enum osd_win_layer osdwin;
> - struct osd_osdwin_state *osdwin_state;
> - struct osd_layer_config *cfg = &win->lconfig;
> - unsigned long flags;
> -
> - spin_lock_irqsave(&osd->lock, flags);
> -
> - win->is_enabled = 0;
> - _osd_disable_layer(sd, layer);
> -
> - win->h_zoom = ZOOM_X1;
> - win->v_zoom = ZOOM_X1;
> - _osd_set_zoom(sd, layer, win->h_zoom, win->v_zoom);
> -
> - win->fb_base_phys = 0;
> - _osd_start_layer(sd, layer, win->fb_base_phys, 0);
> -
> - cfg->line_length = 0;
> - cfg->xsize = 0;
> - cfg->ysize = 0;
> - cfg->xpos = 0;
> - cfg->ypos = 0;
> - cfg->interlaced = 0;
> - switch (layer) {
> - case WIN_OSD0:
> - case WIN_OSD1:
> - osdwin = (layer == WIN_OSD0) ? OSDWIN_OSD0 : OSDWIN_OSD1;
> - osdwin_state = &osd->osdwin[osdwin];
> - /*
> - * Other code relies on the fact that OSD windows default to a
> - * bitmap pixel format when they are deallocated, so don't
> - * change this default pixel format.
> - */
> - cfg->pixfmt = PIXFMT_8BPP;
> - _osd_set_layer_config(sd, layer, cfg);
> - osdwin_state->clut = RAM_CLUT;
> - _osd_set_osd_clut(sd, osdwin, osdwin_state->clut);
> - osdwin_state->colorkey_blending = 0;
> - _osd_disable_color_key(sd, osdwin);
> - osdwin_state->blend = OSD_8_VID_0;
> - _osd_set_blending_factor(sd, osdwin, osdwin_state->blend);
> - osdwin_state->rec601_attenuation = 0;
> - _osd_set_rec601_attenuation(sd, osdwin,
> - osdwin_state->
> - rec601_attenuation);
> - if (osdwin == OSDWIN_OSD1) {
> - osd->is_blinking = 0;
> - osd->blink = BLINK_X1;
> - }
> - break;
> - case WIN_VID0:
> - case WIN_VID1:
> - cfg->pixfmt = osd->yc_pixfmt;
> - _osd_set_layer_config(sd, layer, cfg);
> - break;
> - }
> -
> - spin_unlock_irqrestore(&osd->lock, flags);
> -}
> -
> -static void osd_release_layer(struct osd_state *sd, enum osd_layer layer)
> -{
> - struct osd_state *osd = sd;
> - struct osd_window_state *win = &osd->win[layer];
> - unsigned long flags;
> -
> - spin_lock_irqsave(&osd->lock, flags);
> -
> - if (!win->is_allocated) {
> - spin_unlock_irqrestore(&osd->lock, flags);
> - return;
> - }
> -
> - spin_unlock_irqrestore(&osd->lock, flags);
> - osd_init_layer(sd, layer);
> - spin_lock_irqsave(&osd->lock, flags);
> -
> - win->is_allocated = 0;
> -
> - spin_unlock_irqrestore(&osd->lock, flags);
> -}
> -
> -static int osd_request_layer(struct osd_state *sd, enum osd_layer layer)
> -{
> - struct osd_state *osd = sd;
> - struct osd_window_state *win = &osd->win[layer];
> - unsigned long flags;
> -
> - spin_lock_irqsave(&osd->lock, flags);
> -
> - if (win->is_allocated) {
> - spin_unlock_irqrestore(&osd->lock, flags);
> - return -1;
> - }
> - win->is_allocated = 1;
> -
> - spin_unlock_irqrestore(&osd->lock, flags);
> -
> - return 0;
> -}
> -
> -static void _osd_init(struct osd_state *sd)
> -{
> - osd_write(sd, 0, OSD_MODE);
> - osd_write(sd, 0, OSD_VIDWINMD);
> - osd_write(sd, 0, OSD_OSDWIN0MD);
> - osd_write(sd, 0, OSD_OSDWIN1MD);
> - osd_write(sd, 0, OSD_RECTCUR);
> - osd_write(sd, 0, OSD_MISCCTL);
> - if (sd->vpbe_type == VPBE_VERSION_3) {
> - osd_write(sd, 0, OSD_VBNDRY);
> - osd_write(sd, 0, OSD_EXTMODE);
> - osd_write(sd, OSD_MISCCTL_DMANG, OSD_MISCCTL);
> - }
> -}
> -
> -static void osd_set_left_margin(struct osd_state *sd, u32 val)
> -{
> - osd_write(sd, val, OSD_BASEPX);
> -}
> -
> -static void osd_set_top_margin(struct osd_state *sd, u32 val)
> -{
> - osd_write(sd, val, OSD_BASEPY);
> -}
> -
> -static int osd_initialize(struct osd_state *osd)
> -{
> - if (osd == NULL)
> - return -ENODEV;
> - _osd_init(osd);
> -
> - /* set default Cb/Cr order */
> - osd->yc_pixfmt = PIXFMT_YCBCRI;
> -
> - if (osd->vpbe_type == VPBE_VERSION_3) {
> - /*
> - * ROM CLUT1 on the DM355 is similar (identical?) to ROM CLUT0
> - * on the DM6446, so make ROM_CLUT1 the default on the DM355.
> - */
> - osd->rom_clut = ROM_CLUT1;
> - }
> -
> - _osd_set_field_inversion(osd, osd->field_inversion);
> - _osd_set_rom_clut(osd, osd->rom_clut);
> -
> - osd_init_layer(osd, WIN_OSD0);
> - osd_init_layer(osd, WIN_VID0);
> - osd_init_layer(osd, WIN_OSD1);
> - osd_init_layer(osd, WIN_VID1);
> -
> - return 0;
> -}
> -
> -static const struct vpbe_osd_ops osd_ops = {
> - .initialize = osd_initialize,
> - .request_layer = osd_request_layer,
> - .release_layer = osd_release_layer,
> - .enable_layer = osd_enable_layer,
> - .disable_layer = osd_disable_layer,
> - .set_layer_config = osd_set_layer_config,
> - .get_layer_config = osd_get_layer_config,
> - .start_layer = osd_start_layer,
> - .set_left_margin = osd_set_left_margin,
> - .set_top_margin = osd_set_top_margin,
> -};
> -
> -static int osd_probe(struct platform_device *pdev)
> -{
> - const struct platform_device_id *pdev_id;
> - struct osd_state *osd;
> - struct resource *res;
> -
> - pdev_id = platform_get_device_id(pdev);
> - if (!pdev_id)
> - return -EINVAL;
> -
> - osd = devm_kzalloc(&pdev->dev, sizeof(struct osd_state), GFP_KERNEL);
> - if (osd == NULL)
> - return -ENOMEM;
> -
> -
> - osd->dev = &pdev->dev;
> - osd->vpbe_type = pdev_id->driver_data;
> -
> - res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> - osd->osd_base = devm_ioremap_resource(&pdev->dev, res);
> - if (IS_ERR(osd->osd_base))
> - return PTR_ERR(osd->osd_base);
> -
> - osd->osd_base_phys = res->start;
> - osd->osd_size = resource_size(res);
> - spin_lock_init(&osd->lock);
> - osd->ops = osd_ops;
> - platform_set_drvdata(pdev, osd);
> - dev_notice(osd->dev, "OSD sub device probe success\n");
> -
> - return 0;
> -}
> -
> -static int osd_remove(struct platform_device *pdev)
> -{
> - return 0;
> -}
> -
> -static struct platform_driver osd_driver = {
> - .probe = osd_probe,
> - .remove = osd_remove,
> - .driver = {
> - .name = MODULE_NAME,
> - },
> - .id_table = vpbe_osd_devtype
> -};
> -
> -module_platform_driver(osd_driver);
> -
> -MODULE_LICENSE("GPL");
> -MODULE_DESCRIPTION("DaVinci OSD Manager Driver");
> -MODULE_AUTHOR("Texas Instruments");
> diff --git a/drivers/media/platform/ti/davinci/vpbe_osd_regs.h b/drivers/media/platform/ti/davinci/vpbe_osd_regs.h
> deleted file mode 100644
> index cecd5991d4c5..000000000000
> --- a/drivers/media/platform/ti/davinci/vpbe_osd_regs.h
> +++ /dev/null
> @@ -1,352 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * Copyright (C) 2006-2010 Texas Instruments Inc
> - */
> -#ifndef _VPBE_OSD_REGS_H
> -#define _VPBE_OSD_REGS_H
> -
> -/* VPBE Global Registers */
> -#define VPBE_PID 0x0
> -#define VPBE_PCR 0x4
> -
> -/* VPSS CLock Registers */
> -#define VPSSCLK_PID 0x00
> -#define VPSSCLK_CLKCTRL 0x04
> -
> -/* VPSS Buffer Logic Registers */
> -#define VPSSBL_PID 0x00
> -#define VPSSBL_PCR 0x04
> -#define VPSSBL_BCR 0x08
> -#define VPSSBL_INTSTAT 0x0C
> -#define VPSSBL_INTSEL 0x10
> -#define VPSSBL_EVTSEL 0x14
> -#define VPSSBL_MEMCTRL 0x18
> -#define VPSSBL_CCDCMUX 0x1C
> -
> -/* DM365 ISP5 system configuration */
> -#define ISP5_PID 0x0
> -#define ISP5_PCCR 0x4
> -#define ISP5_BCR 0x8
> -#define ISP5_INTSTAT 0xC
> -#define ISP5_INTSEL1 0x10
> -#define ISP5_INTSEL2 0x14
> -#define ISP5_INTSEL3 0x18
> -#define ISP5_EVTSEL 0x1c
> -#define ISP5_CCDCMUX 0x20
> -
> -/* VPBE On-Screen Display Subsystem Registers (OSD) */
> -#define OSD_MODE 0x00
> -#define OSD_VIDWINMD 0x04
> -#define OSD_OSDWIN0MD 0x08
> -#define OSD_OSDWIN1MD 0x0C
> -#define OSD_OSDATRMD 0x0C
> -#define OSD_RECTCUR 0x10
> -#define OSD_VIDWIN0OFST 0x18
> -#define OSD_VIDWIN1OFST 0x1C
> -#define OSD_OSDWIN0OFST 0x20
> -#define OSD_OSDWIN1OFST 0x24
> -#define OSD_VIDWINADH 0x28
> -#define OSD_VIDWIN0ADL 0x2C
> -#define OSD_VIDWIN0ADR 0x2C
> -#define OSD_VIDWIN1ADL 0x30
> -#define OSD_VIDWIN1ADR 0x30
> -#define OSD_OSDWINADH 0x34
> -#define OSD_OSDWIN0ADL 0x38
> -#define OSD_OSDWIN0ADR 0x38
> -#define OSD_OSDWIN1ADL 0x3C
> -#define OSD_OSDWIN1ADR 0x3C
> -#define OSD_BASEPX 0x40
> -#define OSD_BASEPY 0x44
> -#define OSD_VIDWIN0XP 0x48
> -#define OSD_VIDWIN0YP 0x4C
> -#define OSD_VIDWIN0XL 0x50
> -#define OSD_VIDWIN0YL 0x54
> -#define OSD_VIDWIN1XP 0x58
> -#define OSD_VIDWIN1YP 0x5C
> -#define OSD_VIDWIN1XL 0x60
> -#define OSD_VIDWIN1YL 0x64
> -#define OSD_OSDWIN0XP 0x68
> -#define OSD_OSDWIN0YP 0x6C
> -#define OSD_OSDWIN0XL 0x70
> -#define OSD_OSDWIN0YL 0x74
> -#define OSD_OSDWIN1XP 0x78
> -#define OSD_OSDWIN1YP 0x7C
> -#define OSD_OSDWIN1XL 0x80
> -#define OSD_OSDWIN1YL 0x84
> -#define OSD_CURXP 0x88
> -#define OSD_CURYP 0x8C
> -#define OSD_CURXL 0x90
> -#define OSD_CURYL 0x94
> -#define OSD_W0BMP01 0xA0
> -#define OSD_W0BMP23 0xA4
> -#define OSD_W0BMP45 0xA8
> -#define OSD_W0BMP67 0xAC
> -#define OSD_W0BMP89 0xB0
> -#define OSD_W0BMPAB 0xB4
> -#define OSD_W0BMPCD 0xB8
> -#define OSD_W0BMPEF 0xBC
> -#define OSD_W1BMP01 0xC0
> -#define OSD_W1BMP23 0xC4
> -#define OSD_W1BMP45 0xC8
> -#define OSD_W1BMP67 0xCC
> -#define OSD_W1BMP89 0xD0
> -#define OSD_W1BMPAB 0xD4
> -#define OSD_W1BMPCD 0xD8
> -#define OSD_W1BMPEF 0xDC
> -#define OSD_VBNDRY 0xE0
> -#define OSD_EXTMODE 0xE4
> -#define OSD_MISCCTL 0xE8
> -#define OSD_CLUTRAMYCB 0xEC
> -#define OSD_CLUTRAMCR 0xF0
> -#define OSD_TRANSPVAL 0xF4
> -#define OSD_TRANSPVALL 0xF4
> -#define OSD_TRANSPVALU 0xF8
> -#define OSD_TRANSPBMPIDX 0xFC
> -#define OSD_PPVWIN0ADR 0xFC
> -
> -/* bit definitions */
> -#define VPBE_PCR_VENC_DIV (1 << 1)
> -#define VPBE_PCR_CLK_OFF (1 << 0)
> -
> -#define VPSSBL_INTSTAT_HSSIINT (1 << 14)
> -#define VPSSBL_INTSTAT_CFALDINT (1 << 13)
> -#define VPSSBL_INTSTAT_IPIPE_INT5 (1 << 12)
> -#define VPSSBL_INTSTAT_IPIPE_INT4 (1 << 11)
> -#define VPSSBL_INTSTAT_IPIPE_INT3 (1 << 10)
> -#define VPSSBL_INTSTAT_IPIPE_INT2 (1 << 9)
> -#define VPSSBL_INTSTAT_IPIPE_INT1 (1 << 8)
> -#define VPSSBL_INTSTAT_IPIPE_INT0 (1 << 7)
> -#define VPSSBL_INTSTAT_IPIPEIFINT (1 << 6)
> -#define VPSSBL_INTSTAT_OSDINT (1 << 5)
> -#define VPSSBL_INTSTAT_VENCINT (1 << 4)
> -#define VPSSBL_INTSTAT_H3AINT (1 << 3)
> -#define VPSSBL_INTSTAT_CCDC_VDINT2 (1 << 2)
> -#define VPSSBL_INTSTAT_CCDC_VDINT1 (1 << 1)
> -#define VPSSBL_INTSTAT_CCDC_VDINT0 (1 << 0)
> -
> -/* DM365 ISP5 bit definitions */
> -#define ISP5_INTSTAT_VENCINT (1 << 21)
> -#define ISP5_INTSTAT_OSDINT (1 << 20)
> -
> -/* VMOD TVTYP options for HDMD=0 */
> -#define SDTV_NTSC 0
> -#define SDTV_PAL 1
> -/* VMOD TVTYP options for HDMD=1 */
> -#define HDTV_525P 0
> -#define HDTV_625P 1
> -#define HDTV_1080I 2
> -#define HDTV_720P 3
> -
> -#define OSD_MODE_CS (1 << 15)
> -#define OSD_MODE_OVRSZ (1 << 14)
> -#define OSD_MODE_OHRSZ (1 << 13)
> -#define OSD_MODE_EF (1 << 12)
> -#define OSD_MODE_VVRSZ (1 << 11)
> -#define OSD_MODE_VHRSZ (1 << 10)
> -#define OSD_MODE_FSINV (1 << 9)
> -#define OSD_MODE_BCLUT (1 << 8)
> -#define OSD_MODE_CABG_SHIFT 0
> -#define OSD_MODE_CABG (0xff << 0)
> -
> -#define OSD_VIDWINMD_VFINV (1 << 15)
> -#define OSD_VIDWINMD_V1EFC (1 << 14)
> -#define OSD_VIDWINMD_VHZ1_SHIFT 12
> -#define OSD_VIDWINMD_VHZ1 (3 << 12)
> -#define OSD_VIDWINMD_VVZ1_SHIFT 10
> -#define OSD_VIDWINMD_VVZ1 (3 << 10)
> -#define OSD_VIDWINMD_VFF1 (1 << 9)
> -#define OSD_VIDWINMD_ACT1 (1 << 8)
> -#define OSD_VIDWINMD_V0EFC (1 << 6)
> -#define OSD_VIDWINMD_VHZ0_SHIFT 4
> -#define OSD_VIDWINMD_VHZ0 (3 << 4)
> -#define OSD_VIDWINMD_VVZ0_SHIFT 2
> -#define OSD_VIDWINMD_VVZ0 (3 << 2)
> -#define OSD_VIDWINMD_VFF0 (1 << 1)
> -#define OSD_VIDWINMD_ACT0 (1 << 0)
> -
> -#define OSD_OSDWIN0MD_ATN0E (1 << 14)
> -#define OSD_OSDWIN0MD_RGB0E (1 << 13)
> -#define OSD_OSDWIN0MD_BMP0MD_SHIFT 13
> -#define OSD_OSDWIN0MD_BMP0MD (3 << 13)
> -#define OSD_OSDWIN0MD_CLUTS0 (1 << 12)
> -#define OSD_OSDWIN0MD_OHZ0_SHIFT 10
> -#define OSD_OSDWIN0MD_OHZ0 (3 << 10)
> -#define OSD_OSDWIN0MD_OVZ0_SHIFT 8
> -#define OSD_OSDWIN0MD_OVZ0 (3 << 8)
> -#define OSD_OSDWIN0MD_BMW0_SHIFT 6
> -#define OSD_OSDWIN0MD_BMW0 (3 << 6)
> -#define OSD_OSDWIN0MD_BLND0_SHIFT 3
> -#define OSD_OSDWIN0MD_BLND0 (7 << 3)
> -#define OSD_OSDWIN0MD_TE0 (1 << 2)
> -#define OSD_OSDWIN0MD_OFF0 (1 << 1)
> -#define OSD_OSDWIN0MD_OACT0 (1 << 0)
> -
> -#define OSD_OSDWIN1MD_OASW (1 << 15)
> -#define OSD_OSDWIN1MD_ATN1E (1 << 14)
> -#define OSD_OSDWIN1MD_RGB1E (1 << 13)
> -#define OSD_OSDWIN1MD_BMP1MD_SHIFT 13
> -#define OSD_OSDWIN1MD_BMP1MD (3 << 13)
> -#define OSD_OSDWIN1MD_CLUTS1 (1 << 12)
> -#define OSD_OSDWIN1MD_OHZ1_SHIFT 10
> -#define OSD_OSDWIN1MD_OHZ1 (3 << 10)
> -#define OSD_OSDWIN1MD_OVZ1_SHIFT 8
> -#define OSD_OSDWIN1MD_OVZ1 (3 << 8)
> -#define OSD_OSDWIN1MD_BMW1_SHIFT 6
> -#define OSD_OSDWIN1MD_BMW1 (3 << 6)
> -#define OSD_OSDWIN1MD_BLND1_SHIFT 3
> -#define OSD_OSDWIN1MD_BLND1 (7 << 3)
> -#define OSD_OSDWIN1MD_TE1 (1 << 2)
> -#define OSD_OSDWIN1MD_OFF1 (1 << 1)
> -#define OSD_OSDWIN1MD_OACT1 (1 << 0)
> -
> -#define OSD_OSDATRMD_OASW (1 << 15)
> -#define OSD_OSDATRMD_OHZA_SHIFT 10
> -#define OSD_OSDATRMD_OHZA (3 << 10)
> -#define OSD_OSDATRMD_OVZA_SHIFT 8
> -#define OSD_OSDATRMD_OVZA (3 << 8)
> -#define OSD_OSDATRMD_BLNKINT_SHIFT 6
> -#define OSD_OSDATRMD_BLNKINT (3 << 6)
> -#define OSD_OSDATRMD_OFFA (1 << 1)
> -#define OSD_OSDATRMD_BLNK (1 << 0)
> -
> -#define OSD_RECTCUR_RCAD_SHIFT 8
> -#define OSD_RECTCUR_RCAD (0xff << 8)
> -#define OSD_RECTCUR_CLUTSR (1 << 7)
> -#define OSD_RECTCUR_RCHW_SHIFT 4
> -#define OSD_RECTCUR_RCHW (7 << 4)
> -#define OSD_RECTCUR_RCVW_SHIFT 1
> -#define OSD_RECTCUR_RCVW (7 << 1)
> -#define OSD_RECTCUR_RCACT (1 << 0)
> -
> -#define OSD_VIDWIN0OFST_V0LO (0x1ff << 0)
> -
> -#define OSD_VIDWIN1OFST_V1LO (0x1ff << 0)
> -
> -#define OSD_OSDWIN0OFST_O0LO (0x1ff << 0)
> -
> -#define OSD_OSDWIN1OFST_O1LO (0x1ff << 0)
> -
> -#define OSD_WINOFST_AH_SHIFT 9
> -
> -#define OSD_VIDWIN0OFST_V0AH (0xf << 9)
> -#define OSD_VIDWIN1OFST_V1AH (0xf << 9)
> -#define OSD_OSDWIN0OFST_O0AH (0xf << 9)
> -#define OSD_OSDWIN1OFST_O1AH (0xf << 9)
> -
> -#define OSD_VIDWINADH_V1AH_SHIFT 8
> -#define OSD_VIDWINADH_V1AH (0x7f << 8)
> -#define OSD_VIDWINADH_V0AH_SHIFT 0
> -#define OSD_VIDWINADH_V0AH (0x7f << 0)
> -
> -#define OSD_VIDWIN0ADL_V0AL (0xffff << 0)
> -
> -#define OSD_VIDWIN1ADL_V1AL (0xffff << 0)
> -
> -#define OSD_OSDWINADH_O1AH_SHIFT 8
> -#define OSD_OSDWINADH_O1AH (0x7f << 8)
> -#define OSD_OSDWINADH_O0AH_SHIFT 0
> -#define OSD_OSDWINADH_O0AH (0x7f << 0)
> -
> -#define OSD_OSDWIN0ADL_O0AL (0xffff << 0)
> -
> -#define OSD_OSDWIN1ADL_O1AL (0xffff << 0)
> -
> -#define OSD_BASEPX_BPX (0x3ff << 0)
> -
> -#define OSD_BASEPY_BPY (0x1ff << 0)
> -
> -#define OSD_VIDWIN0XP_V0X (0x7ff << 0)
> -
> -#define OSD_VIDWIN0YP_V0Y (0x7ff << 0)
> -
> -#define OSD_VIDWIN0XL_V0W (0x7ff << 0)
> -
> -#define OSD_VIDWIN0YL_V0H (0x7ff << 0)
> -
> -#define OSD_VIDWIN1XP_V1X (0x7ff << 0)
> -
> -#define OSD_VIDWIN1YP_V1Y (0x7ff << 0)
> -
> -#define OSD_VIDWIN1XL_V1W (0x7ff << 0)
> -
> -#define OSD_VIDWIN1YL_V1H (0x7ff << 0)
> -
> -#define OSD_OSDWIN0XP_W0X (0x7ff << 0)
> -
> -#define OSD_OSDWIN0YP_W0Y (0x7ff << 0)
> -
> -#define OSD_OSDWIN0XL_W0W (0x7ff << 0)
> -
> -#define OSD_OSDWIN0YL_W0H (0x7ff << 0)
> -
> -#define OSD_OSDWIN1XP_W1X (0x7ff << 0)
> -
> -#define OSD_OSDWIN1YP_W1Y (0x7ff << 0)
> -
> -#define OSD_OSDWIN1XL_W1W (0x7ff << 0)
> -
> -#define OSD_OSDWIN1YL_W1H (0x7ff << 0)
> -
> -#define OSD_CURXP_RCSX (0x7ff << 0)
> -
> -#define OSD_CURYP_RCSY (0x7ff << 0)
> -
> -#define OSD_CURXL_RCSW (0x7ff << 0)
> -
> -#define OSD_CURYL_RCSH (0x7ff << 0)
> -
> -#define OSD_EXTMODE_EXPMDSEL (1 << 15)
> -#define OSD_EXTMODE_SCRNHEXP_SHIFT 13
> -#define OSD_EXTMODE_SCRNHEXP (3 << 13)
> -#define OSD_EXTMODE_SCRNVEXP (1 << 12)
> -#define OSD_EXTMODE_OSD1BLDCHR (1 << 11)
> -#define OSD_EXTMODE_OSD0BLDCHR (1 << 10)
> -#define OSD_EXTMODE_ATNOSD1EN (1 << 9)
> -#define OSD_EXTMODE_ATNOSD0EN (1 << 8)
> -#define OSD_EXTMODE_OSDHRSZ15 (1 << 7)
> -#define OSD_EXTMODE_VIDHRSZ15 (1 << 6)
> -#define OSD_EXTMODE_ZMFILV1HEN (1 << 5)
> -#define OSD_EXTMODE_ZMFILV1VEN (1 << 4)
> -#define OSD_EXTMODE_ZMFILV0HEN (1 << 3)
> -#define OSD_EXTMODE_ZMFILV0VEN (1 << 2)
> -#define OSD_EXTMODE_EXPFILHEN (1 << 1)
> -#define OSD_EXTMODE_EXPFILVEN (1 << 0)
> -
> -#define OSD_MISCCTL_BLDSEL (1 << 15)
> -#define OSD_MISCCTL_S420D (1 << 14)
> -#define OSD_MISCCTL_BMAPT (1 << 13)
> -#define OSD_MISCCTL_DM365M (1 << 12)
> -#define OSD_MISCCTL_RGBEN (1 << 7)
> -#define OSD_MISCCTL_RGBWIN (1 << 6)
> -#define OSD_MISCCTL_DMANG (1 << 6)
> -#define OSD_MISCCTL_TMON (1 << 5)
> -#define OSD_MISCCTL_RSEL (1 << 4)
> -#define OSD_MISCCTL_CPBSY (1 << 3)
> -#define OSD_MISCCTL_PPSW (1 << 2)
> -#define OSD_MISCCTL_PPRV (1 << 1)
> -
> -#define OSD_CLUTRAMYCB_Y_SHIFT 8
> -#define OSD_CLUTRAMYCB_Y (0xff << 8)
> -#define OSD_CLUTRAMYCB_CB_SHIFT 0
> -#define OSD_CLUTRAMYCB_CB (0xff << 0)
> -
> -#define OSD_CLUTRAMCR_CR_SHIFT 8
> -#define OSD_CLUTRAMCR_CR (0xff << 8)
> -#define OSD_CLUTRAMCR_CADDR_SHIFT 0
> -#define OSD_CLUTRAMCR_CADDR (0xff << 0)
> -
> -#define OSD_TRANSPVAL_RGBTRANS (0xffff << 0)
> -
> -#define OSD_TRANSPVALL_RGBL (0xffff << 0)
> -
> -#define OSD_TRANSPVALU_Y_SHIFT 8
> -#define OSD_TRANSPVALU_Y (0xff << 8)
> -#define OSD_TRANSPVALU_RGBU_SHIFT 0
> -#define OSD_TRANSPVALU_RGBU (0xff << 0)
> -
> -#define OSD_TRANSPBMPIDX_BMP1_SHIFT 8
> -#define OSD_TRANSPBMPIDX_BMP1 (0xff << 8)
> -#define OSD_TRANSPBMPIDX_BMP0_SHIFT 0
> -#define OSD_TRANSPBMPIDX_BMP0 0xff
> -
> -#endif /* _DAVINCI_VPBE_H_ */
> diff --git a/drivers/media/platform/ti/davinci/vpbe_venc.c b/drivers/media/platform/ti/davinci/vpbe_venc.c
> deleted file mode 100644
> index 4c8e31de12b1..000000000000
> --- a/drivers/media/platform/ti/davinci/vpbe_venc.c
> +++ /dev/null
> @@ -1,676 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * Copyright (C) 2010 Texas Instruments Inc
> - */
> -#include <linux/module.h>
> -#include <linux/mod_devicetable.h>
> -#include <linux/kernel.h>
> -#include <linux/init.h>
> -#include <linux/ctype.h>
> -#include <linux/delay.h>
> -#include <linux/device.h>
> -#include <linux/interrupt.h>
> -#include <linux/platform_device.h>
> -#include <linux/videodev2.h>
> -#include <linux/slab.h>
> -
> -#include <linux/platform_data/i2c-davinci.h>
> -
> -#include <linux/io.h>
> -
> -#include <media/davinci/vpbe_types.h>
> -#include <media/davinci/vpbe_venc.h>
> -#include <media/davinci/vpss.h>
> -#include <media/v4l2-device.h>
> -
> -#include "vpbe_venc_regs.h"
> -
> -#define MODULE_NAME "davinci-vpbe-venc"
> -
> -static const struct platform_device_id vpbe_venc_devtype[] = {
> - {
> - .name = DM644X_VPBE_VENC_SUBDEV_NAME,
> - .driver_data = VPBE_VERSION_1,
> - }, {
> - .name = DM365_VPBE_VENC_SUBDEV_NAME,
> - .driver_data = VPBE_VERSION_2,
> - }, {
> - .name = DM355_VPBE_VENC_SUBDEV_NAME,
> - .driver_data = VPBE_VERSION_3,
> - },
> - {
> - /* sentinel */
> - }
> -};
> -
> -MODULE_DEVICE_TABLE(platform, vpbe_venc_devtype);
> -
> -static int debug = 2;
> -module_param(debug, int, 0644);
> -MODULE_PARM_DESC(debug, "Debug level 0-2");
> -
> -struct venc_state {
> - struct v4l2_subdev sd;
> - struct venc_callback *callback;
> - struct venc_platform_data *pdata;
> - struct device *pdev;
> - u32 output;
> - v4l2_std_id std;
> - spinlock_t lock;
> - void __iomem *venc_base;
> - void __iomem *vdaccfg_reg;
> - enum vpbe_version venc_type;
> -};
> -
> -static inline struct venc_state *to_state(struct v4l2_subdev *sd)
> -{
> - return container_of(sd, struct venc_state, sd);
> -}
> -
> -static inline u32 venc_read(struct v4l2_subdev *sd, u32 offset)
> -{
> - struct venc_state *venc = to_state(sd);
> -
> - return readl(venc->venc_base + offset);
> -}
> -
> -static inline u32 venc_write(struct v4l2_subdev *sd, u32 offset, u32 val)
> -{
> - struct venc_state *venc = to_state(sd);
> -
> - writel(val, (venc->venc_base + offset));
> -
> - return val;
> -}
> -
> -static inline u32 venc_modify(struct v4l2_subdev *sd, u32 offset,
> - u32 val, u32 mask)
> -{
> - u32 new_val = (venc_read(sd, offset) & ~mask) | (val & mask);
> -
> - venc_write(sd, offset, new_val);
> -
> - return new_val;
> -}
> -
> -static inline u32 vdaccfg_write(struct v4l2_subdev *sd, u32 val)
> -{
> - struct venc_state *venc = to_state(sd);
> -
> - writel(val, venc->vdaccfg_reg);
> -
> - val = readl(venc->vdaccfg_reg);
> -
> - return val;
> -}
> -
> -#define VDAC_COMPONENT 0x543
> -#define VDAC_S_VIDEO 0x210
> -/* This function sets the dac of the VPBE for various outputs
> - */
> -static int venc_set_dac(struct v4l2_subdev *sd, u32 out_index)
> -{
> - switch (out_index) {
> - case 0:
> - v4l2_dbg(debug, 1, sd, "Setting output to Composite\n");
> - venc_write(sd, VENC_DACSEL, 0);
> - break;
> - case 1:
> - v4l2_dbg(debug, 1, sd, "Setting output to Component\n");
> - venc_write(sd, VENC_DACSEL, VDAC_COMPONENT);
> - break;
> - case 2:
> - v4l2_dbg(debug, 1, sd, "Setting output to S-video\n");
> - venc_write(sd, VENC_DACSEL, VDAC_S_VIDEO);
> - break;
> - default:
> - return -EINVAL;
> - }
> -
> - return 0;
> -}
> -
> -static void venc_enabledigitaloutput(struct v4l2_subdev *sd, int benable)
> -{
> - struct venc_state *venc = to_state(sd);
> -
> - v4l2_dbg(debug, 2, sd, "venc_enabledigitaloutput\n");
> -
> - if (benable) {
> - venc_write(sd, VENC_VMOD, 0);
> - venc_write(sd, VENC_CVBS, 0);
> - venc_write(sd, VENC_LCDOUT, 0);
> - venc_write(sd, VENC_HSPLS, 0);
> - venc_write(sd, VENC_HSTART, 0);
> - venc_write(sd, VENC_HVALID, 0);
> - venc_write(sd, VENC_HINT, 0);
> - venc_write(sd, VENC_VSPLS, 0);
> - venc_write(sd, VENC_VSTART, 0);
> - venc_write(sd, VENC_VVALID, 0);
> - venc_write(sd, VENC_VINT, 0);
> - venc_write(sd, VENC_YCCCTL, 0);
> - venc_write(sd, VENC_DACSEL, 0);
> -
> - } else {
> - venc_write(sd, VENC_VMOD, 0);
> - /* disable VCLK output pin enable */
> - venc_write(sd, VENC_VIDCTL, 0x141);
> -
> - /* Disable output sync pins */
> - venc_write(sd, VENC_SYNCCTL, 0);
> -
> - /* Disable DCLOCK */
> - venc_write(sd, VENC_DCLKCTL, 0);
> - venc_write(sd, VENC_DRGBX1, 0x0000057C);
> -
> - /* Disable LCD output control (accepting default polarity) */
> - venc_write(sd, VENC_LCDOUT, 0);
> - if (venc->venc_type != VPBE_VERSION_3)
> - venc_write(sd, VENC_CMPNT, 0x100);
> - venc_write(sd, VENC_HSPLS, 0);
> - venc_write(sd, VENC_HINT, 0);
> - venc_write(sd, VENC_HSTART, 0);
> - venc_write(sd, VENC_HVALID, 0);
> -
> - venc_write(sd, VENC_VSPLS, 0);
> - venc_write(sd, VENC_VINT, 0);
> - venc_write(sd, VENC_VSTART, 0);
> - venc_write(sd, VENC_VVALID, 0);
> -
> - venc_write(sd, VENC_HSDLY, 0);
> - venc_write(sd, VENC_VSDLY, 0);
> -
> - venc_write(sd, VENC_YCCCTL, 0);
> - venc_write(sd, VENC_VSTARTA, 0);
> -
> - /* Set OSD clock and OSD Sync Adavance registers */
> - venc_write(sd, VENC_OSDCLK0, 1);
> - venc_write(sd, VENC_OSDCLK1, 2);
> - }
> -}
> -
> -static void
> -venc_enable_vpss_clock(int venc_type,
> - enum vpbe_enc_timings_type type,
> - unsigned int pclock)
> -{
> - if (venc_type == VPBE_VERSION_1)
> - return;
> -
> - if (venc_type == VPBE_VERSION_2 && (type == VPBE_ENC_STD || (type ==
> - VPBE_ENC_DV_TIMINGS && pclock <= 27000000))) {
> - vpss_enable_clock(VPSS_VENC_CLOCK_SEL, 1);
> - vpss_enable_clock(VPSS_VPBE_CLOCK, 1);
> - return;
> - }
> -
> - if (venc_type == VPBE_VERSION_3 && type == VPBE_ENC_STD)
> - vpss_enable_clock(VPSS_VENC_CLOCK_SEL, 0);
> -}
> -
> -#define VDAC_CONFIG_SD_V3 0x0E21A6B6
> -#define VDAC_CONFIG_SD_V2 0x081141CF
> -/*
> - * setting NTSC mode
> - */
> -static int venc_set_ntsc(struct v4l2_subdev *sd)
> -{
> - struct venc_state *venc = to_state(sd);
> - struct venc_platform_data *pdata = venc->pdata;
> -
> - v4l2_dbg(debug, 2, sd, "venc_set_ntsc\n");
> -
> - /* Setup clock at VPSS & VENC for SD */
> - vpss_enable_clock(VPSS_VENC_CLOCK_SEL, 1);
> - if (pdata->setup_clock(VPBE_ENC_STD, V4L2_STD_525_60) < 0)
> - return -EINVAL;
> -
> - venc_enable_vpss_clock(venc->venc_type, VPBE_ENC_STD, V4L2_STD_525_60);
> - venc_enabledigitaloutput(sd, 0);
> -
> - if (venc->venc_type == VPBE_VERSION_3) {
> - venc_write(sd, VENC_CLKCTL, 0x01);
> - venc_write(sd, VENC_VIDCTL, 0);
> - vdaccfg_write(sd, VDAC_CONFIG_SD_V3);
> - } else if (venc->venc_type == VPBE_VERSION_2) {
> - venc_write(sd, VENC_CLKCTL, 0x01);
> - venc_write(sd, VENC_VIDCTL, 0);
> - vdaccfg_write(sd, VDAC_CONFIG_SD_V2);
> - } else {
> - /* to set VENC CLK DIV to 1 - final clock is 54 MHz */
> - venc_modify(sd, VENC_VIDCTL, 0, 1 << 1);
> - /* Set REC656 Mode */
> - venc_write(sd, VENC_YCCCTL, 0x1);
> - venc_modify(sd, VENC_VDPRO, 0, VENC_VDPRO_DAFRQ);
> - venc_modify(sd, VENC_VDPRO, 0, VENC_VDPRO_DAUPS);
> - }
> -
> - venc_write(sd, VENC_VMOD, 0);
> - venc_modify(sd, VENC_VMOD, (1 << VENC_VMOD_VIE_SHIFT),
> - VENC_VMOD_VIE);
> - venc_modify(sd, VENC_VMOD, (0 << VENC_VMOD_VMD), VENC_VMOD_VMD);
> - venc_modify(sd, VENC_VMOD, (0 << VENC_VMOD_TVTYP_SHIFT),
> - VENC_VMOD_TVTYP);
> - venc_write(sd, VENC_DACTST, 0x0);
> - venc_modify(sd, VENC_VMOD, VENC_VMOD_VENC, VENC_VMOD_VENC);
> -
> - return 0;
> -}
> -
> -/*
> - * setting PAL mode
> - */
> -static int venc_set_pal(struct v4l2_subdev *sd)
> -{
> - struct venc_state *venc = to_state(sd);
> -
> - v4l2_dbg(debug, 2, sd, "venc_set_pal\n");
> -
> - /* Setup clock at VPSS & VENC for SD */
> - vpss_enable_clock(VPSS_VENC_CLOCK_SEL, 1);
> - if (venc->pdata->setup_clock(VPBE_ENC_STD, V4L2_STD_625_50) < 0)
> - return -EINVAL;
> -
> - venc_enable_vpss_clock(venc->venc_type, VPBE_ENC_STD, V4L2_STD_625_50);
> - venc_enabledigitaloutput(sd, 0);
> -
> - if (venc->venc_type == VPBE_VERSION_3) {
> - venc_write(sd, VENC_CLKCTL, 0x1);
> - venc_write(sd, VENC_VIDCTL, 0);
> - vdaccfg_write(sd, VDAC_CONFIG_SD_V3);
> - } else if (venc->venc_type == VPBE_VERSION_2) {
> - venc_write(sd, VENC_CLKCTL, 0x1);
> - venc_write(sd, VENC_VIDCTL, 0);
> - vdaccfg_write(sd, VDAC_CONFIG_SD_V2);
> - } else {
> - /* to set VENC CLK DIV to 1 - final clock is 54 MHz */
> - venc_modify(sd, VENC_VIDCTL, 0, 1 << 1);
> - /* Set REC656 Mode */
> - venc_write(sd, VENC_YCCCTL, 0x1);
> - }
> -
> - venc_modify(sd, VENC_SYNCCTL, 1 << VENC_SYNCCTL_OVD_SHIFT,
> - VENC_SYNCCTL_OVD);
> - venc_write(sd, VENC_VMOD, 0);
> - venc_modify(sd, VENC_VMOD,
> - (1 << VENC_VMOD_VIE_SHIFT),
> - VENC_VMOD_VIE);
> - venc_modify(sd, VENC_VMOD,
> - (0 << VENC_VMOD_VMD), VENC_VMOD_VMD);
> - venc_modify(sd, VENC_VMOD,
> - (1 << VENC_VMOD_TVTYP_SHIFT),
> - VENC_VMOD_TVTYP);
> - venc_write(sd, VENC_DACTST, 0x0);
> - venc_modify(sd, VENC_VMOD, VENC_VMOD_VENC, VENC_VMOD_VENC);
> -
> - return 0;
> -}
> -
> -#define VDAC_CONFIG_HD_V2 0x081141EF
> -/*
> - * venc_set_480p59_94
> - *
> - * This function configures the video encoder to EDTV(525p) component setting.
> - */
> -static int venc_set_480p59_94(struct v4l2_subdev *sd)
> -{
> - struct venc_state *venc = to_state(sd);
> - struct venc_platform_data *pdata = venc->pdata;
> -
> - v4l2_dbg(debug, 2, sd, "venc_set_480p59_94\n");
> - if (venc->venc_type != VPBE_VERSION_1 &&
> - venc->venc_type != VPBE_VERSION_2)
> - return -EINVAL;
> -
> - /* Setup clock at VPSS & VENC for SD */
> - if (pdata->setup_clock(VPBE_ENC_DV_TIMINGS, 27000000) < 0)
> - return -EINVAL;
> -
> - venc_enable_vpss_clock(venc->venc_type, VPBE_ENC_DV_TIMINGS, 27000000);
> - venc_enabledigitaloutput(sd, 0);
> -
> - if (venc->venc_type == VPBE_VERSION_2)
> - vdaccfg_write(sd, VDAC_CONFIG_HD_V2);
> - venc_write(sd, VENC_OSDCLK0, 0);
> - venc_write(sd, VENC_OSDCLK1, 1);
> -
> - if (venc->venc_type == VPBE_VERSION_1) {
> - venc_modify(sd, VENC_VDPRO, VENC_VDPRO_DAFRQ,
> - VENC_VDPRO_DAFRQ);
> - venc_modify(sd, VENC_VDPRO, VENC_VDPRO_DAUPS,
> - VENC_VDPRO_DAUPS);
> - }
> -
> - venc_write(sd, VENC_VMOD, 0);
> - venc_modify(sd, VENC_VMOD, (1 << VENC_VMOD_VIE_SHIFT),
> - VENC_VMOD_VIE);
> - venc_modify(sd, VENC_VMOD, VENC_VMOD_HDMD, VENC_VMOD_HDMD);
> - venc_modify(sd, VENC_VMOD, (HDTV_525P << VENC_VMOD_TVTYP_SHIFT),
> - VENC_VMOD_TVTYP);
> - venc_modify(sd, VENC_VMOD, VENC_VMOD_VDMD_YCBCR8 <<
> - VENC_VMOD_VDMD_SHIFT, VENC_VMOD_VDMD);
> -
> - venc_modify(sd, VENC_VMOD, VENC_VMOD_VENC, VENC_VMOD_VENC);
> -
> - return 0;
> -}
> -
> -/*
> - * venc_set_625p
> - *
> - * This function configures the video encoder to HDTV(625p) component setting
> - */
> -static int venc_set_576p50(struct v4l2_subdev *sd)
> -{
> - struct venc_state *venc = to_state(sd);
> - struct venc_platform_data *pdata = venc->pdata;
> -
> - v4l2_dbg(debug, 2, sd, "venc_set_576p50\n");
> -
> - if (venc->venc_type != VPBE_VERSION_1 &&
> - venc->venc_type != VPBE_VERSION_2)
> - return -EINVAL;
> - /* Setup clock at VPSS & VENC for SD */
> - if (pdata->setup_clock(VPBE_ENC_DV_TIMINGS, 27000000) < 0)
> - return -EINVAL;
> -
> - venc_enable_vpss_clock(venc->venc_type, VPBE_ENC_DV_TIMINGS, 27000000);
> - venc_enabledigitaloutput(sd, 0);
> -
> - if (venc->venc_type == VPBE_VERSION_2)
> - vdaccfg_write(sd, VDAC_CONFIG_HD_V2);
> -
> - venc_write(sd, VENC_OSDCLK0, 0);
> - venc_write(sd, VENC_OSDCLK1, 1);
> -
> - if (venc->venc_type == VPBE_VERSION_1) {
> - venc_modify(sd, VENC_VDPRO, VENC_VDPRO_DAFRQ,
> - VENC_VDPRO_DAFRQ);
> - venc_modify(sd, VENC_VDPRO, VENC_VDPRO_DAUPS,
> - VENC_VDPRO_DAUPS);
> - }
> -
> - venc_write(sd, VENC_VMOD, 0);
> - venc_modify(sd, VENC_VMOD, (1 << VENC_VMOD_VIE_SHIFT),
> - VENC_VMOD_VIE);
> - venc_modify(sd, VENC_VMOD, VENC_VMOD_HDMD, VENC_VMOD_HDMD);
> - venc_modify(sd, VENC_VMOD, (HDTV_625P << VENC_VMOD_TVTYP_SHIFT),
> - VENC_VMOD_TVTYP);
> -
> - venc_modify(sd, VENC_VMOD, VENC_VMOD_VDMD_YCBCR8 <<
> - VENC_VMOD_VDMD_SHIFT, VENC_VMOD_VDMD);
> - venc_modify(sd, VENC_VMOD, VENC_VMOD_VENC, VENC_VMOD_VENC);
> -
> - return 0;
> -}
> -
> -/*
> - * venc_set_720p60_internal - Setup 720p60 in venc for dm365 only
> - */
> -static int venc_set_720p60_internal(struct v4l2_subdev *sd)
> -{
> - struct venc_state *venc = to_state(sd);
> - struct venc_platform_data *pdata = venc->pdata;
> -
> - if (pdata->setup_clock(VPBE_ENC_DV_TIMINGS, 74250000) < 0)
> - return -EINVAL;
> -
> - venc_enable_vpss_clock(venc->venc_type, VPBE_ENC_DV_TIMINGS, 74250000);
> - venc_enabledigitaloutput(sd, 0);
> -
> - venc_write(sd, VENC_OSDCLK0, 0);
> - venc_write(sd, VENC_OSDCLK1, 1);
> -
> - venc_write(sd, VENC_VMOD, 0);
> - /* DM365 component HD mode */
> - venc_modify(sd, VENC_VMOD, (1 << VENC_VMOD_VIE_SHIFT),
> - VENC_VMOD_VIE);
> - venc_modify(sd, VENC_VMOD, VENC_VMOD_HDMD, VENC_VMOD_HDMD);
> - venc_modify(sd, VENC_VMOD, (HDTV_720P << VENC_VMOD_TVTYP_SHIFT),
> - VENC_VMOD_TVTYP);
> - venc_modify(sd, VENC_VMOD, VENC_VMOD_VENC, VENC_VMOD_VENC);
> - venc_write(sd, VENC_XHINTVL, 0);
> - return 0;
> -}
> -
> -/*
> - * venc_set_1080i30_internal - Setup 1080i30 in venc for dm365 only
> - */
> -static int venc_set_1080i30_internal(struct v4l2_subdev *sd)
> -{
> - struct venc_state *venc = to_state(sd);
> - struct venc_platform_data *pdata = venc->pdata;
> -
> - if (pdata->setup_clock(VPBE_ENC_DV_TIMINGS, 74250000) < 0)
> - return -EINVAL;
> -
> - venc_enable_vpss_clock(venc->venc_type, VPBE_ENC_DV_TIMINGS, 74250000);
> - venc_enabledigitaloutput(sd, 0);
> -
> - venc_write(sd, VENC_OSDCLK0, 0);
> - venc_write(sd, VENC_OSDCLK1, 1);
> -
> -
> - venc_write(sd, VENC_VMOD, 0);
> - /* DM365 component HD mode */
> - venc_modify(sd, VENC_VMOD, (1 << VENC_VMOD_VIE_SHIFT),
> - VENC_VMOD_VIE);
> - venc_modify(sd, VENC_VMOD, VENC_VMOD_HDMD, VENC_VMOD_HDMD);
> - venc_modify(sd, VENC_VMOD, (HDTV_1080I << VENC_VMOD_TVTYP_SHIFT),
> - VENC_VMOD_TVTYP);
> - venc_modify(sd, VENC_VMOD, VENC_VMOD_VENC, VENC_VMOD_VENC);
> - venc_write(sd, VENC_XHINTVL, 0);
> - return 0;
> -}
> -
> -static int venc_s_std_output(struct v4l2_subdev *sd, v4l2_std_id norm)
> -{
> - v4l2_dbg(debug, 1, sd, "venc_s_std_output\n");
> -
> - if (norm & V4L2_STD_525_60)
> - return venc_set_ntsc(sd);
> - else if (norm & V4L2_STD_625_50)
> - return venc_set_pal(sd);
> -
> - return -EINVAL;
> -}
> -
> -static int venc_s_dv_timings(struct v4l2_subdev *sd,
> - struct v4l2_dv_timings *dv_timings)
> -{
> - struct venc_state *venc = to_state(sd);
> - u32 height = dv_timings->bt.height;
> - int ret;
> -
> - v4l2_dbg(debug, 1, sd, "venc_s_dv_timings\n");
> -
> - if (height == 576)
> - return venc_set_576p50(sd);
> - else if (height == 480)
> - return venc_set_480p59_94(sd);
> - else if ((height == 720) &&
> - (venc->venc_type == VPBE_VERSION_2)) {
> - /* TBD setup internal 720p mode here */
> - ret = venc_set_720p60_internal(sd);
> - /* for DM365 VPBE, there is DAC inside */
> - vdaccfg_write(sd, VDAC_CONFIG_HD_V2);
> - return ret;
> - } else if ((height == 1080) &&
> - (venc->venc_type == VPBE_VERSION_2)) {
> - /* TBD setup internal 1080i mode here */
> - ret = venc_set_1080i30_internal(sd);
> - /* for DM365 VPBE, there is DAC inside */
> - vdaccfg_write(sd, VDAC_CONFIG_HD_V2);
> - return ret;
> - }
> - return -EINVAL;
> -}
> -
> -static int venc_s_routing(struct v4l2_subdev *sd, u32 input, u32 output,
> - u32 config)
> -{
> - struct venc_state *venc = to_state(sd);
> - int ret;
> -
> - v4l2_dbg(debug, 1, sd, "venc_s_routing\n");
> -
> - ret = venc_set_dac(sd, output);
> - if (!ret)
> - venc->output = output;
> -
> - return ret;
> -}
> -
> -static long venc_command(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
> -{
> - u32 val;
> -
> - switch (cmd) {
> - case VENC_GET_FLD:
> - val = venc_read(sd, VENC_VSTAT);
> - *((int *)arg) = ((val & VENC_VSTAT_FIDST) ==
> - VENC_VSTAT_FIDST);
> - break;
> - default:
> - v4l2_err(sd, "Wrong IOCTL cmd\n");
> - break;
> - }
> -
> - return 0;
> -}
> -
> -static const struct v4l2_subdev_core_ops venc_core_ops = {
> - .command = venc_command,
> -};
> -
> -static const struct v4l2_subdev_video_ops venc_video_ops = {
> - .s_routing = venc_s_routing,
> - .s_std_output = venc_s_std_output,
> - .s_dv_timings = venc_s_dv_timings,
> -};
> -
> -static const struct v4l2_subdev_ops venc_ops = {
> - .core = &venc_core_ops,
> - .video = &venc_video_ops,
> -};
> -
> -static int venc_initialize(struct v4l2_subdev *sd)
> -{
> - struct venc_state *venc = to_state(sd);
> - int ret;
> -
> - /* Set default to output to composite and std to NTSC */
> - venc->output = 0;
> - venc->std = V4L2_STD_525_60;
> -
> - ret = venc_s_routing(sd, 0, venc->output, 0);
> - if (ret < 0) {
> - v4l2_err(sd, "Error setting output during init\n");
> - return -EINVAL;
> - }
> -
> - ret = venc_s_std_output(sd, venc->std);
> - if (ret < 0) {
> - v4l2_err(sd, "Error setting std during init\n");
> - return -EINVAL;
> - }
> -
> - return ret;
> -}
> -
> -static int venc_device_get(struct device *dev, void *data)
> -{
> - struct platform_device *pdev = to_platform_device(dev);
> - struct venc_state **venc = data;
> -
> - if (strstr(pdev->name, "vpbe-venc") != NULL)
> - *venc = platform_get_drvdata(pdev);
> -
> - return 0;
> -}
> -
> -struct v4l2_subdev *venc_sub_dev_init(struct v4l2_device *v4l2_dev,
> - const char *venc_name)
> -{
> - struct venc_state *venc = NULL;
> -
> - bus_for_each_dev(&platform_bus_type, NULL, &venc,
> - venc_device_get);
> - if (venc == NULL)
> - return NULL;
> -
> - v4l2_subdev_init(&venc->sd, &venc_ops);
> -
> - strscpy(venc->sd.name, venc_name, sizeof(venc->sd.name));
> - if (v4l2_device_register_subdev(v4l2_dev, &venc->sd) < 0) {
> - v4l2_err(v4l2_dev,
> - "vpbe unable to register venc sub device\n");
> - return NULL;
> - }
> - if (venc_initialize(&venc->sd)) {
> - v4l2_err(v4l2_dev,
> - "vpbe venc initialization failed\n");
> - return NULL;
> - }
> -
> - return &venc->sd;
> -}
> -EXPORT_SYMBOL(venc_sub_dev_init);
> -
> -static int venc_probe(struct platform_device *pdev)
> -{
> - const struct platform_device_id *pdev_id;
> - struct venc_state *venc;
> -
> - if (!pdev->dev.platform_data) {
> - dev_err(&pdev->dev, "No platform data for VENC sub device");
> - return -EINVAL;
> - }
> -
> - pdev_id = platform_get_device_id(pdev);
> - if (!pdev_id)
> - return -EINVAL;
> -
> - venc = devm_kzalloc(&pdev->dev, sizeof(struct venc_state), GFP_KERNEL);
> - if (venc == NULL)
> - return -ENOMEM;
> -
> - venc->venc_type = pdev_id->driver_data;
> - venc->pdev = &pdev->dev;
> - venc->pdata = pdev->dev.platform_data;
> -
> - venc->venc_base = devm_platform_ioremap_resource(pdev, 0);
> - if (IS_ERR(venc->venc_base))
> - return PTR_ERR(venc->venc_base);
> -
> - if (venc->venc_type != VPBE_VERSION_1) {
> - venc->vdaccfg_reg = devm_platform_ioremap_resource(pdev, 1);
> - if (IS_ERR(venc->vdaccfg_reg))
> - return PTR_ERR(venc->vdaccfg_reg);
> - }
> - spin_lock_init(&venc->lock);
> - platform_set_drvdata(pdev, venc);
> - dev_notice(venc->pdev, "VENC sub device probe success\n");
> -
> - return 0;
> -}
> -
> -static int venc_remove(struct platform_device *pdev)
> -{
> - return 0;
> -}
> -
> -static struct platform_driver venc_driver = {
> - .probe = venc_probe,
> - .remove = venc_remove,
> - .driver = {
> - .name = MODULE_NAME,
> - },
> - .id_table = vpbe_venc_devtype
> -};
> -
> -module_platform_driver(venc_driver);
> -
> -MODULE_LICENSE("GPL");
> -MODULE_DESCRIPTION("VPBE VENC Driver");
> -MODULE_AUTHOR("Texas Instruments");
> diff --git a/drivers/media/platform/ti/davinci/vpbe_venc_regs.h b/drivers/media/platform/ti/davinci/vpbe_venc_regs.h
> deleted file mode 100644
> index 29d8fc3af662..000000000000
> --- a/drivers/media/platform/ti/davinci/vpbe_venc_regs.h
> +++ /dev/null
> @@ -1,165 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * Copyright (C) 2006-2010 Texas Instruments Inc
> - */
> -#ifndef _VPBE_VENC_REGS_H
> -#define _VPBE_VENC_REGS_H
> -
> -/* VPBE Video Encoder / Digital LCD Subsystem Registers (VENC) */
> -#define VENC_VMOD 0x00
> -#define VENC_VIDCTL 0x04
> -#define VENC_VDPRO 0x08
> -#define VENC_SYNCCTL 0x0C
> -#define VENC_HSPLS 0x10
> -#define VENC_VSPLS 0x14
> -#define VENC_HINT 0x18
> -#define VENC_HSTART 0x1C
> -#define VENC_HVALID 0x20
> -#define VENC_VINT 0x24
> -#define VENC_VSTART 0x28
> -#define VENC_VVALID 0x2C
> -#define VENC_HSDLY 0x30
> -#define VENC_VSDLY 0x34
> -#define VENC_YCCCTL 0x38
> -#define VENC_RGBCTL 0x3C
> -#define VENC_RGBCLP 0x40
> -#define VENC_LINECTL 0x44
> -#define VENC_CULLLINE 0x48
> -#define VENC_LCDOUT 0x4C
> -#define VENC_BRTS 0x50
> -#define VENC_BRTW 0x54
> -#define VENC_ACCTL 0x58
> -#define VENC_PWMP 0x5C
> -#define VENC_PWMW 0x60
> -#define VENC_DCLKCTL 0x64
> -#define VENC_DCLKPTN0 0x68
> -#define VENC_DCLKPTN1 0x6C
> -#define VENC_DCLKPTN2 0x70
> -#define VENC_DCLKPTN3 0x74
> -#define VENC_DCLKPTN0A 0x78
> -#define VENC_DCLKPTN1A 0x7C
> -#define VENC_DCLKPTN2A 0x80
> -#define VENC_DCLKPTN3A 0x84
> -#define VENC_DCLKHS 0x88
> -#define VENC_DCLKHSA 0x8C
> -#define VENC_DCLKHR 0x90
> -#define VENC_DCLKVS 0x94
> -#define VENC_DCLKVR 0x98
> -#define VENC_CAPCTL 0x9C
> -#define VENC_CAPDO 0xA0
> -#define VENC_CAPDE 0xA4
> -#define VENC_ATR0 0xA8
> -#define VENC_ATR1 0xAC
> -#define VENC_ATR2 0xB0
> -#define VENC_VSTAT 0xB8
> -#define VENC_RAMADR 0xBC
> -#define VENC_RAMPORT 0xC0
> -#define VENC_DACTST 0xC4
> -#define VENC_YCOLVL 0xC8
> -#define VENC_SCPROG 0xCC
> -#define VENC_CVBS 0xDC
> -#define VENC_CMPNT 0xE0
> -#define VENC_ETMG0 0xE4
> -#define VENC_ETMG1 0xE8
> -#define VENC_ETMG2 0xEC
> -#define VENC_ETMG3 0xF0
> -#define VENC_DACSEL 0xF4
> -#define VENC_ARGBX0 0x100
> -#define VENC_ARGBX1 0x104
> -#define VENC_ARGBX2 0x108
> -#define VENC_ARGBX3 0x10C
> -#define VENC_ARGBX4 0x110
> -#define VENC_DRGBX0 0x114
> -#define VENC_DRGBX1 0x118
> -#define VENC_DRGBX2 0x11C
> -#define VENC_DRGBX3 0x120
> -#define VENC_DRGBX4 0x124
> -#define VENC_VSTARTA 0x128
> -#define VENC_OSDCLK0 0x12C
> -#define VENC_OSDCLK1 0x130
> -#define VENC_HVLDCL0 0x134
> -#define VENC_HVLDCL1 0x138
> -#define VENC_OSDHADV 0x13C
> -#define VENC_CLKCTL 0x140
> -#define VENC_GAMCTL 0x144
> -#define VENC_XHINTVL 0x174
> -
> -/* bit definitions */
> -#define VPBE_PCR_VENC_DIV (1 << 1)
> -#define VPBE_PCR_CLK_OFF (1 << 0)
> -
> -#define VENC_VMOD_VDMD_SHIFT 12
> -#define VENC_VMOD_VDMD_YCBCR16 0
> -#define VENC_VMOD_VDMD_YCBCR8 1
> -#define VENC_VMOD_VDMD_RGB666 2
> -#define VENC_VMOD_VDMD_RGB8 3
> -#define VENC_VMOD_VDMD_EPSON 4
> -#define VENC_VMOD_VDMD_CASIO 5
> -#define VENC_VMOD_VDMD_UDISPQVGA 6
> -#define VENC_VMOD_VDMD_STNLCD 7
> -#define VENC_VMOD_VIE_SHIFT 1
> -#define VENC_VMOD_VDMD (7 << 12)
> -#define VENC_VMOD_ITLCL (1 << 11)
> -#define VENC_VMOD_ITLC (1 << 10)
> -#define VENC_VMOD_NSIT (1 << 9)
> -#define VENC_VMOD_HDMD (1 << 8)
> -#define VENC_VMOD_TVTYP_SHIFT 6
> -#define VENC_VMOD_TVTYP (3 << 6)
> -#define VENC_VMOD_SLAVE (1 << 5)
> -#define VENC_VMOD_VMD (1 << 4)
> -#define VENC_VMOD_BLNK (1 << 3)
> -#define VENC_VMOD_VIE (1 << 1)
> -#define VENC_VMOD_VENC (1 << 0)
> -
> -/* VMOD TVTYP options for HDMD=0 */
> -#define SDTV_NTSC 0
> -#define SDTV_PAL 1
> -/* VMOD TVTYP options for HDMD=1 */
> -#define HDTV_525P 0
> -#define HDTV_625P 1
> -#define HDTV_1080I 2
> -#define HDTV_720P 3
> -
> -#define VENC_VIDCTL_VCLKP (1 << 14)
> -#define VENC_VIDCTL_VCLKE_SHIFT 13
> -#define VENC_VIDCTL_VCLKE (1 << 13)
> -#define VENC_VIDCTL_VCLKZ_SHIFT 12
> -#define VENC_VIDCTL_VCLKZ (1 << 12)
> -#define VENC_VIDCTL_SYDIR_SHIFT 8
> -#define VENC_VIDCTL_SYDIR (1 << 8)
> -#define VENC_VIDCTL_DOMD_SHIFT 4
> -#define VENC_VIDCTL_DOMD (3 << 4)
> -#define VENC_VIDCTL_YCDIR_SHIFT 0
> -#define VENC_VIDCTL_YCDIR (1 << 0)
> -
> -#define VENC_VDPRO_ATYCC_SHIFT 5
> -#define VENC_VDPRO_ATYCC (1 << 5)
> -#define VENC_VDPRO_ATCOM_SHIFT 4
> -#define VENC_VDPRO_ATCOM (1 << 4)
> -#define VENC_VDPRO_DAFRQ (1 << 3)
> -#define VENC_VDPRO_DAUPS (1 << 2)
> -#define VENC_VDPRO_CUPS (1 << 1)
> -#define VENC_VDPRO_YUPS (1 << 0)
> -
> -#define VENC_SYNCCTL_VPL_SHIFT 3
> -#define VENC_SYNCCTL_VPL (1 << 3)
> -#define VENC_SYNCCTL_HPL_SHIFT 2
> -#define VENC_SYNCCTL_HPL (1 << 2)
> -#define VENC_SYNCCTL_SYEV_SHIFT 1
> -#define VENC_SYNCCTL_SYEV (1 << 1)
> -#define VENC_SYNCCTL_SYEH_SHIFT 0
> -#define VENC_SYNCCTL_SYEH (1 << 0)
> -#define VENC_SYNCCTL_OVD_SHIFT 14
> -#define VENC_SYNCCTL_OVD (1 << 14)
> -
> -#define VENC_DCLKCTL_DCKEC_SHIFT 11
> -#define VENC_DCLKCTL_DCKEC (1 << 11)
> -#define VENC_DCLKCTL_DCKPW_SHIFT 0
> -#define VENC_DCLKCTL_DCKPW (0x3f << 0)
> -
> -#define VENC_VSTAT_FIDST (1 << 4)
> -
> -#define VENC_CMPNT_MRGB_SHIFT 14
> -#define VENC_CMPNT_MRGB (1 << 14)
> -
> -#endif /* _VPBE_VENC_REGS_H */
> diff --git a/drivers/media/platform/ti/davinci/vpss.c b/drivers/media/platform/ti/davinci/vpss.c
> deleted file mode 100644
> index d15b991ab17c..000000000000
> --- a/drivers/media/platform/ti/davinci/vpss.c
> +++ /dev/null
> @@ -1,529 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-or-later
> -/*
> - * Copyright (C) 2009 Texas Instruments.
> - *
> - * common vpss system module platform driver for all video drivers.
> - */
> -#include <linux/module.h>
> -#include <linux/platform_device.h>
> -#include <linux/io.h>
> -#include <linux/pm_runtime.h>
> -#include <linux/err.h>
> -
> -#include <media/davinci/vpss.h>
> -
> -MODULE_LICENSE("GPL");
> -MODULE_DESCRIPTION("VPSS Driver");
> -MODULE_AUTHOR("Texas Instruments");
> -
> -/* DM644x defines */
> -#define DM644X_SBL_PCR_VPSS (4)
> -
> -#define DM355_VPSSBL_INTSEL 0x10
> -#define DM355_VPSSBL_EVTSEL 0x14
> -/* vpss BL register offsets */
> -#define DM355_VPSSBL_CCDCMUX 0x1c
> -/* vpss CLK register offsets */
> -#define DM355_VPSSCLK_CLKCTRL 0x04
> -/* masks and shifts */
> -#define VPSS_HSSISEL_SHIFT 4
> -/*
> - * VDINT0 - vpss_int0, VDINT1 - vpss_int1, H3A - vpss_int4,
> - * IPIPE_INT1_SDR - vpss_int5
> - */
> -#define DM355_VPSSBL_INTSEL_DEFAULT 0xff83ff10
> -/* VENCINT - vpss_int8 */
> -#define DM355_VPSSBL_EVTSEL_DEFAULT 0x4
> -
> -#define DM365_ISP5_PCCR 0x04
> -#define DM365_ISP5_PCCR_BL_CLK_ENABLE BIT(0)
> -#define DM365_ISP5_PCCR_ISIF_CLK_ENABLE BIT(1)
> -#define DM365_ISP5_PCCR_H3A_CLK_ENABLE BIT(2)
> -#define DM365_ISP5_PCCR_RSZ_CLK_ENABLE BIT(3)
> -#define DM365_ISP5_PCCR_IPIPE_CLK_ENABLE BIT(4)
> -#define DM365_ISP5_PCCR_IPIPEIF_CLK_ENABLE BIT(5)
> -#define DM365_ISP5_PCCR_RSV BIT(6)
> -
> -#define DM365_ISP5_BCR 0x08
> -#define DM365_ISP5_BCR_ISIF_OUT_ENABLE BIT(1)
> -
> -#define DM365_ISP5_INTSEL1 0x10
> -#define DM365_ISP5_INTSEL2 0x14
> -#define DM365_ISP5_INTSEL3 0x18
> -#define DM365_ISP5_CCDCMUX 0x20
> -#define DM365_ISP5_PG_FRAME_SIZE 0x28
> -#define DM365_VPBE_CLK_CTRL 0x00
> -
> -#define VPSS_CLK_CTRL 0x01c40044
> -#define VPSS_CLK_CTRL_VENCCLKEN BIT(3)
> -#define VPSS_CLK_CTRL_DACCLKEN BIT(4)
> -
> -/*
> - * vpss interrupts. VDINT0 - vpss_int0, VDINT1 - vpss_int1,
> - * AF - vpss_int3
> - */
> -#define DM365_ISP5_INTSEL1_DEFAULT 0x0b1f0100
> -/* AEW - vpss_int6, RSZ_INT_DMA - vpss_int5 */
> -#define DM365_ISP5_INTSEL2_DEFAULT 0x1f0a0f1f
> -/* VENC - vpss_int8 */
> -#define DM365_ISP5_INTSEL3_DEFAULT 0x00000015
> -
> -/* masks and shifts for DM365*/
> -#define DM365_CCDC_PG_VD_POL_SHIFT 0
> -#define DM365_CCDC_PG_HD_POL_SHIFT 1
> -
> -#define CCD_SRC_SEL_MASK (BIT_MASK(5) | BIT_MASK(4))
> -#define CCD_SRC_SEL_SHIFT 4
> -
> -/* Different SoC platforms supported by this driver */
> -enum vpss_platform_type {
> - DM644X,
> - DM355,
> - DM365,
> -};
> -
> -/*
> - * vpss operations. Depends on platform. Not all functions are available
> - * on all platforms. The api, first check if a function is available before
> - * invoking it. In the probe, the function ptrs are initialized based on
> - * vpss name. vpss name can be "dm355_vpss", "dm644x_vpss" etc.
> - */
> -struct vpss_hw_ops {
> - /* enable clock */
> - int (*enable_clock)(enum vpss_clock_sel clock_sel, int en);
> - /* select input to ccdc */
> - void (*select_ccdc_source)(enum vpss_ccdc_source_sel src_sel);
> - /* clear wbl overflow bit */
> - int (*clear_wbl_overflow)(enum vpss_wbl_sel wbl_sel);
> - /* set sync polarity */
> - void (*set_sync_pol)(struct vpss_sync_pol);
> - /* set the PG_FRAME_SIZE register*/
> - void (*set_pg_frame_size)(struct vpss_pg_frame_size);
> - /* check and clear interrupt if occurred */
> - int (*dma_complete_interrupt)(void);
> -};
> -
> -/* vpss configuration */
> -struct vpss_oper_config {
> - __iomem void *vpss_regs_base0;
> - __iomem void *vpss_regs_base1;
> - __iomem void *vpss_regs_base2;
> - enum vpss_platform_type platform;
> - spinlock_t vpss_lock;
> - struct vpss_hw_ops hw_ops;
> -};
> -
> -static struct vpss_oper_config oper_cfg;
> -
> -/* register access routines */
> -static inline u32 bl_regr(u32 offset)
> -{
> - return __raw_readl(oper_cfg.vpss_regs_base0 + offset);
> -}
> -
> -static inline void bl_regw(u32 val, u32 offset)
> -{
> - __raw_writel(val, oper_cfg.vpss_regs_base0 + offset);
> -}
> -
> -static inline u32 vpss_regr(u32 offset)
> -{
> - return __raw_readl(oper_cfg.vpss_regs_base1 + offset);
> -}
> -
> -static inline void vpss_regw(u32 val, u32 offset)
> -{
> - __raw_writel(val, oper_cfg.vpss_regs_base1 + offset);
> -}
> -
> -/* For DM365 only */
> -static inline u32 isp5_read(u32 offset)
> -{
> - return __raw_readl(oper_cfg.vpss_regs_base0 + offset);
> -}
> -
> -/* For DM365 only */
> -static inline void isp5_write(u32 val, u32 offset)
> -{
> - __raw_writel(val, oper_cfg.vpss_regs_base0 + offset);
> -}
> -
> -static void dm365_select_ccdc_source(enum vpss_ccdc_source_sel src_sel)
> -{
> - u32 temp = isp5_read(DM365_ISP5_CCDCMUX) & ~CCD_SRC_SEL_MASK;
> -
> - /* if we are using pattern generator, enable it */
> - if (src_sel == VPSS_PGLPBK || src_sel == VPSS_CCDCPG)
> - temp |= 0x08;
> -
> - temp |= (src_sel << CCD_SRC_SEL_SHIFT);
> - isp5_write(temp, DM365_ISP5_CCDCMUX);
> -}
> -
> -static void dm355_select_ccdc_source(enum vpss_ccdc_source_sel src_sel)
> -{
> - bl_regw(src_sel << VPSS_HSSISEL_SHIFT, DM355_VPSSBL_CCDCMUX);
> -}
> -
> -int vpss_dma_complete_interrupt(void)
> -{
> - if (!oper_cfg.hw_ops.dma_complete_interrupt)
> - return 2;
> - return oper_cfg.hw_ops.dma_complete_interrupt();
> -}
> -EXPORT_SYMBOL(vpss_dma_complete_interrupt);
> -
> -int vpss_select_ccdc_source(enum vpss_ccdc_source_sel src_sel)
> -{
> - if (!oper_cfg.hw_ops.select_ccdc_source)
> - return -EINVAL;
> -
> - oper_cfg.hw_ops.select_ccdc_source(src_sel);
> - return 0;
> -}
> -EXPORT_SYMBOL(vpss_select_ccdc_source);
> -
> -static int dm644x_clear_wbl_overflow(enum vpss_wbl_sel wbl_sel)
> -{
> - u32 mask = 1, val;
> -
> - if (wbl_sel < VPSS_PCR_AEW_WBL_0 ||
> - wbl_sel > VPSS_PCR_CCDC_WBL_O)
> - return -EINVAL;
> -
> - /* writing a 0 clear the overflow */
> - mask = ~(mask << wbl_sel);
> - val = bl_regr(DM644X_SBL_PCR_VPSS) & mask;
> - bl_regw(val, DM644X_SBL_PCR_VPSS);
> - return 0;
> -}
> -
> -void vpss_set_sync_pol(struct vpss_sync_pol sync)
> -{
> - if (!oper_cfg.hw_ops.set_sync_pol)
> - return;
> -
> - oper_cfg.hw_ops.set_sync_pol(sync);
> -}
> -EXPORT_SYMBOL(vpss_set_sync_pol);
> -
> -int vpss_clear_wbl_overflow(enum vpss_wbl_sel wbl_sel)
> -{
> - if (!oper_cfg.hw_ops.clear_wbl_overflow)
> - return -EINVAL;
> -
> - return oper_cfg.hw_ops.clear_wbl_overflow(wbl_sel);
> -}
> -EXPORT_SYMBOL(vpss_clear_wbl_overflow);
> -
> -/*
> - * dm355_enable_clock - Enable VPSS Clock
> - * @clock_sel: Clock to be enabled/disabled
> - * @en: enable/disable flag
> - *
> - * This is called to enable or disable a vpss clock
> - */
> -static int dm355_enable_clock(enum vpss_clock_sel clock_sel, int en)
> -{
> - unsigned long flags;
> - u32 utemp, mask = 0x1, shift = 0;
> -
> - switch (clock_sel) {
> - case VPSS_VPBE_CLOCK:
> - /* nothing since lsb */
> - break;
> - case VPSS_VENC_CLOCK_SEL:
> - shift = 2;
> - break;
> - case VPSS_CFALD_CLOCK:
> - shift = 3;
> - break;
> - case VPSS_H3A_CLOCK:
> - shift = 4;
> - break;
> - case VPSS_IPIPE_CLOCK:
> - shift = 5;
> - break;
> - case VPSS_CCDC_CLOCK:
> - shift = 6;
> - break;
> - default:
> - printk(KERN_ERR "dm355_enable_clock: Invalid selector: %d\n",
> - clock_sel);
> - return -EINVAL;
> - }
> -
> - spin_lock_irqsave(&oper_cfg.vpss_lock, flags);
> - utemp = vpss_regr(DM355_VPSSCLK_CLKCTRL);
> - if (!en)
> - utemp &= ~(mask << shift);
> - else
> - utemp |= (mask << shift);
> -
> - vpss_regw(utemp, DM355_VPSSCLK_CLKCTRL);
> - spin_unlock_irqrestore(&oper_cfg.vpss_lock, flags);
> - return 0;
> -}
> -
> -static int dm365_enable_clock(enum vpss_clock_sel clock_sel, int en)
> -{
> - unsigned long flags;
> - u32 utemp, mask = 0x1, shift = 0, offset = DM365_ISP5_PCCR;
> - u32 (*read)(u32 offset) = isp5_read;
> - void(*write)(u32 val, u32 offset) = isp5_write;
> -
> - switch (clock_sel) {
> - case VPSS_BL_CLOCK:
> - break;
> - case VPSS_CCDC_CLOCK:
> - shift = 1;
> - break;
> - case VPSS_H3A_CLOCK:
> - shift = 2;
> - break;
> - case VPSS_RSZ_CLOCK:
> - shift = 3;
> - break;
> - case VPSS_IPIPE_CLOCK:
> - shift = 4;
> - break;
> - case VPSS_IPIPEIF_CLOCK:
> - shift = 5;
> - break;
> - case VPSS_PCLK_INTERNAL:
> - shift = 6;
> - break;
> - case VPSS_PSYNC_CLOCK_SEL:
> - shift = 7;
> - break;
> - case VPSS_VPBE_CLOCK:
> - read = vpss_regr;
> - write = vpss_regw;
> - offset = DM365_VPBE_CLK_CTRL;
> - break;
> - case VPSS_VENC_CLOCK_SEL:
> - shift = 2;
> - read = vpss_regr;
> - write = vpss_regw;
> - offset = DM365_VPBE_CLK_CTRL;
> - break;
> - case VPSS_LDC_CLOCK:
> - shift = 3;
> - read = vpss_regr;
> - write = vpss_regw;
> - offset = DM365_VPBE_CLK_CTRL;
> - break;
> - case VPSS_FDIF_CLOCK:
> - shift = 4;
> - read = vpss_regr;
> - write = vpss_regw;
> - offset = DM365_VPBE_CLK_CTRL;
> - break;
> - case VPSS_OSD_CLOCK_SEL:
> - shift = 6;
> - read = vpss_regr;
> - write = vpss_regw;
> - offset = DM365_VPBE_CLK_CTRL;
> - break;
> - case VPSS_LDC_CLOCK_SEL:
> - shift = 7;
> - read = vpss_regr;
> - write = vpss_regw;
> - offset = DM365_VPBE_CLK_CTRL;
> - break;
> - default:
> - printk(KERN_ERR "dm365_enable_clock: Invalid selector: %d\n",
> - clock_sel);
> - return -1;
> - }
> -
> - spin_lock_irqsave(&oper_cfg.vpss_lock, flags);
> - utemp = read(offset);
> - if (!en) {
> - mask = ~mask;
> - utemp &= (mask << shift);
> - } else
> - utemp |= (mask << shift);
> -
> - write(utemp, offset);
> - spin_unlock_irqrestore(&oper_cfg.vpss_lock, flags);
> -
> - return 0;
> -}
> -
> -int vpss_enable_clock(enum vpss_clock_sel clock_sel, int en)
> -{
> - if (!oper_cfg.hw_ops.enable_clock)
> - return -EINVAL;
> -
> - return oper_cfg.hw_ops.enable_clock(clock_sel, en);
> -}
> -EXPORT_SYMBOL(vpss_enable_clock);
> -
> -void dm365_vpss_set_sync_pol(struct vpss_sync_pol sync)
> -{
> - int val = 0;
> - val = isp5_read(DM365_ISP5_CCDCMUX);
> -
> - val |= (sync.ccdpg_hdpol << DM365_CCDC_PG_HD_POL_SHIFT);
> - val |= (sync.ccdpg_vdpol << DM365_CCDC_PG_VD_POL_SHIFT);
> -
> - isp5_write(val, DM365_ISP5_CCDCMUX);
> -}
> -EXPORT_SYMBOL(dm365_vpss_set_sync_pol);
> -
> -void vpss_set_pg_frame_size(struct vpss_pg_frame_size frame_size)
> -{
> - if (!oper_cfg.hw_ops.set_pg_frame_size)
> - return;
> -
> - oper_cfg.hw_ops.set_pg_frame_size(frame_size);
> -}
> -EXPORT_SYMBOL(vpss_set_pg_frame_size);
> -
> -void dm365_vpss_set_pg_frame_size(struct vpss_pg_frame_size frame_size)
> -{
> - int current_reg = ((frame_size.hlpfr >> 1) - 1) << 16;
> -
> - current_reg |= (frame_size.pplen - 1);
> - isp5_write(current_reg, DM365_ISP5_PG_FRAME_SIZE);
> -}
> -EXPORT_SYMBOL(dm365_vpss_set_pg_frame_size);
> -
> -static int vpss_probe(struct platform_device *pdev)
> -{
> - char *platform_name;
> -
> - if (!pdev->dev.platform_data) {
> - dev_err(&pdev->dev, "no platform data\n");
> - return -ENOENT;
> - }
> -
> - platform_name = pdev->dev.platform_data;
> - if (!strcmp(platform_name, "dm355_vpss"))
> - oper_cfg.platform = DM355;
> - else if (!strcmp(platform_name, "dm365_vpss"))
> - oper_cfg.platform = DM365;
> - else if (!strcmp(platform_name, "dm644x_vpss"))
> - oper_cfg.platform = DM644X;
> - else {
> - dev_err(&pdev->dev, "vpss driver not supported on this platform\n");
> - return -ENODEV;
> - }
> -
> - dev_info(&pdev->dev, "%s vpss probed\n", platform_name);
> - oper_cfg.vpss_regs_base0 = devm_platform_ioremap_resource(pdev, 0);
> - if (IS_ERR(oper_cfg.vpss_regs_base0))
> - return PTR_ERR(oper_cfg.vpss_regs_base0);
> -
> - if (oper_cfg.platform == DM355 || oper_cfg.platform == DM365) {
> - oper_cfg.vpss_regs_base1 = devm_platform_ioremap_resource(pdev, 1);
> - if (IS_ERR(oper_cfg.vpss_regs_base1))
> - return PTR_ERR(oper_cfg.vpss_regs_base1);
> - }
> -
> - if (oper_cfg.platform == DM355) {
> - oper_cfg.hw_ops.enable_clock = dm355_enable_clock;
> - oper_cfg.hw_ops.select_ccdc_source = dm355_select_ccdc_source;
> - /* Setup vpss interrupts */
> - bl_regw(DM355_VPSSBL_INTSEL_DEFAULT, DM355_VPSSBL_INTSEL);
> - bl_regw(DM355_VPSSBL_EVTSEL_DEFAULT, DM355_VPSSBL_EVTSEL);
> - } else if (oper_cfg.platform == DM365) {
> - oper_cfg.hw_ops.enable_clock = dm365_enable_clock;
> - oper_cfg.hw_ops.select_ccdc_source = dm365_select_ccdc_source;
> - /* Setup vpss interrupts */
> - isp5_write((isp5_read(DM365_ISP5_PCCR) |
> - DM365_ISP5_PCCR_BL_CLK_ENABLE |
> - DM365_ISP5_PCCR_ISIF_CLK_ENABLE |
> - DM365_ISP5_PCCR_H3A_CLK_ENABLE |
> - DM365_ISP5_PCCR_RSZ_CLK_ENABLE |
> - DM365_ISP5_PCCR_IPIPE_CLK_ENABLE |
> - DM365_ISP5_PCCR_IPIPEIF_CLK_ENABLE |
> - DM365_ISP5_PCCR_RSV), DM365_ISP5_PCCR);
> - isp5_write((isp5_read(DM365_ISP5_BCR) |
> - DM365_ISP5_BCR_ISIF_OUT_ENABLE), DM365_ISP5_BCR);
> - isp5_write(DM365_ISP5_INTSEL1_DEFAULT, DM365_ISP5_INTSEL1);
> - isp5_write(DM365_ISP5_INTSEL2_DEFAULT, DM365_ISP5_INTSEL2);
> - isp5_write(DM365_ISP5_INTSEL3_DEFAULT, DM365_ISP5_INTSEL3);
> - } else
> - oper_cfg.hw_ops.clear_wbl_overflow = dm644x_clear_wbl_overflow;
> -
> - pm_runtime_enable(&pdev->dev);
> -
> - pm_runtime_get(&pdev->dev);
> -
> - spin_lock_init(&oper_cfg.vpss_lock);
> - dev_info(&pdev->dev, "%s vpss probe success\n", platform_name);
> -
> - return 0;
> -}
> -
> -static int vpss_remove(struct platform_device *pdev)
> -{
> - pm_runtime_disable(&pdev->dev);
> - return 0;
> -}
> -
> -static int vpss_suspend(struct device *dev)
> -{
> - pm_runtime_put(dev);
> - return 0;
> -}
> -
> -static int vpss_resume(struct device *dev)
> -{
> - pm_runtime_get(dev);
> - return 0;
> -}
> -
> -static const struct dev_pm_ops vpss_pm_ops = {
> - .suspend = vpss_suspend,
> - .resume = vpss_resume,
> -};
> -
> -static struct platform_driver vpss_driver = {
> - .driver = {
> - .name = "vpss",
> - .pm = &vpss_pm_ops,
> - },
> - .remove = vpss_remove,
> - .probe = vpss_probe,
> -};
> -
> -static void vpss_exit(void)
> -{
> - platform_driver_unregister(&vpss_driver);
> - iounmap(oper_cfg.vpss_regs_base2);
> - release_mem_region(VPSS_CLK_CTRL, 4);
> -}
> -
> -static int __init vpss_init(void)
> -{
> - int ret;
> -
> - if (!request_mem_region(VPSS_CLK_CTRL, 4, "vpss_clock_control"))
> - return -EBUSY;
> -
> - oper_cfg.vpss_regs_base2 = ioremap(VPSS_CLK_CTRL, 4);
> - if (unlikely(!oper_cfg.vpss_regs_base2)) {
> - ret = -ENOMEM;
> - goto err_ioremap;
> - }
> -
> - writel(VPSS_CLK_CTRL_VENCCLKEN |
> - VPSS_CLK_CTRL_DACCLKEN, oper_cfg.vpss_regs_base2);
> -
> - ret = platform_driver_register(&vpss_driver);
> - if (ret)
> - goto err_pd_register;
> -
> - return 0;
> -
> -err_pd_register:
> - iounmap(oper_cfg.vpss_regs_base2);
> -err_ioremap:
> - release_mem_region(VPSS_CLK_CTRL, 4);
> - return ret;
> -}
> -subsys_initcall(vpss_init);
> -module_exit(vpss_exit);
> diff --git a/include/media/davinci/vpbe.h b/include/media/davinci/vpbe.h
> deleted file mode 100644
> index e74a93475d21..000000000000
> --- a/include/media/davinci/vpbe.h
> +++ /dev/null
> @@ -1,184 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * Copyright (C) 2010 Texas Instruments Inc
> - */
> -#ifndef _VPBE_H
> -#define _VPBE_H
> -
> -#include <linux/videodev2.h>
> -#include <linux/i2c.h>
> -
> -#include <media/v4l2-dev.h>
> -#include <media/v4l2-ioctl.h>
> -#include <media/v4l2-device.h>
> -#include <media/davinci/vpbe_osd.h>
> -#include <media/davinci/vpbe_venc.h>
> -#include <media/davinci/vpbe_types.h>
> -
> -/* OSD configuration info */
> -struct osd_config_info {
> - char module_name[32];
> -};
> -
> -struct vpbe_output {
> - struct v4l2_output output;
> - /*
> - * If output capabilities include dv_timings, list supported timings
> - * below
> - */
> - char *subdev_name;
> - /*
> - * defualt_mode identifies the default timings set at the venc or
> - * external encoder.
> - */
> - char *default_mode;
> - /*
> - * Fields below are used for supporting multiple modes. For example,
> - * LCD panel might support different modes and they are listed here.
> - * Similarly for supporting external encoders, lcd controller port
> - * requires a set of non-standard timing values to be listed here for
> - * each supported mode since venc is used in non-standard timing mode
> - * for interfacing with external encoder similar to configuring lcd
> - * panel timings
> - */
> - unsigned int num_modes;
> - struct vpbe_enc_mode_info *modes;
> - /*
> - * Bus configuration goes here for external encoders. Some encoders
> - * may require multiple interface types for each of the output. For
> - * example, SD modes would use YCC8 where as HD mode would use YCC16.
> - * Not sure if this is needed on a per mode basis instead of per
> - * output basis. If per mode is needed, we may have to move this to
> - * mode_info structure
> - */
> - u32 if_params;
> -};
> -
> -/* encoder configuration info */
> -struct encoder_config_info {
> - char module_name[32];
> - /* Is this an i2c device ? */
> - unsigned int is_i2c:1;
> - /* i2c subdevice board info */
> - struct i2c_board_info board_info;
> -};
> -
> -/*amplifier configuration info */
> -struct amp_config_info {
> - char module_name[32];
> - /* Is this an i2c device ? */
> - unsigned int is_i2c:1;
> - /* i2c subdevice board info */
> - struct i2c_board_info board_info;
> -};
> -
> -/* structure for defining vpbe display subsystem components */
> -struct vpbe_config {
> - char module_name[32];
> - /* i2c bus adapter no */
> - int i2c_adapter_id;
> - struct osd_config_info osd;
> - struct encoder_config_info venc;
> - /* external encoder information goes here */
> - int num_ext_encoders;
> - struct encoder_config_info *ext_encoders;
> - /* amplifier information goes here */
> - struct amp_config_info *amp;
> - unsigned int num_outputs;
> - /* Order is venc outputs followed by LCD and then external encoders */
> - struct vpbe_output *outputs;
> -};
> -
> -struct vpbe_device;
> -
> -struct vpbe_device_ops {
> - /* Enumerate the outputs */
> - int (*enum_outputs)(struct vpbe_device *vpbe_dev,
> - struct v4l2_output *output);
> -
> - /* Set output to the given index */
> - int (*set_output)(struct vpbe_device *vpbe_dev,
> - int index);
> -
> - /* Get current output */
> - unsigned int (*get_output)(struct vpbe_device *vpbe_dev);
> -
> - /* Set DV preset at current output */
> - int (*s_dv_timings)(struct vpbe_device *vpbe_dev,
> - struct v4l2_dv_timings *dv_timings);
> -
> - /* Get DV presets supported at the output */
> - int (*g_dv_timings)(struct vpbe_device *vpbe_dev,
> - struct v4l2_dv_timings *dv_timings);
> -
> - /* Enumerate the DV Presets supported at the output */
> - int (*enum_dv_timings)(struct vpbe_device *vpbe_dev,
> - struct v4l2_enum_dv_timings *timings_info);
> -
> - /* Set std at the output */
> - int (*s_std)(struct vpbe_device *vpbe_dev, v4l2_std_id std_id);
> -
> - /* Get the current std at the output */
> - int (*g_std)(struct vpbe_device *vpbe_dev, v4l2_std_id *std_id);
> -
> - /* initialize the device */
> - int (*initialize)(struct device *dev, struct vpbe_device *vpbe_dev);
> -
> - /* De-initialize the device */
> - void (*deinitialize)(struct device *dev, struct vpbe_device *vpbe_dev);
> -
> - /* Get the current mode info */
> - int (*get_mode_info)(struct vpbe_device *vpbe_dev,
> - struct vpbe_enc_mode_info*);
> -
> - /*
> - * Set the current mode in the encoder. Alternate way of setting
> - * standard or DV preset or custom timings in the encoder
> - */
> - int (*set_mode)(struct vpbe_device *vpbe_dev,
> - struct vpbe_enc_mode_info*);
> - /* Power management operations */
> - int (*suspend)(struct vpbe_device *vpbe_dev);
> - int (*resume)(struct vpbe_device *vpbe_dev);
> -};
> -
> -/* struct for vpbe device */
> -struct vpbe_device {
> - /* V4l2 device */
> - struct v4l2_device v4l2_dev;
> - /* vpbe dispay controller cfg */
> - struct vpbe_config *cfg;
> - /* parent device */
> - struct device *pdev;
> - /* external encoder v4l2 sub devices */
> - struct v4l2_subdev **encoders;
> - /* current encoder index */
> - int current_sd_index;
> - /* external amplifier v4l2 subdevice */
> - struct v4l2_subdev *amp;
> - struct mutex lock;
> - /* device initialized */
> - int initialized;
> - /* vpbe dac clock */
> - struct clk *dac_clk;
> - /* osd_device pointer */
> - struct osd_state *osd_device;
> - /* venc device pointer */
> - struct venc_platform_data *venc_device;
> - /*
> - * fields below are accessed by users of vpbe_device. Not the
> - * ones above
> - */
> -
> - /* current output */
> - int current_out_index;
> - /* lock used by caller to do atomic operation on vpbe device */
> - /* current timings set in the controller */
> - struct vpbe_enc_mode_info current_timings;
> - /* venc sub device */
> - struct v4l2_subdev *venc;
> - /* device operations below */
> - struct vpbe_device_ops ops;
> -};
> -
> -#endif
> diff --git a/include/media/davinci/vpbe_display.h b/include/media/davinci/vpbe_display.h
> deleted file mode 100644
> index d8751ea926a2..000000000000
> --- a/include/media/davinci/vpbe_display.h
> +++ /dev/null
> @@ -1,122 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
> - */
> -#ifndef VPBE_DISPLAY_H
> -#define VPBE_DISPLAY_H
> -
> -/* Header files */
> -#include <linux/videodev2.h>
> -#include <media/v4l2-common.h>
> -#include <media/v4l2-fh.h>
> -#include <media/videobuf2-v4l2.h>
> -#include <media/videobuf2-dma-contig.h>
> -#include <media/davinci/vpbe_types.h>
> -#include <media/davinci/vpbe_osd.h>
> -#include <media/davinci/vpbe.h>
> -
> -#define VPBE_DISPLAY_MAX_DEVICES 2
> -
> -enum vpbe_display_device_id {
> - VPBE_DISPLAY_DEVICE_0,
> - VPBE_DISPLAY_DEVICE_1
> -};
> -
> -#define VPBE_DISPLAY_DRV_NAME "vpbe-display"
> -
> -#define VPBE_DISPLAY_MAJOR_RELEASE 1
> -#define VPBE_DISPLAY_MINOR_RELEASE 0
> -#define VPBE_DISPLAY_BUILD 1
> -#define VPBE_DISPLAY_VERSION_CODE ((VPBE_DISPLAY_MAJOR_RELEASE << 16) | \
> - (VPBE_DISPLAY_MINOR_RELEASE << 8) | \
> - VPBE_DISPLAY_BUILD)
> -
> -#define VPBE_DISPLAY_VALID_FIELD(field) ((V4L2_FIELD_NONE == field) || \
> - (V4L2_FIELD_ANY == field) || (V4L2_FIELD_INTERLACED == field))
> -
> -/* Exp ratio numerator and denominator constants */
> -#define VPBE_DISPLAY_H_EXP_RATIO_N 9
> -#define VPBE_DISPLAY_H_EXP_RATIO_D 8
> -#define VPBE_DISPLAY_V_EXP_RATIO_N 6
> -#define VPBE_DISPLAY_V_EXP_RATIO_D 5
> -
> -/* Zoom multiplication factor */
> -#define VPBE_DISPLAY_ZOOM_4X 4
> -#define VPBE_DISPLAY_ZOOM_2X 2
> -
> -/* Structures */
> -struct display_layer_info {
> - int enable;
> - /* Layer ID used by Display Manager */
> - enum osd_layer id;
> - struct osd_layer_config config;
> - enum osd_zoom_factor h_zoom;
> - enum osd_zoom_factor v_zoom;
> - enum osd_h_exp_ratio h_exp;
> - enum osd_v_exp_ratio v_exp;
> -};
> -
> -struct vpbe_disp_buffer {
> - struct vb2_v4l2_buffer vb;
> - struct list_head list;
> -};
> -
> -/* vpbe display object structure */
> -struct vpbe_layer {
> - /* Pointer to the vpbe_display */
> - struct vpbe_display *disp_dev;
> - /* Pointer pointing to current v4l2_buffer */
> - struct vpbe_disp_buffer *cur_frm;
> - /* Pointer pointing to next v4l2_buffer */
> - struct vpbe_disp_buffer *next_frm;
> - /* vb2 specific parameters
> - * Buffer queue used in vb2
> - */
> - struct vb2_queue buffer_queue;
> - /* Queue of filled frames */
> - struct list_head dma_queue;
> - /* Used for video buffer handling */
> - spinlock_t irqlock;
> - /* V4l2 specific parameters */
> - /* Identifies video device for this layer */
> - struct video_device video_dev;
> - /* Used to store pixel format */
> - struct v4l2_pix_format pix_fmt;
> - enum v4l2_field buf_field;
> - /* Video layer configuration params */
> - struct display_layer_info layer_info;
> - /* vpbe specific parameters
> - * enable window for display
> - */
> - unsigned char window_enable;
> - /* number of open instances of the layer */
> - unsigned int usrs;
> - /* Indicates id of the field which is being displayed */
> - unsigned int field_id;
> - /* Identifies device object */
> - enum vpbe_display_device_id device_id;
> - /* facilitation of ioctl ops lock by v4l2*/
> - struct mutex opslock;
> - u8 layer_first_int;
> -};
> -
> -/* vpbe device structure */
> -struct vpbe_display {
> - /* layer specific parameters */
> - /* lock for isr updates to buf layers*/
> - spinlock_t dma_queue_lock;
> - /* C-Plane offset from start of y-plane */
> - unsigned int cbcr_ofst;
> - struct vpbe_layer *dev[VPBE_DISPLAY_MAX_DEVICES];
> - struct vpbe_device *vpbe_dev;
> - struct osd_state *osd_device;
> -};
> -
> -struct buf_config_params {
> - unsigned char min_numbuffers;
> - unsigned char numbuffers[VPBE_DISPLAY_MAX_DEVICES];
> - unsigned int min_bufsize[VPBE_DISPLAY_MAX_DEVICES];
> - unsigned int layer_bufsize[VPBE_DISPLAY_MAX_DEVICES];
> -};
> -
> -#endif /* VPBE_DISPLAY_H */
> diff --git a/include/media/davinci/vpbe_osd.h b/include/media/davinci/vpbe_osd.h
> deleted file mode 100644
> index a4fc4f2a56fb..000000000000
> --- a/include/media/davinci/vpbe_osd.h
> +++ /dev/null
> @@ -1,382 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * Copyright (C) 2007-2009 Texas Instruments Inc
> - * Copyright (C) 2007 MontaVista Software, Inc.
> - *
> - * Andy Lowe (alowe@mvista.com), MontaVista Software
> - * - Initial version
> - * Murali Karicheri (mkaricheri@gmail.com), Texas Instruments Ltd.
> - * - ported to sub device interface
> - */
> -#ifndef _OSD_H
> -#define _OSD_H
> -
> -#include <media/davinci/vpbe_types.h>
> -
> -#define DM644X_VPBE_OSD_SUBDEV_NAME "dm644x,vpbe-osd"
> -#define DM365_VPBE_OSD_SUBDEV_NAME "dm365,vpbe-osd"
> -#define DM355_VPBE_OSD_SUBDEV_NAME "dm355,vpbe-osd"
> -
> -/**
> - * enum osd_layer
> - * @WIN_OSD0: On-Screen Display Window 0
> - * @WIN_VID0: Video Window 0
> - * @WIN_OSD1: On-Screen Display Window 1
> - * @WIN_VID1: Video Window 1
> - *
> - * Description:
> - * An enumeration of the osd display layers.
> - */
> -enum osd_layer {
> - WIN_OSD0,
> - WIN_VID0,
> - WIN_OSD1,
> - WIN_VID1,
> -};
> -
> -/**
> - * enum osd_win_layer
> - * @OSDWIN_OSD0: On-Screen Display Window 0
> - * @OSDWIN_OSD1: On-Screen Display Window 1
> - *
> - * Description:
> - * An enumeration of the OSD Window layers.
> - */
> -enum osd_win_layer {
> - OSDWIN_OSD0,
> - OSDWIN_OSD1,
> -};
> -
> -/**
> - * enum osd_pix_format
> - * @PIXFMT_1BPP: 1-bit-per-pixel bitmap
> - * @PIXFMT_2BPP: 2-bits-per-pixel bitmap
> - * @PIXFMT_4BPP: 4-bits-per-pixel bitmap
> - * @PIXFMT_8BPP: 8-bits-per-pixel bitmap
> - * @PIXFMT_RGB565: 16-bits-per-pixel RGB565
> - * @PIXFMT_YCBCRI: YUV 4:2:2
> - * @PIXFMT_RGB888: 24-bits-per-pixel RGB888
> - * @PIXFMT_YCRCBI: YUV 4:2:2 with chroma swap
> - * @PIXFMT_NV12: YUV 4:2:0 planar
> - * @PIXFMT_OSD_ATTR: OSD Attribute Window pixel format (4bpp)
> - *
> - * Description:
> - * An enumeration of the DaVinci pixel formats.
> - */
> -enum osd_pix_format {
> - PIXFMT_1BPP = 0,
> - PIXFMT_2BPP,
> - PIXFMT_4BPP,
> - PIXFMT_8BPP,
> - PIXFMT_RGB565,
> - PIXFMT_YCBCRI,
> - PIXFMT_RGB888,
> - PIXFMT_YCRCBI,
> - PIXFMT_NV12,
> - PIXFMT_OSD_ATTR,
> -};
> -
> -/**
> - * enum osd_h_exp_ratio
> - * @H_EXP_OFF: no expansion (1/1)
> - * @H_EXP_9_OVER_8: 9/8 expansion ratio
> - * @H_EXP_3_OVER_2: 3/2 expansion ratio
> - *
> - * Description:
> - * An enumeration of the available horizontal expansion ratios.
> - */
> -enum osd_h_exp_ratio {
> - H_EXP_OFF,
> - H_EXP_9_OVER_8,
> - H_EXP_3_OVER_2,
> -};
> -
> -/**
> - * enum osd_v_exp_ratio
> - * @V_EXP_OFF: no expansion (1/1)
> - * @V_EXP_6_OVER_5: 6/5 expansion ratio
> - *
> - * Description:
> - * An enumeration of the available vertical expansion ratios.
> - */
> -enum osd_v_exp_ratio {
> - V_EXP_OFF,
> - V_EXP_6_OVER_5,
> -};
> -
> -/**
> - * enum osd_zoom_factor
> - * @ZOOM_X1: no zoom (x1)
> - * @ZOOM_X2: x2 zoom
> - * @ZOOM_X4: x4 zoom
> - *
> - * Description:
> - * An enumeration of the available zoom factors.
> - */
> -enum osd_zoom_factor {
> - ZOOM_X1,
> - ZOOM_X2,
> - ZOOM_X4,
> -};
> -
> -/**
> - * enum osd_clut
> - * @ROM_CLUT: ROM CLUT
> - * @RAM_CLUT: RAM CLUT
> - *
> - * Description:
> - * An enumeration of the available Color Lookup Tables (CLUTs).
> - */
> -enum osd_clut {
> - ROM_CLUT,
> - RAM_CLUT,
> -};
> -
> -/**
> - * enum osd_rom_clut
> - * @ROM_CLUT0: Macintosh CLUT
> - * @ROM_CLUT1: CLUT from DM270 and prior devices
> - *
> - * Description:
> - * An enumeration of the ROM Color Lookup Table (CLUT) options.
> - */
> -enum osd_rom_clut {
> - ROM_CLUT0,
> - ROM_CLUT1,
> -};
> -
> -/**
> - * enum osd_blending_factor
> - * @OSD_0_VID_8: OSD pixels are fully transparent
> - * @OSD_1_VID_7: OSD pixels contribute 1/8, video pixels contribute 7/8
> - * @OSD_2_VID_6: OSD pixels contribute 2/8, video pixels contribute 6/8
> - * @OSD_3_VID_5: OSD pixels contribute 3/8, video pixels contribute 5/8
> - * @OSD_4_VID_4: OSD pixels contribute 4/8, video pixels contribute 4/8
> - * @OSD_5_VID_3: OSD pixels contribute 5/8, video pixels contribute 3/8
> - * @OSD_6_VID_2: OSD pixels contribute 6/8, video pixels contribute 2/8
> - * @OSD_8_VID_0: OSD pixels are fully opaque
> - *
> - * Description:
> - * An enumeration of the DaVinci pixel blending factor options.
> - */
> -enum osd_blending_factor {
> - OSD_0_VID_8,
> - OSD_1_VID_7,
> - OSD_2_VID_6,
> - OSD_3_VID_5,
> - OSD_4_VID_4,
> - OSD_5_VID_3,
> - OSD_6_VID_2,
> - OSD_8_VID_0,
> -};
> -
> -/**
> - * enum osd_blink_interval
> - * @BLINK_X1: blink interval is 1 vertical refresh cycle
> - * @BLINK_X2: blink interval is 2 vertical refresh cycles
> - * @BLINK_X3: blink interval is 3 vertical refresh cycles
> - * @BLINK_X4: blink interval is 4 vertical refresh cycles
> - *
> - * Description:
> - * An enumeration of the DaVinci pixel blinking interval options.
> - */
> -enum osd_blink_interval {
> - BLINK_X1,
> - BLINK_X2,
> - BLINK_X3,
> - BLINK_X4,
> -};
> -
> -/**
> - * enum osd_cursor_h_width
> - * @H_WIDTH_1: horizontal line width is 1 pixel
> - * @H_WIDTH_4: horizontal line width is 4 pixels
> - * @H_WIDTH_8: horizontal line width is 8 pixels
> - * @H_WIDTH_12: horizontal line width is 12 pixels
> - * @H_WIDTH_16: horizontal line width is 16 pixels
> - * @H_WIDTH_20: horizontal line width is 20 pixels
> - * @H_WIDTH_24: horizontal line width is 24 pixels
> - * @H_WIDTH_28: horizontal line width is 28 pixels
> - */
> -enum osd_cursor_h_width {
> - H_WIDTH_1,
> - H_WIDTH_4,
> - H_WIDTH_8,
> - H_WIDTH_12,
> - H_WIDTH_16,
> - H_WIDTH_20,
> - H_WIDTH_24,
> - H_WIDTH_28,
> -};
> -
> -/**
> - * enum osd_cursor_v_width
> - * @V_WIDTH_1: vertical line width is 1 line
> - * @V_WIDTH_2: vertical line width is 2 lines
> - * @V_WIDTH_4: vertical line width is 4 lines
> - * @V_WIDTH_6: vertical line width is 6 lines
> - * @V_WIDTH_8: vertical line width is 8 lines
> - * @V_WIDTH_10: vertical line width is 10 lines
> - * @V_WIDTH_12: vertical line width is 12 lines
> - * @V_WIDTH_14: vertical line width is 14 lines
> - */
> -enum osd_cursor_v_width {
> - V_WIDTH_1,
> - V_WIDTH_2,
> - V_WIDTH_4,
> - V_WIDTH_6,
> - V_WIDTH_8,
> - V_WIDTH_10,
> - V_WIDTH_12,
> - V_WIDTH_14,
> -};
> -
> -/**
> - * struct osd_cursor_config
> - * @xsize: horizontal size in pixels
> - * @ysize: vertical size in lines
> - * @xpos: horizontal offset in pixels from the left edge of the display
> - * @ypos: vertical offset in lines from the top of the display
> - * @interlaced: Non-zero if the display is interlaced, or zero otherwise
> - * @h_width: horizontal line width
> - * @v_width: vertical line width
> - * @clut: the CLUT selector (ROM or RAM) for the cursor color
> - * @clut_index: an index into the CLUT for the cursor color
> - *
> - * Description:
> - * A structure describing the configuration parameters of the hardware
> - * rectangular cursor.
> - */
> -struct osd_cursor_config {
> - unsigned xsize;
> - unsigned ysize;
> - unsigned xpos;
> - unsigned ypos;
> - int interlaced;
> - enum osd_cursor_h_width h_width;
> - enum osd_cursor_v_width v_width;
> - enum osd_clut clut;
> - unsigned char clut_index;
> -};
> -
> -/**
> - * struct osd_layer_config
> - * @pixfmt: pixel format
> - * @line_length: offset in bytes between start of each line in memory
> - * @xsize: number of horizontal pixels displayed per line
> - * @ysize: number of lines displayed
> - * @xpos: horizontal offset in pixels from the left edge of the display
> - * @ypos: vertical offset in lines from the top of the display
> - * @interlaced: Non-zero if the display is interlaced, or zero otherwise
> - *
> - * Description:
> - * A structure describing the configuration parameters of an On-Screen Display
> - * (OSD) or video layer related to how the image is stored in memory.
> - * @line_length must be a multiple of the cache line size (32 bytes).
> - */
> -struct osd_layer_config {
> - enum osd_pix_format pixfmt;
> - unsigned line_length;
> - unsigned xsize;
> - unsigned ysize;
> - unsigned xpos;
> - unsigned ypos;
> - int interlaced;
> -};
> -
> -/* parameters that apply on a per-window (OSD or video) basis */
> -struct osd_window_state {
> - int is_allocated;
> - int is_enabled;
> - unsigned long fb_base_phys;
> - enum osd_zoom_factor h_zoom;
> - enum osd_zoom_factor v_zoom;
> - struct osd_layer_config lconfig;
> -};
> -
> -/* parameters that apply on a per-OSD-window basis */
> -struct osd_osdwin_state {
> - enum osd_clut clut;
> - enum osd_blending_factor blend;
> - int colorkey_blending;
> - unsigned colorkey;
> - int rec601_attenuation;
> - /* index is pixel value */
> - unsigned char palette_map[16];
> -};
> -
> -/* hardware rectangular cursor parameters */
> -struct osd_cursor_state {
> - int is_enabled;
> - struct osd_cursor_config config;
> -};
> -
> -struct osd_state;
> -
> -struct vpbe_osd_ops {
> - int (*initialize)(struct osd_state *sd);
> - int (*request_layer)(struct osd_state *sd, enum osd_layer layer);
> - void (*release_layer)(struct osd_state *sd, enum osd_layer layer);
> - int (*enable_layer)(struct osd_state *sd, enum osd_layer layer,
> - int otherwin);
> - void (*disable_layer)(struct osd_state *sd, enum osd_layer layer);
> - int (*set_layer_config)(struct osd_state *sd, enum osd_layer layer,
> - struct osd_layer_config *lconfig);
> - void (*get_layer_config)(struct osd_state *sd, enum osd_layer layer,
> - struct osd_layer_config *lconfig);
> - void (*start_layer)(struct osd_state *sd, enum osd_layer layer,
> - unsigned long fb_base_phys,
> - unsigned long cbcr_ofst);
> - void (*set_left_margin)(struct osd_state *sd, u32 val);
> - void (*set_top_margin)(struct osd_state *sd, u32 val);
> - void (*set_interpolation_filter)(struct osd_state *sd, int filter);
> - int (*set_vid_expansion)(struct osd_state *sd,
> - enum osd_h_exp_ratio h_exp,
> - enum osd_v_exp_ratio v_exp);
> - void (*get_vid_expansion)(struct osd_state *sd,
> - enum osd_h_exp_ratio *h_exp,
> - enum osd_v_exp_ratio *v_exp);
> - void (*set_zoom)(struct osd_state *sd, enum osd_layer layer,
> - enum osd_zoom_factor h_zoom,
> - enum osd_zoom_factor v_zoom);
> -};
> -
> -struct osd_state {
> - enum vpbe_version vpbe_type;
> - spinlock_t lock;
> - struct device *dev;
> - dma_addr_t osd_base_phys;
> - void __iomem *osd_base;
> - unsigned long osd_size;
> - /* 1-->the isr will toggle the VID0 ping-pong buffer */
> - int pingpong;
> - int interpolation_filter;
> - int field_inversion;
> - enum osd_h_exp_ratio osd_h_exp;
> - enum osd_v_exp_ratio osd_v_exp;
> - enum osd_h_exp_ratio vid_h_exp;
> - enum osd_v_exp_ratio vid_v_exp;
> - enum osd_clut backg_clut;
> - unsigned backg_clut_index;
> - enum osd_rom_clut rom_clut;
> - int is_blinking;
> - /* attribute window blinking enabled */
> - enum osd_blink_interval blink;
> - /* YCbCrI or YCrCbI */
> - enum osd_pix_format yc_pixfmt;
> - /* columns are Y, Cb, Cr */
> - unsigned char clut_ram[256][3];
> - struct osd_cursor_state cursor;
> - /* OSD0, VID0, OSD1, VID1 */
> - struct osd_window_state win[4];
> - /* OSD0, OSD1 */
> - struct osd_osdwin_state osdwin[2];
> - /* OSD device Operations */
> - struct vpbe_osd_ops ops;
> -};
> -
> -struct osd_platform_data {
> - int field_inv_wa_enable;
> -};
> -
> -#endif
> diff --git a/include/media/davinci/vpbe_types.h b/include/media/davinci/vpbe_types.h
> deleted file mode 100644
> index 6015cda235cc..000000000000
> --- a/include/media/davinci/vpbe_types.h
> +++ /dev/null
> @@ -1,74 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * Copyright (C) 2010 Texas Instruments Inc
> - */
> -#ifndef _VPBE_TYPES_H
> -#define _VPBE_TYPES_H
> -
> -enum vpbe_version {
> - VPBE_VERSION_1 = 1,
> - VPBE_VERSION_2,
> - VPBE_VERSION_3,
> -};
> -
> -/* vpbe_timing_type - Timing types used in vpbe device */
> -enum vpbe_enc_timings_type {
> - VPBE_ENC_STD = 0x1,
> - VPBE_ENC_DV_TIMINGS = 0x4,
> - /* Used when set timings through FB device interface */
> - VPBE_ENC_TIMINGS_INVALID = 0x8,
> -};
> -
> -/*
> - * struct vpbe_enc_mode_info
> - * @name: ptr to name string of the standard, "NTSC", "PAL" etc
> - * @std: standard or non-standard mode. 1 - standard, 0 - nonstandard
> - * @interlaced: 1 - interlaced, 0 - non interlaced/progressive
> - * @xres: x or horizontal resolution of the display
> - * @yres: y or vertical resolution of the display
> - * @fps: frame per second
> - * @left_margin: left margin of the display
> - * @right_margin: right margin of the display
> - * @upper_margin: upper margin of the display
> - * @lower_margin: lower margin of the display
> - * @hsync_len: h-sync length
> - * @vsync_len: v-sync length
> - * @flags: bit field: bit usage is documented below
> - *
> - * Description:
> - * Structure holding timing and resolution information of a standard.
> - * Used by vpbe_device to set required non-standard timing in the
> - * venc when lcd controller output is connected to a external encoder.
> - * A table of timings is maintained in vpbe device to set this in
> - * venc when external encoder is connected to lcd controller output.
> - * Encoder may provide a g_dv_timings() API to override these values
> - * as needed.
> - *
> - * Notes
> - * ------
> - * if_type should be used only by encoder manager and encoder.
> - * flags usage
> - * b0 (LSB) - hsync polarity, 0 - negative, 1 - positive
> - * b1 - vsync polarity, 0 - negative, 1 - positive
> - * b2 - field id polarity, 0 - negative, 1 - positive
> - */
> -struct vpbe_enc_mode_info {
> - unsigned char *name;
> - enum vpbe_enc_timings_type timings_type;
> - v4l2_std_id std_id;
> - struct v4l2_dv_timings dv_timings;
> - unsigned int interlaced;
> - unsigned int xres;
> - unsigned int yres;
> - struct v4l2_fract aspect;
> - struct v4l2_fract fps;
> - unsigned int left_margin;
> - unsigned int right_margin;
> - unsigned int upper_margin;
> - unsigned int lower_margin;
> - unsigned int hsync_len;
> - unsigned int vsync_len;
> - unsigned int flags;
> -};
> -
> -#endif
> diff --git a/include/media/davinci/vpbe_venc.h b/include/media/davinci/vpbe_venc.h
> deleted file mode 100644
> index 93cf6a5fb49d..000000000000
> --- a/include/media/davinci/vpbe_venc.h
> +++ /dev/null
> @@ -1,37 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * Copyright (C) 2010 Texas Instruments Inc
> - */
> -#ifndef _VPBE_VENC_H
> -#define _VPBE_VENC_H
> -
> -#include <media/v4l2-subdev.h>
> -#include <media/davinci/vpbe_types.h>
> -
> -#define DM644X_VPBE_VENC_SUBDEV_NAME "dm644x,vpbe-venc"
> -#define DM365_VPBE_VENC_SUBDEV_NAME "dm365,vpbe-venc"
> -#define DM355_VPBE_VENC_SUBDEV_NAME "dm355,vpbe-venc"
> -
> -/* venc events */
> -#define VENC_END_OF_FRAME BIT(0)
> -#define VENC_FIRST_FIELD BIT(1)
> -#define VENC_SECOND_FIELD BIT(2)
> -
> -struct venc_platform_data {
> - int (*setup_pinmux)(u32 if_type, int field);
> - int (*setup_clock)(enum vpbe_enc_timings_type type,
> - unsigned int pixclock);
> - int (*setup_if_config)(u32 pixcode);
> - /* Number of LCD outputs supported */
> - int num_lcd_outputs;
> - struct vpbe_if_params *lcd_if_params;
> -};
> -
> -enum venc_ioctls {
> - VENC_GET_FLD = 1,
> -};
> -
> -/* exported functions */
> -struct v4l2_subdev *venc_sub_dev_init(struct v4l2_device *v4l2_dev,
> - const char *venc_name);
> -#endif
> diff --git a/include/media/davinci/vpss.h b/include/media/davinci/vpss.h
> deleted file mode 100644
> index 315fa77e238c..000000000000
> --- a/include/media/davinci/vpss.h
> +++ /dev/null
> @@ -1,111 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-or-later */
> -/*
> - * Copyright (C) 2009 Texas Instruments Inc
> - *
> - * vpss - video processing subsystem module header file.
> - *
> - * Include this header file if a driver needs to configure vpss system
> - * module. It exports a set of library functions for video drivers to
> - * configure vpss system module functions such as clock enable/disable,
> - * vpss interrupt mux to arm, and other common vpss system module
> - * functions.
> - */
> -#ifndef _VPSS_H
> -#define _VPSS_H
> -
> -/* selector for ccdc input selection on DM355 */
> -enum vpss_ccdc_source_sel {
> - VPSS_CCDCIN,
> - VPSS_HSSIIN,
> - VPSS_PGLPBK, /* for DM365 only */
> - VPSS_CCDCPG /* for DM365 only */
> -};
> -
> -struct vpss_sync_pol {
> - unsigned int ccdpg_hdpol:1;
> - unsigned int ccdpg_vdpol:1;
> -};
> -
> -struct vpss_pg_frame_size {
> - short hlpfr;
> - short pplen;
> -};
> -
> -/* Used for enable/disable VPSS Clock */
> -enum vpss_clock_sel {
> - /* DM355/DM365 */
> - VPSS_CCDC_CLOCK,
> - VPSS_IPIPE_CLOCK,
> - VPSS_H3A_CLOCK,
> - VPSS_CFALD_CLOCK,
> - /*
> - * When using VPSS_VENC_CLOCK_SEL in vpss_enable_clock() api
> - * following applies:-
> - * en = 0 selects ENC_CLK
> - * en = 1 selects ENC_CLK/2
> - */
> - VPSS_VENC_CLOCK_SEL,
> - VPSS_VPBE_CLOCK,
> - /* DM365 only clocks */
> - VPSS_IPIPEIF_CLOCK,
> - VPSS_RSZ_CLOCK,
> - VPSS_BL_CLOCK,
> - /*
> - * When using VPSS_PCLK_INTERNAL in vpss_enable_clock() api
> - * following applies:-
> - * en = 0 disable internal PCLK
> - * en = 1 enables internal PCLK
> - */
> - VPSS_PCLK_INTERNAL,
> - /*
> - * When using VPSS_PSYNC_CLOCK_SEL in vpss_enable_clock() api
> - * following applies:-
> - * en = 0 enables MMR clock
> - * en = 1 enables VPSS clock
> - */
> - VPSS_PSYNC_CLOCK_SEL,
> - VPSS_LDC_CLOCK_SEL,
> - VPSS_OSD_CLOCK_SEL,
> - VPSS_FDIF_CLOCK,
> - VPSS_LDC_CLOCK
> -};
> -
> -/* select input to ccdc on dm355 */
> -int vpss_select_ccdc_source(enum vpss_ccdc_source_sel src_sel);
> -/* enable/disable a vpss clock, 0 - success, -1 - failure */
> -int vpss_enable_clock(enum vpss_clock_sel clock_sel, int en);
> -/* set sync polarity, only for DM365*/
> -void dm365_vpss_set_sync_pol(struct vpss_sync_pol);
> -/* set the PG_FRAME_SIZE register, only for DM365 */
> -void dm365_vpss_set_pg_frame_size(struct vpss_pg_frame_size);
> -
> -/* wbl reset for dm644x */
> -enum vpss_wbl_sel {
> - VPSS_PCR_AEW_WBL_0 = 16,
> - VPSS_PCR_AF_WBL_0,
> - VPSS_PCR_RSZ4_WBL_0,
> - VPSS_PCR_RSZ3_WBL_0,
> - VPSS_PCR_RSZ2_WBL_0,
> - VPSS_PCR_RSZ1_WBL_0,
> - VPSS_PCR_PREV_WBL_0,
> - VPSS_PCR_CCDC_WBL_O,
> -};
> -/* clear wbl overflow flag for DM6446 */
> -int vpss_clear_wbl_overflow(enum vpss_wbl_sel wbl_sel);
> -
> -/* set sync polarity*/
> -void vpss_set_sync_pol(struct vpss_sync_pol sync);
> -/* set the PG_FRAME_SIZE register */
> -void vpss_set_pg_frame_size(struct vpss_pg_frame_size frame_size);
> -/*
> - * vpss_check_and_clear_interrupt - check and clear interrupt
> - * @irq - common enumerator for IRQ
> - *
> - * Following return values used:-
> - * 0 - interrupt occurred and cleared
> - * 1 - interrupt not occurred
> - * 2 - interrupt status not available
> - */
> -int vpss_dma_complete_interrupt(void);
> -
> -#endif
^ permalink raw reply [flat|nested] 48+ messages in thread* Re: [PATCH 14/14] media: davinci: remove vpbe support
2022-10-19 15:29 ` [PATCH 14/14] media: davinci: remove vpbe support Arnd Bergmann
2022-10-24 11:03 ` Hans Verkuil
@ 2022-10-25 22:22 ` Lad, Prabhakar
1 sibling, 0 replies; 48+ messages in thread
From: Lad, Prabhakar @ 2022-10-25 22:22 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Sekhar Nori, Bartosz Golaszewski, linux-arm-kernel,
Mauro Carvalho Chehab, linux-kernel, Kevin Hilman, Arnd Bergmann,
Hans Verkuil, linux-media
On Wed, Oct 19, 2022 at 4:41 PM Arnd Bergmann <arnd@kernel.org> wrote:
>
> From: Arnd Bergmann <arnd@arndb.de>
>
> The davinci dm3xx/dm644x platforms are gone now, and the remaining
> da8xx platforms do not use the vpbe driver, so the driver can be
> removed as well.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Lad Prabhakar <prabhakar.csengg@gmail.com>
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 00/14] ARM: remove unused davinci board & drivers
2022-10-19 15:29 [PATCH 00/14] ARM: remove unused davinci board & drivers Arnd Bergmann
` (13 preceding siblings ...)
2022-10-19 15:29 ` [PATCH 14/14] media: davinci: remove vpbe support Arnd Bergmann
@ 2022-10-19 15:39 ` Marc Zyngier
2022-10-24 18:25 ` Kevin Hilman
2022-11-14 21:08 ` Alexandre Belloni
16 siblings, 0 replies; 48+ messages in thread
From: Marc Zyngier @ 2022-10-19 15:39 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Sekhar Nori, Bartosz Golaszewski, linux-arm-kernel, linux-kernel,
Kevin Hilman, Arnd Bergmann, Russell King, Mauro Carvalho Chehab,
Damien Le Moal, Sergey Shtylyov, David Lechner,
Michael Turquette, Stephen Boyd, Dmitry Torokhov,
Thomas Gleixner, Lad, Prabhakar, Lee Jones, Alessandro Zummo,
Alexandre Belloni, Greg Kroah-Hartman, Bin Liu, Peter Ujfalusi,
Liam Girdwood, Mark Brown, Jaroslav Kysela, Takashi Iwai,
Laurent Pinchart, Hans Verkuil, Yang Yingliang, linux-media,
linux-ide, linux-clk, linux-input, linux-rtc, linux-staging,
linux-usb, alsa-devel
On Wed, 19 Oct 2022 16:29:26 +0100,
Arnd Bergmann <arnd@kernel.org> wrote:
>
> From: Arnd Bergmann <arnd@arndb.de>
>
> As part of removing all board files that were previously marked as unused,
> I looked through the davinci platform and recursively removed everything
> that has now become unused.
>
> In particular, this is for all dm3xx support, in addition to the dm64xx
> support removed previously. The remaining support is now for da8xx using
> devicetree only, which means a lot of the da8xx specific device support
> can also go away.
>
> As with the previous series, I can keep patches together in the
> soc tree, or subsystem maintainers can pick them up individually
> through their subsystems, whichever they prefer.
>
> Arnd Bergmann (14):
[...]
> irqchip: remove davinci aintc driver
Acked-by: Marc Zyngier <maz@kernel.org>
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply [flat|nested] 48+ messages in thread* Re: [PATCH 00/14] ARM: remove unused davinci board & drivers
2022-10-19 15:29 [PATCH 00/14] ARM: remove unused davinci board & drivers Arnd Bergmann
` (14 preceding siblings ...)
2022-10-19 15:39 ` [PATCH 00/14] ARM: remove unused davinci board & drivers Marc Zyngier
@ 2022-10-24 18:25 ` Kevin Hilman
2022-11-14 21:08 ` Alexandre Belloni
16 siblings, 0 replies; 48+ messages in thread
From: Kevin Hilman @ 2022-10-24 18:25 UTC (permalink / raw)
To: Arnd Bergmann, Sekhar Nori, Bartosz Golaszewski, linux-arm-kernel
Cc: linux-kernel, Arnd Bergmann, Russell King, Mauro Carvalho Chehab,
Damien Le Moal, Sergey Shtylyov, David Lechner,
Michael Turquette, Stephen Boyd, Dmitry Torokhov,
Thomas Gleixner, Marc Zyngier, Lad, Prabhakar, Lee Jones,
Alessandro Zummo, Alexandre Belloni, Greg Kroah-Hartman, Bin Liu,
Peter Ujfalusi, Liam Girdwood, Mark Brown, Jaroslav Kysela,
Takashi Iwai, Laurent Pinchart, Hans Verkuil, Yang Yingliang,
linux-media, linux-ide, linux-clk, linux-input, linux-rtc,
linux-staging, linux-usb, alsa-devel
Arnd Bergmann <arnd@kernel.org> writes:
> From: Arnd Bergmann <arnd@arndb.de>
>
> As part of removing all board files that were previously marked as unused,
> I looked through the davinci platform and recursively removed everything
> that has now become unused.
>
> In particular, this is for all dm3xx support, in addition to the dm64xx
> support removed previously. The remaining support is now for da8xx using
> devicetree only, which means a lot of the da8xx specific device support
> can also go away.
Acked-by: Kevin Hilman <khilman@baylibre.com>
Kevin
^ permalink raw reply [flat|nested] 48+ messages in thread* Re: [PATCH 00/14] ARM: remove unused davinci board & drivers
2022-10-19 15:29 [PATCH 00/14] ARM: remove unused davinci board & drivers Arnd Bergmann
` (15 preceding siblings ...)
2022-10-24 18:25 ` Kevin Hilman
@ 2022-11-14 21:08 ` Alexandre Belloni
16 siblings, 0 replies; 48+ messages in thread
From: Alexandre Belloni @ 2022-11-14 21:08 UTC (permalink / raw)
To: Bartosz Golaszewski, Sekhar Nori, Arnd Bergmann, linux-arm-kernel
Cc: linux-staging, Russell King, linux-clk, Marc Zyngier,
Hans Verkuil, Lad, Prabhakar, Lee Jones, linux-media,
linux-input, Mauro Carvalho Chehab, Stephen Boyd,
Laurent Pinchart, Jaroslav Kysela, Alessandro Zummo,
Kevin Hilman, David Lechner, Thomas Gleixner, Mark Brown,
linux-rtc, Dmitry Torokhov, Yang Yingliang, Liam Girdwood,
alsa-devel, Arnd Bergmann, Greg Kroah-Hartman, Damien Le Moal,
Peter Ujfalusi, linux-ide, Sergey Shtylyov, Bin Liu,
Takashi Iwai, linux-usb, linux-kernel, Michael Turquette
On Wed, 19 Oct 2022 17:29:26 +0200, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> As part of removing all board files that were previously marked as unused,
> I looked through the davinci platform and recursively removed everything
> that has now become unused.
>
> In particular, this is for all dm3xx support, in addition to the dm64xx
> support removed previously. The remaining support is now for da8xx using
> devicetree only, which means a lot of the da8xx specific device support
> can also go away.
>
> [...]
Applied, thanks!
[08/14] rtc: remove davinci rtc driver
commit: 6274ef3c7eb5e9792a708c23757e16b444e4267f
Best regards,
--
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply [flat|nested] 48+ messages in thread