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From: Thomas Gleixner <tglx@linutronix.de>
To: Kar Hin Ong <kar.hin.ong@ni.com>, Bjorn Helgaas <helgaas@kernel.org>
Cc: linux-rt-users <linux-rt-users@vger.kernel.org>,
	LKML <linux-kernel@vger.kernel.org>,
	x86@kernel.org,
	"linux-pci\@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"H. Peter Anvin" <hpa@zytor.com>,
	Dave Hansen <dave.hansen@linux.intel.com>,
	Julia Cartwright <julia.cartwright@ni.com>,
	Keng Soon Cheah <keng.soon.cheah@ni.com>
Subject: RE: Re: "oneshot" interrupt causes another interrupt to be fired erroneously in Haswell system
Date: Thu, 16 Jan 2020 00:05:38 +0100	[thread overview]
Message-ID: <87a76oxqv1.fsf@nanos.tec.linutronix.de> (raw)
In-Reply-To: <MN2PR04MB625594021250E0FB92EC955DC3780@MN2PR04MB6255.namprd04.prod.outlook.com>

Kar Hin Ong <kar.hin.ong@ni.com> writes:
>> > > From Intel Xeon Processor E5/E7 v3 Product Family External Design
>> > > Specification (EDS), Volume One: Architecture, section 13.1 (Legacy
>> > > PCI Interrupt Handling), it mention: "If the I/OxAPIC entry is
>> > > masked (via the 'mask' bit in the corresponding Redirection Table
>> > > Entry), then the corresponding PCI Express interrupt(s) is forwarded
>> > > to the legacy PCH"
>> 
>> Oh well. Really useful behaviour - NOT!

Second thoughts on this. This behaviour is intentional to make PCI
interrupts work even when the IOAPIC is not initialized at all.

I don't have access to the document you mentioned, but I know that
chipsets have a knob to control that behaviour. Just checked a few
chipset docs and they contain the same sentence, but then in the next
paragraph they say:

 "If the I/OxAPIC entry is masked (via the mask bit in the corresponding
  Redirection Table Entry), then the corresponding PCI Express
  interrupt(s) is forwarded to the legacy ICH, provided the Disable PCI
  INTx Routing to ICH bit is clear, Section 19.10.2.27, QPIPINTRC: Intel
  QuickPath Interconnect Protocol Interrupt Control."

That control bit is 0 after reset, so the legacy forwarding works.

Another way to avoid this is to use MSI interrupts instead of the legacy
PCI ones, which is recommended for various reasons (including
performance) anyway.

Can you please provide the exact CPU and PCH types and the output of
'lspci -vvv'?

Thanks,

        tglx





  parent reply	other threads:[~2020-01-15 23:05 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-31  3:53 "oneshot" interrupt causes another interrupt to be fired erroneously in Haswell system Kar Hin Ong
2019-10-31 23:05 ` Bjorn Helgaas
2019-11-01  7:46   ` Kar Hin Ong
2019-11-04 23:41   ` Thomas Gleixner
2019-11-07  9:38     ` Kar Hin Ong
2019-11-21 11:22       ` Kar Hin Ong
2020-01-15 23:05       ` Thomas Gleixner [this message]
2020-01-16  7:32         ` Kar Hin Ong
2020-01-16 10:01           ` Thomas Gleixner
2020-01-23  1:37             ` Sean V Kelley
2020-01-23 13:08               ` Thomas Gleixner
2020-02-09 15:37                 ` Thomas Gleixner
2020-02-10 16:32                   ` Sean V Kelley

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