[PATCH net-next 0/2] net: dsa: realtek: fix PHY register read corruption

[PATCH net-next 0/2] net: dsa: realtek: fix PHY register read corruption

[Alvin Šipraga]

From: Alvin Šipraga <alsi@bang-olufsen.dk>

These two patches fix the issue reported by Arınç where PHY register
reads sometimes return garbage data.

MAINTAINERS: Please can you help me with the targetting of these two
patches? This bug is present ca. 5.16, when the SMI version of the
rtl8365mb driver was introduced. But now in net-next we have the MDIO
interface from Luiz, where the issue is also present. I am sending what
I think is an ideal patch series, but should I split it up and send the
SMI-related changes to net and the MDIO changes to net-next? If so, how
would I go about splitting it while preventing merge conflicts and build
errors?

For now I am sending it to net-next so that the whole thing can be
reviewed. If it's applied, I would gladly backport the fix to the stable
tree for 5.16, but I am still confused about what to do for 5.17.

Thanks for your help.


Alvin Šipraga (2):
  net: dsa: realtek: allow subdrivers to externally lock regmap
  net: dsa: realtek: rtl8365mb: serialize indirect PHY register access

 drivers/net/dsa/realtek/realtek-mdio.c | 46 +++++++++++++++++++++-
 drivers/net/dsa/realtek/realtek-smi.c  | 48 +++++++++++++++++++++--
 drivers/net/dsa/realtek/realtek.h      |  2 +
 drivers/net/dsa/realtek/rtl8365mb.c    | 54 ++++++++++++++++----------
 4 files changed, 124 insertions(+), 26 deletions(-)

-- 
2.35.0

[PATCH net-next 1/2] net: dsa: realtek: allow subdrivers to externally lock regmap

[Alvin Šipraga]

From: Alvin Šipraga <alsi@bang-olufsen.dk>

Currently there is no way for Realtek DSA subdrivers to serialize
consecutive regmap accesses. In preparation for a bugfix relating to
indirect PHY register access - which involves a series of regmap
reads and writes - add a facility for subdrivers to serialize their
regmap access.

Specifically, a mutex is added to the driver private data structure and
the standard regmap is initialized with custom lock/unlock ops which use
this mutex. Then, a "nolock" variant of the regmap is added, which is
functionally equivalent to the existing regmap except that regmap
locking is disabled. Functions that wish to serialize a sequence of
regmap accesses may then lock the newly introduced driver-owned mutex
before using the nolock regmap.

Doing things this way means that subdriver code that doesn't care about
serialized register access - i.e. the vast majority of code - needn't
worry about synchronizing register access with an external lock: it can
just continue to use the original regmap.

Another advantage of this design is that, while regmaps with locking
disabled do not expose a debugfs interface for obvious reasons, there
still exists the original regmap which does expose this interface. This
interface remains safe to use even combined with driver codepaths that
use the nolock regmap, because said codepaths will use the same mutex
to synchronize access.

With respect to disadvantages, it can be argued that having
near-duplicate regmaps is confusing. However, the naming is rather
explicit, and examples will abound.

Finally, while we are at it, rename realtek_smi_mdio_regmap_config to
realtek_smi_regmap_config. This makes it consistent with the naming
realtek_mdio_regmap_config in realtek-mdio.c.

Signed-off-by: Alvin Šipraga <alsi@bang-olufsen.dk>
---
 drivers/net/dsa/realtek/realtek-mdio.c | 46 ++++++++++++++++++++++--
 drivers/net/dsa/realtek/realtek-smi.c  | 48 ++++++++++++++++++++++++--
 drivers/net/dsa/realtek/realtek.h      |  2 ++
 3 files changed, 91 insertions(+), 5 deletions(-)

diff --git a/drivers/net/dsa/realtek/realtek-mdio.c b/drivers/net/dsa/realtek/realtek-mdio.c
index 0308be95d00a..31e1f100e48e 100644
--- a/drivers/net/dsa/realtek/realtek-mdio.c
+++ b/drivers/net/dsa/realtek/realtek-mdio.c
@@ -98,6 +98,20 @@ static int realtek_mdio_read(void *ctx, u32 reg, u32 *val)
 	return ret;
 }
 
+static void realtek_mdio_lock(void *ctx)
+{
+	struct realtek_priv *priv = ctx;
+
+	mutex_lock(&priv->map_lock);
+}
+
+static void realtek_mdio_unlock(void *ctx)
+{
+	struct realtek_priv *priv = ctx;
+
+	mutex_unlock(&priv->map_lock);
+}
+
 static const struct regmap_config realtek_mdio_regmap_config = {
 	.reg_bits = 10, /* A4..A0 R4..R0 */
 	.val_bits = 16,
@@ -108,6 +122,21 @@ static const struct regmap_config realtek_mdio_regmap_config = {
 	.reg_read = realtek_mdio_read,
 	.reg_write = realtek_mdio_write,
 	.cache_type = REGCACHE_NONE,
+	.lock = realtek_mdio_lock,
+	.unlock = realtek_mdio_unlock,
+};
+
+static const struct regmap_config realtek_mdio_nolock_regmap_config = {
+	.reg_bits = 10, /* A4..A0 R4..R0 */
+	.val_bits = 16,
+	.reg_stride = 1,
+	/* PHY regs are at 0x8000 */
+	.max_register = 0xffff,
+	.reg_format_endian = REGMAP_ENDIAN_BIG,
+	.reg_read = realtek_mdio_read,
+	.reg_write = realtek_mdio_write,
+	.cache_type = REGCACHE_NONE,
+	.disable_locking = true,
 };
 
 static int realtek_mdio_probe(struct mdio_device *mdiodev)
@@ -115,8 +144,9 @@ static int realtek_mdio_probe(struct mdio_device *mdiodev)
 	struct realtek_priv *priv;
 	struct device *dev = &mdiodev->dev;
 	const struct realtek_variant *var;
-	int ret;
+	struct regmap_config rc;
 	struct device_node *np;
+	int ret;
 
 	var = of_device_get_match_data(dev);
 	if (!var)
@@ -126,13 +156,25 @@ static int realtek_mdio_probe(struct mdio_device *mdiodev)
 	if (!priv)
 		return -ENOMEM;
 
-	priv->map = devm_regmap_init(dev, NULL, priv, &realtek_mdio_regmap_config);
+	mutex_init(&priv->map_lock);
+
+	rc = realtek_mdio_regmap_config;
+	rc.lock_arg = priv;
+	priv->map = devm_regmap_init(dev, NULL, priv, &rc);
 	if (IS_ERR(priv->map)) {
 		ret = PTR_ERR(priv->map);
 		dev_err(dev, "regmap init failed: %d\n", ret);
 		return ret;
 	}
 
+	rc = realtek_mdio_nolock_regmap_config;
+	priv->map_nolock = devm_regmap_init(dev, NULL, priv, &rc);
+	if (IS_ERR(priv->map_nolock)) {
+		ret = PTR_ERR(priv->map_nolock);
+		dev_err(dev, "regmap init failed: %d\n", ret);
+		return ret;
+	}
+
 	priv->mdio_addr = mdiodev->addr;
 	priv->bus = mdiodev->bus;
 	priv->dev = &mdiodev->dev;
diff --git a/drivers/net/dsa/realtek/realtek-smi.c b/drivers/net/dsa/realtek/realtek-smi.c
index 8806b74bd7a8..2243d3da55b2 100644
--- a/drivers/net/dsa/realtek/realtek-smi.c
+++ b/drivers/net/dsa/realtek/realtek-smi.c
@@ -311,7 +311,21 @@ static int realtek_smi_read(void *ctx, u32 reg, u32 *val)
 	return realtek_smi_read_reg(priv, reg, val);
 }
 
-static const struct regmap_config realtek_smi_mdio_regmap_config = {
+static void realtek_smi_lock(void *ctx)
+{
+	struct realtek_priv *priv = ctx;
+
+	mutex_lock(&priv->map_lock);
+}
+
+static void realtek_smi_unlock(void *ctx)
+{
+	struct realtek_priv *priv = ctx;
+
+	mutex_unlock(&priv->map_lock);
+}
+
+static const struct regmap_config realtek_smi_regmap_config = {
 	.reg_bits = 10, /* A4..A0 R4..R0 */
 	.val_bits = 16,
 	.reg_stride = 1,
@@ -321,6 +335,21 @@ static const struct regmap_config realtek_smi_mdio_regmap_config = {
 	.reg_read = realtek_smi_read,
 	.reg_write = realtek_smi_write,
 	.cache_type = REGCACHE_NONE,
+	.lock = realtek_smi_lock,
+	.unlock = realtek_smi_unlock,
+};
+
+static const struct regmap_config realtek_smi_nolock_regmap_config = {
+	.reg_bits = 10, /* A4..A0 R4..R0 */
+	.val_bits = 16,
+	.reg_stride = 1,
+	/* PHY regs are at 0x8000 */
+	.max_register = 0xffff,
+	.reg_format_endian = REGMAP_ENDIAN_BIG,
+	.reg_read = realtek_smi_read,
+	.reg_write = realtek_smi_write,
+	.cache_type = REGCACHE_NONE,
+	.disable_locking = true,
 };
 
 static int realtek_smi_mdio_read(struct mii_bus *bus, int addr, int regnum)
@@ -385,6 +414,7 @@ static int realtek_smi_probe(struct platform_device *pdev)
 	const struct realtek_variant *var;
 	struct device *dev = &pdev->dev;
 	struct realtek_priv *priv;
+	struct regmap_config rc;
 	struct device_node *np;
 	int ret;
 
@@ -395,14 +425,26 @@ static int realtek_smi_probe(struct platform_device *pdev)
 	if (!priv)
 		return -ENOMEM;
 	priv->chip_data = (void *)priv + sizeof(*priv);
-	priv->map = devm_regmap_init(dev, NULL, priv,
-				     &realtek_smi_mdio_regmap_config);
+
+	mutex_init(&priv->map_lock);
+
+	rc = realtek_smi_regmap_config;
+	rc.lock_arg = priv;
+	priv->map = devm_regmap_init(dev, NULL, priv, &rc);
 	if (IS_ERR(priv->map)) {
 		ret = PTR_ERR(priv->map);
 		dev_err(dev, "regmap init failed: %d\n", ret);
 		return ret;
 	}
 
+	rc = realtek_smi_nolock_regmap_config;
+	priv->map_nolock = devm_regmap_init(dev, NULL, priv, &rc);
+	if (IS_ERR(priv->map_nolock)) {
+		ret = PTR_ERR(priv->map_nolock);
+		dev_err(dev, "regmap init failed: %d\n", ret);
+		return ret;
+	}
+
 	/* Link forward and backward */
 	priv->dev = dev;
 	priv->clk_delay = var->clk_delay;
diff --git a/drivers/net/dsa/realtek/realtek.h b/drivers/net/dsa/realtek/realtek.h
index e7d3e1bcf8b8..4fa7c6ba874a 100644
--- a/drivers/net/dsa/realtek/realtek.h
+++ b/drivers/net/dsa/realtek/realtek.h
@@ -52,6 +52,8 @@ struct realtek_priv {
 	struct gpio_desc	*mdc;
 	struct gpio_desc	*mdio;
 	struct regmap		*map;
+	struct regmap		*map_nolock;
+	struct mutex		map_lock;
 	struct mii_bus		*slave_mii_bus;
 	struct mii_bus		*bus;
 	int			mdio_addr;
-- 
2.35.0

[PATCH net-next 2/2] net: dsa: realtek: rtl8365mb: serialize indirect PHY register access

[Alvin Šipraga]

From: Alvin Šipraga <alsi@bang-olufsen.dk>

Realtek switches in the rtl8365mb family can access the PHY registers of
the internal PHYs via the switch registers. This method is called
indirect access. At a high level, the indirect PHY register access
method involves reading and writing some special switch registers in a
particular sequence. This works for both SMI and MDIO connected
switches.

Currently the rtl8365mb driver does not take any care to serialize the
aforementioned access to the switch registers. In particular, it is
permitted for other driver code to access other switch registers while
the indirect PHY register access is ongoing. Locking is only done at the
regmap level. This, however, is a bug: concurrent register access, even
to unrelated switch registers, risks corrupting the PHY register value
read back via the indirect access method described above.

Arınç reported that the switch sometimes returns nonsense data when
reading the PHY registers. In particular, a value of 0 causes the
kernel's PHY subsystem to think that the link is down, but since most
reads return correct data, the link then flip-flops between up and down
over a period of time.

The aforementioned bug can be readily observed by:

 1. Enabling ftrace events for regmap and mdio
 2. Polling BSMR PHY register for a connected port;
    it should always read the same (e.g. 0x79ed)
 3. Wait for step 2 to give a different value

Example command for step 2:

    while true; do phytool read swp2/2/0x01; done

On my i.MX8MM, the above steps will yield a bogus value for the BSMR PHY
register within a matter of seconds. The interleaved register access it
then evident in the trace log:

 kworker/3:4-70      [003] .......  1927.139849: regmap_reg_write: ethernet-switch reg=1004 val=bd
     phytool-16816   [002] .......  1927.139979: regmap_reg_read: ethernet-switch reg=1f01 val=0
 kworker/3:4-70      [003] .......  1927.140381: regmap_reg_read: ethernet-switch reg=1005 val=0
     phytool-16816   [002] .......  1927.140468: regmap_reg_read: ethernet-switch reg=1d15 val=a69
 kworker/3:4-70      [003] .......  1927.140864: regmap_reg_read: ethernet-switch reg=1003 val=0
     phytool-16816   [002] .......  1927.140955: regmap_reg_write: ethernet-switch reg=1f02 val=2041
 kworker/3:4-70      [003] .......  1927.141390: regmap_reg_read: ethernet-switch reg=1002 val=0
     phytool-16816   [002] .......  1927.141479: regmap_reg_write: ethernet-switch reg=1f00 val=1
 kworker/3:4-70      [003] .......  1927.142311: regmap_reg_write: ethernet-switch reg=1004 val=be
     phytool-16816   [002] .......  1927.142410: regmap_reg_read: ethernet-switch reg=1f01 val=0
 kworker/3:4-70      [003] .......  1927.142534: regmap_reg_read: ethernet-switch reg=1005 val=0
     phytool-16816   [002] .......  1927.142618: regmap_reg_read: ethernet-switch reg=1f04 val=0
     phytool-16816   [002] .......  1927.142641: mdio_access: SMI-0 read  phy:0x02 reg:0x01 val:0x0000 <- ?!
 kworker/3:4-70      [003] .......  1927.143037: regmap_reg_read: ethernet-switch reg=1001 val=0
 kworker/3:4-70      [003] .......  1927.143133: regmap_reg_read: ethernet-switch reg=1000 val=2d89
 kworker/3:4-70      [003] .......  1927.143213: regmap_reg_write: ethernet-switch reg=1004 val=be
 kworker/3:4-70      [003] .......  1927.143291: regmap_reg_read: ethernet-switch reg=1005 val=0
 kworker/3:4-70      [003] .......  1927.143368: regmap_reg_read: ethernet-switch reg=1003 val=0
 kworker/3:4-70      [003] .......  1927.143443: regmap_reg_read: ethernet-switch reg=1002 val=6

The kworker here is polling MIB counters for stats, as evidenced by the
register 0x1004 that we are writing to (RTL8365MB_MIB_ADDRESS_REG). This
polling is performed every 3 seconds, but is just one example of such
unsynchronized access.

Further investigation reveals the underlying problem: if we read from an
arbitrary register A and this read coincides with the indirect access
method in rtl8365mb_phy_ocp_read, then the final read from
RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG will always return the value in
register A. The value read back can be readily poisoned by repeatedly
reading back the value of another register A via debugfs in a busy loop
via the dd utility or similar.

This issue appears to be unique to the indirect PHY register access
pattern. In particular, it does not seem to impact similar sequential
register operations such MIB counter access.

To fix this problem, one must guard against exactly the scenario seen in
the above trace. In particular, other parts of the driver using the
regmap API must not be permitted to access the switch registers until
the PHY register access is complete. Fix this by using the newly
introduced "nolock" regmap in all PHY-related functions, and by aquiring
the regmap mutex at the top level of the PHY register access callbacks.
Although no issue has been observed with PHY register _writes_, this
change also serializes the indirect access method there. This is done
purely as a matter of convenience.

Fixes: 4af2950c50c8 ("net: dsa: realtek-smi: add rtl8365mb subdriver for RTL8365MB-VC")
Link: https://lore.kernel.org/netdev/CAJq09z5FCgG-+jVT7uxh1a-0CiiFsoKoHYsAWJtiKwv7LXKofQ@mail.gmail.com/
Reported-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Reported-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Signed-off-by: Alvin Šipraga <alsi@bang-olufsen.dk>
---
 drivers/net/dsa/realtek/rtl8365mb.c | 54 ++++++++++++++++++-----------
 1 file changed, 33 insertions(+), 21 deletions(-)

diff --git a/drivers/net/dsa/realtek/rtl8365mb.c b/drivers/net/dsa/realtek/rtl8365mb.c
index 2ed592147c20..c39d6b744597 100644
--- a/drivers/net/dsa/realtek/rtl8365mb.c
+++ b/drivers/net/dsa/realtek/rtl8365mb.c
@@ -590,7 +590,7 @@ static int rtl8365mb_phy_poll_busy(struct realtek_priv *priv)
 {
 	u32 val;
 
-	return regmap_read_poll_timeout(priv->map,
+	return regmap_read_poll_timeout(priv->map_nolock,
 					RTL8365MB_INDIRECT_ACCESS_STATUS_REG,
 					val, !val, 10, 100);
 }
@@ -604,7 +604,7 @@ static int rtl8365mb_phy_ocp_prepare(struct realtek_priv *priv, int phy,
 	/* Set OCP prefix */
 	val = FIELD_GET(RTL8365MB_PHY_OCP_ADDR_PREFIX_MASK, ocp_addr);
 	ret = regmap_update_bits(
-		priv->map, RTL8365MB_GPHY_OCP_MSB_0_REG,
+		priv->map_nolock, RTL8365MB_GPHY_OCP_MSB_0_REG,
 		RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK,
 		FIELD_PREP(RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK, val));
 	if (ret)
@@ -617,8 +617,8 @@ static int rtl8365mb_phy_ocp_prepare(struct realtek_priv *priv, int phy,
 			  ocp_addr >> 1);
 	val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK,
 			  ocp_addr >> 6);
-	ret = regmap_write(priv->map, RTL8365MB_INDIRECT_ACCESS_ADDRESS_REG,
-			   val);
+	ret = regmap_write(priv->map_nolock,
+			   RTL8365MB_INDIRECT_ACCESS_ADDRESS_REG, val);
 	if (ret)
 		return ret;
 
@@ -631,36 +631,42 @@ static int rtl8365mb_phy_ocp_read(struct realtek_priv *priv, int phy,
 	u32 val;
 	int ret;
 
+	mutex_lock(&priv->map_lock);
+
 	ret = rtl8365mb_phy_poll_busy(priv);
 	if (ret)
-		return ret;
+		goto out;
 
 	ret = rtl8365mb_phy_ocp_prepare(priv, phy, ocp_addr);
 	if (ret)
-		return ret;
+		goto out;
 
 	/* Execute read operation */
 	val = FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK,
 			 RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE) |
 	      FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK,
 			 RTL8365MB_INDIRECT_ACCESS_CTRL_RW_READ);
-	ret = regmap_write(priv->map, RTL8365MB_INDIRECT_ACCESS_CTRL_REG, val);
+	ret = regmap_write(priv->map_nolock, RTL8365MB_INDIRECT_ACCESS_CTRL_REG,
+			   val);
 	if (ret)
-		return ret;
+		goto out;
 
 	ret = rtl8365mb_phy_poll_busy(priv);
 	if (ret)
-		return ret;
+		goto out;
 
 	/* Get PHY register data */
-	ret = regmap_read(priv->map, RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG,
-			  &val);
+	ret = regmap_read(priv->map_nolock,
+			  RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG, &val);
 	if (ret)
-		return ret;
+		goto out;
 
 	*data = val & 0xFFFF;
 
-	return 0;
+out:
+	mutex_unlock(&priv->map_lock);
+
+	return ret;
 }
 
 static int rtl8365mb_phy_ocp_write(struct realtek_priv *priv, int phy,
@@ -669,32 +675,38 @@ static int rtl8365mb_phy_ocp_write(struct realtek_priv *priv, int phy,
 	u32 val;
 	int ret;
 
+	mutex_lock(&priv->map_lock);
+
 	ret = rtl8365mb_phy_poll_busy(priv);
 	if (ret)
-		return ret;
+		goto out;
 
 	ret = rtl8365mb_phy_ocp_prepare(priv, phy, ocp_addr);
 	if (ret)
-		return ret;
+		goto out;
 
 	/* Set PHY register data */
-	ret = regmap_write(priv->map, RTL8365MB_INDIRECT_ACCESS_WRITE_DATA_REG,
-			   data);
+	ret = regmap_write(priv->map_nolock,
+			   RTL8365MB_INDIRECT_ACCESS_WRITE_DATA_REG, data);
 	if (ret)
-		return ret;
+		goto out;
 
 	/* Execute write operation */
 	val = FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK,
 			 RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE) |
 	      FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK,
 			 RTL8365MB_INDIRECT_ACCESS_CTRL_RW_WRITE);
-	ret = regmap_write(priv->map, RTL8365MB_INDIRECT_ACCESS_CTRL_REG, val);
+	ret = regmap_write(priv->map_nolock, RTL8365MB_INDIRECT_ACCESS_CTRL_REG,
+			   val);
 	if (ret)
-		return ret;
+		goto out;
 
 	ret = rtl8365mb_phy_poll_busy(priv);
 	if (ret)
-		return ret;
+		goto out;
+
+out:
+	mutex_unlock(&priv->map_lock);
 
 	return 0;
 }
-- 
2.35.0

Re: [PATCH net-next 2/2] net: dsa: realtek: rtl8365mb: serialize indirect PHY register access

[Vladimir Oltean]

On Wed, Feb 16, 2022 at 05:05:00PM +0100, Alvin Šipraga wrote:
> From: Alvin Šipraga <alsi@bang-olufsen.dk>
> 
> Realtek switches in the rtl8365mb family can access the PHY registers of
> the internal PHYs via the switch registers. This method is called
> indirect access. At a high level, the indirect PHY register access
> method involves reading and writing some special switch registers in a
> particular sequence. This works for both SMI and MDIO connected
> switches.
> 
> Currently the rtl8365mb driver does not take any care to serialize the
> aforementioned access to the switch registers. In particular, it is
> permitted for other driver code to access other switch registers while
> the indirect PHY register access is ongoing. Locking is only done at the
> regmap level. This, however, is a bug: concurrent register access, even
> to unrelated switch registers, risks corrupting the PHY register value
> read back via the indirect access method described above.
> 
> Arınç reported that the switch sometimes returns nonsense data when
> reading the PHY registers. In particular, a value of 0 causes the
> kernel's PHY subsystem to think that the link is down, but since most
> reads return correct data, the link then flip-flops between up and down
> over a period of time.
> 
> The aforementioned bug can be readily observed by:
> 
>  1. Enabling ftrace events for regmap and mdio
>  2. Polling BSMR PHY register for a connected port;
>     it should always read the same (e.g. 0x79ed)
>  3. Wait for step 2 to give a different value
> 
> Example command for step 2:
> 
>     while true; do phytool read swp2/2/0x01; done
> 
> On my i.MX8MM, the above steps will yield a bogus value for the BSMR PHY
> register within a matter of seconds. The interleaved register access it
> then evident in the trace log:
> 
>  kworker/3:4-70      [003] .......  1927.139849: regmap_reg_write: ethernet-switch reg=1004 val=bd
>      phytool-16816   [002] .......  1927.139979: regmap_reg_read: ethernet-switch reg=1f01 val=0
>  kworker/3:4-70      [003] .......  1927.140381: regmap_reg_read: ethernet-switch reg=1005 val=0
>      phytool-16816   [002] .......  1927.140468: regmap_reg_read: ethernet-switch reg=1d15 val=a69
>  kworker/3:4-70      [003] .......  1927.140864: regmap_reg_read: ethernet-switch reg=1003 val=0
>      phytool-16816   [002] .......  1927.140955: regmap_reg_write: ethernet-switch reg=1f02 val=2041
>  kworker/3:4-70      [003] .......  1927.141390: regmap_reg_read: ethernet-switch reg=1002 val=0
>      phytool-16816   [002] .......  1927.141479: regmap_reg_write: ethernet-switch reg=1f00 val=1
>  kworker/3:4-70      [003] .......  1927.142311: regmap_reg_write: ethernet-switch reg=1004 val=be
>      phytool-16816   [002] .......  1927.142410: regmap_reg_read: ethernet-switch reg=1f01 val=0
>  kworker/3:4-70      [003] .......  1927.142534: regmap_reg_read: ethernet-switch reg=1005 val=0
>      phytool-16816   [002] .......  1927.142618: regmap_reg_read: ethernet-switch reg=1f04 val=0
>      phytool-16816   [002] .......  1927.142641: mdio_access: SMI-0 read  phy:0x02 reg:0x01 val:0x0000 <- ?!
>  kworker/3:4-70      [003] .......  1927.143037: regmap_reg_read: ethernet-switch reg=1001 val=0
>  kworker/3:4-70      [003] .......  1927.143133: regmap_reg_read: ethernet-switch reg=1000 val=2d89
>  kworker/3:4-70      [003] .......  1927.143213: regmap_reg_write: ethernet-switch reg=1004 val=be
>  kworker/3:4-70      [003] .......  1927.143291: regmap_reg_read: ethernet-switch reg=1005 val=0
>  kworker/3:4-70      [003] .......  1927.143368: regmap_reg_read: ethernet-switch reg=1003 val=0
>  kworker/3:4-70      [003] .......  1927.143443: regmap_reg_read: ethernet-switch reg=1002 val=6
> 
> The kworker here is polling MIB counters for stats, as evidenced by the
> register 0x1004 that we are writing to (RTL8365MB_MIB_ADDRESS_REG). This
> polling is performed every 3 seconds, but is just one example of such
> unsynchronized access.
> 
> Further investigation reveals the underlying problem: if we read from an
> arbitrary register A and this read coincides with the indirect access
> method in rtl8365mb_phy_ocp_read, then the final read from
> RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG will always return the value in
> register A. The value read back can be readily poisoned by repeatedly
> reading back the value of another register A via debugfs in a busy loop
> via the dd utility or similar.
> 
> This issue appears to be unique to the indirect PHY register access
> pattern. In particular, it does not seem to impact similar sequential
> register operations such MIB counter access.
> 
> To fix this problem, one must guard against exactly the scenario seen in
> the above trace. In particular, other parts of the driver using the
> regmap API must not be permitted to access the switch registers until
> the PHY register access is complete. Fix this by using the newly
> introduced "nolock" regmap in all PHY-related functions, and by aquiring
> the regmap mutex at the top level of the PHY register access callbacks.
> Although no issue has been observed with PHY register _writes_, this
> change also serializes the indirect access method there. This is done
> purely as a matter of convenience.
> 
> Fixes: 4af2950c50c8 ("net: dsa: realtek-smi: add rtl8365mb subdriver for RTL8365MB-VC")
> Link: https://lore.kernel.org/netdev/CAJq09z5FCgG-+jVT7uxh1a-0CiiFsoKoHYsAWJtiKwv7LXKofQ@mail.gmail.com/
> Reported-by: Arınç ÜNAL <arinc.unal@arinc9.com>
> Reported-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
> Signed-off-by: Alvin Šipraga <alsi@bang-olufsen.dk>
> ---

This implementation where the indirect PHY access blocks out every other
register read and write is only justified if you can prove that you can
stuff just about any unrelated register read or write before
RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG, and this, in and of itself,
will poison what gets read back from RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG.

rtl8365mb_mib_counter_read() doesn't seem like a particularly good
example to prove this, since it appears to be an indirect access
procedure as well. Single register reads or writes would be ideal, like
RTL8365MB_CPU_CTRL_REG, artificially inserted into strategic places.
Ideally you wouldn't even have a DSA or MDIO or PHY driver running.
Just a simple kernel module with access to the regmap, and try to read
something known, like the PHY ID of one of the internal PHYs, via an
open-coded function. Then add extra regmap accesses and see what
corrupts the indirect PHY access procedure.

Are Realtek aware of this and do they confirm the issue? Sounds like
erratum material to me, and a pretty severe one, at that. Alternatively,
we may simply not be understanding the hardware architecture, like for
example the fact that MIB indirect access and PHY indirect access may
share some common bus and must be sequential w.r.t. each other.

Re: [PATCH net-next 2/2] net: dsa: realtek: rtl8365mb: serialize indirect PHY register access

[Luiz Angelo Daros de Luca]

Hi Vladimir,

> This implementation where the indirect PHY access blocks out every other
> register read and write is only justified if you can prove that you can
> stuff just about any unrelated register read or write before
> RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG, and this, in and of itself,
> will poison what gets read back from RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG.

I was the first one trying to fix this issue reported by Arinç with
SMP devices. At first I thought it was caused by two parallel indirect
access reads polling the interface (it was not using interrupts). With
no lock, they will eventually collide and one reads the result of the
other one. However, a simple lock over the indirect access didn't
solve the issue. Alvin tested it much further to isolate that indirect
register access is messed up by any other register read. The fails
while polling the interface status or the other test Alvin created
only manifests in a device with multiple cores and mine is single
core. I do get something similar in a single core device by reading an
unused register address but it is hard to blame Realtek when we are
doing something we were not supposed to do. Anyway, that indicates
that "reading a register" is not an atomic operation inside the switch
asic.

> rtl8365mb_mib_counter_read() doesn't seem like a particularly good
> example to prove this, since it appears to be an indirect access
> procedure as well. Single register reads or writes would be ideal, like
> RTL8365MB_CPU_CTRL_REG, artificially inserted into strategic places.
> Ideally you wouldn't even have a DSA or MDIO or PHY driver running.
> Just a simple kernel module with access to the regmap, and try to read
> something known, like the PHY ID of one of the internal PHYs, via an
> open-coded function. Then add extra regmap accesses and see what
> corrupts the indirect PHY access procedure.

The MIB might be just another example where the issue happens. It was
first noticed with a SMP device without interruptions configured. I
believe it will always fail with that configuration.

> Are Realtek aware of this and do they confirm the issue? Sounds like
> erratum material to me, and a pretty severe one, at that. Alternatively,
> we may simply not be understanding the hardware architecture, like for
> example the fact that MIB indirect access and PHY indirect access may
> share some common bus and must be sequential w.r.t. each other.

The realtek "API/driver" does exactly how the driver was doing. They
do have a lock/unlock placeholder, but only in the equivalent
regmap_{read,write} functions. Indirect access does not use locks at
all (in fact, there is no other mention of "lock" elsewhere), even
being obvious that it is not thread-safe. It was just with a DSA
driver that we started to exercise register access for real, specially
without interruptions. And even in that case, we could only notice
this issue in multicore devices. I believe that, if they know about
this issue, they might not be worried because it has never affected a
real device. It would be very interesting to hear from Realtek but I
do not have the contacts.

Regards,

Luiz

Re: [PATCH net-next 2/2] net: dsa: realtek: rtl8365mb: serialize indirect PHY register access

[Alvin Šipraga]

Luiz Angelo Daros de Luca <luizluca@gmail.com> writes:

> Hi Vladimir,
>
>> This implementation where the indirect PHY access blocks out every other
>> register read and write is only justified if you can prove that you can
>> stuff just about any unrelated register read or write before
>> RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG, and this, in and of itself,
>> will poison what gets read back from RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG.
>
> I was the first one trying to fix this issue reported by Arinç with
> SMP devices. At first I thought it was caused by two parallel indirect
> access reads polling the interface (it was not using interrupts). With
> no lock, they will eventually collide and one reads the result of the
> other one. However, a simple lock over the indirect access didn't
> solve the issue. Alvin tested it much further to isolate that indirect
> register access is messed up by any other register read. The fails
> while polling the interface status or the other test Alvin created
> only manifests in a device with multiple cores and mine is single
> core. I do get something similar in a single core device by reading an
> unused register address but it is hard to blame Realtek when we are
> doing something we were not supposed to do. Anyway, that indicates
> that "reading a register" is not an atomic operation inside the switch
> asic.

I never observed any issue which suggests that switch register reads are
not atomic... I mean, they are (and always have been) protected by the
default regmap lock. So what makes you say this?

I have only seen issues related to PHY register access, please enlighten
us if there are other issues.

>
>> rtl8365mb_mib_counter_read() doesn't seem like a particularly good
>> example to prove this, since it appears to be an indirect access
>> procedure as well. Single register reads or writes would be ideal, like
>> RTL8365MB_CPU_CTRL_REG, artificially inserted into strategic places.
>> Ideally you wouldn't even have a DSA or MDIO or PHY driver running.
>> Just a simple kernel module with access to the regmap, and try to read
>> something known, like the PHY ID of one of the internal PHYs, via an
>> open-coded function. Then add extra regmap accesses and see what
>> corrupts the indirect PHY access procedure.
>
> The MIB might be just another example where the issue happens. It was
> first noticed with a SMP device without interruptions configured. I
> believe it will always fail with that configuration.

As I stated in the last thread, I tested MIB access and the problem did
not manifest itself there.

>
>> Are Realtek aware of this and do they confirm the issue? Sounds like
>> erratum material to me, and a pretty severe one, at that. Alternatively,
>> we may simply not be understanding the hardware architecture, like for
>> example the fact that MIB indirect access and PHY indirect access may
>> share some common bus and must be sequential w.r.t. each other.
>
> The realtek "API/driver" does exactly how the driver was doing. They
> do have a lock/unlock placeholder, but only in the equivalent
> regmap_{read,write} functions. Indirect access does not use locks at
> all (in fact, there is no other mention of "lock" elsewhere), even
> being obvious that it is not thread-safe. It was just with a DSA
> driver that we started to exercise register access for real, specially
> without interruptions. And even in that case, we could only notice
> this issue in multicore devices. I believe that, if they know about
> this issue, they might not be worried because it has never affected a
> real device. It would be very interesting to hear from Realtek but I
> do not have the contacts.

This is not true, at least with the sources I am reading. As I said in
my reply to Vladimir, the Realtek code takes a lock around each
top-level API call. Example:

rtk_api_ret_t rtk_port_phyStatus_get(...)
{
    rtk_api_ret_t retVal;

    if (NULL == RT_MAPPER->port_phyStatus_get)
        return RT_ERR_DRIVER_NOT_FOUND;

    RTK_API_LOCK();
    retVal = RT_MAPPER->port_phyStatus_get(port, pLinkStatus, pSpeed, pDuplex);
    RTK_API_UNLOCK();

    return retVal;
}

Deep down in this port_phyStatus_get() callback, the indirect PHY
register access takes place.

Kind regards,
Alvin

Re: [PATCH net-next 2/2] net: dsa: realtek: rtl8365mb: serialize indirect PHY register access

[Luiz Angelo Daros de Luca]

> > The realtek "API/driver" does exactly how the driver was doing. They
> > do have a lock/unlock placeholder, but only in the equivalent
> > regmap_{read,write} functions. Indirect access does not use locks at
> > all (in fact, there is no other mention of "lock" elsewhere), even
> > being obvious that it is not thread-safe. It was just with a DSA
> > driver that we started to exercise register access for real, specially
> > without interruptions. And even in that case, we could only notice
> > this issue in multicore devices. I believe that, if they know about
> > this issue, they might not be worried because it has never affected a
> > real device. It would be very interesting to hear from Realtek but I
> > do not have the contacts.
>
> This is not true, at least with the sources I am reading. As I said in
> my reply to Vladimir, the Realtek code takes a lock around each
> top-level API call. Example:
>
> rtk_api_ret_t rtk_port_phyStatus_get(...)
> {
>     rtk_api_ret_t retVal;
>
>     if (NULL == RT_MAPPER->port_phyStatus_get)
>         return RT_ERR_DRIVER_NOT_FOUND;
>
>     RTK_API_LOCK();
>     retVal = RT_MAPPER->port_phyStatus_get(port, pLinkStatus, pSpeed, pDuplex);
>     RTK_API_UNLOCK();
>
>     return retVal;
> }
>
> Deep down in this port_phyStatus_get() callback, the indirect PHY
> register access takes place.

For the record, in the rtl8367c driver I'm using as reference, there
is no mention of RTK_API_LOCK(). Check here same function you copied:

https://github.com/openwrt/openwrt/blob/aae7af4219e56c2787f675109d9dd1a44a5dcba4/target/linux/mediatek/files-5.10/drivers/net/phy/rtk/rtl8367c/port.c#L1003-L1040

So, this indirect reg access protection is something they added along
the way, probably when they started to use it with SMP systems.

> Kind regards,
> Alvin

Re: [PATCH net-next 2/2] net: dsa: realtek: rtl8365mb: serialize indirect PHY register access

[Alvin Šipraga]

Vladimir Oltean <olteanv@gmail.com> writes:

> On Wed, Feb 16, 2022 at 05:05:00PM +0100, Alvin Šipraga wrote:
>> From: Alvin Šipraga <alsi@bang-olufsen.dk>
>> 
>> Realtek switches in the rtl8365mb family can access the PHY registers of
>> the internal PHYs via the switch registers. This method is called
>> indirect access. At a high level, the indirect PHY register access
>> method involves reading and writing some special switch registers in a
>> particular sequence. This works for both SMI and MDIO connected
>> switches.
>> 
>> Currently the rtl8365mb driver does not take any care to serialize the
>> aforementioned access to the switch registers. In particular, it is
>> permitted for other driver code to access other switch registers while
>> the indirect PHY register access is ongoing. Locking is only done at the
>> regmap level. This, however, is a bug: concurrent register access, even
>> to unrelated switch registers, risks corrupting the PHY register value
>> read back via the indirect access method described above.
>> 
>> Arınç reported that the switch sometimes returns nonsense data when
>> reading the PHY registers. In particular, a value of 0 causes the
>> kernel's PHY subsystem to think that the link is down, but since most
>> reads return correct data, the link then flip-flops between up and down
>> over a period of time.
>> 
>> The aforementioned bug can be readily observed by:
>> 
>>  1. Enabling ftrace events for regmap and mdio
>>  2. Polling BSMR PHY register for a connected port;
>>     it should always read the same (e.g. 0x79ed)
>>  3. Wait for step 2 to give a different value
>> 
>> Example command for step 2:
>> 
>>     while true; do phytool read swp2/2/0x01; done
>> 
>> On my i.MX8MM, the above steps will yield a bogus value for the BSMR PHY
>> register within a matter of seconds. The interleaved register access it
>> then evident in the trace log:
>> 
>>  kworker/3:4-70      [003] .......  1927.139849: regmap_reg_write: ethernet-switch reg=1004 val=bd
>>      phytool-16816   [002] .......  1927.139979: regmap_reg_read: ethernet-switch reg=1f01 val=0
>>  kworker/3:4-70      [003] .......  1927.140381: regmap_reg_read: ethernet-switch reg=1005 val=0
>>      phytool-16816   [002] .......  1927.140468: regmap_reg_read: ethernet-switch reg=1d15 val=a69
>>  kworker/3:4-70      [003] .......  1927.140864: regmap_reg_read: ethernet-switch reg=1003 val=0
>>      phytool-16816   [002] .......  1927.140955: regmap_reg_write: ethernet-switch reg=1f02 val=2041
>>  kworker/3:4-70      [003] .......  1927.141390: regmap_reg_read: ethernet-switch reg=1002 val=0
>>      phytool-16816   [002] .......  1927.141479: regmap_reg_write: ethernet-switch reg=1f00 val=1
>>  kworker/3:4-70      [003] .......  1927.142311: regmap_reg_write: ethernet-switch reg=1004 val=be
>>      phytool-16816   [002] .......  1927.142410: regmap_reg_read: ethernet-switch reg=1f01 val=0
>>  kworker/3:4-70      [003] .......  1927.142534: regmap_reg_read: ethernet-switch reg=1005 val=0
>>      phytool-16816   [002] .......  1927.142618: regmap_reg_read: ethernet-switch reg=1f04 val=0
>>      phytool-16816   [002] .......  1927.142641: mdio_access: SMI-0 read  phy:0x02 reg:0x01 val:0x0000 <- ?!
>>  kworker/3:4-70      [003] .......  1927.143037: regmap_reg_read: ethernet-switch reg=1001 val=0
>>  kworker/3:4-70      [003] .......  1927.143133: regmap_reg_read: ethernet-switch reg=1000 val=2d89
>>  kworker/3:4-70      [003] .......  1927.143213: regmap_reg_write: ethernet-switch reg=1004 val=be
>>  kworker/3:4-70      [003] .......  1927.143291: regmap_reg_read: ethernet-switch reg=1005 val=0
>>  kworker/3:4-70      [003] .......  1927.143368: regmap_reg_read: ethernet-switch reg=1003 val=0
>>  kworker/3:4-70      [003] .......  1927.143443: regmap_reg_read: ethernet-switch reg=1002 val=6
>> 
>> The kworker here is polling MIB counters for stats, as evidenced by the
>> register 0x1004 that we are writing to (RTL8365MB_MIB_ADDRESS_REG). This
>> polling is performed every 3 seconds, but is just one example of such
>> unsynchronized access.
>> 
>> Further investigation reveals the underlying problem: if we read from an
>> arbitrary register A and this read coincides with the indirect access
>> method in rtl8365mb_phy_ocp_read, then the final read from
>> RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG will always return the value in
>> register A. The value read back can be readily poisoned by repeatedly
>> reading back the value of another register A via debugfs in a busy loop
>> via the dd utility or similar.
>> 
>> This issue appears to be unique to the indirect PHY register access
>> pattern. In particular, it does not seem to impact similar sequential
>> register operations such MIB counter access.
>> 
>> To fix this problem, one must guard against exactly the scenario seen in
>> the above trace. In particular, other parts of the driver using the
>> regmap API must not be permitted to access the switch registers until
>> the PHY register access is complete. Fix this by using the newly
>> introduced "nolock" regmap in all PHY-related functions, and by aquiring
>> the regmap mutex at the top level of the PHY register access callbacks.
>> Although no issue has been observed with PHY register _writes_, this
>> change also serializes the indirect access method there. This is done
>> purely as a matter of convenience.
>> 
>> Fixes: 4af2950c50c8 ("net: dsa: realtek-smi: add rtl8365mb subdriver for RTL8365MB-VC")
>> Link: https://lore.kernel.org/netdev/CAJq09z5FCgG-+jVT7uxh1a-0CiiFsoKoHYsAWJtiKwv7LXKofQ@mail.gmail.com/
>> Reported-by: Arınç ÜNAL <arinc.unal@arinc9.com>
>> Reported-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
>> Signed-off-by: Alvin Šipraga <alsi@bang-olufsen.dk>
>> ---
>
> This implementation where the indirect PHY access blocks out every other
> register read and write is only justified if you can prove that you can
> stuff just about any unrelated register read or write before
> RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG, and this, in and of itself,
> will poison what gets read back from RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG.

I (at least treied to) state that clearly here:

>> Further investigation reveals the underlying problem: if we read from an
>> arbitrary register A and this read coincides with the indirect access
>> method in rtl8365mb_phy_ocp_read, then the final read from
>> RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG will always return the value in
>> register A. The value read back can be readily poisoned by repeatedly
>> reading back the value of another register A via debugfs in a busy loop
>> via the dd utility or similar.

That is, I used regmap debugfs to spam reads of switch registers like,
for example, this one:

#define RTL8365MB_CFG0_MAX_LEN_REG	0x088C

... which controls the MTU of the switch. This is something we set up
just once to be 0x600 and then it is never touched again. Now in the
above example, let A = 0x088C. Spamming the read of A phytool command
described above, I would expect to read a value 0x79c9 out of my BSMR
PHY register with phytool. But in cases where the read of switch
register A coincides with the indirect access procedure, I end up
reading back 0x600 from the PHY register. This is specifically because
the read of A (=0x600) then poisons the value in
RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG (should be 0x79c9, but is
0x600).

>
> rtl8365mb_mib_counter_read() doesn't seem like a particularly good
> example to prove this, since it appears to be an indirect access
> procedure as well. Single register reads or writes would be ideal, like
> RTL8365MB_CPU_CTRL_REG, artificially inserted into strategic places.
> Ideally you wouldn't even have a DSA or MDIO or PHY driver running.

I hope it is clear from my above explanation that I did show this, if
you agree that RTL8365MB_CFG0_MAX_LEN_REG is just as arbitrary as
RTL8365MB_CPU_CTRL_REG.

What I meant to say here:

>> This issue appears to be unique to the indirect PHY register access
>> pattern. In particular, it does not seem to impact similar sequential
>> register operations such MIB counter access.

... about MIB counter access (which is also indirect as you point out),
is that it does _not_ suffer from the above problem. The way I checked
this was with ethtool -S, while again spamming regmap_read of an
unrelated switch register like CPU_CTRL or CFG0_MAX_LEN. In this case
the counter values always seem sane, and I can't detect the poisoned
value getting read back (like 0x600 in the above example).

> Just a simple kernel module with access to the regmap, and try to read
> something known, like the PHY ID of one of the internal PHYs, via an
> open-coded function. Then add extra regmap accesses and see what
> corrupts the indirect PHY access procedure.

The switch is generally idle and I did my testing with the periodic MIB
counter disabled, so I think what you describe is not far off from what
I did. The only difference is that the switch was already configured and
switching packets. I used ftrace events to verify the phenomenon.

If you are still not persuaded, just write me back here, and I will go
ahead and implement such a test module. But it seems like you
misunderstood my initial commit message, so perhaps I just need to
rephrase it?

>
> Are Realtek aware of this and do they confirm the issue? Sounds like
> erratum material to me, and a pretty severe one, at that. Alternatively,
> we may simply not be understanding the hardware architecture, like for
> example the fact that MIB indirect access and PHY indirect access may
> share some common bus and must be sequential w.r.t. each other.

The thing is that Realtek's vendor driver takes a common lock around
every public API call. One of those APIs is "read phy register" and
there it will take a lock around the whole procedure. At the same time
it will also take the same lock for something like "read switch MTU" or
"read CPU tag position", etc. So I don't believe their driver will
suffer from this issue.

In any case it was on my list to write them a mail about this, so let's
see what they say.

Kind regards,
Alvin

Re: [PATCH net-next 2/2] net: dsa: realtek: rtl8365mb: serialize indirect PHY register access

[Vladimir Oltean]

On Thu, Feb 17, 2022 at 07:41:32AM +0000, Alvin Šipraga wrote:
> Vladimir Oltean <olteanv@gmail.com> writes:
> 
> > On Wed, Feb 16, 2022 at 05:05:00PM +0100, Alvin Šipraga wrote:
> >> From: Alvin Šipraga <alsi@bang-olufsen.dk>
> >> 
> >> Realtek switches in the rtl8365mb family can access the PHY registers of
> >> the internal PHYs via the switch registers. This method is called
> >> indirect access. At a high level, the indirect PHY register access
> >> method involves reading and writing some special switch registers in a
> >> particular sequence. This works for both SMI and MDIO connected
> >> switches.
> >> 
> >> Currently the rtl8365mb driver does not take any care to serialize the
> >> aforementioned access to the switch registers. In particular, it is
> >> permitted for other driver code to access other switch registers while
> >> the indirect PHY register access is ongoing. Locking is only done at the
> >> regmap level. This, however, is a bug: concurrent register access, even
> >> to unrelated switch registers, risks corrupting the PHY register value
> >> read back via the indirect access method described above.
> >> 
> >> Arınç reported that the switch sometimes returns nonsense data when
> >> reading the PHY registers. In particular, a value of 0 causes the
> >> kernel's PHY subsystem to think that the link is down, but since most
> >> reads return correct data, the link then flip-flops between up and down
> >> over a period of time.
> >> 
> >> The aforementioned bug can be readily observed by:
> >> 
> >>  1. Enabling ftrace events for regmap and mdio
> >>  2. Polling BSMR PHY register for a connected port;
> >>     it should always read the same (e.g. 0x79ed)
> >>  3. Wait for step 2 to give a different value
> >> 
> >> Example command for step 2:
> >> 
> >>     while true; do phytool read swp2/2/0x01; done
> >> 
> >> On my i.MX8MM, the above steps will yield a bogus value for the BSMR PHY
> >> register within a matter of seconds. The interleaved register access it
> >> then evident in the trace log:
> >> 
> >>  kworker/3:4-70      [003] .......  1927.139849: regmap_reg_write: ethernet-switch reg=1004 val=bd
> >>      phytool-16816   [002] .......  1927.139979: regmap_reg_read: ethernet-switch reg=1f01 val=0
> >>  kworker/3:4-70      [003] .......  1927.140381: regmap_reg_read: ethernet-switch reg=1005 val=0
> >>      phytool-16816   [002] .......  1927.140468: regmap_reg_read: ethernet-switch reg=1d15 val=a69
> >>  kworker/3:4-70      [003] .......  1927.140864: regmap_reg_read: ethernet-switch reg=1003 val=0
> >>      phytool-16816   [002] .......  1927.140955: regmap_reg_write: ethernet-switch reg=1f02 val=2041
> >>  kworker/3:4-70      [003] .......  1927.141390: regmap_reg_read: ethernet-switch reg=1002 val=0
> >>      phytool-16816   [002] .......  1927.141479: regmap_reg_write: ethernet-switch reg=1f00 val=1
> >>  kworker/3:4-70      [003] .......  1927.142311: regmap_reg_write: ethernet-switch reg=1004 val=be
> >>      phytool-16816   [002] .......  1927.142410: regmap_reg_read: ethernet-switch reg=1f01 val=0
> >>  kworker/3:4-70      [003] .......  1927.142534: regmap_reg_read: ethernet-switch reg=1005 val=0
> >>      phytool-16816   [002] .......  1927.142618: regmap_reg_read: ethernet-switch reg=1f04 val=0
> >>      phytool-16816   [002] .......  1927.142641: mdio_access: SMI-0 read  phy:0x02 reg:0x01 val:0x0000 <- ?!
> >>  kworker/3:4-70      [003] .......  1927.143037: regmap_reg_read: ethernet-switch reg=1001 val=0
> >>  kworker/3:4-70      [003] .......  1927.143133: regmap_reg_read: ethernet-switch reg=1000 val=2d89
> >>  kworker/3:4-70      [003] .......  1927.143213: regmap_reg_write: ethernet-switch reg=1004 val=be
> >>  kworker/3:4-70      [003] .......  1927.143291: regmap_reg_read: ethernet-switch reg=1005 val=0
> >>  kworker/3:4-70      [003] .......  1927.143368: regmap_reg_read: ethernet-switch reg=1003 val=0
> >>  kworker/3:4-70      [003] .......  1927.143443: regmap_reg_read: ethernet-switch reg=1002 val=6
> >> 
> >> The kworker here is polling MIB counters for stats, as evidenced by the
> >> register 0x1004 that we are writing to (RTL8365MB_MIB_ADDRESS_REG). This
> >> polling is performed every 3 seconds, but is just one example of such
> >> unsynchronized access.
> >> 
> >> Further investigation reveals the underlying problem: if we read from an
> >> arbitrary register A and this read coincides with the indirect access
> >> method in rtl8365mb_phy_ocp_read, then the final read from
> >> RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG will always return the value in
> >> register A. The value read back can be readily poisoned by repeatedly
> >> reading back the value of another register A via debugfs in a busy loop
> >> via the dd utility or similar.
> >> 
> >> This issue appears to be unique to the indirect PHY register access
> >> pattern. In particular, it does not seem to impact similar sequential
> >> register operations such MIB counter access.
> >> 
> >> To fix this problem, one must guard against exactly the scenario seen in
> >> the above trace. In particular, other parts of the driver using the
> >> regmap API must not be permitted to access the switch registers until
> >> the PHY register access is complete. Fix this by using the newly
> >> introduced "nolock" regmap in all PHY-related functions, and by aquiring
> >> the regmap mutex at the top level of the PHY register access callbacks.
> >> Although no issue has been observed with PHY register _writes_, this
> >> change also serializes the indirect access method there. This is done
> >> purely as a matter of convenience.
> >> 
> >> Fixes: 4af2950c50c8 ("net: dsa: realtek-smi: add rtl8365mb subdriver for RTL8365MB-VC")
> >> Link: https://lore.kernel.org/netdev/CAJq09z5FCgG-+jVT7uxh1a-0CiiFsoKoHYsAWJtiKwv7LXKofQ@mail.gmail.com/
> >> Reported-by: Arınç ÜNAL <arinc.unal@arinc9.com>
> >> Reported-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
> >> Signed-off-by: Alvin Šipraga <alsi@bang-olufsen.dk>
> >> ---
> >
> > This implementation where the indirect PHY access blocks out every other
> > register read and write is only justified if you can prove that you can
> > stuff just about any unrelated register read or write before
> > RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG, and this, in and of itself,
> > will poison what gets read back from RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG.
> 
> I (at least treied to) state that clearly here:
> 
> >> Further investigation reveals the underlying problem: if we read from an
> >> arbitrary register A and this read coincides with the indirect access
> >> method in rtl8365mb_phy_ocp_read, then the final read from
> >> RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG will always return the value in
> >> register A. The value read back can be readily poisoned by repeatedly
> >> reading back the value of another register A via debugfs in a busy loop
> >> via the dd utility or similar.
> 
> That is, I used regmap debugfs to spam reads of switch registers like,
> for example, this one:
> 
> #define RTL8365MB_CFG0_MAX_LEN_REG	0x088C
> 
> ... which controls the MTU of the switch. This is something we set up
> just once to be 0x600 and then it is never touched again. Now in the
> above example, let A = 0x088C. Spamming the read of A phytool command
> described above, I would expect to read a value 0x79c9 out of my BSMR
> PHY register with phytool. But in cases where the read of switch
> register A coincides with the indirect access procedure, I end up
> reading back 0x600 from the PHY register. This is specifically because
> the read of A (=0x600) then poisons the value in
> RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG (should be 0x79c9, but is
> 0x600).

Yes, well, that was a bit handwavy, you didn't mention any other
specific register, you just stated a rule which appeared to be inferred
from little evidence.

> > rtl8365mb_mib_counter_read() doesn't seem like a particularly good
> > example to prove this, since it appears to be an indirect access
> > procedure as well. Single register reads or writes would be ideal, like
> > RTL8365MB_CPU_CTRL_REG, artificially inserted into strategic places.
> > Ideally you wouldn't even have a DSA or MDIO or PHY driver running.
> 
> I hope it is clear from my above explanation that I did show this, if
> you agree that RTL8365MB_CFG0_MAX_LEN_REG is just as arbitrary as
> RTL8365MB_CPU_CTRL_REG.
> 
> What I meant to say here:
> 
> >> This issue appears to be unique to the indirect PHY register access
> >> pattern. In particular, it does not seem to impact similar sequential
> >> register operations such MIB counter access.
> 
> ... about MIB counter access (which is also indirect as you point out),
> is that it does _not_ suffer from the above problem. The way I checked
> this was with ethtool -S, while again spamming regmap_read of an
> unrelated switch register like CPU_CTRL or CFG0_MAX_LEN. In this case
> the counter values always seem sane, and I can't detect the poisoned
> value getting read back (like 0x600 in the above example).
> 
> > Just a simple kernel module with access to the regmap, and try to read
> > something known, like the PHY ID of one of the internal PHYs, via an
> > open-coded function. Then add extra regmap accesses and see what
> > corrupts the indirect PHY access procedure.
> 
> The switch is generally idle and I did my testing with the periodic MIB
> counter disabled, so I think what you describe is not far off from what
> I did. The only difference is that the switch was already configured and
> switching packets. I used ftrace events to verify the phenomenon.
> 
> If you are still not persuaded, just write me back here, and I will go
> ahead and implement such a test module. But it seems like you
> misunderstood my initial commit message, so perhaps I just need to
> rephrase it?

If the problem you've identified is correct, then this simple test
module would yield the exact same result, yet would eliminate beyond any
doubt the timing and other circumstantial factors, and you could also
do better testing of the PHY write sequence, and MIB counter reads.
And if simply inserting a stray register access in the middle of the PHY
read procedure doesn't produce the same result, this would be new
information. It shouldn't even be too hard to do.

> > Are Realtek aware of this and do they confirm the issue? Sounds like
> > erratum material to me, and a pretty severe one, at that. Alternatively,
> > we may simply not be understanding the hardware architecture, like for
> > example the fact that MIB indirect access and PHY indirect access may
> > share some common bus and must be sequential w.r.t. each other.
> 
> The thing is that Realtek's vendor driver takes a common lock around
> every public API call. One of those APIs is "read phy register" and
> there it will take a lock around the whole procedure. At the same time
> it will also take the same lock for something like "read switch MTU" or
> "read CPU tag position", etc. So I don't believe their driver will
> suffer from this issue.
> 
> In any case it was on my list to write them a mail about this, so let's
> see what they say.
> 
> Kind regards,
> Alvin

I have little to no problem with the workaround you've implemented, it's
just that extraordinary claims require extraordinary proof. Having a
standalone kernel module that can deterministically and not statistically
reproduce the bug would go a long way.

Re: [PATCH net-next 2/2] net: dsa: realtek: rtl8365mb: serialize indirect PHY register access

[Alvin Šipraga]

Vladimir Oltean <olteanv@gmail.com> writes:

> On Thu, Feb 17, 2022 at 07:41:32AM +0000, Alvin Šipraga wrote:
>> Vladimir Oltean <olteanv@gmail.com> writes:
>> 
>> > On Wed, Feb 16, 2022 at 05:05:00PM +0100, Alvin Šipraga wrote:
>> >> From: Alvin Šipraga <alsi@bang-olufsen.dk>
>> >> 
>> >> Realtek switches in the rtl8365mb family can access the PHY registers of
>> >> the internal PHYs via the switch registers. This method is called
>> >> indirect access. At a high level, the indirect PHY register access
>> >> method involves reading and writing some special switch registers in a
>> >> particular sequence. This works for both SMI and MDIO connected
>> >> switches.
>> >> 
>> >> Currently the rtl8365mb driver does not take any care to serialize the
>> >> aforementioned access to the switch registers. In particular, it is
>> >> permitted for other driver code to access other switch registers while
>> >> the indirect PHY register access is ongoing. Locking is only done at the
>> >> regmap level. This, however, is a bug: concurrent register access, even
>> >> to unrelated switch registers, risks corrupting the PHY register value
>> >> read back via the indirect access method described above.
>> >> 
>> >> Arınç reported that the switch sometimes returns nonsense data when
>> >> reading the PHY registers. In particular, a value of 0 causes the
>> >> kernel's PHY subsystem to think that the link is down, but since most
>> >> reads return correct data, the link then flip-flops between up and down
>> >> over a period of time.
>> >> 
>> >> The aforementioned bug can be readily observed by:
>> >> 
>> >>  1. Enabling ftrace events for regmap and mdio
>> >>  2. Polling BSMR PHY register for a connected port;
>> >>     it should always read the same (e.g. 0x79ed)
>> >>  3. Wait for step 2 to give a different value
>> >> 
>> >> Example command for step 2:
>> >> 
>> >>     while true; do phytool read swp2/2/0x01; done
>> >> 
>> >> On my i.MX8MM, the above steps will yield a bogus value for the BSMR PHY
>> >> register within a matter of seconds. The interleaved register access it
>> >> then evident in the trace log:
>> >> 
>> >>  kworker/3:4-70      [003] .......  1927.139849: regmap_reg_write: ethernet-switch reg=1004 val=bd
>> >>      phytool-16816   [002] .......  1927.139979: regmap_reg_read: ethernet-switch reg=1f01 val=0
>> >>  kworker/3:4-70      [003] .......  1927.140381: regmap_reg_read: ethernet-switch reg=1005 val=0
>> >>      phytool-16816   [002] .......  1927.140468: regmap_reg_read: ethernet-switch reg=1d15 val=a69
>> >>  kworker/3:4-70      [003] .......  1927.140864: regmap_reg_read: ethernet-switch reg=1003 val=0
>> >>      phytool-16816   [002] .......  1927.140955: regmap_reg_write: ethernet-switch reg=1f02 val=2041
>> >>  kworker/3:4-70      [003] .......  1927.141390: regmap_reg_read: ethernet-switch reg=1002 val=0
>> >>      phytool-16816   [002] .......  1927.141479: regmap_reg_write: ethernet-switch reg=1f00 val=1
>> >>  kworker/3:4-70      [003] .......  1927.142311: regmap_reg_write: ethernet-switch reg=1004 val=be
>> >>      phytool-16816   [002] .......  1927.142410: regmap_reg_read: ethernet-switch reg=1f01 val=0
>> >>  kworker/3:4-70      [003] .......  1927.142534: regmap_reg_read: ethernet-switch reg=1005 val=0
>> >>      phytool-16816   [002] .......  1927.142618: regmap_reg_read: ethernet-switch reg=1f04 val=0
>> >>      phytool-16816   [002] .......  1927.142641: mdio_access: SMI-0 read  phy:0x02 reg:0x01 val:0x0000 <- ?!
>> >>  kworker/3:4-70      [003] .......  1927.143037: regmap_reg_read: ethernet-switch reg=1001 val=0
>> >>  kworker/3:4-70      [003] .......  1927.143133: regmap_reg_read: ethernet-switch reg=1000 val=2d89
>> >>  kworker/3:4-70      [003] .......  1927.143213: regmap_reg_write: ethernet-switch reg=1004 val=be
>> >>  kworker/3:4-70      [003] .......  1927.143291: regmap_reg_read: ethernet-switch reg=1005 val=0
>> >>  kworker/3:4-70      [003] .......  1927.143368: regmap_reg_read: ethernet-switch reg=1003 val=0
>> >>  kworker/3:4-70      [003] .......  1927.143443: regmap_reg_read: ethernet-switch reg=1002 val=6
>> >> 
>> >> The kworker here is polling MIB counters for stats, as evidenced by the
>> >> register 0x1004 that we are writing to (RTL8365MB_MIB_ADDRESS_REG). This
>> >> polling is performed every 3 seconds, but is just one example of such
>> >> unsynchronized access.
>> >> 
>> >> Further investigation reveals the underlying problem: if we read from an
>> >> arbitrary register A and this read coincides with the indirect access
>> >> method in rtl8365mb_phy_ocp_read, then the final read from
>> >> RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG will always return the value in
>> >> register A. The value read back can be readily poisoned by repeatedly
>> >> reading back the value of another register A via debugfs in a busy loop
>> >> via the dd utility or similar.
>> >> 
>> >> This issue appears to be unique to the indirect PHY register access
>> >> pattern. In particular, it does not seem to impact similar sequential
>> >> register operations such MIB counter access.
>> >> 
>> >> To fix this problem, one must guard against exactly the scenario seen in
>> >> the above trace. In particular, other parts of the driver using the
>> >> regmap API must not be permitted to access the switch registers until
>> >> the PHY register access is complete. Fix this by using the newly
>> >> introduced "nolock" regmap in all PHY-related functions, and by aquiring
>> >> the regmap mutex at the top level of the PHY register access callbacks.
>> >> Although no issue has been observed with PHY register _writes_, this
>> >> change also serializes the indirect access method there. This is done
>> >> purely as a matter of convenience.
>> >> 
>> >> Fixes: 4af2950c50c8 ("net: dsa: realtek-smi: add rtl8365mb subdriver for RTL8365MB-VC")
>> >> Link: https://lore.kernel.org/netdev/CAJq09z5FCgG-+jVT7uxh1a-0CiiFsoKoHYsAWJtiKwv7LXKofQ@mail.gmail.com/
>> >> Reported-by: Arınç ÜNAL <arinc.unal@arinc9.com>
>> >> Reported-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
>> >> Signed-off-by: Alvin Šipraga <alsi@bang-olufsen.dk>
>> >> ---
>> >
>> > This implementation where the indirect PHY access blocks out every other
>> > register read and write is only justified if you can prove that you can
>> > stuff just about any unrelated register read or write before
>> > RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG, and this, in and of itself,
>> > will poison what gets read back from RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG.
>> 
>> I (at least treied to) state that clearly here:
>> 
>> >> Further investigation reveals the underlying problem: if we read from an
>> >> arbitrary register A and this read coincides with the indirect access
>> >> method in rtl8365mb_phy_ocp_read, then the final read from
>> >> RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG will always return the value in
>> >> register A. The value read back can be readily poisoned by repeatedly
>> >> reading back the value of another register A via debugfs in a busy loop
>> >> via the dd utility or similar.
>> 
>> That is, I used regmap debugfs to spam reads of switch registers like,
>> for example, this one:
>> 
>> #define RTL8365MB_CFG0_MAX_LEN_REG	0x088C
>> 
>> ... which controls the MTU of the switch. This is something we set up
>> just once to be 0x600 and then it is never touched again. Now in the
>> above example, let A = 0x088C. Spamming the read of A phytool command
>> described above, I would expect to read a value 0x79c9 out of my BSMR
>> PHY register with phytool. But in cases where the read of switch
>> register A coincides with the indirect access procedure, I end up
>> reading back 0x600 from the PHY register. This is specifically because
>> the read of A (=0x600) then poisons the value in
>> RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG (should be 0x79c9, but is
>> 0x600).
>
> Yes, well, that was a bit handwavy, you didn't mention any other
> specific register, you just stated a rule which appeared to be inferred
> from little evidence.
>
>> > rtl8365mb_mib_counter_read() doesn't seem like a particularly good
>> > example to prove this, since it appears to be an indirect access
>> > procedure as well. Single register reads or writes would be ideal, like
>> > RTL8365MB_CPU_CTRL_REG, artificially inserted into strategic places.
>> > Ideally you wouldn't even have a DSA or MDIO or PHY driver running.
>> 
>> I hope it is clear from my above explanation that I did show this, if
>> you agree that RTL8365MB_CFG0_MAX_LEN_REG is just as arbitrary as
>> RTL8365MB_CPU_CTRL_REG.
>> 
>> What I meant to say here:
>> 
>> >> This issue appears to be unique to the indirect PHY register access
>> >> pattern. In particular, it does not seem to impact similar sequential
>> >> register operations such MIB counter access.
>> 
>> ... about MIB counter access (which is also indirect as you point out),
>> is that it does _not_ suffer from the above problem. The way I checked
>> this was with ethtool -S, while again spamming regmap_read of an
>> unrelated switch register like CPU_CTRL or CFG0_MAX_LEN. In this case
>> the counter values always seem sane, and I can't detect the poisoned
>> value getting read back (like 0x600 in the above example).
>> 
>> > Just a simple kernel module with access to the regmap, and try to read
>> > something known, like the PHY ID of one of the internal PHYs, via an
>> > open-coded function. Then add extra regmap accesses and see what
>> > corrupts the indirect PHY access procedure.
>> 
>> The switch is generally idle and I did my testing with the periodic MIB
>> counter disabled, so I think what you describe is not far off from what
>> I did. The only difference is that the switch was already configured and
>> switching packets. I used ftrace events to verify the phenomenon.
>> 
>> If you are still not persuaded, just write me back here, and I will go
>> ahead and implement such a test module. But it seems like you
>> misunderstood my initial commit message, so perhaps I just need to
>> rephrase it?
>
> If the problem you've identified is correct, then this simple test
> module would yield the exact same result, yet would eliminate beyond any
> doubt the timing and other circumstantial factors, and you could also
> do better testing of the PHY write sequence, and MIB counter reads.
> And if simply inserting a stray register access in the middle of the PHY
> read procedure doesn't produce the same result, this would be new
> information. It shouldn't even be too hard to do.
>
<snip>
>
> I have little to no problem with the workaround you've implemented, it's
> just that extraordinary claims require extraordinary proof. Having a
> standalone kernel module that can deterministically and not statistically
> reproduce the bug would go a long way.

Thanks Vladimir, I very much appreciate your scrutiny here. I'll make
the test module to verify the claims I have made. In the mean time I
asked Realtek if they have any comment.

Kind regards,
Alvin

Re: [PATCH net-next 2/2] net: dsa: realtek: rtl8365mb: serialize indirect PHY register access

[Alvin Šipraga]

[-- Attachment #1: Type: text/plain, Size: 5229 bytes --]

Hi again Vladimir,

Alvin Šipraga <ALSI@bang-olufsen.dk> writes:

> Vladimir Oltean <olteanv@gmail.com> writes:
>
>> If the problem you've identified is correct, then this simple test
>> module would yield the exact same result, yet would eliminate beyond any
>> doubt the timing and other circumstantial factors, and you could also
>> do better testing of the PHY write sequence, and MIB counter reads.
>> And if simply inserting a stray register access in the middle of the PHY
>> read procedure doesn't produce the same result, this would be new
>> information. It shouldn't even be too hard to do.
>>
> <snip>
>>
>> I have little to no problem with the workaround you've implemented, it's
>> just that extraordinary claims require extraordinary proof. Having a
>> standalone kernel module that can deterministically and not statistically
>> reproduce the bug would go a long way.
>
> Thanks Vladimir, I very much appreciate your scrutiny here. I'll make
> the test module to verify the claims I have made. In the mean time I
> asked Realtek if they have any comment.

So I made a test module which, in summary, checks the following:

1. for PHY reads, at what point does inserting a stray register access
   (either read or write) cause the PHY read to fail?
2. for PHY writes, can stray register access also cause failure?
2. for MIB reads, can stray register access also cause failure?

For (1) I instrumented the PHY indirect access functions in the 6
possible places where spurious register access could occur. Of those 6
locations for spurious register access, 4 have no effect: you can put a
read or write to an unrelated register there and the PHY read will
always succeed. I tested this with spurious access to nearly every
available register on the switch.

However, for two locations of spurious register access, the PHY read
_always_ fails. The locations are marked /* XXX */ below:

/* Simplified for brevity */
static int rtl8365mb_phy_ocp_read(struct realtek_priv *priv, int phy,
				  u32 ocp_addr, u16 *data)
{
	rtl8365mb_phy_poll_busy(priv);

	rtl8365mb_phy_ocp_prepare(priv, phy, ocp_addr);

	/* Execute read operation */
	regmap_write(priv->map, RTL8365MB_INDIRECT_ACCESS_CTRL_REG, val);

	/* XXX */

	rtl8365mb_phy_poll_busy(priv);

	/* XXX */

	/* Get PHY register data */
	regmap_read(priv->map, RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG,
		    &val);

	*data = val & 0xFFFF;

	return 0;
}

In the case of a spurious read, the result of that read then poisons the
ongoing PHY read, as suggested before. Again I verified that this is
always the case, for each available register on the switch. Spurious
writes also cause failure, and in the same locations too. I did not
investigate whether the value written is then read back as part of the
PHY read.

For (2) I did something similar to (1), but the difference here is that
I could never get PHY writes to fail. Admittedly not all bits of the PHY
registers tend to be writable, but for those bits that were writable, I
would always then read back what I had written.

For (3) I did something similar to (1), and as claimed previously, this
never resulted in a read failure. Here I had to use the MIB counters of
a disconnected port so that I could assume the values were always 0.

I have attached the test module (and header file generated from an
enormous header file from the Realtek driver sources, so that I could
iterate over every possible register). It is pretty gruesome reading but
gives me confidence in my earlier claims. The only refinements to those
claims are:

- where _exactly_ a spurious register access will cause failure: see the
  /* XXX */ in the code snippet upstairs;
- PHY writes seem not to be affected at all.

Finally, I reached out to Realtek, and they confirmed pretty much the
same as above. However, they claim it is not a hardware bug, but merely
a property of the hardware design. Here I paraphrase what was said:

1. Yes, spurious register access during PHY indirect access will cause
the indirect access to fail. This is a result of the hardware design. In
general, _if a read fails, the value read back will be the result of the
last successful read_. This confirms the "register poisoning" described
earlier.

2. MIB access is a different story - this is table lookup, not indirect
access. Table lookup is not affected by spurious register access.

3. Other possible accesses - not currently present in this driver, but
for which I have some WIP changes - include ACL (Access Control List),
L2 (FDB), and MC (MDB) access. But all of these are table access similar
to MIB access, and hence not troubled by spurious register access.

4. HOWEVER, only one table can be accessed at a time. So a lock is
needed here. Currently the only table lookup is MIB access, which is
protected by mib_lock, so we are OK for now.

5. It should be sufficient to lock during indirect PHY register access
as prescribed in my patch.

I hope that clears things up. I will be sending a v2 with a revised
description, including the statements from Realtek and the results of
the tests I ran.

Kind regards,
Alvin


[-- Attachment #2: regs.h --]
[-- Type: text/plain, Size: 284915 bytes --]

/* Lifted from Realtek driver */

struct rtl_reg {
	u32 addr;
	const char *name;
};

enum reg {
RTL_REG_PORT0_CGST_HALF_CFG,
RTL_REG_TX_ERR_CNT_PORT0,
RTL_REG_PORT0_MISC_CFG,
RTL_REG_INGRESSBW_PORT0_RATE_CTRL0,
RTL_REG_INGRESSBW_PORT0_RATE_CTRL1,
RTL_REG_PORT0_FORCE_RATE0,
RTL_REG_PORT0_FORCE_RATE1,
RTL_REG_PORT0_CURENT_RATE0,
RTL_REG_PORT0_CURENT_RATE1,
RTL_REG_PORT0_PAGE_COUNTER,
RTL_REG_PAGEMETER_PORT0_CTRL0,
RTL_REG_PAGEMETER_PORT0_CTRL1,
RTL_REG_PORT0_EEECFG,
RTL_REG_PORT0_EEETXMTR,
RTL_REG_PORT0_EEERXMTR,
RTL_REG_PORT0_EEEPTXMTR,
RTL_REG_PORT0_EEEPRXMTR,
RTL_REG_PTP_PORT0_CFG1,
RTL_REG_P0_MSIC1,
RTL_REG_PORT1_CGST_HALF_CFG,
RTL_REG_TX_ERR_CNT_PORT1,
RTL_REG_PORT1_MISC_CFG,
RTL_REG_INGRESSBW_PORT1_RATE_CTRL0,
RTL_REG_INGRESSBW_PORT1_RATE_CTRL1,
RTL_REG_PORT1_FORCE_RATE0,
RTL_REG_PORT1_FORCE_RATE1,
RTL_REG_PORT1_CURENT_RATE0,
RTL_REG_PORT1_CURENT_RATE1,
RTL_REG_PORT1_PAGE_COUNTER,
RTL_REG_PAGEMETER_PORT1_CTRL0,
RTL_REG_PAGEMETER_PORT1_CTRL1,
RTL_REG_PORT1_EEECFG,
RTL_REG_PORT1_EEETXMTR,
RTL_REG_PORT1_EEERXMTR,
RTL_REG_PORT1_EEEPTXMTR,
RTL_REG_PORT1_EEEPRXMTR,
RTL_REG_PTP_PORT1_CFG1,
RTL_REG_P1_MSIC1,
RTL_REG_PORT2_CGST_HALF_CFG,
RTL_REG_TX_ERR_CNT_PORT2,
RTL_REG_PORT2_MISC_CFG,
RTL_REG_INGRESSBW_PORT2_RATE_CTRL0,
RTL_REG_INGRESSBW_PORT2_RATE_CTRL1,
RTL_REG_PORT2_FORCE_RATE0,
RTL_REG_PORT2_FORCE_RATE1,
RTL_REG_PORT2_CURENT_RATE0,
RTL_REG_PORT2_CURENT_RATE1,
RTL_REG_PORT2_PAGE_COUNTER,
RTL_REG_PAGEMETER_PORT2_CTRL0,
RTL_REG_PAGEMETER_PORT2_CTRL1,
RTL_REG_PORT2_EEECFG,
RTL_REG_PORT2_EEETXMTR,
RTL_REG_PORT2_EEERXMTR,
RTL_REG_PORT2_EEEPTXMTR,
RTL_REG_PORT2_EEEPRXMTR,
RTL_REG_PTP_PORT2_CFG1,
RTL_REG_P2_MSIC1,
RTL_REG_PORT3_CGST_HALF_CFG,
RTL_REG_TX_ERR_CNT_PORT3,
RTL_REG_PORT3_MISC_CFG,
RTL_REG_INGRESSBW_PORT3_RATE_CTRL0,
RTL_REG_INGRESSBW_PORT3_RATE_CTRL1,
RTL_REG_PORT3_FORCE_RATE0,
RTL_REG_PORT3_FORCE_RATE1,
RTL_REG_PORT3_CURENT_RATE0,
RTL_REG_PORT3_CURENT_RATE1,
RTL_REG_PORT3_PAGE_COUNTER,
RTL_REG_PAGEMETER_PORT3_CTRL0,
RTL_REG_PAGEMETER_PORT3_CTRL1,
RTL_REG_PORT3_EEECFG,
RTL_REG_PORT3_EEETXMTR,
RTL_REG_PORT3_EEERXMTR,
RTL_REG_PORT3_EEEPTXMTR,
RTL_REG_PORT3_EEEPRXMTR,
RTL_REG_PTP_PORT3_CFG1,
RTL_REG_P3_MSIC1,
RTL_REG_PORT4_CGST_HALF_CFG,
RTL_REG_TX_ERR_CNT_PORT4,
RTL_REG_PORT4_MISC_CFG,
RTL_REG_INGRESSBW_PORT4_RATE_CTRL0,
RTL_REG_INGRESSBW_PORT4_RATE_CTRL1,
RTL_REG_PORT4_FORCE_RATE0,
RTL_REG_PORT4_FORCE_RATE1,
RTL_REG_PORT4_CURENT_RATE0,
RTL_REG_PORT4_CURENT_RATE1,
RTL_REG_PORT4_PAGE_COUNTER,
RTL_REG_PAGEMETER_PORT4_CTRL0,
RTL_REG_PAGEMETER_PORT4_CTRL1,
RTL_REG_PORT4_EEECFG,
RTL_REG_PORT4_EEETXMTR,
RTL_REG_PORT4_EEERXMTR,
RTL_REG_PORT4_EEEPTXMTR,
RTL_REG_PORT4_EEEPRXMTR,
RTL_REG_PTP_PORT4_CFG1,
RTL_REG_P4_MSIC1,
RTL_REG_PORT5_CGST_HALF_CFG,
RTL_REG_TX_ERR_CNT_PORT5,
RTL_REG_PORT5_MISC_CFG,
RTL_REG_INGRESSBW_PORT5_RATE_CTRL0,
RTL_REG_INGRESSBW_PORT5_RATE_CTRL1,
RTL_REG_PORT5_FORCE_RATE0,
RTL_REG_PORT5_FORCE_RATE1,
RTL_REG_PORT5_CURENT_RATE0,
RTL_REG_PORT5_CURENT_RATE1,
RTL_REG_PORT5_PAGE_COUNTER,
RTL_REG_PAGEMETER_PORT5_CTRL0,
RTL_REG_PAGEMETER_PORT5_CTRL1,
RTL_REG_PORT5_EEECFG,
RTL_REG_PORT5_EEETXMTR,
RTL_REG_PORT5_EEERXMTR,
RTL_REG_PORT5_EEEPTXMTR,
RTL_REG_PORT5_EEEPRXMTR,
RTL_REG_PTP_PORT5_CFG1,
RTL_REG_P5_MSIC1,
RTL_REG_PORT6_CGST_HALF_CFG,
RTL_REG_TX_ERR_CNT_PORT6,
RTL_REG_PORT6_MISC_CFG,
RTL_REG_INGRESSBW_PORT6_RATE_CTRL0,
RTL_REG_INGRESSBW_PORT6_RATE_CTRL1,
RTL_REG_PORT6_FORCE_RATE0,
RTL_REG_PORT6_FORCE_RATE1,
RTL_REG_PORT6_CURENT_RATE0,
RTL_REG_PORT6_CURENT_RATE1,
RTL_REG_PORT6_PAGE_COUNTER,
RTL_REG_PAGEMETER_PORT6_CTRL0,
RTL_REG_PAGEMETER_PORT6_CTRL1,
RTL_REG_PORT6_EEECFG,
RTL_REG_PORT6_EEETXMTR,
RTL_REG_PORT6_EEERXMTR,
RTL_REG_PORT6_EEEPTXMTR,
RTL_REG_PORT6_EEEPRXMTR,
RTL_REG_PTP_PORT6_CFG1,
RTL_REG_P6_MSIC1,
RTL_REG_PORT7_CGST_HALF_CFG,
RTL_REG_TX_ERR_CNT_PORT7,
RTL_REG_PORT7_MISC_CFG,
RTL_REG_INGRESSBW_PORT7_RATE_CTRL0,
RTL_REG_INGRESSBW_PORT7_RATE_CTRL1,
RTL_REG_PORT7_FORCE_RATE0,
RTL_REG_PORT7_FORCE_RATE1,
RTL_REG_PORT7_CURENT_RATE0,
RTL_REG_PORT7_CURENT_RATE1,
RTL_REG_PORT7_PAGE_COUNTER,
RTL_REG_PAGEMETER_PORT7_CTRL0,
RTL_REG_PAGEMETER_PORT7_CTRL1,
RTL_REG_PORT7_EEECFG,
RTL_REG_PORT7_EEETXMTR,
RTL_REG_PORT7_EEERXMTR,
RTL_REG_PORT7_EEEPTXMTR,
RTL_REG_PORT7_EEEPRXMTR,
RTL_REG_PTP_PORT7_CFG1,
RTL_REG_P7_MSIC1,
RTL_REG_PORT8_CGST_HALF_CFG,
RTL_REG_TX_ERR_CNT_PORT8,
RTL_REG_PORT8_MISC_CFG,
RTL_REG_INGRESSBW_PORT8_RATE_CTRL0,
RTL_REG_INGRESSBW_PORT8_RATE_CTRL1,
RTL_REG_PORT8_FORCE_RATE0,
RTL_REG_PORT8_FORCE_RATE1,
RTL_REG_PORT8_CURENT_RATE0,
RTL_REG_PORT8_CURENT_RATE1,
RTL_REG_PORT8_PAGE_COUNTER,
RTL_REG_PAGEMETER_PORT8_CTRL0,
RTL_REG_PAGEMETER_PORT8_CTRL1,
RTL_REG_PORT8_EEECFG,
RTL_REG_PORT8_EEETXMTR,
RTL_REG_PORT8_EEERXMTR,
RTL_REG_PORT8_EEEPTXMTR,
RTL_REG_PORT8_EEEPRXMTR,
RTL_REG_PTP_PORT8_CFG1,
RTL_REG_P8_MSIC1,
RTL_REG_PORT9_CGST_HALF_CFG,
RTL_REG_TX_ERR_CNT_PORT9,
RTL_REG_PORT9_MISC_CFG,
RTL_REG_INGRESSBW_PORT9_RATE_CTRL0,
RTL_REG_INGRESSBW_PORT9_RATE_CTRL1,
RTL_REG_PORT9_FORCE_RATE0,
RTL_REG_PORT9_FORCE_RATE1,
RTL_REG_PORT9_CURENT_RATE0,
RTL_REG_PORT9_CURENT_RATE1,
RTL_REG_PORT9_PAGE_COUNTER,
RTL_REG_PAGEMETER_PORT9_CTRL0,
RTL_REG_PAGEMETER_PORT9_CTRL1,
RTL_REG_PORT9_EEECFG,
RTL_REG_PORT9_EEETXMTR,
RTL_REG_PORT9_EEERXMTR,
RTL_REG_PORT9_EEEPTXMTR,
RTL_REG_PORT9_EEEPRXMTR,
RTL_REG_PTP_PORT9_CFG1,
RTL_REG_P9_MSIC1,
RTL_REG_PORT10_CGST_HALF_CFG,
RTL_REG_TX_ERR_CNT_PORT10,
RTL_REG_PORT10_MISC_CFG,
RTL_REG_INGRESSBW_PORT10_RATE_CTRL0,
RTL_REG_INGRESSBW_PORT10_RATE_CTRL1,
RTL_REG_PORT10_FORCE_RATE0,
RTL_REG_PORT10_FORCE_RATE1,
RTL_REG_PORT10_CURENT_RATE0,
RTL_REG_PORT10_CURENT_RATE1,
RTL_REG_PORT10_PAGE_COUNTER,
RTL_REG_PAGEMETER_PORT10_CTRL0,
RTL_REG_PAGEMETER_PORT10_CTRL1,
RTL_REG_PORT10_EEECFG,
RTL_REG_PORT10_EEETXMTR,
RTL_REG_PORT10_EEERXMTR,
RTL_REG_PORT10_EEEPTXMTR,
RTL_REG_PORT10_EEEPRXMTR,
RTL_REG_PTP_PORT10_CFG1,
RTL_REG_P10_MSIC1,
RTL_REG_FLOWCTRL_QUEUE0_DROP_ON,
RTL_REG_FLOWCTRL_QUEUE1_DROP_ON,
RTL_REG_FLOWCTRL_QUEUE2_DROP_ON,
RTL_REG_FLOWCTRL_QUEUE3_DROP_ON,
RTL_REG_FLOWCTRL_QUEUE4_DROP_ON,
RTL_REG_FLOWCTRL_QUEUE5_DROP_ON,
RTL_REG_FLOWCTRL_QUEUE6_DROP_ON,
RTL_REG_FLOWCTRL_QUEUE7_DROP_ON,
RTL_REG_FLOWCTRL_PORT0_DROP_ON,
RTL_REG_FLOWCTRL_PORT1_DROP_ON,
RTL_REG_FLOWCTRL_PORT2_DROP_ON,
RTL_REG_FLOWCTRL_PORT3_DROP_ON,
RTL_REG_FLOWCTRL_PORT4_DROP_ON,
RTL_REG_FLOWCTRL_PORT5_DROP_ON,
RTL_REG_FLOWCTRL_PORT6_DROP_ON,
RTL_REG_FLOWCTRL_PORT7_DROP_ON,
RTL_REG_FLOWCTRL_PORT8_DROP_ON,
RTL_REG_FLOWCTRL_PORT9_DROP_ON,
RTL_REG_FLOWCTRL_PORT10_DROP_ON,
RTL_REG_FLOWCTRL_PORT_GAP,
RTL_REG_FLOWCTRL_QUEUE_GAP,
RTL_REG_PORT_QEMPTY,
RTL_REG_FLOWCTRL_DEBUG_CTRL0,
RTL_REG_FLOWCTRL_DEBUG_CTRL1,
RTL_REG_FLOWCTRL_QUEUE0_PAGE_COUNT,
RTL_REG_FLOWCTRL_QUEUE1_PAGE_COUNT,
RTL_REG_FLOWCTRL_QUEUE2_PAGE_COUNT,
RTL_REG_FLOWCTRL_QUEUE3_PAGE_COUNT,
RTL_REG_FLOWCTRL_QUEUE4_PAGE_COUNT,
RTL_REG_FLOWCTRL_QUEUE5_PAGE_COUNT,
RTL_REG_FLOWCTRL_QUEUE6_PAGE_COUNT,
RTL_REG_FLOWCTRL_QUEUE7_PAGE_COUNT,
RTL_REG_FLOWCTRL_PORT_PAGE_COUNT,
RTL_REG_FLOWCTRL_QUEUE0_MAX_PAGE_COUNT,
RTL_REG_FLOWCTRL_QUEUE1_MAX_PAGE_COUNT,
RTL_REG_FLOWCTRL_QUEUE2_MAX_PAGE_COUNT,
RTL_REG_FLOWCTRL_QUEUE3_MAX_PAGE_COUNT,
RTL_REG_FLOWCTRL_QUEUE4_MAX_PAGE_COUNT,
RTL_REG_FLOWCTRL_QUEUE5_MAX_PAGE_COUNT,
RTL_REG_FLOWCTRL_QUEUE6_MAX_PAGE_COUNT,
RTL_REG_FLOWCTRL_QUEUE7_MAX_PAGE_COUNT,
RTL_REG_FLOWCTRL_PORT_MAX_PAGE_COUNT,
RTL_REG_FLOWCTRL_TOTAL_PACKET_COUNT,
RTL_REG_HIGH_QUEUE_MASK0,
RTL_REG_HIGH_QUEUE_MASK1,
RTL_REG_HIGH_QUEUE_MASK2,
RTL_REG_HIGH_QUEUE_MASK3,
RTL_REG_HIGH_QUEUE_MASK4,
RTL_REG_HIGH_QUEUE_MASK5,
RTL_REG_LOW_QUEUE_TH,
RTL_REG_TH_TX_PREFET,
RTL_REG_DUMMY_0251,
RTL_REG_DUMMY_0252,
RTL_REG_DUMMY_0253,
RTL_REG_DUMMY_0254,
RTL_REG_DUMMY_0255,
RTL_REG_DUMMY_0256,
RTL_REG_DUMMY_0257,
RTL_REG_DUMMY_0258,
RTL_REG_DUMMY_0259,
RTL_REG_DUMMY_025A,
RTL_REG_DUMMY_025B,
RTL_REG_DUMMY_025C,
RTL_REG_Q_TXPKT_CNT_CTL,
RTL_REG_Q0_TXPKT_CNT_L,
RTL_REG_Q0_TXPKT_CNT_H,
RTL_REG_Q1_TXPKT_CNT_L,
RTL_REG_Q1_TXPKT_CNT_H,
RTL_REG_Q2_TXPKT_CNT_L,
RTL_REG_Q2_TXPKT_CNT_H,
RTL_REG_Q3_TXPKT_CNT_L,
RTL_REG_Q3_TXPKT_CNT_H,
RTL_REG_Q4_TXPKT_CNT_L,
RTL_REG_Q4_TXPKT_CNT_H,
RTL_REG_Q5_TXPKT_CNT_L,
RTL_REG_Q5_TXPKT_CNT_H,
RTL_REG_Q6_TXPKT_CNT_L,
RTL_REG_Q6_TXPKT_CNT_H,
RTL_REG_Q7_TXPKT_CNT_L,
RTL_REG_Q7_TXPKT_CNT_H,
RTL_REG_SCHEDULE_WFQ_CTRL,
RTL_REG_SCHEDULE_WFQ_BURST_SIZE,
RTL_REG_SCHEDULE_QUEUE_TYPE_CTRL0,
RTL_REG_SCHEDULE_QUEUE_TYPE_CTRL1,
RTL_REG_SCHEDULE_QUEUE_TYPE_CTRL2,
RTL_REG_SCHEDULE_QUEUE_TYPE_CTRL3,
RTL_REG_SCHEDULE_QUEUE_TYPE_CTRL4,
RTL_REG_SCHEDULE_QUEUE_TYPE_CTRL5,
RTL_REG_SCHEDULE_APR_CTRL0,
RTL_REG_SCHEDULE_PORT0_QUEUE0_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT0_QUEUE1_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT0_QUEUE2_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT0_QUEUE3_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT0_QUEUE4_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT0_QUEUE5_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT0_QUEUE6_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT0_QUEUE7_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT1_QUEUE0_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT1_QUEUE1_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT1_QUEUE2_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT1_QUEUE3_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT1_QUEUE4_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT1_QUEUE5_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT1_QUEUE6_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT1_QUEUE7_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT2_QUEUE0_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT2_QUEUE1_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT2_QUEUE2_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT2_QUEUE3_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT2_QUEUE4_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT2_QUEUE5_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT2_QUEUE6_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT2_QUEUE7_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT3_QUEUE0_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT3_QUEUE1_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT3_QUEUE2_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT3_QUEUE3_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT3_QUEUE4_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT3_QUEUE5_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT3_QUEUE6_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT3_QUEUE7_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT4_QUEUE0_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT4_QUEUE1_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT4_QUEUE2_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT4_QUEUE3_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT4_QUEUE4_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT4_QUEUE5_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT4_QUEUE6_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT4_QUEUE7_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT5_QUEUE0_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT5_QUEUE1_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT5_QUEUE2_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT5_QUEUE3_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT5_QUEUE4_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT5_QUEUE5_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT5_QUEUE6_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT5_QUEUE7_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT6_QUEUE0_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT6_QUEUE1_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT6_QUEUE2_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT6_QUEUE3_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT6_QUEUE4_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT6_QUEUE5_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT6_QUEUE6_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT6_QUEUE7_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT7_QUEUE0_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT7_QUEUE1_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT7_QUEUE2_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT7_QUEUE3_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT7_QUEUE4_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT7_QUEUE5_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT7_QUEUE6_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT7_QUEUE7_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT8_QUEUE0_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT8_QUEUE1_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT8_QUEUE2_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT8_QUEUE3_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT8_QUEUE4_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT8_QUEUE5_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT8_QUEUE6_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT8_QUEUE7_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT9_QUEUE0_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT9_QUEUE1_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT9_QUEUE2_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT9_QUEUE3_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT9_QUEUE4_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT9_QUEUE5_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT9_QUEUE6_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT9_QUEUE7_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT10_QUEUE0_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT10_QUEUE1_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT10_QUEUE2_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT10_QUEUE3_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT10_QUEUE4_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT10_QUEUE5_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT10_QUEUE6_WFQ_WEIGHT,
RTL_REG_SCHEDULE_PORT10_QUEUE7_WFQ_WEIGHT,
RTL_REG_PORT0_EGRESSBW_CTRL0,
RTL_REG_PORT0_EGRESSBW_CTRL1,
RTL_REG_PORT1_EGRESSBW_CTRL0,
RTL_REG_PORT1_EGRESSBW_CTRL1,
RTL_REG_PORT2_EGRESSBW_CTRL0,
RTL_REG_PORT2_EGRESSBW_CTRL1,
RTL_REG_PORT3_EGRESSBW_CTRL0,
RTL_REG_PORT3_EGRESSBW_CTRL1,
RTL_REG_PORT4_EGRESSBW_CTRL0,
RTL_REG_PORT4_EGRESSBW_CTRL1,
RTL_REG_PORT5_EGRESSBW_CTRL0,
RTL_REG_PORT5_EGRESSBW_CTRL1,
RTL_REG_PORT6_EGRESSBW_CTRL0,
RTL_REG_PORT6_EGRESSBW_CTRL1,
RTL_REG_PORT7_EGRESSBW_CTRL0,
RTL_REG_PORT7_EGRESSBW_CTRL1,
RTL_REG_PORT8_EGRESSBW_CTRL0,
RTL_REG_PORT8_EGRESSBW_CTRL1,
RTL_REG_PORT9_EGRESSBW_CTRL0,
RTL_REG_PORT9_EGRESSBW_CTRL1,
RTL_REG_PORT10_EGRESSBW_CTRL0,
RTL_REG_PORT10_EGRESSBW_CTRL1,
RTL_REG_SCHEDULE_PORT0_APR_METER_CTRL0,
RTL_REG_SCHEDULE_PORT0_APR_METER_CTRL1,
RTL_REG_SCHEDULE_PORT1_APR_METER_CTRL0,
RTL_REG_SCHEDULE_PORT1_APR_METER_CTRL1,
RTL_REG_SCHEDULE_PORT2_APR_METER_CTRL0,
RTL_REG_SCHEDULE_PORT2_APR_METER_CTRL1,
RTL_REG_SCHEDULE_PORT3_APR_METER_CTRL0,
RTL_REG_SCHEDULE_PORT3_APR_METER_CTRL1,
RTL_REG_SCHEDULE_PORT4_APR_METER_CTRL0,
RTL_REG_SCHEDULE_PORT4_APR_METER_CTRL1,
RTL_REG_SCHEDULE_PORT5_APR_METER_CTRL0,
RTL_REG_SCHEDULE_PORT5_APR_METER_CTRL1,
RTL_REG_SCHEDULE_PORT6_APR_METER_CTRL0,
RTL_REG_SCHEDULE_PORT6_APR_METER_CTRL1,
RTL_REG_SCHEDULE_PORT7_APR_METER_CTRL0,
RTL_REG_SCHEDULE_PORT7_APR_METER_CTRL1,
RTL_REG_SCHEDULE_PORT8_APR_METER_CTRL0,
RTL_REG_SCHEDULE_PORT8_APR_METER_CTRL1,
RTL_REG_SCHEDULE_PORT9_APR_METER_CTRL0,
RTL_REG_SCHEDULE_PORT9_APR_METER_CTRL1,
RTL_REG_SCHEDULE_PORT10_APR_METER_CTRL0,
RTL_REG_SCHEDULE_PORT10_APR_METER_CTRL1,
RTL_REG_LINE_RATE_1G_L,
RTL_REG_LINE_RATE_1G_H,
RTL_REG_LINE_RATE_100_L,
RTL_REG_LINE_RATE_100_H,
RTL_REG_LINE_RATE_10_L,
RTL_REG_LINE_RATE_10_H,
RTL_REG_DUMMY_03f2,
RTL_REG_DUMMY_03f3,
RTL_REG_DUMMY_03f4,
RTL_REG_DUMMY_03f5,
RTL_REG_DUMMY_03f6,
RTL_REG_BYPASS_LINE_RATE,
RTL_REG_LINE_RATE_500_H,
RTL_REG_LINE_RATE_500_L,
RTL_REG_LINE_RATE_HSG_H,
RTL_REG_LINE_RATE_HSG_L,
RTL_REG_TABLE_ACCESS_CTRL,
RTL_REG_TABLE_ACCESS_ADDR,
RTL_REG_TABLE_LUT_ADDR,
RTL_REG_HSA_HSB_LATCH,
RTL_REG_HSA_HSB_LATCH2,
RTL_REG_TABLE_WRITE_DATA0,
RTL_REG_TABLE_WRITE_DATA1,
RTL_REG_TABLE_WRITE_DATA2,
RTL_REG_TABLE_WRITE_DATA3,
RTL_REG_TABLE_WRITE_DATA4,
RTL_REG_TABLE_WRITE_DATA5,
RTL_REG_TABLE_WRITE_DATA6,
RTL_REG_TABLE_WRITE_DATA7,
RTL_REG_TABLE_WRITE_DATA8,
RTL_REG_TABLE_WRITE_DATA9,
RTL_REG_TABLE_READ_DATA0,
RTL_REG_TABLE_READ_DATA1,
RTL_REG_TABLE_READ_DATA2,
RTL_REG_TABLE_READ_DATA3,
RTL_REG_TABLE_READ_DATA4,
RTL_REG_TABLE_READ_DATA5,
RTL_REG_TABLE_READ_DATA6,
RTL_REG_TABLE_READ_DATA7,
RTL_REG_TABLE_READ_DATA8,
RTL_REG_TABLE_READ_DATA9,
RTL_REG_TBL_DUMMY00,
RTL_REG_TBL_DUMMY01,
RTL_REG_ACL_RULE_TEMPLATE0_CTRL0,
RTL_REG_ACL_RULE_TEMPLATE0_CTRL1,
RTL_REG_ACL_RULE_TEMPLATE0_CTRL2,
RTL_REG_ACL_RULE_TEMPLATE0_CTRL3,
RTL_REG_ACL_RULE_TEMPLATE1_CTRL0,
RTL_REG_ACL_RULE_TEMPLATE1_CTRL1,
RTL_REG_ACL_RULE_TEMPLATE1_CTRL2,
RTL_REG_ACL_RULE_TEMPLATE1_CTRL3,
RTL_REG_ACL_RULE_TEMPLATE2_CTRL0,
RTL_REG_ACL_RULE_TEMPLATE2_CTRL1,
RTL_REG_ACL_RULE_TEMPLATE2_CTRL2,
RTL_REG_ACL_RULE_TEMPLATE2_CTRL3,
RTL_REG_ACL_RULE_TEMPLATE3_CTRL0,
RTL_REG_ACL_RULE_TEMPLATE3_CTRL1,
RTL_REG_ACL_RULE_TEMPLATE3_CTRL2,
RTL_REG_ACL_RULE_TEMPLATE3_CTRL3,
RTL_REG_ACL_RULE_TEMPLATE4_CTRL0,
RTL_REG_ACL_RULE_TEMPLATE4_CTRL1,
RTL_REG_ACL_RULE_TEMPLATE4_CTRL2,
RTL_REG_ACL_RULE_TEMPLATE4_CTRL3,
RTL_REG_ACL_ACTION_CTRL0,
RTL_REG_ACL_ACTION_CTRL1,
RTL_REG_ACL_ACTION_CTRL2,
RTL_REG_ACL_ACTION_CTRL3,
RTL_REG_ACL_ACTION_CTRL4,
RTL_REG_ACL_ACTION_CTRL5,
RTL_REG_ACL_ACTION_CTRL6,
RTL_REG_ACL_ACTION_CTRL7,
RTL_REG_ACL_ACTION_CTRL8,
RTL_REG_ACL_ACTION_CTRL9,
RTL_REG_ACL_ACTION_CTRL10,
RTL_REG_ACL_ACTION_CTRL11,
RTL_REG_ACL_ACTION_CTRL12,
RTL_REG_ACL_ACTION_CTRL13,
RTL_REG_ACL_ACTION_CTRL14,
RTL_REG_ACL_ACTION_CTRL15,
RTL_REG_ACL_ACTION_CTRL16,
RTL_REG_ACL_ACTION_CTRL17,
RTL_REG_ACL_ACTION_CTRL18,
RTL_REG_ACL_ACTION_CTRL19,
RTL_REG_ACL_ACTION_CTRL20,
RTL_REG_ACL_ACTION_CTRL21,
RTL_REG_ACL_ACTION_CTRL22,
RTL_REG_ACL_ACTION_CTRL23,
RTL_REG_ACL_ACTION_CTRL24,
RTL_REG_ACL_ACTION_CTRL25,
RTL_REG_ACL_ACTION_CTRL26,
RTL_REG_ACL_ACTION_CTRL27,
RTL_REG_ACL_ACTION_CTRL28,
RTL_REG_ACL_ACTION_CTRL29,
RTL_REG_ACL_ACTION_CTRL30,
RTL_REG_ACL_ACTION_CTRL31,
RTL_REG_ACL_SDPORT_RANGE_ENTRY0_CTRL0,
RTL_REG_ACL_SDPORT_RANGE_ENTRY0_CTRL1,
RTL_REG_ACL_SDPORT_RANGE_ENTRY0_CTRL2,
RTL_REG_ACL_SDPORT_RANGE_ENTRY1_CTRL0,
RTL_REG_ACL_SDPORT_RANGE_ENTRY1_CTRL1,
RTL_REG_ACL_SDPORT_RANGE_ENTRY1_CTRL2,
RTL_REG_ACL_SDPORT_RANGE_ENTRY2_CTRL0,
RTL_REG_ACL_SDPORT_RANGE_ENTRY2_CTRL1,
RTL_REG_ACL_SDPORT_RANGE_ENTRY2_CTRL2,
RTL_REG_ACL_SDPORT_RANGE_ENTRY3_CTRL0,
RTL_REG_ACL_SDPORT_RANGE_ENTRY3_CTRL1,
RTL_REG_ACL_SDPORT_RANGE_ENTRY3_CTRL2,
RTL_REG_ACL_SDPORT_RANGE_ENTRY4_CTRL0,
RTL_REG_ACL_SDPORT_RANGE_ENTRY4_CTRL1,
RTL_REG_ACL_SDPORT_RANGE_ENTRY4_CTRL2,
RTL_REG_ACL_SDPORT_RANGE_ENTRY5_CTRL0,
RTL_REG_ACL_SDPORT_RANGE_ENTRY5_CTRL1,
RTL_REG_ACL_SDPORT_RANGE_ENTRY5_CTRL2,
RTL_REG_ACL_SDPORT_RANGE_ENTRY6_CTRL0,
RTL_REG_ACL_SDPORT_RANGE_ENTRY6_CTRL1,
RTL_REG_ACL_SDPORT_RANGE_ENTRY6_CTRL2,
RTL_REG_ACL_SDPORT_RANGE_ENTRY7_CTRL0,
RTL_REG_ACL_SDPORT_RANGE_ENTRY7_CTRL1,
RTL_REG_ACL_SDPORT_RANGE_ENTRY7_CTRL2,
RTL_REG_ACL_SDPORT_RANGE_ENTRY8_CTRL0,
RTL_REG_ACL_SDPORT_RANGE_ENTRY8_CTRL1,
RTL_REG_ACL_SDPORT_RANGE_ENTRY8_CTRL2,
RTL_REG_ACL_SDPORT_RANGE_ENTRY9_CTRL0,
RTL_REG_ACL_SDPORT_RANGE_ENTRY9_CTRL1,
RTL_REG_ACL_SDPORT_RANGE_ENTRY9_CTRL2,
RTL_REG_ACL_SDPORT_RANGE_ENTRY10_CTRL0,
RTL_REG_ACL_SDPORT_RANGE_ENTRY10_CTRL1,
RTL_REG_ACL_SDPORT_RANGE_ENTRY10_CTRL2,
RTL_REG_ACL_SDPORT_RANGE_ENTRY11_CTRL0,
RTL_REG_ACL_SDPORT_RANGE_ENTRY11_CTRL1,
RTL_REG_ACL_SDPORT_RANGE_ENTRY11_CTRL2,
RTL_REG_ACL_SDPORT_RANGE_ENTRY12_CTRL0,
RTL_REG_ACL_SDPORT_RANGE_ENTRY12_CTRL1,
RTL_REG_ACL_SDPORT_RANGE_ENTRY12_CTRL2,
RTL_REG_ACL_SDPORT_RANGE_ENTRY13_CTRL0,
RTL_REG_ACL_SDPORT_RANGE_ENTRY13_CTRL1,
RTL_REG_ACL_SDPORT_RANGE_ENTRY13_CTRL2,
RTL_REG_ACL_SDPORT_RANGE_ENTRY14_CTRL0,
RTL_REG_ACL_SDPORT_RANGE_ENTRY14_CTRL1,
RTL_REG_ACL_SDPORT_RANGE_ENTRY14_CTRL2,
RTL_REG_ACL_SDPORT_RANGE_ENTRY15_CTRL0,
RTL_REG_ACL_SDPORT_RANGE_ENTRY15_CTRL1,
RTL_REG_ACL_SDPORT_RANGE_ENTRY15_CTRL2,
RTL_REG_ACL_VID_RANGE_ENTRY0_CTRL0,
RTL_REG_ACL_VID_RANGE_ENTRY0_CTRL1,
RTL_REG_ACL_VID_RANGE_ENTRY1_CTRL0,
RTL_REG_ACL_VID_RANGE_ENTRY1_CTRL1,
RTL_REG_ACL_VID_RANGE_ENTRY2_CTRL0,
RTL_REG_ACL_VID_RANGE_ENTRY2_CTRL1,
RTL_REG_ACL_VID_RANGE_ENTRY3_CTRL0,
RTL_REG_ACL_VID_RANGE_ENTRY3_CTRL1,
RTL_REG_ACL_VID_RANGE_ENTRY4_CTRL0,
RTL_REG_ACL_VID_RANGE_ENTRY4_CTRL1,
RTL_REG_ACL_VID_RANGE_ENTRY5_CTRL0,
RTL_REG_ACL_VID_RANGE_ENTRY5_CTRL1,
RTL_REG_ACL_VID_RANGE_ENTRY6_CTRL0,
RTL_REG_ACL_VID_RANGE_ENTRY6_CTRL1,
RTL_REG_ACL_VID_RANGE_ENTRY7_CTRL0,
RTL_REG_ACL_VID_RANGE_ENTRY7_CTRL1,
RTL_REG_ACL_VID_RANGE_ENTRY8_CTRL0,
RTL_REG_ACL_VID_RANGE_ENTRY8_CTRL1,
RTL_REG_ACL_VID_RANGE_ENTRY9_CTRL0,
RTL_REG_ACL_VID_RANGE_ENTRY9_CTRL1,
RTL_REG_ACL_VID_RANGE_ENTRY10_CTRL0,
RTL_REG_ACL_VID_RANGE_ENTRY10_CTRL1,
RTL_REG_ACL_VID_RANGE_ENTRY11_CTRL0,
RTL_REG_ACL_VID_RANGE_ENTRY11_CTRL1,
RTL_REG_ACL_VID_RANGE_ENTRY12_CTRL0,
RTL_REG_ACL_VID_RANGE_ENTRY12_CTRL1,
RTL_REG_ACL_VID_RANGE_ENTRY13_CTRL0,
RTL_REG_ACL_VID_RANGE_ENTRY13_CTRL1,
RTL_REG_ACL_VID_RANGE_ENTRY14_CTRL0,
RTL_REG_ACL_VID_RANGE_ENTRY14_CTRL1,
RTL_REG_ACL_VID_RANGE_ENTRY15_CTRL0,
RTL_REG_ACL_VID_RANGE_ENTRY15_CTRL1,
RTL_REG_ACL_IP_RANGE_ENTRY0_CTRL0,
RTL_REG_ACL_IP_RANGE_ENTRY0_CTRL1,
RTL_REG_ACL_IP_RANGE_ENTRY0_CTRL2,
RTL_REG_ACL_IP_RANGE_ENTRY0_CTRL3,
RTL_REG_ACL_IP_RANGE_ENTRY0_CTRL4,
RTL_REG_ACL_IP_RANGE_ENTRY1_CTRL0,
RTL_REG_ACL_IP_RANGE_ENTRY1_CTRL1,
RTL_REG_ACL_IP_RANGE_ENTRY1_CTRL2,
RTL_REG_ACL_IP_RANGE_ENTRY1_CTRL3,
RTL_REG_ACL_IP_RANGE_ENTRY1_CTRL4,
RTL_REG_ACL_IP_RANGE_ENTRY2_CTRL0,
RTL_REG_ACL_IP_RANGE_ENTRY2_CTRL1,
RTL_REG_ACL_IP_RANGE_ENTRY2_CTRL2,
RTL_REG_ACL_IP_RANGE_ENTRY2_CTRL3,
RTL_REG_ACL_IP_RANGE_ENTRY2_CTRL4,
RTL_REG_ACL_IP_RANGE_ENTRY3_CTRL0,
RTL_REG_ACL_IP_RANGE_ENTRY3_CTRL1,
RTL_REG_ACL_IP_RANGE_ENTRY3_CTRL2,
RTL_REG_ACL_IP_RANGE_ENTRY3_CTRL3,
RTL_REG_ACL_IP_RANGE_ENTRY3_CTRL4,
RTL_REG_ACL_IP_RANGE_ENTRY4_CTRL0,
RTL_REG_ACL_IP_RANGE_ENTRY4_CTRL1,
RTL_REG_ACL_IP_RANGE_ENTRY4_CTRL2,
RTL_REG_ACL_IP_RANGE_ENTRY4_CTRL3,
RTL_REG_ACL_IP_RANGE_ENTRY4_CTRL4,
RTL_REG_ACL_IP_RANGE_ENTRY5_CTRL0,
RTL_REG_ACL_IP_RANGE_ENTRY5_CTRL1,
RTL_REG_ACL_IP_RANGE_ENTRY5_CTRL2,
RTL_REG_ACL_IP_RANGE_ENTRY5_CTRL3,
RTL_REG_ACL_IP_RANGE_ENTRY5_CTRL4,
RTL_REG_ACL_IP_RANGE_ENTRY6_CTRL0,
RTL_REG_ACL_IP_RANGE_ENTRY6_CTRL1,
RTL_REG_ACL_IP_RANGE_ENTRY6_CTRL2,
RTL_REG_ACL_IP_RANGE_ENTRY6_CTRL3,
RTL_REG_ACL_IP_RANGE_ENTRY6_CTRL4,
RTL_REG_ACL_IP_RANGE_ENTRY7_CTRL0,
RTL_REG_ACL_IP_RANGE_ENTRY7_CTRL1,
RTL_REG_ACL_IP_RANGE_ENTRY7_CTRL2,
RTL_REG_ACL_IP_RANGE_ENTRY7_CTRL3,
RTL_REG_ACL_IP_RANGE_ENTRY7_CTRL4,
RTL_REG_ACL_IP_RANGE_ENTRY8_CTRL0,
RTL_REG_ACL_IP_RANGE_ENTRY8_CTRL1,
RTL_REG_ACL_IP_RANGE_ENTRY8_CTRL2,
RTL_REG_ACL_IP_RANGE_ENTRY8_CTRL3,
RTL_REG_ACL_IP_RANGE_ENTRY8_CTRL4,
RTL_REG_ACL_IP_RANGE_ENTRY9_CTRL0,
RTL_REG_ACL_IP_RANGE_ENTRY9_CTRL1,
RTL_REG_ACL_IP_RANGE_ENTRY9_CTRL2,
RTL_REG_ACL_IP_RANGE_ENTRY9_CTRL3,
RTL_REG_ACL_IP_RANGE_ENTRY9_CTRL4,
RTL_REG_ACL_IP_RANGE_ENTRY10_CTRL0,
RTL_REG_ACL_IP_RANGE_ENTRY10_CTRL1,
RTL_REG_ACL_IP_RANGE_ENTRY10_CTRL2,
RTL_REG_ACL_IP_RANGE_ENTRY10_CTRL3,
RTL_REG_ACL_IP_RANGE_ENTRY10_CTRL4,
RTL_REG_ACL_IP_RANGE_ENTRY11_CTRL0,
RTL_REG_ACL_IP_RANGE_ENTRY11_CTRL1,
RTL_REG_ACL_IP_RANGE_ENTRY11_CTRL2,
RTL_REG_ACL_IP_RANGE_ENTRY11_CTRL3,
RTL_REG_ACL_IP_RANGE_ENTRY11_CTRL4,
RTL_REG_ACL_IP_RANGE_ENTRY12_CTRL0,
RTL_REG_ACL_IP_RANGE_ENTRY12_CTRL1,
RTL_REG_ACL_IP_RANGE_ENTRY12_CTRL2,
RTL_REG_ACL_IP_RANGE_ENTRY12_CTRL3,
RTL_REG_ACL_IP_RANGE_ENTRY12_CTRL4,
RTL_REG_ACL_IP_RANGE_ENTRY13_CTRL0,
RTL_REG_ACL_IP_RANGE_ENTRY13_CTRL1,
RTL_REG_ACL_IP_RANGE_ENTRY13_CTRL2,
RTL_REG_ACL_IP_RANGE_ENTRY13_CTRL3,
RTL_REG_ACL_IP_RANGE_ENTRY13_CTRL4,
RTL_REG_ACL_IP_RANGE_ENTRY14_CTRL0,
RTL_REG_ACL_IP_RANGE_ENTRY14_CTRL1,
RTL_REG_ACL_IP_RANGE_ENTRY14_CTRL2,
RTL_REG_ACL_IP_RANGE_ENTRY14_CTRL3,
RTL_REG_ACL_IP_RANGE_ENTRY14_CTRL4,
RTL_REG_ACL_IP_RANGE_ENTRY15_CTRL0,
RTL_REG_ACL_IP_RANGE_ENTRY15_CTRL1,
RTL_REG_ACL_IP_RANGE_ENTRY15_CTRL2,
RTL_REG_ACL_IP_RANGE_ENTRY15_CTRL3,
RTL_REG_ACL_IP_RANGE_ENTRY15_CTRL4,
RTL_REG_ACL_ENABLE,
RTL_REG_ACL_UNMATCH_PERMIT,
RTL_REG_ACL_GPIO_POLARITY,
RTL_REG_ACL_LOG_CNT_TYPE,
RTL_REG_ACL_RESET_CFG,
RTL_REG_ACL_DUMMY00,
RTL_REG_ACL_DUMMY01,
RTL_REG_ACL_DUMMY02,
RTL_REG_ACL_DUMMY03,
RTL_REG_ACL_DUMMY04,
RTL_REG_ACL_DUMMY05,
RTL_REG_ACL_DUMMY06,
RTL_REG_ACL_DUMMY07,
RTL_REG_ACL_REASON_01,
RTL_REG_ACL_REASON_23,
RTL_REG_ACL_REASON_45,
RTL_REG_ACL_ACCESS_MODE,
RTL_REG_ACL_ACTION_CTRL32,
RTL_REG_ACL_ACTION_CTRL33,
RTL_REG_ACL_ACTION_CTRL34,
RTL_REG_ACL_ACTION_CTRL35,
RTL_REG_ACL_ACTION_CTRL36,
RTL_REG_ACL_ACTION_CTRL37,
RTL_REG_ACL_ACTION_CTRL38,
RTL_REG_ACL_ACTION_CTRL39,
RTL_REG_ACL_ACTION_CTRL40,
RTL_REG_ACL_ACTION_CTRL41,
RTL_REG_ACL_ACTION_CTRL42,
RTL_REG_ACL_ACTION_CTRL43,
RTL_REG_ACL_ACTION_CTRL44,
RTL_REG_ACL_ACTION_CTRL45,
RTL_REG_ACL_ACTION_CTRL46,
RTL_REG_ACL_ACTION_CTRL47,
RTL_REG_VLAN_PVID_CTRL0,
RTL_REG_VLAN_PVID_CTRL1,
RTL_REG_VLAN_PVID_CTRL2,
RTL_REG_VLAN_PVID_CTRL3,
RTL_REG_VLAN_PVID_CTRL4,
RTL_REG_VLAN_PVID_CTRL5,
RTL_REG_VLAN_PPB0_VALID,
RTL_REG_VLAN_PPB0_CTRL0,
RTL_REG_VLAN_PPB0_CTRL1,
RTL_REG_VLAN_PPB0_CTRL2,
RTL_REG_VLAN_PPB0_CTRL4,
RTL_REG_VLAN_PPB0_CTRL3,
RTL_REG_VLAN_PPB1_VALID,
RTL_REG_VLAN_PPB1_CTRL0,
RTL_REG_VLAN_PPB1_CTRL1,
RTL_REG_VLAN_PPB1_CTRL2,
RTL_REG_VLAN_PPB1_CTRL4,
RTL_REG_VLAN_PPB1_CTRL3,
RTL_REG_VLAN_PPB2_VALID,
RTL_REG_VLAN_PPB2_CTRL0,
RTL_REG_VLAN_PPB2_CTRL1,
RTL_REG_VLAN_PPB2_CTRL2,
RTL_REG_VLAN_PPB2_CTRL4,
RTL_REG_VLAN_PPB2_CTRL3,
RTL_REG_VLAN_PPB3_VALID,
RTL_REG_VLAN_PPB3_CTRL0,
RTL_REG_VLAN_PPB3_CTRL1,
RTL_REG_VLAN_PPB3_CTRL2,
RTL_REG_VLAN_PPB3_CTRL4,
RTL_REG_VLAN_PPB3_CTRL3,
RTL_REG_VLAN_MEMBER_CONFIGURATION0_CTRL0,
RTL_REG_VLAN_MEMBER_CONFIGURATION0_CTRL1,
RTL_REG_VLAN_MEMBER_CONFIGURATION0_CTRL2,
RTL_REG_VLAN_MEMBER_CONFIGURATION0_CTRL3,
RTL_REG_VLAN_MEMBER_CONFIGURATION1_CTRL0,
RTL_REG_VLAN_MEMBER_CONFIGURATION1_CTRL1,
RTL_REG_VLAN_MEMBER_CONFIGURATION1_CTRL2,
RTL_REG_VLAN_MEMBER_CONFIGURATION1_CTRL3,
RTL_REG_VLAN_MEMBER_CONFIGURATION2_CTRL0,
RTL_REG_VLAN_MEMBER_CONFIGURATION2_CTRL1,
RTL_REG_VLAN_MEMBER_CONFIGURATION2_CTRL2,
RTL_REG_VLAN_MEMBER_CONFIGURATION2_CTRL3,
RTL_REG_VLAN_MEMBER_CONFIGURATION3_CTRL0,
RTL_REG_VLAN_MEMBER_CONFIGURATION3_CTRL1,
RTL_REG_VLAN_MEMBER_CONFIGURATION3_CTRL2,
RTL_REG_VLAN_MEMBER_CONFIGURATION3_CTRL3,
RTL_REG_VLAN_MEMBER_CONFIGURATION4_CTRL0,
RTL_REG_VLAN_MEMBER_CONFIGURATION4_CTRL1,
RTL_REG_VLAN_MEMBER_CONFIGURATION4_CTRL2,
RTL_REG_VLAN_MEMBER_CONFIGURATION4_CTRL3,
RTL_REG_VLAN_MEMBER_CONFIGURATION5_CTRL0,
RTL_REG_VLAN_MEMBER_CONFIGURATION5_CTRL1,
RTL_REG_VLAN_MEMBER_CONFIGURATION5_CTRL2,
RTL_REG_VLAN_MEMBER_CONFIGURATION5_CTRL3,
RTL_REG_VLAN_MEMBER_CONFIGURATION6_CTRL0,
RTL_REG_VLAN_MEMBER_CONFIGURATION6_CTRL1,
RTL_REG_VLAN_MEMBER_CONFIGURATION6_CTRL2,
RTL_REG_VLAN_MEMBER_CONFIGURATION6_CTRL3,
RTL_REG_VLAN_MEMBER_CONFIGURATION7_CTRL0,
RTL_REG_VLAN_MEMBER_CONFIGURATION7_CTRL1,
RTL_REG_VLAN_MEMBER_CONFIGURATION7_CTRL2,
RTL_REG_VLAN_MEMBER_CONFIGURATION7_CTRL3,
RTL_REG_VLAN_MEMBER_CONFIGURATION8_CTRL0,
RTL_REG_VLAN_MEMBER_CONFIGURATION8_CTRL1,
RTL_REG_VLAN_MEMBER_CONFIGURATION8_CTRL2,
RTL_REG_VLAN_MEMBER_CONFIGURATION8_CTRL3,
RTL_REG_VLAN_MEMBER_CONFIGURATION9_CTRL0,
RTL_REG_VLAN_MEMBER_CONFIGURATION9_CTRL1,
RTL_REG_VLAN_MEMBER_CONFIGURATION9_CTRL2,
RTL_REG_VLAN_MEMBER_CONFIGURATION9_CTRL3,
RTL_REG_VLAN_MEMBER_CONFIGURATION10_CTRL0,
RTL_REG_VLAN_MEMBER_CONFIGURATION10_CTRL1,
RTL_REG_VLAN_MEMBER_CONFIGURATION10_CTRL2,
RTL_REG_VLAN_MEMBER_CONFIGURATION10_CTRL3,
RTL_REG_VLAN_MEMBER_CONFIGURATION11_CTRL0,
RTL_REG_VLAN_MEMBER_CONFIGURATION11_CTRL1,
RTL_REG_VLAN_MEMBER_CONFIGURATION11_CTRL2,
RTL_REG_VLAN_MEMBER_CONFIGURATION11_CTRL3,
RTL_REG_VLAN_MEMBER_CONFIGURATION12_CTRL0,
RTL_REG_VLAN_MEMBER_CONFIGURATION12_CTRL1,
RTL_REG_VLAN_MEMBER_CONFIGURATION12_CTRL2,
RTL_REG_VLAN_MEMBER_CONFIGURATION12_CTRL3,
RTL_REG_VLAN_MEMBER_CONFIGURATION13_CTRL0,
RTL_REG_VLAN_MEMBER_CONFIGURATION13_CTRL1,
RTL_REG_VLAN_MEMBER_CONFIGURATION13_CTRL2,
RTL_REG_VLAN_MEMBER_CONFIGURATION13_CTRL3,
RTL_REG_VLAN_MEMBER_CONFIGURATION14_CTRL0,
RTL_REG_VLAN_MEMBER_CONFIGURATION14_CTRL1,
RTL_REG_VLAN_MEMBER_CONFIGURATION14_CTRL2,
RTL_REG_VLAN_MEMBER_CONFIGURATION14_CTRL3,
RTL_REG_VLAN_MEMBER_CONFIGURATION15_CTRL0,
RTL_REG_VLAN_MEMBER_CONFIGURATION15_CTRL1,
RTL_REG_VLAN_MEMBER_CONFIGURATION15_CTRL2,
RTL_REG_VLAN_MEMBER_CONFIGURATION15_CTRL3,
RTL_REG_VLAN_MEMBER_CONFIGURATION16_CTRL0,
RTL_REG_VLAN_MEMBER_CONFIGURATION16_CTRL1,
RTL_REG_VLAN_MEMBER_CONFIGURATION16_CTRL2,
RTL_REG_VLAN_MEMBER_CONFIGURATION16_CTRL3,
RTL_REG_VLAN_MEMBER_CONFIGURATION17_CTRL0,
RTL_REG_VLAN_MEMBER_CONFIGURATION17_CTRL1,
RTL_REG_VLAN_MEMBER_CONFIGURATION17_CTRL2,
RTL_REG_VLAN_MEMBER_CONFIGURATION17_CTRL3,
RTL_REG_VLAN_MEMBER_CONFIGURATION18_CTRL0,
RTL_REG_VLAN_MEMBER_CONFIGURATION18_CTRL1,
RTL_REG_VLAN_MEMBER_CONFIGURATION18_CTRL2,
RTL_REG_VLAN_MEMBER_CONFIGURATION18_CTRL3,
RTL_REG_VLAN_MEMBER_CONFIGURATION19_CTRL0,
RTL_REG_VLAN_MEMBER_CONFIGURATION19_CTRL1,
RTL_REG_VLAN_MEMBER_CONFIGURATION19_CTRL2,
RTL_REG_VLAN_MEMBER_CONFIGURATION19_CTRL3,
RTL_REG_VLAN_MEMBER_CONFIGURATION20_CTRL0,
RTL_REG_VLAN_MEMBER_CONFIGURATION20_CTRL1,
RTL_REG_VLAN_MEMBER_CONFIGURATION20_CTRL2,
RTL_REG_VLAN_MEMBER_CONFIGURATION20_CTRL3,
RTL_REG_VLAN_MEMBER_CONFIGURATION21_CTRL0,
RTL_REG_VLAN_MEMBER_CONFIGURATION21_CTRL1,
RTL_REG_VLAN_MEMBER_CONFIGURATION21_CTRL2,
RTL_REG_VLAN_MEMBER_CONFIGURATION21_CTRL3,
RTL_REG_VLAN_MEMBER_CONFIGURATION22_CTRL0,
RTL_REG_VLAN_MEMBER_CONFIGURATION22_CTRL1,
RTL_REG_VLAN_MEMBER_CONFIGURATION22_CTRL2,
RTL_REG_VLAN_MEMBER_CONFIGURATION22_CTRL3,
RTL_REG_VLAN_MEMBER_CONFIGURATION23_CTRL0,
RTL_REG_VLAN_MEMBER_CONFIGURATION23_CTRL1,
RTL_REG_VLAN_MEMBER_CONFIGURATION23_CTRL2,
RTL_REG_VLAN_MEMBER_CONFIGURATION23_CTRL3,
RTL_REG_VLAN_MEMBER_CONFIGURATION24_CTRL0,
RTL_REG_VLAN_MEMBER_CONFIGURATION24_CTRL1,
RTL_REG_VLAN_MEMBER_CONFIGURATION24_CTRL2,
RTL_REG_VLAN_MEMBER_CONFIGURATION24_CTRL3,
RTL_REG_VLAN_MEMBER_CONFIGURATION25_CTRL0,
RTL_REG_VLAN_MEMBER_CONFIGURATION25_CTRL1,
RTL_REG_VLAN_MEMBER_CONFIGURATION25_CTRL2,
RTL_REG_VLAN_MEMBER_CONFIGURATION25_CTRL3,
RTL_REG_VLAN_MEMBER_CONFIGURATION26_CTRL0,
RTL_REG_VLAN_MEMBER_CONFIGURATION26_CTRL1,
RTL_REG_VLAN_MEMBER_CONFIGURATION26_CTRL2,
RTL_REG_VLAN_MEMBER_CONFIGURATION26_CTRL3,
RTL_REG_VLAN_MEMBER_CONFIGURATION27_CTRL0,
RTL_REG_VLAN_MEMBER_CONFIGURATION27_CTRL1,
RTL_REG_VLAN_MEMBER_CONFIGURATION27_CTRL2,
RTL_REG_VLAN_MEMBER_CONFIGURATION27_CTRL3,
RTL_REG_VLAN_MEMBER_CONFIGURATION28_CTRL0,
RTL_REG_VLAN_MEMBER_CONFIGURATION28_CTRL1,
RTL_REG_VLAN_MEMBER_CONFIGURATION28_CTRL2,
RTL_REG_VLAN_MEMBER_CONFIGURATION28_CTRL3,
RTL_REG_VLAN_MEMBER_CONFIGURATION29_CTRL0,
RTL_REG_VLAN_MEMBER_CONFIGURATION29_CTRL1,
RTL_REG_VLAN_MEMBER_CONFIGURATION29_CTRL2,
RTL_REG_VLAN_MEMBER_CONFIGURATION29_CTRL3,
RTL_REG_VLAN_MEMBER_CONFIGURATION30_CTRL0,
RTL_REG_VLAN_MEMBER_CONFIGURATION30_CTRL1,
RTL_REG_VLAN_MEMBER_CONFIGURATION30_CTRL2,
RTL_REG_VLAN_MEMBER_CONFIGURATION30_CTRL3,
RTL_REG_VLAN_MEMBER_CONFIGURATION31_CTRL0,
RTL_REG_VLAN_MEMBER_CONFIGURATION31_CTRL1,
RTL_REG_VLAN_MEMBER_CONFIGURATION31_CTRL2,
RTL_REG_VLAN_MEMBER_CONFIGURATION31_CTRL3,
RTL_REG_VLAN_CTRL,
RTL_REG_VLAN_INGRESS,
RTL_REG_VLAN_ACCEPT_FRAME_TYPE_CTRL0,
RTL_REG_VLAN_ACCEPT_FRAME_TYPE_CTRL1,
RTL_REG_PORT_PBFIDEN,
RTL_REG_PORT0_PBFID,
RTL_REG_PORT1_PBFID,
RTL_REG_PORT2_PBFID,
RTL_REG_PORT3_PBFID,
RTL_REG_PORT4_PBFID,
RTL_REG_PORT5_PBFID,
RTL_REG_PORT6_PBFID,
RTL_REG_PORT7_PBFID,
RTL_REG_VLAN_EXT_CTRL,
RTL_REG_VLAN_EXT_CTRL2,
RTL_REG_PORT8_PBFID,
RTL_REG_PORT9_PBFID,
RTL_REG_PORT10_PBFID,
RTL_REG_CVLAN_DUMMY00,
RTL_REG_CVLAN_DUMMY01,
RTL_REG_CVLAN_DUMMY02,
RTL_REG_CVLAN_DUMMY03,
RTL_REG_CVLAN_DUMMY04,
RTL_REG_CVLAN_DUMMY05,
RTL_REG_CVLAN_DUMMY06,
RTL_REG_CVLAN_DUMMY07,
RTL_REG_CVLAN_DUMMY08,
RTL_REG_CVLAN_DUMMY09,
RTL_REG_CVLAN_DUMMY10,
RTL_REG_CVLAN_DUMMY11,
RTL_REG_CVLAN_DUMMY12,
RTL_REG_CVLAN_DUMMY13,
RTL_REG_CVLAN_DUMMY14,
RTL_REG_CVLAN_DUMMY15,
RTL_REG_RMA_CTRL00,
RTL_REG_RMA_CTRL01,
RTL_REG_RMA_CTRL02,
RTL_REG_RMA_CTRL03,
RTL_REG_RMA_CTRL04,
RTL_REG_RMA_CTRL08,
RTL_REG_RMA_CTRL0D,
RTL_REG_RMA_CTRL0E,
RTL_REG_RMA_CTRL10,
RTL_REG_RMA_CTRL11,
RTL_REG_RMA_CTRL12,
RTL_REG_RMA_CTRL13,
RTL_REG_RMA_CTRL18,
RTL_REG_RMA_CTRL1A,
RTL_REG_RMA_CTRL20,
RTL_REG_RMA_CTRL21,
RTL_REG_RMA_CTRL22,
RTL_REG_RMA_CTRL_CDP,
RTL_REG_RMA_CTRL_CSSTP,
RTL_REG_RMA_CTRL_LLDP,
RTL_REG_RMA_LLDP_EN,
RTL_REG_VLAN_PORTBASED_PRIORITY_CTRL0,
RTL_REG_VLAN_PORTBASED_PRIORITY_CTRL1,
RTL_REG_VLAN_PORTBASED_PRIORITY_CTRL2,
RTL_REG_VLAN_PPB_PRIORITY_ITEM0_CTRL0,
RTL_REG_VLAN_PPB_PRIORITY_ITEM0_CTRL1,
RTL_REG_VLAN_PPB_PRIORITY_ITEM0_CTRL2,
RTL_REG_VLAN_PPB_PRIORITY_ITEM1_CTRL0,
RTL_REG_VLAN_PPB_PRIORITY_ITEM1_CTRL1,
RTL_REG_VLAN_PPB_PRIORITY_ITEM1_CTRL2,
RTL_REG_VLAN_PPB_PRIORITY_ITEM2_CTRL0,
RTL_REG_VLAN_PPB_PRIORITY_ITEM2_CTRL1,
RTL_REG_VLAN_PPB_PRIORITY_ITEM2_CTRL2,
RTL_REG_VLAN_PPB_PRIORITY_ITEM3_CTRL0,
RTL_REG_VLAN_PPB_PRIORITY_ITEM3_CTRL1,
RTL_REG_VLAN_PPB_PRIORITY_ITEM3_CTRL2,
RTL_REG_QOS_1Q_PRIORITY_REMAPPING_CTRL0,
RTL_REG_QOS_1Q_PRIORITY_REMAPPING_CTRL1,
RTL_REG_QOS_DSCP_TO_PRIORITY_CTRL0,
RTL_REG_QOS_DSCP_TO_PRIORITY_CTRL1,
RTL_REG_QOS_DSCP_TO_PRIORITY_CTRL2,
RTL_REG_QOS_DSCP_TO_PRIORITY_CTRL3,
RTL_REG_QOS_DSCP_TO_PRIORITY_CTRL4,
RTL_REG_QOS_DSCP_TO_PRIORITY_CTRL5,
RTL_REG_QOS_DSCP_TO_PRIORITY_CTRL6,
RTL_REG_QOS_DSCP_TO_PRIORITY_CTRL7,
RTL_REG_QOS_DSCP_TO_PRIORITY_CTRL8,
RTL_REG_QOS_DSCP_TO_PRIORITY_CTRL9,
RTL_REG_QOS_DSCP_TO_PRIORITY_CTRL10,
RTL_REG_QOS_DSCP_TO_PRIORITY_CTRL11,
RTL_REG_QOS_DSCP_TO_PRIORITY_CTRL12,
RTL_REG_QOS_DSCP_TO_PRIORITY_CTRL13,
RTL_REG_QOS_DSCP_TO_PRIORITY_CTRL14,
RTL_REG_QOS_DSCP_TO_PRIORITY_CTRL15,
RTL_REG_QOS_PORTBASED_PRIORITY_CTRL0,
RTL_REG_QOS_PORTBASED_PRIORITY_CTRL1,
RTL_REG_DUMMY0879,
RTL_REG_QOS_PORTBASED_PRIORITY_CTRL2,
RTL_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL0,
RTL_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL1,
RTL_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL2,
RTL_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL3,
RTL_REG_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0,
RTL_REG_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1,
RTL_REG_QOS_TRAP_PRIORITY0,
RTL_REG_QOS_TRAP_PRIORITY1,
RTL_REG_MAX_LENGTH_CFG,
RTL_REG_MAX_LEN_RX_TX,
RTL_REG_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0,
RTL_REG_QOS_INTERNAL_PRIORITY_DECISION2_CTRL1,
RTL_REG_QOS_INTERNAL_PRIORITY_DECISION2_CTRL2,
RTL_REG_QOS_INTERNAL_PRIORITY_DECISION2_CTRL3,
RTL_REG_QOS_INTERNAL_PRIORITY_DECISION_IDX,
RTL_REG_MAX_LENGTH_CFG_EXT,
RTL_REG_MAX_LEN_RX_TX_CFG0,
RTL_REG_MAX_LEN_RX_TX_CFG1,
RTL_REG_UNDA_FLOODING_PMSK,
RTL_REG_UNMCAST_FLOADING_PMSK,
RTL_REG_BCAST_FLOADING_PMSK,
RTL_REG_PORT_TRUNK_HASH_MAPPING_CTRL2,
RTL_REG_PORT_TRUNK_HASH_MAPPING_CTRL3,
RTL_REG_PORT_ISOLATION_PORT0_MASK,
RTL_REG_PORT_ISOLATION_PORT1_MASK,
RTL_REG_PORT_ISOLATION_PORT2_MASK,
RTL_REG_PORT_ISOLATION_PORT3_MASK,
RTL_REG_PORT_ISOLATION_PORT4_MASK,
RTL_REG_PORT_ISOLATION_PORT5_MASK,
RTL_REG_PORT_ISOLATION_PORT6_MASK,
RTL_REG_PORT_ISOLATION_PORT7_MASK,
RTL_REG_PORT_ISOLATION_PORT8_MASK,
RTL_REG_PORT_ISOLATION_PORT9_MASK,
RTL_REG_PORT_ISOLATION_PORT10_MASK,
RTL_REG_FORCE_CTRL,
RTL_REG_FORCE_PORT0_MASK,
RTL_REG_FORCE_PORT1_MASK,
RTL_REG_FORCE_PORT2_MASK,
RTL_REG_FORCE_PORT3_MASK,
RTL_REG_FORCE_PORT4_MASK,
RTL_REG_FORCE_PORT5_MASK,
RTL_REG_FORCE_PORT6_MASK,
RTL_REG_FORCE_PORT7_MASK,
RTL_REG_FORCE_PORT8_MASK,
RTL_REG_FORCE_PORT9_MASK,
RTL_REG_FORCE_PORT10_MASK,
RTL_REG_SOURCE_PORT_PERMIT,
RTL_REG_IPMCAST_VLAN_LEAKY,
RTL_REG_IPMCAST_PORTISO_LEAKY,
RTL_REG_PORT_SECURITY_CTRL,
RTL_REG_UNKNOWN_IPV4_MULTICAST_CTRL0,
RTL_REG_UNKNOWN_IPV4_MULTICAST_CTRL1,
RTL_REG_UNKNOWN_IPV6_MULTICAST_CTRL0,
RTL_REG_UNKNOWN_IPV6_MULTICAST_CTRL1,
RTL_REG_UNKNOWN_L2_MULTICAST_CTRL0,
RTL_REG_PORT_TRUNK_DROP_CTRL,
RTL_REG_PORT_TRUNK_CTRL,
RTL_REG_PORT_TRUNK_GROUP_MASK,
RTL_REG_PORT_TRUNK_FLOWCTRL,
RTL_REG_PORT_TRUNK_HASH_MAPPING_CTRL0,
RTL_REG_PORT_TRUNK_HASH_MAPPING_CTRL1,
RTL_REG_DOS_CFG,
RTL_REG_UNKNOWN_L2_MULTICAST_CTRL1,
RTL_REG_VLAN_EGRESS_KEEP_CTRL4,
RTL_REG_VLAN_EGRESS_KEEP_CTRL5,
RTL_REG_VLAN_EGRESS_KEEP_CTRL0_EXT,
RTL_REG_VLAN_EGRESS_KEEP_CTRL1_EXT,
RTL_REG_VLAN_EGRESS_KEEP_CTRL2_EXT,
RTL_REG_VLAN_EGRESS_KEEP_CTRL3_EXT,
RTL_REG_VLAN_EGRESS_KEEP_CTRL4_EXT,
RTL_REG_VLAN_EGRESS_KEEP_CTRL5_EXT,
RTL_REG_VLAN_EGRESS_TRANS_CTRL10,
RTL_REG_FPGA_VER_CEN,
RTL_REG_FPGA_TIME_CEN,
RTL_REG_FPGA_DATE_CEN,
RTL_REG_QOS_PORT_QUEUE_NUMBER_CTRL0,
RTL_REG_QOS_PORT_QUEUE_NUMBER_CTRL1,
RTL_REG_QOS_PORT_QUEUE_NUMBER_CTRL2,
RTL_REG_QOS_1Q_PRIORITY_TO_QID_CTRL0,
RTL_REG_QOS_1Q_PRIORITY_TO_QID_CTRL1,
RTL_REG_QOS_2Q_PRIORITY_TO_QID_CTRL0,
RTL_REG_QOS_2Q_PRIORITY_TO_QID_CTRL1,
RTL_REG_QOS_3Q_PRIORITY_TO_QID_CTRL0,
RTL_REG_QOS_3Q_PRIORITY_TO_QID_CTRL1,
RTL_REG_QOS_4Q_PRIORITY_TO_QID_CTRL0,
RTL_REG_QOS_4Q_PRIORITY_TO_QID_CTRL1,
RTL_REG_QOS_5Q_PRIORITY_TO_QID_CTRL0,
RTL_REG_QOS_5Q_PRIORITY_TO_QID_CTRL1,
RTL_REG_QOS_6Q_PRIORITY_TO_QID_CTRL0,
RTL_REG_QOS_6Q_PRIORITY_TO_QID_CTRL1,
RTL_REG_QOS_7Q_PRIORITY_TO_QID_CTRL0,
RTL_REG_QOS_7Q_PRIORITY_TO_QID_CTRL1,
RTL_REG_QOS_8Q_PRIORITY_TO_QID_CTRL0,
RTL_REG_QOS_8Q_PRIORITY_TO_QID_CTRL1,
RTL_REG_HIGHPRI_INDICATOR,
RTL_REG_HIGHPRI_CFG,
RTL_REG_PORT_DEBUG_INFO_CTRL0,
RTL_REG_PORT_DEBUG_INFO_CTRL1,
RTL_REG_PORT_DEBUG_INFO_CTRL2,
RTL_REG_PORT_DEBUG_INFO_CTRL3,
RTL_REG_PORT_DEBUG_INFO_CTRL4,
RTL_REG_PORT_DEBUG_INFO_CTRL5,
RTL_REG_PORT_DEBUG_INFO_CTRL6,
RTL_REG_PORT_DEBUG_INFO_CTRL7,
RTL_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL0,
RTL_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL1,
RTL_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL2,
RTL_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL3,
RTL_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL4,
RTL_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL5,
RTL_REG_FLOWCRTL_EGRESS_PORT_ENABLE,
RTL_REG_EAV_CTRL,
RTL_REG_UNTAG_DSCP_PRI_CFG,
RTL_REG_VLAN_EGRESS_KEEP_CTRL0,
RTL_REG_VLAN_EGRESS_KEEP_CTRL1,
RTL_REG_VLAN_EGRESS_KEEP_CTRL2,
RTL_REG_VLAN_EGRESS_KEEP_CTRL3,
RTL_REG_VLAN_TRANSPARENT_EN_CFG,
RTL_REG_IPMC_GROUP_ENTRY0_H,
RTL_REG_IPMC_GROUP_ENTRY0_L,
RTL_REG_IPMC_GROUP_ENTRY1_H,
RTL_REG_IPMC_GROUP_ENTRY1_L,
RTL_REG_IPMC_GROUP_ENTRY2_H,
RTL_REG_IPMC_GROUP_ENTRY2_L,
RTL_REG_IPMC_GROUP_ENTRY3_H,
RTL_REG_IPMC_GROUP_ENTRY3_L,
RTL_REG_IPMC_GROUP_ENTRY4_H,
RTL_REG_IPMC_GROUP_ENTRY4_L,
RTL_REG_IPMC_GROUP_ENTRY5_H,
RTL_REG_IPMC_GROUP_ENTRY5_L,
RTL_REG_IPMC_GROUP_ENTRY6_H,
RTL_REG_IPMC_GROUP_ENTRY6_L,
RTL_REG_IPMC_GROUP_ENTRY7_H,
RTL_REG_IPMC_GROUP_ENTRY7_L,
RTL_REG_IPMC_GROUP_ENTRY8_H,
RTL_REG_IPMC_GROUP_ENTRY8_L,
RTL_REG_IPMC_GROUP_ENTRY9_H,
RTL_REG_IPMC_GROUP_ENTRY9_L,
RTL_REG_IPMC_GROUP_ENTRY10_H,
RTL_REG_IPMC_GROUP_ENTRY10_L,
RTL_REG_IPMC_GROUP_ENTRY11_H,
RTL_REG_IPMC_GROUP_ENTRY11_L,
RTL_REG_IPMC_GROUP_ENTRY12_H,
RTL_REG_IPMC_GROUP_ENTRY12_L,
RTL_REG_IPMC_GROUP_ENTRY13_H,
RTL_REG_IPMC_GROUP_ENTRY13_L,
RTL_REG_IPMC_GROUP_ENTRY14_H,
RTL_REG_IPMC_GROUP_ENTRY14_L,
RTL_REG_IPMC_GROUP_ENTRY15_H,
RTL_REG_IPMC_GROUP_ENTRY15_L,
RTL_REG_IPMC_GROUP_ENTRY16_H,
RTL_REG_IPMC_GROUP_ENTRY16_L,
RTL_REG_IPMC_GROUP_ENTRY17_H,
RTL_REG_IPMC_GROUP_ENTRY17_L,
RTL_REG_IPMC_GROUP_ENTRY18_H,
RTL_REG_IPMC_GROUP_ENTRY18_L,
RTL_REG_IPMC_GROUP_ENTRY19_H,
RTL_REG_IPMC_GROUP_ENTRY19_L,
RTL_REG_IPMC_GROUP_ENTRY20_H,
RTL_REG_IPMC_GROUP_ENTRY20_L,
RTL_REG_IPMC_GROUP_ENTRY21_H,
RTL_REG_IPMC_GROUP_ENTRY21_L,
RTL_REG_IPMC_GROUP_ENTRY22_H,
RTL_REG_IPMC_GROUP_ENTRY22_L,
RTL_REG_IPMC_GROUP_ENTRY23_H,
RTL_REG_IPMC_GROUP_ENTRY23_L,
RTL_REG_IPMC_GROUP_ENTRY24_H,
RTL_REG_IPMC_GROUP_ENTRY24_L,
RTL_REG_IPMC_GROUP_ENTRY25_H,
RTL_REG_IPMC_GROUP_ENTRY25_L,
RTL_REG_IPMC_GROUP_ENTRY26_H,
RTL_REG_IPMC_GROUP_ENTRY26_L,
RTL_REG_IPMC_GROUP_ENTRY27_H,
RTL_REG_IPMC_GROUP_ENTRY27_L,
RTL_REG_IPMC_GROUP_ENTRY28_H,
RTL_REG_IPMC_GROUP_ENTRY28_L,
RTL_REG_IPMC_GROUP_ENTRY29_H,
RTL_REG_IPMC_GROUP_ENTRY29_L,
RTL_REG_IPMC_GROUP_ENTRY30_H,
RTL_REG_IPMC_GROUP_ENTRY30_L,
RTL_REG_IPMC_GROUP_ENTRY31_H,
RTL_REG_IPMC_GROUP_ENTRY31_L,
RTL_REG_IPMC_GROUP_ENTRY32_H,
RTL_REG_IPMC_GROUP_ENTRY32_L,
RTL_REG_IPMC_GROUP_ENTRY33_H,
RTL_REG_IPMC_GROUP_ENTRY33_L,
RTL_REG_IPMC_GROUP_ENTRY34_H,
RTL_REG_IPMC_GROUP_ENTRY34_L,
RTL_REG_IPMC_GROUP_ENTRY35_H,
RTL_REG_IPMC_GROUP_ENTRY35_L,
RTL_REG_IPMC_GROUP_ENTRY36_H,
RTL_REG_IPMC_GROUP_ENTRY36_L,
RTL_REG_IPMC_GROUP_ENTRY37_H,
RTL_REG_IPMC_GROUP_ENTRY37_L,
RTL_REG_IPMC_GROUP_ENTRY38_H,
RTL_REG_IPMC_GROUP_ENTRY38_L,
RTL_REG_IPMC_GROUP_ENTRY39_H,
RTL_REG_IPMC_GROUP_ENTRY39_L,
RTL_REG_IPMC_GROUP_ENTRY40_H,
RTL_REG_IPMC_GROUP_ENTRY40_L,
RTL_REG_IPMC_GROUP_ENTRY41_H,
RTL_REG_IPMC_GROUP_ENTRY41_L,
RTL_REG_IPMC_GROUP_ENTRY42_H,
RTL_REG_IPMC_GROUP_ENTRY42_L,
RTL_REG_IPMC_GROUP_ENTRY43_H,
RTL_REG_IPMC_GROUP_ENTRY43_L,
RTL_REG_IPMC_GROUP_ENTRY44_H,
RTL_REG_IPMC_GROUP_ENTRY44_L,
RTL_REG_IPMC_GROUP_ENTRY45_H,
RTL_REG_IPMC_GROUP_ENTRY45_L,
RTL_REG_IPMC_GROUP_ENTRY46_H,
RTL_REG_IPMC_GROUP_ENTRY46_L,
RTL_REG_IPMC_GROUP_ENTRY47_H,
RTL_REG_IPMC_GROUP_ENTRY47_L,
RTL_REG_IPMC_GROUP_ENTRY48_H,
RTL_REG_IPMC_GROUP_ENTRY48_L,
RTL_REG_IPMC_GROUP_ENTRY49_H,
RTL_REG_IPMC_GROUP_ENTRY49_L,
RTL_REG_IPMC_GROUP_ENTRY50_H,
RTL_REG_IPMC_GROUP_ENTRY50_L,
RTL_REG_IPMC_GROUP_ENTRY51_H,
RTL_REG_IPMC_GROUP_ENTRY51_L,
RTL_REG_IPMC_GROUP_ENTRY52_H,
RTL_REG_IPMC_GROUP_ENTRY52_L,
RTL_REG_IPMC_GROUP_ENTRY53_H,
RTL_REG_IPMC_GROUP_ENTRY53_L,
RTL_REG_IPMC_GROUP_ENTRY54_H,
RTL_REG_IPMC_GROUP_ENTRY54_L,
RTL_REG_IPMC_GROUP_ENTRY55_H,
RTL_REG_IPMC_GROUP_ENTRY55_L,
RTL_REG_IPMC_GROUP_ENTRY56_H,
RTL_REG_IPMC_GROUP_ENTRY56_L,
RTL_REG_IPMC_GROUP_ENTRY57_H,
RTL_REG_IPMC_GROUP_ENTRY57_L,
RTL_REG_IPMC_GROUP_ENTRY58_H,
RTL_REG_IPMC_GROUP_ENTRY58_L,
RTL_REG_IPMC_GROUP_ENTRY59_H,
RTL_REG_IPMC_GROUP_ENTRY59_L,
RTL_REG_IPMC_GROUP_ENTRY60_H,
RTL_REG_IPMC_GROUP_ENTRY60_L,
RTL_REG_IPMC_GROUP_ENTRY61_H,
RTL_REG_IPMC_GROUP_ENTRY61_L,
RTL_REG_IPMC_GROUP_ENTRY62_H,
RTL_REG_IPMC_GROUP_ENTRY62_L,
RTL_REG_IPMC_GROUP_ENTRY63_H,
RTL_REG_IPMC_GROUP_ENTRY63_L,
RTL_REG_UNKNOWN_UNICAST_DA_PORT_BEHAVE,
RTL_REG_MIRROR_CTRL3,
RTL_REG_DPM_DUMMY02,
RTL_REG_DPM_DUMMY03,
RTL_REG_DPM_DUMMY04,
RTL_REG_DPM_DUMMY05,
RTL_REG_DPM_DUMMY06,
RTL_REG_DPM_DUMMY07,
RTL_REG_DPM_DUMMY08,
RTL_REG_DPM_DUMMY09,
RTL_REG_DPM_DUMMY10,
RTL_REG_DPM_DUMMY11,
RTL_REG_DPM_DUMMY12,
RTL_REG_DPM_DUMMY13,
RTL_REG_DPM_DUMMY14,
RTL_REG_DPM_DUMMY15,
RTL_REG_VLAN_EGRESS_TRANS_CTRL0,
RTL_REG_VLAN_EGRESS_TRANS_CTRL1,
RTL_REG_VLAN_EGRESS_TRANS_CTRL2,
RTL_REG_VLAN_EGRESS_TRANS_CTRL3,
RTL_REG_VLAN_EGRESS_TRANS_CTRL4,
RTL_REG_VLAN_EGRESS_TRANS_CTRL5,
RTL_REG_VLAN_EGRESS_TRANS_CTRL6,
RTL_REG_VLAN_EGRESS_TRANS_CTRL7,
RTL_REG_VLAN_EGRESS_TRANS_CTRL8,
RTL_REG_VLAN_EGRESS_TRANS_CTRL9,
RTL_REG_MIRROR_CTRL2,
RTL_REG_OUTPUT_DROP_CFG,
RTL_REG_UNKNOWN_UNICAST_DA_PORT_BEHAVE_EXT,
RTL_REG_RMK_CFG_SEL_CTRL,
RTL_REG_QOS_DSCP_REMARK_DSCP_CTRL0,
RTL_REG_QOS_DSCP_REMARK_DSCP_CTRL1,
RTL_REG_QOS_DSCP_REMARK_DSCP_CTRL2,
RTL_REG_QOS_DSCP_REMARK_DSCP_CTRL3,
RTL_REG_QOS_DSCP_REMARK_DSCP_CTRL4,
RTL_REG_QOS_DSCP_REMARK_DSCP_CTRL5,
RTL_REG_QOS_DSCP_REMARK_DSCP_CTRL6,
RTL_REG_QOS_DSCP_REMARK_DSCP_CTRL7,
RTL_REG_QOS_DSCP_REMARK_DSCP_CTRL8,
RTL_REG_QOS_DSCP_REMARK_DSCP_CTRL9,
RTL_REG_QOS_DSCP_REMARK_DSCP_CTRL10,
RTL_REG_QOS_DSCP_REMARK_DSCP_CTRL11,
RTL_REG_QOS_DSCP_REMARK_DSCP_CTRL12,
RTL_REG_QOS_DSCP_REMARK_DSCP_CTRL13,
RTL_REG_QOS_DSCP_REMARK_DSCP_CTRL14,
RTL_REG_QOS_DSCP_REMARK_DSCP_CTRL15,
RTL_REG_QOS_DSCP_REMARK_DSCP_CTRL16,
RTL_REG_QOS_DSCP_REMARK_DSCP_CTRL17,
RTL_REG_QOS_DSCP_REMARK_DSCP_CTRL18,
RTL_REG_QOS_DSCP_REMARK_DSCP_CTRL19,
RTL_REG_QOS_DSCP_REMARK_DSCP_CTRL20,
RTL_REG_QOS_DSCP_REMARK_DSCP_CTRL21,
RTL_REG_QOS_DSCP_REMARK_DSCP_CTRL22,
RTL_REG_QOS_DSCP_REMARK_DSCP_CTRL23,
RTL_REG_QOS_DSCP_REMARK_DSCP_CTRL24,
RTL_REG_QOS_DSCP_REMARK_DSCP_CTRL25,
RTL_REG_QOS_DSCP_REMARK_DSCP_CTRL26,
RTL_REG_QOS_DSCP_REMARK_DSCP_CTRL27,
RTL_REG_QOS_DSCP_REMARK_DSCP_CTRL28,
RTL_REG_QOS_DSCP_REMARK_DSCP_CTRL29,
RTL_REG_QOS_DSCP_REMARK_DSCP_CTRL30,
RTL_REG_QOS_DSCP_REMARK_DSCP_CTRL31,
RTL_REG_VLAN_MSTI0_CTRL0,
RTL_REG_VLAN_MSTI0_CTRL1,
RTL_REG_VLAN_MSTI1_CTRL0,
RTL_REG_VLAN_MSTI1_CTRL1,
RTL_REG_VLAN_MSTI2_CTRL0,
RTL_REG_VLAN_MSTI2_CTRL1,
RTL_REG_VLAN_MSTI3_CTRL0,
RTL_REG_VLAN_MSTI3_CTRL1,
RTL_REG_VLAN_MSTI4_CTRL0,
RTL_REG_VLAN_MSTI4_CTRL1,
RTL_REG_VLAN_MSTI5_CTRL0,
RTL_REG_VLAN_MSTI5_CTRL1,
RTL_REG_VLAN_MSTI6_CTRL0,
RTL_REG_VLAN_MSTI6_CTRL1,
RTL_REG_VLAN_MSTI7_CTRL0,
RTL_REG_VLAN_MSTI7_CTRL1,
RTL_REG_VLAN_MSTI8_CTRL0,
RTL_REG_VLAN_MSTI8_CTRL1,
RTL_REG_VLAN_MSTI9_CTRL0,
RTL_REG_VLAN_MSTI9_CTRL1,
RTL_REG_VLAN_MSTI10_CTRL0,
RTL_REG_VLAN_MSTI10_CTRL1,
RTL_REG_VLAN_MSTI11_CTRL0,
RTL_REG_VLAN_MSTI11_CTRL1,
RTL_REG_VLAN_MSTI12_CTRL0,
RTL_REG_VLAN_MSTI12_CTRL1,
RTL_REG_VLAN_MSTI13_CTRL0,
RTL_REG_VLAN_MSTI13_CTRL1,
RTL_REG_VLAN_MSTI14_CTRL0,
RTL_REG_VLAN_MSTI14_CTRL1,
RTL_REG_VLAN_MSTI15_CTRL0,
RTL_REG_VLAN_MSTI15_CTRL1,
RTL_REG_LUT_PORT0_LEARN_LIMITNO,
RTL_REG_LUT_PORT1_LEARN_LIMITNO,
RTL_REG_LUT_PORT2_LEARN_LIMITNO,
RTL_REG_LUT_PORT3_LEARN_LIMITNO,
RTL_REG_LUT_PORT4_LEARN_LIMITNO,
RTL_REG_LUT_PORT5_LEARN_LIMITNO,
RTL_REG_LUT_PORT6_LEARN_LIMITNO,
RTL_REG_LUT_PORT7_LEARN_LIMITNO,
RTL_REG_LUT_SYS_LEARN_LIMITNO,
RTL_REG_LUT_LRN_SYS_LMT_CTRL,
RTL_REG_LUT_PORT8_LEARN_LIMITNO,
RTL_REG_LUT_PORT9_LEARN_LIMITNO,
RTL_REG_LUT_PORT10_LEARN_LIMITNO,
RTL_REG_LUT_CFG,
RTL_REG_LUT_AGEOUT_CTRL,
RTL_REG_PORT_EFID_CTRL0,
RTL_REG_PORT_EFID_CTRL1,
RTL_REG_PORT_EFID_CTRL2,
RTL_REG_FORCE_FLUSH1,
RTL_REG_FORCE_FLUSH,
RTL_REG_L2_FLUSH_CTRL1,
RTL_REG_L2_FLUSH_CTRL2,
RTL_REG_L2_FLUSH_CTRL3,
RTL_REG_LUT_CFG2,
RTL_REG_FLUSH_STATUS,
RTL_REG_STORM_BCAST,
RTL_REG_STORM_MCAST,
RTL_REG_STORM_UNKOWN_UCAST,
RTL_REG_STORM_UNKOWN_MCAST,
RTL_REG_STORM_BCAST_METER_CTRL0,
RTL_REG_STORM_BCAST_METER_CTRL1,
RTL_REG_STORM_BCAST_METER_CTRL2,
RTL_REG_STORM_BCAST_METER_CTRL3,
RTL_REG_STORM_BCAST_METER_CTRL4,
RTL_REG_STORM_BCAST_METER_CTRL5,
RTL_REG_STORM_MCAST_METER_CTRL0,
RTL_REG_STORM_MCAST_METER_CTRL1,
RTL_REG_STORM_MCAST_METER_CTRL2,
RTL_REG_STORM_MCAST_METER_CTRL3,
RTL_REG_STORM_MCAST_METER_CTRL4,
RTL_REG_STORM_MCAST_METER_CTRL5,
RTL_REG_STORM_UNDA_METER_CTRL0,
RTL_REG_STORM_UNDA_METER_CTRL1,
RTL_REG_STORM_UNDA_METER_CTRL2,
RTL_REG_STORM_UNDA_METER_CTRL3,
RTL_REG_STORM_UNDA_METER_CTRL4,
RTL_REG_STORM_UNDA_METER_CTRL5,
RTL_REG_STORM_UNMC_METER_CTRL0,
RTL_REG_STORM_UNMC_METER_CTRL1,
RTL_REG_STORM_UNMC_METER_CTRL2,
RTL_REG_STORM_UNMC_METER_CTRL3,
RTL_REG_STORM_EXT_CFG,
RTL_REG_STORM_EXT_MTRIDX_CFG0,
RTL_REG_STORM_EXT_MTRIDX_CFG1,
RTL_REG_STORM_UNMC_METER_CTRL4,
RTL_REG_STORM_UNMC_METER_CTRL5,
RTL_REG_OAM_PARSER_CTRL0,
RTL_REG_OAM_PARSER_CTRL1,
RTL_REG_OAM_MULTIPLEXER_CTRL0,
RTL_REG_OAM_MULTIPLEXER_CTRL1,
RTL_REG_OAM_CTRL,
RTL_REG_DOT1X_PORT_ENABLE,
RTL_REG_DOT1X_MAC_ENABLE,
RTL_REG_DOT1X_PORT_AUTH,
RTL_REG_DOT1X_PORT_OPDIR,
RTL_REG_DOT1X_UNAUTH_ACT_W0,
RTL_REG_DOT1X_UNAUTH_ACT_W1,
RTL_REG_DOT1X_CFG,
RTL_REG_L2_LRN_CNT_CTRL0,
RTL_REG_L2_LRN_CNT_CTRL1,
RTL_REG_L2_LRN_CNT_CTRL2,
RTL_REG_L2_LRN_CNT_CTRL3,
RTL_REG_L2_LRN_CNT_CTRL4,
RTL_REG_L2_LRN_CNT_CTRL5,
RTL_REG_L2_LRN_CNT_CTRL6,
RTL_REG_L2_LRN_CNT_CTRL7,
RTL_REG_L2_LRN_CNT_CTRL8,
RTL_REG_L2_LRN_CNT_CTRL9,
RTL_REG_L2_LRN_CNT_CTRL10,
RTL_REG_LUT_LRN_UNDER_STATUS,
RTL_REG_L2_SA_MOVING_FORBID,
RTL_REG_DRPORT_LEARN_CTRL,
RTL_REG_L2_DUMMY02,
RTL_REG_L2_DUMMY03,
RTL_REG_L2_DUMMY04,
RTL_REG_L2_DUMMY05,
RTL_REG_L2_DUMMY06,
RTL_REG_L2_DUMMY07,
RTL_REG_IPMC_GROUP_PMSK_00,
RTL_REG_IPMC_GROUP_PMSK_01,
RTL_REG_IPMC_GROUP_PMSK_02,
RTL_REG_IPMC_GROUP_PMSK_03,
RTL_REG_IPMC_GROUP_PMSK_04,
RTL_REG_IPMC_GROUP_PMSK_05,
RTL_REG_IPMC_GROUP_PMSK_06,
RTL_REG_IPMC_GROUP_PMSK_07,
RTL_REG_IPMC_GROUP_PMSK_08,
RTL_REG_IPMC_GROUP_PMSK_09,
RTL_REG_IPMC_GROUP_PMSK_10,
RTL_REG_IPMC_GROUP_PMSK_11,
RTL_REG_IPMC_GROUP_PMSK_12,
RTL_REG_IPMC_GROUP_PMSK_13,
RTL_REG_IPMC_GROUP_PMSK_14,
RTL_REG_IPMC_GROUP_PMSK_15,
RTL_REG_IPMC_GROUP_PMSK_16,
RTL_REG_IPMC_GROUP_PMSK_17,
RTL_REG_IPMC_GROUP_PMSK_18,
RTL_REG_IPMC_GROUP_PMSK_19,
RTL_REG_IPMC_GROUP_PMSK_20,
RTL_REG_IPMC_GROUP_PMSK_21,
RTL_REG_IPMC_GROUP_PMSK_22,
RTL_REG_IPMC_GROUP_PMSK_23,
RTL_REG_IPMC_GROUP_PMSK_24,
RTL_REG_IPMC_GROUP_PMSK_25,
RTL_REG_IPMC_GROUP_PMSK_26,
RTL_REG_IPMC_GROUP_PMSK_27,
RTL_REG_IPMC_GROUP_PMSK_28,
RTL_REG_IPMC_GROUP_PMSK_29,
RTL_REG_IPMC_GROUP_PMSK_30,
RTL_REG_IPMC_GROUP_PMSK_31,
RTL_REG_IPMC_GROUP_PMSK_32,
RTL_REG_IPMC_GROUP_PMSK_33,
RTL_REG_IPMC_GROUP_PMSK_34,
RTL_REG_IPMC_GROUP_PMSK_35,
RTL_REG_IPMC_GROUP_PMSK_36,
RTL_REG_IPMC_GROUP_PMSK_37,
RTL_REG_IPMC_GROUP_PMSK_38,
RTL_REG_IPMC_GROUP_PMSK_39,
RTL_REG_IPMC_GROUP_PMSK_40,
RTL_REG_IPMC_GROUP_PMSK_41,
RTL_REG_IPMC_GROUP_PMSK_42,
RTL_REG_IPMC_GROUP_PMSK_43,
RTL_REG_IPMC_GROUP_PMSK_44,
RTL_REG_IPMC_GROUP_PMSK_45,
RTL_REG_IPMC_GROUP_PMSK_46,
RTL_REG_IPMC_GROUP_PMSK_47,
RTL_REG_IPMC_GROUP_PMSK_48,
RTL_REG_IPMC_GROUP_PMSK_49,
RTL_REG_IPMC_GROUP_PMSK_50,
RTL_REG_IPMC_GROUP_PMSK_51,
RTL_REG_IPMC_GROUP_PMSK_52,
RTL_REG_IPMC_GROUP_PMSK_53,
RTL_REG_IPMC_GROUP_PMSK_54,
RTL_REG_IPMC_GROUP_PMSK_55,
RTL_REG_IPMC_GROUP_PMSK_56,
RTL_REG_IPMC_GROUP_PMSK_57,
RTL_REG_IPMC_GROUP_PMSK_58,
RTL_REG_IPMC_GROUP_PMSK_59,
RTL_REG_IPMC_GROUP_PMSK_60,
RTL_REG_IPMC_GROUP_PMSK_61,
RTL_REG_IPMC_GROUP_PMSK_62,
RTL_REG_IPMC_GROUP_PMSK_63,
RTL_REG_SVLAN_MCAST2S_ENTRY0_CTRL0,
RTL_REG_SVLAN_MCAST2S_ENTRY0_CTRL1,
RTL_REG_SVLAN_MCAST2S_ENTRY0_CTRL2,
RTL_REG_SVLAN_MCAST2S_ENTRY0_CTRL3,
RTL_REG_SVLAN_MCAST2S_ENTRY0_CTRL4,
RTL_REG_SVLAN_MCAST2S_ENTRY1_CTRL0,
RTL_REG_SVLAN_MCAST2S_ENTRY1_CTRL1,
RTL_REG_SVLAN_MCAST2S_ENTRY1_CTRL2,
RTL_REG_SVLAN_MCAST2S_ENTRY1_CTRL3,
RTL_REG_SVLAN_MCAST2S_ENTRY1_CTRL4,
RTL_REG_SVLAN_MCAST2S_ENTRY2_CTRL0,
RTL_REG_SVLAN_MCAST2S_ENTRY2_CTRL1,
RTL_REG_SVLAN_MCAST2S_ENTRY2_CTRL2,
RTL_REG_SVLAN_MCAST2S_ENTRY2_CTRL3,
RTL_REG_SVLAN_MCAST2S_ENTRY2_CTRL4,
RTL_REG_SVLAN_MCAST2S_ENTRY3_CTRL0,
RTL_REG_SVLAN_MCAST2S_ENTRY3_CTRL1,
RTL_REG_SVLAN_MCAST2S_ENTRY3_CTRL2,
RTL_REG_SVLAN_MCAST2S_ENTRY3_CTRL3,
RTL_REG_SVLAN_MCAST2S_ENTRY3_CTRL4,
RTL_REG_SVLAN_MCAST2S_ENTRY4_CTRL0,
RTL_REG_SVLAN_MCAST2S_ENTRY4_CTRL1,
RTL_REG_SVLAN_MCAST2S_ENTRY4_CTRL2,
RTL_REG_SVLAN_MCAST2S_ENTRY4_CTRL3,
RTL_REG_SVLAN_MCAST2S_ENTRY4_CTRL4,
RTL_REG_SVLAN_MCAST2S_ENTRY5_CTRL0,
RTL_REG_SVLAN_MCAST2S_ENTRY5_CTRL1,
RTL_REG_SVLAN_MCAST2S_ENTRY5_CTRL2,
RTL_REG_SVLAN_MCAST2S_ENTRY5_CTRL3,
RTL_REG_SVLAN_MCAST2S_ENTRY5_CTRL4,
RTL_REG_SVLAN_MCAST2S_ENTRY6_CTRL0,
RTL_REG_SVLAN_MCAST2S_ENTRY6_CTRL1,
RTL_REG_SVLAN_MCAST2S_ENTRY6_CTRL2,
RTL_REG_SVLAN_MCAST2S_ENTRY6_CTRL3,
RTL_REG_SVLAN_MCAST2S_ENTRY6_CTRL4,
RTL_REG_SVLAN_MCAST2S_ENTRY7_CTRL0,
RTL_REG_SVLAN_MCAST2S_ENTRY7_CTRL1,
RTL_REG_SVLAN_MCAST2S_ENTRY7_CTRL2,
RTL_REG_SVLAN_MCAST2S_ENTRY7_CTRL3,
RTL_REG_SVLAN_MCAST2S_ENTRY7_CTRL4,
RTL_REG_SVLAN_MCAST2S_ENTRY8_CTRL0,
RTL_REG_SVLAN_MCAST2S_ENTRY8_CTRL1,
RTL_REG_SVLAN_MCAST2S_ENTRY8_CTRL2,
RTL_REG_SVLAN_MCAST2S_ENTRY8_CTRL3,
RTL_REG_SVLAN_MCAST2S_ENTRY8_CTRL4,
RTL_REG_SVLAN_MCAST2S_ENTRY9_CTRL0,
RTL_REG_SVLAN_MCAST2S_ENTRY9_CTRL1,
RTL_REG_SVLAN_MCAST2S_ENTRY9_CTRL2,
RTL_REG_SVLAN_MCAST2S_ENTRY9_CTRL3,
RTL_REG_SVLAN_MCAST2S_ENTRY9_CTRL4,
RTL_REG_SVLAN_MCAST2S_ENTRY10_CTRL0,
RTL_REG_SVLAN_MCAST2S_ENTRY10_CTRL1,
RTL_REG_SVLAN_MCAST2S_ENTRY10_CTRL2,
RTL_REG_SVLAN_MCAST2S_ENTRY10_CTRL3,
RTL_REG_SVLAN_MCAST2S_ENTRY10_CTRL4,
RTL_REG_SVLAN_MCAST2S_ENTRY11_CTRL0,
RTL_REG_SVLAN_MCAST2S_ENTRY11_CTRL1,
RTL_REG_SVLAN_MCAST2S_ENTRY11_CTRL2,
RTL_REG_SVLAN_MCAST2S_ENTRY11_CTRL3,
RTL_REG_SVLAN_MCAST2S_ENTRY11_CTRL4,
RTL_REG_SVLAN_MCAST2S_ENTRY12_CTRL0,
RTL_REG_SVLAN_MCAST2S_ENTRY12_CTRL1,
RTL_REG_SVLAN_MCAST2S_ENTRY12_CTRL2,
RTL_REG_SVLAN_MCAST2S_ENTRY12_CTRL3,
RTL_REG_SVLAN_MCAST2S_ENTRY12_CTRL4,
RTL_REG_SVLAN_MCAST2S_ENTRY13_CTRL0,
RTL_REG_SVLAN_MCAST2S_ENTRY13_CTRL1,
RTL_REG_SVLAN_MCAST2S_ENTRY13_CTRL2,
RTL_REG_SVLAN_MCAST2S_ENTRY13_CTRL3,
RTL_REG_SVLAN_MCAST2S_ENTRY13_CTRL4,
RTL_REG_SVLAN_MCAST2S_ENTRY14_CTRL0,
RTL_REG_SVLAN_MCAST2S_ENTRY14_CTRL1,
RTL_REG_SVLAN_MCAST2S_ENTRY14_CTRL2,
RTL_REG_SVLAN_MCAST2S_ENTRY14_CTRL3,
RTL_REG_SVLAN_MCAST2S_ENTRY14_CTRL4,
RTL_REG_SVLAN_MCAST2S_ENTRY15_CTRL0,
RTL_REG_SVLAN_MCAST2S_ENTRY15_CTRL1,
RTL_REG_SVLAN_MCAST2S_ENTRY15_CTRL2,
RTL_REG_SVLAN_MCAST2S_ENTRY15_CTRL3,
RTL_REG_SVLAN_MCAST2S_ENTRY15_CTRL4,
RTL_REG_SVLAN_MCAST2S_ENTRY16_CTRL0,
RTL_REG_SVLAN_MCAST2S_ENTRY16_CTRL1,
RTL_REG_SVLAN_MCAST2S_ENTRY16_CTRL2,
RTL_REG_SVLAN_MCAST2S_ENTRY16_CTRL3,
RTL_REG_SVLAN_MCAST2S_ENTRY16_CTRL4,
RTL_REG_SVLAN_MCAST2S_ENTRY17_CTRL0,
RTL_REG_SVLAN_MCAST2S_ENTRY17_CTRL1,
RTL_REG_SVLAN_MCAST2S_ENTRY17_CTRL2,
RTL_REG_SVLAN_MCAST2S_ENTRY17_CTRL3,
RTL_REG_SVLAN_MCAST2S_ENTRY17_CTRL4,
RTL_REG_SVLAN_MCAST2S_ENTRY18_CTRL0,
RTL_REG_SVLAN_MCAST2S_ENTRY18_CTRL1,
RTL_REG_SVLAN_MCAST2S_ENTRY18_CTRL2,
RTL_REG_SVLAN_MCAST2S_ENTRY18_CTRL3,
RTL_REG_SVLAN_MCAST2S_ENTRY18_CTRL4,
RTL_REG_SVLAN_MCAST2S_ENTRY19_CTRL0,
RTL_REG_SVLAN_MCAST2S_ENTRY19_CTRL1,
RTL_REG_SVLAN_MCAST2S_ENTRY19_CTRL2,
RTL_REG_SVLAN_MCAST2S_ENTRY19_CTRL3,
RTL_REG_SVLAN_MCAST2S_ENTRY19_CTRL4,
RTL_REG_SVLAN_MCAST2S_ENTRY20_CTRL0,
RTL_REG_SVLAN_MCAST2S_ENTRY20_CTRL1,
RTL_REG_SVLAN_MCAST2S_ENTRY20_CTRL2,
RTL_REG_SVLAN_MCAST2S_ENTRY20_CTRL3,
RTL_REG_SVLAN_MCAST2S_ENTRY20_CTRL4,
RTL_REG_SVLAN_MCAST2S_ENTRY21_CTRL0,
RTL_REG_SVLAN_MCAST2S_ENTRY21_CTRL1,
RTL_REG_SVLAN_MCAST2S_ENTRY21_CTRL2,
RTL_REG_SVLAN_MCAST2S_ENTRY21_CTRL3,
RTL_REG_SVLAN_MCAST2S_ENTRY21_CTRL4,
RTL_REG_SVLAN_MCAST2S_ENTRY22_CTRL0,
RTL_REG_SVLAN_MCAST2S_ENTRY22_CTRL1,
RTL_REG_SVLAN_MCAST2S_ENTRY22_CTRL2,
RTL_REG_SVLAN_MCAST2S_ENTRY22_CTRL3,
RTL_REG_SVLAN_MCAST2S_ENTRY22_CTRL4,
RTL_REG_SVLAN_MCAST2S_ENTRY23_CTRL0,
RTL_REG_SVLAN_MCAST2S_ENTRY23_CTRL1,
RTL_REG_SVLAN_MCAST2S_ENTRY23_CTRL2,
RTL_REG_SVLAN_MCAST2S_ENTRY23_CTRL3,
RTL_REG_SVLAN_MCAST2S_ENTRY23_CTRL4,
RTL_REG_SVLAN_MCAST2S_ENTRY24_CTRL0,
RTL_REG_SVLAN_MCAST2S_ENTRY24_CTRL1,
RTL_REG_SVLAN_MCAST2S_ENTRY24_CTRL2,
RTL_REG_SVLAN_MCAST2S_ENTRY24_CTRL3,
RTL_REG_SVLAN_MCAST2S_ENTRY24_CTRL4,
RTL_REG_SVLAN_MCAST2S_ENTRY25_CTRL0,
RTL_REG_SVLAN_MCAST2S_ENTRY25_CTRL1,
RTL_REG_SVLAN_MCAST2S_ENTRY25_CTRL2,
RTL_REG_SVLAN_MCAST2S_ENTRY25_CTRL3,
RTL_REG_SVLAN_MCAST2S_ENTRY25_CTRL4,
RTL_REG_SVLAN_MCAST2S_ENTRY26_CTRL0,
RTL_REG_SVLAN_MCAST2S_ENTRY26_CTRL1,
RTL_REG_SVLAN_MCAST2S_ENTRY26_CTRL2,
RTL_REG_SVLAN_MCAST2S_ENTRY26_CTRL3,
RTL_REG_SVLAN_MCAST2S_ENTRY26_CTRL4,
RTL_REG_SVLAN_MCAST2S_ENTRY27_CTRL0,
RTL_REG_SVLAN_MCAST2S_ENTRY27_CTRL1,
RTL_REG_SVLAN_MCAST2S_ENTRY27_CTRL2,
RTL_REG_SVLAN_MCAST2S_ENTRY27_CTRL3,
RTL_REG_SVLAN_MCAST2S_ENTRY27_CTRL4,
RTL_REG_SVLAN_MCAST2S_ENTRY28_CTRL0,
RTL_REG_SVLAN_MCAST2S_ENTRY28_CTRL1,
RTL_REG_SVLAN_MCAST2S_ENTRY28_CTRL2,
RTL_REG_SVLAN_MCAST2S_ENTRY28_CTRL3,
RTL_REG_SVLAN_MCAST2S_ENTRY28_CTRL4,
RTL_REG_SVLAN_MCAST2S_ENTRY29_CTRL0,
RTL_REG_SVLAN_MCAST2S_ENTRY29_CTRL1,
RTL_REG_SVLAN_MCAST2S_ENTRY29_CTRL2,
RTL_REG_SVLAN_MCAST2S_ENTRY29_CTRL3,
RTL_REG_SVLAN_MCAST2S_ENTRY29_CTRL4,
RTL_REG_SVLAN_MCAST2S_ENTRY30_CTRL0,
RTL_REG_SVLAN_MCAST2S_ENTRY30_CTRL1,
RTL_REG_SVLAN_MCAST2S_ENTRY30_CTRL2,
RTL_REG_SVLAN_MCAST2S_ENTRY30_CTRL3,
RTL_REG_SVLAN_MCAST2S_ENTRY30_CTRL4,
RTL_REG_SVLAN_MCAST2S_ENTRY31_CTRL0,
RTL_REG_SVLAN_MCAST2S_ENTRY31_CTRL1,
RTL_REG_SVLAN_MCAST2S_ENTRY31_CTRL2,
RTL_REG_SVLAN_MCAST2S_ENTRY31_CTRL3,
RTL_REG_SVLAN_MCAST2S_ENTRY31_CTRL4,
RTL_REG_MLTVLAN_DUMMY_0,
RTL_REG_MLTVLAN_DUMMY_1,
RTL_REG_MLTVLAN_DUMMY_2,
RTL_REG_MLTVLAN_DUMMY_3,
RTL_REG_MLTVLAN_DUMMY_4,
RTL_REG_MLTVLAN_DUMMY_5,
RTL_REG_MLTVLAN_DUMMY_6,
RTL_REG_MLTVLAN_DUMMY_7,
RTL_REG_SVLAN_MEMBERCFG0_CTRL1,
RTL_REG_SVLAN_MEMBERCFG0_CTRL2,
RTL_REG_SVLAN_MEMBERCFG0_CTRL3,
RTL_REG_SVLAN_MEMBERCFG1_CTRL1,
RTL_REG_SVLAN_MEMBERCFG1_CTRL2,
RTL_REG_SVLAN_MEMBERCFG1_CTRL3,
RTL_REG_SVLAN_MEMBERCFG2_CTRL1,
RTL_REG_SVLAN_MEMBERCFG2_CTRL2,
RTL_REG_SVLAN_MEMBERCFG2_CTRL3,
RTL_REG_SVLAN_MEMBERCFG3_CTRL1,
RTL_REG_SVLAN_MEMBERCFG3_CTRL2,
RTL_REG_SVLAN_MEMBERCFG3_CTRL3,
RTL_REG_SVLAN_MEMBERCFG4_CTRL1,
RTL_REG_SVLAN_MEMBERCFG4_CTRL2,
RTL_REG_SVLAN_MEMBERCFG4_CTRL3,
RTL_REG_SVLAN_MEMBERCFG5_CTRL1,
RTL_REG_SVLAN_MEMBERCFG5_CTRL2,
RTL_REG_SVLAN_MEMBERCFG5_CTRL3,
RTL_REG_SVLAN_MEMBERCFG6_CTRL1,
RTL_REG_SVLAN_MEMBERCFG6_CTRL2,
RTL_REG_SVLAN_MEMBERCFG6_CTRL3,
RTL_REG_SVLAN_MEMBERCFG7_CTRL1,
RTL_REG_SVLAN_MEMBERCFG7_CTRL2,
RTL_REG_SVLAN_MEMBERCFG7_CTRL3,
RTL_REG_SVLAN_MEMBERCFG8_CTRL1,
RTL_REG_SVLAN_MEMBERCFG8_CTRL2,
RTL_REG_SVLAN_MEMBERCFG8_CTRL3,
RTL_REG_SVLAN_MEMBERCFG9_CTRL1,
RTL_REG_SVLAN_MEMBERCFG9_CTRL2,
RTL_REG_SVLAN_MEMBERCFG9_CTRL3,
RTL_REG_SVLAN_MEMBERCFG10_CTRL1,
RTL_REG_SVLAN_MEMBERCFG10_CTRL2,
RTL_REG_SVLAN_MEMBERCFG10_CTRL3,
RTL_REG_SVLAN_MEMBERCFG11_CTRL1,
RTL_REG_SVLAN_MEMBERCFG11_CTRL2,
RTL_REG_SVLAN_MEMBERCFG11_CTRL3,
RTL_REG_SVLAN_MEMBERCFG12_CTRL1,
RTL_REG_SVLAN_MEMBERCFG12_CTRL2,
RTL_REG_SVLAN_MEMBERCFG12_CTRL3,
RTL_REG_SVLAN_MEMBERCFG13_CTRL1,
RTL_REG_SVLAN_MEMBERCFG13_CTRL2,
RTL_REG_SVLAN_MEMBERCFG13_CTRL3,
RTL_REG_SVLAN_MEMBERCFG14_CTRL1,
RTL_REG_SVLAN_MEMBERCFG14_CTRL2,
RTL_REG_SVLAN_MEMBERCFG14_CTRL3,
RTL_REG_SVLAN_MEMBERCFG15_CTRL1,
RTL_REG_SVLAN_MEMBERCFG15_CTRL2,
RTL_REG_SVLAN_MEMBERCFG15_CTRL3,
RTL_REG_SVLAN_MEMBERCFG16_CTRL1,
RTL_REG_SVLAN_MEMBERCFG16_CTRL2,
RTL_REG_SVLAN_MEMBERCFG16_CTRL3,
RTL_REG_SVLAN_MEMBERCFG17_CTRL1,
RTL_REG_SVLAN_MEMBERCFG17_CTRL2,
RTL_REG_SVLAN_MEMBERCFG17_CTRL3,
RTL_REG_SVLAN_MEMBERCFG18_CTRL1,
RTL_REG_SVLAN_MEMBERCFG18_CTRL2,
RTL_REG_SVLAN_MEMBERCFG18_CTRL3,
RTL_REG_SVLAN_MEMBERCFG19_CTRL1,
RTL_REG_SVLAN_MEMBERCFG19_CTRL2,
RTL_REG_SVLAN_MEMBERCFG19_CTRL3,
RTL_REG_SVLAN_MEMBERCFG20_CTRL1,
RTL_REG_SVLAN_MEMBERCFG20_CTRL2,
RTL_REG_SVLAN_MEMBERCFG20_CTRL3,
RTL_REG_SVLAN_MEMBERCFG21_CTRL1,
RTL_REG_SVLAN_MEMBERCFG21_CTRL2,
RTL_REG_SVLAN_MEMBERCFG21_CTRL3,
RTL_REG_SVLAN_MEMBERCFG22_CTRL1,
RTL_REG_SVLAN_MEMBERCFG22_CTRL2,
RTL_REG_SVLAN_MEMBERCFG22_CTRL3,
RTL_REG_SVLAN_MEMBERCFG23_CTRL1,
RTL_REG_SVLAN_MEMBERCFG23_CTRL2,
RTL_REG_SVLAN_MEMBERCFG23_CTRL3,
RTL_REG_SVLAN_MEMBERCFG24_CTRL1,
RTL_REG_SVLAN_MEMBERCFG24_CTRL2,
RTL_REG_SVLAN_MEMBERCFG24_CTRL3,
RTL_REG_SVLAN_MEMBERCFG25_CTRL1,
RTL_REG_SVLAN_MEMBERCFG25_CTRL2,
RTL_REG_SVLAN_MEMBERCFG25_CTRL3,
RTL_REG_SVLAN_MEMBERCFG26_CTRL1,
RTL_REG_SVLAN_MEMBERCFG26_CTRL2,
RTL_REG_SVLAN_MEMBERCFG26_CTRL3,
RTL_REG_SVLAN_MEMBERCFG27_CTRL1,
RTL_REG_SVLAN_MEMBERCFG27_CTRL2,
RTL_REG_SVLAN_MEMBERCFG27_CTRL3,
RTL_REG_SVLAN_MEMBERCFG28_CTRL1,
RTL_REG_SVLAN_MEMBERCFG28_CTRL2,
RTL_REG_SVLAN_MEMBERCFG28_CTRL3,
RTL_REG_SVLAN_MEMBERCFG29_CTRL1,
RTL_REG_SVLAN_MEMBERCFG29_CTRL2,
RTL_REG_SVLAN_MEMBERCFG29_CTRL3,
RTL_REG_SVLAN_MEMBERCFG30_CTRL1,
RTL_REG_SVLAN_MEMBERCFG30_CTRL2,
RTL_REG_SVLAN_MEMBERCFG30_CTRL3,
RTL_REG_SVLAN_MEMBERCFG31_CTRL1,
RTL_REG_SVLAN_MEMBERCFG31_CTRL2,
RTL_REG_SVLAN_MEMBERCFG31_CTRL3,
RTL_REG_SVLAN_MEMBERCFG32_CTRL1,
RTL_REG_SVLAN_MEMBERCFG32_CTRL2,
RTL_REG_SVLAN_MEMBERCFG32_CTRL3,
RTL_REG_SVLAN_MEMBERCFG33_CTRL1,
RTL_REG_SVLAN_MEMBERCFG33_CTRL2,
RTL_REG_SVLAN_MEMBERCFG33_CTRL3,
RTL_REG_SVLAN_MEMBERCFG34_CTRL1,
RTL_REG_SVLAN_MEMBERCFG34_CTRL2,
RTL_REG_SVLAN_MEMBERCFG34_CTRL3,
RTL_REG_SVLAN_MEMBERCFG35_CTRL1,
RTL_REG_SVLAN_MEMBERCFG35_CTRL2,
RTL_REG_SVLAN_MEMBERCFG35_CTRL3,
RTL_REG_SVLAN_MEMBERCFG36_CTRL1,
RTL_REG_SVLAN_MEMBERCFG36_CTRL2,
RTL_REG_SVLAN_MEMBERCFG36_CTRL3,
RTL_REG_SVLAN_MEMBERCFG37_CTRL1,
RTL_REG_SVLAN_MEMBERCFG37_CTRL2,
RTL_REG_SVLAN_MEMBERCFG37_CTRL3,
RTL_REG_SVLAN_MEMBERCFG38_CTRL1,
RTL_REG_SVLAN_MEMBERCFG38_CTRL2,
RTL_REG_SVLAN_MEMBERCFG38_CTRL3,
RTL_REG_SVLAN_MEMBERCFG39_CTRL1,
RTL_REG_SVLAN_MEMBERCFG39_CTRL2,
RTL_REG_SVLAN_MEMBERCFG39_CTRL3,
RTL_REG_SVLAN_MEMBERCFG40_CTRL1,
RTL_REG_SVLAN_MEMBERCFG40_CTRL2,
RTL_REG_SVLAN_MEMBERCFG40_CTRL3,
RTL_REG_SVLAN_MEMBERCFG41_CTRL1,
RTL_REG_SVLAN_MEMBERCFG41_CTRL2,
RTL_REG_SVLAN_MEMBERCFG41_CTRL3,
RTL_REG_SVLAN_MEMBERCFG42_CTRL1,
RTL_REG_SVLAN_MEMBERCFG42_CTRL2,
RTL_REG_SVLAN_MEMBERCFG42_CTRL3,
RTL_REG_SVLAN_MEMBERCFG43_CTRL1,
RTL_REG_SVLAN_MEMBERCFG43_CTRL2,
RTL_REG_SVLAN_MEMBERCFG43_CTRL3,
RTL_REG_SVLAN_MEMBERCFG44_CTRL1,
RTL_REG_SVLAN_MEMBERCFG44_CTRL2,
RTL_REG_SVLAN_MEMBERCFG44_CTRL3,
RTL_REG_SVLAN_MEMBERCFG45_CTRL1,
RTL_REG_SVLAN_MEMBERCFG45_CTRL2,
RTL_REG_SVLAN_MEMBERCFG45_CTRL3,
RTL_REG_SVLAN_MEMBERCFG46_CTRL1,
RTL_REG_SVLAN_MEMBERCFG46_CTRL2,
RTL_REG_SVLAN_MEMBERCFG46_CTRL3,
RTL_REG_SVLAN_MEMBERCFG47_CTRL1,
RTL_REG_SVLAN_MEMBERCFG47_CTRL2,
RTL_REG_SVLAN_MEMBERCFG47_CTRL3,
RTL_REG_SVLAN_MEMBERCFG48_CTRL1,
RTL_REG_SVLAN_MEMBERCFG48_CTRL2,
RTL_REG_SVLAN_MEMBERCFG48_CTRL3,
RTL_REG_SVLAN_MEMBERCFG49_CTRL1,
RTL_REG_SVLAN_MEMBERCFG49_CTRL2,
RTL_REG_SVLAN_MEMBERCFG49_CTRL3,
RTL_REG_SVLAN_MEMBERCFG50_CTRL1,
RTL_REG_SVLAN_MEMBERCFG50_CTRL2,
RTL_REG_SVLAN_MEMBERCFG50_CTRL3,
RTL_REG_SVLAN_MEMBERCFG51_CTRL1,
RTL_REG_SVLAN_MEMBERCFG51_CTRL2,
RTL_REG_SVLAN_MEMBERCFG51_CTRL3,
RTL_REG_SVLAN_MEMBERCFG52_CTRL1,
RTL_REG_SVLAN_MEMBERCFG52_CTRL2,
RTL_REG_SVLAN_MEMBERCFG52_CTRL3,
RTL_REG_SVLAN_MEMBERCFG53_CTRL1,
RTL_REG_SVLAN_MEMBERCFG53_CTRL2,
RTL_REG_SVLAN_MEMBERCFG53_CTRL3,
RTL_REG_SVLAN_MEMBERCFG54_CTRL1,
RTL_REG_SVLAN_MEMBERCFG54_CTRL2,
RTL_REG_SVLAN_MEMBERCFG54_CTRL3,
RTL_REG_SVLAN_MEMBERCFG55_CTRL1,
RTL_REG_SVLAN_MEMBERCFG55_CTRL2,
RTL_REG_SVLAN_MEMBERCFG55_CTRL3,
RTL_REG_SVLAN_MEMBERCFG56_CTRL1,
RTL_REG_SVLAN_MEMBERCFG56_CTRL2,
RTL_REG_SVLAN_MEMBERCFG56_CTRL3,
RTL_REG_SVLAN_MEMBERCFG57_CTRL1,
RTL_REG_SVLAN_MEMBERCFG57_CTRL2,
RTL_REG_SVLAN_MEMBERCFG57_CTRL3,
RTL_REG_SVLAN_MEMBERCFG58_CTRL1,
RTL_REG_SVLAN_MEMBERCFG58_CTRL2,
RTL_REG_SVLAN_MEMBERCFG58_CTRL3,
RTL_REG_SVLAN_MEMBERCFG59_CTRL1,
RTL_REG_SVLAN_MEMBERCFG59_CTRL2,
RTL_REG_SVLAN_MEMBERCFG59_CTRL3,
RTL_REG_SVLAN_MEMBERCFG60_CTRL1,
RTL_REG_SVLAN_MEMBERCFG60_CTRL2,
RTL_REG_SVLAN_MEMBERCFG60_CTRL3,
RTL_REG_SVLAN_MEMBERCFG61_CTRL1,
RTL_REG_SVLAN_MEMBERCFG61_CTRL2,
RTL_REG_SVLAN_MEMBERCFG61_CTRL3,
RTL_REG_SVLAN_MEMBERCFG62_CTRL1,
RTL_REG_SVLAN_MEMBERCFG62_CTRL2,
RTL_REG_SVLAN_MEMBERCFG62_CTRL3,
RTL_REG_SVLAN_MEMBERCFG63_CTRL1,
RTL_REG_SVLAN_MEMBERCFG63_CTRL2,
RTL_REG_SVLAN_MEMBERCFG63_CTRL3,
RTL_REG_SVLAN_MEMBERCFG0_CTRL4,
RTL_REG_SVLAN_MEMBERCFG1_CTRL4,
RTL_REG_SVLAN_MEMBERCFG2_CTRL4,
RTL_REG_SVLAN_MEMBERCFG3_CTRL4,
RTL_REG_SVLAN_MEMBERCFG4_CTRL4,
RTL_REG_SVLAN_MEMBERCFG5_CTRL4,
RTL_REG_SVLAN_MEMBERCFG6_CTRL4,
RTL_REG_SVLAN_MEMBERCFG7_CTRL4,
RTL_REG_SVLAN_MEMBERCFG8_CTRL4,
RTL_REG_SVLAN_MEMBERCFG9_CTRL4,
RTL_REG_SVLAN_MEMBERCFG10_CTRL4,
RTL_REG_SVLAN_MEMBERCFG11_CTRL4,
RTL_REG_SVLAN_MEMBERCFG12_CTRL4,
RTL_REG_SVLAN_MEMBERCFG13_CTRL4,
RTL_REG_SVLAN_MEMBERCFG14_CTRL4,
RTL_REG_SVLAN_MEMBERCFG15_CTRL4,
RTL_REG_SVLAN_MEMBERCFG16_CTRL4,
RTL_REG_SVLAN_MEMBERCFG17_CTRL4,
RTL_REG_SVLAN_MEMBERCFG18_CTRL4,
RTL_REG_SVLAN_MEMBERCFG19_CTRL4,
RTL_REG_SVLAN_MEMBERCFG20_CTRL4,
RTL_REG_SVLAN_MEMBERCFG21_CTRL4,
RTL_REG_SVLAN_MEMBERCFG22_CTRL4,
RTL_REG_SVLAN_MEMBERCFG23_CTRL4,
RTL_REG_SVLAN_MEMBERCFG24_CTRL4,
RTL_REG_SVLAN_MEMBERCFG25_CTRL4,
RTL_REG_SVLAN_MEMBERCFG26_CTRL4,
RTL_REG_SVLAN_MEMBERCFG27_CTRL4,
RTL_REG_SVLAN_MEMBERCFG28_CTRL4,
RTL_REG_SVLAN_MEMBERCFG29_CTRL4,
RTL_REG_SVLAN_MEMBERCFG30_CTRL4,
RTL_REG_SVLAN_MEMBERCFG31_CTRL4,
RTL_REG_SVLAN_MEMBERCFG32_CTRL4,
RTL_REG_SVLAN_MEMBERCFG33_CTRL4,
RTL_REG_SVLAN_MEMBERCFG34_CTRL4,
RTL_REG_SVLAN_MEMBERCFG35_CTRL4,
RTL_REG_SVLAN_MEMBERCFG36_CTRL4,
RTL_REG_SVLAN_MEMBERCFG37_CTRL4,
RTL_REG_SVLAN_MEMBERCFG38_CTRL4,
RTL_REG_SVLAN_MEMBERCFG39_CTRL4,
RTL_REG_SVLAN_MEMBERCFG40_CTRL4,
RTL_REG_SVLAN_MEMBERCFG41_CTRL4,
RTL_REG_SVLAN_MEMBERCFG42_CTRL4,
RTL_REG_SVLAN_MEMBERCFG43_CTRL4,
RTL_REG_SVLAN_MEMBERCFG44_CTRL4,
RTL_REG_SVLAN_MEMBERCFG45_CTRL4,
RTL_REG_SVLAN_MEMBERCFG46_CTRL4,
RTL_REG_SVLAN_MEMBERCFG47_CTRL4,
RTL_REG_SVLAN_MEMBERCFG48_CTRL4,
RTL_REG_SVLAN_MEMBERCFG49_CTRL4,
RTL_REG_SVLAN_MEMBERCFG50_CTRL4,
RTL_REG_SVLAN_MEMBERCFG51_CTRL4,
RTL_REG_SVLAN_MEMBERCFG52_CTRL4,
RTL_REG_SVLAN_MEMBERCFG53_CTRL4,
RTL_REG_SVLAN_MEMBERCFG54_CTRL4,
RTL_REG_SVLAN_MEMBERCFG55_CTRL4,
RTL_REG_SVLAN_MEMBERCFG56_CTRL4,
RTL_REG_SVLAN_MEMBERCFG57_CTRL4,
RTL_REG_SVLAN_MEMBERCFG58_CTRL4,
RTL_REG_SVLAN_MEMBERCFG59_CTRL4,
RTL_REG_SVLAN_MEMBERCFG60_CTRL4,
RTL_REG_SVLAN_MEMBERCFG61_CTRL4,
RTL_REG_SVLAN_MEMBERCFG62_CTRL4,
RTL_REG_SVLAN_C2SCFG0_CTRL0,
RTL_REG_SVLAN_C2SCFG0_CTRL1,
RTL_REG_SVLAN_C2SCFG0_CTRL2,
RTL_REG_SVLAN_C2SCFG1_CTRL0,
RTL_REG_SVLAN_C2SCFG1_CTRL1,
RTL_REG_SVLAN_C2SCFG1_CTRL2,
RTL_REG_SVLAN_C2SCFG2_CTRL0,
RTL_REG_SVLAN_C2SCFG2_CTRL1,
RTL_REG_SVLAN_C2SCFG2_CTRL2,
RTL_REG_SVLAN_C2SCFG3_CTRL0,
RTL_REG_SVLAN_C2SCFG3_CTRL1,
RTL_REG_SVLAN_C2SCFG3_CTRL2,
RTL_REG_SVLAN_C2SCFG4_CTRL0,
RTL_REG_SVLAN_C2SCFG4_CTRL1,
RTL_REG_SVLAN_C2SCFG4_CTRL2,
RTL_REG_SVLAN_C2SCFG5_CTRL0,
RTL_REG_SVLAN_C2SCFG5_CTRL1,
RTL_REG_SVLAN_C2SCFG5_CTRL2,
RTL_REG_SVLAN_C2SCFG6_CTRL0,
RTL_REG_SVLAN_C2SCFG6_CTRL1,
RTL_REG_SVLAN_C2SCFG6_CTRL2,
RTL_REG_SVLAN_C2SCFG7_CTRL0,
RTL_REG_SVLAN_C2SCFG7_CTRL1,
RTL_REG_SVLAN_C2SCFG7_CTRL2,
RTL_REG_SVLAN_C2SCFG8_CTRL0,
RTL_REG_SVLAN_C2SCFG8_CTRL1,
RTL_REG_SVLAN_C2SCFG8_CTRL2,
RTL_REG_SVLAN_C2SCFG9_CTRL0,
RTL_REG_SVLAN_C2SCFG9_CTRL1,
RTL_REG_SVLAN_C2SCFG9_CTRL2,
RTL_REG_SVLAN_C2SCFG10_CTRL0,
RTL_REG_SVLAN_C2SCFG10_CTRL1,
RTL_REG_SVLAN_C2SCFG10_CTRL2,
RTL_REG_SVLAN_C2SCFG11_CTRL0,
RTL_REG_SVLAN_C2SCFG11_CTRL1,
RTL_REG_SVLAN_C2SCFG11_CTRL2,
RTL_REG_SVLAN_C2SCFG12_CTRL0,
RTL_REG_SVLAN_C2SCFG12_CTRL1,
RTL_REG_SVLAN_C2SCFG12_CTRL2,
RTL_REG_SVLAN_C2SCFG13_CTRL0,
RTL_REG_SVLAN_C2SCFG13_CTRL1,
RTL_REG_SVLAN_C2SCFG13_CTRL2,
RTL_REG_SVLAN_C2SCFG14_CTRL0,
RTL_REG_SVLAN_C2SCFG14_CTRL1,
RTL_REG_SVLAN_C2SCFG14_CTRL2,
RTL_REG_SVLAN_C2SCFG15_CTRL0,
RTL_REG_SVLAN_C2SCFG15_CTRL1,
RTL_REG_SVLAN_C2SCFG15_CTRL2,
RTL_REG_SVLAN_C2SCFG16_CTRL0,
RTL_REG_SVLAN_C2SCFG16_CTRL1,
RTL_REG_SVLAN_C2SCFG16_CTRL2,
RTL_REG_SVLAN_C2SCFG17_CTRL0,
RTL_REG_SVLAN_C2SCFG17_CTRL1,
RTL_REG_SVLAN_C2SCFG17_CTRL2,
RTL_REG_SVLAN_C2SCFG18_CTRL0,
RTL_REG_SVLAN_C2SCFG18_CTRL1,
RTL_REG_SVLAN_C2SCFG18_CTRL2,
RTL_REG_SVLAN_C2SCFG19_CTRL0,
RTL_REG_SVLAN_C2SCFG19_CTRL1,
RTL_REG_SVLAN_C2SCFG19_CTRL2,
RTL_REG_SVLAN_C2SCFG20_CTRL0,
RTL_REG_SVLAN_C2SCFG20_CTRL1,
RTL_REG_SVLAN_C2SCFG20_CTRL2,
RTL_REG_SVLAN_C2SCFG21_CTRL0,
RTL_REG_SVLAN_C2SCFG21_CTRL1,
RTL_REG_SVLAN_C2SCFG21_CTRL2,
RTL_REG_SVLAN_C2SCFG22_CTRL0,
RTL_REG_SVLAN_C2SCFG22_CTRL1,
RTL_REG_SVLAN_C2SCFG22_CTRL2,
RTL_REG_SVLAN_C2SCFG23_CTRL0,
RTL_REG_SVLAN_C2SCFG23_CTRL1,
RTL_REG_SVLAN_C2SCFG23_CTRL2,
RTL_REG_SVLAN_C2SCFG24_CTRL0,
RTL_REG_SVLAN_C2SCFG24_CTRL1,
RTL_REG_SVLAN_C2SCFG24_CTRL2,
RTL_REG_SVLAN_C2SCFG25_CTRL0,
RTL_REG_SVLAN_C2SCFG25_CTRL1,
RTL_REG_SVLAN_C2SCFG25_CTRL2,
RTL_REG_SVLAN_C2SCFG26_CTRL0,
RTL_REG_SVLAN_C2SCFG26_CTRL1,
RTL_REG_SVLAN_C2SCFG26_CTRL2,
RTL_REG_SVLAN_C2SCFG27_CTRL0,
RTL_REG_SVLAN_C2SCFG27_CTRL1,
RTL_REG_SVLAN_C2SCFG27_CTRL2,
RTL_REG_SVLAN_C2SCFG28_CTRL0,
RTL_REG_SVLAN_C2SCFG28_CTRL1,
RTL_REG_SVLAN_C2SCFG28_CTRL2,
RTL_REG_SVLAN_C2SCFG29_CTRL0,
RTL_REG_SVLAN_C2SCFG29_CTRL1,
RTL_REG_SVLAN_C2SCFG29_CTRL2,
RTL_REG_SVLAN_C2SCFG30_CTRL0,
RTL_REG_SVLAN_C2SCFG30_CTRL1,
RTL_REG_SVLAN_C2SCFG30_CTRL2,
RTL_REG_SVLAN_C2SCFG31_CTRL0,
RTL_REG_SVLAN_C2SCFG31_CTRL1,
RTL_REG_SVLAN_C2SCFG31_CTRL2,
RTL_REG_SVLAN_C2SCFG32_CTRL0,
RTL_REG_SVLAN_C2SCFG32_CTRL1,
RTL_REG_SVLAN_C2SCFG32_CTRL2,
RTL_REG_SVLAN_C2SCFG33_CTRL0,
RTL_REG_SVLAN_C2SCFG33_CTRL1,
RTL_REG_SVLAN_C2SCFG33_CTRL2,
RTL_REG_SVLAN_C2SCFG34_CTRL0,
RTL_REG_SVLAN_C2SCFG34_CTRL1,
RTL_REG_SVLAN_C2SCFG34_CTRL2,
RTL_REG_SVLAN_C2SCFG35_CTRL0,
RTL_REG_SVLAN_C2SCFG35_CTRL1,
RTL_REG_SVLAN_C2SCFG35_CTRL2,
RTL_REG_SVLAN_C2SCFG36_CTRL0,
RTL_REG_SVLAN_C2SCFG36_CTRL1,
RTL_REG_SVLAN_C2SCFG36_CTRL2,
RTL_REG_SVLAN_C2SCFG37_CTRL0,
RTL_REG_SVLAN_C2SCFG37_CTRL1,
RTL_REG_SVLAN_C2SCFG37_CTRL2,
RTL_REG_SVLAN_C2SCFG38_CTRL0,
RTL_REG_SVLAN_C2SCFG38_CTRL1,
RTL_REG_SVLAN_C2SCFG38_CTRL2,
RTL_REG_SVLAN_C2SCFG39_CTRL0,
RTL_REG_SVLAN_C2SCFG39_CTRL1,
RTL_REG_SVLAN_C2SCFG39_CTRL2,
RTL_REG_SVLAN_C2SCFG40_CTRL0,
RTL_REG_SVLAN_C2SCFG40_CTRL1,
RTL_REG_SVLAN_C2SCFG40_CTRL2,
RTL_REG_SVLAN_C2SCFG41_CTRL0,
RTL_REG_SVLAN_C2SCFG41_CTRL1,
RTL_REG_SVLAN_C2SCFG41_CTRL2,
RTL_REG_SVLAN_C2SCFG42_CTRL0,
RTL_REG_SVLAN_C2SCFG42_CTRL1,
RTL_REG_SVLAN_C2SCFG42_CTRL2,
RTL_REG_SVLAN_C2SCFG43_CTRL0,
RTL_REG_SVLAN_C2SCFG43_CTRL1,
RTL_REG_SVLAN_C2SCFG43_CTRL2,
RTL_REG_SVLAN_C2SCFG44_CTRL0,
RTL_REG_SVLAN_C2SCFG44_CTRL1,
RTL_REG_SVLAN_C2SCFG44_CTRL2,
RTL_REG_SVLAN_C2SCFG45_CTRL0,
RTL_REG_SVLAN_C2SCFG45_CTRL1,
RTL_REG_SVLAN_C2SCFG45_CTRL2,
RTL_REG_SVLAN_C2SCFG46_CTRL0,
RTL_REG_SVLAN_C2SCFG46_CTRL1,
RTL_REG_SVLAN_C2SCFG46_CTRL2,
RTL_REG_SVLAN_C2SCFG47_CTRL0,
RTL_REG_SVLAN_C2SCFG47_CTRL1,
RTL_REG_SVLAN_C2SCFG47_CTRL2,
RTL_REG_SVLAN_C2SCFG48_CTRL0,
RTL_REG_SVLAN_C2SCFG48_CTRL1,
RTL_REG_SVLAN_C2SCFG48_CTRL2,
RTL_REG_SVLAN_C2SCFG49_CTRL0,
RTL_REG_SVLAN_C2SCFG49_CTRL1,
RTL_REG_SVLAN_C2SCFG49_CTRL2,
RTL_REG_SVLAN_C2SCFG50_CTRL0,
RTL_REG_SVLAN_C2SCFG50_CTRL1,
RTL_REG_SVLAN_C2SCFG50_CTRL2,
RTL_REG_SVLAN_C2SCFG51_CTRL0,
RTL_REG_SVLAN_C2SCFG51_CTRL1,
RTL_REG_SVLAN_C2SCFG51_CTRL2,
RTL_REG_SVLAN_C2SCFG52_CTRL0,
RTL_REG_SVLAN_C2SCFG52_CTRL1,
RTL_REG_SVLAN_C2SCFG52_CTRL2,
RTL_REG_SVLAN_C2SCFG53_CTRL0,
RTL_REG_SVLAN_C2SCFG53_CTRL1,
RTL_REG_SVLAN_C2SCFG53_CTRL2,
RTL_REG_SVLAN_C2SCFG54_CTRL0,
RTL_REG_SVLAN_C2SCFG54_CTRL1,
RTL_REG_SVLAN_C2SCFG54_CTRL2,
RTL_REG_SVLAN_C2SCFG55_CTRL0,
RTL_REG_SVLAN_C2SCFG55_CTRL1,
RTL_REG_SVLAN_C2SCFG55_CTRL2,
RTL_REG_SVLAN_C2SCFG56_CTRL0,
RTL_REG_SVLAN_C2SCFG56_CTRL1,
RTL_REG_SVLAN_C2SCFG56_CTRL2,
RTL_REG_SVLAN_C2SCFG57_CTRL0,
RTL_REG_SVLAN_C2SCFG57_CTRL1,
RTL_REG_SVLAN_C2SCFG57_CTRL2,
RTL_REG_SVLAN_C2SCFG58_CTRL0,
RTL_REG_SVLAN_C2SCFG58_CTRL1,
RTL_REG_SVLAN_C2SCFG58_CTRL2,
RTL_REG_SVLAN_C2SCFG59_CTRL0,
RTL_REG_SVLAN_C2SCFG59_CTRL1,
RTL_REG_SVLAN_C2SCFG59_CTRL2,
RTL_REG_SVLAN_C2SCFG60_CTRL0,
RTL_REG_SVLAN_C2SCFG60_CTRL1,
RTL_REG_SVLAN_C2SCFG60_CTRL2,
RTL_REG_SVLAN_C2SCFG61_CTRL0,
RTL_REG_SVLAN_C2SCFG61_CTRL1,
RTL_REG_SVLAN_C2SCFG61_CTRL2,
RTL_REG_SVLAN_C2SCFG62_CTRL0,
RTL_REG_SVLAN_C2SCFG62_CTRL1,
RTL_REG_SVLAN_C2SCFG62_CTRL2,
RTL_REG_SVLAN_C2SCFG63_CTRL0,
RTL_REG_SVLAN_C2SCFG63_CTRL1,
RTL_REG_SVLAN_C2SCFG63_CTRL2,
RTL_REG_SVLAN_C2SCFG64_CTRL0,
RTL_REG_SVLAN_C2SCFG64_CTRL1,
RTL_REG_SVLAN_C2SCFG64_CTRL2,
RTL_REG_SVLAN_C2SCFG65_CTRL0,
RTL_REG_SVLAN_C2SCFG65_CTRL1,
RTL_REG_SVLAN_C2SCFG65_CTRL2,
RTL_REG_SVLAN_C2SCFG66_CTRL0,
RTL_REG_SVLAN_C2SCFG66_CTRL1,
RTL_REG_SVLAN_C2SCFG66_CTRL2,
RTL_REG_SVLAN_C2SCFG67_CTRL0,
RTL_REG_SVLAN_C2SCFG67_CTRL1,
RTL_REG_SVLAN_C2SCFG67_CTRL2,
RTL_REG_SVLAN_C2SCFG68_CTRL0,
RTL_REG_SVLAN_C2SCFG68_CTRL1,
RTL_REG_SVLAN_C2SCFG68_CTRL2,
RTL_REG_SVLAN_C2SCFG69_CTRL0,
RTL_REG_SVLAN_C2SCFG69_CTRL1,
RTL_REG_SVLAN_C2SCFG69_CTRL2,
RTL_REG_SVLAN_C2SCFG70_CTRL0,
RTL_REG_SVLAN_C2SCFG70_CTRL1,
RTL_REG_SVLAN_C2SCFG70_CTRL2,
RTL_REG_SVLAN_C2SCFG71_CTRL0,
RTL_REG_SVLAN_C2SCFG71_CTRL1,
RTL_REG_SVLAN_C2SCFG71_CTRL2,
RTL_REG_SVLAN_C2SCFG72_CTRL0,
RTL_REG_SVLAN_C2SCFG72_CTRL1,
RTL_REG_SVLAN_C2SCFG72_CTRL2,
RTL_REG_SVLAN_C2SCFG73_CTRL0,
RTL_REG_SVLAN_C2SCFG73_CTRL1,
RTL_REG_SVLAN_C2SCFG73_CTRL2,
RTL_REG_SVLAN_C2SCFG74_CTRL0,
RTL_REG_SVLAN_C2SCFG74_CTRL1,
RTL_REG_SVLAN_C2SCFG74_CTRL2,
RTL_REG_SVLAN_C2SCFG75_CTRL0,
RTL_REG_SVLAN_C2SCFG75_CTRL1,
RTL_REG_SVLAN_C2SCFG75_CTRL2,
RTL_REG_SVLAN_C2SCFG76_CTRL0,
RTL_REG_SVLAN_C2SCFG76_CTRL1,
RTL_REG_SVLAN_C2SCFG76_CTRL2,
RTL_REG_SVLAN_C2SCFG77_CTRL0,
RTL_REG_SVLAN_C2SCFG77_CTRL1,
RTL_REG_SVLAN_C2SCFG77_CTRL2,
RTL_REG_SVLAN_C2SCFG78_CTRL0,
RTL_REG_SVLAN_C2SCFG78_CTRL1,
RTL_REG_SVLAN_C2SCFG78_CTRL2,
RTL_REG_SVLAN_C2SCFG79_CTRL0,
RTL_REG_SVLAN_C2SCFG79_CTRL1,
RTL_REG_SVLAN_C2SCFG79_CTRL2,
RTL_REG_SVLAN_C2SCFG80_CTRL0,
RTL_REG_SVLAN_C2SCFG80_CTRL1,
RTL_REG_SVLAN_C2SCFG80_CTRL2,
RTL_REG_SVLAN_C2SCFG81_CTRL0,
RTL_REG_SVLAN_C2SCFG81_CTRL1,
RTL_REG_SVLAN_C2SCFG81_CTRL2,
RTL_REG_SVLAN_C2SCFG82_CTRL0,
RTL_REG_SVLAN_C2SCFG82_CTRL1,
RTL_REG_SVLAN_C2SCFG82_CTRL2,
RTL_REG_SVLAN_C2SCFG83_CTRL0,
RTL_REG_SVLAN_C2SCFG83_CTRL1,
RTL_REG_SVLAN_C2SCFG83_CTRL2,
RTL_REG_SVLAN_C2SCFG84_CTRL0,
RTL_REG_SVLAN_C2SCFG84_CTRL1,
RTL_REG_SVLAN_C2SCFG84_CTRL2,
RTL_REG_SVLAN_C2SCFG85_CTRL0,
RTL_REG_SVLAN_C2SCFG85_CTRL1,
RTL_REG_SVLAN_C2SCFG85_CTRL2,
RTL_REG_SVLAN_C2SCFG86_CTRL0,
RTL_REG_SVLAN_C2SCFG86_CTRL1,
RTL_REG_SVLAN_C2SCFG86_CTRL2,
RTL_REG_SVLAN_C2SCFG87_CTRL0,
RTL_REG_SVLAN_C2SCFG87_CTRL1,
RTL_REG_SVLAN_C2SCFG87_CTRL2,
RTL_REG_SVLAN_C2SCFG88_CTRL0,
RTL_REG_SVLAN_C2SCFG88_CTRL1,
RTL_REG_SVLAN_C2SCFG88_CTRL2,
RTL_REG_SVLAN_C2SCFG89_CTRL0,
RTL_REG_SVLAN_C2SCFG89_CTRL1,
RTL_REG_SVLAN_C2SCFG89_CTRL2,
RTL_REG_SVLAN_C2SCFG90_CTRL0,
RTL_REG_SVLAN_C2SCFG90_CTRL1,
RTL_REG_SVLAN_C2SCFG90_CTRL2,
RTL_REG_SVLAN_C2SCFG91_CTRL0,
RTL_REG_SVLAN_C2SCFG91_CTRL1,
RTL_REG_SVLAN_C2SCFG91_CTRL2,
RTL_REG_SVLAN_C2SCFG92_CTRL0,
RTL_REG_SVLAN_C2SCFG92_CTRL1,
RTL_REG_SVLAN_C2SCFG92_CTRL2,
RTL_REG_SVLAN_C2SCFG93_CTRL0,
RTL_REG_SVLAN_C2SCFG93_CTRL1,
RTL_REG_SVLAN_C2SCFG93_CTRL2,
RTL_REG_SVLAN_C2SCFG94_CTRL0,
RTL_REG_SVLAN_C2SCFG94_CTRL1,
RTL_REG_SVLAN_C2SCFG94_CTRL2,
RTL_REG_SVLAN_C2SCFG95_CTRL0,
RTL_REG_SVLAN_C2SCFG95_CTRL1,
RTL_REG_SVLAN_C2SCFG95_CTRL2,
RTL_REG_SVLAN_C2SCFG96_CTRL0,
RTL_REG_SVLAN_C2SCFG96_CTRL1,
RTL_REG_SVLAN_C2SCFG96_CTRL2,
RTL_REG_SVLAN_C2SCFG97_CTRL0,
RTL_REG_SVLAN_C2SCFG97_CTRL1,
RTL_REG_SVLAN_C2SCFG97_CTRL2,
RTL_REG_SVLAN_C2SCFG98_CTRL0,
RTL_REG_SVLAN_C2SCFG98_CTRL1,
RTL_REG_SVLAN_C2SCFG98_CTRL2,
RTL_REG_SVLAN_C2SCFG99_CTRL0,
RTL_REG_SVLAN_C2SCFG99_CTRL1,
RTL_REG_SVLAN_C2SCFG99_CTRL2,
RTL_REG_SVLAN_C2SCFG100_CTRL0,
RTL_REG_SVLAN_C2SCFG100_CTRL1,
RTL_REG_SVLAN_C2SCFG100_CTRL2,
RTL_REG_SVLAN_C2SCFG101_CTRL0,
RTL_REG_SVLAN_C2SCFG101_CTRL1,
RTL_REG_SVLAN_C2SCFG101_CTRL2,
RTL_REG_SVLAN_C2SCFG102_CTRL0,
RTL_REG_SVLAN_C2SCFG102_CTRL1,
RTL_REG_SVLAN_C2SCFG102_CTRL2,
RTL_REG_SVLAN_C2SCFG103_CTRL0,
RTL_REG_SVLAN_C2SCFG103_CTRL1,
RTL_REG_SVLAN_C2SCFG103_CTRL2,
RTL_REG_SVLAN_C2SCFG104_CTRL0,
RTL_REG_SVLAN_C2SCFG104_CTRL1,
RTL_REG_SVLAN_C2SCFG104_CTRL2,
RTL_REG_SVLAN_C2SCFG105_CTRL0,
RTL_REG_SVLAN_C2SCFG105_CTRL1,
RTL_REG_SVLAN_C2SCFG105_CTRL2,
RTL_REG_SVLAN_C2SCFG106_CTRL0,
RTL_REG_SVLAN_C2SCFG106_CTRL1,
RTL_REG_SVLAN_C2SCFG106_CTRL2,
RTL_REG_SVLAN_C2SCFG107_CTRL0,
RTL_REG_SVLAN_C2SCFG107_CTRL1,
RTL_REG_SVLAN_C2SCFG107_CTRL2,
RTL_REG_SVLAN_C2SCFG108_CTRL0,
RTL_REG_SVLAN_C2SCFG108_CTRL1,
RTL_REG_SVLAN_C2SCFG108_CTRL2,
RTL_REG_SVLAN_C2SCFG109_CTRL0,
RTL_REG_SVLAN_C2SCFG109_CTRL1,
RTL_REG_SVLAN_C2SCFG109_CTRL2,
RTL_REG_SVLAN_C2SCFG110_CTRL0,
RTL_REG_SVLAN_C2SCFG110_CTRL1,
RTL_REG_SVLAN_C2SCFG110_CTRL2,
RTL_REG_SVLAN_C2SCFG111_CTRL0,
RTL_REG_SVLAN_C2SCFG111_CTRL1,
RTL_REG_SVLAN_C2SCFG111_CTRL2,
RTL_REG_SVLAN_C2SCFG112_CTRL0,
RTL_REG_SVLAN_C2SCFG112_CTRL1,
RTL_REG_SVLAN_C2SCFG112_CTRL2,
RTL_REG_SVLAN_C2SCFG113_CTRL0,
RTL_REG_SVLAN_C2SCFG113_CTRL1,
RTL_REG_SVLAN_C2SCFG113_CTRL2,
RTL_REG_SVLAN_C2SCFG114_CTRL0,
RTL_REG_SVLAN_C2SCFG114_CTRL1,
RTL_REG_SVLAN_C2SCFG114_CTRL2,
RTL_REG_SVLAN_C2SCFG115_CTRL0,
RTL_REG_SVLAN_C2SCFG115_CTRL1,
RTL_REG_SVLAN_C2SCFG115_CTRL2,
RTL_REG_SVLAN_C2SCFG116_CTRL0,
RTL_REG_SVLAN_C2SCFG116_CTRL1,
RTL_REG_SVLAN_C2SCFG116_CTRL2,
RTL_REG_SVLAN_C2SCFG117_CTRL0,
RTL_REG_SVLAN_C2SCFG117_CTRL1,
RTL_REG_SVLAN_C2SCFG117_CTRL2,
RTL_REG_SVLAN_C2SCFG118_CTRL0,
RTL_REG_SVLAN_C2SCFG118_CTRL1,
RTL_REG_SVLAN_C2SCFG118_CTRL2,
RTL_REG_SVLAN_C2SCFG119_CTRL0,
RTL_REG_SVLAN_C2SCFG119_CTRL1,
RTL_REG_SVLAN_C2SCFG119_CTRL2,
RTL_REG_SVLAN_C2SCFG120_CTRL0,
RTL_REG_SVLAN_C2SCFG120_CTRL1,
RTL_REG_SVLAN_C2SCFG120_CTRL2,
RTL_REG_SVLAN_C2SCFG121_CTRL0,
RTL_REG_SVLAN_C2SCFG121_CTRL1,
RTL_REG_SVLAN_C2SCFG121_CTRL2,
RTL_REG_SVLAN_C2SCFG122_CTRL0,
RTL_REG_SVLAN_C2SCFG122_CTRL1,
RTL_REG_SVLAN_C2SCFG122_CTRL2,
RTL_REG_SVLAN_C2SCFG123_CTRL0,
RTL_REG_SVLAN_C2SCFG123_CTRL1,
RTL_REG_SVLAN_C2SCFG123_CTRL2,
RTL_REG_SVLAN_C2SCFG124_CTRL0,
RTL_REG_SVLAN_C2SCFG124_CTRL1,
RTL_REG_SVLAN_C2SCFG124_CTRL2,
RTL_REG_SVLAN_C2SCFG125_CTRL0,
RTL_REG_SVLAN_C2SCFG125_CTRL1,
RTL_REG_SVLAN_C2SCFG125_CTRL2,
RTL_REG_SVLAN_C2SCFG126_CTRL0,
RTL_REG_SVLAN_C2SCFG126_CTRL1,
RTL_REG_SVLAN_C2SCFG126_CTRL2,
RTL_REG_SVLAN_C2SCFG127_CTRL0,
RTL_REG_SVLAN_C2SCFG127_CTRL1,
RTL_REG_SVLAN_C2SCFG127_CTRL2,
RTL_REG_SVLAN_CFG,
RTL_REG_SVLAN_PORTBASED_SVIDX_CTRL0,
RTL_REG_SVLAN_PORTBASED_SVIDX_CTRL1,
RTL_REG_SVLAN_PORTBASED_SVIDX_CTRL2,
RTL_REG_SVLAN_PORTBASED_SVIDX_CTRL3,
RTL_REG_SVLAN_UNTAG_UNMAT_CFG,
RTL_REG_SVLAN_LOOKUP_TYPE,
RTL_REG_IPMC_GROUP_VALID_15_0,
RTL_REG_IPMC_GROUP_VALID_31_16,
RTL_REG_IPMC_GROUP_VALID_47_32,
RTL_REG_IPMC_GROUP_VALID_63_48,
RTL_REG_SVLAN_PORTBASED_SVIDX_CTRL4,
RTL_REG_SVLAN_PORTBASED_SVIDX_CTRL5,
RTL_REG_SVLAN_CFG_EXT,
RTL_REG_SVLAN_MEMBERCFG63_CTRL4,
RTL_REG_SVLAN_DUMMY_0,
RTL_REG_SVLAN_DUMMY_1,
RTL_REG_SVLAN_DUMMY_2,
RTL_REG_SVLAN_DUMMY_3,
RTL_REG_SVLAN_DUMMY_4,
RTL_REG_SVLAN_DUMMY_5,
RTL_REG_SVLAN_DUMMY_6,
RTL_REG_SVLAN_DUMMY_7,
RTL_REG_SVLAN_DUMMY_8,
RTL_REG_SVLAN_DUMMY_9,
RTL_REG_SVLAN_DUMMY_10,
RTL_REG_SVLAN_DUMMY_11,
RTL_REG_SVLAN_DUMMY_12,
RTL_REG_SVLAN_DUMMY_13,
RTL_REG_SVLAN_DUMMY_14,
RTL_REG_SVLAN_DUMMY_15,
RTL_REG_SVLAN_DUMMY_16,
RTL_REG_SVLAN_DUMMY_17,
RTL_REG_SVLAN_DUMMY_18,
RTL_REG_SVLAN_DUMMY_19,
RTL_REG_SVLAN_DUMMY_20,
RTL_REG_SVLAN_DUMMY_21,
RTL_REG_SVLAN_DUMMY_22,
RTL_REG_SVLAN_DUMMY_23,
RTL_REG_SVLAN_DUMMY_24,
RTL_REG_SVLAN_DUMMY_25,
RTL_REG_SVLAN_DUMMY_26,
RTL_REG_SVLAN_DUMMY_27,
RTL_REG_SVLAN_DUMMY_28,
RTL_REG_SVLAN_DUMMY_29,
RTL_REG_SVLAN_DUMMY_30,
RTL_REG_SVLAN_DUMMY_31,
RTL_REG_IPMC_GROUP_VID_00,
RTL_REG_IPMC_GROUP_VID_01,
RTL_REG_IPMC_GROUP_VID_02,
RTL_REG_IPMC_GROUP_VID_03,
RTL_REG_IPMC_GROUP_VID_04,
RTL_REG_IPMC_GROUP_VID_05,
RTL_REG_IPMC_GROUP_VID_06,
RTL_REG_IPMC_GROUP_VID_07,
RTL_REG_IPMC_GROUP_VID_08,
RTL_REG_IPMC_GROUP_VID_09,
RTL_REG_IPMC_GROUP_VID_10,
RTL_REG_IPMC_GROUP_VID_11,
RTL_REG_IPMC_GROUP_VID_12,
RTL_REG_IPMC_GROUP_VID_13,
RTL_REG_IPMC_GROUP_VID_14,
RTL_REG_IPMC_GROUP_VID_15,
RTL_REG_IPMC_GROUP_VID_16,
RTL_REG_IPMC_GROUP_VID_17,
RTL_REG_IPMC_GROUP_VID_18,
RTL_REG_IPMC_GROUP_VID_19,
RTL_REG_IPMC_GROUP_VID_20,
RTL_REG_IPMC_GROUP_VID_21,
RTL_REG_IPMC_GROUP_VID_22,
RTL_REG_IPMC_GROUP_VID_23,
RTL_REG_IPMC_GROUP_VID_24,
RTL_REG_IPMC_GROUP_VID_25,
RTL_REG_IPMC_GROUP_VID_26,
RTL_REG_IPMC_GROUP_VID_27,
RTL_REG_IPMC_GROUP_VID_28,
RTL_REG_IPMC_GROUP_VID_29,
RTL_REG_IPMC_GROUP_VID_30,
RTL_REG_IPMC_GROUP_VID_31,
RTL_REG_IPMC_GROUP_VID_32,
RTL_REG_IPMC_GROUP_VID_33,
RTL_REG_IPMC_GROUP_VID_34,
RTL_REG_IPMC_GROUP_VID_35,
RTL_REG_IPMC_GROUP_VID_36,
RTL_REG_IPMC_GROUP_VID_37,
RTL_REG_IPMC_GROUP_VID_38,
RTL_REG_IPMC_GROUP_VID_39,
RTL_REG_IPMC_GROUP_VID_40,
RTL_REG_IPMC_GROUP_VID_41,
RTL_REG_IPMC_GROUP_VID_42,
RTL_REG_IPMC_GROUP_VID_43,
RTL_REG_IPMC_GROUP_VID_44,
RTL_REG_IPMC_GROUP_VID_45,
RTL_REG_IPMC_GROUP_VID_46,
RTL_REG_IPMC_GROUP_VID_47,
RTL_REG_IPMC_GROUP_VID_48,
RTL_REG_IPMC_GROUP_VID_49,
RTL_REG_IPMC_GROUP_VID_50,
RTL_REG_IPMC_GROUP_VID_51,
RTL_REG_IPMC_GROUP_VID_52,
RTL_REG_IPMC_GROUP_VID_53,
RTL_REG_IPMC_GROUP_VID_54,
RTL_REG_IPMC_GROUP_VID_55,
RTL_REG_IPMC_GROUP_VID_56,
RTL_REG_IPMC_GROUP_VID_57,
RTL_REG_IPMC_GROUP_VID_58,
RTL_REG_IPMC_GROUP_VID_59,
RTL_REG_IPMC_GROUP_VID_60,
RTL_REG_IPMC_GROUP_VID_61,
RTL_REG_IPMC_GROUP_VID_62,
RTL_REG_IPMC_GROUP_VID_63,
RTL_REG_SVLAN_SP2C_ENTRY0_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY0_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY1_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY1_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY2_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY2_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY3_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY3_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY4_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY4_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY5_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY5_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY6_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY6_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY7_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY7_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY8_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY8_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY9_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY9_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY10_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY10_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY11_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY11_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY12_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY12_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY13_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY13_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY14_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY14_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY15_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY15_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY16_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY16_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY17_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY17_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY18_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY18_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY19_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY19_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY20_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY20_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY21_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY21_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY22_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY22_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY23_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY23_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY24_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY24_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY25_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY25_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY26_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY26_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY27_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY27_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY28_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY28_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY29_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY29_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY30_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY30_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY31_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY31_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY32_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY32_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY33_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY33_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY34_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY34_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY35_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY35_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY36_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY36_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY37_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY37_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY38_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY38_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY39_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY39_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY40_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY40_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY41_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY41_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY42_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY42_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY43_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY43_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY44_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY44_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY45_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY45_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY46_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY46_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY47_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY47_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY48_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY48_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY49_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY49_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY50_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY50_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY51_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY51_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY52_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY52_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY53_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY53_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY54_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY54_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY55_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY55_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY56_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY56_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY57_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY57_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY58_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY58_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY59_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY59_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY60_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY60_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY61_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY61_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY62_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY62_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY63_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY63_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY64_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY64_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY65_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY65_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY66_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY66_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY67_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY67_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY68_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY68_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY69_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY69_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY70_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY70_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY71_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY71_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY72_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY72_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY73_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY73_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY74_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY74_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY75_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY75_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY76_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY76_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY77_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY77_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY78_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY78_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY79_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY79_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY80_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY80_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY81_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY81_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY82_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY82_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY83_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY83_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY84_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY84_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY85_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY85_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY86_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY86_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY87_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY87_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY88_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY88_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY89_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY89_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY90_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY90_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY91_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY91_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY92_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY92_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY93_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY93_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY94_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY94_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY95_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY95_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY96_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY96_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY97_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY97_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY98_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY98_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY99_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY99_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY100_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY100_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY101_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY101_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY102_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY102_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY103_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY103_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY104_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY104_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY105_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY105_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY106_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY106_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY107_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY107_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY108_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY108_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY109_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY109_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY110_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY110_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY111_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY111_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY112_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY112_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY113_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY113_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY114_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY114_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY115_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY115_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY116_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY116_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY117_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY117_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY118_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY118_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY119_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY119_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY120_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY120_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY121_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY121_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY122_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY122_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY123_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY123_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY124_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY124_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY125_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY125_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY126_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY126_CTRL1,
RTL_REG_SVLAN_SP2C_ENTRY127_CTRL0,
RTL_REG_SVLAN_SP2C_ENTRY127_CTRL1,
RTL_REG_MIB_COUNTER0,
RTL_REG_MIB_COUNTER1,
RTL_REG_MIB_COUNTER2,
RTL_REG_MIB_COUNTER3,
RTL_REG_MIB_ADDRESS,
RTL_REG_MIB_CTRL0,
RTL_REG_MIB_CTRL1,
RTL_REG_MIB_CTRL2,
RTL_REG_MIB_CTRL3,
RTL_REG_MIB_CTRL4,
RTL_REG_MIB_CTRL5,
RTL_REG_INTR_CTRL,
RTL_REG_INTR_IMR,
RTL_REG_INTR_IMS,
RTL_REG_LEARN_OVER_INDICATOR,
RTL_REG_SPEED_CHANGE_INDICATOR,
RTL_REG_SPECIAL_CONGEST_INDICATOR,
RTL_REG_PORT_LINKDOWN_INDICATOR,
RTL_REG_PORT_LINKUP_INDICATOR,
RTL_REG_SYSTEM_LEARN_OVER_INDICATOR,
RTL_REG_INTR_IMR_8051,
RTL_REG_INTR_IMS_8051,
RTL_REG_DW8051_INT_CPU,
RTL_REG_LEARN_OVER_INDICATOR_8051,
RTL_REG_SPEED_CHANGE_INDICATOR_8051,
RTL_REG_SPECIAL_CONGEST_INDICATOR_8051,
RTL_REG_PORT_LINKDOWN_INDICATOR_8051,
RTL_REG_PORT_LINKUP_INDICATOR_8051,
RTL_REG_DUMMY_1125,
RTL_REG_DUMMY_1126,
RTL_REG_DUMMY_1127,
RTL_REG_DUMMY_1128,
RTL_REG_DUMMY_1129,
RTL_REG_INTR_IMS_BUFFER_RESET,
RTL_REG_INTR_IMS_8051_BUFFER_RESET,
RTL_REG_GPHY_INTRPT_8051,
RTL_REG_GPHY_INTRPT,
RTL_REG_THERMAL_INTRPT,
RTL_REG_THERMAL_INTRPT_8051,
RTL_REG_SDS_LINK_CHG_INT,
RTL_REG_SDS_LINK_CHG_INT_8051,
RTL_REG_MAX_LENGTH_LIMINT_IPG,
RTL_REG_IOL_RXDROP_CFG,
RTL_REG_VS_TPID,
RTL_REG_INBW_BOUND,
RTL_REG_CFG_TX_ITFSP_OP,
RTL_REG_INBW_BOUND2,
RTL_REG_CFG_48PASS1_DROP,
RTL_REG_CFG_BACKPRESSURE,
RTL_REG_CFG_UNHIOL,
RTL_REG_SWITCH_MAC0,
RTL_REG_SWITCH_MAC1,
RTL_REG_SWITCH_MAC2,
RTL_REG_SWITCH_CTRL0,
RTL_REG_QOS_DSCP_REMARK_CTRL0,
RTL_REG_QOS_DSCP_REMARK_CTRL1,
RTL_REG_QOS_DSCP_REMARK_CTRL2,
RTL_REG_QOS_DSCP_REMARK_CTRL3,
RTL_REG_QOS_1Q_REMARK_CTRL0,
RTL_REG_QOS_1Q_REMARK_CTRL1,
RTL_REG_SW_DUMMY0,
RTL_REG_SW_DUMMY1,
RTL_REG_SVLAN_UPLINK_PORTMASK,
RTL_REG_CPU_PORT_MASK,
RTL_REG_CPU_CTRL,
RTL_REG_MIRROR_CTRL,
RTL_REG_FLOWCTRL_CTRL0,
RTL_REG_FLOWCTRL_ALL_ON,
RTL_REG_FLOWCTRL_SYS_ON,
RTL_REG_FLOWCTRL_SYS_OFF,
RTL_REG_FLOWCTRL_SHARE_ON,
RTL_REG_FLOWCTRL_SHARE_OFF,
RTL_REG_FLOWCTRL_FCOFF_SYS_ON,
RTL_REG_FLOWCTRL_FCOFF_SYS_OFF,
RTL_REG_FLOWCTRL_FCOFF_SHARE_ON,
RTL_REG_FLOWCTRL_FCOFF_SHARE_OFF,
RTL_REG_FLOWCTRL_PORT_ON,
RTL_REG_FLOWCTRL_PORT_OFF,
RTL_REG_FLOWCTRL_PORT_PRIVATE_ON,
RTL_REG_FLOWCTRL_PORT_PRIVATE_OFF,
RTL_REG_RRCP_CTRL0,
RTL_REG_RRCP_CTRL1,
RTL_REG_RRCP_CTRL2,
RTL_REG_RRCP_CTRL3,
RTL_REG_FLOWCTRL_FCOFF_PORT_ON,
RTL_REG_FLOWCTRL_FCOFF_PORT_OFF,
RTL_REG_FLOWCTRL_FCOFF_PORT_PRIVATE_ON,
RTL_REG_FLOWCTRL_FCOFF_PORT_PRIVATE_OFF,
RTL_REG_FLOWCTRL_JUMBO_SYS_ON,
RTL_REG_FLOWCTRL_JUMBO_SYS_OFF,
RTL_REG_FLOWCTRL_JUMBO_SHARE_ON,
RTL_REG_FLOWCTRL_JUMBO_SHARE_OFF,
RTL_REG_FLOWCTRL_JUMBO_PORT_ON,
RTL_REG_FLOWCTRL_JUMBO_PORT_OFF,
RTL_REG_FLOWCTRL_JUMBO_PORT_PRIVATE_ON,
RTL_REG_FLOWCTRL_JUMBO_PORT_PRIVATE_OFF,
RTL_REG_FLOWCTRL_JUMBO_SIZE,
RTL_REG_FLOWCTRL_TOTAL_PAGE_COUNTER,
RTL_REG_FLOWCTRL_PUBLIC_PAGE_COUNTER,
RTL_REG_FLOWCTRL_TOTAL_PAGE_MAX,
RTL_REG_FLOWCTRL_PUBLIC_PAGE_MAX,
RTL_REG_FLOWCTRL_PORT0_PAGE_COUNTER,
RTL_REG_FLOWCTRL_PORT1_PAGE_COUNTER,
RTL_REG_FLOWCTRL_PORT2_PAGE_COUNTER,
RTL_REG_FLOWCTRL_PORT3_PAGE_COUNTER,
RTL_REG_FLOWCTRL_PORT4_PAGE_COUNTER,
RTL_REG_FLOWCTRL_PORT5_PAGE_COUNTER,
RTL_REG_FLOWCTRL_PORT6_PAGE_COUNTER,
RTL_REG_FLOWCTRL_PORT7_PAGE_COUNTER,
RTL_REG_FLOWCTRL_PUBLIC_FCOFF_PAGE_COUNTER,
RTL_REG_FLOWCTRL_PUBLIC_JUMBO_PAGE_COUNTER,
RTL_REG_FLOWCTRL_MAX_PUBLIC_FCOFF_PAGE_COUNTER,
RTL_REG_FLOWCTRL_MAX_PUBLIC_JUMBO_PAGE_COUNTER,
RTL_REG_FLOWCTRL_PORT0_PAGE_MAX,
RTL_REG_FLOWCTRL_PORT1_PAGE_MAX,
RTL_REG_FLOWCTRL_PORT2_PAGE_MAX,
RTL_REG_FLOWCTRL_PORT3_PAGE_MAX,
RTL_REG_FLOWCTRL_PORT4_PAGE_MAX,
RTL_REG_FLOWCTRL_PORT5_PAGE_MAX,
RTL_REG_FLOWCTRL_PORT6_PAGE_MAX,
RTL_REG_FLOWCTRL_PORT7_PAGE_MAX,
RTL_REG_FLOWCTRL_PAGE_COUNT_CLEAR,
RTL_REG_FLOWCTRL_PORT8_PAGE_MAX,
RTL_REG_FLOWCTRL_PORT9_PAGE_MAX,
RTL_REG_FLOWCTRL_PORT10_PAGE_MAX,
RTL_REG_FLOWCTRL_PORT8_PAGE_COUNTER,
RTL_REG_FLOWCTRL_PORT9_PAGE_COUNTER,
RTL_REG_FLOWCTRL_PORT10_PAGE_COUNTER,
RTL_REG_RRCP_CTRL1_H,
RTL_REG_EMA_CTRL0,
RTL_REG_EMA_CTRL1,
RTL_REG_EMA_CTRL2,
RTL_REG_EMA_CTRL3,
RTL_REG_EMA_CTRL4,
RTL_REG_DIAG_MODE,
RTL_REG_BIST_MODE,
RTL_REG_STS_BIST_DONE,
RTL_REG_STS_BIST_RLT0,
RTL_REG_STS_BIST_RLT1,
RTL_REG_STS_BIST_RLT2,
RTL_REG_STS_BIST_RLT3,
RTL_REG_STS_BIST_RLT4,
RTL_REG_VIAROM_MISR,
RTL_REG_DRF_BIST_MODE,
RTL_REG_STS_DRF_BIST,
RTL_REG_STS_DRF_BIST_RLT0,
RTL_REG_STS_DRF_BIST_RLT1,
RTL_REG_STS_DRF_BIST_RLT2,
RTL_REG_STS_DRF_BIST_RLT3,
RTL_REG_STS_DRF_BIST_RLT4,
RTL_REG_RAM_DRF_CTRL,
RTL_REG_MIB_RMON_LEN_CTRL,
RTL_REG_COND0_BISR_OUT0,
RTL_REG_COND0_BISR_OUT1,
RTL_REG_COND0_BISR_OUT2,
RTL_REG_COND0_BISR_OUT3,
RTL_REG_COND0_BISR_OUT4,
RTL_REG_COND0_BISR_OUT5,
RTL_REG_CHG_DUPLEX_CFG,
RTL_REG_COND0_BIST_PASS,
RTL_REG_COND1_BISR_OUT0,
RTL_REG_COND1_BISR_OUT1,
RTL_REG_COND1_BISR_OUT2,
RTL_REG_COND1_BISR_OUT3,
RTL_REG_COND1_BISR_OUT4,
RTL_REG_COND1_BISR_OUT5,
RTL_REG_COND1_BIST_PASS,
RTL_REG_EEE_TX_THR_Giga_500M,
RTL_REG_EEE_TX_THR_FE,
RTL_REG_EEE_MISC,
RTL_REG_EEE_GIGA_CTRL0,
RTL_REG_EEE_GIGA_CTRL1,
RTL_REG_EEE_100M_CTRL0,
RTL_REG_EEE_100M_CTRL1,
RTL_REG_RX_FC_REG,
RTL_REG_MAX_FIFO_SIZE,
RTL_REG_EEEP_RX_RATE_GIGA,
RTL_REG_EEEP_RX_RATE_100M,
RTL_REG_DUMMY_REG_12_2,
RTL_REG_EEEP_TX_RATE_GIGA,
RTL_REG_EEEP_TX_RATE_100M,
RTL_REG_DUMMY_REG_12_3,
RTL_REG_EEEP_GIGA_CTRL0,
RTL_REG_EEEP_GIGA_CTRL1,
RTL_REG_EEEP_GIGA_CTRL2,
RTL_REG_EEEP_100M_CTRL0,
RTL_REG_EEEP_100M_CTRL1,
RTL_REG_EEEP_100M_CTRL2,
RTL_REG_EEEP_CTRL0,
RTL_REG_EEEP_CTRL1,
RTL_REG_BACK_PRESSURE_IPG,
RTL_REG_TX_ESD_LEVEL,
RTL_REG_RRCP_CTRL4,
RTL_REG_RRCP_CTRL5,
RTL_REG_RRCP_CTRL6,
RTL_REG_RRCP_CTRL7,
RTL_REG_RRCP_CTRL8,
RTL_REG_RRCP_CTRL9,
RTL_REG_RRCP_CTRL10,
RTL_REG_FIELD_SELECTOR0,
RTL_REG_FIELD_SELECTOR1,
RTL_REG_FIELD_SELECTOR2,
RTL_REG_FIELD_SELECTOR3,
RTL_REG_FIELD_SELECTOR4,
RTL_REG_FIELD_SELECTOR5,
RTL_REG_FIELD_SELECTOR6,
RTL_REG_FIELD_SELECTOR7,
RTL_REG_FIELD_SELECTOR8,
RTL_REG_FIELD_SELECTOR9,
RTL_REG_FIELD_SELECTOR10,
RTL_REG_FIELD_SELECTOR11,
RTL_REG_FIELD_SELECTOR12,
RTL_REG_FIELD_SELECTOR13,
RTL_REG_FIELD_SELECTOR14,
RTL_REG_FIELD_SELECTOR15,
RTL_REG_HWPKT_GEN_MISC_H,
RTL_REG_MIRROR_SRC_PMSK,
RTL_REG_EEE_BURSTSIZE,
RTL_REG_EEE_IFG_CFG,
RTL_REG_FPGA_VER_MAC,
RTL_REG_HWPKT_GEN_MISC,
RTL_REG_CHIP_NUMBER,
RTL_REG_CHIP_VER,
RTL_REG_CHIP_DEBUG0,
RTL_REG_CHIP_DEBUG1,
RTL_REG_DIGITAL_INTERFACE_SELECT,
RTL_REG_EXT0_RGMXF,
RTL_REG_EXT1_RGMXF,
RTL_REG_BISR_CTRL,
RTL_REG_SLF_IF,
RTL_REG_I2C_CLOCK_DIV,
RTL_REG_MDX_MDC_DIV,
RTL_REG_MISCELLANEOUS_CONFIGURE0,
RTL_REG_MISCELLANEOUS_CONFIGURE1,
RTL_REG_PHY_AD,
RTL_REG_DIGITAL_INTERFACE0_FORCE,
RTL_REG_DIGITAL_INTERFACE1_FORCE,
RTL_REG_MAC0_FORCE_SELECT,
RTL_REG_MAC1_FORCE_SELECT,
RTL_REG_MAC2_FORCE_SELECT,
RTL_REG_MAC3_FORCE_SELECT,
RTL_REG_MAC4_FORCE_SELECT,
RTL_REG_MAC5_FORCE_SELECT,
RTL_REG_MAC6_FORCE_SELECT,
RTL_REG_MAC7_FORCE_SELECT,
RTL_REG_M10_FORCE_SELECT,
RTL_REG_CHIP_RESET,
RTL_REG_DIGITAL_DEBUG_0,
RTL_REG_DIGITAL_DEBUG_1,
RTL_REG_INTERNAL_PHY_MDC_DRIVER,
RTL_REG_LINKDOWN_TIME_CTRL,
RTL_REG_PHYACK_TIMEOUT,
RTL_REG_MDXACK_TIMEOUT,
RTL_REG_DW8051_RDY,
RTL_REG_BIST_CTRL,
RTL_REG_DIAG_MODE2,
RTL_REG_MDX_PHY_REG0,
RTL_REG_MDX_PHY_REG1,
RTL_REG_DEBUG_SIGNAL_SELECT_SW,
RTL_REG_DEBUG_SIGNAL_SELECT_B,
RTL_REG_DEBUG_SIGNAL_I,
RTL_REG_DEBUG_SIGNAL_H,
RTL_REG_DBGO_SEL_GPHY,
RTL_REG_DBGO_SEL_MISC,
RTL_REG_BYPASS_ABLTY_LOCK,
RTL_REG_BYPASS_ABLTY_LOCK_EXT,
RTL_REG_ACL_GPIO,
RTL_REG_EN_GPIO,
RTL_REG_CFG_MULTI_PIN,
RTL_REG_PORT0_STATUS,
RTL_REG_PORT1_STATUS,
RTL_REG_PORT2_STATUS,
RTL_REG_PORT3_STATUS,
RTL_REG_PORT4_STATUS,
RTL_REG_PORT5_STATUS,
RTL_REG_PORT6_STATUS,
RTL_REG_PORT7_STATUS,
RTL_REG_PORT8_STATUS,
RTL_REG_PORT9_STATUS,
RTL_REG_PORT10_STATUS,
RTL_REG_UPS_CTRL0,
RTL_REG_UPS_CTRL1,
RTL_REG_UPS_CTRL2,
RTL_REG_GATING_CLK_1,
RTL_REG_UPS_CTRL4,
RTL_REG_UPS_CTRL5,
RTL_REG_UPS_CTRL6,
RTL_REG_I2C_CTRL,
RTL_REG_EEE_CFG,
RTL_REG_EEE_PAGE,
RTL_REG_EEE_EXT_PAGE,
RTL_REG_EEE_EN_SPD1000,
RTL_REG_EEE_EN_SPD100,
RTL_REG_EEE_LP_SPD1000,
RTL_REG_EEE_LP_SPD100,
RTL_REG_DW8051_PRO_REG0,
RTL_REG_DW8051_PRO_REG1,
RTL_REG_DW8051_PRO_REG2,
RTL_REG_DW8051_PRO_REG3,
RTL_REG_DW8051_PRO_REG4,
RTL_REG_DW8051_PRO_REG5,
RTL_REG_DW8051_PRO_REG6,
RTL_REG_DW8051_PRO_REG7,
RTL_REG_PROTECT_ID,
RTL_REG_CHIP_VER_INTL,
RTL_REG_MAGIC_ID,
RTL_REG_DIGITAL_INTERFACE_SELECT_1,
RTL_REG_DIGITAL_INTERFACE2_FORCE,
RTL_REG_EXT2_RGMXF,
RTL_REG_ROUTER_UPS_CFG,
RTL_REG_CTRL_GPIO,
RTL_REG_SEL_GPIO,
RTL_REG_STATUS_GPIO,
RTL_REG_SYNC_ETH_CFG,
RTL_REG_LED_DRI_CFG,
RTL_REG_CHIP_DEBUG2,
RTL_REG_DIGITAL_DEBUG_2,
RTL_REG_FIBER_RTL_OUI_CFG0,
RTL_REG_FIBER_RTL_OUI_CFG1,
RTL_REG_FIBER_CFG_0,
RTL_REG_FIBER_CFG_1,
RTL_REG_FIBER_CFG_2,
RTL_REG_FIBER_CFG_3,
RTL_REG_FIBER_CFG_4,
RTL_REG_UTP_FIB_DET,
RTL_REG_NRESTORE_MAGIC_NUM,
RTL_REG_MAC_ACTIVE,
RTL_REG_SERDES_RESULT,
RTL_REG_CHIP_ECO,
RTL_REG_WAKELPI_SLOT_PRD,
RTL_REG_WAKELPI_SLOT_PG0,
RTL_REG_WAKELPI_SLOT_PG1,
RTL_REG_WAKELPI_SLOT_PG2,
RTL_REG_WAKELPI_SLOT_PG3,
RTL_REG_SYNC_FIFO_0,
RTL_REG_SYNC_FIFO_1,
RTL_REG_RGM_EEE,
RTL_REG_EXT_TXC_DLY,
RTL_REG_IO_MISC_CTRL,
RTL_REG_CHIP_DUMMY_NO,
RTL_REG_RC_CALIB_CFG,
RTL_REG_WAKELPI_SLOT_PG4,
RTL_REG_WAKELPI_SLOT_PG5,
RTL_REG_METER0_RATE_CTRL0,
RTL_REG_METER0_RATE_CTRL1,
RTL_REG_METER1_RATE_CTRL0,
RTL_REG_METER1_RATE_CTRL1,
RTL_REG_METER2_RATE_CTRL0,
RTL_REG_METER2_RATE_CTRL1,
RTL_REG_METER3_RATE_CTRL0,
RTL_REG_METER3_RATE_CTRL1,
RTL_REG_METER4_RATE_CTRL0,
RTL_REG_METER4_RATE_CTRL1,
RTL_REG_METER5_RATE_CTRL0,
RTL_REG_METER5_RATE_CTRL1,
RTL_REG_METER6_RATE_CTRL0,
RTL_REG_METER6_RATE_CTRL1,
RTL_REG_METER7_RATE_CTRL0,
RTL_REG_METER7_RATE_CTRL1,
RTL_REG_METER8_RATE_CTRL0,
RTL_REG_METER8_RATE_CTRL1,
RTL_REG_METER9_RATE_CTRL0,
RTL_REG_METER9_RATE_CTRL1,
RTL_REG_METER10_RATE_CTRL0,
RTL_REG_METER10_RATE_CTRL1,
RTL_REG_METER11_RATE_CTRL0,
RTL_REG_METER11_RATE_CTRL1,
RTL_REG_METER12_RATE_CTRL0,
RTL_REG_METER12_RATE_CTRL1,
RTL_REG_METER13_RATE_CTRL0,
RTL_REG_METER13_RATE_CTRL1,
RTL_REG_METER14_RATE_CTRL0,
RTL_REG_METER14_RATE_CTRL1,
RTL_REG_METER15_RATE_CTRL0,
RTL_REG_METER15_RATE_CTRL1,
RTL_REG_METER16_RATE_CTRL0,
RTL_REG_METER16_RATE_CTRL1,
RTL_REG_METER17_RATE_CTRL0,
RTL_REG_METER17_RATE_CTRL1,
RTL_REG_METER18_RATE_CTRL0,
RTL_REG_METER18_RATE_CTRL1,
RTL_REG_METER19_RATE_CTRL0,
RTL_REG_METER19_RATE_CTRL1,
RTL_REG_METER20_RATE_CTRL0,
RTL_REG_METER20_RATE_CTRL1,
RTL_REG_METER21_RATE_CTRL0,
RTL_REG_METER21_RATE_CTRL1,
RTL_REG_METER22_RATE_CTRL0,
RTL_REG_METER22_RATE_CTRL1,
RTL_REG_METER23_RATE_CTRL0,
RTL_REG_METER23_RATE_CTRL1,
RTL_REG_METER24_RATE_CTRL0,
RTL_REG_METER24_RATE_CTRL1,
RTL_REG_METER25_RATE_CTRL0,
RTL_REG_METER25_RATE_CTRL1,
RTL_REG_METER26_RATE_CTRL0,
RTL_REG_METER26_RATE_CTRL1,
RTL_REG_METER27_RATE_CTRL0,
RTL_REG_METER27_RATE_CTRL1,
RTL_REG_METER28_RATE_CTRL0,
RTL_REG_METER28_RATE_CTRL1,
RTL_REG_METER29_RATE_CTRL0,
RTL_REG_METER29_RATE_CTRL1,
RTL_REG_METER30_RATE_CTRL0,
RTL_REG_METER30_RATE_CTRL1,
RTL_REG_METER31_RATE_CTRL0,
RTL_REG_METER31_RATE_CTRL1,
RTL_REG_METER_MODE_SETTING0,
RTL_REG_METER_MODE_SETTING1,
RTL_REG_METER_MODE_TOKEN_CFG,
RTL_REG_METER0_BUCKET_SIZE,
RTL_REG_METER1_BUCKET_SIZE,
RTL_REG_METER2_BUCKET_SIZE,
RTL_REG_METER3_BUCKET_SIZE,
RTL_REG_METER4_BUCKET_SIZE,
RTL_REG_METER5_BUCKET_SIZE,
RTL_REG_METER6_BUCKET_SIZE,
RTL_REG_METER7_BUCKET_SIZE,
RTL_REG_METER8_BUCKET_SIZE,
RTL_REG_METER9_BUCKET_SIZE,
RTL_REG_METER10_BUCKET_SIZE,
RTL_REG_METER11_BUCKET_SIZE,
RTL_REG_METER12_BUCKET_SIZE,
RTL_REG_METER13_BUCKET_SIZE,
RTL_REG_METER14_BUCKET_SIZE,
RTL_REG_METER15_BUCKET_SIZE,
RTL_REG_METER16_BUCKET_SIZE,
RTL_REG_METER17_BUCKET_SIZE,
RTL_REG_METER18_BUCKET_SIZE,
RTL_REG_METER19_BUCKET_SIZE,
RTL_REG_METER20_BUCKET_SIZE,
RTL_REG_METER21_BUCKET_SIZE,
RTL_REG_METER22_BUCKET_SIZE,
RTL_REG_METER23_BUCKET_SIZE,
RTL_REG_METER24_BUCKET_SIZE,
RTL_REG_METER25_BUCKET_SIZE,
RTL_REG_METER26_BUCKET_SIZE,
RTL_REG_METER27_BUCKET_SIZE,
RTL_REG_METER28_BUCKET_SIZE,
RTL_REG_METER29_BUCKET_SIZE,
RTL_REG_METER30_BUCKET_SIZE,
RTL_REG_METER31_BUCKET_SIZE,
RTL_REG_METER_CTRL0,
RTL_REG_METER_CTRL1,
RTL_REG_METER_OVERRATE_INDICATOR0,
RTL_REG_METER_OVERRATE_INDICATOR1,
RTL_REG_METER_OVERRATE_INDICATOR0_8051,
RTL_REG_METER_OVERRATE_INDICATOR1_8051,
RTL_REG_METER_IFG_CTRL0,
RTL_REG_METER_IFG_CTRL1,
RTL_REG_METER_CTRL2,
RTL_REG_DUMMY_1723,
RTL_REG_DUMMY_1724,
RTL_REG_DUMMY_1725,
RTL_REG_DUMMY_1726,
RTL_REG_DUMMY_1727,
RTL_REG_DUMMY_1728,
RTL_REG_DUMMY_1729,
RTL_REG_DUMMY_172A,
RTL_REG_DUMMY_172B,
RTL_REG_DUMMY_172C,
RTL_REG_DUMMY_172D,
RTL_REG_DUMMY_172E,
RTL_REG_DUMMY_172F,
RTL_REG_DUMMY_1730,
RTL_REG_DUMMY_1731,
RTL_REG_METER32_RATE_CTRL0,
RTL_REG_METER32_RATE_CTRL1,
RTL_REG_METER33_RATE_CTRL0,
RTL_REG_METER33_RATE_CTRL1,
RTL_REG_METER34_RATE_CTRL0,
RTL_REG_METER34_RATE_CTRL1,
RTL_REG_METER35_RATE_CTRL0,
RTL_REG_METER35_RATE_CTRL1,
RTL_REG_METER36_RATE_CTRL0,
RTL_REG_METER36_RATE_CTRL1,
RTL_REG_METER37_RATE_CTRL0,
RTL_REG_METER37_RATE_CTRL1,
RTL_REG_METER38_RATE_CTRL0,
RTL_REG_METER38_RATE_CTRL1,
RTL_REG_METER39_RATE_CTRL0,
RTL_REG_METER39_RATE_CTRL1,
RTL_REG_METER40_RATE_CTRL0,
RTL_REG_METER40_RATE_CTRL1,
RTL_REG_METER41_RATE_CTRL0,
RTL_REG_METER41_RATE_CTRL1,
RTL_REG_METER42_RATE_CTRL0,
RTL_REG_METER42_RATE_CTRL1,
RTL_REG_METER43_RATE_CTRL0,
RTL_REG_METER43_RATE_CTRL1,
RTL_REG_METER44_RATE_CTRL0,
RTL_REG_METER44_RATE_CTRL1,
RTL_REG_METER45_RATE_CTRL0,
RTL_REG_METER45_RATE_CTRL1,
RTL_REG_METER46_RATE_CTRL0,
RTL_REG_METER46_RATE_CTRL1,
RTL_REG_METER47_RATE_CTRL0,
RTL_REG_METER47_RATE_CTRL1,
RTL_REG_METER48_RATE_CTRL0,
RTL_REG_METER48_RATE_CTRL1,
RTL_REG_METER49_RATE_CTRL0,
RTL_REG_METER49_RATE_CTRL1,
RTL_REG_METER50_RATE_CTRL0,
RTL_REG_METER50_RATE_CTRL1,
RTL_REG_METER51_RATE_CTRL0,
RTL_REG_METER51_RATE_CTRL1,
RTL_REG_METER52_RATE_CTRL0,
RTL_REG_METER52_RATE_CTRL1,
RTL_REG_METER53_RATE_CTRL0,
RTL_REG_METER53_RATE_CTRL1,
RTL_REG_METER54_RATE_CTRL0,
RTL_REG_METER54_RATE_CTRL1,
RTL_REG_METER55_RATE_CTRL0,
RTL_REG_METER55_RATE_CTRL1,
RTL_REG_METER56_RATE_CTRL0,
RTL_REG_METER56_RATE_CTRL1,
RTL_REG_METER57_RATE_CTRL0,
RTL_REG_METER57_RATE_CTRL1,
RTL_REG_METER58_RATE_CTRL0,
RTL_REG_METER58_RATE_CTRL1,
RTL_REG_METER59_RATE_CTRL0,
RTL_REG_METER59_RATE_CTRL1,
RTL_REG_METER60_RATE_CTRL0,
RTL_REG_METER60_RATE_CTRL1,
RTL_REG_METER61_RATE_CTRL0,
RTL_REG_METER61_RATE_CTRL1,
RTL_REG_METER62_RATE_CTRL0,
RTL_REG_METER62_RATE_CTRL1,
RTL_REG_METER63_RATE_CTRL0,
RTL_REG_METER63_RATE_CTRL1,
RTL_REG_METER_MODE_SETTING2,
RTL_REG_METER_MODE_SETTING3,
RTL_REG_METER32_BUCKET_SIZE,
RTL_REG_METER33_BUCKET_SIZE,
RTL_REG_METER34_BUCKET_SIZE,
RTL_REG_METER35_BUCKET_SIZE,
RTL_REG_METER36_BUCKET_SIZE,
RTL_REG_METER37_BUCKET_SIZE,
RTL_REG_METER38_BUCKET_SIZE,
RTL_REG_METER39_BUCKET_SIZE,
RTL_REG_METER40_BUCKET_SIZE,
RTL_REG_METER41_BUCKET_SIZE,
RTL_REG_METER42_BUCKET_SIZE,
RTL_REG_METER43_BUCKET_SIZE,
RTL_REG_METER44_BUCKET_SIZE,
RTL_REG_METER45_BUCKET_SIZE,
RTL_REG_METER46_BUCKET_SIZE,
RTL_REG_METER47_BUCKET_SIZE,
RTL_REG_METER48_BUCKET_SIZE,
RTL_REG_METER49_BUCKET_SIZE,
RTL_REG_METER50_BUCKET_SIZE,
RTL_REG_METER51_BUCKET_SIZE,
RTL_REG_METER52_BUCKET_SIZE,
RTL_REG_METER53_BUCKET_SIZE,
RTL_REG_METER54_BUCKET_SIZE,
RTL_REG_METER55_BUCKET_SIZE,
RTL_REG_METER56_BUCKET_SIZE,
RTL_REG_METER57_BUCKET_SIZE,
RTL_REG_METER58_BUCKET_SIZE,
RTL_REG_METER59_BUCKET_SIZE,
RTL_REG_METER60_BUCKET_SIZE,
RTL_REG_METER61_BUCKET_SIZE,
RTL_REG_METER62_BUCKET_SIZE,
RTL_REG_METER63_BUCKET_SIZE,
RTL_REG_METER_OVERRATE_INDICATOR2,
RTL_REG_METER_OVERRATE_INDICATOR3,
RTL_REG_METER_OVERRATE_INDICATOR2_8051,
RTL_REG_METER_OVERRATE_INDICATOR3_8051,
RTL_REG_METER_IFG_CTRL2,
RTL_REG_METER_IFG_CTRL3,
RTL_REG_METER_MISC,
RTL_REG_EEELLDP_CTRL0,
RTL_REG_EEELLDP_PMSK,
RTL_REG_EEELLDP_RX_VALUE_P00_08,
RTL_REG_EEELLDP_RX_VALUE_P00_07,
RTL_REG_EEELLDP_RX_VALUE_P00_06,
RTL_REG_EEELLDP_RX_VALUE_P00_05,
RTL_REG_EEELLDP_RX_VALUE_P00_04,
RTL_REG_EEELLDP_RX_VALUE_P00_03,
RTL_REG_EEELLDP_RX_VALUE_P00_02,
RTL_REG_EEELLDP_RX_VALUE_P00_01,
RTL_REG_EEELLDP_RX_VALUE_P00_00,
RTL_REG_EEELLDP_RX_VALUE_P01_08,
RTL_REG_EEELLDP_RX_VALUE_P01_07,
RTL_REG_EEELLDP_RX_VALUE_P01_06,
RTL_REG_EEELLDP_RX_VALUE_P01_05,
RTL_REG_EEELLDP_RX_VALUE_P01_04,
RTL_REG_EEELLDP_RX_VALUE_P01_03,
RTL_REG_EEELLDP_RX_VALUE_P01_02,
RTL_REG_EEELLDP_RX_VALUE_P01_01,
RTL_REG_EEELLDP_RX_VALUE_P01_00,
RTL_REG_EEELLDP_RX_VALUE_P02_08,
RTL_REG_EEELLDP_RX_VALUE_P02_07,
RTL_REG_EEELLDP_RX_VALUE_P02_06,
RTL_REG_EEELLDP_RX_VALUE_P02_05,
RTL_REG_EEELLDP_RX_VALUE_P02_04,
RTL_REG_EEELLDP_RX_VALUE_P02_03,
RTL_REG_EEELLDP_RX_VALUE_P02_02,
RTL_REG_EEELLDP_RX_VALUE_P02_01,
RTL_REG_EEELLDP_RX_VALUE_P02_00,
RTL_REG_EEELLDP_RX_VALUE_P03_08,
RTL_REG_EEELLDP_RX_VALUE_P03_07,
RTL_REG_EEELLDP_RX_VALUE_P03_06,
RTL_REG_EEELLDP_RX_VALUE_P03_05,
RTL_REG_EEELLDP_RX_VALUE_P03_04,
RTL_REG_EEELLDP_RX_VALUE_P03_03,
RTL_REG_EEELLDP_RX_VALUE_P03_02,
RTL_REG_EEELLDP_RX_VALUE_P03_01,
RTL_REG_EEELLDP_RX_VALUE_P03_00,
RTL_REG_EEELLDP_RX_VALUE_P04_08,
RTL_REG_EEELLDP_RX_VALUE_P04_07,
RTL_REG_EEELLDP_RX_VALUE_P04_06,
RTL_REG_EEELLDP_RX_VALUE_P04_05,
RTL_REG_EEELLDP_RX_VALUE_P04_04,
RTL_REG_EEELLDP_RX_VALUE_P04_03,
RTL_REG_EEELLDP_RX_VALUE_P04_02,
RTL_REG_EEELLDP_RX_VALUE_P04_01,
RTL_REG_EEELLDP_RX_VALUE_P04_00,
RTL_REG_EEELLDP_RX_VALUE_P05_08,
RTL_REG_EEELLDP_RX_VALUE_P05_07,
RTL_REG_EEELLDP_RX_VALUE_P05_06,
RTL_REG_EEELLDP_RX_VALUE_P05_05,
RTL_REG_EEELLDP_RX_VALUE_P05_04,
RTL_REG_EEELLDP_RX_VALUE_P05_03,
RTL_REG_EEELLDP_RX_VALUE_P05_02,
RTL_REG_EEELLDP_RX_VALUE_P05_01,
RTL_REG_EEELLDP_RX_VALUE_P05_00,
RTL_REG_EEELLDP_RX_VALUE_P06_08,
RTL_REG_EEELLDP_RX_VALUE_P06_07,
RTL_REG_EEELLDP_RX_VALUE_P06_06,
RTL_REG_EEELLDP_RX_VALUE_P06_05,
RTL_REG_EEELLDP_RX_VALUE_P06_04,
RTL_REG_EEELLDP_RX_VALUE_P06_03,
RTL_REG_EEELLDP_RX_VALUE_P06_02,
RTL_REG_EEELLDP_RX_VALUE_P06_01,
RTL_REG_EEELLDP_RX_VALUE_P06_00,
RTL_REG_EEELLDP_RX_VALUE_P07_08,
RTL_REG_EEELLDP_RX_VALUE_P07_07,
RTL_REG_EEELLDP_RX_VALUE_P07_06,
RTL_REG_EEELLDP_RX_VALUE_P07_05,
RTL_REG_EEELLDP_RX_VALUE_P07_04,
RTL_REG_EEELLDP_RX_VALUE_P07_03,
RTL_REG_EEELLDP_RX_VALUE_P07_02,
RTL_REG_EEELLDP_RX_VALUE_P07_01,
RTL_REG_EEELLDP_RX_VALUE_P07_00,
RTL_REG_EEELLDP_RX_VALUE_P08_08,
RTL_REG_EEELLDP_RX_VALUE_P08_07,
RTL_REG_EEELLDP_RX_VALUE_P08_06,
RTL_REG_EEELLDP_RX_VALUE_P08_05,
RTL_REG_EEELLDP_RX_VALUE_P08_04,
RTL_REG_EEELLDP_RX_VALUE_P08_03,
RTL_REG_EEELLDP_RX_VALUE_P08_02,
RTL_REG_EEELLDP_RX_VALUE_P08_01,
RTL_REG_EEELLDP_RX_VALUE_P08_00,
RTL_REG_EEELLDP_RX_VALUE_P09_08,
RTL_REG_EEELLDP_RX_VALUE_P09_07,
RTL_REG_EEELLDP_RX_VALUE_P09_06,
RTL_REG_EEELLDP_RX_VALUE_P09_05,
RTL_REG_EEELLDP_RX_VALUE_P09_04,
RTL_REG_EEELLDP_RX_VALUE_P09_03,
RTL_REG_EEELLDP_RX_VALUE_P09_02,
RTL_REG_EEELLDP_RX_VALUE_P09_01,
RTL_REG_EEELLDP_RX_VALUE_P09_00,
RTL_REG_EEELLDP_RX_VALUE_P10_08,
RTL_REG_EEELLDP_RX_VALUE_P10_07,
RTL_REG_EEELLDP_RX_VALUE_P10_06,
RTL_REG_EEELLDP_RX_VALUE_P10_05,
RTL_REG_EEELLDP_RX_VALUE_P10_04,
RTL_REG_EEELLDP_RX_VALUE_P10_03,
RTL_REG_EEELLDP_RX_VALUE_P10_02,
RTL_REG_EEELLDP_RX_VALUE_P10_01,
RTL_REG_EEELLDP_RX_VALUE_P10_00,
RTL_REG_RLDP_CTRL0,
RTL_REG_RLDP_CTRL1,
RTL_REG_RLDP_CTRL2,
RTL_REG_RLDP_CTRL3,
RTL_REG_RLDP_CTRL4,
RTL_REG_RLDP_RAND_NUM0,
RTL_REG_RLDP_RAND_NUM1,
RTL_REG_RLDP_RAND_NUM2,
RTL_REG_RLDP_MAGIC_NUM0,
RTL_REG_RLDP_MAGIC_NUM1,
RTL_REG_RLDP_MAGIC_NUM2,
RTL_REG_RLDP_LOOPED_INDICATOR,
RTL_REG_RLDP_LOOP_PORT_REG0,
RTL_REG_RLDP_LOOP_PORT_REG1,
RTL_REG_RLDP_LOOP_PORT_REG2,
RTL_REG_RLDP_LOOP_PORT_REG3,
RTL_REG_RLDP_RELEASED_INDICATOR,
RTL_REG_RLDP_LOOPSTATUS_INDICATOR,
RTL_REG_RLDP_LOOP_PORT_REG4,
RTL_REG_RLDP_LOOP_PORT_REG5,
RTL_REG_RLDP_CTRL5,
RTL_REG_EEE_500M_CTRL0,
RTL_REG_EEE_RXIDLE_GIGA_CTRL,
RTL_REG_EEE_RXIDLE_500M_CTRL,
RTL_REG_EEE_DECISION_GIGA_500M,
RTL_REG_EEE_DECISION_100M,
RTL_REG_EEEP_DEFER_TXLPI,
RTL_REG_EEEP_EN,
RTL_REG_EEEP_TI_GIGA_500M,
RTL_REG_EEEP_TI_100M,
RTL_REG_EEEP_CTRL2,
RTL_REG_EEEP_RX_RATE_500M,
RTL_REG_EEEP_RW_GIGA_SLV,
RTL_REG_EEEP_TMR_GIGA,
RTL_REG_EEEP_TMR_500M,
RTL_REG_EEEP_TMR_100M,
RTL_REG_EEEP_RW_500M_MST_SLV,
RTL_REG_EEEP_500M_CTRL0,
RTL_REG_EEEP_500M_CTRL1,
RTL_REG_EEEP_500M_CTRL2,
RTL_REG_EEE_NEW_CTRL0,
RTL_REG_EEE_LONGIDLE_100M,
RTL_REG_EEE_LONGIDLE_500M,
RTL_REG_EEE_LONGIDLE_GIGA,
RTL_REG_EEE_MINIPG_100M,
RTL_REG_EEE_MINIPG_500M,
RTL_REG_EEE_MINIPG_GIGA,
RTL_REG_EEE_LONGIDLE_CTRL0,
RTL_REG_EEE_LONGIDLE_CTRL1,
RTL_REG_EEE_TD_CTRL_H,
RTL_REG_NIC_RXRDRL,
RTL_REG_NIC_RXRDRH,
RTL_REG_NIC_TXASRL,
RTL_REG_NIC_TXASRH,
RTL_REG_NIC_RXCMDR,
RTL_REG_NIC_TXCMDR,
RTL_REG_NIC_IMS,
RTL_REG_NIC_IMR,
RTL_REG_NIC_RXCR0,
RTL_REG_NIC_RXCR1,
RTL_REG_NIC_TXCR,
RTL_REG_NIC_GCR,
RTL_REG_NIC_MHR0,
RTL_REG_NIC_MHR1,
RTL_REG_NIC_MHR2,
RTL_REG_NIC_MHR3,
RTL_REG_NIC_MHR4,
RTL_REG_NIC_MHR5,
RTL_REG_NIC_MHR6,
RTL_REG_NIC_MHR7,
RTL_REG_NIC_PAHR0,
RTL_REG_NIC_PAHR1,
RTL_REG_NIC_PAHR2,
RTL_REG_NIC_PAHR3,
RTL_REG_NIC_PAHR4,
RTL_REG_NIC_PAHR5,
RTL_REG_NIC_PAHR6,
RTL_REG_NIC_PAHR7,
RTL_REG_NIC_TXSTOPRL,
RTL_REG_NIC_TXSTOPRH,
RTL_REG_NIC_RXSTOPRL,
RTL_REG_NIC_RXSTOPRH,
RTL_REG_NIC_RXFSTR,
RTL_REG_NIC_RXMBTRL,
RTL_REG_NIC_RXMBTRH,
RTL_REG_NIC_RXMPTR,
RTL_REG_NIC_T0TR,
RTL_REG_NIC_CRXCPRL,
RTL_REG_NIC_CRXCPRH,
RTL_REG_NIC_CTXCPRL,
RTL_REG_NIC_CTXPCRH,
RTL_REG_NIC_SRXCURPKTRL,
RTL_REG_NIC_SRXCURPKTRH,
RTL_REG_NIC_STXCURPKTRL,
RTL_REG_NIC_STXCURPKTRH,
RTL_REG_NIC_STXPKTLENRL,
RTL_REG_NIC_STXPKTLENRH,
RTL_REG_NIC_STXCURUNITRL,
RTL_REG_NIC_STXCURUNITRH,
RTL_REG_NIC_DROP_MODE,
RTL_REG_LED_SYS_CONFIG,
RTL_REG_LED_SYS_CONFIG2,
RTL_REG_LED_MODE,
RTL_REG_LED_CONFIGURATION,
RTL_REG_RTCT_RESULTS_CFG,
RTL_REG_RTCT_LED,
RTL_REG_CPU_FORCE_LED_CFG,
RTL_REG_CPU_FORCE_LED0_CFG0,
RTL_REG_CPU_FORCE_LED0_CFG1,
RTL_REG_CPU_FORCE_LED1_CFG0,
RTL_REG_CPU_FORCE_LED1_CFG1,
RTL_REG_CPU_FORCE_LED2_CFG0,
RTL_REG_CPU_FORCE_LED2_CFG1,
RTL_REG_LED_ACTIVE_LOW_CFG0,
RTL_REG_LED_ACTIVE_LOW_CFG1,
RTL_REG_LED_ACTIVE_LOW_CFG2,
RTL_REG_SEL_RTCT_PARA,
RTL_REG_RTCT_ENABLE,
RTL_REG_RTCT_TIMEOUT,
RTL_REG_PARA_LED_IO_EN1,
RTL_REG_PARA_LED_IO_EN2,
RTL_REG_SCAN0_LED_IO_EN1,
RTL_REG_SCAN1_LED_IO_EN2,
RTL_REG_LPI_LED_OPT1,
RTL_REG_LPI_LED_OPT2,
RTL_REG_LPI_LED_OPT3,
RTL_REG_P0_LED_MUX,
RTL_REG_P1_LED_MUX,
RTL_REG_P2_LED_MUX,
RTL_REG_P3_LED_MUX,
RTL_REG_P4_LED_MUX,
RTL_REG_LED0_DATA_CTRL,
RTL_REG_LED1_DATA_CTRL,
RTL_REG_LED2_DATA_CTRL,
RTL_REG_PARA_LED_IO_EN3,
RTL_REG_SCAN1_LED_IO_EN3,
RTL_REG_P5_LED_MUX,
RTL_REG_P6_LED_MUX,
RTL_REG_P7_LED_MUX,
RTL_REG_P8_LED_MUX,
RTL_REG_P9_LED_MUX,
RTL_REG_SERIAL_LED_CTRL,
RTL_REG_IGMP_MLD_CFG0,
RTL_REG_IGMP_MLD_CFG1,
RTL_REG_IGMP_MLD_CFG2,
RTL_REG_IGMP_DYNAMIC_ROUTER_PORT,
RTL_REG_IGMP_STATIC_ROUTER_PORT,
RTL_REG_IGMP_PORT0_CONTROL,
RTL_REG_IGMP_PORT1_CONTROL,
RTL_REG_IGMP_PORT2_CONTROL,
RTL_REG_IGMP_PORT3_CONTROL,
RTL_REG_IGMP_PORT4_CONTROL,
RTL_REG_IGMP_PORT5_CONTROL,
RTL_REG_IGMP_PORT6_CONTROL,
RTL_REG_IGMP_PORT7_CONTROL,
RTL_REG_IGMP_PORT01_MAX_GROUP,
RTL_REG_IGMP_PORT23_MAX_GROUP,
RTL_REG_IGMP_PORT45_MAX_GROUP,
RTL_REG_IGMP_PORT67_MAX_GROUP,
RTL_REG_IGMP_PORT01_CURRENT_GROUP,
RTL_REG_IGMP_PORT23_CURRENT_GROUP,
RTL_REG_IGMP_PORT45_CURRENT_GROUP,
RTL_REG_IGMP_PORT67_CURRENT_GROUP,
RTL_REG_IGMP_MLD_CFG3,
RTL_REG_IGMP_MLD_CFG4,
RTL_REG_IGMP_GROUP_USAGE_LIST0,
RTL_REG_IGMP_GROUP_USAGE_LIST1,
RTL_REG_IGMP_GROUP_USAGE_LIST2,
RTL_REG_IGMP_GROUP_USAGE_LIST3,
RTL_REG_IGMP_GROUP_USAGE_LIST4,
RTL_REG_IGMP_GROUP_USAGE_LIST5,
RTL_REG_IGMP_GROUP_USAGE_LIST6,
RTL_REG_IGMP_GROUP_USAGE_LIST7,
RTL_REG_IGMP_GROUP_USAGE_LIST8,
RTL_REG_IGMP_GROUP_USAGE_LIST9,
RTL_REG_IGMP_GROUP_USAGE_LIST10,
RTL_REG_IGMP_GROUP_USAGE_LIST11,
RTL_REG_IGMP_GROUP_USAGE_LIST12,
RTL_REG_IGMP_GROUP_USAGE_LIST13,
RTL_REG_IGMP_GROUP_USAGE_LIST14,
RTL_REG_IGMP_GROUP_USAGE_LIST15,
RTL_REG_EAV_CTRL0,
RTL_REG_EAV_CTRL1,
RTL_REG_EAV_CTRL2,
RTL_REG_SYS_TIME_FREQ,
RTL_REG_SYS_TIME_OFFSET_L,
RTL_REG_SYS_TIME_OFFSET_H,
RTL_REG_SYS_TIME_OFFSET_512NS_L,
RTL_REG_SYS_TIME_OFFSET_512NS_H,
RTL_REG_SYS_TIME_SEC_TRANSIT,
RTL_REG_SYS_TIME_SEC_HIGH_L,
RTL_REG_SYS_TIME_SEC_HIGH_H,
RTL_REG_SYS_TIME_512NS_L,
RTL_REG_SYS_TIME_512NS_H,
RTL_REG_FALLBACK_CTRL,
RTL_REG_FALLBACK_PORT0_CFG0,
RTL_REG_FALLBACK_PORT0_CFG1,
RTL_REG_FALLBACK_PORT0_CFG2,
RTL_REG_FALLBACK_PORT0_CFG3,
RTL_REG_FALLBACK_PORT1_CFG0,
RTL_REG_FALLBACK_PORT1_CFG1,
RTL_REG_FALLBACK_PORT1_CFG2,
RTL_REG_FALLBACK_PORT1_CFG3,
RTL_REG_FALLBACK_PORT2_CFG0,
RTL_REG_FALLBACK_PORT2_CFG1,
RTL_REG_FALLBACK_PORT2_CFG2,
RTL_REG_FALLBACK_PORT2_CFG3,
RTL_REG_FALLBACK_PORT3_CFG0,
RTL_REG_FALLBACK_PORT3_CFG1,
RTL_REG_FALLBACK_PORT3_CFG2,
RTL_REG_FALLBACK_PORT3_CFG3,
RTL_REG_FALLBACK_PORT4_CFG0,
RTL_REG_FALLBACK_PORT4_CFG1,
RTL_REG_FALLBACK_PORT4_CFG2,
RTL_REG_FALLBACK_PORT4_CFG3,
RTL_REG_FALLBACK_CTRL1,
RTL_REG_FALLBACK_CPL,
RTL_REG_FALLBACK_PHY_PAGE,
RTL_REG_FALLBACK_PHY_REG,
RTL_REG_AFBK_INFO_X0,
RTL_REG_AFBK_INFO_X1,
RTL_REG_AFBK_INFO_X2,
RTL_REG_AFBK_INFO_X3,
RTL_REG_AFBK_INFO_X4,
RTL_REG_AFBK_INFO_X5,
RTL_REG_AFBK_INFO_X6,
RTL_REG_AFBK_INFO_X7,
RTL_REG_AFBK_INFO_X8,
RTL_REG_AFBK_INFO_X9,
RTL_REG_AFBK_INFO_X10,
RTL_REG_AFBK_INFO_X11,
RTL_REG_FALLBACK_PORT5_CFG0,
RTL_REG_FALLBACK_PORT5_CFG1,
RTL_REG_FALLBACK_PORT5_CFG2,
RTL_REG_FALLBACK_PORT5_CFG3,
RTL_REG_FALLBACK_PORT6_CFG0,
RTL_REG_FALLBACK_PORT6_CFG1,
RTL_REG_FALLBACK_PORT6_CFG2,
RTL_REG_FALLBACK_PORT6_CFG3,
RTL_REG_FALLBACK_PORT7_CFG0,
RTL_REG_FALLBACK_PORT7_CFG1,
RTL_REG_FALLBACK_PORT7_CFG2,
RTL_REG_FALLBACK_PORT7_CFG3,
RTL_REG_IGMP_PORT8_CONTROL,
RTL_REG_IGMP_PORT9_CONTROL,
RTL_REG_IGMP_PORT10_CONTROL,
RTL_REG_IGMP_PORT89_MAX_GROUP,
RTL_REG_IGMP_PORT10_MAX_GROUP,
RTL_REG_IGMP_PORT89_CURRENT_GROUP,
RTL_REG_IGMP_PORT10_CURRENT_GROUP,
RTL_REG_IGMP_L3_CHECKSUM_CHECK,
RTL_REG_PCSXF_CFG,
RTL_REG_PHYID_CFG0,
RTL_REG_PHYID_CFG1,
RTL_REG_PHY_POLL_CFG0,
RTL_REG_PHY_POLL_CFG1,
RTL_REG_PHY_POLL_CFG2,
RTL_REG_PHY_POLL_CFG3,
RTL_REG_PHY_POLL_CFG4,
RTL_REG_PHY_POLL_CFG5,
RTL_REG_PHY_POLL_CFG6,
RTL_REG_PHY_POLL_CFG7,
RTL_REG_PHY_POLL_CFG8,
RTL_REG_PHY_POLL_CFG9,
RTL_REG_PHY_POLL_CFG10,
RTL_REG_PHY_POLL_CFG11,
RTL_REG_PHY_POLL_CFG12,
RTL_REG_SDS_MISC,
RTL_REG_FIFO_CTRL,
RTL_REG_BCAM_SETTING,
RTL_REG_GPHY_ACS_MISC,
RTL_REG_GPHY_OCP_MSB_0,
RTL_REG_GPHY_OCP_MSB_1,
RTL_REG_GPHY_OCP_MSB_2,
RTL_REG_GPHY_OCP_MSB_3,
RTL_REG_GPIO_67C_I_X0,
RTL_REG_GPIO_67C_I_X1,
RTL_REG_GPIO_67C_I_X2,
RTL_REG_GPIO_67C_I_X3,
RTL_REG_GPIO_67C_O_X0,
RTL_REG_GPIO_67C_O_X1,
RTL_REG_GPIO_67C_O_X2,
RTL_REG_GPIO_67C_O_X3,
RTL_REG_GPIO_67C_OE_X0,
RTL_REG_GPIO_67C_OE_X1,
RTL_REG_GPIO_67C_OE_X2,
RTL_REG_GPIO_67C_OE_X3,
RTL_REG_GPIO_MODE_67C_X0,
RTL_REG_GPIO_MODE_67C_X1,
RTL_REG_GPIO_MODE_67C_X2,
RTL_REG_GPIO_MODE_67C_X3,
RTL_REG_WGPHY_MISC_0,
RTL_REG_WGPHY_MISC_1,
RTL_REG_WGPHY_MISC_2,
RTL_REG_CFG_AFBK_GPHY_0,
RTL_REG_CFG_AFBK_GPHY_1,
RTL_REG_EF_SLV_CTRL_0,
RTL_REG_EF_SLV_CTRL_1,
RTL_REG_EF_SLV_CTRL_2,
RTL_REG_IO_MISC_FUNC,
RTL_REG_HTRAM_DVS,
RTL_REG_EF_SLV_CTRL_3,
RTL_REG_INBAND_EN14C,
RTL_REG_CFG_SWR_L,
RTL_REG_BTCAM_CTRL,
RTL_REG_PBRAM_BISR_CTRL,
RTL_REG_CVLANRAM_BISR_CTRL,
RTL_REG_CFG_1588_TIMER_EN_GPI,
RTL_REG_MDIO_PRMB_SUPP,
RTL_REG_BOND4READ,
RTL_REG_REG_TO_ECO0,
RTL_REG_REG_TO_ECO1,
RTL_REG_REG_TO_ECO2,
RTL_REG_REG_TO_ECO3,
RTL_REG_REG_TO_ECO4,
RTL_REG_PHYSTS_CTRL0,
RTL_REG_SSC_CTRL0_0,
RTL_REG_SSC_RDM_SEED,
RTL_REG_SSC_PN_POLY_SEL,
RTL_REG_SSC_CTRL0_3,
RTL_REG_SSC_CTRL0_4,
RTL_REG_SSC_CTRL0_5,
RTL_REG_SSC_STS0,
RTL_REG_SSC_CTRL1_0,
RTL_REG_SSC_RDM_SEED1,
RTL_REG_SSC_PN_POLY_SEL1,
RTL_REG_SSC_CTRL1_3,
RTL_REG_SSC_CTRL1_4,
RTL_REG_SSC_CTRL1_5,
RTL_REG_SSC_STS1,
RTL_REG_SSC_CTRL2_0,
RTL_REG_SSC_RDM_SEED2,
RTL_REG_SSC_PN_POLY_SEL2,
RTL_REG_SSC_CTRL2_3,
RTL_REG_SSC_CTRL2_4,
RTL_REG_SSC_CTRL2_5,
RTL_REG_SSC_STS2,
RTL_REG_SSC_CTRL3_0,
RTL_REG_SSC_RDM_SEED3,
RTL_REG_SSC_PN_POLY_SEL3,
RTL_REG_SSC_CTRL3_3,
RTL_REG_SSC_CTRL3_4,
RTL_REG_SSC_CTRL3_5,
RTL_REG_SSC_STS3,
RTL_REG_PHY_POLL_CFG13,
RTL_REG_PHY_POLL_CFG14,
RTL_REG_FRC_SYS_CLK,
RTL_REG_AFE_SSC_CTRL,
RTL_REG_BUFF_RST_CTRL0,
RTL_REG_BUFF_RST_CTRL1,
RTL_REG_BUFF_RST_CTRL2,
RTL_REG_BUFF_RST_CTRL3,
RTL_REG_BUFF_RST_CTRL4,
RTL_REG_BUFF_RST_CTRL5,
RTL_REG_TOP_CON0,
RTL_REG_TOP_CON1,
RTL_REG_SWR_FPWM,
RTL_REG_EEEP_CTRL_500M,
RTL_REG_SHORT_PRMB,
RTL_REG_INDSC_THR_CTRL,
RTL_REG_SET_PAD_CTRL_NEW,
RTL_REG_SET_PAD_DRI_0,
RTL_REG_SET_PAD_DRI_1,
RTL_REG_SET_PAD_DRI_2,
RTL_REG_SET_PAD_SLEW_0,
RTL_REG_SET_PAD_SLEW_1,
RTL_REG_SET_PAD_SLEW_2,
RTL_REG_SET_PAD_SMT_0,
RTL_REG_SET_PAD_SMT_1,
RTL_REG_SET_PAD_SMT_2,
RTL_REG_M_I2C_CTL_STA_REG,
RTL_REG_M_I2C_DUMB_RW_ADDR_0,
RTL_REG_M_I2C_DUMB_RW_ADDR_1,
RTL_REG_M_I2C_DUMB_RW_DATA_0,
RTL_REG_M_I2C_DUMB_RW_DATA_1,
RTL_REG_M_I2C_DUMB_RW_CTL,
RTL_REG_M_I2C_SYS_CTL,
RTL_REG_HT_PB_SRAM_CTRL,
RTL_REG_HT_PB_SRAM_ADDR,
RTL_REG_HT_PB_SRAM_DIN0,
RTL_REG_HT_PB_SRAM_DIN1,
RTL_REG_HT_PB_SRAM_DOUT0,
RTL_REG_HT_PB_SRAM_DOUT1,
RTL_REG_PHY_STAT_0,
RTL_REG_PHY_STAT_1,
RTL_REG_PHY_STAT_2,
RTL_REG_PHY_STAT_3,
RTL_REG_PHY_STAT_4,
RTL_REG_PHY_STAT_5,
RTL_REG_PHY_STAT_6,
RTL_REG_PHY_STAT_7,
RTL_REG_SDS_STAT_0,
RTL_REG_SDS_STAT_1,
RTL_REG_MAC_LINK_STAT_0,
RTL_REG_MAC_LINK_STAT_1,
RTL_REG_MISC_CONTROL_1,
RTL_REG_SDS_MISC_1,
RTL_REG_FIBER_CFG_2_1,
RTL_REG_FIBER_CFG_1_1,
RTL_REG_PHYSTS_CTRL0_1,
RTL_REG_FIBER_CFG_3_1,
RTL_REG_FIBER_CFG_4_1,
RTL_REG_BUFF_RST_CTRL2_2,
RTL_REG_PHY_DEBUG_CNT_CTRL,
RTL_REG_TXPKT_CNT_L_0,
RTL_REG_TXPKT_CNT_H_0,
RTL_REG_RXPKT_CNT_L_0,
RTL_REG_RXPKT_CNT_H_0,
RTL_REG_TX_CRC_0,
RTL_REG_RX_CRC_0,
RTL_REG_TXPKT_CNT_L_1,
RTL_REG_TXPKT_CNT_H_1,
RTL_REG_RXPKT_CNT_L_1,
RTL_REG_RXPKT_CNT_H_1,
RTL_REG_TX_CRC_1,
RTL_REG_RX_CRC_1,
RTL_REG_TXPKT_CNT_L_2,
RTL_REG_TXPKT_CNT_H_2,
RTL_REG_RXPKT_CNT_L_2,
RTL_REG_RXPKT_CNT_H_2,
RTL_REG_TX_CRC_2,
RTL_REG_RX_CRC_2,
RTL_REG_TXPKT_CNT_L_3,
RTL_REG_TXPKT_CNT_H_3,
RTL_REG_RXPKT_CNT_L_3,
RTL_REG_RXPKT_CNT_H_3,
RTL_REG_TX_CRC_3,
RTL_REG_RX_CRC_3,
RTL_REG_TXPKT_CNT_L_4,
RTL_REG_TXPKT_CNT_H_4,
RTL_REG_RXPKT_CNT_L_4,
RTL_REG_RXPKT_CNT_H_4,
RTL_REG_TX_CRC_4,
RTL_REG_RX_CRC_4,
RTL_REG_TXPKT_CNT_L_5,
RTL_REG_TXPKT_CNT_H_5,
RTL_REG_RXPKT_CNT_L_5,
RTL_REG_RXPKT_CNT_H_5,
RTL_REG_TX_CRC_5,
RTL_REG_RX_CRC_5,
RTL_REG_TXPKT_CNT_L_6,
RTL_REG_TXPKT_CNT_H_6,
RTL_REG_RXPKT_CNT_L_6,
RTL_REG_RXPKT_CNT_H_6,
RTL_REG_TX_CRC_6,
RTL_REG_RX_CRC_6,
RTL_REG_TXPKT_CNT_L_7,
RTL_REG_TXPKT_CNT_H_7,
RTL_REG_RXPKT_CNT_L_7,
RTL_REG_RXPKT_CNT_H_7,
RTL_REG_TX_CRC_7,
RTL_REG_RX_CRC_7,
RTL_REG_BOND_DBG_0,
RTL_REG_BOND_DBG_1,
RTL_REG_STRP_DBG_0,
RTL_REG_STRP_DBG_1,
RTL_REG_STRP_DBG_2,
RTL_REG_FIB0_CFG00,
RTL_REG_FIB0_CFG01,
RTL_REG_FIB0_CFG02,
RTL_REG_FIB0_CFG03,
RTL_REG_FIB0_CFG04,
RTL_REG_FIB0_CFG05,
RTL_REG_FIB0_CFG06,
RTL_REG_FIB0_CFG07,
RTL_REG_FIB0_CFG08,
RTL_REG_FIB0_CFG09,
RTL_REG_FIB0_CFG10,
RTL_REG_FIB0_CFG11,
RTL_REG_FIB0_CFG12,
RTL_REG_FIB0_CFG13,
RTL_REG_FIB0_CFG14,
RTL_REG_FIB0_CFG15,
RTL_REG_FIB1_CFG00,
RTL_REG_FIB1_CFG01,
RTL_REG_FIB1_CFG02,
RTL_REG_FIB1_CFG03,
RTL_REG_FIB1_CFG04,
RTL_REG_FIB1_CFG05,
RTL_REG_FIB1_CFG06,
RTL_REG_FIB1_CFG07,
RTL_REG_FIB1_CFG08,
RTL_REG_FIB1_CFG09,
RTL_REG_FIB1_CFG10,
RTL_REG_FIB1_CFG11,
RTL_REG_FIB1_CFG12,
RTL_REG_FIB1_CFG13,
RTL_REG_FIB1_CFG14,
RTL_REG_FIB1_CFG15,
RTL_REG_PTP_TIME_NSEC_L_NSEC,
RTL_REG_PTP_TIME_NSEC_H_NSEC,
RTL_REG_PTP_TIME_SEC_L_SEC,
RTL_REG_PTP_TIME_SEC_H_SEC,
RTL_REG_PTP_TIME_CFG,
RTL_REG_OTAG_TPID,
RTL_REG_ITAG_TPID,
RTL_REG_MAC_ADDR_L,
RTL_REG_MAC_ADDR_M,
RTL_REG_MAC_ADDR_H,
RTL_REG_PTP_TIME_NSEC_L_NSEC_RD,
RTL_REG_PTP_TIME_NSEC_H_NSEC_RD,
RTL_REG_PTP_TIME_SEC_L_SEC_RD,
RTL_REG_PTP_TIME_SEC_H_SEC_RD,
RTL_REG_PTP_TIME_CFG2,
RTL_REG_PTP_INTERRUPT_CFG,
RTL_REG_P0_TX_SYNC_SEQ_ID,
RTL_REG_P0_TX_DELAY_REQ_SEQ_ID,
RTL_REG_P0_TX_PDELAY_REQ_SEQ_ID,
RTL_REG_P0_TX_PDELAY_RESP_SEQ_ID,
RTL_REG_P0_RX_SYNC_SEQ_ID,
RTL_REG_P0_RX_DELAY_REQ_SEQ_ID,
RTL_REG_P0_RX_PDELAY_REQ_SEQ_ID,
RTL_REG_P0_RX_PDELAY_RESP_SEQ_ID,
RTL_REG_P0_PORT_NSEC_15_0,
RTL_REG_P0_PORT_NSEC_26_16,
RTL_REG_P0_PORT_SEC_15_0,
RTL_REG_P0_PORT_SEC_31_16,
RTL_REG_P0_EAV_CFG,
RTL_REG_P1_TX_SYNC_SEQ_ID,
RTL_REG_P1_TX_DELAY_REQ_SEQ_ID,
RTL_REG_P1_TX_PDELAY_REQ_SEQ_ID,
RTL_REG_P1_TX_PDELAY_RESP_SEQ_ID,
RTL_REG_P1_RX_SYNC_SEQ_ID,
RTL_REG_P1_RX_DELAY_REQ_SEQ_ID,
RTL_REG_P1_RX_PDELAY_REQ_SEQ_ID,
RTL_REG_P1_RX_PDELAY_RESP_SEQ_ID,
RTL_REG_P1_PORT_NSEC_15_0,
RTL_REG_P1_PORT_NSEC_26_16,
RTL_REG_P1_PORT_SEC_15_0,
RTL_REG_P1_PORT_SEC_31_16,
RTL_REG_P1_EAV_CFG,
RTL_REG_P2_TX_SYNC_SEQ_ID,
RTL_REG_P2_TX_DELAY_REQ_SEQ_ID,
RTL_REG_P2_TX_PDELAY_REQ_SEQ_ID,
RTL_REG_P2_TX_PDELAY_RESP_SEQ_ID,
RTL_REG_P2_RX_SYNC_SEQ_ID,
RTL_REG_P2_RX_DELAY_REQ_SEQ_ID,
RTL_REG_P2_RX_PDELAY_REQ_SEQ_ID,
RTL_REG_P2_RX_PDELAY_RESP_SEQ_ID,
RTL_REG_P2_PORT_NSEC_15_0,
RTL_REG_P2_PORT_NSEC_26_16,
RTL_REG_P2_PORT_SEC_15_0,
RTL_REG_P2_PORT_SEC_31_16,
RTL_REG_P2_EAV_CFG,
RTL_REG_P3_TX_SYNC_SEQ_ID,
RTL_REG_P3_TX_DELAY_REQ_SEQ_ID,
RTL_REG_P3_TX_PDELAY_REQ_SEQ_ID,
RTL_REG_P3_TX_PDELAY_RESP_SEQ_ID,
RTL_REG_P3_RX_SYNC_SEQ_ID,
RTL_REG_P3_RX_DELAY_REQ_SEQ_ID,
RTL_REG_P3_RX_PDELAY_REQ_SEQ_ID,
RTL_REG_P3_RX_PDELAY_RESP_SEQ_ID,
RTL_REG_P3_PORT_NSEC_15_0,
RTL_REG_P3_PORT_NSEC_26_16,
RTL_REG_P3_PORT_SEC_15_0,
RTL_REG_P3_PORT_SEC_31_16,
RTL_REG_P3_EAV_CFG,
RTL_REG_P4_TX_SYNC_SEQ_ID,
RTL_REG_P4_TX_DELAY_REQ_SEQ_ID,
RTL_REG_P4_TX_PDELAY_REQ_SEQ_ID,
RTL_REG_P4_TX_PDELAY_RESP_SEQ_ID,
RTL_REG_P4_RX_SYNC_SEQ_ID,
RTL_REG_P4_RX_DELAY_REQ_SEQ_ID,
RTL_REG_P4_RX_PDELAY_REQ_SEQ_ID,
RTL_REG_P4_RX_PDELAY_RESP_SEQ_ID,
RTL_REG_P4_PORT_NSEC_15_0,
RTL_REG_P4_PORT_NSEC_26_16,
RTL_REG_P4_PORT_SEC_15_0,
RTL_REG_P4_PORT_SEC_31_16,
RTL_REG_P4_EAV_CFG,
RTL_REG_P6_TX_SYNC_SEQ_ID,
RTL_REG_P6_TX_DELAY_REQ_SEQ_ID,
RTL_REG_P6_TX_PDELAY_REQ_SEQ_ID,
RTL_REG_P6_TX_PDELAY_RESP_SEQ_ID,
RTL_REG_P6_RX_SYNC_SEQ_ID,
RTL_REG_P6_RX_DELAY_REQ_SEQ_ID,
RTL_REG_P6_RX_PDELAY_REQ_SEQ_ID,
RTL_REG_P6_RX_PDELAY_RESP_SEQ_ID,
RTL_REG_P6_PORT_NSEC_15_0,
RTL_REG_P6_PORT_NSEC_26_16,
RTL_REG_P6_PORT_SEC_15_0,
RTL_REG_P6_PORT_SEC_31_16,
RTL_REG_P6_EAV_CFG,
RTL_REG_P7_TX_SYNC_SEQ_ID,
RTL_REG_P7_TX_DELAY_REQ_SEQ_ID,
RTL_REG_P7_TX_PDELAY_REQ_SEQ_ID,
RTL_REG_P7_TX_PDELAY_RESP_SEQ_ID,
RTL_REG_P7_RX_SYNC_SEQ_ID,
RTL_REG_P7_RX_DELAY_REQ_SEQ_ID,
RTL_REG_P7_RX_PDELAY_REQ_SEQ_ID,
RTL_REG_P7_RX_PDELAY_RESP_SEQ_ID,
RTL_REG_P7_PORT_NSEC_15_0,
RTL_REG_P7_PORT_NSEC_26_16,
RTL_REG_P7_PORT_SEC_15_0,
RTL_REG_P7_PORT_SEC_31_16,
RTL_REG_P7_EAV_CFG,
RTL_REG_P5_TX_SYNC_SEQ_ID,
RTL_REG_P5_TX_DELAY_REQ_SEQ_ID,
RTL_REG_P5_TX_PDELAY_REQ_SEQ_ID,
RTL_REG_P5_TX_PDELAY_RESP_SEQ_ID,
RTL_REG_P5_RX_SYNC_SEQ_ID,
RTL_REG_P5_RX_DELAY_REQ_SEQ_ID,
RTL_REG_P5_RX_PDELAY_REQ_SEQ_ID,
RTL_REG_P5_RX_PDELAY_RESP_SEQ_ID,
RTL_REG_P5_PORT_NSEC_15_0,
RTL_REG_P5_PORT_NSEC_26_16,
RTL_REG_P5_PORT_SEC_15_0,
RTL_REG_P5_PORT_SEC_31_16,
RTL_REG_P5_EAV_CFG,
RTL_REG_P8_TX_SYNC_SEQ_ID,
RTL_REG_P8_TX_DELAY_REQ_SEQ_ID,
RTL_REG_P8_TX_PDELAY_REQ_SEQ_ID,
RTL_REG_P8_TX_PDELAY_RESP_SEQ_ID,
RTL_REG_P8_RX_SYNC_SEQ_ID,
RTL_REG_P8_RX_DELAY_REQ_SEQ_ID,
RTL_REG_P8_RX_PDELAY_REQ_SEQ_ID,
RTL_REG_P8_RX_PDELAY_RESP_SEQ_ID,
RTL_REG_P8_PORT_NSEC_15_0,
RTL_REG_P8_PORT_NSEC_26_16,
RTL_REG_P8_PORT_SEC_15_0,
RTL_REG_P8_PORT_SEC_31_16,
RTL_REG_P8_EAV_CFG,
RTL_REG_P9_TX_SYNC_SEQ_ID,
RTL_REG_P9_TX_DELAY_REQ_SEQ_ID,
RTL_REG_P9_TX_PDELAY_REQ_SEQ_ID,
RTL_REG_P9_TX_PDELAY_RESP_SEQ_ID,
RTL_REG_P9_RX_SYNC_SEQ_ID,
RTL_REG_P9_RX_DELAY_REQ_SEQ_ID,
RTL_REG_P9_RX_PDELAY_REQ_SEQ_ID,
RTL_REG_P9_RX_PDELAY_RESP_SEQ_ID,
RTL_REG_P9_PORT_NSEC_15_0,
RTL_REG_P9_PORT_NSEC_26_16,
RTL_REG_P9_PORT_SEC_15_0,
RTL_REG_P9_PORT_SEC_31_16,
RTL_REG_P9_EAV_CFG,
RTL_REG_SDS_INDACS_CMD,
RTL_REG_SDS_INDACS_ADR,
RTL_REG_SDS_INDACS_DATA,
RTL_REG_END,
};

#define MAKE_REG(_name, _addr) \
		[RTL_REG_ ## _name] = { _addr, #_name }

static struct rtl_reg rtl_regs[] = {
MAKE_REG(PORT0_CGST_HALF_CFG, 0x0000),
MAKE_REG(TX_ERR_CNT_PORT0, 0x0002),
MAKE_REG(PORT0_MISC_CFG, 0x000e),
MAKE_REG(INGRESSBW_PORT0_RATE_CTRL0, 0x000f),
MAKE_REG(INGRESSBW_PORT0_RATE_CTRL1, 0x0010),
MAKE_REG(PORT0_FORCE_RATE0, 0x0011),
MAKE_REG(PORT0_FORCE_RATE1, 0x0012),
MAKE_REG(PORT0_CURENT_RATE0, 0x0013),
MAKE_REG(PORT0_CURENT_RATE1, 0x0014),
MAKE_REG(PORT0_PAGE_COUNTER, 0x0015),
MAKE_REG(PAGEMETER_PORT0_CTRL0, 0x0016),
MAKE_REG(PAGEMETER_PORT0_CTRL1, 0x0017),
MAKE_REG(PORT0_EEECFG, 0x0018),
MAKE_REG(PORT0_EEETXMTR, 0x0019),
MAKE_REG(PORT0_EEERXMTR, 0x001a),
MAKE_REG(PORT0_EEEPTXMTR, 0x001b),
MAKE_REG(PORT0_EEEPRXMTR, 0x001c),
MAKE_REG(PTP_PORT0_CFG1, 0x001e),
MAKE_REG(P0_MSIC1, 0x001f),
MAKE_REG(PORT1_CGST_HALF_CFG, 0x0020),
MAKE_REG(TX_ERR_CNT_PORT1, 0x0022),
MAKE_REG(PORT1_MISC_CFG, 0x002e),
MAKE_REG(INGRESSBW_PORT1_RATE_CTRL0, 0x002f),
MAKE_REG(INGRESSBW_PORT1_RATE_CTRL1, 0x0030),
MAKE_REG(PORT1_FORCE_RATE0, 0x0031),
MAKE_REG(PORT1_FORCE_RATE1, 0x0032),
MAKE_REG(PORT1_CURENT_RATE0, 0x0033),
MAKE_REG(PORT1_CURENT_RATE1, 0x0034),
MAKE_REG(PORT1_PAGE_COUNTER, 0x0035),
MAKE_REG(PAGEMETER_PORT1_CTRL0, 0x0036),
MAKE_REG(PAGEMETER_PORT1_CTRL1, 0x0037),
MAKE_REG(PORT1_EEECFG, 0x0038),
MAKE_REG(PORT1_EEETXMTR, 0x0039),
MAKE_REG(PORT1_EEERXMTR, 0x003a),
MAKE_REG(PORT1_EEEPTXMTR, 0x003b),
MAKE_REG(PORT1_EEEPRXMTR, 0x003c),
MAKE_REG(PTP_PORT1_CFG1, 0x003e),
MAKE_REG(P1_MSIC1, 0x003f),
MAKE_REG(PORT2_CGST_HALF_CFG, 0x0040),
MAKE_REG(TX_ERR_CNT_PORT2, 0x0042),
MAKE_REG(PORT2_MISC_CFG, 0x004e),
MAKE_REG(INGRESSBW_PORT2_RATE_CTRL0, 0x004f),
MAKE_REG(INGRESSBW_PORT2_RATE_CTRL1, 0x0050),
MAKE_REG(PORT2_FORCE_RATE0, 0x0051),
MAKE_REG(PORT2_FORCE_RATE1, 0x0052),
MAKE_REG(PORT2_CURENT_RATE0, 0x0053),
MAKE_REG(PORT2_CURENT_RATE1, 0x0054),
MAKE_REG(PORT2_PAGE_COUNTER, 0x0055),
MAKE_REG(PAGEMETER_PORT2_CTRL0, 0x0056),
MAKE_REG(PAGEMETER_PORT2_CTRL1, 0x0057),
MAKE_REG(PORT2_EEECFG, 0x0058),
MAKE_REG(PORT2_EEETXMTR, 0x0059),
MAKE_REG(PORT2_EEERXMTR, 0x005a),
MAKE_REG(PORT2_EEEPTXMTR, 0x005b),
MAKE_REG(PORT2_EEEPRXMTR, 0x005c),
MAKE_REG(PTP_PORT2_CFG1, 0x005e),
MAKE_REG(P2_MSIC1, 0x005f),
MAKE_REG(PORT3_CGST_HALF_CFG, 0x0060),
MAKE_REG(TX_ERR_CNT_PORT3, 0x0062),
MAKE_REG(PORT3_MISC_CFG, 0x006e),
MAKE_REG(INGRESSBW_PORT3_RATE_CTRL0, 0x006f),
MAKE_REG(INGRESSBW_PORT3_RATE_CTRL1, 0x0070),
MAKE_REG(PORT3_FORCE_RATE0, 0x0071),
MAKE_REG(PORT3_FORCE_RATE1, 0x0072),
MAKE_REG(PORT3_CURENT_RATE0, 0x0073),
MAKE_REG(PORT3_CURENT_RATE1, 0x0074),
MAKE_REG(PORT3_PAGE_COUNTER, 0x0075),
MAKE_REG(PAGEMETER_PORT3_CTRL0, 0x0076),
MAKE_REG(PAGEMETER_PORT3_CTRL1, 0x0077),
MAKE_REG(PORT3_EEECFG, 0x0078),
MAKE_REG(PORT3_EEETXMTR, 0x0079),
MAKE_REG(PORT3_EEERXMTR, 0x007a),
MAKE_REG(PORT3_EEEPTXMTR, 0x007b),
MAKE_REG(PORT3_EEEPRXMTR, 0x007c),
MAKE_REG(PTP_PORT3_CFG1, 0x007e),
MAKE_REG(P3_MSIC1, 0x007f),
MAKE_REG(PORT4_CGST_HALF_CFG, 0x0080),
MAKE_REG(TX_ERR_CNT_PORT4, 0x0082),
MAKE_REG(PORT4_MISC_CFG, 0x008e),
MAKE_REG(INGRESSBW_PORT4_RATE_CTRL0, 0x008f),
MAKE_REG(INGRESSBW_PORT4_RATE_CTRL1, 0x0090),
MAKE_REG(PORT4_FORCE_RATE0, 0x0091),
MAKE_REG(PORT4_FORCE_RATE1, 0x0092),
MAKE_REG(PORT4_CURENT_RATE0, 0x0093),
MAKE_REG(PORT4_CURENT_RATE1, 0x0094),
MAKE_REG(PORT4_PAGE_COUNTER, 0x0095),
MAKE_REG(PAGEMETER_PORT4_CTRL0, 0x0096),
MAKE_REG(PAGEMETER_PORT4_CTRL1, 0x0097),
MAKE_REG(PORT4_EEECFG, 0x0098),
MAKE_REG(PORT4_EEETXMTR, 0x0099),
MAKE_REG(PORT4_EEERXMTR, 0x009a),
MAKE_REG(PORT4_EEEPTXMTR, 0x009b),
MAKE_REG(PORT4_EEEPRXMTR, 0x009c),
MAKE_REG(PTP_PORT4_CFG1, 0x009e),
MAKE_REG(P4_MSIC1, 0x009f),
MAKE_REG(PORT5_CGST_HALF_CFG, 0x00a0),
MAKE_REG(TX_ERR_CNT_PORT5, 0x00a2),
MAKE_REG(PORT5_MISC_CFG, 0x00ae),
MAKE_REG(INGRESSBW_PORT5_RATE_CTRL0, 0x00af),
MAKE_REG(INGRESSBW_PORT5_RATE_CTRL1, 0x00b0),
MAKE_REG(PORT5_FORCE_RATE0, 0x00b1),
MAKE_REG(PORT5_FORCE_RATE1, 0x00b2),
MAKE_REG(PORT5_CURENT_RATE0, 0x00b3),
MAKE_REG(PORT5_CURENT_RATE1, 0x00b4),
MAKE_REG(PORT5_PAGE_COUNTER, 0x00b5),
MAKE_REG(PAGEMETER_PORT5_CTRL0, 0x00b6),
MAKE_REG(PAGEMETER_PORT5_CTRL1, 0x00b7),
MAKE_REG(PORT5_EEECFG, 0x00b8),
MAKE_REG(PORT5_EEETXMTR, 0x00b9),
MAKE_REG(PORT5_EEERXMTR, 0x00ba),
MAKE_REG(PORT5_EEEPTXMTR, 0x00bb),
MAKE_REG(PORT5_EEEPRXMTR, 0x00bc),
MAKE_REG(PTP_PORT5_CFG1, 0x00be),
MAKE_REG(P5_MSIC1, 0x00bf),
MAKE_REG(PORT6_CGST_HALF_CFG, 0x00c0),
MAKE_REG(TX_ERR_CNT_PORT6, 0x00c2),
MAKE_REG(PORT6_MISC_CFG, 0x00ce),
MAKE_REG(INGRESSBW_PORT6_RATE_CTRL0, 0x00cf),
MAKE_REG(INGRESSBW_PORT6_RATE_CTRL1, 0x00d0),
MAKE_REG(PORT6_FORCE_RATE0, 0x00d1),
MAKE_REG(PORT6_FORCE_RATE1, 0x00d2),
MAKE_REG(PORT6_CURENT_RATE0, 0x00d3),
MAKE_REG(PORT6_CURENT_RATE1, 0x00d4),
MAKE_REG(PORT6_PAGE_COUNTER, 0x00d5),
MAKE_REG(PAGEMETER_PORT6_CTRL0, 0x00d6),
MAKE_REG(PAGEMETER_PORT6_CTRL1, 0x00d7),
MAKE_REG(PORT6_EEECFG, 0x00d8),
MAKE_REG(PORT6_EEETXMTR, 0x00d9),
MAKE_REG(PORT6_EEERXMTR, 0x00da),
MAKE_REG(PORT6_EEEPTXMTR, 0x00db),
MAKE_REG(PORT6_EEEPRXMTR, 0x00dc),
MAKE_REG(PTP_PORT6_CFG1, 0x00de),
MAKE_REG(P6_MSIC1, 0x00df),
MAKE_REG(PORT7_CGST_HALF_CFG, 0x00e0),
MAKE_REG(TX_ERR_CNT_PORT7, 0x00e2),
MAKE_REG(PORT7_MISC_CFG, 0x00ee),
MAKE_REG(INGRESSBW_PORT7_RATE_CTRL0, 0x00ef),
MAKE_REG(INGRESSBW_PORT7_RATE_CTRL1, 0x00f0),
MAKE_REG(PORT7_FORCE_RATE0, 0x00f1),
MAKE_REG(PORT7_FORCE_RATE1, 0x00f2),
MAKE_REG(PORT7_CURENT_RATE0, 0x00f3),
MAKE_REG(PORT7_CURENT_RATE1, 0x00f4),
MAKE_REG(PORT7_PAGE_COUNTER, 0x00f5),
MAKE_REG(PAGEMETER_PORT7_CTRL0, 0x00f6),
MAKE_REG(PAGEMETER_PORT7_CTRL1, 0x00f7),
MAKE_REG(PORT7_EEECFG, 0x00f8),
MAKE_REG(PORT7_EEETXMTR, 0x00f9),
MAKE_REG(PORT7_EEERXMTR, 0x00fa),
MAKE_REG(PORT7_EEEPTXMTR, 0x00fb),
MAKE_REG(PORT7_EEEPRXMTR, 0x00fc),
MAKE_REG(PTP_PORT7_CFG1, 0x00fe),
MAKE_REG(P7_MSIC1, 0x00ff),
MAKE_REG(PORT8_CGST_HALF_CFG, 0x0100),
MAKE_REG(TX_ERR_CNT_PORT8, 0x0102),
MAKE_REG(PORT8_MISC_CFG, 0x010e),
MAKE_REG(INGRESSBW_PORT8_RATE_CTRL0, 0x010f),
MAKE_REG(INGRESSBW_PORT8_RATE_CTRL1, 0x0110),
MAKE_REG(PORT8_FORCE_RATE0, 0x0111),
MAKE_REG(PORT8_FORCE_RATE1, 0x0112),
MAKE_REG(PORT8_CURENT_RATE0, 0x0113),
MAKE_REG(PORT8_CURENT_RATE1, 0x0114),
MAKE_REG(PORT8_PAGE_COUNTER, 0x0115),
MAKE_REG(PAGEMETER_PORT8_CTRL0, 0x0116),
MAKE_REG(PAGEMETER_PORT8_CTRL1, 0x0117),
MAKE_REG(PORT8_EEECFG, 0x0118),
MAKE_REG(PORT8_EEETXMTR, 0x0119),
MAKE_REG(PORT8_EEERXMTR, 0x011a),
MAKE_REG(PORT8_EEEPTXMTR, 0x011b),
MAKE_REG(PORT8_EEEPRXMTR, 0x011c),
MAKE_REG(PTP_PORT8_CFG1, 0x011e),
MAKE_REG(P8_MSIC1, 0x011f),
MAKE_REG(PORT9_CGST_HALF_CFG, 0x0120),
MAKE_REG(TX_ERR_CNT_PORT9, 0x0122),
MAKE_REG(PORT9_MISC_CFG, 0x012e),
MAKE_REG(INGRESSBW_PORT9_RATE_CTRL0, 0x012f),
MAKE_REG(INGRESSBW_PORT9_RATE_CTRL1, 0x0130),
MAKE_REG(PORT9_FORCE_RATE0, 0x0131),
MAKE_REG(PORT9_FORCE_RATE1, 0x0132),
MAKE_REG(PORT9_CURENT_RATE0, 0x0133),
MAKE_REG(PORT9_CURENT_RATE1, 0x0134),
MAKE_REG(PORT9_PAGE_COUNTER, 0x0135),
MAKE_REG(PAGEMETER_PORT9_CTRL0, 0x0136),
MAKE_REG(PAGEMETER_PORT9_CTRL1, 0x0137),
MAKE_REG(PORT9_EEECFG, 0x0138),
MAKE_REG(PORT9_EEETXMTR, 0x0139),
MAKE_REG(PORT9_EEERXMTR, 0x013a),
MAKE_REG(PORT9_EEEPTXMTR, 0x013b),
MAKE_REG(PORT9_EEEPRXMTR, 0x013c),
MAKE_REG(PTP_PORT9_CFG1, 0x013e),
MAKE_REG(P9_MSIC1, 0x013f),
MAKE_REG(PORT10_CGST_HALF_CFG, 0x0140),
MAKE_REG(TX_ERR_CNT_PORT10, 0x0142),
MAKE_REG(PORT10_MISC_CFG, 0x014e),
MAKE_REG(INGRESSBW_PORT10_RATE_CTRL0, 0x014f),
MAKE_REG(INGRESSBW_PORT10_RATE_CTRL1, 0x0150),
MAKE_REG(PORT10_FORCE_RATE0, 0x0151),
MAKE_REG(PORT10_FORCE_RATE1, 0x0152),
MAKE_REG(PORT10_CURENT_RATE0, 0x0153),
MAKE_REG(PORT10_CURENT_RATE1, 0x0154),
MAKE_REG(PORT10_PAGE_COUNTER, 0x0155),
MAKE_REG(PAGEMETER_PORT10_CTRL0, 0x0156),
MAKE_REG(PAGEMETER_PORT10_CTRL1, 0x0157),
MAKE_REG(PORT10_EEECFG, 0x0158),
MAKE_REG(PORT10_EEETXMTR, 0x0159),
MAKE_REG(PORT10_EEERXMTR, 0x015a),
MAKE_REG(PORT10_EEEPTXMTR, 0x015b),
MAKE_REG(PORT10_EEEPRXMTR, 0x015c),
MAKE_REG(PTP_PORT10_CFG1, 0x015e),
MAKE_REG(P10_MSIC1, 0x015f),
MAKE_REG(FLOWCTRL_QUEUE0_DROP_ON, 0x0200),
MAKE_REG(FLOWCTRL_QUEUE1_DROP_ON, 0x0201),
MAKE_REG(FLOWCTRL_QUEUE2_DROP_ON, 0x0202),
MAKE_REG(FLOWCTRL_QUEUE3_DROP_ON, 0x0203),
MAKE_REG(FLOWCTRL_QUEUE4_DROP_ON, 0x0204),
MAKE_REG(FLOWCTRL_QUEUE5_DROP_ON, 0x0205),
MAKE_REG(FLOWCTRL_QUEUE6_DROP_ON, 0x0206),
MAKE_REG(FLOWCTRL_QUEUE7_DROP_ON, 0x0207),
MAKE_REG(FLOWCTRL_PORT0_DROP_ON, 0x0208),
MAKE_REG(FLOWCTRL_PORT1_DROP_ON, 0x0209),
MAKE_REG(FLOWCTRL_PORT2_DROP_ON, 0x020a),
MAKE_REG(FLOWCTRL_PORT3_DROP_ON, 0x020b),
MAKE_REG(FLOWCTRL_PORT4_DROP_ON, 0x020c),
MAKE_REG(FLOWCTRL_PORT5_DROP_ON, 0x020d),
MAKE_REG(FLOWCTRL_PORT6_DROP_ON, 0x020e),
MAKE_REG(FLOWCTRL_PORT7_DROP_ON, 0x020f),
MAKE_REG(FLOWCTRL_PORT8_DROP_ON, 0x0210),
MAKE_REG(FLOWCTRL_PORT9_DROP_ON, 0x0211),
MAKE_REG(FLOWCTRL_PORT10_DROP_ON, 0x0212),
MAKE_REG(FLOWCTRL_PORT_GAP, 0x0218),
MAKE_REG(FLOWCTRL_QUEUE_GAP, 0x0219),
MAKE_REG(PORT_QEMPTY, 0x022d),
MAKE_REG(FLOWCTRL_DEBUG_CTRL0, 0x022e),
MAKE_REG(FLOWCTRL_DEBUG_CTRL1, 0x022f),
MAKE_REG(FLOWCTRL_QUEUE0_PAGE_COUNT, 0x0230),
MAKE_REG(FLOWCTRL_QUEUE1_PAGE_COUNT, 0x0231),
MAKE_REG(FLOWCTRL_QUEUE2_PAGE_COUNT, 0x0232),
MAKE_REG(FLOWCTRL_QUEUE3_PAGE_COUNT, 0x0233),
MAKE_REG(FLOWCTRL_QUEUE4_PAGE_COUNT, 0x0234),
MAKE_REG(FLOWCTRL_QUEUE5_PAGE_COUNT, 0x0235),
MAKE_REG(FLOWCTRL_QUEUE6_PAGE_COUNT, 0x0236),
MAKE_REG(FLOWCTRL_QUEUE7_PAGE_COUNT, 0x0237),
MAKE_REG(FLOWCTRL_PORT_PAGE_COUNT, 0x0238),
MAKE_REG(FLOWCTRL_QUEUE0_MAX_PAGE_COUNT, 0x0239),
MAKE_REG(FLOWCTRL_QUEUE1_MAX_PAGE_COUNT, 0x023a),
MAKE_REG(FLOWCTRL_QUEUE2_MAX_PAGE_COUNT, 0x023b),
MAKE_REG(FLOWCTRL_QUEUE3_MAX_PAGE_COUNT, 0x023c),
MAKE_REG(FLOWCTRL_QUEUE4_MAX_PAGE_COUNT, 0x023d),
MAKE_REG(FLOWCTRL_QUEUE5_MAX_PAGE_COUNT, 0x023e),
MAKE_REG(FLOWCTRL_QUEUE6_MAX_PAGE_COUNT, 0x023f),
MAKE_REG(FLOWCTRL_QUEUE7_MAX_PAGE_COUNT, 0x0240),
MAKE_REG(FLOWCTRL_PORT_MAX_PAGE_COUNT, 0x0241),
MAKE_REG(FLOWCTRL_TOTAL_PACKET_COUNT, 0x0243),
MAKE_REG(HIGH_QUEUE_MASK0, 0x0244),
MAKE_REG(HIGH_QUEUE_MASK1, 0x0245),
MAKE_REG(HIGH_QUEUE_MASK2, 0x0246),
MAKE_REG(HIGH_QUEUE_MASK3, 0x0247),
MAKE_REG(HIGH_QUEUE_MASK4, 0x0248),
MAKE_REG(HIGH_QUEUE_MASK5, 0x0249),
MAKE_REG(LOW_QUEUE_TH, 0x024c),
MAKE_REG(TH_TX_PREFET, 0x0250),
MAKE_REG(DUMMY_0251, 0x0251),
MAKE_REG(DUMMY_0252, 0x0252),
MAKE_REG(DUMMY_0253, 0x0253),
MAKE_REG(DUMMY_0254, 0x0254),
MAKE_REG(DUMMY_0255, 0x0255),
MAKE_REG(DUMMY_0256, 0x0256),
MAKE_REG(DUMMY_0257, 0x0257),
MAKE_REG(DUMMY_0258, 0x0258),
MAKE_REG(DUMMY_0259, 0x0259),
MAKE_REG(DUMMY_025A, 0x025A),
MAKE_REG(DUMMY_025B, 0x025B),
MAKE_REG(DUMMY_025C, 0x025C),
MAKE_REG(Q_TXPKT_CNT_CTL, 0x025d),
MAKE_REG(Q0_TXPKT_CNT_L, 0x025e),
MAKE_REG(Q0_TXPKT_CNT_H, 0x025f),
MAKE_REG(Q1_TXPKT_CNT_L, 0x0260),
MAKE_REG(Q1_TXPKT_CNT_H, 0x0261),
MAKE_REG(Q2_TXPKT_CNT_L, 0x0262),
MAKE_REG(Q2_TXPKT_CNT_H, 0x0263),
MAKE_REG(Q3_TXPKT_CNT_L, 0x0264),
MAKE_REG(Q3_TXPKT_CNT_H, 0x0265),
MAKE_REG(Q4_TXPKT_CNT_L, 0x0266),
MAKE_REG(Q4_TXPKT_CNT_H, 0x0267),
MAKE_REG(Q5_TXPKT_CNT_L, 0x0268),
MAKE_REG(Q5_TXPKT_CNT_H, 0x0269),
MAKE_REG(Q6_TXPKT_CNT_L, 0x026a),
MAKE_REG(Q6_TXPKT_CNT_H, 0x026b),
MAKE_REG(Q7_TXPKT_CNT_L, 0x026c),
MAKE_REG(Q7_TXPKT_CNT_H, 0x026d),
MAKE_REG(SCHEDULE_WFQ_CTRL, 0x0300),
MAKE_REG(SCHEDULE_WFQ_BURST_SIZE, 0x0301),
MAKE_REG(SCHEDULE_QUEUE_TYPE_CTRL0, 0x0302),
MAKE_REG(SCHEDULE_QUEUE_TYPE_CTRL1, 0x0303),
MAKE_REG(SCHEDULE_QUEUE_TYPE_CTRL2, 0x0304),
MAKE_REG(SCHEDULE_QUEUE_TYPE_CTRL3, 0x0305),
MAKE_REG(SCHEDULE_QUEUE_TYPE_CTRL4, 0x0306),
MAKE_REG(SCHEDULE_QUEUE_TYPE_CTRL5, 0x0307),
MAKE_REG(SCHEDULE_APR_CTRL0, 0x030a),
MAKE_REG(SCHEDULE_PORT0_QUEUE0_WFQ_WEIGHT, 0x030c),
MAKE_REG(SCHEDULE_PORT0_QUEUE1_WFQ_WEIGHT, 0x030d),
MAKE_REG(SCHEDULE_PORT0_QUEUE2_WFQ_WEIGHT, 0x030e),
MAKE_REG(SCHEDULE_PORT0_QUEUE3_WFQ_WEIGHT, 0x030f),
MAKE_REG(SCHEDULE_PORT0_QUEUE4_WFQ_WEIGHT, 0x0310),
MAKE_REG(SCHEDULE_PORT0_QUEUE5_WFQ_WEIGHT, 0x0311),
MAKE_REG(SCHEDULE_PORT0_QUEUE6_WFQ_WEIGHT, 0x0312),
MAKE_REG(SCHEDULE_PORT0_QUEUE7_WFQ_WEIGHT, 0x0313),
MAKE_REG(SCHEDULE_PORT1_QUEUE0_WFQ_WEIGHT, 0x0314),
MAKE_REG(SCHEDULE_PORT1_QUEUE1_WFQ_WEIGHT, 0x0315),
MAKE_REG(SCHEDULE_PORT1_QUEUE2_WFQ_WEIGHT, 0x0316),
MAKE_REG(SCHEDULE_PORT1_QUEUE3_WFQ_WEIGHT, 0x0317),
MAKE_REG(SCHEDULE_PORT1_QUEUE4_WFQ_WEIGHT, 0x0318),
MAKE_REG(SCHEDULE_PORT1_QUEUE5_WFQ_WEIGHT, 0x0319),
MAKE_REG(SCHEDULE_PORT1_QUEUE6_WFQ_WEIGHT, 0x031a),
MAKE_REG(SCHEDULE_PORT1_QUEUE7_WFQ_WEIGHT, 0x031b),
MAKE_REG(SCHEDULE_PORT2_QUEUE0_WFQ_WEIGHT, 0x031c),
MAKE_REG(SCHEDULE_PORT2_QUEUE1_WFQ_WEIGHT, 0x031d),
MAKE_REG(SCHEDULE_PORT2_QUEUE2_WFQ_WEIGHT, 0x031e),
MAKE_REG(SCHEDULE_PORT2_QUEUE3_WFQ_WEIGHT, 0x031f),
MAKE_REG(SCHEDULE_PORT2_QUEUE4_WFQ_WEIGHT, 0x0320),
MAKE_REG(SCHEDULE_PORT2_QUEUE5_WFQ_WEIGHT, 0x0321),
MAKE_REG(SCHEDULE_PORT2_QUEUE6_WFQ_WEIGHT, 0x0322),
MAKE_REG(SCHEDULE_PORT2_QUEUE7_WFQ_WEIGHT, 0x0323),
MAKE_REG(SCHEDULE_PORT3_QUEUE0_WFQ_WEIGHT, 0x0324),
MAKE_REG(SCHEDULE_PORT3_QUEUE1_WFQ_WEIGHT, 0x0325),
MAKE_REG(SCHEDULE_PORT3_QUEUE2_WFQ_WEIGHT, 0x0326),
MAKE_REG(SCHEDULE_PORT3_QUEUE3_WFQ_WEIGHT, 0x0327),
MAKE_REG(SCHEDULE_PORT3_QUEUE4_WFQ_WEIGHT, 0x0328),
MAKE_REG(SCHEDULE_PORT3_QUEUE5_WFQ_WEIGHT, 0x0329),
MAKE_REG(SCHEDULE_PORT3_QUEUE6_WFQ_WEIGHT, 0x032a),
MAKE_REG(SCHEDULE_PORT3_QUEUE7_WFQ_WEIGHT, 0x032b),
MAKE_REG(SCHEDULE_PORT4_QUEUE0_WFQ_WEIGHT, 0x032c),
MAKE_REG(SCHEDULE_PORT4_QUEUE1_WFQ_WEIGHT, 0x032d),
MAKE_REG(SCHEDULE_PORT4_QUEUE2_WFQ_WEIGHT, 0x032e),
MAKE_REG(SCHEDULE_PORT4_QUEUE3_WFQ_WEIGHT, 0x032f),
MAKE_REG(SCHEDULE_PORT4_QUEUE4_WFQ_WEIGHT, 0x0330),
MAKE_REG(SCHEDULE_PORT4_QUEUE5_WFQ_WEIGHT, 0x0331),
MAKE_REG(SCHEDULE_PORT4_QUEUE6_WFQ_WEIGHT, 0x0332),
MAKE_REG(SCHEDULE_PORT4_QUEUE7_WFQ_WEIGHT, 0x0333),
MAKE_REG(SCHEDULE_PORT5_QUEUE0_WFQ_WEIGHT, 0x0334),
MAKE_REG(SCHEDULE_PORT5_QUEUE1_WFQ_WEIGHT, 0x0335),
MAKE_REG(SCHEDULE_PORT5_QUEUE2_WFQ_WEIGHT, 0x0336),
MAKE_REG(SCHEDULE_PORT5_QUEUE3_WFQ_WEIGHT, 0x0337),
MAKE_REG(SCHEDULE_PORT5_QUEUE4_WFQ_WEIGHT, 0x0338),
MAKE_REG(SCHEDULE_PORT5_QUEUE5_WFQ_WEIGHT, 0x0339),
MAKE_REG(SCHEDULE_PORT5_QUEUE6_WFQ_WEIGHT, 0x033a),
MAKE_REG(SCHEDULE_PORT5_QUEUE7_WFQ_WEIGHT, 0x033b),
MAKE_REG(SCHEDULE_PORT6_QUEUE0_WFQ_WEIGHT, 0x033c),
MAKE_REG(SCHEDULE_PORT6_QUEUE1_WFQ_WEIGHT, 0x033d),
MAKE_REG(SCHEDULE_PORT6_QUEUE2_WFQ_WEIGHT, 0x033e),
MAKE_REG(SCHEDULE_PORT6_QUEUE3_WFQ_WEIGHT, 0x033f),
MAKE_REG(SCHEDULE_PORT6_QUEUE4_WFQ_WEIGHT, 0x0340),
MAKE_REG(SCHEDULE_PORT6_QUEUE5_WFQ_WEIGHT, 0x0341),
MAKE_REG(SCHEDULE_PORT6_QUEUE6_WFQ_WEIGHT, 0x0342),
MAKE_REG(SCHEDULE_PORT6_QUEUE7_WFQ_WEIGHT, 0x0343),
MAKE_REG(SCHEDULE_PORT7_QUEUE0_WFQ_WEIGHT, 0x0344),
MAKE_REG(SCHEDULE_PORT7_QUEUE1_WFQ_WEIGHT, 0x0345),
MAKE_REG(SCHEDULE_PORT7_QUEUE2_WFQ_WEIGHT, 0x0346),
MAKE_REG(SCHEDULE_PORT7_QUEUE3_WFQ_WEIGHT, 0x0347),
MAKE_REG(SCHEDULE_PORT7_QUEUE4_WFQ_WEIGHT, 0x0348),
MAKE_REG(SCHEDULE_PORT7_QUEUE5_WFQ_WEIGHT, 0x0349),
MAKE_REG(SCHEDULE_PORT7_QUEUE6_WFQ_WEIGHT, 0x034a),
MAKE_REG(SCHEDULE_PORT7_QUEUE7_WFQ_WEIGHT, 0x034b),
MAKE_REG(SCHEDULE_PORT8_QUEUE0_WFQ_WEIGHT, 0x034c),
MAKE_REG(SCHEDULE_PORT8_QUEUE1_WFQ_WEIGHT, 0x034d),
MAKE_REG(SCHEDULE_PORT8_QUEUE2_WFQ_WEIGHT, 0x034e),
MAKE_REG(SCHEDULE_PORT8_QUEUE3_WFQ_WEIGHT, 0x034f),
MAKE_REG(SCHEDULE_PORT8_QUEUE4_WFQ_WEIGHT, 0x0350),
MAKE_REG(SCHEDULE_PORT8_QUEUE5_WFQ_WEIGHT, 0x0351),
MAKE_REG(SCHEDULE_PORT8_QUEUE6_WFQ_WEIGHT, 0x0352),
MAKE_REG(SCHEDULE_PORT8_QUEUE7_WFQ_WEIGHT, 0x0353),
MAKE_REG(SCHEDULE_PORT9_QUEUE0_WFQ_WEIGHT, 0x0354),
MAKE_REG(SCHEDULE_PORT9_QUEUE1_WFQ_WEIGHT, 0x0355),
MAKE_REG(SCHEDULE_PORT9_QUEUE2_WFQ_WEIGHT, 0x0356),
MAKE_REG(SCHEDULE_PORT9_QUEUE3_WFQ_WEIGHT, 0x0357),
MAKE_REG(SCHEDULE_PORT9_QUEUE4_WFQ_WEIGHT, 0x0358),
MAKE_REG(SCHEDULE_PORT9_QUEUE5_WFQ_WEIGHT, 0x0359),
MAKE_REG(SCHEDULE_PORT9_QUEUE6_WFQ_WEIGHT, 0x035a),
MAKE_REG(SCHEDULE_PORT9_QUEUE7_WFQ_WEIGHT, 0x035b),
MAKE_REG(SCHEDULE_PORT10_QUEUE0_WFQ_WEIGHT, 0x035c),
MAKE_REG(SCHEDULE_PORT10_QUEUE1_WFQ_WEIGHT, 0x035d),
MAKE_REG(SCHEDULE_PORT10_QUEUE2_WFQ_WEIGHT, 0x035e),
MAKE_REG(SCHEDULE_PORT10_QUEUE3_WFQ_WEIGHT, 0x035f),
MAKE_REG(SCHEDULE_PORT10_QUEUE4_WFQ_WEIGHT, 0x0360),
MAKE_REG(SCHEDULE_PORT10_QUEUE5_WFQ_WEIGHT, 0x0361),
MAKE_REG(SCHEDULE_PORT10_QUEUE6_WFQ_WEIGHT, 0x0362),
MAKE_REG(SCHEDULE_PORT10_QUEUE7_WFQ_WEIGHT, 0x0363),
MAKE_REG(PORT0_EGRESSBW_CTRL0, 0x038c),
MAKE_REG(PORT0_EGRESSBW_CTRL1, 0x038d),
MAKE_REG(PORT1_EGRESSBW_CTRL0, 0x038e),
MAKE_REG(PORT1_EGRESSBW_CTRL1, 0x038f),
MAKE_REG(PORT2_EGRESSBW_CTRL0, 0x0390),
MAKE_REG(PORT2_EGRESSBW_CTRL1, 0x0391),
MAKE_REG(PORT3_EGRESSBW_CTRL0, 0x0392),
MAKE_REG(PORT3_EGRESSBW_CTRL1, 0x0393),
MAKE_REG(PORT4_EGRESSBW_CTRL0, 0x0394),
MAKE_REG(PORT4_EGRESSBW_CTRL1, 0x0395),
MAKE_REG(PORT5_EGRESSBW_CTRL0, 0x0396),
MAKE_REG(PORT5_EGRESSBW_CTRL1, 0x0397),
MAKE_REG(PORT6_EGRESSBW_CTRL0, 0x0398),
MAKE_REG(PORT6_EGRESSBW_CTRL1, 0x0399),
MAKE_REG(PORT7_EGRESSBW_CTRL0, 0x039a),
MAKE_REG(PORT7_EGRESSBW_CTRL1, 0x039b),
MAKE_REG(PORT8_EGRESSBW_CTRL0, 0x039c),
MAKE_REG(PORT8_EGRESSBW_CTRL1, 0x039d),
MAKE_REG(PORT9_EGRESSBW_CTRL0, 0x039e),
MAKE_REG(PORT9_EGRESSBW_CTRL1, 0x039f),
MAKE_REG(PORT10_EGRESSBW_CTRL0, 0x03a0),
MAKE_REG(PORT10_EGRESSBW_CTRL1, 0x03a1),
MAKE_REG(SCHEDULE_PORT0_APR_METER_CTRL0, 0x03ac),
MAKE_REG(SCHEDULE_PORT0_APR_METER_CTRL1, 0x03ad),
MAKE_REG(SCHEDULE_PORT1_APR_METER_CTRL0, 0x03b0),
MAKE_REG(SCHEDULE_PORT1_APR_METER_CTRL1, 0x03b1),
MAKE_REG(SCHEDULE_PORT2_APR_METER_CTRL0, 0x03b4),
MAKE_REG(SCHEDULE_PORT2_APR_METER_CTRL1, 0x03b5),
MAKE_REG(SCHEDULE_PORT3_APR_METER_CTRL0, 0x03b8),
MAKE_REG(SCHEDULE_PORT3_APR_METER_CTRL1, 0x03b9),
MAKE_REG(SCHEDULE_PORT4_APR_METER_CTRL0, 0x03bc),
MAKE_REG(SCHEDULE_PORT4_APR_METER_CTRL1, 0x03bd),
MAKE_REG(SCHEDULE_PORT5_APR_METER_CTRL0, 0x03c0),
MAKE_REG(SCHEDULE_PORT5_APR_METER_CTRL1, 0x03c1),
MAKE_REG(SCHEDULE_PORT6_APR_METER_CTRL0, 0x03c4),
MAKE_REG(SCHEDULE_PORT6_APR_METER_CTRL1, 0x03c5),
MAKE_REG(SCHEDULE_PORT7_APR_METER_CTRL0, 0x03c8),
MAKE_REG(SCHEDULE_PORT7_APR_METER_CTRL1, 0x03c9),
MAKE_REG(SCHEDULE_PORT8_APR_METER_CTRL0, 0x03ca),
MAKE_REG(SCHEDULE_PORT8_APR_METER_CTRL1, 0x03cb),
MAKE_REG(SCHEDULE_PORT9_APR_METER_CTRL0, 0x03cc),
MAKE_REG(SCHEDULE_PORT9_APR_METER_CTRL1, 0x03cd),
MAKE_REG(SCHEDULE_PORT10_APR_METER_CTRL0, 0x03ce),
MAKE_REG(SCHEDULE_PORT10_APR_METER_CTRL1, 0x03cf),
MAKE_REG(LINE_RATE_1G_L, 0x03ec),
MAKE_REG(LINE_RATE_1G_H, 0x03ed),
MAKE_REG(LINE_RATE_100_L, 0x03ee),
MAKE_REG(LINE_RATE_100_H, 0x03ef),
MAKE_REG(LINE_RATE_10_L, 0x03f0),
MAKE_REG(LINE_RATE_10_H, 0x03f1),
MAKE_REG(DUMMY_03f2, 0x03f2),
MAKE_REG(DUMMY_03f3, 0x03f3),
MAKE_REG(DUMMY_03f4, 0x03f4),
MAKE_REG(DUMMY_03f5, 0x03f5),
MAKE_REG(DUMMY_03f6, 0x03f6),
MAKE_REG(BYPASS_LINE_RATE, 0x03f7),
MAKE_REG(LINE_RATE_500_H, 0x03f8),
MAKE_REG(LINE_RATE_500_L, 0x03f9),
MAKE_REG(LINE_RATE_HSG_H, 0x03fa),
MAKE_REG(LINE_RATE_HSG_L, 0x03fb),
MAKE_REG(TABLE_ACCESS_CTRL, 0x0500),
MAKE_REG(TABLE_ACCESS_ADDR, 0x0501),
MAKE_REG(TABLE_LUT_ADDR, 0x0502),
MAKE_REG(HSA_HSB_LATCH, 0x0503),
MAKE_REG(HSA_HSB_LATCH2, 0x0504),
MAKE_REG(TABLE_WRITE_DATA0, 0x0510),
MAKE_REG(TABLE_WRITE_DATA1, 0x0511),
MAKE_REG(TABLE_WRITE_DATA2, 0x0512),
MAKE_REG(TABLE_WRITE_DATA3, 0x0513),
MAKE_REG(TABLE_WRITE_DATA4, 0x0514),
MAKE_REG(TABLE_WRITE_DATA5, 0x0515),
MAKE_REG(TABLE_WRITE_DATA6, 0x0516),
MAKE_REG(TABLE_WRITE_DATA7, 0x0517),
MAKE_REG(TABLE_WRITE_DATA8, 0x0518),
MAKE_REG(TABLE_WRITE_DATA9, 0x0519),
MAKE_REG(TABLE_READ_DATA0, 0x0520),
MAKE_REG(TABLE_READ_DATA1, 0x0521),
MAKE_REG(TABLE_READ_DATA2, 0x0522),
MAKE_REG(TABLE_READ_DATA3, 0x0523),
MAKE_REG(TABLE_READ_DATA4, 0x0524),
MAKE_REG(TABLE_READ_DATA5, 0x0525),
MAKE_REG(TABLE_READ_DATA6, 0x0526),
MAKE_REG(TABLE_READ_DATA7, 0x0527),
MAKE_REG(TABLE_READ_DATA8, 0x0528),
MAKE_REG(TABLE_READ_DATA9, 0x0529),
MAKE_REG(TBL_DUMMY00, 0x0550),
MAKE_REG(TBL_DUMMY01, 0x0551),
MAKE_REG(ACL_RULE_TEMPLATE0_CTRL0, 0x0600),
MAKE_REG(ACL_RULE_TEMPLATE0_CTRL1, 0x0601),
MAKE_REG(ACL_RULE_TEMPLATE0_CTRL2, 0x0602),
MAKE_REG(ACL_RULE_TEMPLATE0_CTRL3, 0x0603),
MAKE_REG(ACL_RULE_TEMPLATE1_CTRL0, 0x0604),
MAKE_REG(ACL_RULE_TEMPLATE1_CTRL1, 0x0605),
MAKE_REG(ACL_RULE_TEMPLATE1_CTRL2, 0x0606),
MAKE_REG(ACL_RULE_TEMPLATE1_CTRL3, 0x0607),
MAKE_REG(ACL_RULE_TEMPLATE2_CTRL0, 0x0608),
MAKE_REG(ACL_RULE_TEMPLATE2_CTRL1, 0x0609),
MAKE_REG(ACL_RULE_TEMPLATE2_CTRL2, 0x060a),
MAKE_REG(ACL_RULE_TEMPLATE2_CTRL3, 0x060b),
MAKE_REG(ACL_RULE_TEMPLATE3_CTRL0, 0x060c),
MAKE_REG(ACL_RULE_TEMPLATE3_CTRL1, 0x060d),
MAKE_REG(ACL_RULE_TEMPLATE3_CTRL2, 0x060e),
MAKE_REG(ACL_RULE_TEMPLATE3_CTRL3, 0x060f),
MAKE_REG(ACL_RULE_TEMPLATE4_CTRL0, 0x0610),
MAKE_REG(ACL_RULE_TEMPLATE4_CTRL1, 0x0611),
MAKE_REG(ACL_RULE_TEMPLATE4_CTRL2, 0x0612),
MAKE_REG(ACL_RULE_TEMPLATE4_CTRL3, 0x0613),
MAKE_REG(ACL_ACTION_CTRL0, 0x0614),
MAKE_REG(ACL_ACTION_CTRL1, 0x0615),
MAKE_REG(ACL_ACTION_CTRL2, 0x0616),
MAKE_REG(ACL_ACTION_CTRL3, 0x0617),
MAKE_REG(ACL_ACTION_CTRL4, 0x0618),
MAKE_REG(ACL_ACTION_CTRL5, 0x0619),
MAKE_REG(ACL_ACTION_CTRL6, 0x061a),
MAKE_REG(ACL_ACTION_CTRL7, 0x061b),
MAKE_REG(ACL_ACTION_CTRL8, 0x061c),
MAKE_REG(ACL_ACTION_CTRL9, 0x061d),
MAKE_REG(ACL_ACTION_CTRL10, 0x061e),
MAKE_REG(ACL_ACTION_CTRL11, 0x061f),
MAKE_REG(ACL_ACTION_CTRL12, 0x0620),
MAKE_REG(ACL_ACTION_CTRL13, 0x0621),
MAKE_REG(ACL_ACTION_CTRL14, 0x0622),
MAKE_REG(ACL_ACTION_CTRL15, 0x0623),
MAKE_REG(ACL_ACTION_CTRL16, 0x0624),
MAKE_REG(ACL_ACTION_CTRL17, 0x0625),
MAKE_REG(ACL_ACTION_CTRL18, 0x0626),
MAKE_REG(ACL_ACTION_CTRL19, 0x0627),
MAKE_REG(ACL_ACTION_CTRL20, 0x0628),
MAKE_REG(ACL_ACTION_CTRL21, 0x0629),
MAKE_REG(ACL_ACTION_CTRL22, 0x062a),
MAKE_REG(ACL_ACTION_CTRL23, 0x062b),
MAKE_REG(ACL_ACTION_CTRL24, 0x062c),
MAKE_REG(ACL_ACTION_CTRL25, 0x062d),
MAKE_REG(ACL_ACTION_CTRL26, 0x062e),
MAKE_REG(ACL_ACTION_CTRL27, 0x062f),
MAKE_REG(ACL_ACTION_CTRL28, 0x0630),
MAKE_REG(ACL_ACTION_CTRL29, 0x0631),
MAKE_REG(ACL_ACTION_CTRL30, 0x0632),
MAKE_REG(ACL_ACTION_CTRL31, 0x0633),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY0_CTRL0, 0x0635),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY0_CTRL1, 0x0636),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY0_CTRL2, 0x0637),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY1_CTRL0, 0x0638),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY1_CTRL1, 0x0639),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY1_CTRL2, 0x063a),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY2_CTRL0, 0x063b),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY2_CTRL1, 0x063c),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY2_CTRL2, 0x063d),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY3_CTRL0, 0x063e),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY3_CTRL1, 0x063f),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY3_CTRL2, 0x0640),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY4_CTRL0, 0x0641),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY4_CTRL1, 0x0642),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY4_CTRL2, 0x0643),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY5_CTRL0, 0x0644),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY5_CTRL1, 0x0645),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY5_CTRL2, 0x0646),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY6_CTRL0, 0x0647),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY6_CTRL1, 0x0648),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY6_CTRL2, 0x0649),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY7_CTRL0, 0x064a),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY7_CTRL1, 0x064b),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY7_CTRL2, 0x064c),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY8_CTRL0, 0x064d),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY8_CTRL1, 0x064e),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY8_CTRL2, 0x064f),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY9_CTRL0, 0x0650),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY9_CTRL1, 0x0651),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY9_CTRL2, 0x0652),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY10_CTRL0, 0x0653),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY10_CTRL1, 0x0654),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY10_CTRL2, 0x0655),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY11_CTRL0, 0x0656),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY11_CTRL1, 0x0657),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY11_CTRL2, 0x0658),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY12_CTRL0, 0x0659),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY12_CTRL1, 0x065a),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY12_CTRL2, 0x065b),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY13_CTRL0, 0x065c),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY13_CTRL1, 0x065d),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY13_CTRL2, 0x065e),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY14_CTRL0, 0x065f),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY14_CTRL1, 0x0660),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY14_CTRL2, 0x0661),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY15_CTRL0, 0x0662),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY15_CTRL1, 0x0663),
MAKE_REG(ACL_SDPORT_RANGE_ENTRY15_CTRL2, 0x0664),
MAKE_REG(ACL_VID_RANGE_ENTRY0_CTRL0, 0x0665),
MAKE_REG(ACL_VID_RANGE_ENTRY0_CTRL1, 0x0666),
MAKE_REG(ACL_VID_RANGE_ENTRY1_CTRL0, 0x0667),
MAKE_REG(ACL_VID_RANGE_ENTRY1_CTRL1, 0x0668),
MAKE_REG(ACL_VID_RANGE_ENTRY2_CTRL0, 0x0669),
MAKE_REG(ACL_VID_RANGE_ENTRY2_CTRL1, 0x066a),
MAKE_REG(ACL_VID_RANGE_ENTRY3_CTRL0, 0x066b),
MAKE_REG(ACL_VID_RANGE_ENTRY3_CTRL1, 0x066c),
MAKE_REG(ACL_VID_RANGE_ENTRY4_CTRL0, 0x066d),
MAKE_REG(ACL_VID_RANGE_ENTRY4_CTRL1, 0x066e),
MAKE_REG(ACL_VID_RANGE_ENTRY5_CTRL0, 0x066f),
MAKE_REG(ACL_VID_RANGE_ENTRY5_CTRL1, 0x0670),
MAKE_REG(ACL_VID_RANGE_ENTRY6_CTRL0, 0x0671),
MAKE_REG(ACL_VID_RANGE_ENTRY6_CTRL1, 0x0672),
MAKE_REG(ACL_VID_RANGE_ENTRY7_CTRL0, 0x0673),
MAKE_REG(ACL_VID_RANGE_ENTRY7_CTRL1, 0x0674),
MAKE_REG(ACL_VID_RANGE_ENTRY8_CTRL0, 0x0675),
MAKE_REG(ACL_VID_RANGE_ENTRY8_CTRL1, 0x0676),
MAKE_REG(ACL_VID_RANGE_ENTRY9_CTRL0, 0x0677),
MAKE_REG(ACL_VID_RANGE_ENTRY9_CTRL1, 0x0678),
MAKE_REG(ACL_VID_RANGE_ENTRY10_CTRL0, 0x0679),
MAKE_REG(ACL_VID_RANGE_ENTRY10_CTRL1, 0x067a),
MAKE_REG(ACL_VID_RANGE_ENTRY11_CTRL0, 0x067b),
MAKE_REG(ACL_VID_RANGE_ENTRY11_CTRL1, 0x067c),
MAKE_REG(ACL_VID_RANGE_ENTRY12_CTRL0, 0x067d),
MAKE_REG(ACL_VID_RANGE_ENTRY12_CTRL1, 0x067e),
MAKE_REG(ACL_VID_RANGE_ENTRY13_CTRL0, 0x067f),
MAKE_REG(ACL_VID_RANGE_ENTRY13_CTRL1, 0x0680),
MAKE_REG(ACL_VID_RANGE_ENTRY14_CTRL0, 0x0681),
MAKE_REG(ACL_VID_RANGE_ENTRY14_CTRL1, 0x0682),
MAKE_REG(ACL_VID_RANGE_ENTRY15_CTRL0, 0x0683),
MAKE_REG(ACL_VID_RANGE_ENTRY15_CTRL1, 0x0684),
MAKE_REG(ACL_IP_RANGE_ENTRY0_CTRL0, 0x0685),
MAKE_REG(ACL_IP_RANGE_ENTRY0_CTRL1, 0x0686),
MAKE_REG(ACL_IP_RANGE_ENTRY0_CTRL2, 0x0687),
MAKE_REG(ACL_IP_RANGE_ENTRY0_CTRL3, 0x0688),
MAKE_REG(ACL_IP_RANGE_ENTRY0_CTRL4, 0x0689),
MAKE_REG(ACL_IP_RANGE_ENTRY1_CTRL0, 0x068a),
MAKE_REG(ACL_IP_RANGE_ENTRY1_CTRL1, 0x068b),
MAKE_REG(ACL_IP_RANGE_ENTRY1_CTRL2, 0x068c),
MAKE_REG(ACL_IP_RANGE_ENTRY1_CTRL3, 0x068d),
MAKE_REG(ACL_IP_RANGE_ENTRY1_CTRL4, 0x068e),
MAKE_REG(ACL_IP_RANGE_ENTRY2_CTRL0, 0x068f),
MAKE_REG(ACL_IP_RANGE_ENTRY2_CTRL1, 0x0690),
MAKE_REG(ACL_IP_RANGE_ENTRY2_CTRL2, 0x0691),
MAKE_REG(ACL_IP_RANGE_ENTRY2_CTRL3, 0x0692),
MAKE_REG(ACL_IP_RANGE_ENTRY2_CTRL4, 0x0693),
MAKE_REG(ACL_IP_RANGE_ENTRY3_CTRL0, 0x0694),
MAKE_REG(ACL_IP_RANGE_ENTRY3_CTRL1, 0x0695),
MAKE_REG(ACL_IP_RANGE_ENTRY3_CTRL2, 0x0696),
MAKE_REG(ACL_IP_RANGE_ENTRY3_CTRL3, 0x0697),
MAKE_REG(ACL_IP_RANGE_ENTRY3_CTRL4, 0x0698),
MAKE_REG(ACL_IP_RANGE_ENTRY4_CTRL0, 0x0699),
MAKE_REG(ACL_IP_RANGE_ENTRY4_CTRL1, 0x069a),
MAKE_REG(ACL_IP_RANGE_ENTRY4_CTRL2, 0x069b),
MAKE_REG(ACL_IP_RANGE_ENTRY4_CTRL3, 0x069c),
MAKE_REG(ACL_IP_RANGE_ENTRY4_CTRL4, 0x069d),
MAKE_REG(ACL_IP_RANGE_ENTRY5_CTRL0, 0x069e),
MAKE_REG(ACL_IP_RANGE_ENTRY5_CTRL1, 0x069f),
MAKE_REG(ACL_IP_RANGE_ENTRY5_CTRL2, 0x06a0),
MAKE_REG(ACL_IP_RANGE_ENTRY5_CTRL3, 0x06a1),
MAKE_REG(ACL_IP_RANGE_ENTRY5_CTRL4, 0x06a2),
MAKE_REG(ACL_IP_RANGE_ENTRY6_CTRL0, 0x06a3),
MAKE_REG(ACL_IP_RANGE_ENTRY6_CTRL1, 0x06a4),
MAKE_REG(ACL_IP_RANGE_ENTRY6_CTRL2, 0x06a5),
MAKE_REG(ACL_IP_RANGE_ENTRY6_CTRL3, 0x06a6),
MAKE_REG(ACL_IP_RANGE_ENTRY6_CTRL4, 0x06a7),
MAKE_REG(ACL_IP_RANGE_ENTRY7_CTRL0, 0x06a8),
MAKE_REG(ACL_IP_RANGE_ENTRY7_CTRL1, 0x06a9),
MAKE_REG(ACL_IP_RANGE_ENTRY7_CTRL2, 0x06aa),
MAKE_REG(ACL_IP_RANGE_ENTRY7_CTRL3, 0x06ab),
MAKE_REG(ACL_IP_RANGE_ENTRY7_CTRL4, 0x06ac),
MAKE_REG(ACL_IP_RANGE_ENTRY8_CTRL0, 0x06ad),
MAKE_REG(ACL_IP_RANGE_ENTRY8_CTRL1, 0x06ae),
MAKE_REG(ACL_IP_RANGE_ENTRY8_CTRL2, 0x06af),
MAKE_REG(ACL_IP_RANGE_ENTRY8_CTRL3, 0x06b0),
MAKE_REG(ACL_IP_RANGE_ENTRY8_CTRL4, 0x06b1),
MAKE_REG(ACL_IP_RANGE_ENTRY9_CTRL0, 0x06b2),
MAKE_REG(ACL_IP_RANGE_ENTRY9_CTRL1, 0x06b3),
MAKE_REG(ACL_IP_RANGE_ENTRY9_CTRL2, 0x06b4),
MAKE_REG(ACL_IP_RANGE_ENTRY9_CTRL3, 0x06b5),
MAKE_REG(ACL_IP_RANGE_ENTRY9_CTRL4, 0x06b6),
MAKE_REG(ACL_IP_RANGE_ENTRY10_CTRL0, 0x06b7),
MAKE_REG(ACL_IP_RANGE_ENTRY10_CTRL1, 0x06b8),
MAKE_REG(ACL_IP_RANGE_ENTRY10_CTRL2, 0x06b9),
MAKE_REG(ACL_IP_RANGE_ENTRY10_CTRL3, 0x06ba),
MAKE_REG(ACL_IP_RANGE_ENTRY10_CTRL4, 0x06bb),
MAKE_REG(ACL_IP_RANGE_ENTRY11_CTRL0, 0x06bc),
MAKE_REG(ACL_IP_RANGE_ENTRY11_CTRL1, 0x06bd),
MAKE_REG(ACL_IP_RANGE_ENTRY11_CTRL2, 0x06be),
MAKE_REG(ACL_IP_RANGE_ENTRY11_CTRL3, 0x06bf),
MAKE_REG(ACL_IP_RANGE_ENTRY11_CTRL4, 0x06c0),
MAKE_REG(ACL_IP_RANGE_ENTRY12_CTRL0, 0x06c1),
MAKE_REG(ACL_IP_RANGE_ENTRY12_CTRL1, 0x06c2),
MAKE_REG(ACL_IP_RANGE_ENTRY12_CTRL2, 0x06c3),
MAKE_REG(ACL_IP_RANGE_ENTRY12_CTRL3, 0x06c4),
MAKE_REG(ACL_IP_RANGE_ENTRY12_CTRL4, 0x06c5),
MAKE_REG(ACL_IP_RANGE_ENTRY13_CTRL0, 0x06c6),
MAKE_REG(ACL_IP_RANGE_ENTRY13_CTRL1, 0x06c7),
MAKE_REG(ACL_IP_RANGE_ENTRY13_CTRL2, 0x06c8),
MAKE_REG(ACL_IP_RANGE_ENTRY13_CTRL3, 0x06c9),
MAKE_REG(ACL_IP_RANGE_ENTRY13_CTRL4, 0x06ca),
MAKE_REG(ACL_IP_RANGE_ENTRY14_CTRL0, 0x06cb),
MAKE_REG(ACL_IP_RANGE_ENTRY14_CTRL1, 0x06cc),
MAKE_REG(ACL_IP_RANGE_ENTRY14_CTRL2, 0x06cd),
MAKE_REG(ACL_IP_RANGE_ENTRY14_CTRL3, 0x06ce),
MAKE_REG(ACL_IP_RANGE_ENTRY14_CTRL4, 0x06cf),
MAKE_REG(ACL_IP_RANGE_ENTRY15_CTRL0, 0x06d0),
MAKE_REG(ACL_IP_RANGE_ENTRY15_CTRL1, 0x06d1),
MAKE_REG(ACL_IP_RANGE_ENTRY15_CTRL2, 0x06d2),
MAKE_REG(ACL_IP_RANGE_ENTRY15_CTRL3, 0x06d3),
MAKE_REG(ACL_IP_RANGE_ENTRY15_CTRL4, 0x06d4),
MAKE_REG(ACL_ENABLE, 0x06d5),
MAKE_REG(ACL_UNMATCH_PERMIT, 0x06d6),
MAKE_REG(ACL_GPIO_POLARITY, 0x06d7),
MAKE_REG(ACL_LOG_CNT_TYPE, 0x06d8),
MAKE_REG(ACL_RESET_CFG, 0x06d9),
MAKE_REG(ACL_DUMMY00, 0x06E0),
MAKE_REG(ACL_DUMMY01, 0x06E1),
MAKE_REG(ACL_DUMMY02, 0x06E2),
MAKE_REG(ACL_DUMMY03, 0x06E3),
MAKE_REG(ACL_DUMMY04, 0x06E4),
MAKE_REG(ACL_DUMMY05, 0x06E5),
MAKE_REG(ACL_DUMMY06, 0x06E6),
MAKE_REG(ACL_DUMMY07, 0x06E7),
MAKE_REG(ACL_REASON_01, 0x06E8),
MAKE_REG(ACL_REASON_23, 0x06E9),
MAKE_REG(ACL_REASON_45, 0x06EA),
MAKE_REG(ACL_ACCESS_MODE, 0x06EB),
MAKE_REG(ACL_ACTION_CTRL32, 0x06F0),
MAKE_REG(ACL_ACTION_CTRL33, 0x06F1),
MAKE_REG(ACL_ACTION_CTRL34, 0x06F2),
MAKE_REG(ACL_ACTION_CTRL35, 0x06F3),
MAKE_REG(ACL_ACTION_CTRL36, 0x06F4),
MAKE_REG(ACL_ACTION_CTRL37, 0x06F5),
MAKE_REG(ACL_ACTION_CTRL38, 0x06F6),
MAKE_REG(ACL_ACTION_CTRL39, 0x06F7),
MAKE_REG(ACL_ACTION_CTRL40, 0x06F8),
MAKE_REG(ACL_ACTION_CTRL41, 0x06F9),
MAKE_REG(ACL_ACTION_CTRL42, 0x06FA),
MAKE_REG(ACL_ACTION_CTRL43, 0x06FB),
MAKE_REG(ACL_ACTION_CTRL44, 0x06FC),
MAKE_REG(ACL_ACTION_CTRL45, 0x06FD),
MAKE_REG(ACL_ACTION_CTRL46, 0x06FE),
MAKE_REG(ACL_ACTION_CTRL47, 0x06FF),
MAKE_REG(VLAN_PVID_CTRL0, 0x0700),
MAKE_REG(VLAN_PVID_CTRL1, 0x0701),
MAKE_REG(VLAN_PVID_CTRL2, 0x0702),
MAKE_REG(VLAN_PVID_CTRL3, 0x0703),
MAKE_REG(VLAN_PVID_CTRL4, 0x0704),
MAKE_REG(VLAN_PVID_CTRL5, 0x0705),
MAKE_REG(VLAN_PPB0_VALID, 0x0708),
MAKE_REG(VLAN_PPB0_CTRL0, 0x0709),
MAKE_REG(VLAN_PPB0_CTRL1, 0x070a),
MAKE_REG(VLAN_PPB0_CTRL2, 0x070b),
MAKE_REG(VLAN_PPB0_CTRL4, 0x070c),
MAKE_REG(VLAN_PPB0_CTRL3, 0x070f),
MAKE_REG(VLAN_PPB1_VALID, 0x0710),
MAKE_REG(VLAN_PPB1_CTRL0, 0x0711),
MAKE_REG(VLAN_PPB1_CTRL1, 0x0712),
MAKE_REG(VLAN_PPB1_CTRL2, 0x0713),
MAKE_REG(VLAN_PPB1_CTRL4, 0x0714),
MAKE_REG(VLAN_PPB1_CTRL3, 0x0717),
MAKE_REG(VLAN_PPB2_VALID, 0x0718),
MAKE_REG(VLAN_PPB2_CTRL0, 0x0719),
MAKE_REG(VLAN_PPB2_CTRL1, 0x071a),
MAKE_REG(VLAN_PPB2_CTRL2, 0x071b),
MAKE_REG(VLAN_PPB2_CTRL4, 0x071c),
MAKE_REG(VLAN_PPB2_CTRL3, 0x071f),
MAKE_REG(VLAN_PPB3_VALID, 0x0720),
MAKE_REG(VLAN_PPB3_CTRL0, 0x0721),
MAKE_REG(VLAN_PPB3_CTRL1, 0x0722),
MAKE_REG(VLAN_PPB3_CTRL2, 0x0723),
MAKE_REG(VLAN_PPB3_CTRL4, 0x0724),
MAKE_REG(VLAN_PPB3_CTRL3, 0x0727),
MAKE_REG(VLAN_MEMBER_CONFIGURATION0_CTRL0, 0x0728),
MAKE_REG(VLAN_MEMBER_CONFIGURATION0_CTRL1, 0x0729),
MAKE_REG(VLAN_MEMBER_CONFIGURATION0_CTRL2, 0x072a),
MAKE_REG(VLAN_MEMBER_CONFIGURATION0_CTRL3, 0x072b),
MAKE_REG(VLAN_MEMBER_CONFIGURATION1_CTRL0, 0x072c),
MAKE_REG(VLAN_MEMBER_CONFIGURATION1_CTRL1, 0x072d),
MAKE_REG(VLAN_MEMBER_CONFIGURATION1_CTRL2, 0x072e),
MAKE_REG(VLAN_MEMBER_CONFIGURATION1_CTRL3, 0x072f),
MAKE_REG(VLAN_MEMBER_CONFIGURATION2_CTRL0, 0x0730),
MAKE_REG(VLAN_MEMBER_CONFIGURATION2_CTRL1, 0x0731),
MAKE_REG(VLAN_MEMBER_CONFIGURATION2_CTRL2, 0x0732),
MAKE_REG(VLAN_MEMBER_CONFIGURATION2_CTRL3, 0x0733),
MAKE_REG(VLAN_MEMBER_CONFIGURATION3_CTRL0, 0x0734),
MAKE_REG(VLAN_MEMBER_CONFIGURATION3_CTRL1, 0x0735),
MAKE_REG(VLAN_MEMBER_CONFIGURATION3_CTRL2, 0x0736),
MAKE_REG(VLAN_MEMBER_CONFIGURATION3_CTRL3, 0x0737),
MAKE_REG(VLAN_MEMBER_CONFIGURATION4_CTRL0, 0x0738),
MAKE_REG(VLAN_MEMBER_CONFIGURATION4_CTRL1, 0x0739),
MAKE_REG(VLAN_MEMBER_CONFIGURATION4_CTRL2, 0x073a),
MAKE_REG(VLAN_MEMBER_CONFIGURATION4_CTRL3, 0x073b),
MAKE_REG(VLAN_MEMBER_CONFIGURATION5_CTRL0, 0x073c),
MAKE_REG(VLAN_MEMBER_CONFIGURATION5_CTRL1, 0x073d),
MAKE_REG(VLAN_MEMBER_CONFIGURATION5_CTRL2, 0x073e),
MAKE_REG(VLAN_MEMBER_CONFIGURATION5_CTRL3, 0x073f),
MAKE_REG(VLAN_MEMBER_CONFIGURATION6_CTRL0, 0x0740),
MAKE_REG(VLAN_MEMBER_CONFIGURATION6_CTRL1, 0x0741),
MAKE_REG(VLAN_MEMBER_CONFIGURATION6_CTRL2, 0x0742),
MAKE_REG(VLAN_MEMBER_CONFIGURATION6_CTRL3, 0x0743),
MAKE_REG(VLAN_MEMBER_CONFIGURATION7_CTRL0, 0x0744),
MAKE_REG(VLAN_MEMBER_CONFIGURATION7_CTRL1, 0x0745),
MAKE_REG(VLAN_MEMBER_CONFIGURATION7_CTRL2, 0x0746),
MAKE_REG(VLAN_MEMBER_CONFIGURATION7_CTRL3, 0x0747),
MAKE_REG(VLAN_MEMBER_CONFIGURATION8_CTRL0, 0x0748),
MAKE_REG(VLAN_MEMBER_CONFIGURATION8_CTRL1, 0x0749),
MAKE_REG(VLAN_MEMBER_CONFIGURATION8_CTRL2, 0x074a),
MAKE_REG(VLAN_MEMBER_CONFIGURATION8_CTRL3, 0x074b),
MAKE_REG(VLAN_MEMBER_CONFIGURATION9_CTRL0, 0x074c),
MAKE_REG(VLAN_MEMBER_CONFIGURATION9_CTRL1, 0x074d),
MAKE_REG(VLAN_MEMBER_CONFIGURATION9_CTRL2, 0x074e),
MAKE_REG(VLAN_MEMBER_CONFIGURATION9_CTRL3, 0x074f),
MAKE_REG(VLAN_MEMBER_CONFIGURATION10_CTRL0, 0x0750),
MAKE_REG(VLAN_MEMBER_CONFIGURATION10_CTRL1, 0x0751),
MAKE_REG(VLAN_MEMBER_CONFIGURATION10_CTRL2, 0x0752),
MAKE_REG(VLAN_MEMBER_CONFIGURATION10_CTRL3, 0x0753),
MAKE_REG(VLAN_MEMBER_CONFIGURATION11_CTRL0, 0x0754),
MAKE_REG(VLAN_MEMBER_CONFIGURATION11_CTRL1, 0x0755),
MAKE_REG(VLAN_MEMBER_CONFIGURATION11_CTRL2, 0x0756),
MAKE_REG(VLAN_MEMBER_CONFIGURATION11_CTRL3, 0x0757),
MAKE_REG(VLAN_MEMBER_CONFIGURATION12_CTRL0, 0x0758),
MAKE_REG(VLAN_MEMBER_CONFIGURATION12_CTRL1, 0x0759),
MAKE_REG(VLAN_MEMBER_CONFIGURATION12_CTRL2, 0x075a),
MAKE_REG(VLAN_MEMBER_CONFIGURATION12_CTRL3, 0x075b),
MAKE_REG(VLAN_MEMBER_CONFIGURATION13_CTRL0, 0x075c),
MAKE_REG(VLAN_MEMBER_CONFIGURATION13_CTRL1, 0x075d),
MAKE_REG(VLAN_MEMBER_CONFIGURATION13_CTRL2, 0x075e),
MAKE_REG(VLAN_MEMBER_CONFIGURATION13_CTRL3, 0x075f),
MAKE_REG(VLAN_MEMBER_CONFIGURATION14_CTRL0, 0x0760),
MAKE_REG(VLAN_MEMBER_CONFIGURATION14_CTRL1, 0x0761),
MAKE_REG(VLAN_MEMBER_CONFIGURATION14_CTRL2, 0x0762),
MAKE_REG(VLAN_MEMBER_CONFIGURATION14_CTRL3, 0x0763),
MAKE_REG(VLAN_MEMBER_CONFIGURATION15_CTRL0, 0x0764),
MAKE_REG(VLAN_MEMBER_CONFIGURATION15_CTRL1, 0x0765),
MAKE_REG(VLAN_MEMBER_CONFIGURATION15_CTRL2, 0x0766),
MAKE_REG(VLAN_MEMBER_CONFIGURATION15_CTRL3, 0x0767),
MAKE_REG(VLAN_MEMBER_CONFIGURATION16_CTRL0, 0x0768),
MAKE_REG(VLAN_MEMBER_CONFIGURATION16_CTRL1, 0x0769),
MAKE_REG(VLAN_MEMBER_CONFIGURATION16_CTRL2, 0x076a),
MAKE_REG(VLAN_MEMBER_CONFIGURATION16_CTRL3, 0x076b),
MAKE_REG(VLAN_MEMBER_CONFIGURATION17_CTRL0, 0x076c),
MAKE_REG(VLAN_MEMBER_CONFIGURATION17_CTRL1, 0x076d),
MAKE_REG(VLAN_MEMBER_CONFIGURATION17_CTRL2, 0x076e),
MAKE_REG(VLAN_MEMBER_CONFIGURATION17_CTRL3, 0x076f),
MAKE_REG(VLAN_MEMBER_CONFIGURATION18_CTRL0, 0x0770),
MAKE_REG(VLAN_MEMBER_CONFIGURATION18_CTRL1, 0x0771),
MAKE_REG(VLAN_MEMBER_CONFIGURATION18_CTRL2, 0x0772),
MAKE_REG(VLAN_MEMBER_CONFIGURATION18_CTRL3, 0x0773),
MAKE_REG(VLAN_MEMBER_CONFIGURATION19_CTRL0, 0x0774),
MAKE_REG(VLAN_MEMBER_CONFIGURATION19_CTRL1, 0x0775),
MAKE_REG(VLAN_MEMBER_CONFIGURATION19_CTRL2, 0x0776),
MAKE_REG(VLAN_MEMBER_CONFIGURATION19_CTRL3, 0x0777),
MAKE_REG(VLAN_MEMBER_CONFIGURATION20_CTRL0, 0x0778),
MAKE_REG(VLAN_MEMBER_CONFIGURATION20_CTRL1, 0x0779),
MAKE_REG(VLAN_MEMBER_CONFIGURATION20_CTRL2, 0x077a),
MAKE_REG(VLAN_MEMBER_CONFIGURATION20_CTRL3, 0x077b),
MAKE_REG(VLAN_MEMBER_CONFIGURATION21_CTRL0, 0x077c),
MAKE_REG(VLAN_MEMBER_CONFIGURATION21_CTRL1, 0x077d),
MAKE_REG(VLAN_MEMBER_CONFIGURATION21_CTRL2, 0x077e),
MAKE_REG(VLAN_MEMBER_CONFIGURATION21_CTRL3, 0x077f),
MAKE_REG(VLAN_MEMBER_CONFIGURATION22_CTRL0, 0x0780),
MAKE_REG(VLAN_MEMBER_CONFIGURATION22_CTRL1, 0x0781),
MAKE_REG(VLAN_MEMBER_CONFIGURATION22_CTRL2, 0x0782),
MAKE_REG(VLAN_MEMBER_CONFIGURATION22_CTRL3, 0x0783),
MAKE_REG(VLAN_MEMBER_CONFIGURATION23_CTRL0, 0x0784),
MAKE_REG(VLAN_MEMBER_CONFIGURATION23_CTRL1, 0x0785),
MAKE_REG(VLAN_MEMBER_CONFIGURATION23_CTRL2, 0x0786),
MAKE_REG(VLAN_MEMBER_CONFIGURATION23_CTRL3, 0x0787),
MAKE_REG(VLAN_MEMBER_CONFIGURATION24_CTRL0, 0x0788),
MAKE_REG(VLAN_MEMBER_CONFIGURATION24_CTRL1, 0x0789),
MAKE_REG(VLAN_MEMBER_CONFIGURATION24_CTRL2, 0x078a),
MAKE_REG(VLAN_MEMBER_CONFIGURATION24_CTRL3, 0x078b),
MAKE_REG(VLAN_MEMBER_CONFIGURATION25_CTRL0, 0x078c),
MAKE_REG(VLAN_MEMBER_CONFIGURATION25_CTRL1, 0x078d),
MAKE_REG(VLAN_MEMBER_CONFIGURATION25_CTRL2, 0x078e),
MAKE_REG(VLAN_MEMBER_CONFIGURATION25_CTRL3, 0x078f),
MAKE_REG(VLAN_MEMBER_CONFIGURATION26_CTRL0, 0x0790),
MAKE_REG(VLAN_MEMBER_CONFIGURATION26_CTRL1, 0x0791),
MAKE_REG(VLAN_MEMBER_CONFIGURATION26_CTRL2, 0x0792),
MAKE_REG(VLAN_MEMBER_CONFIGURATION26_CTRL3, 0x0793),
MAKE_REG(VLAN_MEMBER_CONFIGURATION27_CTRL0, 0x0794),
MAKE_REG(VLAN_MEMBER_CONFIGURATION27_CTRL1, 0x0795),
MAKE_REG(VLAN_MEMBER_CONFIGURATION27_CTRL2, 0x0796),
MAKE_REG(VLAN_MEMBER_CONFIGURATION27_CTRL3, 0x0797),
MAKE_REG(VLAN_MEMBER_CONFIGURATION28_CTRL0, 0x0798),
MAKE_REG(VLAN_MEMBER_CONFIGURATION28_CTRL1, 0x0799),
MAKE_REG(VLAN_MEMBER_CONFIGURATION28_CTRL2, 0x079a),
MAKE_REG(VLAN_MEMBER_CONFIGURATION28_CTRL3, 0x079b),
MAKE_REG(VLAN_MEMBER_CONFIGURATION29_CTRL0, 0x079c),
MAKE_REG(VLAN_MEMBER_CONFIGURATION29_CTRL1, 0x079d),
MAKE_REG(VLAN_MEMBER_CONFIGURATION29_CTRL2, 0x079e),
MAKE_REG(VLAN_MEMBER_CONFIGURATION29_CTRL3, 0x079f),
MAKE_REG(VLAN_MEMBER_CONFIGURATION30_CTRL0, 0x07a0),
MAKE_REG(VLAN_MEMBER_CONFIGURATION30_CTRL1, 0x07a1),
MAKE_REG(VLAN_MEMBER_CONFIGURATION30_CTRL2, 0x07a2),
MAKE_REG(VLAN_MEMBER_CONFIGURATION30_CTRL3, 0x07a3),
MAKE_REG(VLAN_MEMBER_CONFIGURATION31_CTRL0, 0x07a4),
MAKE_REG(VLAN_MEMBER_CONFIGURATION31_CTRL1, 0x07a5),
MAKE_REG(VLAN_MEMBER_CONFIGURATION31_CTRL2, 0x07a6),
MAKE_REG(VLAN_MEMBER_CONFIGURATION31_CTRL3, 0x07a7),
MAKE_REG(VLAN_CTRL, 0x07a8),
MAKE_REG(VLAN_INGRESS, 0x07a9),
MAKE_REG(VLAN_ACCEPT_FRAME_TYPE_CTRL0, 0x07aa),
MAKE_REG(VLAN_ACCEPT_FRAME_TYPE_CTRL1, 0x07ab),
MAKE_REG(PORT_PBFIDEN, 0x07ac),
MAKE_REG(PORT0_PBFID, 0x07ad),
MAKE_REG(PORT1_PBFID, 0x07ae),
MAKE_REG(PORT2_PBFID, 0x07af),
MAKE_REG(PORT3_PBFID, 0x07b0),
MAKE_REG(PORT4_PBFID, 0x07b1),
MAKE_REG(PORT5_PBFID, 0x07b2),
MAKE_REG(PORT6_PBFID, 0x07b3),
MAKE_REG(PORT7_PBFID, 0x07b4),
MAKE_REG(VLAN_EXT_CTRL, 0x07b5),
MAKE_REG(VLAN_EXT_CTRL2, 0x07b6),
MAKE_REG(PORT8_PBFID, 0x07b7),
MAKE_REG(PORT9_PBFID, 0x07b8),
MAKE_REG(PORT10_PBFID, 0x07b9),
MAKE_REG(CVLAN_DUMMY00, 0x07E0),
MAKE_REG(CVLAN_DUMMY01, 0x07E1),
MAKE_REG(CVLAN_DUMMY02, 0x07E2),
MAKE_REG(CVLAN_DUMMY03, 0x07E3),
MAKE_REG(CVLAN_DUMMY04, 0x07E4),
MAKE_REG(CVLAN_DUMMY05, 0x07E5),
MAKE_REG(CVLAN_DUMMY06, 0x07E6),
MAKE_REG(CVLAN_DUMMY07, 0x07E7),
MAKE_REG(CVLAN_DUMMY08, 0x07E8),
MAKE_REG(CVLAN_DUMMY09, 0x07E9),
MAKE_REG(CVLAN_DUMMY10, 0x07EA),
MAKE_REG(CVLAN_DUMMY11, 0x07EB),
MAKE_REG(CVLAN_DUMMY12, 0x07EC),
MAKE_REG(CVLAN_DUMMY13, 0x07ED),
MAKE_REG(CVLAN_DUMMY14, 0x07EE),
MAKE_REG(CVLAN_DUMMY15, 0x07EF),
MAKE_REG(RMA_CTRL00, 0x0800),
MAKE_REG(RMA_CTRL01, 0x0801),
MAKE_REG(RMA_CTRL02, 0x0802),
MAKE_REG(RMA_CTRL03, 0x0803),
MAKE_REG(RMA_CTRL04, 0x0804),
MAKE_REG(RMA_CTRL08, 0x0808),
MAKE_REG(RMA_CTRL0D, 0x080d),
MAKE_REG(RMA_CTRL0E, 0x080e),
MAKE_REG(RMA_CTRL10, 0x0810),
MAKE_REG(RMA_CTRL11, 0x0811),
MAKE_REG(RMA_CTRL12, 0x0812),
MAKE_REG(RMA_CTRL13, 0x0813),
MAKE_REG(RMA_CTRL18, 0x0818),
MAKE_REG(RMA_CTRL1A, 0x081a),
MAKE_REG(RMA_CTRL20, 0x0820),
MAKE_REG(RMA_CTRL21, 0x0821),
MAKE_REG(RMA_CTRL22, 0x0822),
MAKE_REG(RMA_CTRL_CDP, 0x0830),
MAKE_REG(RMA_CTRL_CSSTP, 0x0831),
MAKE_REG(RMA_CTRL_LLDP, 0x0832),
MAKE_REG(RMA_LLDP_EN, 0x0833),
MAKE_REG(VLAN_PORTBASED_PRIORITY_CTRL0, 0x0851),
MAKE_REG(VLAN_PORTBASED_PRIORITY_CTRL1, 0x0852),
MAKE_REG(VLAN_PORTBASED_PRIORITY_CTRL2, 0x0853),
MAKE_REG(VLAN_PPB_PRIORITY_ITEM0_CTRL0, 0x0855),
MAKE_REG(VLAN_PPB_PRIORITY_ITEM0_CTRL1, 0x0856),
MAKE_REG(VLAN_PPB_PRIORITY_ITEM0_CTRL2, 0x0857),
MAKE_REG(VLAN_PPB_PRIORITY_ITEM1_CTRL0, 0x0859),
MAKE_REG(VLAN_PPB_PRIORITY_ITEM1_CTRL1, 0x085a),
MAKE_REG(VLAN_PPB_PRIORITY_ITEM1_CTRL2, 0x085b),
MAKE_REG(VLAN_PPB_PRIORITY_ITEM2_CTRL0, 0x085d),
MAKE_REG(VLAN_PPB_PRIORITY_ITEM2_CTRL1, 0x085e),
MAKE_REG(VLAN_PPB_PRIORITY_ITEM2_CTRL2, 0x085f),
MAKE_REG(VLAN_PPB_PRIORITY_ITEM3_CTRL0, 0x0861),
MAKE_REG(VLAN_PPB_PRIORITY_ITEM3_CTRL1, 0x0862),
MAKE_REG(VLAN_PPB_PRIORITY_ITEM3_CTRL2, 0x0863),
MAKE_REG(QOS_1Q_PRIORITY_REMAPPING_CTRL0, 0x0865),
MAKE_REG(QOS_1Q_PRIORITY_REMAPPING_CTRL1, 0x0866),
MAKE_REG(QOS_DSCP_TO_PRIORITY_CTRL0, 0x0867),
MAKE_REG(QOS_DSCP_TO_PRIORITY_CTRL1, 0x0868),
MAKE_REG(QOS_DSCP_TO_PRIORITY_CTRL2, 0x0869),
MAKE_REG(QOS_DSCP_TO_PRIORITY_CTRL3, 0x086a),
MAKE_REG(QOS_DSCP_TO_PRIORITY_CTRL4, 0x086b),
MAKE_REG(QOS_DSCP_TO_PRIORITY_CTRL5, 0x086c),
MAKE_REG(QOS_DSCP_TO_PRIORITY_CTRL6, 0x086d),
MAKE_REG(QOS_DSCP_TO_PRIORITY_CTRL7, 0x086e),
MAKE_REG(QOS_DSCP_TO_PRIORITY_CTRL8, 0x086f),
MAKE_REG(QOS_DSCP_TO_PRIORITY_CTRL9, 0x0870),
MAKE_REG(QOS_DSCP_TO_PRIORITY_CTRL10, 0x0871),
MAKE_REG(QOS_DSCP_TO_PRIORITY_CTRL11, 0x0872),
MAKE_REG(QOS_DSCP_TO_PRIORITY_CTRL12, 0x0873),
MAKE_REG(QOS_DSCP_TO_PRIORITY_CTRL13, 0x0874),
MAKE_REG(QOS_DSCP_TO_PRIORITY_CTRL14, 0x0875),
MAKE_REG(QOS_DSCP_TO_PRIORITY_CTRL15, 0x0876),
MAKE_REG(QOS_PORTBASED_PRIORITY_CTRL0, 0x0877),
MAKE_REG(QOS_PORTBASED_PRIORITY_CTRL1, 0x0878),
MAKE_REG(DUMMY0879, 0x0879),
MAKE_REG(QOS_PORTBASED_PRIORITY_CTRL2, 0x087a),
MAKE_REG(QOS_INTERNAL_PRIORITY_DECISION_CTRL0, 0x087b),
MAKE_REG(QOS_INTERNAL_PRIORITY_DECISION_CTRL1, 0x087c),
MAKE_REG(QOS_INTERNAL_PRIORITY_DECISION_CTRL2, 0x087d),
MAKE_REG(QOS_INTERNAL_PRIORITY_DECISION_CTRL3, 0x087e),
MAKE_REG(QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0, 0x087f),
MAKE_REG(QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1, 0x0880),
MAKE_REG(QOS_TRAP_PRIORITY0, 0x0881),
MAKE_REG(QOS_TRAP_PRIORITY1, 0x0882),
MAKE_REG(MAX_LENGTH_CFG, 0x0883),
MAKE_REG(MAX_LEN_RX_TX, 0x0884),
MAKE_REG(QOS_INTERNAL_PRIORITY_DECISION2_CTRL0, 0x0885),
MAKE_REG(QOS_INTERNAL_PRIORITY_DECISION2_CTRL1, 0x0886),
MAKE_REG(QOS_INTERNAL_PRIORITY_DECISION2_CTRL2, 0x0887),
MAKE_REG(QOS_INTERNAL_PRIORITY_DECISION2_CTRL3, 0x0888),
MAKE_REG(QOS_INTERNAL_PRIORITY_DECISION_IDX, 0x0889),
MAKE_REG(MAX_LENGTH_CFG_EXT, 0x088a),
MAKE_REG(MAX_LEN_RX_TX_CFG0, 0x088c),
MAKE_REG(MAX_LEN_RX_TX_CFG1, 0x088d),
MAKE_REG(UNDA_FLOODING_PMSK, 0x0890),
MAKE_REG(UNMCAST_FLOADING_PMSK, 0x0891),
MAKE_REG(BCAST_FLOADING_PMSK, 0x0892),
MAKE_REG(PORT_TRUNK_HASH_MAPPING_CTRL2, 0x08a0),
MAKE_REG(PORT_TRUNK_HASH_MAPPING_CTRL3, 0x08a1),
MAKE_REG(PORT_ISOLATION_PORT0_MASK, 0x08a2),
MAKE_REG(PORT_ISOLATION_PORT1_MASK, 0x08a3),
MAKE_REG(PORT_ISOLATION_PORT2_MASK, 0x08a4),
MAKE_REG(PORT_ISOLATION_PORT3_MASK, 0x08a5),
MAKE_REG(PORT_ISOLATION_PORT4_MASK, 0x08a6),
MAKE_REG(PORT_ISOLATION_PORT5_MASK, 0x08a7),
MAKE_REG(PORT_ISOLATION_PORT6_MASK, 0x08a8),
MAKE_REG(PORT_ISOLATION_PORT7_MASK, 0x08a9),
MAKE_REG(PORT_ISOLATION_PORT8_MASK, 0x08aa),
MAKE_REG(PORT_ISOLATION_PORT9_MASK, 0x08ab),
MAKE_REG(PORT_ISOLATION_PORT10_MASK, 0x08ac),
MAKE_REG(FORCE_CTRL, 0x08b4),
MAKE_REG(FORCE_PORT0_MASK, 0x08b5),
MAKE_REG(FORCE_PORT1_MASK, 0x08b6),
MAKE_REG(FORCE_PORT2_MASK, 0x08b7),
MAKE_REG(FORCE_PORT3_MASK, 0x08b8),
MAKE_REG(FORCE_PORT4_MASK, 0x08b9),
MAKE_REG(FORCE_PORT5_MASK, 0x08ba),
MAKE_REG(FORCE_PORT6_MASK, 0x08bb),
MAKE_REG(FORCE_PORT7_MASK, 0x08bc),
MAKE_REG(FORCE_PORT8_MASK, 0x08bd),
MAKE_REG(FORCE_PORT9_MASK, 0x08be),
MAKE_REG(FORCE_PORT10_MASK, 0x08bf),
MAKE_REG(SOURCE_PORT_PERMIT, 0x08c5),
MAKE_REG(IPMCAST_VLAN_LEAKY, 0x08c6),
MAKE_REG(IPMCAST_PORTISO_LEAKY, 0x08c7),
MAKE_REG(PORT_SECURITY_CTRL, 0x08c8),
MAKE_REG(UNKNOWN_IPV4_MULTICAST_CTRL0, 0x08c9),
MAKE_REG(UNKNOWN_IPV4_MULTICAST_CTRL1, 0x08ca),
MAKE_REG(UNKNOWN_IPV6_MULTICAST_CTRL0, 0x08cb),
MAKE_REG(UNKNOWN_IPV6_MULTICAST_CTRL1, 0x08cc),
MAKE_REG(UNKNOWN_L2_MULTICAST_CTRL0, 0x08cd),
MAKE_REG(PORT_TRUNK_DROP_CTRL, 0x08ce),
MAKE_REG(PORT_TRUNK_CTRL, 0x08cf),
MAKE_REG(PORT_TRUNK_GROUP_MASK, 0x08d0),
MAKE_REG(PORT_TRUNK_FLOWCTRL, 0x08d1),
MAKE_REG(PORT_TRUNK_HASH_MAPPING_CTRL0, 0x08d2),
MAKE_REG(PORT_TRUNK_HASH_MAPPING_CTRL1, 0x08d3),
MAKE_REG(DOS_CFG, 0x08d4),
MAKE_REG(UNKNOWN_L2_MULTICAST_CTRL1, 0x08d5),
MAKE_REG(VLAN_EGRESS_KEEP_CTRL4, 0x08d6),
MAKE_REG(VLAN_EGRESS_KEEP_CTRL5, 0x08d7),
MAKE_REG(VLAN_EGRESS_KEEP_CTRL0_EXT, 0x08d8),
MAKE_REG(VLAN_EGRESS_KEEP_CTRL1_EXT, 0x08d9),
MAKE_REG(VLAN_EGRESS_KEEP_CTRL2_EXT, 0x08da),
MAKE_REG(VLAN_EGRESS_KEEP_CTRL3_EXT, 0x08db),
MAKE_REG(VLAN_EGRESS_KEEP_CTRL4_EXT, 0x08dc),
MAKE_REG(VLAN_EGRESS_KEEP_CTRL5_EXT, 0x08dd),
MAKE_REG(VLAN_EGRESS_TRANS_CTRL10, 0x08de),
MAKE_REG(FPGA_VER_CEN, 0x08e0),
MAKE_REG(FPGA_TIME_CEN, 0x08e1),
MAKE_REG(FPGA_DATE_CEN, 0x08e2),
MAKE_REG(QOS_PORT_QUEUE_NUMBER_CTRL0, 0x0900),
MAKE_REG(QOS_PORT_QUEUE_NUMBER_CTRL1, 0x0901),
MAKE_REG(QOS_PORT_QUEUE_NUMBER_CTRL2, 0x0902),
MAKE_REG(QOS_1Q_PRIORITY_TO_QID_CTRL0, 0x0904),
MAKE_REG(QOS_1Q_PRIORITY_TO_QID_CTRL1, 0x0905),
MAKE_REG(QOS_2Q_PRIORITY_TO_QID_CTRL0, 0x0906),
MAKE_REG(QOS_2Q_PRIORITY_TO_QID_CTRL1, 0x0907),
MAKE_REG(QOS_3Q_PRIORITY_TO_QID_CTRL0, 0x0908),
MAKE_REG(QOS_3Q_PRIORITY_TO_QID_CTRL1, 0x0909),
MAKE_REG(QOS_4Q_PRIORITY_TO_QID_CTRL0, 0x090a),
MAKE_REG(QOS_4Q_PRIORITY_TO_QID_CTRL1, 0x090b),
MAKE_REG(QOS_5Q_PRIORITY_TO_QID_CTRL0, 0x090c),
MAKE_REG(QOS_5Q_PRIORITY_TO_QID_CTRL1, 0x090d),
MAKE_REG(QOS_6Q_PRIORITY_TO_QID_CTRL0, 0x090e),
MAKE_REG(QOS_6Q_PRIORITY_TO_QID_CTRL1, 0x090f),
MAKE_REG(QOS_7Q_PRIORITY_TO_QID_CTRL0, 0x0910),
MAKE_REG(QOS_7Q_PRIORITY_TO_QID_CTRL1, 0x0911),
MAKE_REG(QOS_8Q_PRIORITY_TO_QID_CTRL0, 0x0912),
MAKE_REG(QOS_8Q_PRIORITY_TO_QID_CTRL1, 0x0913),
MAKE_REG(HIGHPRI_INDICATOR, 0x0915),
MAKE_REG(HIGHPRI_CFG, 0x0916),
MAKE_REG(PORT_DEBUG_INFO_CTRL0, 0x0917),
MAKE_REG(PORT_DEBUG_INFO_CTRL1, 0x0918),
MAKE_REG(PORT_DEBUG_INFO_CTRL2, 0x0919),
MAKE_REG(PORT_DEBUG_INFO_CTRL3, 0x091a),
MAKE_REG(PORT_DEBUG_INFO_CTRL4, 0x091b),
MAKE_REG(PORT_DEBUG_INFO_CTRL5, 0x091c),
MAKE_REG(PORT_DEBUG_INFO_CTRL6, 0x091d),
MAKE_REG(PORT_DEBUG_INFO_CTRL7, 0x091e),
MAKE_REG(FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL0, 0x0930),
MAKE_REG(FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL1, 0x0931),
MAKE_REG(FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL2, 0x0932),
MAKE_REG(FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL3, 0x0933),
MAKE_REG(FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL4, 0x0934),
MAKE_REG(FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL5, 0x0935),
MAKE_REG(FLOWCRTL_EGRESS_PORT_ENABLE, 0x0938),
MAKE_REG(EAV_CTRL, 0x0939),
MAKE_REG(UNTAG_DSCP_PRI_CFG, 0x093a),
MAKE_REG(VLAN_EGRESS_KEEP_CTRL0, 0x093b),
MAKE_REG(VLAN_EGRESS_KEEP_CTRL1, 0x093c),
MAKE_REG(VLAN_EGRESS_KEEP_CTRL2, 0x093d),
MAKE_REG(VLAN_EGRESS_KEEP_CTRL3, 0x093e),
MAKE_REG(VLAN_TRANSPARENT_EN_CFG, 0x093f),
MAKE_REG(IPMC_GROUP_ENTRY0_H, 0x0940),
MAKE_REG(IPMC_GROUP_ENTRY0_L, 0x0941),
MAKE_REG(IPMC_GROUP_ENTRY1_H, 0x0942),
MAKE_REG(IPMC_GROUP_ENTRY1_L, 0x0943),
MAKE_REG(IPMC_GROUP_ENTRY2_H, 0x0944),
MAKE_REG(IPMC_GROUP_ENTRY2_L, 0x0945),
MAKE_REG(IPMC_GROUP_ENTRY3_H, 0x0946),
MAKE_REG(IPMC_GROUP_ENTRY3_L, 0x0947),
MAKE_REG(IPMC_GROUP_ENTRY4_H, 0x0948),
MAKE_REG(IPMC_GROUP_ENTRY4_L, 0x0949),
MAKE_REG(IPMC_GROUP_ENTRY5_H, 0x094a),
MAKE_REG(IPMC_GROUP_ENTRY5_L, 0x094b),
MAKE_REG(IPMC_GROUP_ENTRY6_H, 0x094c),
MAKE_REG(IPMC_GROUP_ENTRY6_L, 0x094d),
MAKE_REG(IPMC_GROUP_ENTRY7_H, 0x094e),
MAKE_REG(IPMC_GROUP_ENTRY7_L, 0x094f),
MAKE_REG(IPMC_GROUP_ENTRY8_H, 0x0950),
MAKE_REG(IPMC_GROUP_ENTRY8_L, 0x0951),
MAKE_REG(IPMC_GROUP_ENTRY9_H, 0x0952),
MAKE_REG(IPMC_GROUP_ENTRY9_L, 0x0953),
MAKE_REG(IPMC_GROUP_ENTRY10_H, 0x0954),
MAKE_REG(IPMC_GROUP_ENTRY10_L, 0x0955),
MAKE_REG(IPMC_GROUP_ENTRY11_H, 0x0956),
MAKE_REG(IPMC_GROUP_ENTRY11_L, 0x0957),
MAKE_REG(IPMC_GROUP_ENTRY12_H, 0x0958),
MAKE_REG(IPMC_GROUP_ENTRY12_L, 0x0959),
MAKE_REG(IPMC_GROUP_ENTRY13_H, 0x095a),
MAKE_REG(IPMC_GROUP_ENTRY13_L, 0x095b),
MAKE_REG(IPMC_GROUP_ENTRY14_H, 0x095c),
MAKE_REG(IPMC_GROUP_ENTRY14_L, 0x095d),
MAKE_REG(IPMC_GROUP_ENTRY15_H, 0x095e),
MAKE_REG(IPMC_GROUP_ENTRY15_L, 0x095f),
MAKE_REG(IPMC_GROUP_ENTRY16_H, 0x0960),
MAKE_REG(IPMC_GROUP_ENTRY16_L, 0x0961),
MAKE_REG(IPMC_GROUP_ENTRY17_H, 0x0962),
MAKE_REG(IPMC_GROUP_ENTRY17_L, 0x0963),
MAKE_REG(IPMC_GROUP_ENTRY18_H, 0x0964),
MAKE_REG(IPMC_GROUP_ENTRY18_L, 0x0965),
MAKE_REG(IPMC_GROUP_ENTRY19_H, 0x0966),
MAKE_REG(IPMC_GROUP_ENTRY19_L, 0x0967),
MAKE_REG(IPMC_GROUP_ENTRY20_H, 0x0968),
MAKE_REG(IPMC_GROUP_ENTRY20_L, 0x0969),
MAKE_REG(IPMC_GROUP_ENTRY21_H, 0x096a),
MAKE_REG(IPMC_GROUP_ENTRY21_L, 0x096b),
MAKE_REG(IPMC_GROUP_ENTRY22_H, 0x096c),
MAKE_REG(IPMC_GROUP_ENTRY22_L, 0x096d),
MAKE_REG(IPMC_GROUP_ENTRY23_H, 0x096e),
MAKE_REG(IPMC_GROUP_ENTRY23_L, 0x096f),
MAKE_REG(IPMC_GROUP_ENTRY24_H, 0x0970),
MAKE_REG(IPMC_GROUP_ENTRY24_L, 0x0971),
MAKE_REG(IPMC_GROUP_ENTRY25_H, 0x0972),
MAKE_REG(IPMC_GROUP_ENTRY25_L, 0x0973),
MAKE_REG(IPMC_GROUP_ENTRY26_H, 0x0974),
MAKE_REG(IPMC_GROUP_ENTRY26_L, 0x0975),
MAKE_REG(IPMC_GROUP_ENTRY27_H, 0x0976),
MAKE_REG(IPMC_GROUP_ENTRY27_L, 0x0977),
MAKE_REG(IPMC_GROUP_ENTRY28_H, 0x0978),
MAKE_REG(IPMC_GROUP_ENTRY28_L, 0x0979),
MAKE_REG(IPMC_GROUP_ENTRY29_H, 0x097a),
MAKE_REG(IPMC_GROUP_ENTRY29_L, 0x097b),
MAKE_REG(IPMC_GROUP_ENTRY30_H, 0x097c),
MAKE_REG(IPMC_GROUP_ENTRY30_L, 0x097d),
MAKE_REG(IPMC_GROUP_ENTRY31_H, 0x097e),
MAKE_REG(IPMC_GROUP_ENTRY31_L, 0x097f),
MAKE_REG(IPMC_GROUP_ENTRY32_H, 0x0980),
MAKE_REG(IPMC_GROUP_ENTRY32_L, 0x0981),
MAKE_REG(IPMC_GROUP_ENTRY33_H, 0x0982),
MAKE_REG(IPMC_GROUP_ENTRY33_L, 0x0983),
MAKE_REG(IPMC_GROUP_ENTRY34_H, 0x0984),
MAKE_REG(IPMC_GROUP_ENTRY34_L, 0x0985),
MAKE_REG(IPMC_GROUP_ENTRY35_H, 0x0986),
MAKE_REG(IPMC_GROUP_ENTRY35_L, 0x0987),
MAKE_REG(IPMC_GROUP_ENTRY36_H, 0x0988),
MAKE_REG(IPMC_GROUP_ENTRY36_L, 0x0989),
MAKE_REG(IPMC_GROUP_ENTRY37_H, 0x098a),
MAKE_REG(IPMC_GROUP_ENTRY37_L, 0x098b),
MAKE_REG(IPMC_GROUP_ENTRY38_H, 0x098c),
MAKE_REG(IPMC_GROUP_ENTRY38_L, 0x098d),
MAKE_REG(IPMC_GROUP_ENTRY39_H, 0x098e),
MAKE_REG(IPMC_GROUP_ENTRY39_L, 0x098f),
MAKE_REG(IPMC_GROUP_ENTRY40_H, 0x0990),
MAKE_REG(IPMC_GROUP_ENTRY40_L, 0x0991),
MAKE_REG(IPMC_GROUP_ENTRY41_H, 0x0992),
MAKE_REG(IPMC_GROUP_ENTRY41_L, 0x0993),
MAKE_REG(IPMC_GROUP_ENTRY42_H, 0x0994),
MAKE_REG(IPMC_GROUP_ENTRY42_L, 0x0995),
MAKE_REG(IPMC_GROUP_ENTRY43_H, 0x0996),
MAKE_REG(IPMC_GROUP_ENTRY43_L, 0x0997),
MAKE_REG(IPMC_GROUP_ENTRY44_H, 0x0998),
MAKE_REG(IPMC_GROUP_ENTRY44_L, 0x0999),
MAKE_REG(IPMC_GROUP_ENTRY45_H, 0x099a),
MAKE_REG(IPMC_GROUP_ENTRY45_L, 0x099b),
MAKE_REG(IPMC_GROUP_ENTRY46_H, 0x099c),
MAKE_REG(IPMC_GROUP_ENTRY46_L, 0x099d),
MAKE_REG(IPMC_GROUP_ENTRY47_H, 0x099e),
MAKE_REG(IPMC_GROUP_ENTRY47_L, 0x099f),
MAKE_REG(IPMC_GROUP_ENTRY48_H, 0x09a0),
MAKE_REG(IPMC_GROUP_ENTRY48_L, 0x09a1),
MAKE_REG(IPMC_GROUP_ENTRY49_H, 0x09a2),
MAKE_REG(IPMC_GROUP_ENTRY49_L, 0x09a3),
MAKE_REG(IPMC_GROUP_ENTRY50_H, 0x09a4),
MAKE_REG(IPMC_GROUP_ENTRY50_L, 0x09a5),
MAKE_REG(IPMC_GROUP_ENTRY51_H, 0x09a6),
MAKE_REG(IPMC_GROUP_ENTRY51_L, 0x09a7),
MAKE_REG(IPMC_GROUP_ENTRY52_H, 0x09a8),
MAKE_REG(IPMC_GROUP_ENTRY52_L, 0x09a9),
MAKE_REG(IPMC_GROUP_ENTRY53_H, 0x09aa),
MAKE_REG(IPMC_GROUP_ENTRY53_L, 0x09ab),
MAKE_REG(IPMC_GROUP_ENTRY54_H, 0x09ac),
MAKE_REG(IPMC_GROUP_ENTRY54_L, 0x09ad),
MAKE_REG(IPMC_GROUP_ENTRY55_H, 0x09ae),
MAKE_REG(IPMC_GROUP_ENTRY55_L, 0x09af),
MAKE_REG(IPMC_GROUP_ENTRY56_H, 0x09b0),
MAKE_REG(IPMC_GROUP_ENTRY56_L, 0x09b1),
MAKE_REG(IPMC_GROUP_ENTRY57_H, 0x09b2),
MAKE_REG(IPMC_GROUP_ENTRY57_L, 0x09b3),
MAKE_REG(IPMC_GROUP_ENTRY58_H, 0x09b4),
MAKE_REG(IPMC_GROUP_ENTRY58_L, 0x09b5),
MAKE_REG(IPMC_GROUP_ENTRY59_H, 0x09b6),
MAKE_REG(IPMC_GROUP_ENTRY59_L, 0x09b7),
MAKE_REG(IPMC_GROUP_ENTRY60_H, 0x09b8),
MAKE_REG(IPMC_GROUP_ENTRY60_L, 0x09b9),
MAKE_REG(IPMC_GROUP_ENTRY61_H, 0x09ba),
MAKE_REG(IPMC_GROUP_ENTRY61_L, 0x09bb),
MAKE_REG(IPMC_GROUP_ENTRY62_H, 0x09bc),
MAKE_REG(IPMC_GROUP_ENTRY62_L, 0x09bd),
MAKE_REG(IPMC_GROUP_ENTRY63_H, 0x09be),
MAKE_REG(IPMC_GROUP_ENTRY63_L, 0x09bf),
MAKE_REG(UNKNOWN_UNICAST_DA_PORT_BEHAVE, 0x09C0),
MAKE_REG(MIRROR_CTRL3, 0x09C1),
MAKE_REG(DPM_DUMMY02, 0x09C2),
MAKE_REG(DPM_DUMMY03, 0x09C3),
MAKE_REG(DPM_DUMMY04, 0x09C4),
MAKE_REG(DPM_DUMMY05, 0x09C5),
MAKE_REG(DPM_DUMMY06, 0x09C6),
MAKE_REG(DPM_DUMMY07, 0x09C7),
MAKE_REG(DPM_DUMMY08, 0x09C8),
MAKE_REG(DPM_DUMMY09, 0x09C9),
MAKE_REG(DPM_DUMMY10, 0x09CA),
MAKE_REG(DPM_DUMMY11, 0x09CB),
MAKE_REG(DPM_DUMMY12, 0x09CC),
MAKE_REG(DPM_DUMMY13, 0x09CD),
MAKE_REG(DPM_DUMMY14, 0x09CE),
MAKE_REG(DPM_DUMMY15, 0x09CF),
MAKE_REG(VLAN_EGRESS_TRANS_CTRL0, 0x09D0),
MAKE_REG(VLAN_EGRESS_TRANS_CTRL1, 0x09D1),
MAKE_REG(VLAN_EGRESS_TRANS_CTRL2, 0x09D2),
MAKE_REG(VLAN_EGRESS_TRANS_CTRL3, 0x09D3),
MAKE_REG(VLAN_EGRESS_TRANS_CTRL4, 0x09D4),
MAKE_REG(VLAN_EGRESS_TRANS_CTRL5, 0x09D5),
MAKE_REG(VLAN_EGRESS_TRANS_CTRL6, 0x09D6),
MAKE_REG(VLAN_EGRESS_TRANS_CTRL7, 0x09D7),
MAKE_REG(VLAN_EGRESS_TRANS_CTRL8, 0x09D8),
MAKE_REG(VLAN_EGRESS_TRANS_CTRL9, 0x09D9),
MAKE_REG(MIRROR_CTRL2, 0x09DA),
MAKE_REG(OUTPUT_DROP_CFG, 0x09DB),
MAKE_REG(UNKNOWN_UNICAST_DA_PORT_BEHAVE_EXT, 0x09DC),
MAKE_REG(RMK_CFG_SEL_CTRL, 0x09DF),
MAKE_REG(QOS_DSCP_REMARK_DSCP_CTRL0, 0x09E0),
MAKE_REG(QOS_DSCP_REMARK_DSCP_CTRL1, 0x09E1),
MAKE_REG(QOS_DSCP_REMARK_DSCP_CTRL2, 0x09E2),
MAKE_REG(QOS_DSCP_REMARK_DSCP_CTRL3, 0x09E3),
MAKE_REG(QOS_DSCP_REMARK_DSCP_CTRL4, 0x09E4),
MAKE_REG(QOS_DSCP_REMARK_DSCP_CTRL5, 0x09E5),
MAKE_REG(QOS_DSCP_REMARK_DSCP_CTRL6, 0x09E6),
MAKE_REG(QOS_DSCP_REMARK_DSCP_CTRL7, 0x09E7),
MAKE_REG(QOS_DSCP_REMARK_DSCP_CTRL8, 0x09E8),
MAKE_REG(QOS_DSCP_REMARK_DSCP_CTRL9, 0x09E9),
MAKE_REG(QOS_DSCP_REMARK_DSCP_CTRL10, 0x09EA),
MAKE_REG(QOS_DSCP_REMARK_DSCP_CTRL11, 0x09EB),
MAKE_REG(QOS_DSCP_REMARK_DSCP_CTRL12, 0x09EC),
MAKE_REG(QOS_DSCP_REMARK_DSCP_CTRL13, 0x09ED),
MAKE_REG(QOS_DSCP_REMARK_DSCP_CTRL14, 0x09EE),
MAKE_REG(QOS_DSCP_REMARK_DSCP_CTRL15, 0x09EF),
MAKE_REG(QOS_DSCP_REMARK_DSCP_CTRL16, 0x09F0),
MAKE_REG(QOS_DSCP_REMARK_DSCP_CTRL17, 0x09F1),
MAKE_REG(QOS_DSCP_REMARK_DSCP_CTRL18, 0x09F2),
MAKE_REG(QOS_DSCP_REMARK_DSCP_CTRL19, 0x09F3),
MAKE_REG(QOS_DSCP_REMARK_DSCP_CTRL20, 0x09F4),
MAKE_REG(QOS_DSCP_REMARK_DSCP_CTRL21, 0x09F5),
MAKE_REG(QOS_DSCP_REMARK_DSCP_CTRL22, 0x09F6),
MAKE_REG(QOS_DSCP_REMARK_DSCP_CTRL23, 0x09F7),
MAKE_REG(QOS_DSCP_REMARK_DSCP_CTRL24, 0x09F8),
MAKE_REG(QOS_DSCP_REMARK_DSCP_CTRL25, 0x09F9),
MAKE_REG(QOS_DSCP_REMARK_DSCP_CTRL26, 0x09FA),
MAKE_REG(QOS_DSCP_REMARK_DSCP_CTRL27, 0x09FB),
MAKE_REG(QOS_DSCP_REMARK_DSCP_CTRL28, 0x09FC),
MAKE_REG(QOS_DSCP_REMARK_DSCP_CTRL29, 0x09FD),
MAKE_REG(QOS_DSCP_REMARK_DSCP_CTRL30, 0x09FE),
MAKE_REG(QOS_DSCP_REMARK_DSCP_CTRL31, 0x09FF),
MAKE_REG(VLAN_MSTI0_CTRL0, 0x0a00),
MAKE_REG(VLAN_MSTI0_CTRL1, 0x0a01),
MAKE_REG(VLAN_MSTI1_CTRL0, 0x0a02),
MAKE_REG(VLAN_MSTI1_CTRL1, 0x0a03),
MAKE_REG(VLAN_MSTI2_CTRL0, 0x0a04),
MAKE_REG(VLAN_MSTI2_CTRL1, 0x0a05),
MAKE_REG(VLAN_MSTI3_CTRL0, 0x0a06),
MAKE_REG(VLAN_MSTI3_CTRL1, 0x0a07),
MAKE_REG(VLAN_MSTI4_CTRL0, 0x0a08),
MAKE_REG(VLAN_MSTI4_CTRL1, 0x0a09),
MAKE_REG(VLAN_MSTI5_CTRL0, 0x0a0a),
MAKE_REG(VLAN_MSTI5_CTRL1, 0x0a0b),
MAKE_REG(VLAN_MSTI6_CTRL0, 0x0a0c),
MAKE_REG(VLAN_MSTI6_CTRL1, 0x0a0d),
MAKE_REG(VLAN_MSTI7_CTRL0, 0x0a0e),
MAKE_REG(VLAN_MSTI7_CTRL1, 0x0a0f),
MAKE_REG(VLAN_MSTI8_CTRL0, 0x0a10),
MAKE_REG(VLAN_MSTI8_CTRL1, 0x0a11),
MAKE_REG(VLAN_MSTI9_CTRL0, 0x0a12),
MAKE_REG(VLAN_MSTI9_CTRL1, 0x0a13),
MAKE_REG(VLAN_MSTI10_CTRL0, 0x0a14),
MAKE_REG(VLAN_MSTI10_CTRL1, 0x0a15),
MAKE_REG(VLAN_MSTI11_CTRL0, 0x0a16),
MAKE_REG(VLAN_MSTI11_CTRL1, 0x0a17),
MAKE_REG(VLAN_MSTI12_CTRL0, 0x0a18),
MAKE_REG(VLAN_MSTI12_CTRL1, 0x0a19),
MAKE_REG(VLAN_MSTI13_CTRL0, 0x0a1a),
MAKE_REG(VLAN_MSTI13_CTRL1, 0x0a1b),
MAKE_REG(VLAN_MSTI14_CTRL0, 0x0a1c),
MAKE_REG(VLAN_MSTI14_CTRL1, 0x0a1d),
MAKE_REG(VLAN_MSTI15_CTRL0, 0x0a1e),
MAKE_REG(VLAN_MSTI15_CTRL1, 0x0a1f),
MAKE_REG(LUT_PORT0_LEARN_LIMITNO, 0x0a20),
MAKE_REG(LUT_PORT1_LEARN_LIMITNO, 0x0a21),
MAKE_REG(LUT_PORT2_LEARN_LIMITNO, 0x0a22),
MAKE_REG(LUT_PORT3_LEARN_LIMITNO, 0x0a23),
MAKE_REG(LUT_PORT4_LEARN_LIMITNO, 0x0a24),
MAKE_REG(LUT_PORT5_LEARN_LIMITNO, 0x0a25),
MAKE_REG(LUT_PORT6_LEARN_LIMITNO, 0x0a26),
MAKE_REG(LUT_PORT7_LEARN_LIMITNO, 0x0a27),
MAKE_REG(LUT_SYS_LEARN_LIMITNO, 0x0a28),
MAKE_REG(LUT_LRN_SYS_LMT_CTRL, 0x0a29),
MAKE_REG(LUT_PORT8_LEARN_LIMITNO, 0x0a2a),
MAKE_REG(LUT_PORT9_LEARN_LIMITNO, 0x0a2b),
MAKE_REG(LUT_PORT10_LEARN_LIMITNO, 0x0a2c),
MAKE_REG(LUT_CFG, 0x0a30),
MAKE_REG(LUT_AGEOUT_CTRL, 0x0a31),
MAKE_REG(PORT_EFID_CTRL0, 0x0a32),
MAKE_REG(PORT_EFID_CTRL1, 0x0a33),
MAKE_REG(PORT_EFID_CTRL2, 0x0a34),
MAKE_REG(FORCE_FLUSH1, 0x0a35),
MAKE_REG(FORCE_FLUSH, 0x0a36),
MAKE_REG(L2_FLUSH_CTRL1, 0x0a37),
MAKE_REG(L2_FLUSH_CTRL2, 0x0a38),
MAKE_REG(L2_FLUSH_CTRL3, 0x0a39),
MAKE_REG(LUT_CFG2, 0x0a3a),
MAKE_REG(FLUSH_STATUS, 0x0a3f),
MAKE_REG(STORM_BCAST, 0x0a40),
MAKE_REG(STORM_MCAST, 0x0a41),
MAKE_REG(STORM_UNKOWN_UCAST, 0x0a42),
MAKE_REG(STORM_UNKOWN_MCAST, 0x0a43),
MAKE_REG(STORM_BCAST_METER_CTRL0, 0x0a44),
MAKE_REG(STORM_BCAST_METER_CTRL1, 0x0a45),
MAKE_REG(STORM_BCAST_METER_CTRL2, 0x0a46),
MAKE_REG(STORM_BCAST_METER_CTRL3, 0x0a47),
MAKE_REG(STORM_BCAST_METER_CTRL4, 0x0a48),
MAKE_REG(STORM_BCAST_METER_CTRL5, 0x0a49),
MAKE_REG(STORM_MCAST_METER_CTRL0, 0x0a4c),
MAKE_REG(STORM_MCAST_METER_CTRL1, 0x0a4d),
MAKE_REG(STORM_MCAST_METER_CTRL2, 0x0a4e),
MAKE_REG(STORM_MCAST_METER_CTRL3, 0x0a4f),
MAKE_REG(STORM_MCAST_METER_CTRL4, 0x0a50),
MAKE_REG(STORM_MCAST_METER_CTRL5, 0x0a51),
MAKE_REG(STORM_UNDA_METER_CTRL0, 0x0a54),
MAKE_REG(STORM_UNDA_METER_CTRL1, 0x0a55),
MAKE_REG(STORM_UNDA_METER_CTRL2, 0x0a56),
MAKE_REG(STORM_UNDA_METER_CTRL3, 0x0a57),
MAKE_REG(STORM_UNDA_METER_CTRL4, 0x0a58),
MAKE_REG(STORM_UNDA_METER_CTRL5, 0x0a59),
MAKE_REG(STORM_UNMC_METER_CTRL0, 0x0a5c),
MAKE_REG(STORM_UNMC_METER_CTRL1, 0x0a5d),
MAKE_REG(STORM_UNMC_METER_CTRL2, 0x0a5e),
MAKE_REG(STORM_UNMC_METER_CTRL3, 0x0a5f),
MAKE_REG(STORM_EXT_CFG, 0x0a60),
MAKE_REG(STORM_EXT_MTRIDX_CFG0, 0x0a61),
MAKE_REG(STORM_EXT_MTRIDX_CFG1, 0x0a62),
MAKE_REG(STORM_UNMC_METER_CTRL4, 0x0a63),
MAKE_REG(STORM_UNMC_METER_CTRL5, 0x0a64),
MAKE_REG(OAM_PARSER_CTRL0, 0x0a70),
MAKE_REG(OAM_PARSER_CTRL1, 0x0a71),
MAKE_REG(OAM_MULTIPLEXER_CTRL0, 0x0a72),
MAKE_REG(OAM_MULTIPLEXER_CTRL1, 0x0a73),
MAKE_REG(OAM_CTRL, 0x0a74),
MAKE_REG(DOT1X_PORT_ENABLE, 0x0a80),
MAKE_REG(DOT1X_MAC_ENABLE, 0x0a81),
MAKE_REG(DOT1X_PORT_AUTH, 0x0a82),
MAKE_REG(DOT1X_PORT_OPDIR, 0x0a83),
MAKE_REG(DOT1X_UNAUTH_ACT_W0, 0x0a84),
MAKE_REG(DOT1X_UNAUTH_ACT_W1, 0x0a85),
MAKE_REG(DOT1X_CFG, 0x0a86),
MAKE_REG(L2_LRN_CNT_CTRL0, 0x0a87),
MAKE_REG(L2_LRN_CNT_CTRL1, 0x0a88),
MAKE_REG(L2_LRN_CNT_CTRL2, 0x0a89),
MAKE_REG(L2_LRN_CNT_CTRL3, 0x0a8a),
MAKE_REG(L2_LRN_CNT_CTRL4, 0x0a8b),
MAKE_REG(L2_LRN_CNT_CTRL5, 0x0a8c),
MAKE_REG(L2_LRN_CNT_CTRL6, 0x0a8d),
MAKE_REG(L2_LRN_CNT_CTRL7, 0x0a8e),
MAKE_REG(L2_LRN_CNT_CTRL8, 0x0a8f),
MAKE_REG(L2_LRN_CNT_CTRL9, 0x0a90),
MAKE_REG(L2_LRN_CNT_CTRL10, 0x0a92),
MAKE_REG(LUT_LRN_UNDER_STATUS, 0x0a91),
MAKE_REG(L2_SA_MOVING_FORBID, 0x0aa0),
MAKE_REG(DRPORT_LEARN_CTRL, 0x0aa1),
MAKE_REG(L2_DUMMY02, 0x0aa2),
MAKE_REG(L2_DUMMY03, 0x0aa3),
MAKE_REG(L2_DUMMY04, 0x0aa4),
MAKE_REG(L2_DUMMY05, 0x0aa5),
MAKE_REG(L2_DUMMY06, 0x0aa6),
MAKE_REG(L2_DUMMY07, 0x0aa7),
MAKE_REG(IPMC_GROUP_PMSK_00, 0x0AC0),
MAKE_REG(IPMC_GROUP_PMSK_01, 0x0AC1),
MAKE_REG(IPMC_GROUP_PMSK_02, 0x0AC2),
MAKE_REG(IPMC_GROUP_PMSK_03, 0x0AC3),
MAKE_REG(IPMC_GROUP_PMSK_04, 0x0AC4),
MAKE_REG(IPMC_GROUP_PMSK_05, 0x0AC5),
MAKE_REG(IPMC_GROUP_PMSK_06, 0x0AC6),
MAKE_REG(IPMC_GROUP_PMSK_07, 0x0AC7),
MAKE_REG(IPMC_GROUP_PMSK_08, 0x0AC8),
MAKE_REG(IPMC_GROUP_PMSK_09, 0x0AC9),
MAKE_REG(IPMC_GROUP_PMSK_10, 0x0ACA),
MAKE_REG(IPMC_GROUP_PMSK_11, 0x0ACB),
MAKE_REG(IPMC_GROUP_PMSK_12, 0x0ACC),
MAKE_REG(IPMC_GROUP_PMSK_13, 0x0ACD),
MAKE_REG(IPMC_GROUP_PMSK_14, 0x0ACE),
MAKE_REG(IPMC_GROUP_PMSK_15, 0x0ACF),
MAKE_REG(IPMC_GROUP_PMSK_16, 0x0AD0),
MAKE_REG(IPMC_GROUP_PMSK_17, 0x0AD1),
MAKE_REG(IPMC_GROUP_PMSK_18, 0x0AD2),
MAKE_REG(IPMC_GROUP_PMSK_19, 0x0AD3),
MAKE_REG(IPMC_GROUP_PMSK_20, 0x0AD4),
MAKE_REG(IPMC_GROUP_PMSK_21, 0x0AD5),
MAKE_REG(IPMC_GROUP_PMSK_22, 0x0AD6),
MAKE_REG(IPMC_GROUP_PMSK_23, 0x0AD7),
MAKE_REG(IPMC_GROUP_PMSK_24, 0x0AD8),
MAKE_REG(IPMC_GROUP_PMSK_25, 0x0AD9),
MAKE_REG(IPMC_GROUP_PMSK_26, 0x0ADA),
MAKE_REG(IPMC_GROUP_PMSK_27, 0x0ADB),
MAKE_REG(IPMC_GROUP_PMSK_28, 0x0ADC),
MAKE_REG(IPMC_GROUP_PMSK_29, 0x0ADD),
MAKE_REG(IPMC_GROUP_PMSK_30, 0x0ADE),
MAKE_REG(IPMC_GROUP_PMSK_31, 0x0ADF),
MAKE_REG(IPMC_GROUP_PMSK_32, 0x0AE0),
MAKE_REG(IPMC_GROUP_PMSK_33, 0x0AE1),
MAKE_REG(IPMC_GROUP_PMSK_34, 0x0AE2),
MAKE_REG(IPMC_GROUP_PMSK_35, 0x0AE3),
MAKE_REG(IPMC_GROUP_PMSK_36, 0x0AE4),
MAKE_REG(IPMC_GROUP_PMSK_37, 0x0AE5),
MAKE_REG(IPMC_GROUP_PMSK_38, 0x0AE6),
MAKE_REG(IPMC_GROUP_PMSK_39, 0x0AE7),
MAKE_REG(IPMC_GROUP_PMSK_40, 0x0AE8),
MAKE_REG(IPMC_GROUP_PMSK_41, 0x0AE9),
MAKE_REG(IPMC_GROUP_PMSK_42, 0x0AEA),
MAKE_REG(IPMC_GROUP_PMSK_43, 0x0AEB),
MAKE_REG(IPMC_GROUP_PMSK_44, 0x0AEC),
MAKE_REG(IPMC_GROUP_PMSK_45, 0x0AED),
MAKE_REG(IPMC_GROUP_PMSK_46, 0x0AEE),
MAKE_REG(IPMC_GROUP_PMSK_47, 0x0AEF),
MAKE_REG(IPMC_GROUP_PMSK_48, 0x0AF0),
MAKE_REG(IPMC_GROUP_PMSK_49, 0x0AF1),
MAKE_REG(IPMC_GROUP_PMSK_50, 0x0AF2),
MAKE_REG(IPMC_GROUP_PMSK_51, 0x0AF3),
MAKE_REG(IPMC_GROUP_PMSK_52, 0x0AF4),
MAKE_REG(IPMC_GROUP_PMSK_53, 0x0AF5),
MAKE_REG(IPMC_GROUP_PMSK_54, 0x0AF6),
MAKE_REG(IPMC_GROUP_PMSK_55, 0x0AF7),
MAKE_REG(IPMC_GROUP_PMSK_56, 0x0AF8),
MAKE_REG(IPMC_GROUP_PMSK_57, 0x0AF9),
MAKE_REG(IPMC_GROUP_PMSK_58, 0x0AFA),
MAKE_REG(IPMC_GROUP_PMSK_59, 0x0AFB),
MAKE_REG(IPMC_GROUP_PMSK_60, 0x0AFC),
MAKE_REG(IPMC_GROUP_PMSK_61, 0x0AFD),
MAKE_REG(IPMC_GROUP_PMSK_62, 0x0AFE),
MAKE_REG(IPMC_GROUP_PMSK_63, 0x0AFF),
MAKE_REG(SVLAN_MCAST2S_ENTRY0_CTRL0, 0x0b00),
MAKE_REG(SVLAN_MCAST2S_ENTRY0_CTRL1, 0x0b01),
MAKE_REG(SVLAN_MCAST2S_ENTRY0_CTRL2, 0x0b02),
MAKE_REG(SVLAN_MCAST2S_ENTRY0_CTRL3, 0x0b03),
MAKE_REG(SVLAN_MCAST2S_ENTRY0_CTRL4, 0x0b04),
MAKE_REG(SVLAN_MCAST2S_ENTRY1_CTRL0, 0x0b05),
MAKE_REG(SVLAN_MCAST2S_ENTRY1_CTRL1, 0x0b06),
MAKE_REG(SVLAN_MCAST2S_ENTRY1_CTRL2, 0x0b07),
MAKE_REG(SVLAN_MCAST2S_ENTRY1_CTRL3, 0x0b08),
MAKE_REG(SVLAN_MCAST2S_ENTRY1_CTRL4, 0x0b09),
MAKE_REG(SVLAN_MCAST2S_ENTRY2_CTRL0, 0x0b0a),
MAKE_REG(SVLAN_MCAST2S_ENTRY2_CTRL1, 0x0b0b),
MAKE_REG(SVLAN_MCAST2S_ENTRY2_CTRL2, 0x0b0c),
MAKE_REG(SVLAN_MCAST2S_ENTRY2_CTRL3, 0x0b0d),
MAKE_REG(SVLAN_MCAST2S_ENTRY2_CTRL4, 0x0b0e),
MAKE_REG(SVLAN_MCAST2S_ENTRY3_CTRL0, 0x0b0f),
MAKE_REG(SVLAN_MCAST2S_ENTRY3_CTRL1, 0x0b10),
MAKE_REG(SVLAN_MCAST2S_ENTRY3_CTRL2, 0x0b11),
MAKE_REG(SVLAN_MCAST2S_ENTRY3_CTRL3, 0x0b12),
MAKE_REG(SVLAN_MCAST2S_ENTRY3_CTRL4, 0x0b13),
MAKE_REG(SVLAN_MCAST2S_ENTRY4_CTRL0, 0x0b14),
MAKE_REG(SVLAN_MCAST2S_ENTRY4_CTRL1, 0x0b15),
MAKE_REG(SVLAN_MCAST2S_ENTRY4_CTRL2, 0x0b16),
MAKE_REG(SVLAN_MCAST2S_ENTRY4_CTRL3, 0x0b17),
MAKE_REG(SVLAN_MCAST2S_ENTRY4_CTRL4, 0x0b18),
MAKE_REG(SVLAN_MCAST2S_ENTRY5_CTRL0, 0x0b19),
MAKE_REG(SVLAN_MCAST2S_ENTRY5_CTRL1, 0x0b1a),
MAKE_REG(SVLAN_MCAST2S_ENTRY5_CTRL2, 0x0b1b),
MAKE_REG(SVLAN_MCAST2S_ENTRY5_CTRL3, 0x0b1c),
MAKE_REG(SVLAN_MCAST2S_ENTRY5_CTRL4, 0x0b1d),
MAKE_REG(SVLAN_MCAST2S_ENTRY6_CTRL0, 0x0b1e),
MAKE_REG(SVLAN_MCAST2S_ENTRY6_CTRL1, 0x0b1f),
MAKE_REG(SVLAN_MCAST2S_ENTRY6_CTRL2, 0x0b20),
MAKE_REG(SVLAN_MCAST2S_ENTRY6_CTRL3, 0x0b21),
MAKE_REG(SVLAN_MCAST2S_ENTRY6_CTRL4, 0x0b22),
MAKE_REG(SVLAN_MCAST2S_ENTRY7_CTRL0, 0x0b23),
MAKE_REG(SVLAN_MCAST2S_ENTRY7_CTRL1, 0x0b24),
MAKE_REG(SVLAN_MCAST2S_ENTRY7_CTRL2, 0x0b25),
MAKE_REG(SVLAN_MCAST2S_ENTRY7_CTRL3, 0x0b26),
MAKE_REG(SVLAN_MCAST2S_ENTRY7_CTRL4, 0x0b27),
MAKE_REG(SVLAN_MCAST2S_ENTRY8_CTRL0, 0x0b28),
MAKE_REG(SVLAN_MCAST2S_ENTRY8_CTRL1, 0x0b29),
MAKE_REG(SVLAN_MCAST2S_ENTRY8_CTRL2, 0x0b2a),
MAKE_REG(SVLAN_MCAST2S_ENTRY8_CTRL3, 0x0b2b),
MAKE_REG(SVLAN_MCAST2S_ENTRY8_CTRL4, 0x0b2c),
MAKE_REG(SVLAN_MCAST2S_ENTRY9_CTRL0, 0x0b2d),
MAKE_REG(SVLAN_MCAST2S_ENTRY9_CTRL1, 0x0b2e),
MAKE_REG(SVLAN_MCAST2S_ENTRY9_CTRL2, 0x0b2f),
MAKE_REG(SVLAN_MCAST2S_ENTRY9_CTRL3, 0x0b30),
MAKE_REG(SVLAN_MCAST2S_ENTRY9_CTRL4, 0x0b31),
MAKE_REG(SVLAN_MCAST2S_ENTRY10_CTRL0, 0x0b32),
MAKE_REG(SVLAN_MCAST2S_ENTRY10_CTRL1, 0x0b33),
MAKE_REG(SVLAN_MCAST2S_ENTRY10_CTRL2, 0x0b34),
MAKE_REG(SVLAN_MCAST2S_ENTRY10_CTRL3, 0x0b35),
MAKE_REG(SVLAN_MCAST2S_ENTRY10_CTRL4, 0x0b36),
MAKE_REG(SVLAN_MCAST2S_ENTRY11_CTRL0, 0x0b37),
MAKE_REG(SVLAN_MCAST2S_ENTRY11_CTRL1, 0x0b38),
MAKE_REG(SVLAN_MCAST2S_ENTRY11_CTRL2, 0x0b39),
MAKE_REG(SVLAN_MCAST2S_ENTRY11_CTRL3, 0x0b3a),
MAKE_REG(SVLAN_MCAST2S_ENTRY11_CTRL4, 0x0b3b),
MAKE_REG(SVLAN_MCAST2S_ENTRY12_CTRL0, 0x0b3c),
MAKE_REG(SVLAN_MCAST2S_ENTRY12_CTRL1, 0x0b3d),
MAKE_REG(SVLAN_MCAST2S_ENTRY12_CTRL2, 0x0b3e),
MAKE_REG(SVLAN_MCAST2S_ENTRY12_CTRL3, 0x0b3f),
MAKE_REG(SVLAN_MCAST2S_ENTRY12_CTRL4, 0x0b40),
MAKE_REG(SVLAN_MCAST2S_ENTRY13_CTRL0, 0x0b41),
MAKE_REG(SVLAN_MCAST2S_ENTRY13_CTRL1, 0x0b42),
MAKE_REG(SVLAN_MCAST2S_ENTRY13_CTRL2, 0x0b43),
MAKE_REG(SVLAN_MCAST2S_ENTRY13_CTRL3, 0x0b44),
MAKE_REG(SVLAN_MCAST2S_ENTRY13_CTRL4, 0x0b45),
MAKE_REG(SVLAN_MCAST2S_ENTRY14_CTRL0, 0x0b46),
MAKE_REG(SVLAN_MCAST2S_ENTRY14_CTRL1, 0x0b47),
MAKE_REG(SVLAN_MCAST2S_ENTRY14_CTRL2, 0x0b48),
MAKE_REG(SVLAN_MCAST2S_ENTRY14_CTRL3, 0x0b49),
MAKE_REG(SVLAN_MCAST2S_ENTRY14_CTRL4, 0x0b4a),
MAKE_REG(SVLAN_MCAST2S_ENTRY15_CTRL0, 0x0b4b),
MAKE_REG(SVLAN_MCAST2S_ENTRY15_CTRL1, 0x0b4c),
MAKE_REG(SVLAN_MCAST2S_ENTRY15_CTRL2, 0x0b4d),
MAKE_REG(SVLAN_MCAST2S_ENTRY15_CTRL3, 0x0b4e),
MAKE_REG(SVLAN_MCAST2S_ENTRY15_CTRL4, 0x0b4f),
MAKE_REG(SVLAN_MCAST2S_ENTRY16_CTRL0, 0x0b50),
MAKE_REG(SVLAN_MCAST2S_ENTRY16_CTRL1, 0x0b51),
MAKE_REG(SVLAN_MCAST2S_ENTRY16_CTRL2, 0x0b52),
MAKE_REG(SVLAN_MCAST2S_ENTRY16_CTRL3, 0x0b53),
MAKE_REG(SVLAN_MCAST2S_ENTRY16_CTRL4, 0x0b54),
MAKE_REG(SVLAN_MCAST2S_ENTRY17_CTRL0, 0x0b55),
MAKE_REG(SVLAN_MCAST2S_ENTRY17_CTRL1, 0x0b56),
MAKE_REG(SVLAN_MCAST2S_ENTRY17_CTRL2, 0x0b57),
MAKE_REG(SVLAN_MCAST2S_ENTRY17_CTRL3, 0x0b58),
MAKE_REG(SVLAN_MCAST2S_ENTRY17_CTRL4, 0x0b59),
MAKE_REG(SVLAN_MCAST2S_ENTRY18_CTRL0, 0x0b5a),
MAKE_REG(SVLAN_MCAST2S_ENTRY18_CTRL1, 0x0b5b),
MAKE_REG(SVLAN_MCAST2S_ENTRY18_CTRL2, 0x0b5c),
MAKE_REG(SVLAN_MCAST2S_ENTRY18_CTRL3, 0x0b5d),
MAKE_REG(SVLAN_MCAST2S_ENTRY18_CTRL4, 0x0b5e),
MAKE_REG(SVLAN_MCAST2S_ENTRY19_CTRL0, 0x0b5f),
MAKE_REG(SVLAN_MCAST2S_ENTRY19_CTRL1, 0x0b60),
MAKE_REG(SVLAN_MCAST2S_ENTRY19_CTRL2, 0x0b61),
MAKE_REG(SVLAN_MCAST2S_ENTRY19_CTRL3, 0x0b62),
MAKE_REG(SVLAN_MCAST2S_ENTRY19_CTRL4, 0x0b63),
MAKE_REG(SVLAN_MCAST2S_ENTRY20_CTRL0, 0x0b64),
MAKE_REG(SVLAN_MCAST2S_ENTRY20_CTRL1, 0x0b65),
MAKE_REG(SVLAN_MCAST2S_ENTRY20_CTRL2, 0x0b66),
MAKE_REG(SVLAN_MCAST2S_ENTRY20_CTRL3, 0x0b67),
MAKE_REG(SVLAN_MCAST2S_ENTRY20_CTRL4, 0x0b68),
MAKE_REG(SVLAN_MCAST2S_ENTRY21_CTRL0, 0x0b69),
MAKE_REG(SVLAN_MCAST2S_ENTRY21_CTRL1, 0x0b6a),
MAKE_REG(SVLAN_MCAST2S_ENTRY21_CTRL2, 0x0b6b),
MAKE_REG(SVLAN_MCAST2S_ENTRY21_CTRL3, 0x0b6c),
MAKE_REG(SVLAN_MCAST2S_ENTRY21_CTRL4, 0x0b6d),
MAKE_REG(SVLAN_MCAST2S_ENTRY22_CTRL0, 0x0b6e),
MAKE_REG(SVLAN_MCAST2S_ENTRY22_CTRL1, 0x0b6f),
MAKE_REG(SVLAN_MCAST2S_ENTRY22_CTRL2, 0x0b70),
MAKE_REG(SVLAN_MCAST2S_ENTRY22_CTRL3, 0x0b71),
MAKE_REG(SVLAN_MCAST2S_ENTRY22_CTRL4, 0x0b72),
MAKE_REG(SVLAN_MCAST2S_ENTRY23_CTRL0, 0x0b73),
MAKE_REG(SVLAN_MCAST2S_ENTRY23_CTRL1, 0x0b74),
MAKE_REG(SVLAN_MCAST2S_ENTRY23_CTRL2, 0x0b75),
MAKE_REG(SVLAN_MCAST2S_ENTRY23_CTRL3, 0x0b76),
MAKE_REG(SVLAN_MCAST2S_ENTRY23_CTRL4, 0x0b77),
MAKE_REG(SVLAN_MCAST2S_ENTRY24_CTRL0, 0x0b78),
MAKE_REG(SVLAN_MCAST2S_ENTRY24_CTRL1, 0x0b79),
MAKE_REG(SVLAN_MCAST2S_ENTRY24_CTRL2, 0x0b7a),
MAKE_REG(SVLAN_MCAST2S_ENTRY24_CTRL3, 0x0b7b),
MAKE_REG(SVLAN_MCAST2S_ENTRY24_CTRL4, 0x0b7c),
MAKE_REG(SVLAN_MCAST2S_ENTRY25_CTRL0, 0x0b7d),
MAKE_REG(SVLAN_MCAST2S_ENTRY25_CTRL1, 0x0b7e),
MAKE_REG(SVLAN_MCAST2S_ENTRY25_CTRL2, 0x0b7f),
MAKE_REG(SVLAN_MCAST2S_ENTRY25_CTRL3, 0x0b80),
MAKE_REG(SVLAN_MCAST2S_ENTRY25_CTRL4, 0x0b81),
MAKE_REG(SVLAN_MCAST2S_ENTRY26_CTRL0, 0x0b82),
MAKE_REG(SVLAN_MCAST2S_ENTRY26_CTRL1, 0x0b83),
MAKE_REG(SVLAN_MCAST2S_ENTRY26_CTRL2, 0x0b84),
MAKE_REG(SVLAN_MCAST2S_ENTRY26_CTRL3, 0x0b85),
MAKE_REG(SVLAN_MCAST2S_ENTRY26_CTRL4, 0x0b86),
MAKE_REG(SVLAN_MCAST2S_ENTRY27_CTRL0, 0x0b87),
MAKE_REG(SVLAN_MCAST2S_ENTRY27_CTRL1, 0x0b88),
MAKE_REG(SVLAN_MCAST2S_ENTRY27_CTRL2, 0x0b89),
MAKE_REG(SVLAN_MCAST2S_ENTRY27_CTRL3, 0x0b8a),
MAKE_REG(SVLAN_MCAST2S_ENTRY27_CTRL4, 0x0b8b),
MAKE_REG(SVLAN_MCAST2S_ENTRY28_CTRL0, 0x0b8c),
MAKE_REG(SVLAN_MCAST2S_ENTRY28_CTRL1, 0x0b8d),
MAKE_REG(SVLAN_MCAST2S_ENTRY28_CTRL2, 0x0b8e),
MAKE_REG(SVLAN_MCAST2S_ENTRY28_CTRL3, 0x0b8f),
MAKE_REG(SVLAN_MCAST2S_ENTRY28_CTRL4, 0x0b90),
MAKE_REG(SVLAN_MCAST2S_ENTRY29_CTRL0, 0x0b91),
MAKE_REG(SVLAN_MCAST2S_ENTRY29_CTRL1, 0x0b92),
MAKE_REG(SVLAN_MCAST2S_ENTRY29_CTRL2, 0x0b93),
MAKE_REG(SVLAN_MCAST2S_ENTRY29_CTRL3, 0x0b94),
MAKE_REG(SVLAN_MCAST2S_ENTRY29_CTRL4, 0x0b95),
MAKE_REG(SVLAN_MCAST2S_ENTRY30_CTRL0, 0x0b96),
MAKE_REG(SVLAN_MCAST2S_ENTRY30_CTRL1, 0x0b97),
MAKE_REG(SVLAN_MCAST2S_ENTRY30_CTRL2, 0x0b98),
MAKE_REG(SVLAN_MCAST2S_ENTRY30_CTRL3, 0x0b99),
MAKE_REG(SVLAN_MCAST2S_ENTRY30_CTRL4, 0x0b9a),
MAKE_REG(SVLAN_MCAST2S_ENTRY31_CTRL0, 0x0b9b),
MAKE_REG(SVLAN_MCAST2S_ENTRY31_CTRL1, 0x0b9c),
MAKE_REG(SVLAN_MCAST2S_ENTRY31_CTRL2, 0x0b9d),
MAKE_REG(SVLAN_MCAST2S_ENTRY31_CTRL3, 0x0b9e),
MAKE_REG(SVLAN_MCAST2S_ENTRY31_CTRL4, 0x0b9f),
MAKE_REG(MLTVLAN_DUMMY_0, 0x0ba0),
MAKE_REG(MLTVLAN_DUMMY_1, 0x0ba1),
MAKE_REG(MLTVLAN_DUMMY_2, 0x0ba2),
MAKE_REG(MLTVLAN_DUMMY_3, 0x0ba3),
MAKE_REG(MLTVLAN_DUMMY_4, 0x0ba4),
MAKE_REG(MLTVLAN_DUMMY_5, 0x0ba5),
MAKE_REG(MLTVLAN_DUMMY_6, 0x0ba6),
MAKE_REG(MLTVLAN_DUMMY_7, 0x0ba7),
MAKE_REG(SVLAN_MEMBERCFG0_CTRL1, 0x0c01),
MAKE_REG(SVLAN_MEMBERCFG0_CTRL2, 0x0c02),
MAKE_REG(SVLAN_MEMBERCFG0_CTRL3, 0x0c03),
MAKE_REG(SVLAN_MEMBERCFG1_CTRL1, 0x0c04),
MAKE_REG(SVLAN_MEMBERCFG1_CTRL2, 0x0c05),
MAKE_REG(SVLAN_MEMBERCFG1_CTRL3, 0x0c06),
MAKE_REG(SVLAN_MEMBERCFG2_CTRL1, 0x0c07),
MAKE_REG(SVLAN_MEMBERCFG2_CTRL2, 0x0c08),
MAKE_REG(SVLAN_MEMBERCFG2_CTRL3, 0x0c09),
MAKE_REG(SVLAN_MEMBERCFG3_CTRL1, 0x0c0a),
MAKE_REG(SVLAN_MEMBERCFG3_CTRL2, 0x0c0b),
MAKE_REG(SVLAN_MEMBERCFG3_CTRL3, 0x0c0c),
MAKE_REG(SVLAN_MEMBERCFG4_CTRL1, 0x0c0d),
MAKE_REG(SVLAN_MEMBERCFG4_CTRL2, 0x0c0e),
MAKE_REG(SVLAN_MEMBERCFG4_CTRL3, 0x0c0f),
MAKE_REG(SVLAN_MEMBERCFG5_CTRL1, 0x0c10),
MAKE_REG(SVLAN_MEMBERCFG5_CTRL2, 0x0c11),
MAKE_REG(SVLAN_MEMBERCFG5_CTRL3, 0x0c12),
MAKE_REG(SVLAN_MEMBERCFG6_CTRL1, 0x0c13),
MAKE_REG(SVLAN_MEMBERCFG6_CTRL2, 0x0c14),
MAKE_REG(SVLAN_MEMBERCFG6_CTRL3, 0x0c15),
MAKE_REG(SVLAN_MEMBERCFG7_CTRL1, 0x0c16),
MAKE_REG(SVLAN_MEMBERCFG7_CTRL2, 0x0c17),
MAKE_REG(SVLAN_MEMBERCFG7_CTRL3, 0x0c18),
MAKE_REG(SVLAN_MEMBERCFG8_CTRL1, 0x0c19),
MAKE_REG(SVLAN_MEMBERCFG8_CTRL2, 0x0c1a),
MAKE_REG(SVLAN_MEMBERCFG8_CTRL3, 0x0c1b),
MAKE_REG(SVLAN_MEMBERCFG9_CTRL1, 0x0c1c),
MAKE_REG(SVLAN_MEMBERCFG9_CTRL2, 0x0c1d),
MAKE_REG(SVLAN_MEMBERCFG9_CTRL3, 0x0c1e),
MAKE_REG(SVLAN_MEMBERCFG10_CTRL1, 0x0c1f),
MAKE_REG(SVLAN_MEMBERCFG10_CTRL2, 0x0c20),
MAKE_REG(SVLAN_MEMBERCFG10_CTRL3, 0x0c21),
MAKE_REG(SVLAN_MEMBERCFG11_CTRL1, 0x0c22),
MAKE_REG(SVLAN_MEMBERCFG11_CTRL2, 0x0c23),
MAKE_REG(SVLAN_MEMBERCFG11_CTRL3, 0x0c24),
MAKE_REG(SVLAN_MEMBERCFG12_CTRL1, 0x0c25),
MAKE_REG(SVLAN_MEMBERCFG12_CTRL2, 0x0c26),
MAKE_REG(SVLAN_MEMBERCFG12_CTRL3, 0x0c27),
MAKE_REG(SVLAN_MEMBERCFG13_CTRL1, 0x0c28),
MAKE_REG(SVLAN_MEMBERCFG13_CTRL2, 0x0c29),
MAKE_REG(SVLAN_MEMBERCFG13_CTRL3, 0x0c2a),
MAKE_REG(SVLAN_MEMBERCFG14_CTRL1, 0x0c2b),
MAKE_REG(SVLAN_MEMBERCFG14_CTRL2, 0x0c2c),
MAKE_REG(SVLAN_MEMBERCFG14_CTRL3, 0x0c2d),
MAKE_REG(SVLAN_MEMBERCFG15_CTRL1, 0x0c2e),
MAKE_REG(SVLAN_MEMBERCFG15_CTRL2, 0x0c2f),
MAKE_REG(SVLAN_MEMBERCFG15_CTRL3, 0x0c30),
MAKE_REG(SVLAN_MEMBERCFG16_CTRL1, 0x0c31),
MAKE_REG(SVLAN_MEMBERCFG16_CTRL2, 0x0c32),
MAKE_REG(SVLAN_MEMBERCFG16_CTRL3, 0x0c33),
MAKE_REG(SVLAN_MEMBERCFG17_CTRL1, 0x0c34),
MAKE_REG(SVLAN_MEMBERCFG17_CTRL2, 0x0c35),
MAKE_REG(SVLAN_MEMBERCFG17_CTRL3, 0x0c36),
MAKE_REG(SVLAN_MEMBERCFG18_CTRL1, 0x0c37),
MAKE_REG(SVLAN_MEMBERCFG18_CTRL2, 0x0c38),
MAKE_REG(SVLAN_MEMBERCFG18_CTRL3, 0x0c39),
MAKE_REG(SVLAN_MEMBERCFG19_CTRL1, 0x0c3a),
MAKE_REG(SVLAN_MEMBERCFG19_CTRL2, 0x0c3b),
MAKE_REG(SVLAN_MEMBERCFG19_CTRL3, 0x0c3c),
MAKE_REG(SVLAN_MEMBERCFG20_CTRL1, 0x0c3d),
MAKE_REG(SVLAN_MEMBERCFG20_CTRL2, 0x0c3e),
MAKE_REG(SVLAN_MEMBERCFG20_CTRL3, 0x0c3f),
MAKE_REG(SVLAN_MEMBERCFG21_CTRL1, 0x0c40),
MAKE_REG(SVLAN_MEMBERCFG21_CTRL2, 0x0c41),
MAKE_REG(SVLAN_MEMBERCFG21_CTRL3, 0x0c42),
MAKE_REG(SVLAN_MEMBERCFG22_CTRL1, 0x0c43),
MAKE_REG(SVLAN_MEMBERCFG22_CTRL2, 0x0c44),
MAKE_REG(SVLAN_MEMBERCFG22_CTRL3, 0x0c45),
MAKE_REG(SVLAN_MEMBERCFG23_CTRL1, 0x0c46),
MAKE_REG(SVLAN_MEMBERCFG23_CTRL2, 0x0c47),
MAKE_REG(SVLAN_MEMBERCFG23_CTRL3, 0x0c48),
MAKE_REG(SVLAN_MEMBERCFG24_CTRL1, 0x0c49),
MAKE_REG(SVLAN_MEMBERCFG24_CTRL2, 0x0c4a),
MAKE_REG(SVLAN_MEMBERCFG24_CTRL3, 0x0c4b),
MAKE_REG(SVLAN_MEMBERCFG25_CTRL1, 0x0c4c),
MAKE_REG(SVLAN_MEMBERCFG25_CTRL2, 0x0c4d),
MAKE_REG(SVLAN_MEMBERCFG25_CTRL3, 0x0c4e),
MAKE_REG(SVLAN_MEMBERCFG26_CTRL1, 0x0c4f),
MAKE_REG(SVLAN_MEMBERCFG26_CTRL2, 0x0c50),
MAKE_REG(SVLAN_MEMBERCFG26_CTRL3, 0x0c51),
MAKE_REG(SVLAN_MEMBERCFG27_CTRL1, 0x0c52),
MAKE_REG(SVLAN_MEMBERCFG27_CTRL2, 0x0c53),
MAKE_REG(SVLAN_MEMBERCFG27_CTRL3, 0x0c54),
MAKE_REG(SVLAN_MEMBERCFG28_CTRL1, 0x0c55),
MAKE_REG(SVLAN_MEMBERCFG28_CTRL2, 0x0c56),
MAKE_REG(SVLAN_MEMBERCFG28_CTRL3, 0x0c57),
MAKE_REG(SVLAN_MEMBERCFG29_CTRL1, 0x0c58),
MAKE_REG(SVLAN_MEMBERCFG29_CTRL2, 0x0c59),
MAKE_REG(SVLAN_MEMBERCFG29_CTRL3, 0x0c5a),
MAKE_REG(SVLAN_MEMBERCFG30_CTRL1, 0x0c5b),
MAKE_REG(SVLAN_MEMBERCFG30_CTRL2, 0x0c5c),
MAKE_REG(SVLAN_MEMBERCFG30_CTRL3, 0x0c5d),
MAKE_REG(SVLAN_MEMBERCFG31_CTRL1, 0x0c5e),
MAKE_REG(SVLAN_MEMBERCFG31_CTRL2, 0x0c5f),
MAKE_REG(SVLAN_MEMBERCFG31_CTRL3, 0x0c60),
MAKE_REG(SVLAN_MEMBERCFG32_CTRL1, 0x0c61),
MAKE_REG(SVLAN_MEMBERCFG32_CTRL2, 0x0c62),
MAKE_REG(SVLAN_MEMBERCFG32_CTRL3, 0x0c63),
MAKE_REG(SVLAN_MEMBERCFG33_CTRL1, 0x0c64),
MAKE_REG(SVLAN_MEMBERCFG33_CTRL2, 0x0c65),
MAKE_REG(SVLAN_MEMBERCFG33_CTRL3, 0x0c66),
MAKE_REG(SVLAN_MEMBERCFG34_CTRL1, 0x0c67),
MAKE_REG(SVLAN_MEMBERCFG34_CTRL2, 0x0c68),
MAKE_REG(SVLAN_MEMBERCFG34_CTRL3, 0x0c69),
MAKE_REG(SVLAN_MEMBERCFG35_CTRL1, 0x0c6a),
MAKE_REG(SVLAN_MEMBERCFG35_CTRL2, 0x0c6b),
MAKE_REG(SVLAN_MEMBERCFG35_CTRL3, 0x0c6c),
MAKE_REG(SVLAN_MEMBERCFG36_CTRL1, 0x0c6d),
MAKE_REG(SVLAN_MEMBERCFG36_CTRL2, 0x0c6e),
MAKE_REG(SVLAN_MEMBERCFG36_CTRL3, 0x0c6f),
MAKE_REG(SVLAN_MEMBERCFG37_CTRL1, 0x0c70),
MAKE_REG(SVLAN_MEMBERCFG37_CTRL2, 0x0c71),
MAKE_REG(SVLAN_MEMBERCFG37_CTRL3, 0x0c72),
MAKE_REG(SVLAN_MEMBERCFG38_CTRL1, 0x0c73),
MAKE_REG(SVLAN_MEMBERCFG38_CTRL2, 0x0c74),
MAKE_REG(SVLAN_MEMBERCFG38_CTRL3, 0x0c75),
MAKE_REG(SVLAN_MEMBERCFG39_CTRL1, 0x0c76),
MAKE_REG(SVLAN_MEMBERCFG39_CTRL2, 0x0c77),
MAKE_REG(SVLAN_MEMBERCFG39_CTRL3, 0x0c78),
MAKE_REG(SVLAN_MEMBERCFG40_CTRL1, 0x0c79),
MAKE_REG(SVLAN_MEMBERCFG40_CTRL2, 0x0c7a),
MAKE_REG(SVLAN_MEMBERCFG40_CTRL3, 0x0c7b),
MAKE_REG(SVLAN_MEMBERCFG41_CTRL1, 0x0c7c),
MAKE_REG(SVLAN_MEMBERCFG41_CTRL2, 0x0c7d),
MAKE_REG(SVLAN_MEMBERCFG41_CTRL3, 0x0c7e),
MAKE_REG(SVLAN_MEMBERCFG42_CTRL1, 0x0c7f),
MAKE_REG(SVLAN_MEMBERCFG42_CTRL2, 0x0c80),
MAKE_REG(SVLAN_MEMBERCFG42_CTRL3, 0x0c81),
MAKE_REG(SVLAN_MEMBERCFG43_CTRL1, 0x0c82),
MAKE_REG(SVLAN_MEMBERCFG43_CTRL2, 0x0c83),
MAKE_REG(SVLAN_MEMBERCFG43_CTRL3, 0x0c84),
MAKE_REG(SVLAN_MEMBERCFG44_CTRL1, 0x0c85),
MAKE_REG(SVLAN_MEMBERCFG44_CTRL2, 0x0c86),
MAKE_REG(SVLAN_MEMBERCFG44_CTRL3, 0x0c87),
MAKE_REG(SVLAN_MEMBERCFG45_CTRL1, 0x0c88),
MAKE_REG(SVLAN_MEMBERCFG45_CTRL2, 0x0c89),
MAKE_REG(SVLAN_MEMBERCFG45_CTRL3, 0x0c8a),
MAKE_REG(SVLAN_MEMBERCFG46_CTRL1, 0x0c8b),
MAKE_REG(SVLAN_MEMBERCFG46_CTRL2, 0x0c8c),
MAKE_REG(SVLAN_MEMBERCFG46_CTRL3, 0x0c8d),
MAKE_REG(SVLAN_MEMBERCFG47_CTRL1, 0x0c8e),
MAKE_REG(SVLAN_MEMBERCFG47_CTRL2, 0x0c8f),
MAKE_REG(SVLAN_MEMBERCFG47_CTRL3, 0x0c90),
MAKE_REG(SVLAN_MEMBERCFG48_CTRL1, 0x0c91),
MAKE_REG(SVLAN_MEMBERCFG48_CTRL2, 0x0c92),
MAKE_REG(SVLAN_MEMBERCFG48_CTRL3, 0x0c93),
MAKE_REG(SVLAN_MEMBERCFG49_CTRL1, 0x0c94),
MAKE_REG(SVLAN_MEMBERCFG49_CTRL2, 0x0c95),
MAKE_REG(SVLAN_MEMBERCFG49_CTRL3, 0x0c96),
MAKE_REG(SVLAN_MEMBERCFG50_CTRL1, 0x0c97),
MAKE_REG(SVLAN_MEMBERCFG50_CTRL2, 0x0c98),
MAKE_REG(SVLAN_MEMBERCFG50_CTRL3, 0x0c99),
MAKE_REG(SVLAN_MEMBERCFG51_CTRL1, 0x0c9a),
MAKE_REG(SVLAN_MEMBERCFG51_CTRL2, 0x0c9b),
MAKE_REG(SVLAN_MEMBERCFG51_CTRL3, 0x0c9c),
MAKE_REG(SVLAN_MEMBERCFG52_CTRL1, 0x0c9d),
MAKE_REG(SVLAN_MEMBERCFG52_CTRL2, 0x0c9e),
MAKE_REG(SVLAN_MEMBERCFG52_CTRL3, 0x0c9f),
MAKE_REG(SVLAN_MEMBERCFG53_CTRL1, 0x0ca0),
MAKE_REG(SVLAN_MEMBERCFG53_CTRL2, 0x0ca1),
MAKE_REG(SVLAN_MEMBERCFG53_CTRL3, 0x0ca2),
MAKE_REG(SVLAN_MEMBERCFG54_CTRL1, 0x0ca3),
MAKE_REG(SVLAN_MEMBERCFG54_CTRL2, 0x0ca4),
MAKE_REG(SVLAN_MEMBERCFG54_CTRL3, 0x0ca5),
MAKE_REG(SVLAN_MEMBERCFG55_CTRL1, 0x0ca6),
MAKE_REG(SVLAN_MEMBERCFG55_CTRL2, 0x0ca7),
MAKE_REG(SVLAN_MEMBERCFG55_CTRL3, 0x0ca8),
MAKE_REG(SVLAN_MEMBERCFG56_CTRL1, 0x0ca9),
MAKE_REG(SVLAN_MEMBERCFG56_CTRL2, 0x0caa),
MAKE_REG(SVLAN_MEMBERCFG56_CTRL3, 0x0cab),
MAKE_REG(SVLAN_MEMBERCFG57_CTRL1, 0x0cac),
MAKE_REG(SVLAN_MEMBERCFG57_CTRL2, 0x0cad),
MAKE_REG(SVLAN_MEMBERCFG57_CTRL3, 0x0cae),
MAKE_REG(SVLAN_MEMBERCFG58_CTRL1, 0x0caf),
MAKE_REG(SVLAN_MEMBERCFG58_CTRL2, 0x0cb0),
MAKE_REG(SVLAN_MEMBERCFG58_CTRL3, 0x0cb1),
MAKE_REG(SVLAN_MEMBERCFG59_CTRL1, 0x0cb2),
MAKE_REG(SVLAN_MEMBERCFG59_CTRL2, 0x0cb3),
MAKE_REG(SVLAN_MEMBERCFG59_CTRL3, 0x0cb4),
MAKE_REG(SVLAN_MEMBERCFG60_CTRL1, 0x0cb5),
MAKE_REG(SVLAN_MEMBERCFG60_CTRL2, 0x0cb6),
MAKE_REG(SVLAN_MEMBERCFG60_CTRL3, 0x0cb7),
MAKE_REG(SVLAN_MEMBERCFG61_CTRL1, 0x0cb8),
MAKE_REG(SVLAN_MEMBERCFG61_CTRL2, 0x0cb9),
MAKE_REG(SVLAN_MEMBERCFG61_CTRL3, 0x0cba),
MAKE_REG(SVLAN_MEMBERCFG62_CTRL1, 0x0cbb),
MAKE_REG(SVLAN_MEMBERCFG62_CTRL2, 0x0cbc),
MAKE_REG(SVLAN_MEMBERCFG62_CTRL3, 0x0cbd),
MAKE_REG(SVLAN_MEMBERCFG63_CTRL1, 0x0cbe),
MAKE_REG(SVLAN_MEMBERCFG63_CTRL2, 0x0cbf),
MAKE_REG(SVLAN_MEMBERCFG63_CTRL3, 0x0cc0),
MAKE_REG(SVLAN_MEMBERCFG0_CTRL4, 0x0cc1),
MAKE_REG(SVLAN_MEMBERCFG1_CTRL4, 0x0cc2),
MAKE_REG(SVLAN_MEMBERCFG2_CTRL4, 0x0cc3),
MAKE_REG(SVLAN_MEMBERCFG3_CTRL4, 0x0cc4),
MAKE_REG(SVLAN_MEMBERCFG4_CTRL4, 0x0cc5),
MAKE_REG(SVLAN_MEMBERCFG5_CTRL4, 0x0cc6),
MAKE_REG(SVLAN_MEMBERCFG6_CTRL4, 0x0cc7),
MAKE_REG(SVLAN_MEMBERCFG7_CTRL4, 0x0cc8),
MAKE_REG(SVLAN_MEMBERCFG8_CTRL4, 0x0cc9),
MAKE_REG(SVLAN_MEMBERCFG9_CTRL4, 0x0cca),
MAKE_REG(SVLAN_MEMBERCFG10_CTRL4, 0x0ccb),
MAKE_REG(SVLAN_MEMBERCFG11_CTRL4, 0x0ccc),
MAKE_REG(SVLAN_MEMBERCFG12_CTRL4, 0x0ccd),
MAKE_REG(SVLAN_MEMBERCFG13_CTRL4, 0x0cce),
MAKE_REG(SVLAN_MEMBERCFG14_CTRL4, 0x0ccf),
MAKE_REG(SVLAN_MEMBERCFG15_CTRL4, 0x0cd0),
MAKE_REG(SVLAN_MEMBERCFG16_CTRL4, 0x0cd1),
MAKE_REG(SVLAN_MEMBERCFG17_CTRL4, 0x0cd2),
MAKE_REG(SVLAN_MEMBERCFG18_CTRL4, 0x0cd3),
MAKE_REG(SVLAN_MEMBERCFG19_CTRL4, 0x0cd4),
MAKE_REG(SVLAN_MEMBERCFG20_CTRL4, 0x0cd5),
MAKE_REG(SVLAN_MEMBERCFG21_CTRL4, 0x0cd6),
MAKE_REG(SVLAN_MEMBERCFG22_CTRL4, 0x0cd7),
MAKE_REG(SVLAN_MEMBERCFG23_CTRL4, 0x0cd8),
MAKE_REG(SVLAN_MEMBERCFG24_CTRL4, 0x0cd9),
MAKE_REG(SVLAN_MEMBERCFG25_CTRL4, 0x0cda),
MAKE_REG(SVLAN_MEMBERCFG26_CTRL4, 0x0cdb),
MAKE_REG(SVLAN_MEMBERCFG27_CTRL4, 0x0cdc),
MAKE_REG(SVLAN_MEMBERCFG28_CTRL4, 0x0cdd),
MAKE_REG(SVLAN_MEMBERCFG29_CTRL4, 0x0cde),
MAKE_REG(SVLAN_MEMBERCFG30_CTRL4, 0x0cdf),
MAKE_REG(SVLAN_MEMBERCFG31_CTRL4, 0x0ce0),
MAKE_REG(SVLAN_MEMBERCFG32_CTRL4, 0x0ce1),
MAKE_REG(SVLAN_MEMBERCFG33_CTRL4, 0x0ce2),
MAKE_REG(SVLAN_MEMBERCFG34_CTRL4, 0x0ce3),
MAKE_REG(SVLAN_MEMBERCFG35_CTRL4, 0x0ce4),
MAKE_REG(SVLAN_MEMBERCFG36_CTRL4, 0x0ce5),
MAKE_REG(SVLAN_MEMBERCFG37_CTRL4, 0x0ce6),
MAKE_REG(SVLAN_MEMBERCFG38_CTRL4, 0x0ce7),
MAKE_REG(SVLAN_MEMBERCFG39_CTRL4, 0x0ce8),
MAKE_REG(SVLAN_MEMBERCFG40_CTRL4, 0x0ce9),
MAKE_REG(SVLAN_MEMBERCFG41_CTRL4, 0x0cea),
MAKE_REG(SVLAN_MEMBERCFG42_CTRL4, 0x0ceb),
MAKE_REG(SVLAN_MEMBERCFG43_CTRL4, 0x0cec),
MAKE_REG(SVLAN_MEMBERCFG44_CTRL4, 0x0ced),
MAKE_REG(SVLAN_MEMBERCFG45_CTRL4, 0x0cee),
MAKE_REG(SVLAN_MEMBERCFG46_CTRL4, 0x0cef),
MAKE_REG(SVLAN_MEMBERCFG47_CTRL4, 0x0cf0),
MAKE_REG(SVLAN_MEMBERCFG48_CTRL4, 0x0cf1),
MAKE_REG(SVLAN_MEMBERCFG49_CTRL4, 0x0cf2),
MAKE_REG(SVLAN_MEMBERCFG50_CTRL4, 0x0cf3),
MAKE_REG(SVLAN_MEMBERCFG51_CTRL4, 0x0cf4),
MAKE_REG(SVLAN_MEMBERCFG52_CTRL4, 0x0cf5),
MAKE_REG(SVLAN_MEMBERCFG53_CTRL4, 0x0cf6),
MAKE_REG(SVLAN_MEMBERCFG54_CTRL4, 0x0cf7),
MAKE_REG(SVLAN_MEMBERCFG55_CTRL4, 0x0cf8),
MAKE_REG(SVLAN_MEMBERCFG56_CTRL4, 0x0cf9),
MAKE_REG(SVLAN_MEMBERCFG57_CTRL4, 0x0cfa),
MAKE_REG(SVLAN_MEMBERCFG58_CTRL4, 0x0cfb),
MAKE_REG(SVLAN_MEMBERCFG59_CTRL4, 0x0cfc),
MAKE_REG(SVLAN_MEMBERCFG60_CTRL4, 0x0cfd),
MAKE_REG(SVLAN_MEMBERCFG61_CTRL4, 0x0cfe),
MAKE_REG(SVLAN_MEMBERCFG62_CTRL4, 0x0cff),
MAKE_REG(SVLAN_C2SCFG0_CTRL0, 0x0d00),
MAKE_REG(SVLAN_C2SCFG0_CTRL1, 0x0d01),
MAKE_REG(SVLAN_C2SCFG0_CTRL2, 0x0d02),
MAKE_REG(SVLAN_C2SCFG1_CTRL0, 0x0d03),
MAKE_REG(SVLAN_C2SCFG1_CTRL1, 0x0d04),
MAKE_REG(SVLAN_C2SCFG1_CTRL2, 0x0d05),
MAKE_REG(SVLAN_C2SCFG2_CTRL0, 0x0d06),
MAKE_REG(SVLAN_C2SCFG2_CTRL1, 0x0d07),
MAKE_REG(SVLAN_C2SCFG2_CTRL2, 0x0d08),
MAKE_REG(SVLAN_C2SCFG3_CTRL0, 0x0d09),
MAKE_REG(SVLAN_C2SCFG3_CTRL1, 0x0d0a),
MAKE_REG(SVLAN_C2SCFG3_CTRL2, 0x0d0b),
MAKE_REG(SVLAN_C2SCFG4_CTRL0, 0x0d0c),
MAKE_REG(SVLAN_C2SCFG4_CTRL1, 0x0d0d),
MAKE_REG(SVLAN_C2SCFG4_CTRL2, 0x0d0e),
MAKE_REG(SVLAN_C2SCFG5_CTRL0, 0x0d0f),
MAKE_REG(SVLAN_C2SCFG5_CTRL1, 0x0d10),
MAKE_REG(SVLAN_C2SCFG5_CTRL2, 0x0d11),
MAKE_REG(SVLAN_C2SCFG6_CTRL0, 0x0d12),
MAKE_REG(SVLAN_C2SCFG6_CTRL1, 0x0d13),
MAKE_REG(SVLAN_C2SCFG6_CTRL2, 0x0d14),
MAKE_REG(SVLAN_C2SCFG7_CTRL0, 0x0d15),
MAKE_REG(SVLAN_C2SCFG7_CTRL1, 0x0d16),
MAKE_REG(SVLAN_C2SCFG7_CTRL2, 0x0d17),
MAKE_REG(SVLAN_C2SCFG8_CTRL0, 0x0d18),
MAKE_REG(SVLAN_C2SCFG8_CTRL1, 0x0d19),
MAKE_REG(SVLAN_C2SCFG8_CTRL2, 0x0d1a),
MAKE_REG(SVLAN_C2SCFG9_CTRL0, 0x0d1b),
MAKE_REG(SVLAN_C2SCFG9_CTRL1, 0x0d1c),
MAKE_REG(SVLAN_C2SCFG9_CTRL2, 0x0d1d),
MAKE_REG(SVLAN_C2SCFG10_CTRL0, 0x0d1e),
MAKE_REG(SVLAN_C2SCFG10_CTRL1, 0x0d1f),
MAKE_REG(SVLAN_C2SCFG10_CTRL2, 0x0d20),
MAKE_REG(SVLAN_C2SCFG11_CTRL0, 0x0d21),
MAKE_REG(SVLAN_C2SCFG11_CTRL1, 0x0d22),
MAKE_REG(SVLAN_C2SCFG11_CTRL2, 0x0d23),
MAKE_REG(SVLAN_C2SCFG12_CTRL0, 0x0d24),
MAKE_REG(SVLAN_C2SCFG12_CTRL1, 0x0d25),
MAKE_REG(SVLAN_C2SCFG12_CTRL2, 0x0d26),
MAKE_REG(SVLAN_C2SCFG13_CTRL0, 0x0d27),
MAKE_REG(SVLAN_C2SCFG13_CTRL1, 0x0d28),
MAKE_REG(SVLAN_C2SCFG13_CTRL2, 0x0d29),
MAKE_REG(SVLAN_C2SCFG14_CTRL0, 0x0d2a),
MAKE_REG(SVLAN_C2SCFG14_CTRL1, 0x0d2b),
MAKE_REG(SVLAN_C2SCFG14_CTRL2, 0x0d2c),
MAKE_REG(SVLAN_C2SCFG15_CTRL0, 0x0d2d),
MAKE_REG(SVLAN_C2SCFG15_CTRL1, 0x0d2e),
MAKE_REG(SVLAN_C2SCFG15_CTRL2, 0x0d2f),
MAKE_REG(SVLAN_C2SCFG16_CTRL0, 0x0d30),
MAKE_REG(SVLAN_C2SCFG16_CTRL1, 0x0d31),
MAKE_REG(SVLAN_C2SCFG16_CTRL2, 0x0d32),
MAKE_REG(SVLAN_C2SCFG17_CTRL0, 0x0d33),
MAKE_REG(SVLAN_C2SCFG17_CTRL1, 0x0d34),
MAKE_REG(SVLAN_C2SCFG17_CTRL2, 0x0d35),
MAKE_REG(SVLAN_C2SCFG18_CTRL0, 0x0d36),
MAKE_REG(SVLAN_C2SCFG18_CTRL1, 0x0d37),
MAKE_REG(SVLAN_C2SCFG18_CTRL2, 0x0d38),
MAKE_REG(SVLAN_C2SCFG19_CTRL0, 0x0d39),
MAKE_REG(SVLAN_C2SCFG19_CTRL1, 0x0d3a),
MAKE_REG(SVLAN_C2SCFG19_CTRL2, 0x0d3b),
MAKE_REG(SVLAN_C2SCFG20_CTRL0, 0x0d3c),
MAKE_REG(SVLAN_C2SCFG20_CTRL1, 0x0d3d),
MAKE_REG(SVLAN_C2SCFG20_CTRL2, 0x0d3e),
MAKE_REG(SVLAN_C2SCFG21_CTRL0, 0x0d3f),
MAKE_REG(SVLAN_C2SCFG21_CTRL1, 0x0d40),
MAKE_REG(SVLAN_C2SCFG21_CTRL2, 0x0d41),
MAKE_REG(SVLAN_C2SCFG22_CTRL0, 0x0d42),
MAKE_REG(SVLAN_C2SCFG22_CTRL1, 0x0d43),
MAKE_REG(SVLAN_C2SCFG22_CTRL2, 0x0d44),
MAKE_REG(SVLAN_C2SCFG23_CTRL0, 0x0d45),
MAKE_REG(SVLAN_C2SCFG23_CTRL1, 0x0d46),
MAKE_REG(SVLAN_C2SCFG23_CTRL2, 0x0d47),
MAKE_REG(SVLAN_C2SCFG24_CTRL0, 0x0d48),
MAKE_REG(SVLAN_C2SCFG24_CTRL1, 0x0d49),
MAKE_REG(SVLAN_C2SCFG24_CTRL2, 0x0d4a),
MAKE_REG(SVLAN_C2SCFG25_CTRL0, 0x0d4b),
MAKE_REG(SVLAN_C2SCFG25_CTRL1, 0x0d4c),
MAKE_REG(SVLAN_C2SCFG25_CTRL2, 0x0d4d),
MAKE_REG(SVLAN_C2SCFG26_CTRL0, 0x0d4e),
MAKE_REG(SVLAN_C2SCFG26_CTRL1, 0x0d4f),
MAKE_REG(SVLAN_C2SCFG26_CTRL2, 0x0d50),
MAKE_REG(SVLAN_C2SCFG27_CTRL0, 0x0d51),
MAKE_REG(SVLAN_C2SCFG27_CTRL1, 0x0d52),
MAKE_REG(SVLAN_C2SCFG27_CTRL2, 0x0d53),
MAKE_REG(SVLAN_C2SCFG28_CTRL0, 0x0d54),
MAKE_REG(SVLAN_C2SCFG28_CTRL1, 0x0d55),
MAKE_REG(SVLAN_C2SCFG28_CTRL2, 0x0d56),
MAKE_REG(SVLAN_C2SCFG29_CTRL0, 0x0d57),
MAKE_REG(SVLAN_C2SCFG29_CTRL1, 0x0d58),
MAKE_REG(SVLAN_C2SCFG29_CTRL2, 0x0d59),
MAKE_REG(SVLAN_C2SCFG30_CTRL0, 0x0d5a),
MAKE_REG(SVLAN_C2SCFG30_CTRL1, 0x0d5b),
MAKE_REG(SVLAN_C2SCFG30_CTRL2, 0x0d5c),
MAKE_REG(SVLAN_C2SCFG31_CTRL0, 0x0d5d),
MAKE_REG(SVLAN_C2SCFG31_CTRL1, 0x0d5e),
MAKE_REG(SVLAN_C2SCFG31_CTRL2, 0x0d5f),
MAKE_REG(SVLAN_C2SCFG32_CTRL0, 0x0d60),
MAKE_REG(SVLAN_C2SCFG32_CTRL1, 0x0d61),
MAKE_REG(SVLAN_C2SCFG32_CTRL2, 0x0d62),
MAKE_REG(SVLAN_C2SCFG33_CTRL0, 0x0d63),
MAKE_REG(SVLAN_C2SCFG33_CTRL1, 0x0d64),
MAKE_REG(SVLAN_C2SCFG33_CTRL2, 0x0d65),
MAKE_REG(SVLAN_C2SCFG34_CTRL0, 0x0d66),
MAKE_REG(SVLAN_C2SCFG34_CTRL1, 0x0d67),
MAKE_REG(SVLAN_C2SCFG34_CTRL2, 0x0d68),
MAKE_REG(SVLAN_C2SCFG35_CTRL0, 0x0d69),
MAKE_REG(SVLAN_C2SCFG35_CTRL1, 0x0d6a),
MAKE_REG(SVLAN_C2SCFG35_CTRL2, 0x0d6b),
MAKE_REG(SVLAN_C2SCFG36_CTRL0, 0x0d6c),
MAKE_REG(SVLAN_C2SCFG36_CTRL1, 0x0d6d),
MAKE_REG(SVLAN_C2SCFG36_CTRL2, 0x0d6e),
MAKE_REG(SVLAN_C2SCFG37_CTRL0, 0x0d6f),
MAKE_REG(SVLAN_C2SCFG37_CTRL1, 0x0d70),
MAKE_REG(SVLAN_C2SCFG37_CTRL2, 0x0d71),
MAKE_REG(SVLAN_C2SCFG38_CTRL0, 0x0d72),
MAKE_REG(SVLAN_C2SCFG38_CTRL1, 0x0d73),
MAKE_REG(SVLAN_C2SCFG38_CTRL2, 0x0d74),
MAKE_REG(SVLAN_C2SCFG39_CTRL0, 0x0d75),
MAKE_REG(SVLAN_C2SCFG39_CTRL1, 0x0d76),
MAKE_REG(SVLAN_C2SCFG39_CTRL2, 0x0d77),
MAKE_REG(SVLAN_C2SCFG40_CTRL0, 0x0d78),
MAKE_REG(SVLAN_C2SCFG40_CTRL1, 0x0d79),
MAKE_REG(SVLAN_C2SCFG40_CTRL2, 0x0d7a),
MAKE_REG(SVLAN_C2SCFG41_CTRL0, 0x0d7b),
MAKE_REG(SVLAN_C2SCFG41_CTRL1, 0x0d7c),
MAKE_REG(SVLAN_C2SCFG41_CTRL2, 0x0d7d),
MAKE_REG(SVLAN_C2SCFG42_CTRL0, 0x0d7e),
MAKE_REG(SVLAN_C2SCFG42_CTRL1, 0x0d7f),
MAKE_REG(SVLAN_C2SCFG42_CTRL2, 0x0d80),
MAKE_REG(SVLAN_C2SCFG43_CTRL0, 0x0d81),
MAKE_REG(SVLAN_C2SCFG43_CTRL1, 0x0d82),
MAKE_REG(SVLAN_C2SCFG43_CTRL2, 0x0d83),
MAKE_REG(SVLAN_C2SCFG44_CTRL0, 0x0d84),
MAKE_REG(SVLAN_C2SCFG44_CTRL1, 0x0d85),
MAKE_REG(SVLAN_C2SCFG44_CTRL2, 0x0d86),
MAKE_REG(SVLAN_C2SCFG45_CTRL0, 0x0d87),
MAKE_REG(SVLAN_C2SCFG45_CTRL1, 0x0d88),
MAKE_REG(SVLAN_C2SCFG45_CTRL2, 0x0d89),
MAKE_REG(SVLAN_C2SCFG46_CTRL0, 0x0d8a),
MAKE_REG(SVLAN_C2SCFG46_CTRL1, 0x0d8b),
MAKE_REG(SVLAN_C2SCFG46_CTRL2, 0x0d8c),
MAKE_REG(SVLAN_C2SCFG47_CTRL0, 0x0d8d),
MAKE_REG(SVLAN_C2SCFG47_CTRL1, 0x0d8e),
MAKE_REG(SVLAN_C2SCFG47_CTRL2, 0x0d8f),
MAKE_REG(SVLAN_C2SCFG48_CTRL0, 0x0d90),
MAKE_REG(SVLAN_C2SCFG48_CTRL1, 0x0d91),
MAKE_REG(SVLAN_C2SCFG48_CTRL2, 0x0d92),
MAKE_REG(SVLAN_C2SCFG49_CTRL0, 0x0d93),
MAKE_REG(SVLAN_C2SCFG49_CTRL1, 0x0d94),
MAKE_REG(SVLAN_C2SCFG49_CTRL2, 0x0d95),
MAKE_REG(SVLAN_C2SCFG50_CTRL0, 0x0d96),
MAKE_REG(SVLAN_C2SCFG50_CTRL1, 0x0d97),
MAKE_REG(SVLAN_C2SCFG50_CTRL2, 0x0d98),
MAKE_REG(SVLAN_C2SCFG51_CTRL0, 0x0d99),
MAKE_REG(SVLAN_C2SCFG51_CTRL1, 0x0d9a),
MAKE_REG(SVLAN_C2SCFG51_CTRL2, 0x0d9b),
MAKE_REG(SVLAN_C2SCFG52_CTRL0, 0x0d9c),
MAKE_REG(SVLAN_C2SCFG52_CTRL1, 0x0d9d),
MAKE_REG(SVLAN_C2SCFG52_CTRL2, 0x0d9e),
MAKE_REG(SVLAN_C2SCFG53_CTRL0, 0x0d9f),
MAKE_REG(SVLAN_C2SCFG53_CTRL1, 0x0da0),
MAKE_REG(SVLAN_C2SCFG53_CTRL2, 0x0da1),
MAKE_REG(SVLAN_C2SCFG54_CTRL0, 0x0da2),
MAKE_REG(SVLAN_C2SCFG54_CTRL1, 0x0da3),
MAKE_REG(SVLAN_C2SCFG54_CTRL2, 0x0da4),
MAKE_REG(SVLAN_C2SCFG55_CTRL0, 0x0da5),
MAKE_REG(SVLAN_C2SCFG55_CTRL1, 0x0da6),
MAKE_REG(SVLAN_C2SCFG55_CTRL2, 0x0da7),
MAKE_REG(SVLAN_C2SCFG56_CTRL0, 0x0da8),
MAKE_REG(SVLAN_C2SCFG56_CTRL1, 0x0da9),
MAKE_REG(SVLAN_C2SCFG56_CTRL2, 0x0daa),
MAKE_REG(SVLAN_C2SCFG57_CTRL0, 0x0dab),
MAKE_REG(SVLAN_C2SCFG57_CTRL1, 0x0dac),
MAKE_REG(SVLAN_C2SCFG57_CTRL2, 0x0dad),
MAKE_REG(SVLAN_C2SCFG58_CTRL0, 0x0dae),
MAKE_REG(SVLAN_C2SCFG58_CTRL1, 0x0daf),
MAKE_REG(SVLAN_C2SCFG58_CTRL2, 0x0db0),
MAKE_REG(SVLAN_C2SCFG59_CTRL0, 0x0db1),
MAKE_REG(SVLAN_C2SCFG59_CTRL1, 0x0db2),
MAKE_REG(SVLAN_C2SCFG59_CTRL2, 0x0db3),
MAKE_REG(SVLAN_C2SCFG60_CTRL0, 0x0db4),
MAKE_REG(SVLAN_C2SCFG60_CTRL1, 0x0db5),
MAKE_REG(SVLAN_C2SCFG60_CTRL2, 0x0db6),
MAKE_REG(SVLAN_C2SCFG61_CTRL0, 0x0db7),
MAKE_REG(SVLAN_C2SCFG61_CTRL1, 0x0db8),
MAKE_REG(SVLAN_C2SCFG61_CTRL2, 0x0db9),
MAKE_REG(SVLAN_C2SCFG62_CTRL0, 0x0dba),
MAKE_REG(SVLAN_C2SCFG62_CTRL1, 0x0dbb),
MAKE_REG(SVLAN_C2SCFG62_CTRL2, 0x0dbc),
MAKE_REG(SVLAN_C2SCFG63_CTRL0, 0x0dbd),
MAKE_REG(SVLAN_C2SCFG63_CTRL1, 0x0dbe),
MAKE_REG(SVLAN_C2SCFG63_CTRL2, 0x0dbf),
MAKE_REG(SVLAN_C2SCFG64_CTRL0, 0x0dc0),
MAKE_REG(SVLAN_C2SCFG64_CTRL1, 0x0dc1),
MAKE_REG(SVLAN_C2SCFG64_CTRL2, 0x0dc2),
MAKE_REG(SVLAN_C2SCFG65_CTRL0, 0x0dc3),
MAKE_REG(SVLAN_C2SCFG65_CTRL1, 0x0dc4),
MAKE_REG(SVLAN_C2SCFG65_CTRL2, 0x0dc5),
MAKE_REG(SVLAN_C2SCFG66_CTRL0, 0x0dc6),
MAKE_REG(SVLAN_C2SCFG66_CTRL1, 0x0dc7),
MAKE_REG(SVLAN_C2SCFG66_CTRL2, 0x0dc8),
MAKE_REG(SVLAN_C2SCFG67_CTRL0, 0x0dc9),
MAKE_REG(SVLAN_C2SCFG67_CTRL1, 0x0dca),
MAKE_REG(SVLAN_C2SCFG67_CTRL2, 0x0dcb),
MAKE_REG(SVLAN_C2SCFG68_CTRL0, 0x0dcc),
MAKE_REG(SVLAN_C2SCFG68_CTRL1, 0x0dcd),
MAKE_REG(SVLAN_C2SCFG68_CTRL2, 0x0dce),
MAKE_REG(SVLAN_C2SCFG69_CTRL0, 0x0dcf),
MAKE_REG(SVLAN_C2SCFG69_CTRL1, 0x0dd0),
MAKE_REG(SVLAN_C2SCFG69_CTRL2, 0x0dd1),
MAKE_REG(SVLAN_C2SCFG70_CTRL0, 0x0dd2),
MAKE_REG(SVLAN_C2SCFG70_CTRL1, 0x0dd3),
MAKE_REG(SVLAN_C2SCFG70_CTRL2, 0x0dd4),
MAKE_REG(SVLAN_C2SCFG71_CTRL0, 0x0dd5),
MAKE_REG(SVLAN_C2SCFG71_CTRL1, 0x0dd6),
MAKE_REG(SVLAN_C2SCFG71_CTRL2, 0x0dd7),
MAKE_REG(SVLAN_C2SCFG72_CTRL0, 0x0dd8),
MAKE_REG(SVLAN_C2SCFG72_CTRL1, 0x0dd9),
MAKE_REG(SVLAN_C2SCFG72_CTRL2, 0x0dda),
MAKE_REG(SVLAN_C2SCFG73_CTRL0, 0x0ddb),
MAKE_REG(SVLAN_C2SCFG73_CTRL1, 0x0ddc),
MAKE_REG(SVLAN_C2SCFG73_CTRL2, 0x0ddd),
MAKE_REG(SVLAN_C2SCFG74_CTRL0, 0x0dde),
MAKE_REG(SVLAN_C2SCFG74_CTRL1, 0x0ddf),
MAKE_REG(SVLAN_C2SCFG74_CTRL2, 0x0de0),
MAKE_REG(SVLAN_C2SCFG75_CTRL0, 0x0de1),
MAKE_REG(SVLAN_C2SCFG75_CTRL1, 0x0de2),
MAKE_REG(SVLAN_C2SCFG75_CTRL2, 0x0de3),
MAKE_REG(SVLAN_C2SCFG76_CTRL0, 0x0de4),
MAKE_REG(SVLAN_C2SCFG76_CTRL1, 0x0de5),
MAKE_REG(SVLAN_C2SCFG76_CTRL2, 0x0de6),
MAKE_REG(SVLAN_C2SCFG77_CTRL0, 0x0de7),
MAKE_REG(SVLAN_C2SCFG77_CTRL1, 0x0de8),
MAKE_REG(SVLAN_C2SCFG77_CTRL2, 0x0de9),
MAKE_REG(SVLAN_C2SCFG78_CTRL0, 0x0dea),
MAKE_REG(SVLAN_C2SCFG78_CTRL1, 0x0deb),
MAKE_REG(SVLAN_C2SCFG78_CTRL2, 0x0dec),
MAKE_REG(SVLAN_C2SCFG79_CTRL0, 0x0ded),
MAKE_REG(SVLAN_C2SCFG79_CTRL1, 0x0dee),
MAKE_REG(SVLAN_C2SCFG79_CTRL2, 0x0def),
MAKE_REG(SVLAN_C2SCFG80_CTRL0, 0x0df0),
MAKE_REG(SVLAN_C2SCFG80_CTRL1, 0x0df1),
MAKE_REG(SVLAN_C2SCFG80_CTRL2, 0x0df2),
MAKE_REG(SVLAN_C2SCFG81_CTRL0, 0x0df3),
MAKE_REG(SVLAN_C2SCFG81_CTRL1, 0x0df4),
MAKE_REG(SVLAN_C2SCFG81_CTRL2, 0x0df5),
MAKE_REG(SVLAN_C2SCFG82_CTRL0, 0x0df6),
MAKE_REG(SVLAN_C2SCFG82_CTRL1, 0x0df7),
MAKE_REG(SVLAN_C2SCFG82_CTRL2, 0x0df8),
MAKE_REG(SVLAN_C2SCFG83_CTRL0, 0x0df9),
MAKE_REG(SVLAN_C2SCFG83_CTRL1, 0x0dfa),
MAKE_REG(SVLAN_C2SCFG83_CTRL2, 0x0dfb),
MAKE_REG(SVLAN_C2SCFG84_CTRL0, 0x0dfc),
MAKE_REG(SVLAN_C2SCFG84_CTRL1, 0x0dfd),
MAKE_REG(SVLAN_C2SCFG84_CTRL2, 0x0dfe),
MAKE_REG(SVLAN_C2SCFG85_CTRL0, 0x0dff),
MAKE_REG(SVLAN_C2SCFG85_CTRL1, 0x0e00),
MAKE_REG(SVLAN_C2SCFG85_CTRL2, 0x0e01),
MAKE_REG(SVLAN_C2SCFG86_CTRL0, 0x0e02),
MAKE_REG(SVLAN_C2SCFG86_CTRL1, 0x0e03),
MAKE_REG(SVLAN_C2SCFG86_CTRL2, 0x0e04),
MAKE_REG(SVLAN_C2SCFG87_CTRL0, 0x0e05),
MAKE_REG(SVLAN_C2SCFG87_CTRL1, 0x0e06),
MAKE_REG(SVLAN_C2SCFG87_CTRL2, 0x0e07),
MAKE_REG(SVLAN_C2SCFG88_CTRL0, 0x0e08),
MAKE_REG(SVLAN_C2SCFG88_CTRL1, 0x0e09),
MAKE_REG(SVLAN_C2SCFG88_CTRL2, 0x0e0a),
MAKE_REG(SVLAN_C2SCFG89_CTRL0, 0x0e0b),
MAKE_REG(SVLAN_C2SCFG89_CTRL1, 0x0e0c),
MAKE_REG(SVLAN_C2SCFG89_CTRL2, 0x0e0d),
MAKE_REG(SVLAN_C2SCFG90_CTRL0, 0x0e0e),
MAKE_REG(SVLAN_C2SCFG90_CTRL1, 0x0e0f),
MAKE_REG(SVLAN_C2SCFG90_CTRL2, 0x0e10),
MAKE_REG(SVLAN_C2SCFG91_CTRL0, 0x0e11),
MAKE_REG(SVLAN_C2SCFG91_CTRL1, 0x0e12),
MAKE_REG(SVLAN_C2SCFG91_CTRL2, 0x0e13),
MAKE_REG(SVLAN_C2SCFG92_CTRL0, 0x0e14),
MAKE_REG(SVLAN_C2SCFG92_CTRL1, 0x0e15),
MAKE_REG(SVLAN_C2SCFG92_CTRL2, 0x0e16),
MAKE_REG(SVLAN_C2SCFG93_CTRL0, 0x0e17),
MAKE_REG(SVLAN_C2SCFG93_CTRL1, 0x0e18),
MAKE_REG(SVLAN_C2SCFG93_CTRL2, 0x0e19),
MAKE_REG(SVLAN_C2SCFG94_CTRL0, 0x0e1a),
MAKE_REG(SVLAN_C2SCFG94_CTRL1, 0x0e1b),
MAKE_REG(SVLAN_C2SCFG94_CTRL2, 0x0e1c),
MAKE_REG(SVLAN_C2SCFG95_CTRL0, 0x0e1d),
MAKE_REG(SVLAN_C2SCFG95_CTRL1, 0x0e1e),
MAKE_REG(SVLAN_C2SCFG95_CTRL2, 0x0e1f),
MAKE_REG(SVLAN_C2SCFG96_CTRL0, 0x0e20),
MAKE_REG(SVLAN_C2SCFG96_CTRL1, 0x0e21),
MAKE_REG(SVLAN_C2SCFG96_CTRL2, 0x0e22),
MAKE_REG(SVLAN_C2SCFG97_CTRL0, 0x0e23),
MAKE_REG(SVLAN_C2SCFG97_CTRL1, 0x0e24),
MAKE_REG(SVLAN_C2SCFG97_CTRL2, 0x0e25),
MAKE_REG(SVLAN_C2SCFG98_CTRL0, 0x0e26),
MAKE_REG(SVLAN_C2SCFG98_CTRL1, 0x0e27),
MAKE_REG(SVLAN_C2SCFG98_CTRL2, 0x0e28),
MAKE_REG(SVLAN_C2SCFG99_CTRL0, 0x0e29),
MAKE_REG(SVLAN_C2SCFG99_CTRL1, 0x0e2a),
MAKE_REG(SVLAN_C2SCFG99_CTRL2, 0x0e2b),
MAKE_REG(SVLAN_C2SCFG100_CTRL0, 0x0e2c),
MAKE_REG(SVLAN_C2SCFG100_CTRL1, 0x0e2d),
MAKE_REG(SVLAN_C2SCFG100_CTRL2, 0x0e2e),
MAKE_REG(SVLAN_C2SCFG101_CTRL0, 0x0e2f),
MAKE_REG(SVLAN_C2SCFG101_CTRL1, 0x0e30),
MAKE_REG(SVLAN_C2SCFG101_CTRL2, 0x0e31),
MAKE_REG(SVLAN_C2SCFG102_CTRL0, 0x0e32),
MAKE_REG(SVLAN_C2SCFG102_CTRL1, 0x0e33),
MAKE_REG(SVLAN_C2SCFG102_CTRL2, 0x0e34),
MAKE_REG(SVLAN_C2SCFG103_CTRL0, 0x0e35),
MAKE_REG(SVLAN_C2SCFG103_CTRL1, 0x0e36),
MAKE_REG(SVLAN_C2SCFG103_CTRL2, 0x0e37),
MAKE_REG(SVLAN_C2SCFG104_CTRL0, 0x0e38),
MAKE_REG(SVLAN_C2SCFG104_CTRL1, 0x0e39),
MAKE_REG(SVLAN_C2SCFG104_CTRL2, 0x0e3a),
MAKE_REG(SVLAN_C2SCFG105_CTRL0, 0x0e3b),
MAKE_REG(SVLAN_C2SCFG105_CTRL1, 0x0e3c),
MAKE_REG(SVLAN_C2SCFG105_CTRL2, 0x0e3d),
MAKE_REG(SVLAN_C2SCFG106_CTRL0, 0x0e3e),
MAKE_REG(SVLAN_C2SCFG106_CTRL1, 0x0e3f),
MAKE_REG(SVLAN_C2SCFG106_CTRL2, 0x0e40),
MAKE_REG(SVLAN_C2SCFG107_CTRL0, 0x0e41),
MAKE_REG(SVLAN_C2SCFG107_CTRL1, 0x0e42),
MAKE_REG(SVLAN_C2SCFG107_CTRL2, 0x0e43),
MAKE_REG(SVLAN_C2SCFG108_CTRL0, 0x0e44),
MAKE_REG(SVLAN_C2SCFG108_CTRL1, 0x0e45),
MAKE_REG(SVLAN_C2SCFG108_CTRL2, 0x0e46),
MAKE_REG(SVLAN_C2SCFG109_CTRL0, 0x0e47),
MAKE_REG(SVLAN_C2SCFG109_CTRL1, 0x0e48),
MAKE_REG(SVLAN_C2SCFG109_CTRL2, 0x0e49),
MAKE_REG(SVLAN_C2SCFG110_CTRL0, 0x0e4a),
MAKE_REG(SVLAN_C2SCFG110_CTRL1, 0x0e4b),
MAKE_REG(SVLAN_C2SCFG110_CTRL2, 0x0e4c),
MAKE_REG(SVLAN_C2SCFG111_CTRL0, 0x0e4d),
MAKE_REG(SVLAN_C2SCFG111_CTRL1, 0x0e4e),
MAKE_REG(SVLAN_C2SCFG111_CTRL2, 0x0e4f),
MAKE_REG(SVLAN_C2SCFG112_CTRL0, 0x0e50),
MAKE_REG(SVLAN_C2SCFG112_CTRL1, 0x0e51),
MAKE_REG(SVLAN_C2SCFG112_CTRL2, 0x0e52),
MAKE_REG(SVLAN_C2SCFG113_CTRL0, 0x0e53),
MAKE_REG(SVLAN_C2SCFG113_CTRL1, 0x0e54),
MAKE_REG(SVLAN_C2SCFG113_CTRL2, 0x0e55),
MAKE_REG(SVLAN_C2SCFG114_CTRL0, 0x0e56),
MAKE_REG(SVLAN_C2SCFG114_CTRL1, 0x0e57),
MAKE_REG(SVLAN_C2SCFG114_CTRL2, 0x0e58),
MAKE_REG(SVLAN_C2SCFG115_CTRL0, 0x0e59),
MAKE_REG(SVLAN_C2SCFG115_CTRL1, 0x0e5a),
MAKE_REG(SVLAN_C2SCFG115_CTRL2, 0x0e5b),
MAKE_REG(SVLAN_C2SCFG116_CTRL0, 0x0e5c),
MAKE_REG(SVLAN_C2SCFG116_CTRL1, 0x0e5d),
MAKE_REG(SVLAN_C2SCFG116_CTRL2, 0x0e5e),
MAKE_REG(SVLAN_C2SCFG117_CTRL0, 0x0e5f),
MAKE_REG(SVLAN_C2SCFG117_CTRL1, 0x0e60),
MAKE_REG(SVLAN_C2SCFG117_CTRL2, 0x0e61),
MAKE_REG(SVLAN_C2SCFG118_CTRL0, 0x0e62),
MAKE_REG(SVLAN_C2SCFG118_CTRL1, 0x0e63),
MAKE_REG(SVLAN_C2SCFG118_CTRL2, 0x0e64),
MAKE_REG(SVLAN_C2SCFG119_CTRL0, 0x0e65),
MAKE_REG(SVLAN_C2SCFG119_CTRL1, 0x0e66),
MAKE_REG(SVLAN_C2SCFG119_CTRL2, 0x0e67),
MAKE_REG(SVLAN_C2SCFG120_CTRL0, 0x0e68),
MAKE_REG(SVLAN_C2SCFG120_CTRL1, 0x0e69),
MAKE_REG(SVLAN_C2SCFG120_CTRL2, 0x0e6a),
MAKE_REG(SVLAN_C2SCFG121_CTRL0, 0x0e6b),
MAKE_REG(SVLAN_C2SCFG121_CTRL1, 0x0e6c),
MAKE_REG(SVLAN_C2SCFG121_CTRL2, 0x0e6d),
MAKE_REG(SVLAN_C2SCFG122_CTRL0, 0x0e6e),
MAKE_REG(SVLAN_C2SCFG122_CTRL1, 0x0e6f),
MAKE_REG(SVLAN_C2SCFG122_CTRL2, 0x0e70),
MAKE_REG(SVLAN_C2SCFG123_CTRL0, 0x0e71),
MAKE_REG(SVLAN_C2SCFG123_CTRL1, 0x0e72),
MAKE_REG(SVLAN_C2SCFG123_CTRL2, 0x0e73),
MAKE_REG(SVLAN_C2SCFG124_CTRL0, 0x0e74),
MAKE_REG(SVLAN_C2SCFG124_CTRL1, 0x0e75),
MAKE_REG(SVLAN_C2SCFG124_CTRL2, 0x0e76),
MAKE_REG(SVLAN_C2SCFG125_CTRL0, 0x0e77),
MAKE_REG(SVLAN_C2SCFG125_CTRL1, 0x0e78),
MAKE_REG(SVLAN_C2SCFG125_CTRL2, 0x0e79),
MAKE_REG(SVLAN_C2SCFG126_CTRL0, 0x0e7a),
MAKE_REG(SVLAN_C2SCFG126_CTRL1, 0x0e7b),
MAKE_REG(SVLAN_C2SCFG126_CTRL2, 0x0e7c),
MAKE_REG(SVLAN_C2SCFG127_CTRL0, 0x0e7d),
MAKE_REG(SVLAN_C2SCFG127_CTRL1, 0x0e7e),
MAKE_REG(SVLAN_C2SCFG127_CTRL2, 0x0e7f),
MAKE_REG(SVLAN_CFG, 0x0e80),
MAKE_REG(SVLAN_PORTBASED_SVIDX_CTRL0, 0x0e81),
MAKE_REG(SVLAN_PORTBASED_SVIDX_CTRL1, 0x0e82),
MAKE_REG(SVLAN_PORTBASED_SVIDX_CTRL2, 0x0e83),
MAKE_REG(SVLAN_PORTBASED_SVIDX_CTRL3, 0x0e84),
MAKE_REG(SVLAN_UNTAG_UNMAT_CFG, 0x0e85),
MAKE_REG(SVLAN_LOOKUP_TYPE, 0x0e86),
MAKE_REG(IPMC_GROUP_VALID_15_0, 0x0e87),
MAKE_REG(IPMC_GROUP_VALID_31_16, 0x0e88),
MAKE_REG(IPMC_GROUP_VALID_47_32, 0x0e89),
MAKE_REG(IPMC_GROUP_VALID_63_48, 0x0e8a),
MAKE_REG(SVLAN_PORTBASED_SVIDX_CTRL4, 0x0e8b),
MAKE_REG(SVLAN_PORTBASED_SVIDX_CTRL5, 0x0e8c),
MAKE_REG(SVLAN_CFG_EXT, 0x0e8d),
MAKE_REG(SVLAN_MEMBERCFG63_CTRL4, 0x0e8e),
MAKE_REG(SVLAN_DUMMY_0, 0x0e90),
MAKE_REG(SVLAN_DUMMY_1, 0x0e91),
MAKE_REG(SVLAN_DUMMY_2, 0x0e92),
MAKE_REG(SVLAN_DUMMY_3, 0x0e93),
MAKE_REG(SVLAN_DUMMY_4, 0x0e94),
MAKE_REG(SVLAN_DUMMY_5, 0x0e95),
MAKE_REG(SVLAN_DUMMY_6, 0x0e96),
MAKE_REG(SVLAN_DUMMY_7, 0x0e97),
MAKE_REG(SVLAN_DUMMY_8, 0x0e98),
MAKE_REG(SVLAN_DUMMY_9, 0x0e99),
MAKE_REG(SVLAN_DUMMY_10, 0x0e9a),
MAKE_REG(SVLAN_DUMMY_11, 0x0e9b),
MAKE_REG(SVLAN_DUMMY_12, 0x0e9c),
MAKE_REG(SVLAN_DUMMY_13, 0x0e9d),
MAKE_REG(SVLAN_DUMMY_14, 0x0e9e),
MAKE_REG(SVLAN_DUMMY_15, 0x0e9f),
MAKE_REG(SVLAN_DUMMY_16, 0x0ea0),
MAKE_REG(SVLAN_DUMMY_17, 0x0ea1),
MAKE_REG(SVLAN_DUMMY_18, 0x0ea2),
MAKE_REG(SVLAN_DUMMY_19, 0x0ea3),
MAKE_REG(SVLAN_DUMMY_20, 0x0ea4),
MAKE_REG(SVLAN_DUMMY_21, 0x0ea5),
MAKE_REG(SVLAN_DUMMY_22, 0x0ea6),
MAKE_REG(SVLAN_DUMMY_23, 0x0ea7),
MAKE_REG(SVLAN_DUMMY_24, 0x0ea8),
MAKE_REG(SVLAN_DUMMY_25, 0x0ea9),
MAKE_REG(SVLAN_DUMMY_26, 0x0eaa),
MAKE_REG(SVLAN_DUMMY_27, 0x0eab),
MAKE_REG(SVLAN_DUMMY_28, 0x0eac),
MAKE_REG(SVLAN_DUMMY_29, 0x0ead),
MAKE_REG(SVLAN_DUMMY_30, 0x0eae),
MAKE_REG(SVLAN_DUMMY_31, 0x0eaf),
MAKE_REG(IPMC_GROUP_VID_00, 0x0eb0),
MAKE_REG(IPMC_GROUP_VID_01, 0x0eb1),
MAKE_REG(IPMC_GROUP_VID_02, 0x0eb2),
MAKE_REG(IPMC_GROUP_VID_03, 0x0eb3),
MAKE_REG(IPMC_GROUP_VID_04, 0x0eb4),
MAKE_REG(IPMC_GROUP_VID_05, 0x0eb5),
MAKE_REG(IPMC_GROUP_VID_06, 0x0eb6),
MAKE_REG(IPMC_GROUP_VID_07, 0x0eb7),
MAKE_REG(IPMC_GROUP_VID_08, 0x0eb8),
MAKE_REG(IPMC_GROUP_VID_09, 0x0eb9),
MAKE_REG(IPMC_GROUP_VID_10, 0x0eba),
MAKE_REG(IPMC_GROUP_VID_11, 0x0ebb),
MAKE_REG(IPMC_GROUP_VID_12, 0x0ebc),
MAKE_REG(IPMC_GROUP_VID_13, 0x0ebd),
MAKE_REG(IPMC_GROUP_VID_14, 0x0ebe),
MAKE_REG(IPMC_GROUP_VID_15, 0x0ebf),
MAKE_REG(IPMC_GROUP_VID_16, 0x0ec0),
MAKE_REG(IPMC_GROUP_VID_17, 0x0ec1),
MAKE_REG(IPMC_GROUP_VID_18, 0x0ec2),
MAKE_REG(IPMC_GROUP_VID_19, 0x0ec3),
MAKE_REG(IPMC_GROUP_VID_20, 0x0ec4),
MAKE_REG(IPMC_GROUP_VID_21, 0x0ec5),
MAKE_REG(IPMC_GROUP_VID_22, 0x0ec6),
MAKE_REG(IPMC_GROUP_VID_23, 0x0ec7),
MAKE_REG(IPMC_GROUP_VID_24, 0x0ec8),
MAKE_REG(IPMC_GROUP_VID_25, 0x0ec9),
MAKE_REG(IPMC_GROUP_VID_26, 0x0eca),
MAKE_REG(IPMC_GROUP_VID_27, 0x0ecb),
MAKE_REG(IPMC_GROUP_VID_28, 0x0ecc),
MAKE_REG(IPMC_GROUP_VID_29, 0x0ecd),
MAKE_REG(IPMC_GROUP_VID_30, 0x0ece),
MAKE_REG(IPMC_GROUP_VID_31, 0x0ecf),
MAKE_REG(IPMC_GROUP_VID_32, 0x0ed0),
MAKE_REG(IPMC_GROUP_VID_33, 0x0ed1),
MAKE_REG(IPMC_GROUP_VID_34, 0x0ed2),
MAKE_REG(IPMC_GROUP_VID_35, 0x0ed3),
MAKE_REG(IPMC_GROUP_VID_36, 0x0ed4),
MAKE_REG(IPMC_GROUP_VID_37, 0x0ed5),
MAKE_REG(IPMC_GROUP_VID_38, 0x0ed6),
MAKE_REG(IPMC_GROUP_VID_39, 0x0ed7),
MAKE_REG(IPMC_GROUP_VID_40, 0x0ed8),
MAKE_REG(IPMC_GROUP_VID_41, 0x0ed9),
MAKE_REG(IPMC_GROUP_VID_42, 0x0eda),
MAKE_REG(IPMC_GROUP_VID_43, 0x0edb),
MAKE_REG(IPMC_GROUP_VID_44, 0x0edc),
MAKE_REG(IPMC_GROUP_VID_45, 0x0edd),
MAKE_REG(IPMC_GROUP_VID_46, 0x0ede),
MAKE_REG(IPMC_GROUP_VID_47, 0x0edf),
MAKE_REG(IPMC_GROUP_VID_48, 0x0ef0),
MAKE_REG(IPMC_GROUP_VID_49, 0x0ef1),
MAKE_REG(IPMC_GROUP_VID_50, 0x0ef2),
MAKE_REG(IPMC_GROUP_VID_51, 0x0ef3),
MAKE_REG(IPMC_GROUP_VID_52, 0x0ef4),
MAKE_REG(IPMC_GROUP_VID_53, 0x0ef5),
MAKE_REG(IPMC_GROUP_VID_54, 0x0ef6),
MAKE_REG(IPMC_GROUP_VID_55, 0x0ef7),
MAKE_REG(IPMC_GROUP_VID_56, 0x0ef8),
MAKE_REG(IPMC_GROUP_VID_57, 0x0ef9),
MAKE_REG(IPMC_GROUP_VID_58, 0x0efa),
MAKE_REG(IPMC_GROUP_VID_59, 0x0efb),
MAKE_REG(IPMC_GROUP_VID_60, 0x0efc),
MAKE_REG(IPMC_GROUP_VID_61, 0x0efd),
MAKE_REG(IPMC_GROUP_VID_62, 0x0efe),
MAKE_REG(IPMC_GROUP_VID_63, 0x0eff),
MAKE_REG(SVLAN_SP2C_ENTRY0_CTRL0, 0x0f00),
MAKE_REG(SVLAN_SP2C_ENTRY0_CTRL1, 0x0f01),
MAKE_REG(SVLAN_SP2C_ENTRY1_CTRL0, 0x0f02),
MAKE_REG(SVLAN_SP2C_ENTRY1_CTRL1, 0x0f03),
MAKE_REG(SVLAN_SP2C_ENTRY2_CTRL0, 0x0f04),
MAKE_REG(SVLAN_SP2C_ENTRY2_CTRL1, 0x0f05),
MAKE_REG(SVLAN_SP2C_ENTRY3_CTRL0, 0x0f06),
MAKE_REG(SVLAN_SP2C_ENTRY3_CTRL1, 0x0f07),
MAKE_REG(SVLAN_SP2C_ENTRY4_CTRL0, 0x0f08),
MAKE_REG(SVLAN_SP2C_ENTRY4_CTRL1, 0x0f09),
MAKE_REG(SVLAN_SP2C_ENTRY5_CTRL0, 0x0f0a),
MAKE_REG(SVLAN_SP2C_ENTRY5_CTRL1, 0x0f0b),
MAKE_REG(SVLAN_SP2C_ENTRY6_CTRL0, 0x0f0c),
MAKE_REG(SVLAN_SP2C_ENTRY6_CTRL1, 0x0f0d),
MAKE_REG(SVLAN_SP2C_ENTRY7_CTRL0, 0x0f0e),
MAKE_REG(SVLAN_SP2C_ENTRY7_CTRL1, 0x0f0f),
MAKE_REG(SVLAN_SP2C_ENTRY8_CTRL0, 0x0f10),
MAKE_REG(SVLAN_SP2C_ENTRY8_CTRL1, 0x0f11),
MAKE_REG(SVLAN_SP2C_ENTRY9_CTRL0, 0x0f12),
MAKE_REG(SVLAN_SP2C_ENTRY9_CTRL1, 0x0f13),
MAKE_REG(SVLAN_SP2C_ENTRY10_CTRL0, 0x0f14),
MAKE_REG(SVLAN_SP2C_ENTRY10_CTRL1, 0x0f15),
MAKE_REG(SVLAN_SP2C_ENTRY11_CTRL0, 0x0f16),
MAKE_REG(SVLAN_SP2C_ENTRY11_CTRL1, 0x0f17),
MAKE_REG(SVLAN_SP2C_ENTRY12_CTRL0, 0x0f18),
MAKE_REG(SVLAN_SP2C_ENTRY12_CTRL1, 0x0f19),
MAKE_REG(SVLAN_SP2C_ENTRY13_CTRL0, 0x0f1a),
MAKE_REG(SVLAN_SP2C_ENTRY13_CTRL1, 0x0f1b),
MAKE_REG(SVLAN_SP2C_ENTRY14_CTRL0, 0x0f1c),
MAKE_REG(SVLAN_SP2C_ENTRY14_CTRL1, 0x0f1d),
MAKE_REG(SVLAN_SP2C_ENTRY15_CTRL0, 0x0f1e),
MAKE_REG(SVLAN_SP2C_ENTRY15_CTRL1, 0x0f1f),
MAKE_REG(SVLAN_SP2C_ENTRY16_CTRL0, 0x0f20),
MAKE_REG(SVLAN_SP2C_ENTRY16_CTRL1, 0x0f21),
MAKE_REG(SVLAN_SP2C_ENTRY17_CTRL0, 0x0f22),
MAKE_REG(SVLAN_SP2C_ENTRY17_CTRL1, 0x0f23),
MAKE_REG(SVLAN_SP2C_ENTRY18_CTRL0, 0x0f24),
MAKE_REG(SVLAN_SP2C_ENTRY18_CTRL1, 0x0f25),
MAKE_REG(SVLAN_SP2C_ENTRY19_CTRL0, 0x0f26),
MAKE_REG(SVLAN_SP2C_ENTRY19_CTRL1, 0x0f27),
MAKE_REG(SVLAN_SP2C_ENTRY20_CTRL0, 0x0f28),
MAKE_REG(SVLAN_SP2C_ENTRY20_CTRL1, 0x0f29),
MAKE_REG(SVLAN_SP2C_ENTRY21_CTRL0, 0x0f2a),
MAKE_REG(SVLAN_SP2C_ENTRY21_CTRL1, 0x0f2b),
MAKE_REG(SVLAN_SP2C_ENTRY22_CTRL0, 0x0f2c),
MAKE_REG(SVLAN_SP2C_ENTRY22_CTRL1, 0x0f2d),
MAKE_REG(SVLAN_SP2C_ENTRY23_CTRL0, 0x0f2e),
MAKE_REG(SVLAN_SP2C_ENTRY23_CTRL1, 0x0f2f),
MAKE_REG(SVLAN_SP2C_ENTRY24_CTRL0, 0x0f30),
MAKE_REG(SVLAN_SP2C_ENTRY24_CTRL1, 0x0f31),
MAKE_REG(SVLAN_SP2C_ENTRY25_CTRL0, 0x0f32),
MAKE_REG(SVLAN_SP2C_ENTRY25_CTRL1, 0x0f33),
MAKE_REG(SVLAN_SP2C_ENTRY26_CTRL0, 0x0f34),
MAKE_REG(SVLAN_SP2C_ENTRY26_CTRL1, 0x0f35),
MAKE_REG(SVLAN_SP2C_ENTRY27_CTRL0, 0x0f36),
MAKE_REG(SVLAN_SP2C_ENTRY27_CTRL1, 0x0f37),
MAKE_REG(SVLAN_SP2C_ENTRY28_CTRL0, 0x0f38),
MAKE_REG(SVLAN_SP2C_ENTRY28_CTRL1, 0x0f39),
MAKE_REG(SVLAN_SP2C_ENTRY29_CTRL0, 0x0f3a),
MAKE_REG(SVLAN_SP2C_ENTRY29_CTRL1, 0x0f3b),
MAKE_REG(SVLAN_SP2C_ENTRY30_CTRL0, 0x0f3c),
MAKE_REG(SVLAN_SP2C_ENTRY30_CTRL1, 0x0f3d),
MAKE_REG(SVLAN_SP2C_ENTRY31_CTRL0, 0x0f3e),
MAKE_REG(SVLAN_SP2C_ENTRY31_CTRL1, 0x0f3f),
MAKE_REG(SVLAN_SP2C_ENTRY32_CTRL0, 0x0f40),
MAKE_REG(SVLAN_SP2C_ENTRY32_CTRL1, 0x0f41),
MAKE_REG(SVLAN_SP2C_ENTRY33_CTRL0, 0x0f42),
MAKE_REG(SVLAN_SP2C_ENTRY33_CTRL1, 0x0f43),
MAKE_REG(SVLAN_SP2C_ENTRY34_CTRL0, 0x0f44),
MAKE_REG(SVLAN_SP2C_ENTRY34_CTRL1, 0x0f45),
MAKE_REG(SVLAN_SP2C_ENTRY35_CTRL0, 0x0f46),
MAKE_REG(SVLAN_SP2C_ENTRY35_CTRL1, 0x0f47),
MAKE_REG(SVLAN_SP2C_ENTRY36_CTRL0, 0x0f48),
MAKE_REG(SVLAN_SP2C_ENTRY36_CTRL1, 0x0f49),
MAKE_REG(SVLAN_SP2C_ENTRY37_CTRL0, 0x0f4a),
MAKE_REG(SVLAN_SP2C_ENTRY37_CTRL1, 0x0f4b),
MAKE_REG(SVLAN_SP2C_ENTRY38_CTRL0, 0x0f4c),
MAKE_REG(SVLAN_SP2C_ENTRY38_CTRL1, 0x0f4d),
MAKE_REG(SVLAN_SP2C_ENTRY39_CTRL0, 0x0f4e),
MAKE_REG(SVLAN_SP2C_ENTRY39_CTRL1, 0x0f4f),
MAKE_REG(SVLAN_SP2C_ENTRY40_CTRL0, 0x0f50),
MAKE_REG(SVLAN_SP2C_ENTRY40_CTRL1, 0x0f51),
MAKE_REG(SVLAN_SP2C_ENTRY41_CTRL0, 0x0f52),
MAKE_REG(SVLAN_SP2C_ENTRY41_CTRL1, 0x0f53),
MAKE_REG(SVLAN_SP2C_ENTRY42_CTRL0, 0x0f54),
MAKE_REG(SVLAN_SP2C_ENTRY42_CTRL1, 0x0f55),
MAKE_REG(SVLAN_SP2C_ENTRY43_CTRL0, 0x0f56),
MAKE_REG(SVLAN_SP2C_ENTRY43_CTRL1, 0x0f57),
MAKE_REG(SVLAN_SP2C_ENTRY44_CTRL0, 0x0f58),
MAKE_REG(SVLAN_SP2C_ENTRY44_CTRL1, 0x0f59),
MAKE_REG(SVLAN_SP2C_ENTRY45_CTRL0, 0x0f5a),
MAKE_REG(SVLAN_SP2C_ENTRY45_CTRL1, 0x0f5b),
MAKE_REG(SVLAN_SP2C_ENTRY46_CTRL0, 0x0f5c),
MAKE_REG(SVLAN_SP2C_ENTRY46_CTRL1, 0x0f5d),
MAKE_REG(SVLAN_SP2C_ENTRY47_CTRL0, 0x0f5e),
MAKE_REG(SVLAN_SP2C_ENTRY47_CTRL1, 0x0f5f),
MAKE_REG(SVLAN_SP2C_ENTRY48_CTRL0, 0x0f60),
MAKE_REG(SVLAN_SP2C_ENTRY48_CTRL1, 0x0f61),
MAKE_REG(SVLAN_SP2C_ENTRY49_CTRL0, 0x0f62),
MAKE_REG(SVLAN_SP2C_ENTRY49_CTRL1, 0x0f63),
MAKE_REG(SVLAN_SP2C_ENTRY50_CTRL0, 0x0f64),
MAKE_REG(SVLAN_SP2C_ENTRY50_CTRL1, 0x0f65),
MAKE_REG(SVLAN_SP2C_ENTRY51_CTRL0, 0x0f66),
MAKE_REG(SVLAN_SP2C_ENTRY51_CTRL1, 0x0f67),
MAKE_REG(SVLAN_SP2C_ENTRY52_CTRL0, 0x0f68),
MAKE_REG(SVLAN_SP2C_ENTRY52_CTRL1, 0x0f69),
MAKE_REG(SVLAN_SP2C_ENTRY53_CTRL0, 0x0f6a),
MAKE_REG(SVLAN_SP2C_ENTRY53_CTRL1, 0x0f6b),
MAKE_REG(SVLAN_SP2C_ENTRY54_CTRL0, 0x0f6c),
MAKE_REG(SVLAN_SP2C_ENTRY54_CTRL1, 0x0f6d),
MAKE_REG(SVLAN_SP2C_ENTRY55_CTRL0, 0x0f6e),
MAKE_REG(SVLAN_SP2C_ENTRY55_CTRL1, 0x0f6f),
MAKE_REG(SVLAN_SP2C_ENTRY56_CTRL0, 0x0f70),
MAKE_REG(SVLAN_SP2C_ENTRY56_CTRL1, 0x0f71),
MAKE_REG(SVLAN_SP2C_ENTRY57_CTRL0, 0x0f72),
MAKE_REG(SVLAN_SP2C_ENTRY57_CTRL1, 0x0f73),
MAKE_REG(SVLAN_SP2C_ENTRY58_CTRL0, 0x0f74),
MAKE_REG(SVLAN_SP2C_ENTRY58_CTRL1, 0x0f75),
MAKE_REG(SVLAN_SP2C_ENTRY59_CTRL0, 0x0f76),
MAKE_REG(SVLAN_SP2C_ENTRY59_CTRL1, 0x0f77),
MAKE_REG(SVLAN_SP2C_ENTRY60_CTRL0, 0x0f78),
MAKE_REG(SVLAN_SP2C_ENTRY60_CTRL1, 0x0f79),
MAKE_REG(SVLAN_SP2C_ENTRY61_CTRL0, 0x0f7a),
MAKE_REG(SVLAN_SP2C_ENTRY61_CTRL1, 0x0f7b),
MAKE_REG(SVLAN_SP2C_ENTRY62_CTRL0, 0x0f7c),
MAKE_REG(SVLAN_SP2C_ENTRY62_CTRL1, 0x0f7d),
MAKE_REG(SVLAN_SP2C_ENTRY63_CTRL0, 0x0f7e),
MAKE_REG(SVLAN_SP2C_ENTRY63_CTRL1, 0x0f7f),
MAKE_REG(SVLAN_SP2C_ENTRY64_CTRL0, 0x0f80),
MAKE_REG(SVLAN_SP2C_ENTRY64_CTRL1, 0x0f81),
MAKE_REG(SVLAN_SP2C_ENTRY65_CTRL0, 0x0f82),
MAKE_REG(SVLAN_SP2C_ENTRY65_CTRL1, 0x0f83),
MAKE_REG(SVLAN_SP2C_ENTRY66_CTRL0, 0x0f84),
MAKE_REG(SVLAN_SP2C_ENTRY66_CTRL1, 0x0f85),
MAKE_REG(SVLAN_SP2C_ENTRY67_CTRL0, 0x0f86),
MAKE_REG(SVLAN_SP2C_ENTRY67_CTRL1, 0x0f87),
MAKE_REG(SVLAN_SP2C_ENTRY68_CTRL0, 0x0f88),
MAKE_REG(SVLAN_SP2C_ENTRY68_CTRL1, 0x0f89),
MAKE_REG(SVLAN_SP2C_ENTRY69_CTRL0, 0x0f8a),
MAKE_REG(SVLAN_SP2C_ENTRY69_CTRL1, 0x0f8b),
MAKE_REG(SVLAN_SP2C_ENTRY70_CTRL0, 0x0f8c),
MAKE_REG(SVLAN_SP2C_ENTRY70_CTRL1, 0x0f8d),
MAKE_REG(SVLAN_SP2C_ENTRY71_CTRL0, 0x0f8e),
MAKE_REG(SVLAN_SP2C_ENTRY71_CTRL1, 0x0f8f),
MAKE_REG(SVLAN_SP2C_ENTRY72_CTRL0, 0x0f90),
MAKE_REG(SVLAN_SP2C_ENTRY72_CTRL1, 0x0f91),
MAKE_REG(SVLAN_SP2C_ENTRY73_CTRL0, 0x0f92),
MAKE_REG(SVLAN_SP2C_ENTRY73_CTRL1, 0x0f93),
MAKE_REG(SVLAN_SP2C_ENTRY74_CTRL0, 0x0f94),
MAKE_REG(SVLAN_SP2C_ENTRY74_CTRL1, 0x0f95),
MAKE_REG(SVLAN_SP2C_ENTRY75_CTRL0, 0x0f96),
MAKE_REG(SVLAN_SP2C_ENTRY75_CTRL1, 0x0f97),
MAKE_REG(SVLAN_SP2C_ENTRY76_CTRL0, 0x0f98),
MAKE_REG(SVLAN_SP2C_ENTRY76_CTRL1, 0x0f99),
MAKE_REG(SVLAN_SP2C_ENTRY77_CTRL0, 0x0f9a),
MAKE_REG(SVLAN_SP2C_ENTRY77_CTRL1, 0x0f9b),
MAKE_REG(SVLAN_SP2C_ENTRY78_CTRL0, 0x0f9c),
MAKE_REG(SVLAN_SP2C_ENTRY78_CTRL1, 0x0f9d),
MAKE_REG(SVLAN_SP2C_ENTRY79_CTRL0, 0x0f9e),
MAKE_REG(SVLAN_SP2C_ENTRY79_CTRL1, 0x0f9f),
MAKE_REG(SVLAN_SP2C_ENTRY80_CTRL0, 0x0fa0),
MAKE_REG(SVLAN_SP2C_ENTRY80_CTRL1, 0x0fa1),
MAKE_REG(SVLAN_SP2C_ENTRY81_CTRL0, 0x0fa2),
MAKE_REG(SVLAN_SP2C_ENTRY81_CTRL1, 0x0fa3),
MAKE_REG(SVLAN_SP2C_ENTRY82_CTRL0, 0x0fa4),
MAKE_REG(SVLAN_SP2C_ENTRY82_CTRL1, 0x0fa5),
MAKE_REG(SVLAN_SP2C_ENTRY83_CTRL0, 0x0fa6),
MAKE_REG(SVLAN_SP2C_ENTRY83_CTRL1, 0x0fa7),
MAKE_REG(SVLAN_SP2C_ENTRY84_CTRL0, 0x0fa8),
MAKE_REG(SVLAN_SP2C_ENTRY84_CTRL1, 0x0fa9),
MAKE_REG(SVLAN_SP2C_ENTRY85_CTRL0, 0x0faa),
MAKE_REG(SVLAN_SP2C_ENTRY85_CTRL1, 0x0fab),
MAKE_REG(SVLAN_SP2C_ENTRY86_CTRL0, 0x0fac),
MAKE_REG(SVLAN_SP2C_ENTRY86_CTRL1, 0x0fad),
MAKE_REG(SVLAN_SP2C_ENTRY87_CTRL0, 0x0fae),
MAKE_REG(SVLAN_SP2C_ENTRY87_CTRL1, 0x0faf),
MAKE_REG(SVLAN_SP2C_ENTRY88_CTRL0, 0x0fb0),
MAKE_REG(SVLAN_SP2C_ENTRY88_CTRL1, 0x0fb1),
MAKE_REG(SVLAN_SP2C_ENTRY89_CTRL0, 0x0fb2),
MAKE_REG(SVLAN_SP2C_ENTRY89_CTRL1, 0x0fb3),
MAKE_REG(SVLAN_SP2C_ENTRY90_CTRL0, 0x0fb4),
MAKE_REG(SVLAN_SP2C_ENTRY90_CTRL1, 0x0fb5),
MAKE_REG(SVLAN_SP2C_ENTRY91_CTRL0, 0x0fb6),
MAKE_REG(SVLAN_SP2C_ENTRY91_CTRL1, 0x0fb7),
MAKE_REG(SVLAN_SP2C_ENTRY92_CTRL0, 0x0fb8),
MAKE_REG(SVLAN_SP2C_ENTRY92_CTRL1, 0x0fb9),
MAKE_REG(SVLAN_SP2C_ENTRY93_CTRL0, 0x0fba),
MAKE_REG(SVLAN_SP2C_ENTRY93_CTRL1, 0x0fbb),
MAKE_REG(SVLAN_SP2C_ENTRY94_CTRL0, 0x0fbc),
MAKE_REG(SVLAN_SP2C_ENTRY94_CTRL1, 0x0fbd),
MAKE_REG(SVLAN_SP2C_ENTRY95_CTRL0, 0x0fbe),
MAKE_REG(SVLAN_SP2C_ENTRY95_CTRL1, 0x0fbf),
MAKE_REG(SVLAN_SP2C_ENTRY96_CTRL0, 0x0fc0),
MAKE_REG(SVLAN_SP2C_ENTRY96_CTRL1, 0x0fc1),
MAKE_REG(SVLAN_SP2C_ENTRY97_CTRL0, 0x0fc2),
MAKE_REG(SVLAN_SP2C_ENTRY97_CTRL1, 0x0fc3),
MAKE_REG(SVLAN_SP2C_ENTRY98_CTRL0, 0x0fc4),
MAKE_REG(SVLAN_SP2C_ENTRY98_CTRL1, 0x0fc5),
MAKE_REG(SVLAN_SP2C_ENTRY99_CTRL0, 0x0fc6),
MAKE_REG(SVLAN_SP2C_ENTRY99_CTRL1, 0x0fc7),
MAKE_REG(SVLAN_SP2C_ENTRY100_CTRL0, 0x0fc8),
MAKE_REG(SVLAN_SP2C_ENTRY100_CTRL1, 0x0fc9),
MAKE_REG(SVLAN_SP2C_ENTRY101_CTRL0, 0x0fca),
MAKE_REG(SVLAN_SP2C_ENTRY101_CTRL1, 0x0fcb),
MAKE_REG(SVLAN_SP2C_ENTRY102_CTRL0, 0x0fcc),
MAKE_REG(SVLAN_SP2C_ENTRY102_CTRL1, 0x0fcd),
MAKE_REG(SVLAN_SP2C_ENTRY103_CTRL0, 0x0fce),
MAKE_REG(SVLAN_SP2C_ENTRY103_CTRL1, 0x0fcf),
MAKE_REG(SVLAN_SP2C_ENTRY104_CTRL0, 0x0fd0),
MAKE_REG(SVLAN_SP2C_ENTRY104_CTRL1, 0x0fd1),
MAKE_REG(SVLAN_SP2C_ENTRY105_CTRL0, 0x0fd2),
MAKE_REG(SVLAN_SP2C_ENTRY105_CTRL1, 0x0fd3),
MAKE_REG(SVLAN_SP2C_ENTRY106_CTRL0, 0x0fd4),
MAKE_REG(SVLAN_SP2C_ENTRY106_CTRL1, 0x0fd5),
MAKE_REG(SVLAN_SP2C_ENTRY107_CTRL0, 0x0fd6),
MAKE_REG(SVLAN_SP2C_ENTRY107_CTRL1, 0x0fd7),
MAKE_REG(SVLAN_SP2C_ENTRY108_CTRL0, 0x0fd8),
MAKE_REG(SVLAN_SP2C_ENTRY108_CTRL1, 0x0fd9),
MAKE_REG(SVLAN_SP2C_ENTRY109_CTRL0, 0x0fda),
MAKE_REG(SVLAN_SP2C_ENTRY109_CTRL1, 0x0fdb),
MAKE_REG(SVLAN_SP2C_ENTRY110_CTRL0, 0x0fdc),
MAKE_REG(SVLAN_SP2C_ENTRY110_CTRL1, 0x0fdd),
MAKE_REG(SVLAN_SP2C_ENTRY111_CTRL0, 0x0fde),
MAKE_REG(SVLAN_SP2C_ENTRY111_CTRL1, 0x0fdf),
MAKE_REG(SVLAN_SP2C_ENTRY112_CTRL0, 0x0fe0),
MAKE_REG(SVLAN_SP2C_ENTRY112_CTRL1, 0x0fe1),
MAKE_REG(SVLAN_SP2C_ENTRY113_CTRL0, 0x0fe2),
MAKE_REG(SVLAN_SP2C_ENTRY113_CTRL1, 0x0fe3),
MAKE_REG(SVLAN_SP2C_ENTRY114_CTRL0, 0x0fe4),
MAKE_REG(SVLAN_SP2C_ENTRY114_CTRL1, 0x0fe5),
MAKE_REG(SVLAN_SP2C_ENTRY115_CTRL0, 0x0fe6),
MAKE_REG(SVLAN_SP2C_ENTRY115_CTRL1, 0x0fe7),
MAKE_REG(SVLAN_SP2C_ENTRY116_CTRL0, 0x0fe8),
MAKE_REG(SVLAN_SP2C_ENTRY116_CTRL1, 0x0fe9),
MAKE_REG(SVLAN_SP2C_ENTRY117_CTRL0, 0x0fea),
MAKE_REG(SVLAN_SP2C_ENTRY117_CTRL1, 0x0feb),
MAKE_REG(SVLAN_SP2C_ENTRY118_CTRL0, 0x0fec),
MAKE_REG(SVLAN_SP2C_ENTRY118_CTRL1, 0x0fed),
MAKE_REG(SVLAN_SP2C_ENTRY119_CTRL0, 0x0fee),
MAKE_REG(SVLAN_SP2C_ENTRY119_CTRL1, 0x0fef),
MAKE_REG(SVLAN_SP2C_ENTRY120_CTRL0, 0x0ff0),
MAKE_REG(SVLAN_SP2C_ENTRY120_CTRL1, 0x0ff1),
MAKE_REG(SVLAN_SP2C_ENTRY121_CTRL0, 0x0ff2),
MAKE_REG(SVLAN_SP2C_ENTRY121_CTRL1, 0x0ff3),
MAKE_REG(SVLAN_SP2C_ENTRY122_CTRL0, 0x0ff4),
MAKE_REG(SVLAN_SP2C_ENTRY122_CTRL1, 0x0ff5),
MAKE_REG(SVLAN_SP2C_ENTRY123_CTRL0, 0x0ff6),
MAKE_REG(SVLAN_SP2C_ENTRY123_CTRL1, 0x0ff7),
MAKE_REG(SVLAN_SP2C_ENTRY124_CTRL0, 0x0ff8),
MAKE_REG(SVLAN_SP2C_ENTRY124_CTRL1, 0x0ff9),
MAKE_REG(SVLAN_SP2C_ENTRY125_CTRL0, 0x0ffa),
MAKE_REG(SVLAN_SP2C_ENTRY125_CTRL1, 0x0ffb),
MAKE_REG(SVLAN_SP2C_ENTRY126_CTRL0, 0x0ffc),
MAKE_REG(SVLAN_SP2C_ENTRY126_CTRL1, 0x0ffd),
MAKE_REG(SVLAN_SP2C_ENTRY127_CTRL0, 0x0ffe),
MAKE_REG(SVLAN_SP2C_ENTRY127_CTRL1, 0x0fff),
MAKE_REG(MIB_COUNTER0, 0x1000),
MAKE_REG(MIB_COUNTER1, 0x1001),
MAKE_REG(MIB_COUNTER2, 0x1002),
MAKE_REG(MIB_COUNTER3, 0x1003),
MAKE_REG(MIB_ADDRESS, 0x1004),
MAKE_REG(MIB_CTRL0, 0x1005),
MAKE_REG(MIB_CTRL1, 0x1007),
MAKE_REG(MIB_CTRL2, 0x1008),
MAKE_REG(MIB_CTRL3, 0x1009),
MAKE_REG(MIB_CTRL4, 0x100a),
MAKE_REG(MIB_CTRL5, 0x100b),
MAKE_REG(INTR_CTRL, 0x1100),
MAKE_REG(INTR_IMR, 0x1101),
MAKE_REG(INTR_IMS, 0x1102),
MAKE_REG(LEARN_OVER_INDICATOR, 0x1103),
MAKE_REG(SPEED_CHANGE_INDICATOR, 0x1104),
MAKE_REG(SPECIAL_CONGEST_INDICATOR, 0x1105),
MAKE_REG(PORT_LINKDOWN_INDICATOR, 0x1106),
MAKE_REG(PORT_LINKUP_INDICATOR, 0x1107),
MAKE_REG(SYSTEM_LEARN_OVER_INDICATOR, 0x1108),
MAKE_REG(INTR_IMR_8051, 0x1118),
MAKE_REG(INTR_IMS_8051, 0x1119),
MAKE_REG(DW8051_INT_CPU, 0x111a),
MAKE_REG(LEARN_OVER_INDICATOR_8051, 0x1120),
MAKE_REG(SPEED_CHANGE_INDICATOR_8051, 0x1121),
MAKE_REG(SPECIAL_CONGEST_INDICATOR_8051, 0x1122),
MAKE_REG(PORT_LINKDOWN_INDICATOR_8051, 0x1123),
MAKE_REG(PORT_LINKUP_INDICATOR_8051, 0x1124),
MAKE_REG(DUMMY_1125, 0x1125),
MAKE_REG(DUMMY_1126, 0x1126),
MAKE_REG(DUMMY_1127, 0x1127),
MAKE_REG(DUMMY_1128, 0x1128),
MAKE_REG(DUMMY_1129, 0x1129),
MAKE_REG(INTR_IMS_BUFFER_RESET, 0x112a),
MAKE_REG(INTR_IMS_8051_BUFFER_RESET, 0x112b),
MAKE_REG(GPHY_INTRPT_8051, 0x112c),
MAKE_REG(GPHY_INTRPT, 0x112d),
MAKE_REG(THERMAL_INTRPT, 0x112e),
MAKE_REG(THERMAL_INTRPT_8051, 0x112f),
MAKE_REG(SDS_LINK_CHG_INT, 0x1130),
MAKE_REG(SDS_LINK_CHG_INT_8051, 0x1131),
MAKE_REG(MAX_LENGTH_LIMINT_IPG, 0x1200),
MAKE_REG(IOL_RXDROP_CFG, 0x1201),
MAKE_REG(VS_TPID, 0x1202),
MAKE_REG(INBW_BOUND, 0x1203),
MAKE_REG(CFG_TX_ITFSP_OP, 0x1204),
MAKE_REG(INBW_BOUND2, 0x1205),
MAKE_REG(CFG_48PASS1_DROP, 0x1206),
MAKE_REG(CFG_BACKPRESSURE, 0x1207),
MAKE_REG(CFG_UNHIOL, 0x1208),
MAKE_REG(SWITCH_MAC0, 0x1209),
MAKE_REG(SWITCH_MAC1, 0x120a),
MAKE_REG(SWITCH_MAC2, 0x120b),
MAKE_REG(SWITCH_CTRL0, 0x120c),
MAKE_REG(QOS_DSCP_REMARK_CTRL0, 0x120d),
MAKE_REG(QOS_DSCP_REMARK_CTRL1, 0x120e),
MAKE_REG(QOS_DSCP_REMARK_CTRL2, 0x120f),
MAKE_REG(QOS_DSCP_REMARK_CTRL3, 0x1210),
MAKE_REG(QOS_1Q_REMARK_CTRL0, 0x1211),
MAKE_REG(QOS_1Q_REMARK_CTRL1, 0x1212),
MAKE_REG(SW_DUMMY0, 0x1214),
MAKE_REG(SW_DUMMY1, 0x1215),
MAKE_REG(SVLAN_UPLINK_PORTMASK, 0x1218),
MAKE_REG(CPU_PORT_MASK, 0x1219),
MAKE_REG(CPU_CTRL, 0x121a),
MAKE_REG(MIRROR_CTRL, 0x121c),
MAKE_REG(FLOWCTRL_CTRL0, 0x121d),
MAKE_REG(FLOWCTRL_ALL_ON, 0x121e),
MAKE_REG(FLOWCTRL_SYS_ON, 0x121f),
MAKE_REG(FLOWCTRL_SYS_OFF, 0x1220),
MAKE_REG(FLOWCTRL_SHARE_ON, 0x1221),
MAKE_REG(FLOWCTRL_SHARE_OFF, 0x1222),
MAKE_REG(FLOWCTRL_FCOFF_SYS_ON, 0x1223),
MAKE_REG(FLOWCTRL_FCOFF_SYS_OFF, 0x1224),
MAKE_REG(FLOWCTRL_FCOFF_SHARE_ON, 0x1225),
MAKE_REG(FLOWCTRL_FCOFF_SHARE_OFF, 0x1226),
MAKE_REG(FLOWCTRL_PORT_ON, 0x1227),
MAKE_REG(FLOWCTRL_PORT_OFF, 0x1228),
MAKE_REG(FLOWCTRL_PORT_PRIVATE_ON, 0x1229),
MAKE_REG(FLOWCTRL_PORT_PRIVATE_OFF, 0x122a),
MAKE_REG(RRCP_CTRL0, 0x122b),
MAKE_REG(RRCP_CTRL1, 0x122c),
MAKE_REG(RRCP_CTRL2, 0x122d),
MAKE_REG(RRCP_CTRL3, 0x122e),
MAKE_REG(FLOWCTRL_FCOFF_PORT_ON, 0x122f),
MAKE_REG(FLOWCTRL_FCOFF_PORT_OFF, 0x1230),
MAKE_REG(FLOWCTRL_FCOFF_PORT_PRIVATE_ON, 0x1231),
MAKE_REG(FLOWCTRL_FCOFF_PORT_PRIVATE_OFF, 0x1232),
MAKE_REG(FLOWCTRL_JUMBO_SYS_ON, 0x1233),
MAKE_REG(FLOWCTRL_JUMBO_SYS_OFF, 0x1234),
MAKE_REG(FLOWCTRL_JUMBO_SHARE_ON, 0x1235),
MAKE_REG(FLOWCTRL_JUMBO_SHARE_OFF, 0x1236),
MAKE_REG(FLOWCTRL_JUMBO_PORT_ON, 0x1237),
MAKE_REG(FLOWCTRL_JUMBO_PORT_OFF, 0x1238),
MAKE_REG(FLOWCTRL_JUMBO_PORT_PRIVATE_ON, 0x1239),
MAKE_REG(FLOWCTRL_JUMBO_PORT_PRIVATE_OFF, 0x123a),
MAKE_REG(FLOWCTRL_JUMBO_SIZE, 0x123b),
MAKE_REG(FLOWCTRL_TOTAL_PAGE_COUNTER, 0x124c),
MAKE_REG(FLOWCTRL_PUBLIC_PAGE_COUNTER, 0x124d),
MAKE_REG(FLOWCTRL_TOTAL_PAGE_MAX, 0x124e),
MAKE_REG(FLOWCTRL_PUBLIC_PAGE_MAX, 0x124f),
MAKE_REG(FLOWCTRL_PORT0_PAGE_COUNTER, 0x1250),
MAKE_REG(FLOWCTRL_PORT1_PAGE_COUNTER, 0x1251),
MAKE_REG(FLOWCTRL_PORT2_PAGE_COUNTER, 0x1252),
MAKE_REG(FLOWCTRL_PORT3_PAGE_COUNTER, 0x1253),
MAKE_REG(FLOWCTRL_PORT4_PAGE_COUNTER, 0x1254),
MAKE_REG(FLOWCTRL_PORT5_PAGE_COUNTER, 0x1255),
MAKE_REG(FLOWCTRL_PORT6_PAGE_COUNTER, 0x1256),
MAKE_REG(FLOWCTRL_PORT7_PAGE_COUNTER, 0x1257),
MAKE_REG(FLOWCTRL_PUBLIC_FCOFF_PAGE_COUNTER, 0x1258),
MAKE_REG(FLOWCTRL_PUBLIC_JUMBO_PAGE_COUNTER, 0x1259),
MAKE_REG(FLOWCTRL_MAX_PUBLIC_FCOFF_PAGE_COUNTER, 0x125a),
MAKE_REG(FLOWCTRL_MAX_PUBLIC_JUMBO_PAGE_COUNTER, 0x125b),
MAKE_REG(FLOWCTRL_PORT0_PAGE_MAX, 0x1260),
MAKE_REG(FLOWCTRL_PORT1_PAGE_MAX, 0x1261),
MAKE_REG(FLOWCTRL_PORT2_PAGE_MAX, 0x1262),
MAKE_REG(FLOWCTRL_PORT3_PAGE_MAX, 0x1263),
MAKE_REG(FLOWCTRL_PORT4_PAGE_MAX, 0x1264),
MAKE_REG(FLOWCTRL_PORT5_PAGE_MAX, 0x1265),
MAKE_REG(FLOWCTRL_PORT6_PAGE_MAX, 0x1266),
MAKE_REG(FLOWCTRL_PORT7_PAGE_MAX, 0x1267),
MAKE_REG(FLOWCTRL_PAGE_COUNT_CLEAR, 0x1268),
MAKE_REG(FLOWCTRL_PORT8_PAGE_MAX, 0x1269),
MAKE_REG(FLOWCTRL_PORT9_PAGE_MAX, 0x126a),
MAKE_REG(FLOWCTRL_PORT10_PAGE_MAX, 0x126b),
MAKE_REG(FLOWCTRL_PORT8_PAGE_COUNTER, 0x126c),
MAKE_REG(FLOWCTRL_PORT9_PAGE_COUNTER, 0x126d),
MAKE_REG(FLOWCTRL_PORT10_PAGE_COUNTER, 0x126e),
MAKE_REG(RRCP_CTRL1_H, 0x126f),
MAKE_REG(EMA_CTRL0, 0x1270),
MAKE_REG(EMA_CTRL1, 0x1271),
MAKE_REG(EMA_CTRL2, 0x1272),
MAKE_REG(EMA_CTRL3, 0x1273),
MAKE_REG(EMA_CTRL4, 0x1274),
MAKE_REG(DIAG_MODE, 0x1275),
MAKE_REG(BIST_MODE, 0x1276),
MAKE_REG(STS_BIST_DONE, 0x1277),
MAKE_REG(STS_BIST_RLT0, 0x1278),
MAKE_REG(STS_BIST_RLT1, 0x1279),
MAKE_REG(STS_BIST_RLT2, 0x127a),
MAKE_REG(STS_BIST_RLT3, 0x127b),
MAKE_REG(STS_BIST_RLT4, 0x127c),
MAKE_REG(VIAROM_MISR, 0x127d),
MAKE_REG(DRF_BIST_MODE, 0x1280),
MAKE_REG(STS_DRF_BIST, 0x1281),
MAKE_REG(STS_DRF_BIST_RLT0, 0x1282),
MAKE_REG(STS_DRF_BIST_RLT1, 0x1283),
MAKE_REG(STS_DRF_BIST_RLT2, 0x1284),
MAKE_REG(STS_DRF_BIST_RLT3, 0x1285),
MAKE_REG(STS_DRF_BIST_RLT4, 0x1286),
MAKE_REG(RAM_DRF_CTRL, 0x1289),
MAKE_REG(MIB_RMON_LEN_CTRL, 0x128a),
MAKE_REG(COND0_BISR_OUT0, 0x1290),
MAKE_REG(COND0_BISR_OUT1, 0x1291),
MAKE_REG(COND0_BISR_OUT2, 0x1292),
MAKE_REG(COND0_BISR_OUT3, 0x1293),
MAKE_REG(COND0_BISR_OUT4, 0x1294),
MAKE_REG(COND0_BISR_OUT5, 0x1295),
MAKE_REG(CHG_DUPLEX_CFG, 0x1296),
MAKE_REG(COND0_BIST_PASS, 0x1297),
MAKE_REG(COND1_BISR_OUT0, 0x1298),
MAKE_REG(COND1_BISR_OUT1, 0x1299),
MAKE_REG(COND1_BISR_OUT2, 0x129a),
MAKE_REG(COND1_BISR_OUT3, 0x129b),
MAKE_REG(COND1_BISR_OUT4, 0x129c),
MAKE_REG(COND1_BISR_OUT5, 0x129d),
MAKE_REG(COND1_BIST_PASS, 0x129f),
MAKE_REG(EEE_TX_THR_Giga_500M, 0x12a0),
MAKE_REG(EEE_TX_THR_FE, 0x12a1),
MAKE_REG(EEE_MISC, 0x12a3),
MAKE_REG(EEE_GIGA_CTRL0, 0x12a4),
MAKE_REG(EEE_GIGA_CTRL1, 0x12a5),
MAKE_REG(EEE_100M_CTRL0, 0x12a6),
MAKE_REG(EEE_100M_CTRL1, 0x12a7),
MAKE_REG(RX_FC_REG, 0x12aa),
MAKE_REG(MAX_FIFO_SIZE, 0x12af),
MAKE_REG(EEEP_RX_RATE_GIGA, 0x12b0),
MAKE_REG(EEEP_RX_RATE_100M, 0x12b1),
MAKE_REG(DUMMY_REG_12_2, 0x12b2),
MAKE_REG(EEEP_TX_RATE_GIGA, 0x12b3),
MAKE_REG(EEEP_TX_RATE_100M, 0x12b4),
MAKE_REG(DUMMY_REG_12_3, 0x12b5),
MAKE_REG(EEEP_GIGA_CTRL0, 0x12b6),
MAKE_REG(EEEP_GIGA_CTRL1, 0x12b7),
MAKE_REG(EEEP_GIGA_CTRL2, 0x12b8),
MAKE_REG(EEEP_100M_CTRL0, 0x12b9),
MAKE_REG(EEEP_100M_CTRL1, 0x12ba),
MAKE_REG(EEEP_100M_CTRL2, 0x12bb),
MAKE_REG(EEEP_CTRL0, 0x12bc),
MAKE_REG(EEEP_CTRL1, 0x12bd),
MAKE_REG(BACK_PRESSURE_IPG, 0x12be),
MAKE_REG(TX_ESD_LEVEL, 0x12bf),
MAKE_REG(RRCP_CTRL4, 0x12e0),
MAKE_REG(RRCP_CTRL5, 0x12e1),
MAKE_REG(RRCP_CTRL6, 0x12e2),
MAKE_REG(RRCP_CTRL7, 0x12e3),
MAKE_REG(RRCP_CTRL8, 0x12e4),
MAKE_REG(RRCP_CTRL9, 0x12e5),
MAKE_REG(RRCP_CTRL10, 0x12e6),
MAKE_REG(FIELD_SELECTOR0, 0x12e7),
MAKE_REG(FIELD_SELECTOR1, 0x12e8),
MAKE_REG(FIELD_SELECTOR2, 0x12e9),
MAKE_REG(FIELD_SELECTOR3, 0x12ea),
MAKE_REG(FIELD_SELECTOR4, 0x12eb),
MAKE_REG(FIELD_SELECTOR5, 0x12ec),
MAKE_REG(FIELD_SELECTOR6, 0x12ed),
MAKE_REG(FIELD_SELECTOR7, 0x12ee),
MAKE_REG(FIELD_SELECTOR8, 0x12ef),
MAKE_REG(FIELD_SELECTOR9, 0x12f0),
MAKE_REG(FIELD_SELECTOR10, 0x12f1),
MAKE_REG(FIELD_SELECTOR11, 0x12f2),
MAKE_REG(FIELD_SELECTOR12, 0x12f3),
MAKE_REG(FIELD_SELECTOR13, 0x12f4),
MAKE_REG(FIELD_SELECTOR14, 0x12f5),
MAKE_REG(FIELD_SELECTOR15, 0x12f6),
MAKE_REG(HWPKT_GEN_MISC_H, 0x12f7),
MAKE_REG(MIRROR_SRC_PMSK, 0x12fb),
MAKE_REG(EEE_BURSTSIZE, 0x12fc),
MAKE_REG(EEE_IFG_CFG, 0x12fd),
MAKE_REG(FPGA_VER_MAC, 0x12fe),
MAKE_REG(HWPKT_GEN_MISC, 0x12ff),
MAKE_REG(CHIP_NUMBER, 0x1300),
MAKE_REG(CHIP_VER, 0x1301),
MAKE_REG(CHIP_DEBUG0, 0x1303),
MAKE_REG(CHIP_DEBUG1, 0x1304),
MAKE_REG(DIGITAL_INTERFACE_SELECT, 0x1305),
MAKE_REG(EXT0_RGMXF, 0x1306),
MAKE_REG(EXT1_RGMXF, 0x1307),
MAKE_REG(BISR_CTRL, 0x1308),
MAKE_REG(SLF_IF, 0x1309),
MAKE_REG(I2C_CLOCK_DIV, 0x130a),
MAKE_REG(MDX_MDC_DIV, 0x130b),
MAKE_REG(MISCELLANEOUS_CONFIGURE0, 0x130c),
MAKE_REG(MISCELLANEOUS_CONFIGURE1, 0x130d),
MAKE_REG(PHY_AD, 0x130f),
MAKE_REG(DIGITAL_INTERFACE0_FORCE, 0x1310),
MAKE_REG(DIGITAL_INTERFACE1_FORCE, 0x1311),
MAKE_REG(MAC0_FORCE_SELECT, 0x1312),
MAKE_REG(MAC1_FORCE_SELECT, 0x1313),
MAKE_REG(MAC2_FORCE_SELECT, 0x1314),
MAKE_REG(MAC3_FORCE_SELECT, 0x1315),
MAKE_REG(MAC4_FORCE_SELECT, 0x1316),
MAKE_REG(MAC5_FORCE_SELECT, 0x1317),
MAKE_REG(MAC6_FORCE_SELECT, 0x1318),
MAKE_REG(MAC7_FORCE_SELECT, 0x1319),
MAKE_REG(M10_FORCE_SELECT, 0x131c),
MAKE_REG(CHIP_RESET, 0x1322),
MAKE_REG(DIGITAL_DEBUG_0, 0x1323),
MAKE_REG(DIGITAL_DEBUG_1, 0x1324),
MAKE_REG(INTERNAL_PHY_MDC_DRIVER, 0x1325),
MAKE_REG(LINKDOWN_TIME_CTRL, 0x1326),
MAKE_REG(PHYACK_TIMEOUT, 0x1331),
MAKE_REG(MDXACK_TIMEOUT, 0x1333),
MAKE_REG(DW8051_RDY, 0x1336),
MAKE_REG(BIST_CTRL, 0x133c),
MAKE_REG(DIAG_MODE2, 0x133d),
MAKE_REG(MDX_PHY_REG0, 0x133e),
MAKE_REG(MDX_PHY_REG1, 0x133f),
MAKE_REG(DEBUG_SIGNAL_SELECT_SW, 0x1340),
MAKE_REG(DEBUG_SIGNAL_SELECT_B, 0x1341),
MAKE_REG(DEBUG_SIGNAL_I, 0x1343),
MAKE_REG(DEBUG_SIGNAL_H, 0x1344),
MAKE_REG(DBGO_SEL_GPHY, 0x1345),
MAKE_REG(DBGO_SEL_MISC, 0x1346),
MAKE_REG(BYPASS_ABLTY_LOCK, 0x1349),
MAKE_REG(BYPASS_ABLTY_LOCK_EXT, 0x134a),
MAKE_REG(ACL_GPIO, 0x134f),
MAKE_REG(EN_GPIO, 0x1350),
MAKE_REG(CFG_MULTI_PIN, 0x1351),
MAKE_REG(PORT0_STATUS, 0x1352),
MAKE_REG(PORT1_STATUS, 0x1353),
MAKE_REG(PORT2_STATUS, 0x1354),
MAKE_REG(PORT3_STATUS, 0x1355),
MAKE_REG(PORT4_STATUS, 0x1356),
MAKE_REG(PORT5_STATUS, 0x1357),
MAKE_REG(PORT6_STATUS, 0x1358),
MAKE_REG(PORT7_STATUS, 0x1359),
MAKE_REG(PORT8_STATUS, 0x135a),
MAKE_REG(PORT9_STATUS, 0x135b),
MAKE_REG(PORT10_STATUS, 0x135c),
MAKE_REG(UPS_CTRL0, 0x1362),
MAKE_REG(UPS_CTRL1, 0x1363),
MAKE_REG(UPS_CTRL2, 0x1364),
MAKE_REG(GATING_CLK_1, 0x1365),
MAKE_REG(UPS_CTRL4, 0x1366),
MAKE_REG(UPS_CTRL5, 0x1367),
MAKE_REG(UPS_CTRL6, 0x1368),
MAKE_REG(I2C_CTRL, 0x1374),
MAKE_REG(EEE_CFG, 0x1375),
MAKE_REG(EEE_PAGE, 0x1376),
MAKE_REG(EEE_EXT_PAGE, 0x1377),
MAKE_REG(EEE_EN_SPD1000, 0x1378),
MAKE_REG(EEE_EN_SPD100, 0x1379),
MAKE_REG(EEE_LP_SPD1000, 0x137a),
MAKE_REG(EEE_LP_SPD100, 0x137b),
MAKE_REG(DW8051_PRO_REG0, 0x13a0),
MAKE_REG(DW8051_PRO_REG1, 0x13a1),
MAKE_REG(DW8051_PRO_REG2, 0x13a2),
MAKE_REG(DW8051_PRO_REG3, 0x13a3),
MAKE_REG(DW8051_PRO_REG4, 0x13a4),
MAKE_REG(DW8051_PRO_REG5, 0x13a5),
MAKE_REG(DW8051_PRO_REG6, 0x13a6),
MAKE_REG(DW8051_PRO_REG7, 0x13a7),
MAKE_REG(PROTECT_ID, 0x13c0),
MAKE_REG(CHIP_VER_INTL, 0x13c1),
MAKE_REG(MAGIC_ID, 0x13c2),
MAKE_REG(DIGITAL_INTERFACE_SELECT_1, 0x13c3),
MAKE_REG(DIGITAL_INTERFACE2_FORCE, 0x13c4),
MAKE_REG(EXT2_RGMXF, 0x13c5),
MAKE_REG(ROUTER_UPS_CFG, 0x13c6),
MAKE_REG(CTRL_GPIO, 0x13c7),
MAKE_REG(SEL_GPIO, 0x13c8),
MAKE_REG(STATUS_GPIO, 0x13c9),
MAKE_REG(SYNC_ETH_CFG, 0x13e0),
MAKE_REG(LED_DRI_CFG, 0x13e1),
MAKE_REG(CHIP_DEBUG2, 0x13e2),
MAKE_REG(DIGITAL_DEBUG_2, 0x13e3),
MAKE_REG(FIBER_RTL_OUI_CFG0, 0x13e4),
MAKE_REG(FIBER_RTL_OUI_CFG1, 0x13e5),
MAKE_REG(FIBER_CFG_0, 0x13e6),
MAKE_REG(FIBER_CFG_1, 0x13e7),
MAKE_REG(FIBER_CFG_2, 0x13e8),
MAKE_REG(FIBER_CFG_3, 0x13e9),
MAKE_REG(FIBER_CFG_4, 0x13ea),
MAKE_REG(UTP_FIB_DET, 0x13eb),
MAKE_REG(NRESTORE_MAGIC_NUM, 0x13ec),
MAKE_REG(MAC_ACTIVE, 0x13ee),
MAKE_REG(SERDES_RESULT, 0x13ef),
MAKE_REG(CHIP_ECO, 0x13f0),
MAKE_REG(WAKELPI_SLOT_PRD, 0x13f1),
MAKE_REG(WAKELPI_SLOT_PG0, 0x13f2),
MAKE_REG(WAKELPI_SLOT_PG1, 0x13f3),
MAKE_REG(WAKELPI_SLOT_PG2, 0x13f4),
MAKE_REG(WAKELPI_SLOT_PG3, 0x13f5),
MAKE_REG(SYNC_FIFO_0, 0x13f6),
MAKE_REG(SYNC_FIFO_1, 0x13f7),
MAKE_REG(RGM_EEE, 0x13f8),
MAKE_REG(EXT_TXC_DLY, 0x13f9),
MAKE_REG(IO_MISC_CTRL, 0x13fa),
MAKE_REG(CHIP_DUMMY_NO, 0x13fb),
MAKE_REG(RC_CALIB_CFG, 0x13fc),
MAKE_REG(WAKELPI_SLOT_PG4, 0x13fd),
MAKE_REG(WAKELPI_SLOT_PG5, 0x13fe),
MAKE_REG(METER0_RATE_CTRL0, 0x1400),
MAKE_REG(METER0_RATE_CTRL1, 0x1401),
MAKE_REG(METER1_RATE_CTRL0, 0x1402),
MAKE_REG(METER1_RATE_CTRL1, 0x1403),
MAKE_REG(METER2_RATE_CTRL0, 0x1404),
MAKE_REG(METER2_RATE_CTRL1, 0x1405),
MAKE_REG(METER3_RATE_CTRL0, 0x1406),
MAKE_REG(METER3_RATE_CTRL1, 0x1407),
MAKE_REG(METER4_RATE_CTRL0, 0x1408),
MAKE_REG(METER4_RATE_CTRL1, 0x1409),
MAKE_REG(METER5_RATE_CTRL0, 0x140a),
MAKE_REG(METER5_RATE_CTRL1, 0x140b),
MAKE_REG(METER6_RATE_CTRL0, 0x140c),
MAKE_REG(METER6_RATE_CTRL1, 0x140d),
MAKE_REG(METER7_RATE_CTRL0, 0x140e),
MAKE_REG(METER7_RATE_CTRL1, 0x140f),
MAKE_REG(METER8_RATE_CTRL0, 0x1410),
MAKE_REG(METER8_RATE_CTRL1, 0x1411),
MAKE_REG(METER9_RATE_CTRL0, 0x1412),
MAKE_REG(METER9_RATE_CTRL1, 0x1413),
MAKE_REG(METER10_RATE_CTRL0, 0x1414),
MAKE_REG(METER10_RATE_CTRL1, 0x1415),
MAKE_REG(METER11_RATE_CTRL0, 0x1416),
MAKE_REG(METER11_RATE_CTRL1, 0x1417),
MAKE_REG(METER12_RATE_CTRL0, 0x1418),
MAKE_REG(METER12_RATE_CTRL1, 0x1419),
MAKE_REG(METER13_RATE_CTRL0, 0x141a),
MAKE_REG(METER13_RATE_CTRL1, 0x141b),
MAKE_REG(METER14_RATE_CTRL0, 0x141c),
MAKE_REG(METER14_RATE_CTRL1, 0x141d),
MAKE_REG(METER15_RATE_CTRL0, 0x141e),
MAKE_REG(METER15_RATE_CTRL1, 0x141f),
MAKE_REG(METER16_RATE_CTRL0, 0x1420),
MAKE_REG(METER16_RATE_CTRL1, 0x1421),
MAKE_REG(METER17_RATE_CTRL0, 0x1422),
MAKE_REG(METER17_RATE_CTRL1, 0x1423),
MAKE_REG(METER18_RATE_CTRL0, 0x1424),
MAKE_REG(METER18_RATE_CTRL1, 0x1425),
MAKE_REG(METER19_RATE_CTRL0, 0x1426),
MAKE_REG(METER19_RATE_CTRL1, 0x1427),
MAKE_REG(METER20_RATE_CTRL0, 0x1428),
MAKE_REG(METER20_RATE_CTRL1, 0x1429),
MAKE_REG(METER21_RATE_CTRL0, 0x142a),
MAKE_REG(METER21_RATE_CTRL1, 0x142b),
MAKE_REG(METER22_RATE_CTRL0, 0x142c),
MAKE_REG(METER22_RATE_CTRL1, 0x142d),
MAKE_REG(METER23_RATE_CTRL0, 0x142e),
MAKE_REG(METER23_RATE_CTRL1, 0x142f),
MAKE_REG(METER24_RATE_CTRL0, 0x1430),
MAKE_REG(METER24_RATE_CTRL1, 0x1431),
MAKE_REG(METER25_RATE_CTRL0, 0x1432),
MAKE_REG(METER25_RATE_CTRL1, 0x1433),
MAKE_REG(METER26_RATE_CTRL0, 0x1434),
MAKE_REG(METER26_RATE_CTRL1, 0x1435),
MAKE_REG(METER27_RATE_CTRL0, 0x1436),
MAKE_REG(METER27_RATE_CTRL1, 0x1437),
MAKE_REG(METER28_RATE_CTRL0, 0x1438),
MAKE_REG(METER28_RATE_CTRL1, 0x1439),
MAKE_REG(METER29_RATE_CTRL0, 0x143a),
MAKE_REG(METER29_RATE_CTRL1, 0x143b),
MAKE_REG(METER30_RATE_CTRL0, 0x143c),
MAKE_REG(METER30_RATE_CTRL1, 0x143d),
MAKE_REG(METER31_RATE_CTRL0, 0x143e),
MAKE_REG(METER31_RATE_CTRL1, 0x143f),
MAKE_REG(METER_MODE_SETTING0, 0x1440),
MAKE_REG(METER_MODE_SETTING1, 0x1441),
MAKE_REG(METER_MODE_TOKEN_CFG, 0x1442),
MAKE_REG(METER0_BUCKET_SIZE, 0x1600),
MAKE_REG(METER1_BUCKET_SIZE, 0x1601),
MAKE_REG(METER2_BUCKET_SIZE, 0x1602),
MAKE_REG(METER3_BUCKET_SIZE, 0x1603),
MAKE_REG(METER4_BUCKET_SIZE, 0x1604),
MAKE_REG(METER5_BUCKET_SIZE, 0x1605),
MAKE_REG(METER6_BUCKET_SIZE, 0x1606),
MAKE_REG(METER7_BUCKET_SIZE, 0x1607),
MAKE_REG(METER8_BUCKET_SIZE, 0x1608),
MAKE_REG(METER9_BUCKET_SIZE, 0x1609),
MAKE_REG(METER10_BUCKET_SIZE, 0x160a),
MAKE_REG(METER11_BUCKET_SIZE, 0x160b),
MAKE_REG(METER12_BUCKET_SIZE, 0x160c),
MAKE_REG(METER13_BUCKET_SIZE, 0x160d),
MAKE_REG(METER14_BUCKET_SIZE, 0x160e),
MAKE_REG(METER15_BUCKET_SIZE, 0x160f),
MAKE_REG(METER16_BUCKET_SIZE, 0x1610),
MAKE_REG(METER17_BUCKET_SIZE, 0x1611),
MAKE_REG(METER18_BUCKET_SIZE, 0x1612),
MAKE_REG(METER19_BUCKET_SIZE, 0x1613),
MAKE_REG(METER20_BUCKET_SIZE, 0x1614),
MAKE_REG(METER21_BUCKET_SIZE, 0x1615),
MAKE_REG(METER22_BUCKET_SIZE, 0x1616),
MAKE_REG(METER23_BUCKET_SIZE, 0x1617),
MAKE_REG(METER24_BUCKET_SIZE, 0x1618),
MAKE_REG(METER25_BUCKET_SIZE, 0x1619),
MAKE_REG(METER26_BUCKET_SIZE, 0x161a),
MAKE_REG(METER27_BUCKET_SIZE, 0x161b),
MAKE_REG(METER28_BUCKET_SIZE, 0x161c),
MAKE_REG(METER29_BUCKET_SIZE, 0x161d),
MAKE_REG(METER30_BUCKET_SIZE, 0x161e),
MAKE_REG(METER31_BUCKET_SIZE, 0x161f),
MAKE_REG(METER_CTRL0, 0x1700),
MAKE_REG(METER_CTRL1, 0x1701),
MAKE_REG(METER_OVERRATE_INDICATOR0, 0x1702),
MAKE_REG(METER_OVERRATE_INDICATOR1, 0x1703),
MAKE_REG(METER_OVERRATE_INDICATOR0_8051, 0x1704),
MAKE_REG(METER_OVERRATE_INDICATOR1_8051, 0x1705),
MAKE_REG(METER_IFG_CTRL0, 0x1712),
MAKE_REG(METER_IFG_CTRL1, 0x1713),
MAKE_REG(METER_CTRL2, 0x1722),
MAKE_REG(DUMMY_1723, 0x1723),
MAKE_REG(DUMMY_1724, 0x1724),
MAKE_REG(DUMMY_1725, 0x1725),
MAKE_REG(DUMMY_1726, 0x1726),
MAKE_REG(DUMMY_1727, 0x1727),
MAKE_REG(DUMMY_1728, 0x1728),
MAKE_REG(DUMMY_1729, 0x1729),
MAKE_REG(DUMMY_172A, 0x172a),
MAKE_REG(DUMMY_172B, 0x172b),
MAKE_REG(DUMMY_172C, 0x172c),
MAKE_REG(DUMMY_172D, 0x172d),
MAKE_REG(DUMMY_172E, 0x172e),
MAKE_REG(DUMMY_172F, 0x172f),
MAKE_REG(DUMMY_1730, 0x1730),
MAKE_REG(DUMMY_1731, 0x1731),
MAKE_REG(METER32_RATE_CTRL0, 0x1740),
MAKE_REG(METER32_RATE_CTRL1, 0x1741),
MAKE_REG(METER33_RATE_CTRL0, 0x1742),
MAKE_REG(METER33_RATE_CTRL1, 0x1743),
MAKE_REG(METER34_RATE_CTRL0, 0x1744),
MAKE_REG(METER34_RATE_CTRL1, 0x1745),
MAKE_REG(METER35_RATE_CTRL0, 0x1746),
MAKE_REG(METER35_RATE_CTRL1, 0x1747),
MAKE_REG(METER36_RATE_CTRL0, 0x1748),
MAKE_REG(METER36_RATE_CTRL1, 0x1749),
MAKE_REG(METER37_RATE_CTRL0, 0x174a),
MAKE_REG(METER37_RATE_CTRL1, 0x174b),
MAKE_REG(METER38_RATE_CTRL0, 0x174c),
MAKE_REG(METER38_RATE_CTRL1, 0x174d),
MAKE_REG(METER39_RATE_CTRL0, 0x174e),
MAKE_REG(METER39_RATE_CTRL1, 0x174f),
MAKE_REG(METER40_RATE_CTRL0, 0x1750),
MAKE_REG(METER40_RATE_CTRL1, 0x1751),
MAKE_REG(METER41_RATE_CTRL0, 0x1752),
MAKE_REG(METER41_RATE_CTRL1, 0x1753),
MAKE_REG(METER42_RATE_CTRL0, 0x1754),
MAKE_REG(METER42_RATE_CTRL1, 0x1755),
MAKE_REG(METER43_RATE_CTRL0, 0x1756),
MAKE_REG(METER43_RATE_CTRL1, 0x1757),
MAKE_REG(METER44_RATE_CTRL0, 0x1758),
MAKE_REG(METER44_RATE_CTRL1, 0x1759),
MAKE_REG(METER45_RATE_CTRL0, 0x175a),
MAKE_REG(METER45_RATE_CTRL1, 0x175b),
MAKE_REG(METER46_RATE_CTRL0, 0x175c),
MAKE_REG(METER46_RATE_CTRL1, 0x175d),
MAKE_REG(METER47_RATE_CTRL0, 0x175e),
MAKE_REG(METER47_RATE_CTRL1, 0x175f),
MAKE_REG(METER48_RATE_CTRL0, 0x1760),
MAKE_REG(METER48_RATE_CTRL1, 0x1761),
MAKE_REG(METER49_RATE_CTRL0, 0x1762),
MAKE_REG(METER49_RATE_CTRL1, 0x1763),
MAKE_REG(METER50_RATE_CTRL0, 0x1764),
MAKE_REG(METER50_RATE_CTRL1, 0x1765),
MAKE_REG(METER51_RATE_CTRL0, 0x1766),
MAKE_REG(METER51_RATE_CTRL1, 0x1767),
MAKE_REG(METER52_RATE_CTRL0, 0x1768),
MAKE_REG(METER52_RATE_CTRL1, 0x1769),
MAKE_REG(METER53_RATE_CTRL0, 0x176a),
MAKE_REG(METER53_RATE_CTRL1, 0x176b),
MAKE_REG(METER54_RATE_CTRL0, 0x176c),
MAKE_REG(METER54_RATE_CTRL1, 0x176d),
MAKE_REG(METER55_RATE_CTRL0, 0x176e),
MAKE_REG(METER55_RATE_CTRL1, 0x176f),
MAKE_REG(METER56_RATE_CTRL0, 0x1770),
MAKE_REG(METER56_RATE_CTRL1, 0x1771),
MAKE_REG(METER57_RATE_CTRL0, 0x1772),
MAKE_REG(METER57_RATE_CTRL1, 0x1773),
MAKE_REG(METER58_RATE_CTRL0, 0x1774),
MAKE_REG(METER58_RATE_CTRL1, 0x1775),
MAKE_REG(METER59_RATE_CTRL0, 0x1776),
MAKE_REG(METER59_RATE_CTRL1, 0x1777),
MAKE_REG(METER60_RATE_CTRL0, 0x1778),
MAKE_REG(METER60_RATE_CTRL1, 0x1779),
MAKE_REG(METER61_RATE_CTRL0, 0x177a),
MAKE_REG(METER61_RATE_CTRL1, 0x177b),
MAKE_REG(METER62_RATE_CTRL0, 0x177c),
MAKE_REG(METER62_RATE_CTRL1, 0x177d),
MAKE_REG(METER63_RATE_CTRL0, 0x177e),
MAKE_REG(METER63_RATE_CTRL1, 0x177f),
MAKE_REG(METER_MODE_SETTING2, 0x1780),
MAKE_REG(METER_MODE_SETTING3, 0x1781),
MAKE_REG(METER32_BUCKET_SIZE, 0x1790),
MAKE_REG(METER33_BUCKET_SIZE, 0x1791),
MAKE_REG(METER34_BUCKET_SIZE, 0x1792),
MAKE_REG(METER35_BUCKET_SIZE, 0x1793),
MAKE_REG(METER36_BUCKET_SIZE, 0x1794),
MAKE_REG(METER37_BUCKET_SIZE, 0x1795),
MAKE_REG(METER38_BUCKET_SIZE, 0x1796),
MAKE_REG(METER39_BUCKET_SIZE, 0x1797),
MAKE_REG(METER40_BUCKET_SIZE, 0x1798),
MAKE_REG(METER41_BUCKET_SIZE, 0x1799),
MAKE_REG(METER42_BUCKET_SIZE, 0x179a),
MAKE_REG(METER43_BUCKET_SIZE, 0x179b),
MAKE_REG(METER44_BUCKET_SIZE, 0x179c),
MAKE_REG(METER45_BUCKET_SIZE, 0x179d),
MAKE_REG(METER46_BUCKET_SIZE, 0x179e),
MAKE_REG(METER47_BUCKET_SIZE, 0x179f),
MAKE_REG(METER48_BUCKET_SIZE, 0x17a0),
MAKE_REG(METER49_BUCKET_SIZE, 0x17a1),
MAKE_REG(METER50_BUCKET_SIZE, 0x17a2),
MAKE_REG(METER51_BUCKET_SIZE, 0x17a3),
MAKE_REG(METER52_BUCKET_SIZE, 0x17a4),
MAKE_REG(METER53_BUCKET_SIZE, 0x17a5),
MAKE_REG(METER54_BUCKET_SIZE, 0x17a6),
MAKE_REG(METER55_BUCKET_SIZE, 0x17a7),
MAKE_REG(METER56_BUCKET_SIZE, 0x17a8),
MAKE_REG(METER57_BUCKET_SIZE, 0x17a9),
MAKE_REG(METER58_BUCKET_SIZE, 0x17aa),
MAKE_REG(METER59_BUCKET_SIZE, 0x17ab),
MAKE_REG(METER60_BUCKET_SIZE, 0x17ac),
MAKE_REG(METER61_BUCKET_SIZE, 0x17ad),
MAKE_REG(METER62_BUCKET_SIZE, 0x17ae),
MAKE_REG(METER63_BUCKET_SIZE, 0x17af),
MAKE_REG(METER_OVERRATE_INDICATOR2, 0x17b0),
MAKE_REG(METER_OVERRATE_INDICATOR3, 0x17b1),
MAKE_REG(METER_OVERRATE_INDICATOR2_8051, 0x17b2),
MAKE_REG(METER_OVERRATE_INDICATOR3_8051, 0x17b3),
MAKE_REG(METER_IFG_CTRL2, 0x17b4),
MAKE_REG(METER_IFG_CTRL3, 0x17b5),
MAKE_REG(METER_MISC, 0x17b6),
MAKE_REG(EEELLDP_CTRL0, 0x1820),
MAKE_REG(EEELLDP_PMSK, 0x1822),
MAKE_REG(EEELLDP_RX_VALUE_P00_08, 0x1843),
MAKE_REG(EEELLDP_RX_VALUE_P00_07, 0x1844),
MAKE_REG(EEELLDP_RX_VALUE_P00_06, 0x1845),
MAKE_REG(EEELLDP_RX_VALUE_P00_05, 0x1846),
MAKE_REG(EEELLDP_RX_VALUE_P00_04, 0x1847),
MAKE_REG(EEELLDP_RX_VALUE_P00_03, 0x1848),
MAKE_REG(EEELLDP_RX_VALUE_P00_02, 0x1849),
MAKE_REG(EEELLDP_RX_VALUE_P00_01, 0x184a),
MAKE_REG(EEELLDP_RX_VALUE_P00_00, 0x184b),
MAKE_REG(EEELLDP_RX_VALUE_P01_08, 0x184c),
MAKE_REG(EEELLDP_RX_VALUE_P01_07, 0x184d),
MAKE_REG(EEELLDP_RX_VALUE_P01_06, 0x184e),
MAKE_REG(EEELLDP_RX_VALUE_P01_05, 0x184f),
MAKE_REG(EEELLDP_RX_VALUE_P01_04, 0x1850),
MAKE_REG(EEELLDP_RX_VALUE_P01_03, 0x1851),
MAKE_REG(EEELLDP_RX_VALUE_P01_02, 0x1852),
MAKE_REG(EEELLDP_RX_VALUE_P01_01, 0x1853),
MAKE_REG(EEELLDP_RX_VALUE_P01_00, 0x1854),
MAKE_REG(EEELLDP_RX_VALUE_P02_08, 0x1855),
MAKE_REG(EEELLDP_RX_VALUE_P02_07, 0x1856),
MAKE_REG(EEELLDP_RX_VALUE_P02_06, 0x1857),
MAKE_REG(EEELLDP_RX_VALUE_P02_05, 0x1858),
MAKE_REG(EEELLDP_RX_VALUE_P02_04, 0x1859),
MAKE_REG(EEELLDP_RX_VALUE_P02_03, 0x185a),
MAKE_REG(EEELLDP_RX_VALUE_P02_02, 0x185b),
MAKE_REG(EEELLDP_RX_VALUE_P02_01, 0x185c),
MAKE_REG(EEELLDP_RX_VALUE_P02_00, 0x185d),
MAKE_REG(EEELLDP_RX_VALUE_P03_08, 0x185e),
MAKE_REG(EEELLDP_RX_VALUE_P03_07, 0x185f),
MAKE_REG(EEELLDP_RX_VALUE_P03_06, 0x1860),
MAKE_REG(EEELLDP_RX_VALUE_P03_05, 0x1861),
MAKE_REG(EEELLDP_RX_VALUE_P03_04, 0x1862),
MAKE_REG(EEELLDP_RX_VALUE_P03_03, 0x1863),
MAKE_REG(EEELLDP_RX_VALUE_P03_02, 0x1864),
MAKE_REG(EEELLDP_RX_VALUE_P03_01, 0x1865),
MAKE_REG(EEELLDP_RX_VALUE_P03_00, 0x1866),
MAKE_REG(EEELLDP_RX_VALUE_P04_08, 0x1867),
MAKE_REG(EEELLDP_RX_VALUE_P04_07, 0x1868),
MAKE_REG(EEELLDP_RX_VALUE_P04_06, 0x1869),
MAKE_REG(EEELLDP_RX_VALUE_P04_05, 0x186a),
MAKE_REG(EEELLDP_RX_VALUE_P04_04, 0x186b),
MAKE_REG(EEELLDP_RX_VALUE_P04_03, 0x186c),
MAKE_REG(EEELLDP_RX_VALUE_P04_02, 0x186d),
MAKE_REG(EEELLDP_RX_VALUE_P04_01, 0x186e),
MAKE_REG(EEELLDP_RX_VALUE_P04_00, 0x186f),
MAKE_REG(EEELLDP_RX_VALUE_P05_08, 0x1870),
MAKE_REG(EEELLDP_RX_VALUE_P05_07, 0x1871),
MAKE_REG(EEELLDP_RX_VALUE_P05_06, 0x1872),
MAKE_REG(EEELLDP_RX_VALUE_P05_05, 0x1873),
MAKE_REG(EEELLDP_RX_VALUE_P05_04, 0x1874),
MAKE_REG(EEELLDP_RX_VALUE_P05_03, 0x1875),
MAKE_REG(EEELLDP_RX_VALUE_P05_02, 0x1876),
MAKE_REG(EEELLDP_RX_VALUE_P05_01, 0x1877),
MAKE_REG(EEELLDP_RX_VALUE_P05_00, 0x1878),
MAKE_REG(EEELLDP_RX_VALUE_P06_08, 0x1879),
MAKE_REG(EEELLDP_RX_VALUE_P06_07, 0x187a),
MAKE_REG(EEELLDP_RX_VALUE_P06_06, 0x187b),
MAKE_REG(EEELLDP_RX_VALUE_P06_05, 0x187c),
MAKE_REG(EEELLDP_RX_VALUE_P06_04, 0x187d),
MAKE_REG(EEELLDP_RX_VALUE_P06_03, 0x187e),
MAKE_REG(EEELLDP_RX_VALUE_P06_02, 0x187f),
MAKE_REG(EEELLDP_RX_VALUE_P06_01, 0x1880),
MAKE_REG(EEELLDP_RX_VALUE_P06_00, 0x1881),
MAKE_REG(EEELLDP_RX_VALUE_P07_08, 0x1882),
MAKE_REG(EEELLDP_RX_VALUE_P07_07, 0x1883),
MAKE_REG(EEELLDP_RX_VALUE_P07_06, 0x1884),
MAKE_REG(EEELLDP_RX_VALUE_P07_05, 0x1885),
MAKE_REG(EEELLDP_RX_VALUE_P07_04, 0x1886),
MAKE_REG(EEELLDP_RX_VALUE_P07_03, 0x1887),
MAKE_REG(EEELLDP_RX_VALUE_P07_02, 0x1888),
MAKE_REG(EEELLDP_RX_VALUE_P07_01, 0x1889),
MAKE_REG(EEELLDP_RX_VALUE_P07_00, 0x188a),
MAKE_REG(EEELLDP_RX_VALUE_P08_08, 0x188b),
MAKE_REG(EEELLDP_RX_VALUE_P08_07, 0x188c),
MAKE_REG(EEELLDP_RX_VALUE_P08_06, 0x188d),
MAKE_REG(EEELLDP_RX_VALUE_P08_05, 0x188e),
MAKE_REG(EEELLDP_RX_VALUE_P08_04, 0x188f),
MAKE_REG(EEELLDP_RX_VALUE_P08_03, 0x1890),
MAKE_REG(EEELLDP_RX_VALUE_P08_02, 0x1891),
MAKE_REG(EEELLDP_RX_VALUE_P08_01, 0x1892),
MAKE_REG(EEELLDP_RX_VALUE_P08_00, 0x1893),
MAKE_REG(EEELLDP_RX_VALUE_P09_08, 0x1894),
MAKE_REG(EEELLDP_RX_VALUE_P09_07, 0x1895),
MAKE_REG(EEELLDP_RX_VALUE_P09_06, 0x1896),
MAKE_REG(EEELLDP_RX_VALUE_P09_05, 0x1897),
MAKE_REG(EEELLDP_RX_VALUE_P09_04, 0x1898),
MAKE_REG(EEELLDP_RX_VALUE_P09_03, 0x1899),
MAKE_REG(EEELLDP_RX_VALUE_P09_02, 0x189a),
MAKE_REG(EEELLDP_RX_VALUE_P09_01, 0x189b),
MAKE_REG(EEELLDP_RX_VALUE_P09_00, 0x189c),
MAKE_REG(EEELLDP_RX_VALUE_P10_08, 0x189d),
MAKE_REG(EEELLDP_RX_VALUE_P10_07, 0x189e),
MAKE_REG(EEELLDP_RX_VALUE_P10_06, 0x189f),
MAKE_REG(EEELLDP_RX_VALUE_P10_05, 0x18a0),
MAKE_REG(EEELLDP_RX_VALUE_P10_04, 0x18a1),
MAKE_REG(EEELLDP_RX_VALUE_P10_03, 0x18a2),
MAKE_REG(EEELLDP_RX_VALUE_P10_02, 0x18a3),
MAKE_REG(EEELLDP_RX_VALUE_P10_01, 0x18a4),
MAKE_REG(EEELLDP_RX_VALUE_P10_00, 0x18a5),
MAKE_REG(RLDP_CTRL0, 0x18e0),
MAKE_REG(RLDP_CTRL1, 0x18e1),
MAKE_REG(RLDP_CTRL2, 0x18e2),
MAKE_REG(RLDP_CTRL3, 0x18e3),
MAKE_REG(RLDP_CTRL4, 0x18e4),
MAKE_REG(RLDP_RAND_NUM0, 0x18e5),
MAKE_REG(RLDP_RAND_NUM1, 0x18e6),
MAKE_REG(RLDP_RAND_NUM2, 0x18e7),
MAKE_REG(RLDP_MAGIC_NUM0, 0x18e8),
MAKE_REG(RLDP_MAGIC_NUM1, 0x18e9),
MAKE_REG(RLDP_MAGIC_NUM2, 0x18ea),
MAKE_REG(RLDP_LOOPED_INDICATOR, 0x18eb),
MAKE_REG(RLDP_LOOP_PORT_REG0, 0x18ec),
MAKE_REG(RLDP_LOOP_PORT_REG1, 0x18ed),
MAKE_REG(RLDP_LOOP_PORT_REG2, 0x18ee),
MAKE_REG(RLDP_LOOP_PORT_REG3, 0x18ef),
MAKE_REG(RLDP_RELEASED_INDICATOR, 0x18f0),
MAKE_REG(RLDP_LOOPSTATUS_INDICATOR, 0x18f1),
MAKE_REG(RLDP_LOOP_PORT_REG4, 0x18f2),
MAKE_REG(RLDP_LOOP_PORT_REG5, 0x18f3),
MAKE_REG(RLDP_CTRL5, 0x18f4),
MAKE_REG(EEE_500M_CTRL0, 0x1900),
MAKE_REG(EEE_RXIDLE_GIGA_CTRL, 0x1901),
MAKE_REG(EEE_RXIDLE_500M_CTRL, 0x1902),
MAKE_REG(EEE_DECISION_GIGA_500M, 0x1903),
MAKE_REG(EEE_DECISION_100M, 0x1904),
MAKE_REG(EEEP_DEFER_TXLPI, 0x1905),
MAKE_REG(EEEP_EN, 0x1906),
MAKE_REG(EEEP_TI_GIGA_500M, 0x1907),
MAKE_REG(EEEP_TI_100M, 0x1908),
MAKE_REG(EEEP_CTRL2, 0x1909),
MAKE_REG(EEEP_RX_RATE_500M, 0x190b),
MAKE_REG(EEEP_RW_GIGA_SLV, 0x190c),
MAKE_REG(EEEP_TMR_GIGA, 0x190d),
MAKE_REG(EEEP_TMR_500M, 0x190e),
MAKE_REG(EEEP_TMR_100M, 0x190f),
MAKE_REG(EEEP_RW_500M_MST_SLV, 0x1910),
MAKE_REG(EEEP_500M_CTRL0, 0x1911),
MAKE_REG(EEEP_500M_CTRL1, 0x1912),
MAKE_REG(EEEP_500M_CTRL2, 0x1913),
MAKE_REG(EEE_NEW_CTRL0, 0x1914),
MAKE_REG(EEE_LONGIDLE_100M, 0x1915),
MAKE_REG(EEE_LONGIDLE_500M, 0x1916),
MAKE_REG(EEE_LONGIDLE_GIGA, 0x1917),
MAKE_REG(EEE_MINIPG_100M, 0x1918),
MAKE_REG(EEE_MINIPG_500M, 0x1919),
MAKE_REG(EEE_MINIPG_GIGA, 0x191A),
MAKE_REG(EEE_LONGIDLE_CTRL0, 0x191B),
MAKE_REG(EEE_LONGIDLE_CTRL1, 0x191C),
MAKE_REG(EEE_TD_CTRL_H, 0x191d),
MAKE_REG(NIC_RXRDRL, 0x1a04),
MAKE_REG(NIC_RXRDRH, 0x1a05),
MAKE_REG(NIC_TXASRL, 0x1a08),
MAKE_REG(NIC_TXASRH, 0x1a09),
MAKE_REG(NIC_RXCMDR, 0x1a0c),
MAKE_REG(NIC_TXCMDR, 0x1a0d),
MAKE_REG(NIC_IMS, 0x1a0e),
MAKE_REG(NIC_IMR, 0x1a0f),
MAKE_REG(NIC_RXCR0, 0x1a14),
MAKE_REG(NIC_RXCR1, 0x1a15),
MAKE_REG(NIC_TXCR, 0x1a16),
MAKE_REG(NIC_GCR, 0x1a17),
MAKE_REG(NIC_MHR0, 0x1a24),
MAKE_REG(NIC_MHR1, 0x1a25),
MAKE_REG(NIC_MHR2, 0x1a26),
MAKE_REG(NIC_MHR3, 0x1a27),
MAKE_REG(NIC_MHR4, 0x1a28),
MAKE_REG(NIC_MHR5, 0x1a29),
MAKE_REG(NIC_MHR6, 0x1a2a),
MAKE_REG(NIC_MHR7, 0x1a2b),
MAKE_REG(NIC_PAHR0, 0x1a2c),
MAKE_REG(NIC_PAHR1, 0x1a2d),
MAKE_REG(NIC_PAHR2, 0x1a2e),
MAKE_REG(NIC_PAHR3, 0x1a2f),
MAKE_REG(NIC_PAHR4, 0x1a30),
MAKE_REG(NIC_PAHR5, 0x1a31),
MAKE_REG(NIC_PAHR6, 0x1a32),
MAKE_REG(NIC_PAHR7, 0x1a33),
MAKE_REG(NIC_TXSTOPRL, 0x1a44),
MAKE_REG(NIC_TXSTOPRH, 0x1a45),
MAKE_REG(NIC_RXSTOPRL, 0x1a46),
MAKE_REG(NIC_RXSTOPRH, 0x1a47),
MAKE_REG(NIC_RXFSTR, 0x1a48),
MAKE_REG(NIC_RXMBTRL, 0x1a4c),
MAKE_REG(NIC_RXMBTRH, 0x1a4d),
MAKE_REG(NIC_RXMPTR, 0x1a4e),
MAKE_REG(NIC_T0TR, 0x1a4f),
MAKE_REG(NIC_CRXCPRL, 0x1a50),
MAKE_REG(NIC_CRXCPRH, 0x1a51),
MAKE_REG(NIC_CTXCPRL, 0x1a52),
MAKE_REG(NIC_CTXPCRH, 0x1a53),
MAKE_REG(NIC_SRXCURPKTRL, 0x1a54),
MAKE_REG(NIC_SRXCURPKTRH, 0x1a55),
MAKE_REG(NIC_STXCURPKTRL, 0x1a56),
MAKE_REG(NIC_STXCURPKTRH, 0x1a57),
MAKE_REG(NIC_STXPKTLENRL, 0x1a58),
MAKE_REG(NIC_STXPKTLENRH, 0x1a59),
MAKE_REG(NIC_STXCURUNITRL, 0x1a5a),
MAKE_REG(NIC_STXCURUNITRH, 0x1a5b),
MAKE_REG(NIC_DROP_MODE, 0x1a5c),
MAKE_REG(LED_SYS_CONFIG, 0x1b00),
MAKE_REG(LED_SYS_CONFIG2, 0x1b01),
MAKE_REG(LED_MODE, 0x1b02),
MAKE_REG(LED_CONFIGURATION, 0x1b03),
MAKE_REG(RTCT_RESULTS_CFG, 0x1b04),
MAKE_REG(RTCT_LED, 0x1b05),
MAKE_REG(CPU_FORCE_LED_CFG, 0x1b07),
MAKE_REG(CPU_FORCE_LED0_CFG0, 0x1b08),
MAKE_REG(CPU_FORCE_LED0_CFG1, 0x1b09),
MAKE_REG(CPU_FORCE_LED1_CFG0, 0x1b0a),
MAKE_REG(CPU_FORCE_LED1_CFG1, 0x1b0b),
MAKE_REG(CPU_FORCE_LED2_CFG0, 0x1b0c),
MAKE_REG(CPU_FORCE_LED2_CFG1, 0x1b0d),
MAKE_REG(LED_ACTIVE_LOW_CFG0, 0x1b0e),
MAKE_REG(LED_ACTIVE_LOW_CFG1, 0x1b0f),
MAKE_REG(LED_ACTIVE_LOW_CFG2, 0x1b10),
MAKE_REG(SEL_RTCT_PARA, 0x1b21),
MAKE_REG(RTCT_ENABLE, 0x1b22),
MAKE_REG(RTCT_TIMEOUT, 0x1b23),
MAKE_REG(PARA_LED_IO_EN1, 0x1b24),
MAKE_REG(PARA_LED_IO_EN2, 0x1b25),
MAKE_REG(SCAN0_LED_IO_EN1, 0x1b26),
MAKE_REG(SCAN1_LED_IO_EN2, 0x1b27),
MAKE_REG(LPI_LED_OPT1, 0x1b28),
MAKE_REG(LPI_LED_OPT2, 0x1b29),
MAKE_REG(LPI_LED_OPT3, 0x1b2a),
MAKE_REG(P0_LED_MUX, 0x1b2b),
MAKE_REG(P1_LED_MUX, 0x1b2c),
MAKE_REG(P2_LED_MUX, 0x1b2d),
MAKE_REG(P3_LED_MUX, 0x1b2e),
MAKE_REG(P4_LED_MUX, 0x1b2f),
MAKE_REG(LED0_DATA_CTRL, 0x1b30),
MAKE_REG(LED1_DATA_CTRL, 0x1b31),
MAKE_REG(LED2_DATA_CTRL, 0x1b32),
MAKE_REG(PARA_LED_IO_EN3, 0x1b33),
MAKE_REG(SCAN1_LED_IO_EN3, 0x1b34),
MAKE_REG(P5_LED_MUX, 0x1b35),
MAKE_REG(P6_LED_MUX, 0x1b36),
MAKE_REG(P7_LED_MUX, 0x1b37),
MAKE_REG(P8_LED_MUX, 0x1b38),
MAKE_REG(P9_LED_MUX, 0x1b39),
MAKE_REG(SERIAL_LED_CTRL, 0x1b3a),
MAKE_REG(IGMP_MLD_CFG0, 0x1c00),
MAKE_REG(IGMP_MLD_CFG1, 0x1c01),
MAKE_REG(IGMP_MLD_CFG2, 0x1c02),
MAKE_REG(IGMP_DYNAMIC_ROUTER_PORT, 0x1c03),
MAKE_REG(IGMP_STATIC_ROUTER_PORT, 0x1c04),
MAKE_REG(IGMP_PORT0_CONTROL, 0x1c05),
MAKE_REG(IGMP_PORT1_CONTROL, 0x1c06),
MAKE_REG(IGMP_PORT2_CONTROL, 0x1c07),
MAKE_REG(IGMP_PORT3_CONTROL, 0x1c08),
MAKE_REG(IGMP_PORT4_CONTROL, 0x1c09),
MAKE_REG(IGMP_PORT5_CONTROL, 0x1c0a),
MAKE_REG(IGMP_PORT6_CONTROL, 0x1c0b),
MAKE_REG(IGMP_PORT7_CONTROL, 0x1c0c),
MAKE_REG(IGMP_PORT01_MAX_GROUP, 0x1c0d),
MAKE_REG(IGMP_PORT23_MAX_GROUP, 0x1c0e),
MAKE_REG(IGMP_PORT45_MAX_GROUP, 0x1c0f),
MAKE_REG(IGMP_PORT67_MAX_GROUP, 0x1c10),
MAKE_REG(IGMP_PORT01_CURRENT_GROUP, 0x1c11),
MAKE_REG(IGMP_PORT23_CURRENT_GROUP, 0x1c12),
MAKE_REG(IGMP_PORT45_CURRENT_GROUP, 0x1c13),
MAKE_REG(IGMP_PORT67_CURRENT_GROUP, 0x1c14),
MAKE_REG(IGMP_MLD_CFG3, 0x1c15),
MAKE_REG(IGMP_MLD_CFG4, 0x1c16),
MAKE_REG(IGMP_GROUP_USAGE_LIST0, 0x1c20),
MAKE_REG(IGMP_GROUP_USAGE_LIST1, 0x1c21),
MAKE_REG(IGMP_GROUP_USAGE_LIST2, 0x1c22),
MAKE_REG(IGMP_GROUP_USAGE_LIST3, 0x1c23),
MAKE_REG(IGMP_GROUP_USAGE_LIST4, 0x1c24),
MAKE_REG(IGMP_GROUP_USAGE_LIST5, 0x1c25),
MAKE_REG(IGMP_GROUP_USAGE_LIST6, 0x1c26),
MAKE_REG(IGMP_GROUP_USAGE_LIST7, 0x1c27),
MAKE_REG(IGMP_GROUP_USAGE_LIST8, 0x1c28),
MAKE_REG(IGMP_GROUP_USAGE_LIST9, 0x1c29),
MAKE_REG(IGMP_GROUP_USAGE_LIST10, 0x1c2a),
MAKE_REG(IGMP_GROUP_USAGE_LIST11, 0x1c2b),
MAKE_REG(IGMP_GROUP_USAGE_LIST12, 0x1c2c),
MAKE_REG(IGMP_GROUP_USAGE_LIST13, 0x1c2d),
MAKE_REG(IGMP_GROUP_USAGE_LIST14, 0x1c2e),
MAKE_REG(IGMP_GROUP_USAGE_LIST15, 0x1c2f),
MAKE_REG(EAV_CTRL0, 0x1c30),
MAKE_REG(EAV_CTRL1, 0x1c31),
MAKE_REG(EAV_CTRL2, 0x1c32),
MAKE_REG(SYS_TIME_FREQ, 0x1c43),
MAKE_REG(SYS_TIME_OFFSET_L, 0x1c44),
MAKE_REG(SYS_TIME_OFFSET_H, 0x1c45),
MAKE_REG(SYS_TIME_OFFSET_512NS_L, 0x1c46),
MAKE_REG(SYS_TIME_OFFSET_512NS_H, 0x1c47),
MAKE_REG(SYS_TIME_SEC_TRANSIT, 0x1c48),
MAKE_REG(SYS_TIME_SEC_HIGH_L, 0x1c49),
MAKE_REG(SYS_TIME_SEC_HIGH_H, 0x1c4a),
MAKE_REG(SYS_TIME_512NS_L, 0x1c4b),
MAKE_REG(SYS_TIME_512NS_H, 0x1c4c),
MAKE_REG(FALLBACK_CTRL, 0x1c70),
MAKE_REG(FALLBACK_PORT0_CFG0, 0x1c71),
MAKE_REG(FALLBACK_PORT0_CFG1, 0x1c72),
MAKE_REG(FALLBACK_PORT0_CFG2, 0x1c73),
MAKE_REG(FALLBACK_PORT0_CFG3, 0x1c74),
MAKE_REG(FALLBACK_PORT1_CFG0, 0x1c75),
MAKE_REG(FALLBACK_PORT1_CFG1, 0x1c76),
MAKE_REG(FALLBACK_PORT1_CFG2, 0x1c77),
MAKE_REG(FALLBACK_PORT1_CFG3, 0x1c78),
MAKE_REG(FALLBACK_PORT2_CFG0, 0x1c79),
MAKE_REG(FALLBACK_PORT2_CFG1, 0x1c7a),
MAKE_REG(FALLBACK_PORT2_CFG2, 0x1c7b),
MAKE_REG(FALLBACK_PORT2_CFG3, 0x1c7c),
MAKE_REG(FALLBACK_PORT3_CFG0, 0x1c7d),
MAKE_REG(FALLBACK_PORT3_CFG1, 0x1c7e),
MAKE_REG(FALLBACK_PORT3_CFG2, 0x1c7f),
MAKE_REG(FALLBACK_PORT3_CFG3, 0x1c80),
MAKE_REG(FALLBACK_PORT4_CFG0, 0x1c81),
MAKE_REG(FALLBACK_PORT4_CFG1, 0x1c82),
MAKE_REG(FALLBACK_PORT4_CFG2, 0x1c83),
MAKE_REG(FALLBACK_PORT4_CFG3, 0x1c84),
MAKE_REG(FALLBACK_CTRL1, 0x1c85),
MAKE_REG(FALLBACK_CPL, 0x1c86),
MAKE_REG(FALLBACK_PHY_PAGE, 0x1c87),
MAKE_REG(FALLBACK_PHY_REG, 0x1c88),
MAKE_REG(AFBK_INFO_X0, 0x1c89),
MAKE_REG(AFBK_INFO_X1, 0x1c8a),
MAKE_REG(AFBK_INFO_X2, 0x1c8b),
MAKE_REG(AFBK_INFO_X3, 0x1c8c),
MAKE_REG(AFBK_INFO_X4, 0x1c8d),
MAKE_REG(AFBK_INFO_X5, 0x1c8e),
MAKE_REG(AFBK_INFO_X6, 0x1c8f),
MAKE_REG(AFBK_INFO_X7, 0x1c90),
MAKE_REG(AFBK_INFO_X8, 0x1c91),
MAKE_REG(AFBK_INFO_X9, 0x1c92),
MAKE_REG(AFBK_INFO_X10, 0x1c93),
MAKE_REG(AFBK_INFO_X11, 0x1c94),
MAKE_REG(FALLBACK_PORT5_CFG0, 0x1ca0),
MAKE_REG(FALLBACK_PORT5_CFG1, 0x1ca1),
MAKE_REG(FALLBACK_PORT5_CFG2, 0x1ca2),
MAKE_REG(FALLBACK_PORT5_CFG3, 0x1ca3),
MAKE_REG(FALLBACK_PORT6_CFG0, 0x1ca4),
MAKE_REG(FALLBACK_PORT6_CFG1, 0x1ca5),
MAKE_REG(FALLBACK_PORT6_CFG2, 0x1ca6),
MAKE_REG(FALLBACK_PORT6_CFG3, 0x1ca7),
MAKE_REG(FALLBACK_PORT7_CFG0, 0x1ca8),
MAKE_REG(FALLBACK_PORT7_CFG1, 0x1ca9),
MAKE_REG(FALLBACK_PORT7_CFG2, 0x1caa),
MAKE_REG(FALLBACK_PORT7_CFG3, 0x1cab),
MAKE_REG(IGMP_PORT8_CONTROL, 0x1cb0),
MAKE_REG(IGMP_PORT9_CONTROL, 0x1cb1),
MAKE_REG(IGMP_PORT10_CONTROL, 0x1cb2),
MAKE_REG(IGMP_PORT89_MAX_GROUP, 0x1cb3),
MAKE_REG(IGMP_PORT10_MAX_GROUP, 0x1cb4),
MAKE_REG(IGMP_PORT89_CURRENT_GROUP, 0x1cb5),
MAKE_REG(IGMP_PORT10_CURRENT_GROUP, 0x1cb6),
MAKE_REG(IGMP_L3_CHECKSUM_CHECK, 0x1cb7),
MAKE_REG(PCSXF_CFG, 0x1d00),
MAKE_REG(PHYID_CFG0, 0x1d01),
MAKE_REG(PHYID_CFG1, 0x1d02),
MAKE_REG(PHY_POLL_CFG0, 0x1d03),
MAKE_REG(PHY_POLL_CFG1, 0x1d04),
MAKE_REG(PHY_POLL_CFG2, 0x1d05),
MAKE_REG(PHY_POLL_CFG3, 0x1d06),
MAKE_REG(PHY_POLL_CFG4, 0x1d07),
MAKE_REG(PHY_POLL_CFG5, 0x1d08),
MAKE_REG(PHY_POLL_CFG6, 0x1d09),
MAKE_REG(PHY_POLL_CFG7, 0x1d0a),
MAKE_REG(PHY_POLL_CFG8, 0x1d0b),
MAKE_REG(PHY_POLL_CFG9, 0x1d0c),
MAKE_REG(PHY_POLL_CFG10, 0x1d0d),
MAKE_REG(PHY_POLL_CFG11, 0x1d0e),
MAKE_REG(PHY_POLL_CFG12, 0x1d0f),
MAKE_REG(SDS_MISC, 0x1d11),
MAKE_REG(FIFO_CTRL, 0x1d12),
MAKE_REG(BCAM_SETTING, 0x1d13),
MAKE_REG(GPHY_ACS_MISC, 0x1d14),
MAKE_REG(GPHY_OCP_MSB_0, 0x1d15),
MAKE_REG(GPHY_OCP_MSB_1, 0x1d16),
MAKE_REG(GPHY_OCP_MSB_2, 0x1d17),
MAKE_REG(GPHY_OCP_MSB_3, 0x1d18),
MAKE_REG(GPIO_67C_I_X0, 0x1d19),
MAKE_REG(GPIO_67C_I_X1, 0x1d1a),
MAKE_REG(GPIO_67C_I_X2, 0x1d1b),
MAKE_REG(GPIO_67C_I_X3, 0x1d1c),
MAKE_REG(GPIO_67C_O_X0, 0x1d1d),
MAKE_REG(GPIO_67C_O_X1, 0x1d1e),
MAKE_REG(GPIO_67C_O_X2, 0x1d1f),
MAKE_REG(GPIO_67C_O_X3, 0x1d20),
MAKE_REG(GPIO_67C_OE_X0, 0x1d21),
MAKE_REG(GPIO_67C_OE_X1, 0x1d22),
MAKE_REG(GPIO_67C_OE_X2, 0x1d23),
MAKE_REG(GPIO_67C_OE_X3, 0x1d24),
MAKE_REG(GPIO_MODE_67C_X0, 0x1d25),
MAKE_REG(GPIO_MODE_67C_X1, 0x1d26),
MAKE_REG(GPIO_MODE_67C_X2, 0x1d27),
MAKE_REG(GPIO_MODE_67C_X3, 0x1d28),
MAKE_REG(WGPHY_MISC_0, 0x1d29),
MAKE_REG(WGPHY_MISC_1, 0x1d2a),
MAKE_REG(WGPHY_MISC_2, 0x1d2b),
MAKE_REG(CFG_AFBK_GPHY_0, 0x1d2c),
MAKE_REG(CFG_AFBK_GPHY_1, 0x1d2d),
MAKE_REG(EF_SLV_CTRL_0, 0x1d2e),
MAKE_REG(EF_SLV_CTRL_1, 0x1d2f),
MAKE_REG(EF_SLV_CTRL_2, 0x1d30),
MAKE_REG(IO_MISC_FUNC, 0x1d32),
MAKE_REG(HTRAM_DVS, 0x1d33),
MAKE_REG(EF_SLV_CTRL_3, 0x1d34),
MAKE_REG(INBAND_EN14C, 0x1d35),
MAKE_REG(CFG_SWR_L, 0x1d36),
MAKE_REG(BTCAM_CTRL, 0x1d37),
MAKE_REG(PBRAM_BISR_CTRL, 0x1d38),
MAKE_REG(CVLANRAM_BISR_CTRL, 0x1d39),
MAKE_REG(CFG_1588_TIMER_EN_GPI, 0x1d3a),
MAKE_REG(MDIO_PRMB_SUPP, 0x1d3b),
MAKE_REG(BOND4READ, 0x1d3c),
MAKE_REG(REG_TO_ECO0, 0x1d3d),
MAKE_REG(REG_TO_ECO1, 0x1d3e),
MAKE_REG(REG_TO_ECO2, 0x1d3f),
MAKE_REG(REG_TO_ECO3, 0x1d40),
MAKE_REG(REG_TO_ECO4, 0x1d41),
MAKE_REG(PHYSTS_CTRL0, 0x1d42),
MAKE_REG(SSC_CTRL0_0, 0x1d44),
MAKE_REG(SSC_RDM_SEED, 0x1d45),
MAKE_REG(SSC_PN_POLY_SEL, 0x1d46),
MAKE_REG(SSC_CTRL0_3, 0x1d47),
MAKE_REG(SSC_CTRL0_4, 0x1d48),
MAKE_REG(SSC_CTRL0_5, 0x1d49),
MAKE_REG(SSC_STS0, 0x1d4a),
MAKE_REG(SSC_CTRL1_0, 0x1d4b),
MAKE_REG(SSC_RDM_SEED1, 0x1d4c),
MAKE_REG(SSC_PN_POLY_SEL1, 0x1d4d),
MAKE_REG(SSC_CTRL1_3, 0x1d4e),
MAKE_REG(SSC_CTRL1_4, 0x1d4f),
MAKE_REG(SSC_CTRL1_5, 0x1d50),
MAKE_REG(SSC_STS1, 0x1d51),
MAKE_REG(SSC_CTRL2_0, 0x1d52),
MAKE_REG(SSC_RDM_SEED2, 0x1d53),
MAKE_REG(SSC_PN_POLY_SEL2, 0x1d54),
MAKE_REG(SSC_CTRL2_3, 0x1d55),
MAKE_REG(SSC_CTRL2_4, 0x1d56),
MAKE_REG(SSC_CTRL2_5, 0x1d57),
MAKE_REG(SSC_STS2, 0x1d58),
MAKE_REG(SSC_CTRL3_0, 0x1d59),
MAKE_REG(SSC_RDM_SEED3, 0x1d5a),
MAKE_REG(SSC_PN_POLY_SEL3, 0x1d5b),
MAKE_REG(SSC_CTRL3_3, 0x1d5c),
MAKE_REG(SSC_CTRL3_4, 0x1d5d),
MAKE_REG(SSC_CTRL3_5, 0x1d5e),
MAKE_REG(SSC_STS3, 0x1d5f),
MAKE_REG(PHY_POLL_CFG13, 0x1d60),
MAKE_REG(PHY_POLL_CFG14, 0x1d61),
MAKE_REG(FRC_SYS_CLK, 0x1d62),
MAKE_REG(AFE_SSC_CTRL, 0x1d63),
MAKE_REG(BUFF_RST_CTRL0, 0x1d64),
MAKE_REG(BUFF_RST_CTRL1, 0x1d65),
MAKE_REG(BUFF_RST_CTRL2, 0x1d66),
MAKE_REG(BUFF_RST_CTRL3, 0x1d67),
MAKE_REG(BUFF_RST_CTRL4, 0x1d68),
MAKE_REG(BUFF_RST_CTRL5, 0x1d69),
MAKE_REG(TOP_CON0, 0x1d70),
MAKE_REG(TOP_CON1, 0x1d71),
MAKE_REG(SWR_FPWM, 0x1d72),
MAKE_REG(EEEP_CTRL_500M, 0x1d73),
MAKE_REG(SHORT_PRMB, 0x1d74),
MAKE_REG(INDSC_THR_CTRL, 0x1d75),
MAKE_REG(SET_PAD_CTRL_NEW, 0x1d80),
MAKE_REG(SET_PAD_DRI_0, 0x1d81),
MAKE_REG(SET_PAD_DRI_1, 0x1d82),
MAKE_REG(SET_PAD_DRI_2, 0x1d83),
MAKE_REG(SET_PAD_SLEW_0, 0x1d84),
MAKE_REG(SET_PAD_SLEW_1, 0x1d85),
MAKE_REG(SET_PAD_SLEW_2, 0x1d86),
MAKE_REG(SET_PAD_SMT_0, 0x1d87),
MAKE_REG(SET_PAD_SMT_1, 0x1d88),
MAKE_REG(SET_PAD_SMT_2, 0x1d89),
MAKE_REG(M_I2C_CTL_STA_REG, 0x1d8a),
MAKE_REG(M_I2C_DUMB_RW_ADDR_0, 0x1d8b),
MAKE_REG(M_I2C_DUMB_RW_ADDR_1, 0x1d8c),
MAKE_REG(M_I2C_DUMB_RW_DATA_0, 0x1d8d),
MAKE_REG(M_I2C_DUMB_RW_DATA_1, 0x1d8e),
MAKE_REG(M_I2C_DUMB_RW_CTL, 0x1d8f),
MAKE_REG(M_I2C_SYS_CTL, 0x1d90),
MAKE_REG(HT_PB_SRAM_CTRL, 0x1da0),
MAKE_REG(HT_PB_SRAM_ADDR, 0x1da1),
MAKE_REG(HT_PB_SRAM_DIN0, 0x1da2),
MAKE_REG(HT_PB_SRAM_DIN1, 0x1da3),
MAKE_REG(HT_PB_SRAM_DOUT0, 0x1da4),
MAKE_REG(HT_PB_SRAM_DOUT1, 0x1da5),
MAKE_REG(PHY_STAT_0, 0x1db0),
MAKE_REG(PHY_STAT_1, 0x1db1),
MAKE_REG(PHY_STAT_2, 0x1db2),
MAKE_REG(PHY_STAT_3, 0x1db3),
MAKE_REG(PHY_STAT_4, 0x1db4),
MAKE_REG(PHY_STAT_5, 0x1db5),
MAKE_REG(PHY_STAT_6, 0x1db6),
MAKE_REG(PHY_STAT_7, 0x1db7),
MAKE_REG(SDS_STAT_0, 0x1db8),
MAKE_REG(SDS_STAT_1, 0x1db9),
MAKE_REG(MAC_LINK_STAT_0, 0x1dba),
MAKE_REG(MAC_LINK_STAT_1, 0x1dbb),
MAKE_REG(MISC_CONTROL_1, 0x1dc0),
MAKE_REG(SDS_MISC_1, 0x1dc1),
MAKE_REG(FIBER_CFG_2_1, 0x1dc2),
MAKE_REG(FIBER_CFG_1_1, 0x1dc3),
MAKE_REG(PHYSTS_CTRL0_1, 0x1dc4),
MAKE_REG(FIBER_CFG_3_1, 0x1dc5),
MAKE_REG(FIBER_CFG_4_1, 0x1dc6),
MAKE_REG(BUFF_RST_CTRL2_2, 0x1dc7),
MAKE_REG(PHY_DEBUG_CNT_CTRL, 0x1dc8),
MAKE_REG(TXPKT_CNT_L_0, 0x1dc9),
MAKE_REG(TXPKT_CNT_H_0, 0x1dca),
MAKE_REG(RXPKT_CNT_L_0, 0x1dcb),
MAKE_REG(RXPKT_CNT_H_0, 0x1dcc),
MAKE_REG(TX_CRC_0, 0x1dcd),
MAKE_REG(RX_CRC_0, 0x1dce),
MAKE_REG(TXPKT_CNT_L_1, 0x1dcf),
MAKE_REG(TXPKT_CNT_H_1, 0x1dd0),
MAKE_REG(RXPKT_CNT_L_1, 0x1dd1),
MAKE_REG(RXPKT_CNT_H_1, 0x1dd2),
MAKE_REG(TX_CRC_1, 0x1dd3),
MAKE_REG(RX_CRC_1, 0x1dd4),
MAKE_REG(TXPKT_CNT_L_2, 0x1dd5),
MAKE_REG(TXPKT_CNT_H_2, 0x1dd6),
MAKE_REG(RXPKT_CNT_L_2, 0x1dd7),
MAKE_REG(RXPKT_CNT_H_2, 0x1dd8),
MAKE_REG(TX_CRC_2, 0x1dd9),
MAKE_REG(RX_CRC_2, 0x1dda),
MAKE_REG(TXPKT_CNT_L_3, 0x1ddb),
MAKE_REG(TXPKT_CNT_H_3, 0x1ddc),
MAKE_REG(RXPKT_CNT_L_3, 0x1ddd),
MAKE_REG(RXPKT_CNT_H_3, 0x1dde),
MAKE_REG(TX_CRC_3, 0x1ddf),
MAKE_REG(RX_CRC_3, 0x1de0),
MAKE_REG(TXPKT_CNT_L_4, 0x1de1),
MAKE_REG(TXPKT_CNT_H_4, 0x1de2),
MAKE_REG(RXPKT_CNT_L_4, 0x1de3),
MAKE_REG(RXPKT_CNT_H_4, 0x1de4),
MAKE_REG(TX_CRC_4, 0x1de5),
MAKE_REG(RX_CRC_4, 0x1de6),
MAKE_REG(TXPKT_CNT_L_5, 0x1de7),
MAKE_REG(TXPKT_CNT_H_5, 0x1de8),
MAKE_REG(RXPKT_CNT_L_5, 0x1de9),
MAKE_REG(RXPKT_CNT_H_5, 0x1dea),
MAKE_REG(TX_CRC_5, 0x1deb),
MAKE_REG(RX_CRC_5, 0x1dec),
MAKE_REG(TXPKT_CNT_L_6, 0x1ded),
MAKE_REG(TXPKT_CNT_H_6, 0x1dee),
MAKE_REG(RXPKT_CNT_L_6, 0x1def),
MAKE_REG(RXPKT_CNT_H_6, 0x1df0),
MAKE_REG(TX_CRC_6, 0x1df1),
MAKE_REG(RX_CRC_6, 0x1df2),
MAKE_REG(TXPKT_CNT_L_7, 0x1df3),
MAKE_REG(TXPKT_CNT_H_7, 0x1df4),
MAKE_REG(RXPKT_CNT_L_7, 0x1df5),
MAKE_REG(RXPKT_CNT_H_7, 0x1df6),
MAKE_REG(TX_CRC_7, 0x1df7),
MAKE_REG(RX_CRC_7, 0x1df8),
MAKE_REG(BOND_DBG_0, 0x1df9),
MAKE_REG(BOND_DBG_1, 0x1dfa),
MAKE_REG(STRP_DBG_0, 0x1dfb),
MAKE_REG(STRP_DBG_1, 0x1dfc),
MAKE_REG(STRP_DBG_2, 0x1dfd),
MAKE_REG(FIB0_CFG00, 0x6200),
MAKE_REG(FIB0_CFG01, 0x6201),
MAKE_REG(FIB0_CFG02, 0x6202),
MAKE_REG(FIB0_CFG03, 0x6203),
MAKE_REG(FIB0_CFG04, 0x6204),
MAKE_REG(FIB0_CFG05, 0x6205),
MAKE_REG(FIB0_CFG06, 0x6206),
MAKE_REG(FIB0_CFG07, 0x6207),
MAKE_REG(FIB0_CFG08, 0x6208),
MAKE_REG(FIB0_CFG09, 0x6209),
MAKE_REG(FIB0_CFG10, 0x620a),
MAKE_REG(FIB0_CFG11, 0x620b),
MAKE_REG(FIB0_CFG12, 0x620c),
MAKE_REG(FIB0_CFG13, 0x620d),
MAKE_REG(FIB0_CFG14, 0x620e),
MAKE_REG(FIB0_CFG15, 0x620f),
MAKE_REG(FIB1_CFG00, 0x6210),
MAKE_REG(FIB1_CFG01, 0x6211),
MAKE_REG(FIB1_CFG02, 0x6212),
MAKE_REG(FIB1_CFG03, 0x6213),
MAKE_REG(FIB1_CFG04, 0x6214),
MAKE_REG(FIB1_CFG05, 0x6215),
MAKE_REG(FIB1_CFG06, 0x6216),
MAKE_REG(FIB1_CFG07, 0x6217),
MAKE_REG(FIB1_CFG08, 0x6218),
MAKE_REG(FIB1_CFG09, 0x6219),
MAKE_REG(FIB1_CFG10, 0x621a),
MAKE_REG(FIB1_CFG11, 0x621b),
MAKE_REG(FIB1_CFG12, 0x621c),
MAKE_REG(FIB1_CFG13, 0x621d),
MAKE_REG(FIB1_CFG14, 0x621e),
MAKE_REG(FIB1_CFG15, 0x621f),
MAKE_REG(PTP_TIME_NSEC_L_NSEC, 0x6400),
MAKE_REG(PTP_TIME_NSEC_H_NSEC, 0x6401),
MAKE_REG(PTP_TIME_SEC_L_SEC, 0x6402),
MAKE_REG(PTP_TIME_SEC_H_SEC, 0x6403),
MAKE_REG(PTP_TIME_CFG, 0x6404),
MAKE_REG(OTAG_TPID, 0x6405),
MAKE_REG(ITAG_TPID, 0x6406),
MAKE_REG(MAC_ADDR_L, 0x6407),
MAKE_REG(MAC_ADDR_M, 0x6408),
MAKE_REG(MAC_ADDR_H, 0x6409),
MAKE_REG(PTP_TIME_NSEC_L_NSEC_RD, 0x640a),
MAKE_REG(PTP_TIME_NSEC_H_NSEC_RD, 0x640b),
MAKE_REG(PTP_TIME_SEC_L_SEC_RD, 0x640c),
MAKE_REG(PTP_TIME_SEC_H_SEC_RD, 0x640d),
MAKE_REG(PTP_TIME_CFG2, 0x640e),
MAKE_REG(PTP_INTERRUPT_CFG, 0x640f),
MAKE_REG(P0_TX_SYNC_SEQ_ID, 0x6410),
MAKE_REG(P0_TX_DELAY_REQ_SEQ_ID, 0x6411),
MAKE_REG(P0_TX_PDELAY_REQ_SEQ_ID, 0x6412),
MAKE_REG(P0_TX_PDELAY_RESP_SEQ_ID, 0x6413),
MAKE_REG(P0_RX_SYNC_SEQ_ID, 0x6414),
MAKE_REG(P0_RX_DELAY_REQ_SEQ_ID, 0x6415),
MAKE_REG(P0_RX_PDELAY_REQ_SEQ_ID, 0x6416),
MAKE_REG(P0_RX_PDELAY_RESP_SEQ_ID, 0x6417),
MAKE_REG(P0_PORT_NSEC_15_0, 0x6418),
MAKE_REG(P0_PORT_NSEC_26_16, 0x6419),
MAKE_REG(P0_PORT_SEC_15_0, 0x641a),
MAKE_REG(P0_PORT_SEC_31_16, 0x641b),
MAKE_REG(P0_EAV_CFG, 0x641c),
MAKE_REG(P1_TX_SYNC_SEQ_ID, 0x6420),
MAKE_REG(P1_TX_DELAY_REQ_SEQ_ID, 0x6421),
MAKE_REG(P1_TX_PDELAY_REQ_SEQ_ID, 0x6422),
MAKE_REG(P1_TX_PDELAY_RESP_SEQ_ID, 0x6423),
MAKE_REG(P1_RX_SYNC_SEQ_ID, 0x6424),
MAKE_REG(P1_RX_DELAY_REQ_SEQ_ID, 0x6425),
MAKE_REG(P1_RX_PDELAY_REQ_SEQ_ID, 0x6426),
MAKE_REG(P1_RX_PDELAY_RESP_SEQ_ID, 0x6427),
MAKE_REG(P1_PORT_NSEC_15_0, 0x6428),
MAKE_REG(P1_PORT_NSEC_26_16, 0x6429),
MAKE_REG(P1_PORT_SEC_15_0, 0x642a),
MAKE_REG(P1_PORT_SEC_31_16, 0x642b),
MAKE_REG(P1_EAV_CFG, 0x642c),
MAKE_REG(P2_TX_SYNC_SEQ_ID, 0x6430),
MAKE_REG(P2_TX_DELAY_REQ_SEQ_ID, 0x6431),
MAKE_REG(P2_TX_PDELAY_REQ_SEQ_ID, 0x6432),
MAKE_REG(P2_TX_PDELAY_RESP_SEQ_ID, 0x6433),
MAKE_REG(P2_RX_SYNC_SEQ_ID, 0x6434),
MAKE_REG(P2_RX_DELAY_REQ_SEQ_ID, 0x6435),
MAKE_REG(P2_RX_PDELAY_REQ_SEQ_ID, 0x6436),
MAKE_REG(P2_RX_PDELAY_RESP_SEQ_ID, 0x6437),
MAKE_REG(P2_PORT_NSEC_15_0, 0x6438),
MAKE_REG(P2_PORT_NSEC_26_16, 0x6439),
MAKE_REG(P2_PORT_SEC_15_0, 0x643a),
MAKE_REG(P2_PORT_SEC_31_16, 0x643b),
MAKE_REG(P2_EAV_CFG, 0x643c),
MAKE_REG(P3_TX_SYNC_SEQ_ID, 0x6440),
MAKE_REG(P3_TX_DELAY_REQ_SEQ_ID, 0x6441),
MAKE_REG(P3_TX_PDELAY_REQ_SEQ_ID, 0x6442),
MAKE_REG(P3_TX_PDELAY_RESP_SEQ_ID, 0x6443),
MAKE_REG(P3_RX_SYNC_SEQ_ID, 0x6444),
MAKE_REG(P3_RX_DELAY_REQ_SEQ_ID, 0x6445),
MAKE_REG(P3_RX_PDELAY_REQ_SEQ_ID, 0x6446),
MAKE_REG(P3_RX_PDELAY_RESP_SEQ_ID, 0x6447),
MAKE_REG(P3_PORT_NSEC_15_0, 0x6448),
MAKE_REG(P3_PORT_NSEC_26_16, 0x6449),
MAKE_REG(P3_PORT_SEC_15_0, 0x644a),
MAKE_REG(P3_PORT_SEC_31_16, 0x644b),
MAKE_REG(P3_EAV_CFG, 0x644c),
MAKE_REG(P4_TX_SYNC_SEQ_ID, 0x6450),
MAKE_REG(P4_TX_DELAY_REQ_SEQ_ID, 0x6451),
MAKE_REG(P4_TX_PDELAY_REQ_SEQ_ID, 0x6452),
MAKE_REG(P4_TX_PDELAY_RESP_SEQ_ID, 0x6453),
MAKE_REG(P4_RX_SYNC_SEQ_ID, 0x6454),
MAKE_REG(P4_RX_DELAY_REQ_SEQ_ID, 0x6455),
MAKE_REG(P4_RX_PDELAY_REQ_SEQ_ID, 0x6456),
MAKE_REG(P4_RX_PDELAY_RESP_SEQ_ID, 0x6457),
MAKE_REG(P4_PORT_NSEC_15_0, 0x6458),
MAKE_REG(P4_PORT_NSEC_26_16, 0x6459),
MAKE_REG(P4_PORT_SEC_15_0, 0x645a),
MAKE_REG(P4_PORT_SEC_31_16, 0x645b),
MAKE_REG(P4_EAV_CFG, 0x645c),
MAKE_REG(P6_TX_SYNC_SEQ_ID, 0x6460),
MAKE_REG(P6_TX_DELAY_REQ_SEQ_ID, 0x6461),
MAKE_REG(P6_TX_PDELAY_REQ_SEQ_ID, 0x6462),
MAKE_REG(P6_TX_PDELAY_RESP_SEQ_ID, 0x6463),
MAKE_REG(P6_RX_SYNC_SEQ_ID, 0x6464),
MAKE_REG(P6_RX_DELAY_REQ_SEQ_ID, 0x6465),
MAKE_REG(P6_RX_PDELAY_REQ_SEQ_ID, 0x6466),
MAKE_REG(P6_RX_PDELAY_RESP_SEQ_ID, 0x6467),
MAKE_REG(P6_PORT_NSEC_15_0, 0x6468),
MAKE_REG(P6_PORT_NSEC_26_16, 0x6469),
MAKE_REG(P6_PORT_SEC_15_0, 0x646a),
MAKE_REG(P6_PORT_SEC_31_16, 0x646b),
MAKE_REG(P6_EAV_CFG, 0x646c),
MAKE_REG(P7_TX_SYNC_SEQ_ID, 0x6470),
MAKE_REG(P7_TX_DELAY_REQ_SEQ_ID, 0x6471),
MAKE_REG(P7_TX_PDELAY_REQ_SEQ_ID, 0x6472),
MAKE_REG(P7_TX_PDELAY_RESP_SEQ_ID, 0x6473),
MAKE_REG(P7_RX_SYNC_SEQ_ID, 0x6474),
MAKE_REG(P7_RX_DELAY_REQ_SEQ_ID, 0x6475),
MAKE_REG(P7_RX_PDELAY_REQ_SEQ_ID, 0x6476),
MAKE_REG(P7_RX_PDELAY_RESP_SEQ_ID, 0x6477),
MAKE_REG(P7_PORT_NSEC_15_0, 0x6478),
MAKE_REG(P7_PORT_NSEC_26_16, 0x6479),
MAKE_REG(P7_PORT_SEC_15_0, 0x647a),
MAKE_REG(P7_PORT_SEC_31_16, 0x647b),
MAKE_REG(P7_EAV_CFG, 0x647c),
MAKE_REG(P5_TX_SYNC_SEQ_ID, 0x6480),
MAKE_REG(P5_TX_DELAY_REQ_SEQ_ID, 0x6481),
MAKE_REG(P5_TX_PDELAY_REQ_SEQ_ID, 0x6482),
MAKE_REG(P5_TX_PDELAY_RESP_SEQ_ID, 0x6483),
MAKE_REG(P5_RX_SYNC_SEQ_ID, 0x6484),
MAKE_REG(P5_RX_DELAY_REQ_SEQ_ID, 0x6485),
MAKE_REG(P5_RX_PDELAY_REQ_SEQ_ID, 0x6486),
MAKE_REG(P5_RX_PDELAY_RESP_SEQ_ID, 0x6487),
MAKE_REG(P5_PORT_NSEC_15_0, 0x6488),
MAKE_REG(P5_PORT_NSEC_26_16, 0x6489),
MAKE_REG(P5_PORT_SEC_15_0, 0x648a),
MAKE_REG(P5_PORT_SEC_31_16, 0x648b),
MAKE_REG(P5_EAV_CFG, 0x648c),
MAKE_REG(P8_TX_SYNC_SEQ_ID, 0x6490),
MAKE_REG(P8_TX_DELAY_REQ_SEQ_ID, 0x6491),
MAKE_REG(P8_TX_PDELAY_REQ_SEQ_ID, 0x6492),
MAKE_REG(P8_TX_PDELAY_RESP_SEQ_ID, 0x6493),
MAKE_REG(P8_RX_SYNC_SEQ_ID, 0x6494),
MAKE_REG(P8_RX_DELAY_REQ_SEQ_ID, 0x6495),
MAKE_REG(P8_RX_PDELAY_REQ_SEQ_ID, 0x6496),
MAKE_REG(P8_RX_PDELAY_RESP_SEQ_ID, 0x6497),
MAKE_REG(P8_PORT_NSEC_15_0, 0x6498),
MAKE_REG(P8_PORT_NSEC_26_16, 0x6499),
MAKE_REG(P8_PORT_SEC_15_0, 0x649a),
MAKE_REG(P8_PORT_SEC_31_16, 0x649b),
MAKE_REG(P8_EAV_CFG, 0x649c),
MAKE_REG(P9_TX_SYNC_SEQ_ID, 0x64a0),
MAKE_REG(P9_TX_DELAY_REQ_SEQ_ID, 0x64a1),
MAKE_REG(P9_TX_PDELAY_REQ_SEQ_ID, 0x64a2),
MAKE_REG(P9_TX_PDELAY_RESP_SEQ_ID, 0x64a3),
MAKE_REG(P9_RX_SYNC_SEQ_ID, 0x64a4),
MAKE_REG(P9_RX_DELAY_REQ_SEQ_ID, 0x64a5),
MAKE_REG(P9_RX_PDELAY_REQ_SEQ_ID, 0x64a6),
MAKE_REG(P9_RX_PDELAY_RESP_SEQ_ID, 0x64a7),
MAKE_REG(P9_PORT_NSEC_15_0, 0x64a8),
MAKE_REG(P9_PORT_NSEC_26_16, 0x64a9),
MAKE_REG(P9_PORT_SEC_15_0, 0x64aa),
MAKE_REG(P9_PORT_SEC_31_16, 0x64ab),
MAKE_REG(P9_EAV_CFG, 0x64ac),
MAKE_REG(SDS_INDACS_CMD, 0x6600),
MAKE_REG(SDS_INDACS_ADR, 0x6601),
MAKE_REG(SDS_INDACS_DATA, 0x6602),
};

[-- Attachment #3: rtltest.c --]
[-- Type: text/plain, Size: 49654 bytes --]

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/spinlock.h>
#include <linux/skbuff.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_mdio.h>
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/bitops.h>
#include <linux/if_bridge.h>

#include "regs.h"

#define REALTEK_HW_STOP_DELAY		25	/* msecs */
#define REALTEK_HW_START_DELAY		100	/* msecs */

#define REALTEK_SMI_ACK_RETRY_COUNT		5

/* Chip-specific data and limits */
#define RTL8365MB_CHIP_ID_8365MB_VC	0x6367
#define RTL8365MB_CHIP_VER_8365MB_VC	0x0040

#define RTL8365MB_CHIP_ID_8367S		0x6367
#define RTL8365MB_CHIP_VER_8367S	0x00A0

#define RTL8365MB_CHIP_ID_8367RB	0x6367
#define RTL8365MB_CHIP_VER_8367RB	0x0020

/* Family-specific data and limits */
#define RTL8365MB_PHYADDRMAX		7
#define RTL8365MB_NUM_PHYREGS		32
#define RTL8365MB_PHYREGMAX		(RTL8365MB_NUM_PHYREGS - 1)
/* RTL8370MB and RTL8310SR, possibly suportable by this driver, have 10 ports */
#define RTL8365MB_MAX_NUM_PORTS		10
#define RTL8365MB_LEARN_LIMIT_MAX	2112

/* valid for all 6-port or less variants */
static const int rtl8365mb_extint_port_map[]  = { -1, -1, -1, -1, -1, -1, 1, 2, -1, -1};

/* Chip identification registers */
#define RTL8365MB_CHIP_ID_REG		0x1300

#define RTL8365MB_CHIP_VER_REG		0x1301

#define RTL8365MB_MAGIC_REG		0x13C2
#define   RTL8365MB_MAGIC_VALUE		0x0249

/* Chip reset register */
#define RTL8365MB_CHIP_RESET_REG	0x1322
#define RTL8365MB_CHIP_RESET_SW_MASK	0x0002
#define RTL8365MB_CHIP_RESET_HW_MASK	0x0001

/* Interrupt polarity register */
#define RTL8365MB_INTR_POLARITY_REG	0x1100
#define   RTL8365MB_INTR_POLARITY_MASK	0x0001
#define   RTL8365MB_INTR_POLARITY_HIGH	0
#define   RTL8365MB_INTR_POLARITY_LOW	1

/* Interrupt control/status register - enable/check specific interrupt types */
#define RTL8365MB_INTR_CTRL_REG			0x1101
#define RTL8365MB_INTR_STATUS_REG		0x1102
#define   RTL8365MB_INTR_SLIENT_START_2_MASK	0x1000
#define   RTL8365MB_INTR_SLIENT_START_MASK	0x0800
#define   RTL8365MB_INTR_ACL_ACTION_MASK	0x0200
#define   RTL8365MB_INTR_CABLE_DIAG_FIN_MASK	0x0100
#define   RTL8365MB_INTR_INTERRUPT_8051_MASK	0x0080
#define   RTL8365MB_INTR_LOOP_DETECTION_MASK	0x0040
#define   RTL8365MB_INTR_GREEN_TIMER_MASK	0x0020
#define   RTL8365MB_INTR_SPECIAL_CONGEST_MASK	0x0010
#define   RTL8365MB_INTR_SPEED_CHANGE_MASK	0x0008
#define   RTL8365MB_INTR_LEARN_OVER_MASK	0x0004
#define   RTL8365MB_INTR_METER_EXCEEDED_MASK	0x0002
#define   RTL8365MB_INTR_LINK_CHANGE_MASK	0x0001
#define   RTL8365MB_INTR_ALL_MASK                      \
		(RTL8365MB_INTR_SLIENT_START_2_MASK |  \
		 RTL8365MB_INTR_SLIENT_START_MASK |    \
		 RTL8365MB_INTR_ACL_ACTION_MASK |      \
		 RTL8365MB_INTR_CABLE_DIAG_FIN_MASK |  \
		 RTL8365MB_INTR_INTERRUPT_8051_MASK |  \
		 RTL8365MB_INTR_LOOP_DETECTION_MASK |  \
		 RTL8365MB_INTR_GREEN_TIMER_MASK |     \
		 RTL8365MB_INTR_SPECIAL_CONGEST_MASK | \
		 RTL8365MB_INTR_SPEED_CHANGE_MASK |    \
		 RTL8365MB_INTR_LEARN_OVER_MASK |      \
		 RTL8365MB_INTR_METER_EXCEEDED_MASK |  \
		 RTL8365MB_INTR_LINK_CHANGE_MASK)

/* Per-port interrupt type status registers */
#define RTL8365MB_PORT_LINKDOWN_IND_REG		0x1106
#define   RTL8365MB_PORT_LINKDOWN_IND_MASK	0x07FF

#define RTL8365MB_PORT_LINKUP_IND_REG		0x1107
#define   RTL8365MB_PORT_LINKUP_IND_MASK	0x07FF

/* PHY indirect access registers */
#define RTL8365MB_INDIRECT_ACCESS_CTRL_REG			0x1F00
#define   RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK		0x0002
#define   RTL8365MB_INDIRECT_ACCESS_CTRL_RW_READ		0
#define   RTL8365MB_INDIRECT_ACCESS_CTRL_RW_WRITE		1
#define   RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK		0x0001
#define   RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE		1
#define RTL8365MB_INDIRECT_ACCESS_STATUS_REG			0x1F01
#define RTL8365MB_INDIRECT_ACCESS_ADDRESS_REG			0x1F02
#define   RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_5_1_MASK	GENMASK(4, 0)
#define   RTL8365MB_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK		GENMASK(7, 5)
#define   RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK	GENMASK(11, 8)
#define   RTL8365MB_PHY_BASE					0x2000
#define RTL8365MB_INDIRECT_ACCESS_WRITE_DATA_REG		0x1F03
#define RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG			0x1F04

/* PHY OCP address prefix register */
#define RTL8365MB_GPHY_OCP_MSB_0_REG			0x1D15
#define   RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK	0x0FC0
#define RTL8365MB_PHY_OCP_ADDR_PREFIX_MASK		0xFC00

/* The PHY OCP addresses of PHY registers 0~31 start here */
#define RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE		0xA400

/* EXT interface port mode values - used in DIGITAL_INTERFACE_SELECT */
#define RTL8365MB_EXT_PORT_MODE_DISABLE		0
#define RTL8365MB_EXT_PORT_MODE_RGMII		1
#define RTL8365MB_EXT_PORT_MODE_MII_MAC		2
#define RTL8365MB_EXT_PORT_MODE_MII_PHY		3
#define RTL8365MB_EXT_PORT_MODE_TMII_MAC	4
#define RTL8365MB_EXT_PORT_MODE_TMII_PHY	5
#define RTL8365MB_EXT_PORT_MODE_GMII		6
#define RTL8365MB_EXT_PORT_MODE_RMII_MAC	7
#define RTL8365MB_EXT_PORT_MODE_RMII_PHY	8
#define RTL8365MB_EXT_PORT_MODE_SGMII		9
#define RTL8365MB_EXT_PORT_MODE_HSGMII		10
#define RTL8365MB_EXT_PORT_MODE_1000X_100FX	11
#define RTL8365MB_EXT_PORT_MODE_1000X		12
#define RTL8365MB_EXT_PORT_MODE_100FX		13

/* Realtek docs and driver uses logic number as EXT_PORT0=16, EXT_PORT1=17,
 * EXT_PORT2=18, to interact with switch ports. That logic number is internally
 * converted to either a physical port number (0..9) or an external interface id (0..2),
 * depending on which function was called. The external interface id is calculated as
 * (ext_id=logic_port-15), while the logical to physical map depends on the chip id/version.
 *
 * EXT_PORT0 mentioned in datasheets and rtl8367c driver is used in this driver
 * as extid==1, EXT_PORT2, mentioned in Realtek rtl8367c driver for 10-port switches,
 * would have an ext_id of 3 (out of range for most extint macros) and ext_id 0 does
 * not seem to be used as well for this family.
 */

/* EXT interface mode configuration registers 0~1 */
#define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG0		0x1305 /* EXT1 */
#define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG1		0x13C3 /* EXT2 */
#define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(_extint) \
		((_extint) == 1 ? RTL8365MB_DIGITAL_INTERFACE_SELECT_REG0 : \
		 (_extint) == 2 ? RTL8365MB_DIGITAL_INTERFACE_SELECT_REG1 : \
		 0x0)
#define   RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(_extint) \
		(0xF << (((_extint) % 2)))
#define   RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_OFFSET(_extint) \
		(((_extint) % 2) * 4)

/* EXT interface RGMII TX/RX delay configuration registers 0~2 */
#define RTL8365MB_EXT_RGMXF_REG0		0x1306 /* EXT0 */
#define RTL8365MB_EXT_RGMXF_REG1		0x1307 /* EXT1 */
#define RTL8365MB_EXT_RGMXF_REG2		0x13C5 /* EXT2 */
#define RTL8365MB_EXT_RGMXF_REG(_extint) \
		((_extint) == 0 ? RTL8365MB_EXT_RGMXF_REG0 : \
		 (_extint) == 1 ? RTL8365MB_EXT_RGMXF_REG1 : \
		 (_extint) == 2 ? RTL8365MB_EXT_RGMXF_REG2 : \
		 0x0)
#define   RTL8365MB_EXT_RGMXF_RXDELAY_MASK	0x0007
#define   RTL8365MB_EXT_RGMXF_TXDELAY_MASK	0x0008

/* External interface port speed values - used in DIGITAL_INTERFACE_FORCE */
#define RTL8365MB_PORT_SPEED_10M	0
#define RTL8365MB_PORT_SPEED_100M	1
#define RTL8365MB_PORT_SPEED_1000M	2

/* EXT interface force configuration registers 0~2 */
#define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG0		0x1310 /* EXT0 */
#define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG1		0x1311 /* EXT1 */
#define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG2		0x13C4 /* EXT2 */
#define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG(_extint) \
		((_extint) == 0 ? RTL8365MB_DIGITAL_INTERFACE_FORCE_REG0 : \
		 (_extint) == 1 ? RTL8365MB_DIGITAL_INTERFACE_FORCE_REG1 : \
		 (_extint) == 2 ? RTL8365MB_DIGITAL_INTERFACE_FORCE_REG2 : \
		 0x0)
#define   RTL8365MB_DIGITAL_INTERFACE_FORCE_EN_MASK		0x1000
#define   RTL8365MB_DIGITAL_INTERFACE_FORCE_NWAY_MASK		0x0080
#define   RTL8365MB_DIGITAL_INTERFACE_FORCE_TXPAUSE_MASK	0x0040
#define   RTL8365MB_DIGITAL_INTERFACE_FORCE_RXPAUSE_MASK	0x0020
#define   RTL8365MB_DIGITAL_INTERFACE_FORCE_LINK_MASK		0x0010
#define   RTL8365MB_DIGITAL_INTERFACE_FORCE_DUPLEX_MASK		0x0004
#define   RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK		0x0003

/* CPU port mask register - controls which ports are treated as CPU ports */
#define RTL8365MB_CPU_PORT_MASK_REG	0x1219
#define   RTL8365MB_CPU_PORT_MASK_MASK	0x07FF

/* CPU control register */
#define RTL8365MB_CPU_CTRL_REG			0x121A
#define   RTL8365MB_CPU_CTRL_TRAP_PORT_EXT_MASK	0x0400
#define   RTL8365MB_CPU_CTRL_TAG_FORMAT_MASK	0x0200
#define   RTL8365MB_CPU_CTRL_RXBYTECOUNT_MASK	0x0080
#define   RTL8365MB_CPU_CTRL_TAG_POSITION_MASK	0x0040
#define   RTL8365MB_CPU_CTRL_TRAP_PORT_MASK	0x0038
#define   RTL8365MB_CPU_CTRL_INSERTMODE_MASK	0x0006
#define   RTL8365MB_CPU_CTRL_EN_MASK		0x0001

/* Maximum packet length register */
#define RTL8365MB_CFG0_MAX_LEN_REG	0x088C
#define   RTL8365MB_CFG0_MAX_LEN_MASK	0x3FFF

/* Port learning limit registers */
#define RTL8365MB_LUT_PORT_LEARN_LIMIT_BASE		0x0A20
#define RTL8365MB_LUT_PORT_LEARN_LIMIT_REG(_physport) \
		(RTL8365MB_LUT_PORT_LEARN_LIMIT_BASE + (_physport))

/* Port isolation (forwarding mask) registers */
#define RTL8365MB_PORT_ISOLATION_REG_BASE		0x08A2
#define RTL8365MB_PORT_ISOLATION_REG(_physport) \
		(RTL8365MB_PORT_ISOLATION_REG_BASE + (_physport))
#define   RTL8365MB_PORT_ISOLATION_MASK			0x07FF

/* MSTP port state registers - indexed by tree instance */
#define RTL8365MB_MSTI_CTRL_BASE			0x0A00
#define RTL8365MB_MSTI_CTRL_REG(_msti, _physport) \
		(RTL8365MB_MSTI_CTRL_BASE + ((_msti) << 1) + ((_physport) >> 3))
#define   RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET(_physport) ((_physport) << 1)
#define   RTL8365MB_MSTI_CTRL_PORT_STATE_MASK(_physport) \
		(0x3 << RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET((_physport)))

/* MIB counter value registers */
#define RTL8365MB_MIB_COUNTER_BASE	0x1000
#define RTL8365MB_MIB_COUNTER_REG(_x)	(RTL8365MB_MIB_COUNTER_BASE + (_x))

/* MIB counter address register */
#define RTL8365MB_MIB_ADDRESS_REG		0x1004
#define   RTL8365MB_MIB_ADDRESS_PORT_OFFSET	0x007C
#define   RTL8365MB_MIB_ADDRESS(_p, _x) \
		(((RTL8365MB_MIB_ADDRESS_PORT_OFFSET) * (_p) + (_x)) >> 2)

#define RTL8365MB_MIB_CTRL0_REG			0x1005
#define   RTL8365MB_MIB_CTRL0_RESET_MASK	0x0002
#define   RTL8365MB_MIB_CTRL0_BUSY_MASK		0x0001

/* The DSA callback .get_stats64 runs in atomic context, so we are not allowed
 * to block. On the other hand, accessing MIB counters absolutely requires us to
 * block. The solution is thus to schedule work which polls the MIB counters
 * asynchronously and updates some private data, which the callback can then
 * fetch atomically. Three seconds should be a good enough polling interval.
 */
#define RTL8365MB_STATS_INTERVAL_JIFFIES	(3 * HZ)

enum rtl8365mb_mib_counter_index {
	RTL8365MB_MIB_ifInOctets,
	RTL8365MB_MIB_dot3StatsFCSErrors,
	RTL8365MB_MIB_dot3StatsSymbolErrors,
	RTL8365MB_MIB_dot3InPauseFrames,
	RTL8365MB_MIB_dot3ControlInUnknownOpcodes,
	RTL8365MB_MIB_etherStatsFragments,
	RTL8365MB_MIB_etherStatsJabbers,
	RTL8365MB_MIB_ifInUcastPkts,
	RTL8365MB_MIB_etherStatsDropEvents,
	RTL8365MB_MIB_ifInMulticastPkts,
	RTL8365MB_MIB_ifInBroadcastPkts,
	RTL8365MB_MIB_inMldChecksumError,
	RTL8365MB_MIB_inIgmpChecksumError,
	RTL8365MB_MIB_inMldSpecificQuery,
	RTL8365MB_MIB_inMldGeneralQuery,
	RTL8365MB_MIB_inIgmpSpecificQuery,
	RTL8365MB_MIB_inIgmpGeneralQuery,
	RTL8365MB_MIB_inMldLeaves,
	RTL8365MB_MIB_inIgmpLeaves,
	RTL8365MB_MIB_etherStatsOctets,
	RTL8365MB_MIB_etherStatsUnderSizePkts,
	RTL8365MB_MIB_etherOversizeStats,
	RTL8365MB_MIB_etherStatsPkts64Octets,
	RTL8365MB_MIB_etherStatsPkts65to127Octets,
	RTL8365MB_MIB_etherStatsPkts128to255Octets,
	RTL8365MB_MIB_etherStatsPkts256to511Octets,
	RTL8365MB_MIB_etherStatsPkts512to1023Octets,
	RTL8365MB_MIB_etherStatsPkts1024to1518Octets,
	RTL8365MB_MIB_ifOutOctets,
	RTL8365MB_MIB_dot3StatsSingleCollisionFrames,
	RTL8365MB_MIB_dot3StatsMultipleCollisionFrames,
	RTL8365MB_MIB_dot3StatsDeferredTransmissions,
	RTL8365MB_MIB_dot3StatsLateCollisions,
	RTL8365MB_MIB_etherStatsCollisions,
	RTL8365MB_MIB_dot3StatsExcessiveCollisions,
	RTL8365MB_MIB_dot3OutPauseFrames,
	RTL8365MB_MIB_ifOutDiscards,
	RTL8365MB_MIB_dot1dTpPortInDiscards,
	RTL8365MB_MIB_ifOutUcastPkts,
	RTL8365MB_MIB_ifOutMulticastPkts,
	RTL8365MB_MIB_ifOutBroadcastPkts,
	RTL8365MB_MIB_outOampduPkts,
	RTL8365MB_MIB_inOampduPkts,
	RTL8365MB_MIB_inIgmpJoinsSuccess,
	RTL8365MB_MIB_inIgmpJoinsFail,
	RTL8365MB_MIB_inMldJoinsSuccess,
	RTL8365MB_MIB_inMldJoinsFail,
	RTL8365MB_MIB_inReportSuppressionDrop,
	RTL8365MB_MIB_inLeaveSuppressionDrop,
	RTL8365MB_MIB_outIgmpReports,
	RTL8365MB_MIB_outIgmpLeaves,
	RTL8365MB_MIB_outIgmpGeneralQuery,
	RTL8365MB_MIB_outIgmpSpecificQuery,
	RTL8365MB_MIB_outMldReports,
	RTL8365MB_MIB_outMldLeaves,
	RTL8365MB_MIB_outMldGeneralQuery,
	RTL8365MB_MIB_outMldSpecificQuery,
	RTL8365MB_MIB_inKnownMulticastPkts,
	RTL8365MB_MIB_END,
};

struct rtl8365mb_mib_counter {
	u32 offset;
	u32 length;
	const char *name;
};

#define RTL8365MB_MAKE_MIB_COUNTER(_offset, _length, _name) \
		[RTL8365MB_MIB_ ## _name] = { _offset, _length, #_name }

static struct rtl8365mb_mib_counter rtl8365mb_mib_counters[] = {
	RTL8365MB_MAKE_MIB_COUNTER(0, 4, ifInOctets),
	RTL8365MB_MAKE_MIB_COUNTER(4, 2, dot3StatsFCSErrors),
	RTL8365MB_MAKE_MIB_COUNTER(6, 2, dot3StatsSymbolErrors),
	RTL8365MB_MAKE_MIB_COUNTER(8, 2, dot3InPauseFrames),
	RTL8365MB_MAKE_MIB_COUNTER(10, 2, dot3ControlInUnknownOpcodes),
	RTL8365MB_MAKE_MIB_COUNTER(12, 2, etherStatsFragments),
	RTL8365MB_MAKE_MIB_COUNTER(14, 2, etherStatsJabbers),
	RTL8365MB_MAKE_MIB_COUNTER(16, 2, ifInUcastPkts),
	RTL8365MB_MAKE_MIB_COUNTER(18, 2, etherStatsDropEvents),
	RTL8365MB_MAKE_MIB_COUNTER(20, 2, ifInMulticastPkts),
	RTL8365MB_MAKE_MIB_COUNTER(22, 2, ifInBroadcastPkts),
	RTL8365MB_MAKE_MIB_COUNTER(24, 2, inMldChecksumError),
	RTL8365MB_MAKE_MIB_COUNTER(26, 2, inIgmpChecksumError),
	RTL8365MB_MAKE_MIB_COUNTER(28, 2, inMldSpecificQuery),
	RTL8365MB_MAKE_MIB_COUNTER(30, 2, inMldGeneralQuery),
	RTL8365MB_MAKE_MIB_COUNTER(32, 2, inIgmpSpecificQuery),
	RTL8365MB_MAKE_MIB_COUNTER(34, 2, inIgmpGeneralQuery),
	RTL8365MB_MAKE_MIB_COUNTER(36, 2, inMldLeaves),
	RTL8365MB_MAKE_MIB_COUNTER(38, 2, inIgmpLeaves),
	RTL8365MB_MAKE_MIB_COUNTER(40, 4, etherStatsOctets),
	RTL8365MB_MAKE_MIB_COUNTER(44, 2, etherStatsUnderSizePkts),
	RTL8365MB_MAKE_MIB_COUNTER(46, 2, etherOversizeStats),
	RTL8365MB_MAKE_MIB_COUNTER(48, 2, etherStatsPkts64Octets),
	RTL8365MB_MAKE_MIB_COUNTER(50, 2, etherStatsPkts65to127Octets),
	RTL8365MB_MAKE_MIB_COUNTER(52, 2, etherStatsPkts128to255Octets),
	RTL8365MB_MAKE_MIB_COUNTER(54, 2, etherStatsPkts256to511Octets),
	RTL8365MB_MAKE_MIB_COUNTER(56, 2, etherStatsPkts512to1023Octets),
	RTL8365MB_MAKE_MIB_COUNTER(58, 2, etherStatsPkts1024to1518Octets),
	RTL8365MB_MAKE_MIB_COUNTER(60, 4, ifOutOctets),
	RTL8365MB_MAKE_MIB_COUNTER(64, 2, dot3StatsSingleCollisionFrames),
	RTL8365MB_MAKE_MIB_COUNTER(66, 2, dot3StatsMultipleCollisionFrames),
	RTL8365MB_MAKE_MIB_COUNTER(68, 2, dot3StatsDeferredTransmissions),
	RTL8365MB_MAKE_MIB_COUNTER(70, 2, dot3StatsLateCollisions),
	RTL8365MB_MAKE_MIB_COUNTER(72, 2, etherStatsCollisions),
	RTL8365MB_MAKE_MIB_COUNTER(74, 2, dot3StatsExcessiveCollisions),
	RTL8365MB_MAKE_MIB_COUNTER(76, 2, dot3OutPauseFrames),
	RTL8365MB_MAKE_MIB_COUNTER(78, 2, ifOutDiscards),
	RTL8365MB_MAKE_MIB_COUNTER(80, 2, dot1dTpPortInDiscards),
	RTL8365MB_MAKE_MIB_COUNTER(82, 2, ifOutUcastPkts),
	RTL8365MB_MAKE_MIB_COUNTER(84, 2, ifOutMulticastPkts),
	RTL8365MB_MAKE_MIB_COUNTER(86, 2, ifOutBroadcastPkts),
	RTL8365MB_MAKE_MIB_COUNTER(88, 2, outOampduPkts),
	RTL8365MB_MAKE_MIB_COUNTER(90, 2, inOampduPkts),
	RTL8365MB_MAKE_MIB_COUNTER(92, 4, inIgmpJoinsSuccess),
	RTL8365MB_MAKE_MIB_COUNTER(96, 2, inIgmpJoinsFail),
	RTL8365MB_MAKE_MIB_COUNTER(98, 2, inMldJoinsSuccess),
	RTL8365MB_MAKE_MIB_COUNTER(100, 2, inMldJoinsFail),
	RTL8365MB_MAKE_MIB_COUNTER(102, 2, inReportSuppressionDrop),
	RTL8365MB_MAKE_MIB_COUNTER(104, 2, inLeaveSuppressionDrop),
	RTL8365MB_MAKE_MIB_COUNTER(106, 2, outIgmpReports),
	RTL8365MB_MAKE_MIB_COUNTER(108, 2, outIgmpLeaves),
	RTL8365MB_MAKE_MIB_COUNTER(110, 2, outIgmpGeneralQuery),
	RTL8365MB_MAKE_MIB_COUNTER(112, 2, outIgmpSpecificQuery),
	RTL8365MB_MAKE_MIB_COUNTER(114, 2, outMldReports),
	RTL8365MB_MAKE_MIB_COUNTER(116, 2, outMldLeaves),
	RTL8365MB_MAKE_MIB_COUNTER(118, 2, outMldGeneralQuery),
	RTL8365MB_MAKE_MIB_COUNTER(120, 2, outMldSpecificQuery),
	RTL8365MB_MAKE_MIB_COUNTER(122, 2, inKnownMulticastPkts),
};

static_assert(ARRAY_SIZE(rtl8365mb_mib_counters) == RTL8365MB_MIB_END);

struct rtl8365mb_jam_tbl_entry {
	u16 reg;
	u16 val;
};

/* Lifted from the vendor driver sources */
static const struct rtl8365mb_jam_tbl_entry rtl8365mb_init_jam_8365mb_vc[] = {
	{ 0x13EB, 0x15BB }, { 0x1303, 0x06D6 }, { 0x1304, 0x0700 },
	{ 0x13E2, 0x003F }, { 0x13F9, 0x0090 }, { 0x121E, 0x03CA },
	{ 0x1233, 0x0352 }, { 0x1237, 0x00A0 }, { 0x123A, 0x0030 },
	{ 0x1239, 0x0084 }, { 0x0301, 0x1000 }, { 0x1349, 0x001F },
	{ 0x18E0, 0x4004 }, { 0x122B, 0x241C }, { 0x1305, 0xC000 },
	{ 0x13F0, 0x0000 },
};

static const struct rtl8365mb_jam_tbl_entry rtl8365mb_init_jam_common[] = {
	{ 0x1200, 0x7FCB }, { 0x0884, 0x0003 }, { 0x06EB, 0x0001 },
	{ 0x03Fa, 0x0007 }, { 0x08C8, 0x00C0 }, { 0x0A30, 0x020E },
	{ 0x0800, 0x0000 }, { 0x0802, 0x0000 }, { 0x09DA, 0x0013 },
	{ 0x1D32, 0x0002 },
};


struct realtek_priv {
	struct device		*dev;
	struct gpio_desc	*reset;
	struct gpio_desc	*mdc;
	struct gpio_desc	*mdio;
	struct regmap		*map;
	struct regmap		*map_nolock;
	struct mutex		map_lock;
	u32 r_crossread;
	u32 r_crosswrite;
	u32 w_crossread;
	u32 w_crosswrite;
	u32 read_reg;
	u32 last_write;
	struct delayed_work work;

	unsigned int		clk_delay;
	u8			cmd_read;
	u8			cmd_write;
	spinlock_t		lock; /* Locks around command writes */
};



static inline void realtek_smi_clk_delay(struct realtek_priv *priv)
{
	ndelay(priv->clk_delay);
}

static void realtek_smi_start(struct realtek_priv *priv)
{
	/* Set GPIO pins to output mode, with initial state:
	 * SCK = 0, SDA = 1
	 */
	gpiod_direction_output(priv->mdc, 0);
	gpiod_direction_output(priv->mdio, 1);
	realtek_smi_clk_delay(priv);

	/* CLK 1: 0 -> 1, 1 -> 0 */
	gpiod_set_value(priv->mdc, 1);
	realtek_smi_clk_delay(priv);
	gpiod_set_value(priv->mdc, 0);
	realtek_smi_clk_delay(priv);

	/* CLK 2: */
	gpiod_set_value(priv->mdc, 1);
	realtek_smi_clk_delay(priv);
	gpiod_set_value(priv->mdio, 0);
	realtek_smi_clk_delay(priv);
	gpiod_set_value(priv->mdc, 0);
	realtek_smi_clk_delay(priv);
	gpiod_set_value(priv->mdio, 1);
}

static void realtek_smi_stop(struct realtek_priv *priv)
{
	realtek_smi_clk_delay(priv);
	gpiod_set_value(priv->mdio, 0);
	gpiod_set_value(priv->mdc, 1);
	realtek_smi_clk_delay(priv);
	gpiod_set_value(priv->mdio, 1);
	realtek_smi_clk_delay(priv);
	gpiod_set_value(priv->mdc, 1);
	realtek_smi_clk_delay(priv);
	gpiod_set_value(priv->mdc, 0);
	realtek_smi_clk_delay(priv);
	gpiod_set_value(priv->mdc, 1);

	/* Add a click */
	realtek_smi_clk_delay(priv);
	gpiod_set_value(priv->mdc, 0);
	realtek_smi_clk_delay(priv);
	gpiod_set_value(priv->mdc, 1);

	/* Set GPIO pins to input mode */
	gpiod_direction_input(priv->mdio);
	gpiod_direction_input(priv->mdc);
}

static void realtek_smi_write_bits(struct realtek_priv *priv, u32 data, u32 len)
{
	for (; len > 0; len--) {
		realtek_smi_clk_delay(priv);

		/* Prepare data */
		gpiod_set_value(priv->mdio, !!(data & (1 << (len - 1))));
		realtek_smi_clk_delay(priv);

		/* Clocking */
		gpiod_set_value(priv->mdc, 1);
		realtek_smi_clk_delay(priv);
		gpiod_set_value(priv->mdc, 0);
	}
}

static void realtek_smi_read_bits(struct realtek_priv *priv, u32 len, u32 *data)
{
	gpiod_direction_input(priv->mdio);

	for (*data = 0; len > 0; len--) {
		u32 u;

		realtek_smi_clk_delay(priv);

		/* Clocking */
		gpiod_set_value(priv->mdc, 1);
		realtek_smi_clk_delay(priv);
		u = !!gpiod_get_value(priv->mdio);
		gpiod_set_value(priv->mdc, 0);

		*data |= (u << (len - 1));
	}

	gpiod_direction_output(priv->mdio, 0);
}

static int realtek_smi_wait_for_ack(struct realtek_priv *priv)
{
	int retry_cnt;

	retry_cnt = 0;
	do {
		u32 ack;

		realtek_smi_read_bits(priv, 1, &ack);
		if (ack == 0)
			break;

		if (++retry_cnt > REALTEK_SMI_ACK_RETRY_COUNT) {
			dev_err(priv->dev, "ACK timeout\n");
			return -ETIMEDOUT;
		}
	} while (1);

	return 0;
}

static int realtek_smi_write_byte(struct realtek_priv *priv, u8 data)
{
	realtek_smi_write_bits(priv, data, 8);
	return realtek_smi_wait_for_ack(priv);
}

static int realtek_smi_write_byte_noack(struct realtek_priv *priv, u8 data)
{
	realtek_smi_write_bits(priv, data, 8);
	return 0;
}

static int realtek_smi_read_byte0(struct realtek_priv *priv, u8 *data)
{
	u32 t;

	/* Read data */
	realtek_smi_read_bits(priv, 8, &t);
	*data = (t & 0xff);

	/* Send an ACK */
	realtek_smi_write_bits(priv, 0x00, 1);

	return 0;
}

static int realtek_smi_read_byte1(struct realtek_priv *priv, u8 *data)
{
	u32 t;

	/* Read data */
	realtek_smi_read_bits(priv, 8, &t);
	*data = (t & 0xff);

	/* Send an ACK */
	realtek_smi_write_bits(priv, 0x01, 1);

	return 0;
}

static int realtek_smi_read_reg(struct realtek_priv *priv, u32 addr, u32 *data)
{
	unsigned long flags;
	u8 lo = 0;
	u8 hi = 0;
	int ret;

	spin_lock_irqsave(&priv->lock, flags);

	realtek_smi_start(priv);

	/* Send READ command */
	ret = realtek_smi_write_byte(priv, priv->cmd_read);
	if (ret)
		goto out;

	/* Set ADDR[7:0] */
	ret = realtek_smi_write_byte(priv, addr & 0xff);
	if (ret)
		goto out;

	/* Set ADDR[15:8] */
	ret = realtek_smi_write_byte(priv, addr >> 8);
	if (ret)
		goto out;

	/* Read DATA[7:0] */
	realtek_smi_read_byte0(priv, &lo);
	/* Read DATA[15:8] */
	realtek_smi_read_byte1(priv, &hi);

	*data = ((u32)lo) | (((u32)hi) << 8);

	ret = 0;

 out:
	realtek_smi_stop(priv);
	spin_unlock_irqrestore(&priv->lock, flags);

	return ret;
}

static int realtek_smi_write_reg(struct realtek_priv *priv,
				 u32 addr, u32 data, bool ack)
{
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&priv->lock, flags);

	realtek_smi_start(priv);

	/* Send WRITE command */
	ret = realtek_smi_write_byte(priv, priv->cmd_write);
	if (ret)
		goto out;

	/* Set ADDR[7:0] */
	ret = realtek_smi_write_byte(priv, addr & 0xff);
	if (ret)
		goto out;

	/* Set ADDR[15:8] */
	ret = realtek_smi_write_byte(priv, addr >> 8);
	if (ret)
		goto out;

	/* Write DATA[7:0] */
	ret = realtek_smi_write_byte(priv, data & 0xff);
	if (ret)
		goto out;

	/* Write DATA[15:8] */
	if (ack)
		ret = realtek_smi_write_byte(priv, data >> 8);
	else
		ret = realtek_smi_write_byte_noack(priv, data >> 8);
	if (ret)
		goto out;

	ret = 0;

 out:
	realtek_smi_stop(priv);
	spin_unlock_irqrestore(&priv->lock, flags);

	return ret;
}

/* There is one single case when we need to use this accessor and that
 * is when issueing soft reset. Since the device reset as soon as we write
 * that bit, no ACK will come back for natural reasons.
 */
static int realtek_smi_write_reg_noack(void *ctx, u32 reg, u32 val)
{
	return realtek_smi_write_reg(ctx, reg, val, false);
}

/* Regmap accessors */

static int realtek_smi_write(void *ctx, u32 reg, u32 val)
{
	struct realtek_priv *priv = ctx;

	return realtek_smi_write_reg(priv, reg, val, true);
}

static int realtek_smi_read(void *ctx, u32 reg, u32 *val)
{
	struct realtek_priv *priv = ctx;

	return realtek_smi_read_reg(priv, reg, val);
}

static void realtek_smi_lock(void *ctx)
{
	struct realtek_priv *priv = ctx;

	mutex_lock(&priv->map_lock);
}

static void realtek_smi_unlock(void *ctx)
{
	struct realtek_priv *priv = ctx;

	mutex_unlock(&priv->map_lock);
}

static const struct regmap_config realtek_smi_regmap_config = {
	.reg_bits = 10, /* A4..A0 R4..R0 */
	.val_bits = 16,
	.reg_stride = 1,
	/* PHY regs are at 0x8000 */
	.max_register = 0xffff,
	.reg_format_endian = REGMAP_ENDIAN_BIG,
	.reg_read = realtek_smi_read,
	.reg_write = realtek_smi_write,
	.cache_type = REGCACHE_NONE,
	.lock = realtek_smi_lock,
	.unlock = realtek_smi_unlock,
};

static const struct regmap_config realtek_smi_nolock_regmap_config = {
	.reg_bits = 10, /* A4..A0 R4..R0 */
	.val_bits = 16,
	.reg_stride = 1,
	/* PHY regs are at 0x8000 */
	.max_register = 0xffff,
	.reg_format_endian = REGMAP_ENDIAN_BIG,
	.reg_read = realtek_smi_read,
	.reg_write = realtek_smi_write,
	.cache_type = REGCACHE_NONE,
	.disable_locking = true,
};

static u32 last_reg_read[RTL_REG_END] = {};
static bool bad_regs[RTL_REG_END] = {};

static void check_good_regs(struct realtek_priv *priv)
{
	struct device *dev = priv->dev;
	int ret;
	int i;
	int n_checks = 30;
	int check = 0;
	int n_good_regs = RTL_REG_END;

	/* Check over every register we know of and see if its value
	is subject to change over n_checks. Note that some registers
	which are defined may be missing in the silicon, in which case
	reads will fail. Reads silently fail, however, and the value
	of the last successful read is simply returned. To avoid
	marking those registers as good - because they cause issues in
	later sanity checks otherwise - we alrenately read a different
	value from a known good register beforehand on each
	iteration. */
	for (check = 0; check < n_checks; check++) {
		/* This will set the CHIP_ID_REG return either 0 or
		non-0, so that we filter out non-existent regs whose
		read returns the value of the last successful read */
		if (check % 2) {
			regmap_write(priv->map, RTL8365MB_MAGIC_REG, RTL8365MB_MAGIC_VALUE);
		}
		else {
			regmap_write(priv->map, RTL8365MB_MAGIC_REG, 0);
		}
		
		for (i = 0; i < RTL_REG_END; i++) {
			u32 val;
			if (bad_regs[i])
				continue;

			/* read this reg - we alternate its value to
			avoid read failures showing up as good regs */
			regmap_read(priv->map, RTL8365MB_CHIP_ID_REG, &val);
			
			ret = regmap_read(priv->map, rtl_regs[i].addr, &val);
			if (ret) {
				dev_err(dev, "error reading reg %s (0x%04x): %d\n",
					rtl_regs[i].name, rtl_regs[i].addr, ret);
				break;
			}

			dev_dbg(dev, "reg %s (0x%04x) = 0x%04x\n",
				 rtl_regs[i].name, rtl_regs[i].addr, val);

			if (check != 0) {
				if (val != last_reg_read[i]) {
					dev_dbg(dev,
						"read mismatch: reg %s (0x%04x), old=0x%04x, new=0x%04x\n",
						rtl_regs[i].name,
						rtl_regs[i].addr,
						last_reg_read[i], val);
					bad_regs[i] = true;
					continue;
				}
			} else {
				last_reg_read[i] = val;
			}
		}

		msleep(100);
	}

	regmap_write(priv->map, RTL8365MB_MAGIC_REG, 0);
	regmap_read(priv->map, RTL8365MB_CHIP_ID_REG, &last_reg_read[RTL_REG_CHIP_NUMBER]);
	regmap_read(priv->map, RTL8365MB_MAGIC_REG, &last_reg_read[RTL_REG_MAGIC_ID]);
	bad_regs[RTL_REG_CHIP_NUMBER] = 0; /* we know it's good */
	bad_regs[RTL_REG_MAGIC_ID] = 0; /* we know it's good */

	for (i = 0; i < RTL_REG_END; i++) {
		if (bad_regs[i]) {
			n_good_regs--;
			dev_dbg(dev, "bad reg %s\n", rtl_regs[i].name);
		}
	}

	dev_err(dev, "n_good_regs = %d\n", n_good_regs);
	dev_err(dev, "n_bad_regs = %d\n", RTL_REG_END - n_good_regs);
}

/* Do we initiate a cross{read,write} during PHY READING or PHY WRITING? */
enum rw {
	READING,
	WRITING,
};

static int cross_read(struct realtek_priv *priv, u32 mask, enum rw rw)
{
	u32 val;
	int ret;
	
	if (rw == READING) {
		/* only read if enabled for reads */
		if (!(mask & priv->r_crossread))
			return 0;
	} else {
		/* only read if enabled for writes */
		if (!(mask & priv->w_crossread))
			return 0;
	}

	ret = regmap_read(priv->map, rtl_regs[priv->read_reg].addr, &val);
	if (ret) {
		dev_err(priv->dev, "crossread fail %s: %d\n",
			rtl_regs[priv->read_reg].name, ret);
		return ret;
	}

	/* Since we end up doing cross-reads during MIB access (to
	check it's OK), we can no longer assume that the values of
	these addresses will stay the same as what was initially read
	in check_good_regs */
	if (val != last_reg_read[priv->read_reg] &&
	    priv->read_reg != RTL_REG_MIB_ADDRESS &&
	    priv->read_reg != RTL_REG_MIB_CTRL0 &&
	    priv->read_reg != RTL_REG_MIB_COUNTER0 &&
	    priv->read_reg != RTL_REG_MIB_COUNTER1 &&
	    priv->read_reg != RTL_REG_MIB_COUNTER2 &&
	    priv->read_reg != RTL_REG_MIB_COUNTER3
	    ) {
		dev_err(priv->dev, "crossread mismatch %s: 0x%04x != 0x%04x\n",
			rtl_regs[priv->read_reg].name, val,
			last_reg_read[priv->read_reg]);
		return -1;
	}
	return 0;
}

/* Here, since we cannot assume that all registers will happily be
written to without side-effects, we use a simple well-known register
to write to. We alternate the value written each time. */
static int cross_write(struct realtek_priv *priv, u32 mask, enum rw rw)
{
	static int A_OR_B_WRITE = 0; /* flip between 0 and 1 to decide what to write */
	u32 wval;

	if (rw == READING) {
		/* only write if enabled for reads */
		if (!(mask & priv->r_crosswrite))
			return 0;
	} else {
		/* only write if enabled for writes */
		if (!(mask & priv->w_crosswrite))
			return 0;
	}

	if (A_OR_B_WRITE)
		wval = 0;
	else
		wval = RTL8365MB_MAGIC_VALUE;

	if (regmap_write(priv->map, RTL8365MB_MAGIC_REG, wval)) {
		dev_err(priv->dev, "crosswrite failed\n");
		return -1;
	}

	A_OR_B_WRITE = A_OR_B_WRITE ? 0 : 1;
	priv->last_write = wval;

	return 0;
}

#define CROSS_READ(n) if (cross_read(priv, BIT(n), READING)) return 0xFFFF;
#define CROSS_WRITE(n) if (cross_write(priv, BIT(n), READING)) return 0xFFFF;
#define W_CROSS_READ(n) if (cross_read(priv, BIT(n), WRITING)) return 0xFFFF;
#define W_CROSS_WRITE(n) if (cross_write(priv, BIT(n), WRITING)) return 0xFFFF;

static int rtl8365mb_mib_counter_read(struct realtek_priv *priv, int port,
				      u32 offset, u32 length, u64 *mibvalue)
{
	u64 tmpvalue = 0;
	u32 val;
	int ret;
	int i;

	/* The MIB address is an SRAM address. We request a particular address
	 * and then poll the control register before reading the value from some
	 * counter registers.
	 */
	ret = regmap_write(priv->map, RTL8365MB_MIB_ADDRESS_REG,
			   RTL8365MB_MIB_ADDRESS(port, offset));
	if (ret)
		return ret;

	CROSS_READ(0);
	CROSS_WRITE(0);

	/* Poll for completion */
	while (1) {
		CROSS_READ(1);
		CROSS_WRITE(1);
		regmap_read(priv->map, RTL8365MB_MIB_CTRL0_REG, &val);
		if (!(val & RTL8365MB_MIB_CTRL0_BUSY_MASK))
			break;
		udelay(10);
	}

	CROSS_READ(2);
	CROSS_WRITE(2);

	/* Presumably this indicates a MIB counter read failure */
	if (val & RTL8365MB_MIB_CTRL0_RESET_MASK)
		return -EIO;

	/* There are four MIB counter registers each holding a 16 bit word of a
	 * MIB counter. Depending on the offset, we should read from the upper
	 * two or lower two registers. In case the MIB counter is 4 words, we
	 * read from all four registers.
	 */
	if (length == 4)
		offset = 3;
	else
		offset = (offset + 1) % 4;

	/* Read the MIB counter 16 bits at a time */
	for (i = 0; i < length; i++) {
		CROSS_READ(3);
		CROSS_WRITE(3);

		ret = regmap_read(priv->map,
				  RTL8365MB_MIB_COUNTER_REG(offset - i), &val);
		if (ret)
			return ret;

		tmpvalue = ((tmpvalue) << 16) | (val & 0xFFFF);
	}

	/* Only commit the result if no error occurred */
	*mibvalue = tmpvalue;

	return 0;
}

/* Check MIB read at mibidx i is OK - crossreads/writes may occur but
the MIB counter should always return 0. */
static int _check_mib_read(struct realtek_priv *priv, int i)
{
	int ret;
	int port = 0; /* NOTE: hardcoded and assume counters always 0 */
	u64 val;

	struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i];

	ret = rtl8365mb_mib_counter_read(priv, port, mib->offset,
						mib->length, &val);
	if (ret) {
		dev_err(priv->dev,
			"failed to read port %d counters: %d\n", port,
			ret);
		return -1;
	}

	if (val) {
		dev_err(priv->dev,
			"mib counter not 0! %llu\n", val);
		return -1;
	}

	return 0;
}

/* For each register check if reading it at some point during a MIB
read will cause a MIB read failure. Every MIB counter is checked.
Likewise for writing to a register during a MIB read, although here we
only check once because of how the crosswrite is implemented. */
static int check_mib_read(struct realtek_priv *priv)
{
	int mibidx;
	int bit;
	u32 reg;

	for (reg = 0; reg < RTL_REG_END; reg++) {
		if (bad_regs[reg]) continue;

		for (bit = 0; bit < 4; bit++) {
			priv->r_crossread = BIT(bit);
			priv->read_reg = reg;
			
			for (mibidx = 0; mibidx < RTL8365MB_MIB_END; mibidx++) {
				if (_check_mib_read(priv, mibidx))
					return -1;
			}
		}
		priv->r_crossread = 0;
	}

	for (bit = 0; bit < 4; bit++) {
		priv->r_crosswrite = BIT(bit);

		for (mibidx = 0; mibidx < RTL8365MB_MIB_END; mibidx++) {
			if (_check_mib_read(priv, mibidx))
				return -1;
		}
	}
	priv->r_crosswrite = 0;

	return 0;
}

static int rtl8365mb_phy_poll_busy(struct realtek_priv *priv)
{
	u32 val;

	return regmap_read_poll_timeout(priv->map,
					RTL8365MB_INDIRECT_ACCESS_STATUS_REG,
					val, !val, 10, 100);
}

static int rtl8365mb_phy_ocp_prepare(struct realtek_priv *priv, int phy,
				     u32 ocp_addr)
{
	u32 val;
	int ret;

	/* Set OCP prefix */
	val = FIELD_GET(RTL8365MB_PHY_OCP_ADDR_PREFIX_MASK, ocp_addr);
	ret = regmap_update_bits(
		priv->map, RTL8365MB_GPHY_OCP_MSB_0_REG,
		RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK,
		FIELD_PREP(RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK, val));
	if (ret)
		return ret;

	CROSS_READ(0);
	CROSS_WRITE(0);

	/* Set PHY register address */
	val = RTL8365MB_PHY_BASE;
	val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK, phy);
	val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_5_1_MASK,
			  (ocp_addr >> 1)&GENMASK(4,0));
	val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK,
			  (ocp_addr >> 6)&GENMASK(3,0));
	ret = regmap_write(priv->map, RTL8365MB_INDIRECT_ACCESS_ADDRESS_REG,
			   val);
	if (ret)
		return ret;

	return 0;
}

/* version for phy_write */
static int W_rtl8365mb_phy_ocp_prepare(struct realtek_priv *priv, int phy,
				     u32 ocp_addr)
{
	u32 val;
	int ret;

	/* Set OCP prefix */
	val = FIELD_GET(RTL8365MB_PHY_OCP_ADDR_PREFIX_MASK, ocp_addr);
	ret = regmap_update_bits(
		priv->map, RTL8365MB_GPHY_OCP_MSB_0_REG,
		RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK,
		FIELD_PREP(RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK, val));
	if (ret)
		return ret;

	W_CROSS_READ(0);
	W_CROSS_WRITE(0);

	/* Set PHY register address */
	val = RTL8365MB_PHY_BASE;
	val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK, phy);
	val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_5_1_MASK,
			  (ocp_addr >> 1)&GENMASK(4,0));
	val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK,
			  (ocp_addr >> 6)&GENMASK(3,0));
	ret = regmap_write(priv->map, RTL8365MB_INDIRECT_ACCESS_ADDRESS_REG,
			   val);
	if (ret)
		return ret;

	return 0;
}


static int rtl8365mb_phy_ocp_read(struct realtek_priv *priv, int phy,
				  u32 ocp_addr, u16 *data)
{
	u32 val;
	int ret;

	CROSS_READ(1);
	CROSS_WRITE(1);

	ret = rtl8365mb_phy_poll_busy(priv);
	if (ret)
		goto out;

	CROSS_READ(2);
	CROSS_WRITE(2);

	ret = rtl8365mb_phy_ocp_prepare(priv, phy, ocp_addr);
	if (ret)
		goto out;

	CROSS_READ(3);
	CROSS_WRITE(3);

	/* Execute read operation */
	val = FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK,
			 RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE) |
	      FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK,
			 RTL8365MB_INDIRECT_ACCESS_CTRL_RW_READ);
	ret = regmap_write(priv->map, RTL8365MB_INDIRECT_ACCESS_CTRL_REG,
			   val);
	if (ret)
		goto out;

	CROSS_READ(4); // XXX
	CROSS_WRITE(4); // XXX

	ret = rtl8365mb_phy_poll_busy(priv);
	if (ret)
		goto out;

	CROSS_READ(5); // XXX
	CROSS_WRITE(5); // XXX

	/* Get PHY register data */
	ret = regmap_read(priv->map,
			  RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG, &val);
	if (ret)
		goto out;

	*data = val & 0xFFFF;

out:

	return ret;
}

static int rtl8365mb_phy_ocp_write(struct realtek_priv *priv, int phy,
				   u32 ocp_addr, u16 data)
{
	u32 val;
	int ret;

	W_CROSS_READ(1);
	W_CROSS_WRITE(1);

	ret = rtl8365mb_phy_poll_busy(priv);
	if (ret)
		goto out;

	W_CROSS_READ(2);
	W_CROSS_WRITE(2);

	ret = W_rtl8365mb_phy_ocp_prepare(priv, phy, ocp_addr);
	if (ret)
		goto out;

	W_CROSS_READ(3);
	W_CROSS_WRITE(3);

	/* Set PHY register data */
	ret = regmap_write(priv->map,
			   RTL8365MB_INDIRECT_ACCESS_WRITE_DATA_REG, data);
	if (ret)
		goto out;

	W_CROSS_READ(4);
	W_CROSS_WRITE(4);

	/* Execute write operation */
	val = FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK,
			 RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE) |
	      FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK,
			 RTL8365MB_INDIRECT_ACCESS_CTRL_RW_WRITE);
	ret = regmap_write(priv->map, RTL8365MB_INDIRECT_ACCESS_CTRL_REG,
			   val);
	if (ret)
		goto out;

	W_CROSS_READ(5);
	W_CROSS_WRITE(5);

	ret = rtl8365mb_phy_poll_busy(priv);
	if (ret)
		goto out;

out:

	return 0;
}

static int rtl8365mb_phy_read(struct realtek_priv *priv, int phy, int regnum)
{
	u32 ocp_addr;
	u16 val;
	int ret;

	if (phy > RTL8365MB_PHYADDRMAX)
		return -EINVAL;

	if (regnum > RTL8365MB_PHYREGMAX)
		return -EINVAL;

	ocp_addr = RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE + regnum * 2;

	ret = rtl8365mb_phy_ocp_read(priv, phy, ocp_addr, &val);
	if (ret) {
		dev_err(priv->dev,
			"failed to read PHY%d reg %02x @ %04x, ret %d\n", phy,
			regnum, ocp_addr, ret);
		return ret;
	}

	dev_dbg(priv->dev, "read PHY%d register 0x%02x @ %04x, val <- %04x\n",
		phy, regnum, ocp_addr, val);

	return val;
}

static int rtl8365mb_phy_write(struct realtek_priv *priv, int phy, int regnum,
			       u16 val)
{
	u32 ocp_addr;
	int ret;

	if (phy > RTL8365MB_PHYADDRMAX)
		return -EINVAL;

	if (regnum > RTL8365MB_PHYREGMAX)
		return -EINVAL;

	ocp_addr = RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE + regnum * 2;

	ret = rtl8365mb_phy_ocp_write(priv, phy, ocp_addr, val);
	if (ret) {
		dev_err(priv->dev,
			"failed to write PHY%d reg %02x @ %04x, ret %d\n", phy,
			regnum, ocp_addr, ret);
		return ret;
	}

	dev_dbg(priv->dev, "write PHY%d register 0x%02x @ %04x, val -> %04x\n",
		phy, regnum, ocp_addr, val);

	return 0;
}

/* For register i, do a PHY read with each possible
crossread/crosswrite and check our hypotheses. */
static int check_phy_read(struct realtek_priv *priv, int phynum, u32 i)
{
	struct device *dev = priv->dev;
	int ret;
	u32 reg2;
	u32 reg3;
	u32 read_bit = 0;
	int read_bad[6] = {};
	int write_bad[6] = {};

	reg2 = rtl8365mb_phy_read(priv, phynum, 2);
	if (!reg2 || reg2 == 0xffff) {
		dev_err(dev, "reg2 read fail\n");
		return -1;
	}

	reg3 = rtl8365mb_phy_read(priv, phynum, 3);
	if (!reg3 || reg3 == 0xffff) {
		dev_err(dev, "reg3 read fail\n");
		return -1;
	}

	/* We expect the PHY ID regs to have these values */
	if (reg2 != 0x001c || reg3 != 0xc942) {
		dev_err(dev, "bad initial: reg2=0x%04x reg3=0x%04x\n",reg2,reg3);
		return -1;
	}

	/* check with crossreads */
	for (read_bit = 0; read_bit < 6; read_bit++) {
		u32 r2;
		u32 r3;
		priv->r_crossread = BIT(read_bit);
		priv->read_reg = i;
		r2 = rtl8365mb_phy_read(priv, phynum, 2);
		r3 = rtl8365mb_phy_read(priv, phynum, 3);
		if (r2 != reg2 || r3 != reg3) {
			read_bad[read_bit] = 1;
			/* In the event of failure, print an error if
			the hypothesis of a poisoned read does not
			hold. Poisoned read means the result of the
			crossread ends up being returned by the PHY
			read too. MIB regs are discounted because we
			manipulate them earlier without updating
			last_reg_read. */
			if (priv->read_reg != RTL_REG_MIB_ADDRESS &&
			    priv->read_reg != RTL_REG_MIB_CTRL0 &&
			    priv->read_reg != RTL_REG_MIB_COUNTER0 &&
			    priv->read_reg != RTL_REG_MIB_COUNTER1 &&
			    priv->read_reg != RTL_REG_MIB_COUNTER2 &&
			    priv->read_reg != RTL_REG_MIB_COUNTER3) {
				if (r2 != last_reg_read[priv->read_reg])
					dev_err(dev,
						"r2 = 0x%04x != 0x%04x(swreg read %s)\n",
						r2,
						last_reg_read[priv->read_reg],
						rtl_regs[priv->read_reg].name);
				if (r3 != last_reg_read[priv->read_reg])
					dev_err(dev,
						"r3 = 0x%04x != 0x%04x(swreg read %s)\n",
						r3,
						last_reg_read[priv->read_reg],
						rtl_regs[priv->read_reg].name);
			}
		}
	}
	priv->r_crossread = 0;// reset

	/* Assert that only crossreads @ 4 and 5 are bad. */
	if (read_bad[0]) { dev_err(dev, "crossread 0 bad!\n"); return -1; }
	if (read_bad[1]) { dev_err(dev, "crossread 1 bad!\n"); return -1; }
	if (read_bad[2]) { dev_err(dev, "crossread 2 bad!\n"); return -1; }
	if (read_bad[3]) { dev_err(dev, "crossread 3 bad!\n"); return -1; }
	if (!read_bad[4]) { dev_err(dev, "crossread 4 good?!\n"); return -1; }
	if (!read_bad[5]) { dev_err(dev, "crossread 5 good?!\n"); return -1; }

	/* check with crosswrites */
	for (read_bit = 0; read_bit < 6; read_bit++) {
		u32 r2;
		u32 r3;
		priv->r_crosswrite = BIT(read_bit);
		r2 = rtl8365mb_phy_read(priv, phynum, 2);
		r3 = rtl8365mb_phy_read(priv, phynum, 3);
		if (r2 != reg2 || r3 != reg3) {
			write_bad[read_bit] = 1;
		}
	}
	priv->r_crosswrite = 0;// reset

	/* Assert that only crosswrites @ 4 and 5 are bad. */
	if (write_bad[0]) { dev_err(dev, "crosswrite 0 bad!\n"); return -1; }
	if (write_bad[1]) { dev_err(dev, "crosswrite 1 bad!\n"); return -1; }
	if (write_bad[2]) { dev_err(dev, "crosswrite 2 bad!\n"); return -1; }
	if (write_bad[3]) { dev_err(dev, "crosswrite 3 bad!\n"); return -1; }
	if (!write_bad[4]) { dev_err(dev, "crosswrite 4 good?!\n"); return -1; }
	if (!write_bad[5]) { dev_err(dev, "crosswrite 5 good?!\n"); return -1; }

	return 0;
}

static int _check_phy_write(struct realtek_priv *priv, int phynum)
{
	u32 orig;
	u32 wval;
	u32 rval;
	struct device *dev = priv->dev;

	orig = rtl8365mb_phy_read(priv, phynum, 0);

	/* flip all the flippable bits */
	wval = orig;
	wval |= BIT(13);
	wval &= ~BIT(12);
	wval |= BIT(10);
	wval &= ~BIT(8);
	wval &= BIT(6);
	rtl8365mb_phy_write(priv, phynum, 0, wval);
	
	/* check it got written OK */
	rval = rtl8365mb_phy_read(priv, phynum, 0);
	if (rval != wval) {
		dev_err(dev, "phy%d rval 0x%04x != wval 0x%04x\n", phynum, rval, wval);
		return -1;
	}

	/* now flip back */
	wval = orig;
	rtl8365mb_phy_write(priv, phynum, 0, wval);
	
	/* check it got written OK */
	rval = rtl8365mb_phy_read(priv, phynum, 0);
	if (rval != wval) {
		dev_err(dev, "phy%d rval 0x%04x != wval 0x%04x\n", phynum, rval, wval);
		return -1;
	}

	return 0;
}

static int _check_phy_writes(struct realtek_priv *priv)
{
	if (_check_phy_write(priv, 0)) return -1;
	if (_check_phy_write(priv, 1)) return -1;
	if (_check_phy_write(priv, 2)) return -1;
	if (_check_phy_write(priv, 3)) return -1;
	return 0;
}

static int check_phy_write(struct realtek_priv *priv)
{
	int count = 0;
	int bit = 0;

	for (bit = 0; bit < 6; bit++) {
		priv->w_crossread = BIT(bit);
		if (_check_phy_writes(priv))
			return -1;
	}
	priv->w_crossread = 0;

	for (bit = 0; bit < 6; bit++) {
		priv->w_crosswrite = BIT(bit);
		if (_check_phy_writes(priv))
			return -1;
	}
	priv->w_crosswrite = 0;
	
	return 0;
}

static void do_reg_work(struct realtek_priv *priv)
{
	struct device *dev = priv->dev;
	int ret;
	u32 reg;
	int n_errors = 0;
	int n_checks = 3;
	int check = 0;

	dev_err(dev, "checking PHY write...\n");
	check_phy_write(priv);

	dev_err(dev, "checking good regs...\n");
	check_good_regs(priv);

	dev_err(dev, "checking MIB read...\n");
	check_mib_read(priv);

	/* For n_checks checks, for each (good) register, perform each
	possible cross-read/write while doing a PHY read, and make
	sure that it fails only in the way we expect it to. */
	dev_err(dev, "checking PHY read...\n");
	for (check = 0; check < n_checks; check++) {
		int initial_error_count = n_errors;
		for (reg = 0; reg < RTL_REG_END && n_errors < 5; reg++) {
			int phynum;
			if (bad_regs[reg]) continue;
			for(phynum = 0; phynum < 4 && n_errors < 5; phynum++) {
				if (check_phy_read(priv, phynum, reg)) {
					dev_err(dev,
						"was checking reg %s(0x%04x)\n",
						rtl_regs[reg].name,
						rtl_regs[reg].addr);
					n_errors++;
				}
			}
		}	
		if (n_errors >= 5) {
			dev_err(dev, "too many errors\n");
			return;
		}
		if (n_errors == initial_error_count)
			dev_err(dev, "OK %d/%d\n", check+1, n_checks);
	}
	
	return;
}

static void reg_work(struct work_struct *work)
{
	struct realtek_priv *priv = container_of(to_delayed_work(work),
						struct realtek_priv,
						work);

	do_reg_work(priv);
}


static int rtl8365mb_switch_init(struct realtek_priv *priv)
{
	int ret;
	int i;

	/* RTL8365MB init jam */
	for (i = 0; i < ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc); i++) {
		ret = regmap_write(priv->map, rtl8365mb_init_jam_8365mb_vc[i].reg,
				   rtl8365mb_init_jam_8365mb_vc[i].val);
		if (ret)
			return ret;
	}

	/* Common init jam */
	for (i = 0; i < ARRAY_SIZE(rtl8365mb_init_jam_common); i++) {
		ret = regmap_write(priv->map, rtl8365mb_init_jam_common[i].reg,
				   rtl8365mb_init_jam_common[i].val);
		if (ret)
			return ret;
	}

	return 0;
}

static int rtl8365mb_reset_chip(struct realtek_priv *priv)
{
	u32 val;

	realtek_smi_write_reg_noack(priv, RTL8365MB_CHIP_RESET_REG,
			      FIELD_PREP(RTL8365MB_CHIP_RESET_HW_MASK, 1));

	/* Realtek documentation says the chip needs 1 second to reset. Sleep
	 * for 100 ms before accessing any registers to prevent ACK timeouts.
	 */
	msleep(100);
	return regmap_read_poll_timeout(priv->map, RTL8365MB_CHIP_RESET_REG, val,
					!(val & RTL8365MB_CHIP_RESET_HW_MASK),
					20000, 1e6);
}



static int realtek_smi_probe(struct platform_device *pdev)
{
	const struct realtek_variant *var;
	struct device *dev = &pdev->dev;
	struct realtek_priv *priv;
	struct regmap_config rc;
	struct device_node *np;
	int ret;

	var = of_device_get_match_data(dev);
	np = dev->of_node;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	mutex_init(&priv->map_lock);

	rc = realtek_smi_regmap_config;
	rc.lock_arg = priv;
	priv->map = devm_regmap_init(dev, NULL, priv, &rc);
	if (IS_ERR(priv->map)) {
		ret = PTR_ERR(priv->map);
		dev_err(dev, "regmap init failed: %d\n", ret);
		return ret;
	}

	rc = realtek_smi_nolock_regmap_config;
	priv->map_nolock = devm_regmap_init(dev, NULL, priv, &rc);
	if (IS_ERR(priv->map_nolock)) {
		ret = PTR_ERR(priv->map_nolock);
		dev_err(dev, "regmap init failed: %d\n", ret);
		return ret;
	}

	/* Link forward and backward */
	priv->dev = dev;
	priv->clk_delay = 10;
	priv->cmd_read = 0xb9;
	priv->cmd_write = 0xb8;

	dev_set_drvdata(dev, priv);
	spin_lock_init(&priv->lock);

	priv->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
	if (IS_ERR(priv->reset)) {
		dev_err(dev, "failed to get RESET GPIO\n");
		return PTR_ERR(priv->reset);
	}
	if (priv->reset) {
		gpiod_set_value(priv->reset, 1);
		dev_dbg(dev, "asserted RESET\n");
		msleep(REALTEK_HW_STOP_DELAY);
		gpiod_set_value(priv->reset, 0);
		msleep(REALTEK_HW_START_DELAY);
		dev_dbg(dev, "deasserted RESET\n");
	}

	/* Fetch MDIO pins */
	priv->mdc = devm_gpiod_get_optional(dev, "mdc", GPIOD_OUT_LOW);
	if (IS_ERR(priv->mdc))
		return PTR_ERR(priv->mdc);
	priv->mdio = devm_gpiod_get_optional(dev, "mdio", GPIOD_OUT_LOW);
	if (IS_ERR(priv->mdio))
		return PTR_ERR(priv->mdio);

	ret = rtl8365mb_reset_chip(priv);
	if (ret) {
		dev_err(priv->dev, "failed to reset chip: %d\n", ret);
		return ret;
	}

	/* Configure switch to vendor-defined initial state */
	ret = rtl8365mb_switch_init(priv);
	if (ret) {
		dev_err(priv->dev, "failed to initialize switch: %d\n", ret);
		return ret;
	}

	INIT_DELAYED_WORK(&priv->work, reg_work);

	schedule_delayed_work(&priv->work, HZ);

	return 0;
}

static int realtek_smi_remove(struct platform_device *pdev)
{
	struct realtek_priv *priv = platform_get_drvdata(pdev);

	if (!priv)
		return 0;

	cancel_delayed_work_sync(&priv->work);

	/* leave the device reset asserted */
	if (priv->reset)
		gpiod_set_value(priv->reset, 1);

	platform_set_drvdata(pdev, NULL);

	return 0;
}

static const struct of_device_id realtek_smi_of_match[] = {
	{
		.compatible = "realtek,rtl8365mb",
	},
	{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, realtek_smi_of_match);

static struct platform_driver realtek_smi_driver = {
	.driver = {
		.name = "rtltest",
		.of_match_table = of_match_ptr(realtek_smi_of_match),
	},
	.probe  = realtek_smi_probe,
	.remove = realtek_smi_remove,
};
module_platform_driver(realtek_smi_driver);

MODULE_LICENSE("GPL");

Re: [PATCH net-next 2/2] net: dsa: realtek: rtl8365mb: serialize indirect PHY register access

[Vladimir Oltean]

Hi Alvin,

On Mon, Feb 21, 2022 at 02:50:24PM +0000, Alvin Šipraga wrote:
> So I made a test module which, in summary, checks the following:
> 
> 1. for PHY reads, at what point does inserting a stray register access
>    (either read or write) cause the PHY read to fail?
> 2. for PHY writes, can stray register access also cause failure?
> 2. for MIB reads, can stray register access also cause failure?
> 
> For (1) I instrumented the PHY indirect access functions in the 6
> possible places where spurious register access could occur. Of those 6
> locations for spurious register access, 4 have no effect: you can put a
> read or write to an unrelated register there and the PHY read will
> always succeed. I tested this with spurious access to nearly every
> available register on the switch.
> 
> However, for two locations of spurious register access, the PHY read
> _always_ fails. The locations are marked /* XXX */ below:
> 
> /* Simplified for brevity */
> static int rtl8365mb_phy_ocp_read(struct realtek_priv *priv, int phy,
> 				  u32 ocp_addr, u16 *data)
> {
> 	rtl8365mb_phy_poll_busy(priv);
> 
> 	rtl8365mb_phy_ocp_prepare(priv, phy, ocp_addr);
> 
> 	/* Execute read operation */
> 	regmap_write(priv->map, RTL8365MB_INDIRECT_ACCESS_CTRL_REG, val);
> 
> 	/* XXX */
> 
> 	rtl8365mb_phy_poll_busy(priv);
> 
> 	/* XXX */
> 
> 	/* Get PHY register data */
> 	regmap_read(priv->map, RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG,
> 		    &val);
> 
> 	*data = val & 0xFFFF;
> 
> 	return 0;
> }
> 
> In the case of a spurious read, the result of that read then poisons the
> ongoing PHY read, as suggested before. Again I verified that this is
> always the case, for each available register on the switch. Spurious
> writes also cause failure, and in the same locations too. I did not
> investigate whether the value written is then read back as part of the
> PHY read.
> 
> For (2) I did something similar to (1), but the difference here is that
> I could never get PHY writes to fail. Admittedly not all bits of the PHY
> registers tend to be writable, but for those bits that were writable, I
> would always then read back what I had written.
> 
> For (3) I did something similar to (1), and as claimed previously, this
> never resulted in a read failure. Here I had to use the MIB counters of
> a disconnected port so that I could assume the values were always 0.
> 
> I have attached the test module (and header file generated from an
> enormous header file from the Realtek driver sources, so that I could
> iterate over every possible register). It is pretty gruesome reading but
> gives me confidence in my earlier claims. The only refinements to those
> claims are:
> 
> - where _exactly_ a spurious register access will cause failure: see the
>   /* XXX */ in the code snippet upstairs;
> - PHY writes seem not to be affected at all.
> 
> Finally, I reached out to Realtek, and they confirmed pretty much the
> same as above. However, they claim it is not a hardware bug, but merely
> a property of the hardware design. Here I paraphrase what was said:
> 
> 1. Yes, spurious register access during PHY indirect access will cause
> the indirect access to fail. This is a result of the hardware design. In
> general, _if a read fails, the value read back will be the result of the
> last successful read_. This confirms the "register poisoning" described
> earlier.
> 
> 2. MIB access is a different story - this is table lookup, not indirect
> access. Table lookup is not affected by spurious register access.
> 
> 3. Other possible accesses - not currently present in this driver, but
> for which I have some WIP changes - include ACL (Access Control List),
> L2 (FDB), and MC (MDB) access. But all of these are table access similar
> to MIB access, and hence not troubled by spurious register access.
> 
> 4. HOWEVER, only one table can be accessed at a time. So a lock is
> needed here. Currently the only table lookup is MIB access, which is
> protected by mib_lock, so we are OK for now.
> 
> 5. It should be sufficient to lock during indirect PHY register access
> as prescribed in my patch.
> 
> I hope that clears things up. I will be sending a v2 with a revised
> description, including the statements from Realtek and the results of
> the tests I ran.
> 
> Kind regards,
> Alvin

Nice work!

This looks more comprehensive, although regarding check_phy_write(),
my understanding is that you checked cross-reads and cross-writes with
only one register: priv->read_reg is implicitly 0 during the
do_reg_work() -> check_phy_write() call sequence, so that register is
probably PORT0_CGST_HALF_CFG.

Anyway, if Realtek's description is that "if a read fails, the value
read back will be the result of the last successful read", then it's
probably not suprising that cross-reads and cross-writes don't make the
indirect PHY write fail (since there's no register read). I don't have
the background of what is the OCP, but the implication of the above
paragraph seems to be that an indirect PHY read is in essence the read
of a single register, which gets aborted when a read of any other
register except RTL8365MB_INDIRECT_ACCESS_STATUS_REG or
RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG gets initiated.

Re: [PATCH net-next 2/2] net: dsa: realtek: rtl8365mb: serialize indirect PHY register access

[Alvin Šipraga]

Vladimir Oltean <olteanv@gmail.com> writes:

> Hi Alvin,
>
> On Mon, Feb 21, 2022 at 02:50:24PM +0000, Alvin Šipraga wrote:
>> So I made a test module which, in summary, checks the following:
>> 
>> 1. for PHY reads, at what point does inserting a stray register access
>>    (either read or write) cause the PHY read to fail?
>> 2. for PHY writes, can stray register access also cause failure?
>> 2. for MIB reads, can stray register access also cause failure?
>> 
>> For (1) I instrumented the PHY indirect access functions in the 6
>> possible places where spurious register access could occur. Of those 6
>> locations for spurious register access, 4 have no effect: you can put a
>> read or write to an unrelated register there and the PHY read will
>> always succeed. I tested this with spurious access to nearly every
>> available register on the switch.
>> 
>> However, for two locations of spurious register access, the PHY read
>> _always_ fails. The locations are marked /* XXX */ below:
>> 
>> /* Simplified for brevity */
>> static int rtl8365mb_phy_ocp_read(struct realtek_priv *priv, int phy,
>> 				  u32 ocp_addr, u16 *data)
>> {
>> 	rtl8365mb_phy_poll_busy(priv);
>> 
>> 	rtl8365mb_phy_ocp_prepare(priv, phy, ocp_addr);
>> 
>> 	/* Execute read operation */
>> 	regmap_write(priv->map, RTL8365MB_INDIRECT_ACCESS_CTRL_REG, val);
>> 
>> 	/* XXX */
>> 
>> 	rtl8365mb_phy_poll_busy(priv);
>> 
>> 	/* XXX */
>> 
>> 	/* Get PHY register data */
>> 	regmap_read(priv->map, RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG,
>> 		    &val);
>> 
>> 	*data = val & 0xFFFF;
>> 
>> 	return 0;
>> }
>> 
>> In the case of a spurious read, the result of that read then poisons the
>> ongoing PHY read, as suggested before. Again I verified that this is
>> always the case, for each available register on the switch. Spurious
>> writes also cause failure, and in the same locations too. I did not
>> investigate whether the value written is then read back as part of the
>> PHY read.
>> 
>> For (2) I did something similar to (1), but the difference here is that
>> I could never get PHY writes to fail. Admittedly not all bits of the PHY
>> registers tend to be writable, but for those bits that were writable, I
>> would always then read back what I had written.
>> 
>> For (3) I did something similar to (1), and as claimed previously, this
>> never resulted in a read failure. Here I had to use the MIB counters of
>> a disconnected port so that I could assume the values were always 0.
>> 
>> I have attached the test module (and header file generated from an
>> enormous header file from the Realtek driver sources, so that I could
>> iterate over every possible register). It is pretty gruesome reading but
>> gives me confidence in my earlier claims. The only refinements to those
>> claims are:
>> 
>> - where _exactly_ a spurious register access will cause failure: see the
>>   /* XXX */ in the code snippet upstairs;
>> - PHY writes seem not to be affected at all.
>> 
>> Finally, I reached out to Realtek, and they confirmed pretty much the
>> same as above. However, they claim it is not a hardware bug, but merely
>> a property of the hardware design. Here I paraphrase what was said:
>> 
>> 1. Yes, spurious register access during PHY indirect access will cause
>> the indirect access to fail. This is a result of the hardware design. In
>> general, _if a read fails, the value read back will be the result of the
>> last successful read_. This confirms the "register poisoning" described
>> earlier.
>> 
>> 2. MIB access is a different story - this is table lookup, not indirect
>> access. Table lookup is not affected by spurious register access.
>> 
>> 3. Other possible accesses - not currently present in this driver, but
>> for which I have some WIP changes - include ACL (Access Control List),
>> L2 (FDB), and MC (MDB) access. But all of these are table access similar
>> to MIB access, and hence not troubled by spurious register access.
>> 
>> 4. HOWEVER, only one table can be accessed at a time. So a lock is
>> needed here. Currently the only table lookup is MIB access, which is
>> protected by mib_lock, so we are OK for now.
>> 
>> 5. It should be sufficient to lock during indirect PHY register access
>> as prescribed in my patch.
>> 
>> I hope that clears things up. I will be sending a v2 with a revised
>> description, including the statements from Realtek and the results of
>> the tests I ran.
>> 
>> Kind regards,
>> Alvin
>
> Nice work!
>
> This looks more comprehensive, although regarding check_phy_write(),
> my understanding is that you checked cross-reads and cross-writes with
> only one register: priv->read_reg is implicitly 0 during the
> do_reg_work() -> check_phy_write() call sequence, so that register is
> probably PORT0_CGST_HALF_CFG.

Woops, my bad - thanks for checking. I added an extra loop in
check_phy_write() now to do the checking with a cross-read of every
(good) register (and moved check_good_regs() before
check_phy_write()). The results are broadly the same, although I start
to get some changes when reaching registers like PORT0_STATUS (for
obvious reasons, since I'm poking the PHY control register). There the
logic of my test starts to break down a bit because a lot of the sanity
checks assume that the registers are non-volatile.

Still, PORT0_STATUS is the ~3000th register in the list, so if all other
cross-reads prior to that don't affect the PHY write, I am convinced
that this is not a problem for PHY writes.

For cross-writes I am always writing the same register anyway.

>
> Anyway, if Realtek's description is that "if a read fails, the value
> read back will be the result of the last successful read", then it's
> probably not suprising that cross-reads and cross-writes don't make the
> indirect PHY write fail (since there's no register read). I don't have
> the background of what is the OCP, but the implication of the above
> paragraph seems to be that an indirect PHY read is in essence the read
> of a single register, which gets aborted when a read of any other
> register except RTL8365MB_INDIRECT_ACCESS_STATUS_REG or
> RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG gets initiated.

I agree with what you wrote above, I think it captures the point
succinctly. (I also don't know what OCP stands for.)

Kind regards,
Alvin

Re: [PATCH net-next 0/2] net: dsa: realtek: fix PHY register read corruption

[Luiz Angelo Daros de Luca]

> These two patches fix the issue reported by Arınç where PHY register
> reads sometimes return garbage data.
>
> MAINTAINERS: Please can you help me with the targetting of these two
> patches? This bug is present ca. 5.16, when the SMI version of the
> rtl8365mb driver was introduced. But now in net-next we have the MDIO
> interface from Luiz, where the issue is also present. I am sending what
> I think is an ideal patch series, but should I split it up and send the
> SMI-related changes to net and the MDIO changes to net-next? If so, how
> would I go about splitting it while preventing merge conflicts and build
> errors?
>
> For now I am sending it to net-next so that the whole thing can be
> reviewed. If it's applied, I would gladly backport the fix to the stable
> tree for 5.16, but I am still confused about what to do for 5.17.
>
> Thanks for your help.
>
>
> Alvin Šipraga (2):
>   net: dsa: realtek: allow subdrivers to externally lock regmap
>   net: dsa: realtek: rtl8365mb: serialize indirect PHY register access
>
>  drivers/net/dsa/realtek/realtek-mdio.c | 46 +++++++++++++++++++++-
>  drivers/net/dsa/realtek/realtek-smi.c  | 48 +++++++++++++++++++++--
>  drivers/net/dsa/realtek/realtek.h      |  2 +
>  drivers/net/dsa/realtek/rtl8365mb.c    | 54 ++++++++++++++++----------
>  4 files changed, 124 insertions(+), 26 deletions(-)
>
> --
> 2.35.0
>

Thanks for the fix, Alvin.

I still feel like we are trying to go around a regmap limitation
instead of fixing it there. If we control regmap lock (we can define a
custom lock/unlock) and create new regmap_{read,write}_nolock
variants, we'll just need to lock the regmap, do whatever you need,
and unlock it.

BTW, I believe that, for realtek-mdio, a regmap custom lock mechanism
could simply use mdio lock while realtek-smi already has priv->lock.

Regards,

Re: [PATCH net-next 0/2] net: dsa: realtek: fix PHY register read corruption

[Alvin Šipraga]

Luiz Angelo Daros de Luca <luizluca@gmail.com> writes:

>> These two patches fix the issue reported by Arınç where PHY register
>> reads sometimes return garbage data.
>>
>> MAINTAINERS: Please can you help me with the targetting of these two
>> patches? This bug is present ca. 5.16, when the SMI version of the
>> rtl8365mb driver was introduced. But now in net-next we have the MDIO
>> interface from Luiz, where the issue is also present. I am sending what
>> I think is an ideal patch series, but should I split it up and send the
>> SMI-related changes to net and the MDIO changes to net-next? If so, how
>> would I go about splitting it while preventing merge conflicts and build
>> errors?
>>
>> For now I am sending it to net-next so that the whole thing can be
>> reviewed. If it's applied, I would gladly backport the fix to the stable
>> tree for 5.16, but I am still confused about what to do for 5.17.
>>
>> Thanks for your help.
>>
>>
>> Alvin Šipraga (2):
>>   net: dsa: realtek: allow subdrivers to externally lock regmap
>>   net: dsa: realtek: rtl8365mb: serialize indirect PHY register access
>>
>>  drivers/net/dsa/realtek/realtek-mdio.c | 46 +++++++++++++++++++++-
>>  drivers/net/dsa/realtek/realtek-smi.c  | 48 +++++++++++++++++++++--
>>  drivers/net/dsa/realtek/realtek.h      |  2 +
>>  drivers/net/dsa/realtek/rtl8365mb.c    | 54 ++++++++++++++++----------
>>  4 files changed, 124 insertions(+), 26 deletions(-)
>>
>> --
>> 2.35.0
>>
>
> Thanks for the fix, Alvin.
>
> I still feel like we are trying to go around a regmap limitation
> instead of fixing it there. If we control regmap lock (we can define a
> custom lock/unlock) and create new regmap_{read,write}_nolock
> variants, we'll just need to lock the regmap, do whatever you need,
> and unlock it.

Can you show me what those regmap_{read,write}_nolock variants would
look like in your example? And what about the other regmap_ APIs we use,
like regmap_read_poll_timeout, regmap_update_bits, etc. - do you propose
to reimplement all of these?

>
> BTW, I believe that, for realtek-mdio, a regmap custom lock mechanism
> could simply use mdio lock while realtek-smi already has priv->lock.

Hmm OK. Actually I'm a bit confused about the mdio_lock: can you explain
what it's guarding against, for someone unfamiliar with MDIO? Currently
realtek-mdio's regmap has an additional lock around it (disable_locking
is 0), so with these patches applied the number of locks remains the
same.

priv->lock is a spinlock which is inappropriate here. I'm not really
sure what the point of it is, besides to handle unlocked calls to the
_noack function. It might be removable altogether but I would prefer not
to touch it for this series.

Kind regards,
Alvin

Re: [PATCH net-next 0/2] net: dsa: realtek: fix PHY register read corruption

[Andrew Lunn]

> Hmm OK. Actually I'm a bit confused about the mdio_lock: can you explain
> what it's guarding against, for someone unfamiliar with MDIO?

The more normal use case for MDIO is for PHYs, not switches. There can
be multiple PHYs on one MDIO bus. And these PHYs each have there own
state machine in phylib. At any point in time, that state machine can
request the driver to do something, like poll the PHY status, does it
have link? To prevent two PHY drivers trying to use the MDIO bus at
the same time, there is an MDIO lock. At the beginning of an MDIO
transaction, the lock is taken. And the end of the transaction,
reading or writing one register of a device on the bus, the lock is
released.

So the MDIO lock simply ensures there is only one user of the MDIO bus
at one time, for a single read or write.

For PHYs this is sufficient. For switches, sometimes you need
additional protection. The granularity of an access might not be a
single register read or a write. It could be you need to read or write
a few registers in an atomic way. If that is the case, you need a lock
at a higher level.

   Andrew

Re: [PATCH net-next 0/2] net: dsa: realtek: fix PHY register read corruption

[Alvin Šipraga]

Andrew Lunn <andrew@lunn.ch> writes:
>> Hmm OK. Actually I'm a bit confused about the mdio_lock: can you explain
>> what it's guarding against, for someone unfamiliar with MDIO?
>
> The more normal use case for MDIO is for PHYs, not switches. There can
> be multiple PHYs on one MDIO bus. And these PHYs each have there own
> state machine in phylib. At any point in time, that state machine can
> request the driver to do something, like poll the PHY status, does it
> have link? To prevent two PHY drivers trying to use the MDIO bus at
> the same time, there is an MDIO lock. At the beginning of an MDIO
> transaction, the lock is taken. And the end of the transaction,
> reading or writing one register of a device on the bus, the lock is
> released.
>
> So the MDIO lock simply ensures there is only one user of the MDIO bus
> at one time, for a single read or write.
>
> For PHYs this is sufficient. For switches, sometimes you need
> additional protection. The granularity of an access might not be a
> single register read or a write. It could be you need to read or write
> a few registers in an atomic way. If that is the case, you need a lock
> at a higher level.

Thank you Andrew for the clear explanation.

Somewhat unrelated to this series, but are you able to explain to me the
difference between:

	mutex_lock(&bus->mdio_lock);
and
	mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);

While looking at other driver examples I noticed the latter form quite a
few times too.

Kind regards,
Alvin

Re: [PATCH net-next 0/2] net: dsa: realtek: fix PHY register read corruption

[Andrew Lunn]

> Thank you Andrew for the clear explanation.
> 
> Somewhat unrelated to this series, but are you able to explain to me the
> difference between:
> 
> 	mutex_lock(&bus->mdio_lock);
> and
> 	mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
> 
> While looking at other driver examples I noticed the latter form quite a
> few times too.

This is to do with the debug code for checking for deadlocks,
CONFIG_PROVE_LOCKING. When that feature is enables, each lock/unlock
of a mutex is tracked, and a list is made of what other locks are also
taken, and the order. The code can find deadlocks where one thread
takes A then B, while another thread takes B and then A. It can also
detect when a thread takes lock A and then tries to take lock A again.

Rather than track each individual mutex, it uses classes of mutex. So
bus->mdio_lock is a class of mutex. The code simply tracks that a
bus->mdio_lock has been taken, not a specific bus->mdio_lock. That is
generally sufficient, but not always. The mv88e6xxx switch is like
many switches, accessed over MDIO. But the mv88e6xxx switch offers an
MDIO bus, and there is an MDIO bus driver inside the mv88e6xxx
driver. So you have nested MDIO calls. So this debug code seems the
same class of mutex being taken twice, and thinks it is a
deadlock. You can tell it that nested MDIO calls are actually O.K, it
won't deadlock.

      Andrew

Re: [PATCH net-next 0/2] net: dsa: realtek: fix PHY register read corruption

[Alvin Šipraga]

Andrew Lunn <andrew@lunn.ch> writes:

>> Thank you Andrew for the clear explanation.
>> 
>> Somewhat unrelated to this series, but are you able to explain to me the
>> difference between:
>> 
>> 	mutex_lock(&bus->mdio_lock);
>> and
>> 	mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
>> 
>> While looking at other driver examples I noticed the latter form quite a
>> few times too.
>
> This is to do with the debug code for checking for deadlocks,
> CONFIG_PROVE_LOCKING. When that feature is enables, each lock/unlock
> of a mutex is tracked, and a list is made of what other locks are also
> taken, and the order. The code can find deadlocks where one thread
> takes A then B, while another thread takes B and then A. It can also
> detect when a thread takes lock A and then tries to take lock A again.
>
> Rather than track each individual mutex, it uses classes of mutex. So
> bus->mdio_lock is a class of mutex. The code simply tracks that a
> bus->mdio_lock has been taken, not a specific bus->mdio_lock. That is
> generally sufficient, but not always. The mv88e6xxx switch is like
> many switches, accessed over MDIO. But the mv88e6xxx switch offers an
> MDIO bus, and there is an MDIO bus driver inside the mv88e6xxx
> driver. So you have nested MDIO calls. So this debug code seems the
> same class of mutex being taken twice, and thinks it is a
> deadlock. You can tell it that nested MDIO calls are actually O.K, it
> won't deadlock.

Thanks for the explanation, the missing piece of the puzzle was the fact
that some switch drivers expose an additional MDIO bus. I can understand
the CONFIG_PROVE_LOCKING rationale.

If you have the patience to answer a few more questions:

1. You mentioned in an earlier mail that the mdio_lock is used mostly by
PHY drivers to synchronize their access to the MDIO bus, for a single
read or write. You also mentioned that for switches which have a more
involved access pattern (for instance to access switch management
registers), a higher lock is required. In realtek-mdio this is the case:
we do a couple of reads and writes over the MDIO bus to access the
switch registers. Moreover, the mdio_lock is held for the duration of
these MDIO bus reads/writes. Do you mean to say that one should rather
take a higher-level lock and only lock/unlock the mdio_lock on a
per-read or per-write basis? Put another way, should this:

static int realtek_mdio_read(void *ctx, u32 reg, u32 *val)
{
	/* ... */
        
	mutex_lock(&bus->mdio_lock);

	bus->write(bus, priv->mdio_addr, ...);
	bus->write(bus, priv->mdio_addr, ...);
	bus->write(bus, priv->mdio_addr, ...);
	bus->read(bus, priv->mdio_addr, ...);

	/* ... */

	mutex_unlock(&bus->mdio_lock);

	return ret;
}

rather look like this?:

static int realtek_mdio_read(void *ctx, u32 reg, u32 *val)
{
	/* ... */
        
	mutex_lock(&my_realtek_driver_lock); /* synchronize concurrent realtek_mdio_{read,write} */

	mdiobus_write(bus, priv->mdio_addr, ...); /* mdio_lock locked/unlocked here */
	mdiobus_write(bus, priv->mdio_addr, ...); /* ditto */
	mdiobus_write(bus, priv->mdio_addr, ...); /* ditto */
	mdiobus_read(bus, priv->mdio_addr, ...);  /* ditto */

	/* ... */

	mutex_unlock(&my_realtek_driver_lock);

	return ret;
}


2. Is the nested locking only relevant for DSA switches which offer
another MDIO bus? Or should all switch drivers do this, on the basis
that, feasibly, one could connect my Realtek switch to the MDIO bus of a
mv88e6xxx switch? In that case, and assuming the latter form of
raeltek_mdio_read above, should one use the mdiobus_{read,write}_nested
functions instead?

Kind regards,
Alvin

Re: [PATCH net-next 0/2] net: dsa: realtek: fix PHY register read corruption

[Andrew Lunn]

> If you have the patience to answer a few more questions:
> 
> 1. You mentioned in an earlier mail that the mdio_lock is used mostly by
> PHY drivers to synchronize their access to the MDIO bus, for a single
> read or write. You also mentioned that for switches which have a more
> involved access pattern (for instance to access switch management
> registers), a higher lock is required. In realtek-mdio this is the case:
> we do a couple of reads and writes over the MDIO bus to access the
> switch registers. Moreover, the mdio_lock is held for the duration of
> these MDIO bus reads/writes. Do you mean to say that one should rather
> take a higher-level lock and only lock/unlock the mdio_lock on a
> per-read or per-write basis? Put another way, should this:
> 
> static int realtek_mdio_read(void *ctx, u32 reg, u32 *val)
> {
> 	/* ... */
>         
> 	mutex_lock(&bus->mdio_lock);
> 
> 	bus->write(bus, priv->mdio_addr, ...);

It would be better to use __mdiobus_write()

> 	bus->write(bus, priv->mdio_addr, ...);
> 	bus->write(bus, priv->mdio_addr, ...);
> 	bus->read(bus, priv->mdio_addr, ...);

__mdiobus_read()

> 	/* ... */
> 
> 	mutex_unlock(&bus->mdio_lock);
> 
> 	return ret;
> }

You can do this.


> rather look like this?:
> 
> static int realtek_mdio_read(void *ctx, u32 reg, u32 *val)
> {
> 	/* ... */
>         
> 	mutex_lock(&my_realtek_driver_lock); /* synchronize concurrent realtek_mdio_{read,write} */
> 
> 	mdiobus_write(bus, priv->mdio_addr, ...); /* mdio_lock locked/unlocked here */
> 	mdiobus_write(bus, priv->mdio_addr, ...); /* ditto */
> 	mdiobus_write(bus, priv->mdio_addr, ...); /* ditto */
> 	mdiobus_read(bus, priv->mdio_addr, ...);  /* ditto */
> 
> 	/* ... */
> 
> 	mutex_unlock(&my_realtek_driver_lock);
> 
> 	return ret;
> }

This would also work. The advantage of this is when you have multiple
switches on one MDIO bus, you can allow parallel operations on those
switches. Also, if there are PHYs on the MDIO bus as well as the
switch, the PHYs can be accessed as well. If you are only doing 3
writes and read, it probably does not matter. If you are going to do a
lot of accesses, maybe read all the MIB values, allowing access to the
PHYs at the same time would be nice.

> 2. Is the nested locking only relevant for DSA switches which offer
> another MDIO bus? Or should all switch drivers do this, on the basis
> that, feasibly, one could connect my Realtek switch to the MDIO bus of a
> mv88e6xxx switch? In that case, and assuming the latter form of
> raeltek_mdio_read above, should one use the mdiobus_{read,write}_nested
> functions instead?

I would suggest you start with plain mdiobus_{read,write}. Using the
_nested could potentially hide a deadlock. If somebody does build
hardware with this sort of chaining, we can change to the _nested
calls.

	Andrew

Re: [PATCH net-next 0/2] net: dsa: realtek: fix PHY register read corruption

[Luiz Angelo Daros de Luca]

> > I still feel like we are trying to go around a regmap limitation
> > instead of fixing it there. If we control regmap lock (we can define a
> > custom lock/unlock) and create new regmap_{read,write}_nolock
> > variants, we'll just need to lock the regmap, do whatever you need,
> > and unlock it.
>
> Can you show me what those regmap_{read,write}_nolock variants would
> look like in your example? And what about the other regmap_ APIs we use,
> like regmap_read_poll_timeout, regmap_update_bits, etc. - do you propose
> to reimplement all of these?

The option of having two regmaps is a nice way to have "_nolock"
variants for free. It is much cleaner than any solutions I imagined!
Ayway, I don't believe the regmap API expects to have an evil
non-locked clone. It looks like it is being abused.

What regmap API misses is a way to create a "transaction". Mdio, for
example, expects the user to lock the bus before doing a series of
accesses while regmap api assumes a single atomic access is enough.
However, Realtek indirect register access shows that it is not enough.
We could reimplement a mutex for every case where two calls might
share the same register (or indirectly affect others like we saw with
Realtek) but I believe a shared solution would be better, even if it
costs a couple more wrap functions.

It would be even nicer if we have a regmap "manual lock" mode that
will expose the lock/unlock functions but it will never call them by
itself. It would work if it could check if the caller is actually the
same thread/context that locked it. However I doubt there is a clean
solution in a kernel code that can check if the lock was acquired by
the same context that is calling the read.


> > BTW, I believe that, for realtek-mdio, a regmap custom lock mechanism
> > could simply use mdio lock while realtek-smi already has priv->lock.
>
> Hmm OK. Actually I'm a bit confused about the mdio_lock: can you explain
> what it's guarding against, for someone unfamiliar with MDIO? Currently
> realtek-mdio's regmap has an additional lock around it (disable_locking
> is 0), so with these patches applied the number of locks remains the
> same.

Today we already have to redundants locks (mdio and regmap). Your
patch is just replacing the regmap lock.

regmap_read is something like this:

regmap_read
    lock regmap
    realtek_mdio_read()
        lock mdio
        ...
        unlock mdio
   unlock regmap

If you are implementing a custom lock, simply use mdio lock directly.

And the map_nolock you created does not mean "access without locks"
but "you must lock it yourself before using anything here". If that
lock is actually mdio_lock, it would be ok to remove the lock inside
realtek_mdio_{read,write}. You just need a reference to those
lock/unlock functions in realtek_priv.

> priv->lock is a spinlock which is inappropriate here. I'm not really
> sure what the point of it is, besides to handle unlocked calls to the
> _noack function. It might be removable altogether but I would prefer not
> to touch it for this series.

If spinlock is inappropriate, it can be easily converted to a mutex.
Everything else from realtek-mdio might apply.

> Kind regards,
> Alvin

Re: [PATCH net-next 0/2] net: dsa: realtek: fix PHY register read corruption

[Alvin Šipraga]

Luiz Angelo Daros de Luca <luizluca@gmail.com> writes:

>> > I still feel like we are trying to go around a regmap limitation
>> > instead of fixing it there. If we control regmap lock (we can define a
>> > custom lock/unlock) and create new regmap_{read,write}_nolock
>> > variants, we'll just need to lock the regmap, do whatever you need,
>> > and unlock it.
>>
>> Can you show me what those regmap_{read,write}_nolock variants would
>> look like in your example? And what about the other regmap_ APIs we use,
>> like regmap_read_poll_timeout, regmap_update_bits, etc. - do you propose
>> to reimplement all of these?
>
> The option of having two regmaps is a nice way to have "_nolock"
> variants for free. It is much cleaner than any solutions I imagined!
> Ayway, I don't believe the regmap API expects to have an evil
> non-locked clone. It looks like it is being abused.
>
> What regmap API misses is a way to create a "transaction". Mdio, for
> example, expects the user to lock the bus before doing a series of
> accesses while regmap api assumes a single atomic access is enough.
> However, Realtek indirect register access shows that it is not enough.
> We could reimplement a mutex for every case where two calls might
> share the same register (or indirectly affect others like we saw with
> Realtek) but I believe a shared solution would be better, even if it
> costs a couple more wrap functions.
>
> It would be even nicer if we have a regmap "manual lock" mode that
> will expose the lock/unlock functions but it will never call them by
> itself. It would work if it could check if the caller is actually the
> same thread/context that locked it. However I doubt there is a clean
> solution in a kernel code that can check if the lock was acquired by
> the same context that is calling the read.

I went through all of this while preparing the patch, so your arguments
are familiar to me ;-)

What I sent was the cleanest solution I could eventually think of. I
don't think it is foul play, but I agree it is a bit funny to have this
kind of "shadow regmap". However, the interface is quite safe, and as I
implied in the commit message, quite foolproof as well.

Basically, rather than reimplementing every regmap API that I want to
use while manually taking the lock, I just use another regmap with
locking disabled. It boils down to exactly the same thing.

>
>
>> > BTW, I believe that, for realtek-mdio, a regmap custom lock mechanism
>> > could simply use mdio lock while realtek-smi already has priv->lock.
>>
>> Hmm OK. Actually I'm a bit confused about the mdio_lock: can you explain
>> what it's guarding against, for someone unfamiliar with MDIO? Currently
>> realtek-mdio's regmap has an additional lock around it (disable_locking
>> is 0), so with these patches applied the number of locks remains the
>> same.
>
> Today we already have to redundants locks (mdio and regmap). Your
> patch is just replacing the regmap lock.

Is that so? Andrew seems to imply that you shouldn't be using the
mdio_lock like this, but only for per-register access, and then
implement your own higher level lock:

> For PHYs this is sufficient. For switches, sometimes you need
> additional protection. The granularity of an access might not be a
> single register read or a write. It could be you need to read or write
> a few registers in an atomic way. If that is the case, you need a lock
> at a higher level.

It seems to me like you should have used mdiobus_{read,write} or even
mdiobus_{read,write}_nested? Although the state of the art in other DSA
drivers seems like a mixed bag, so I don't know.

Since I do not have an MDIO switch in front of me to test with, and
since the existing MDIO code looks a little suspect, again I would
prefer to stick in my lane and just fix the problem without
refactoring.

>
> regmap_read is something like this:
>
> regmap_read
>     lock regmap
>     realtek_mdio_read()
>         lock mdio
>         ...
>         unlock mdio
>    unlock regmap
>
> If you are implementing a custom lock, simply use mdio lock directly.
>
> And the map_nolock you created does not mean "access without locks"
> but "you must lock it yourself before using anything here". If that
> lock is actually mdio_lock, it would be ok to remove the lock inside
> realtek_mdio_{read,write}. You just need a reference to those
> lock/unlock functions in realtek_priv.
>
>> priv->lock is a spinlock which is inappropriate here. I'm not really
>> sure what the point of it is, besides to handle unlocked calls to the
>> _noack function. It might be removable altogether but I would prefer not
>> to touch it for this series.
>
> If spinlock is inappropriate, it can be easily converted to a mutex.
> Everything else from realtek-mdio might apply.

Well, this is a bugfix series, not a refactoring. I am not adding more
locks than were here before. If I start touching old code (this spinlock
predates my engagement with this driver), I will have to answer to that
in the commit message too. If we want to do this, let's do it after the
bugfix has been reviewed and merged. It will be easier to justify as
well.

Kind regards,
Alvin

>
>> Kind regards,
>> Alvin