From: Marc Zyngier <firstname.lastname@example.org> To: Huacai Chen <email@example.com> Cc: Huacai Chen <firstname.lastname@example.org>, Thomas Gleixner <email@example.com>, LKML <firstname.lastname@example.org>, Xuefeng Li <email@example.com>, Jiaxun Yang <firstname.lastname@example.org> Subject: Re: [PATCH V3 08/10] irqchip: Add LoongArch CPU interrupt controller support Date: Sun, 29 Aug 2021 11:10:49 +0100 [thread overview] Message-ID: <email@example.com> (raw) In-Reply-To: <CAAhV-H41rridOo_3Eq5t9LPz-mefketAKNdhgbguFtZ0Cqz5Ng@mail.gmail.com> On Sun, 29 Aug 2021 10:37:48 +0100, Huacai Chen <firstname.lastname@example.org> wrote: > > Are you saying that there is no way for the interrupt controller > > driver to figure out the hwirq number on its own? That would seem > > pretty odd (even the MIPS GIC has that). Worse case, you can provide > > an arch-specific helper that exposes the current hwirq based on the > > vector that triggered. > We can get the hwirq number by reading CSR.ESTAT register, but in this > way "vectored interrupts" is meaningless. Let's face it, the way you use vectored interrupts makes zero sense already. The whole point of vectored interrupts is that the CPU can branch to the handler directly, making the interrupt handling cheaper as there should be no additional decoding and you can run the final handler immediately. Here, all your interrupts point to the same "default handler"... What do vectored interrupts bring? "Absolutely Nothing! (say it again!)" M. -- Without deviation from the norm, progress is not possible.
next prev parent reply other threads:[~2021-08-29 10:10 UTC|newest] Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-08-25 6:11 [PATCH V3 00/10] irqchip: Add LoongArch-related irqchip drivers Huacai Chen 2021-08-25 6:11 ` [PATCH V3 01/10] irqchip: Adjust Kconfig for Loongson Huacai Chen 2021-08-25 6:11 ` [PATCH V3 02/10] irqchip/loongson-pch-pic: Add ACPI init support Huacai Chen 2021-08-25 6:11 ` [PATCH V3 03/10] irqchip/loongson-pch-pic: Add suspend/resume support Huacai Chen 2021-08-25 6:11 ` [PATCH V3 04/10] irqchip/loongson-pch-msi: Add ACPI init support Huacai Chen 2021-08-25 6:11 ` [PATCH V3 05/10] irqchip/loongson-htvec: " Huacai Chen 2021-08-25 6:11 ` [PATCH V3 06/10] irqchip/loongson-htvec: Add suspend/resume support Huacai Chen 2021-08-25 6:11 ` [PATCH V3 07/10] irqchip/loongson-liointc: Add ACPI init support Huacai Chen 2021-08-25 6:11 ` [PATCH V3 08/10] irqchip: Add LoongArch CPU interrupt controller support Huacai Chen 2021-08-25 8:40 ` Marc Zyngier 2021-08-27 8:12 ` Huacai Chen 2021-08-28 10:07 ` Huacai Chen 2021-08-28 11:07 ` Marc Zyngier 2021-08-29 9:37 ` Huacai Chen 2021-08-29 10:10 ` Marc Zyngier [this message] 2021-08-29 10:34 ` Huacai Chen 2021-08-29 11:00 ` Marc Zyngier 2021-08-30 3:19 ` Huacai Chen 2021-08-25 6:11 ` [PATCH V3 09/10] irqchip: Add Loongson Extended I/O " Huacai Chen 2021-08-25 6:11 ` [PATCH V3 10/10] irqchip: Add Loongson PCH LPC " Huacai Chen
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