* [PATCH] clk: rockchip: fix clock select order for usbphy480m_src
@ 2014-11-13 8:11 Kever Yang
2014-11-15 23:41 ` Heiko Stübner
0 siblings, 1 reply; 2+ messages in thread
From: Kever Yang @ 2014-11-13 8:11 UTC (permalink / raw)
To: Heiko Stuebner, Mike Turquette
Cc: dianders, sonnyrao, addy.ke, cf, dkl, huangtao, linux-rockchip,
Kever Yang, linux-arm-kernel, linux-kernel
According to rk3288 trm, the mux selector locate at bit[12:11]
of CRU_CLKSEL13_CON shows:
2'b00: select HOST0 USB pll clock (clk_otgphy1)
2'b01: select HOST1 USB pll clock (clk_otgphy2)
2'b10: select OTG USB pll clock (clk_otgphy0)
The clock map is in Fig. 3-4 CRU Clock Architecture Diagram 3
- clk_otgphy0 -> USB PHY OTG
- clk_otgphy1 -> USB PHY host0
- clk_otgphy2 -> USB PHY host1
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
drivers/clk/rockchip/clk-rk3288.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 157b60b..4d70518 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -195,8 +195,8 @@ PNAME(mux_hsadcout_p) = { "hsadc_src", "ext_hsadc" };
PNAME(mux_edp_24m_p) = { "ext_edp_24m", "xin24m" };
PNAME(mux_tspout_p) = { "cpll", "gpll", "npll", "xin27m" };
-PNAME(mux_usbphy480m_p) = { "sclk_otgphy0", "sclk_otgphy1",
- "sclk_otgphy2" };
+PNAME(mux_usbphy480m_p) = { "sclk_otgphy1", "sclk_otgphy2",
+ "sclk_otgphy0" };
PNAME(mux_hsicphy480m_p) = { "cpll", "gpll", "usbphy480m_src" };
PNAME(mux_hsicphy12m_p) = { "hsicphy12m_xin12m", "hsicphy12m_usbphy" };
--
1.9.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] clk: rockchip: fix clock select order for usbphy480m_src
2014-11-13 8:11 [PATCH] clk: rockchip: fix clock select order for usbphy480m_src Kever Yang
@ 2014-11-15 23:41 ` Heiko Stübner
0 siblings, 0 replies; 2+ messages in thread
From: Heiko Stübner @ 2014-11-15 23:41 UTC (permalink / raw)
To: Kever Yang
Cc: Mike Turquette, dianders, sonnyrao, addy.ke, cf, dkl, huangtao,
linux-rockchip, linux-arm-kernel, linux-kernel
Am Donnerstag, 13. November 2014, 16:11:49 schrieb Kever Yang:
> According to rk3288 trm, the mux selector locate at bit[12:11]
> of CRU_CLKSEL13_CON shows:
> 2'b00: select HOST0 USB pll clock (clk_otgphy1)
> 2'b01: select HOST1 USB pll clock (clk_otgphy2)
> 2'b10: select OTG USB pll clock (clk_otgphy0)
>
> The clock map is in Fig. 3-4 CRU Clock Architecture Diagram 3
> - clk_otgphy0 -> USB PHY OTG
> - clk_otgphy1 -> USB PHY host0
> - clk_otgphy2 -> USB PHY host1
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
applied this to my clk branch for 3.19
Heiko
^ permalink raw reply [flat|nested] 2+ messages in thread
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2014-11-15 23:41 ` Heiko Stübner
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