* [PATCH v7 0/2] Add support for Layerscape external interrupt lines
@ 2019-11-07 12:21 Rasmus Villemoes
2019-11-07 12:21 ` [PATCH v7 1/2] dt/bindings: Add bindings for Layerscape external irqs Rasmus Villemoes
` (2 more replies)
0 siblings, 3 replies; 10+ messages in thread
From: Rasmus Villemoes @ 2019-11-07 12:21 UTC (permalink / raw)
To: Thomas Gleixner, Jason Cooper, Marc Zyngier, Rob Herring, Mark Rutland
Cc: Rasmus Villemoes, linux-kernel, devicetree, Kurt Kanzenbach
In v7, I've tried to change from a custom binding to use
interrupt-map, modelled on the recent addition of the
renesas,rza1-irqc (commits a644ccb819bc and 5e27a314a11f). It's
possible that the interrupt-map parsing code can be factored to a
common helper, but it's a bit hard to generalize from two examples to
know what a good interface would look like.
The interrupt-map-mask is a bit arbitrary. 0xff would likely work just
as well (but I think the ls2088a has 32 external lines, so it has to
be a least 0x1f).
Also, this drops the fsl,bit-reverse property and instead reads the
SCFGREVCR register to determine if bit-reversing is needed.
The dt/bindings patch now comes first in accordance with
Documentation/devicetree/bindings/submitting-patches.txt.
Earlier versions can be found here:
v6: https://lore.kernel.org/lkml/20190923101513.32719-1-kurt@linutronix.de/
v5: https://lore.kernel.org/lkml/20180223210901.23480-1-rasmus.villemoes@prevas.dk/
Rasmus Villemoes (2):
dt/bindings: Add bindings for Layerscape external irqs
irqchip: add support for Layerscape external interrupt lines
.../interrupt-controller/fsl,ls-extirq.txt | 49 +++++
drivers/irqchip/Kconfig | 4 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-ls-extirq.c | 197 ++++++++++++++++++
4 files changed, 251 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt
create mode 100644 drivers/irqchip/irq-ls-extirq.c
--
2.23.0
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v7 1/2] dt/bindings: Add bindings for Layerscape external irqs
2019-11-07 12:21 [PATCH v7 0/2] Add support for Layerscape external interrupt lines Rasmus Villemoes
@ 2019-11-07 12:21 ` Rasmus Villemoes
2019-11-20 13:21 ` [tip: irq/core] " tip-bot2 for Rasmus Villemoes
2019-11-07 12:21 ` [PATCH v7 2/2] irqchip: add support for Layerscape external interrupt lines Rasmus Villemoes
2019-11-11 10:24 ` [PATCH v7 0/2] " Marc Zyngier
2 siblings, 1 reply; 10+ messages in thread
From: Rasmus Villemoes @ 2019-11-07 12:21 UTC (permalink / raw)
To: Thomas Gleixner, Jason Cooper, Marc Zyngier, Rob Herring, Mark Rutland
Cc: Rasmus Villemoes, linux-kernel, devicetree, Kurt Kanzenbach
This adds Device Tree binding documentation for the external interrupt
lines with configurable polarity present on some Layerscape SOCs.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
.../interrupt-controller/fsl,ls-extirq.txt | 49 +++++++++++++++++++
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt
diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt
new file mode 100644
index 000000000000..f0ad7801e8cf
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt
@@ -0,0 +1,49 @@
+* Freescale Layerscape external IRQs
+
+Some Layerscape SOCs (LS1021A, LS1043A, LS1046A) support inverting
+the polarity of certain external interrupt lines.
+
+The device node must be a child of the node representing the
+Supplemental Configuration Unit (SCFG).
+
+Required properties:
+- compatible: should be "fsl,<soc-name>-extirq", e.g. "fsl,ls1021a-extirq".
+- #interrupt-cells: Must be 2. The first element is the index of the
+ external interrupt line. The second element is the trigger type.
+- #address-cells: Must be 0.
+- interrupt-controller: Identifies the node as an interrupt controller
+- reg: Specifies the Interrupt Polarity Control Register (INTPCR) in
+ the SCFG.
+- interrupt-map: Specifies the mapping from external interrupts to GIC
+ interrupts.
+- interrupt-map-mask: Must be <0xffffffff 0>.
+
+Example:
+ scfg: scfg@1570000 {
+ compatible = "fsl,ls1021a-scfg", "syscon";
+ reg = <0x0 0x1570000 0x0 0x10000>;
+ big-endian;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1570000 0x10000>;
+
+ extirq: interrupt-controller@1ac {
+ compatible = "fsl,ls1021a-extirq";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x1ac 4>;
+ interrupt-map =
+ <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0xffffffff 0x0>;
+ };
+ };
+
+
+ interrupts-extended = <&gic GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <&extirq 1 IRQ_TYPE_LEVEL_LOW>;
--
2.23.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v7 2/2] irqchip: add support for Layerscape external interrupt lines
2019-11-07 12:21 [PATCH v7 0/2] Add support for Layerscape external interrupt lines Rasmus Villemoes
2019-11-07 12:21 ` [PATCH v7 1/2] dt/bindings: Add bindings for Layerscape external irqs Rasmus Villemoes
@ 2019-11-07 12:21 ` Rasmus Villemoes
2019-11-20 13:21 ` [tip: irq/core] irqchip: Add " tip-bot2 for Rasmus Villemoes
2019-11-11 10:24 ` [PATCH v7 0/2] " Marc Zyngier
2 siblings, 1 reply; 10+ messages in thread
From: Rasmus Villemoes @ 2019-11-07 12:21 UTC (permalink / raw)
To: Thomas Gleixner, Jason Cooper, Marc Zyngier, Rob Herring, Mark Rutland
Cc: Rasmus Villemoes, linux-kernel, devicetree, Kurt Kanzenbach
The LS1021A allows inverting the polarity of six interrupt lines
IRQ[0:5] via the scfg_intpcr register, effectively allowing
IRQ_TYPE_LEVEL_LOW and IRQ_TYPE_EDGE_FALLING for those. We just need to
check the type, set the relevant bit in INTPCR accordingly, and fixup
the type argument before calling the GIC's irq_set_type.
In fact, the power-on-reset value of the INTPCR register on the LS1021A
is so that all six lines have their polarity inverted. Hence any
hardware connected to those lines is unusable without this: If the line
is indeed active low, the generic GIC code will reject an irq spec with
IRQ_TYPE_LEVEL_LOW, while if the line is active high, we must obviously
disable the polarity inversion (writing 0 to the relevant bit) before
unmasking the interrupt.
Some other Layerscape SOCs (LS1043A, LS1046A) have a similar feature,
just with a different number of external interrupt lines (and a
different POR value for the INTPCR register). This driver should be
prepared for supporting those by properly filling out the device tree
node. I have the reference manuals for all three boards, but I've only
tested the driver on an LS1021A.
Unfortunately, the Kconfig symbol ARCH_LAYERSCAPE only exists on
arm64, so do as is done for irq-ls-scfg-msi.c: introduce a new symbol
which is set when either ARCH_LAYERSCAPE or SOC_LS1021A is set.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
drivers/irqchip/Kconfig | 4 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-ls-extirq.c | 197 ++++++++++++++++++++++++++++++++
3 files changed, 202 insertions(+)
create mode 100644 drivers/irqchip/irq-ls-extirq.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index ccbb8973a324..bbb323462912 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -370,6 +370,10 @@ config MVEBU_PIC
config MVEBU_SEI
bool
+config LS_EXTIRQ
+ def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
+ select MFD_SYSCON
+
config LS_SCFG_MSI
def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
depends on PCI && PCI_MSI
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index cc7c43932f16..e806dda690ea 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -84,6 +84,7 @@ obj-$(CONFIG_MVEBU_ICU) += irq-mvebu-icu.o
obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o
obj-$(CONFIG_MVEBU_PIC) += irq-mvebu-pic.o
obj-$(CONFIG_MVEBU_SEI) += irq-mvebu-sei.o
+obj-$(CONFIG_LS_EXTIRQ) += irq-ls-extirq.o
obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o
obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o
obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o
diff --git a/drivers/irqchip/irq-ls-extirq.c b/drivers/irqchip/irq-ls-extirq.c
new file mode 100644
index 000000000000..4d1179fed77c
--- /dev/null
+++ b/drivers/irqchip/irq-ls-extirq.c
@@ -0,0 +1,197 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#define pr_fmt(fmt) "irq-ls-extirq: " fmt
+
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqdomain.h>
+#include <linux/of.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#define MAXIRQ 12
+#define LS1021A_SCFGREVCR 0x200
+
+struct ls_extirq_data {
+ struct regmap *syscon;
+ u32 intpcr;
+ bool bit_reverse;
+ u32 nirq;
+ struct irq_fwspec map[MAXIRQ];
+};
+
+static int
+ls_extirq_set_type(struct irq_data *data, unsigned int type)
+{
+ struct ls_extirq_data *priv = data->chip_data;
+ irq_hw_number_t hwirq = data->hwirq;
+ u32 value, mask;
+
+ if (priv->bit_reverse)
+ mask = 1U << (31 - hwirq);
+ else
+ mask = 1U << hwirq;
+
+ switch (type) {
+ case IRQ_TYPE_LEVEL_LOW:
+ type = IRQ_TYPE_LEVEL_HIGH;
+ value = mask;
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ type = IRQ_TYPE_EDGE_RISING;
+ value = mask;
+ break;
+ case IRQ_TYPE_LEVEL_HIGH:
+ case IRQ_TYPE_EDGE_RISING:
+ value = 0;
+ break;
+ default:
+ return -EINVAL;
+ }
+ regmap_update_bits(priv->syscon, priv->intpcr, mask, value);
+
+ return irq_chip_set_type_parent(data, type);
+}
+
+static struct irq_chip ls_extirq_chip = {
+ .name = "ls-extirq",
+ .irq_mask = irq_chip_mask_parent,
+ .irq_unmask = irq_chip_unmask_parent,
+ .irq_eoi = irq_chip_eoi_parent,
+ .irq_set_type = ls_extirq_set_type,
+ .irq_retrigger = irq_chip_retrigger_hierarchy,
+ .irq_set_affinity = irq_chip_set_affinity_parent,
+ .flags = IRQCHIP_SET_TYPE_MASKED,
+};
+
+static int
+ls_extirq_domain_alloc(struct irq_domain *domain, unsigned int virq,
+ unsigned int nr_irqs, void *arg)
+{
+ struct ls_extirq_data *priv = domain->host_data;
+ struct irq_fwspec *fwspec = arg;
+ irq_hw_number_t hwirq;
+
+ if (fwspec->param_count != 2)
+ return -EINVAL;
+
+ hwirq = fwspec->param[0];
+ if (hwirq >= priv->nirq)
+ return -EINVAL;
+
+ irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &ls_extirq_chip,
+ priv);
+
+ return irq_domain_alloc_irqs_parent(domain, virq, 1, &priv->map[hwirq]);
+}
+
+static const struct irq_domain_ops extirq_domain_ops = {
+ .xlate = irq_domain_xlate_twocell,
+ .alloc = ls_extirq_domain_alloc,
+ .free = irq_domain_free_irqs_common,
+};
+
+static int
+ls_extirq_parse_map(struct ls_extirq_data *priv, struct device_node *node)
+{
+ const __be32 *map;
+ u32 mapsize;
+ int ret;
+
+ map = of_get_property(node, "interrupt-map", &mapsize);
+ if (!map)
+ return -ENOENT;
+ if (mapsize % sizeof(*map))
+ return -EINVAL;
+ mapsize /= sizeof(*map);
+
+ while (mapsize) {
+ struct device_node *ipar;
+ u32 hwirq, intsize, j;
+
+ if (mapsize < 3)
+ return -EINVAL;
+ hwirq = be32_to_cpup(map);
+ if (hwirq >= MAXIRQ)
+ return -EINVAL;
+ priv->nirq = max(priv->nirq, hwirq + 1);
+
+ ipar = of_find_node_by_phandle(be32_to_cpup(map + 2));
+ map += 3;
+ mapsize -= 3;
+ if (!ipar)
+ return -EINVAL;
+ priv->map[hwirq].fwnode = &ipar->fwnode;
+ ret = of_property_read_u32(ipar, "#interrupt-cells", &intsize);
+ if (ret)
+ return ret;
+
+ if (intsize > mapsize)
+ return -EINVAL;
+
+ priv->map[hwirq].param_count = intsize;
+ for (j = 0; j < intsize; ++j)
+ priv->map[hwirq].param[j] = be32_to_cpup(map++);
+ mapsize -= intsize;
+ }
+ return 0;
+}
+
+static int __init
+ls_extirq_of_init(struct device_node *node, struct device_node *parent)
+{
+
+ struct irq_domain *domain, *parent_domain;
+ struct ls_extirq_data *priv;
+ int ret;
+
+ parent_domain = irq_find_host(parent);
+ if (!parent_domain) {
+ pr_err("Cannot find parent domain\n");
+ return -ENODEV;
+ }
+
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->syscon = syscon_node_to_regmap(node->parent);
+ if (IS_ERR(priv->syscon)) {
+ ret = PTR_ERR(priv->syscon);
+ pr_err("Failed to lookup parent regmap\n");
+ goto out;
+ }
+ ret = of_property_read_u32(node, "reg", &priv->intpcr);
+ if (ret) {
+ pr_err("Missing INTPCR offset value\n");
+ goto out;
+ }
+
+ ret = ls_extirq_parse_map(priv, node);
+ if (ret)
+ goto out;
+
+ if (of_device_is_compatible(node, "fsl,ls1021a-extirq")) {
+ u32 revcr;
+
+ ret = regmap_read(priv->syscon, LS1021A_SCFGREVCR, &revcr);
+ if (ret)
+ goto out;
+ priv->bit_reverse = (revcr != 0);
+ }
+
+ domain = irq_domain_add_hierarchy(parent_domain, 0, priv->nirq, node,
+ &extirq_domain_ops, priv);
+ if (!domain)
+ ret = -ENOMEM;
+
+out:
+ if (ret)
+ kfree(priv);
+ return ret;
+}
+
+IRQCHIP_DECLARE(ls1021a_extirq, "fsl,ls1021a-extirq", ls_extirq_of_init);
--
2.23.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v7 0/2] Add support for Layerscape external interrupt lines
2019-11-07 12:21 [PATCH v7 0/2] Add support for Layerscape external interrupt lines Rasmus Villemoes
2019-11-07 12:21 ` [PATCH v7 1/2] dt/bindings: Add bindings for Layerscape external irqs Rasmus Villemoes
2019-11-07 12:21 ` [PATCH v7 2/2] irqchip: add support for Layerscape external interrupt lines Rasmus Villemoes
@ 2019-11-11 10:24 ` Marc Zyngier
2019-11-11 10:31 ` Vladimir Oltean
2019-11-12 10:18 ` Rasmus Villemoes
2 siblings, 2 replies; 10+ messages in thread
From: Marc Zyngier @ 2019-11-11 10:24 UTC (permalink / raw)
To: Rasmus Villemoes
Cc: Thomas Gleixner, Jason Cooper, Rob Herring, Mark Rutland,
linux-kernel, devicetree, Kurt Kanzenbach
On 2019-11-07 13:30, Rasmus Villemoes wrote:
> In v7, I've tried to change from a custom binding to use
> interrupt-map, modelled on the recent addition of the
> renesas,rza1-irqc (commits a644ccb819bc and 5e27a314a11f). It's
> possible that the interrupt-map parsing code can be factored to a
> common helper, but it's a bit hard to generalize from two examples to
> know what a good interface would look like.
>
> The interrupt-map-mask is a bit arbitrary. 0xff would likely work
> just
> as well (but I think the ls2088a has 32 external lines, so it has to
> be a least 0x1f).
>
> Also, this drops the fsl,bit-reverse property and instead reads the
> SCFGREVCR register to determine if bit-reversing is needed.
>
> The dt/bindings patch now comes first in accordance with
> Documentation/devicetree/bindings/submitting-patches.txt.
>
> Earlier versions can be found here:
>
> v6:
> https://lore.kernel.org/lkml/20190923101513.32719-1-kurt@linutronix.de/
> v5:
>
> https://lore.kernel.org/lkml/20180223210901.23480-1-rasmus.villemoes@prevas.dk/
>
> Rasmus Villemoes (2):
> dt/bindings: Add bindings for Layerscape external irqs
> irqchip: add support for Layerscape external interrupt lines
>
> .../interrupt-controller/fsl,ls-extirq.txt | 49 +++++
> drivers/irqchip/Kconfig | 4 +
> drivers/irqchip/Makefile | 1 +
> drivers/irqchip/irq-ls-extirq.c | 197
> ++++++++++++++++++
> 4 files changed, 251 insertions(+)
> create mode 100644
>
> Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt
> create mode 100644 drivers/irqchip/irq-ls-extirq.c
Applied to irqchip-next.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v7 0/2] Add support for Layerscape external interrupt lines
2019-11-11 10:24 ` [PATCH v7 0/2] " Marc Zyngier
@ 2019-11-11 10:31 ` Vladimir Oltean
2019-11-12 10:18 ` Rasmus Villemoes
1 sibling, 0 replies; 10+ messages in thread
From: Vladimir Oltean @ 2019-11-11 10:31 UTC (permalink / raw)
To: Marc Zyngier
Cc: Rasmus Villemoes, Thomas Gleixner, Jason Cooper, Rob Herring,
Mark Rutland, lkml, devicetree, Kurt Kanzenbach
On Mon, 11 Nov 2019 at 12:24, Marc Zyngier <maz@kernel.org> wrote:
>
> On 2019-11-07 13:30, Rasmus Villemoes wrote:
> > In v7, I've tried to change from a custom binding to use
> > interrupt-map, modelled on the recent addition of the
> > renesas,rza1-irqc (commits a644ccb819bc and 5e27a314a11f). It's
> > possible that the interrupt-map parsing code can be factored to a
> > common helper, but it's a bit hard to generalize from two examples to
> > know what a good interface would look like.
> >
> > The interrupt-map-mask is a bit arbitrary. 0xff would likely work
> > just
> > as well (but I think the ls2088a has 32 external lines, so it has to
> > be a least 0x1f).
> >
> > Also, this drops the fsl,bit-reverse property and instead reads the
> > SCFGREVCR register to determine if bit-reversing is needed.
> >
> > The dt/bindings patch now comes first in accordance with
> > Documentation/devicetree/bindings/submitting-patches.txt.
> >
> > Earlier versions can be found here:
> >
> > v6:
> > https://lore.kernel.org/lkml/20190923101513.32719-1-kurt@linutronix.de/
> > v5:
> >
> > https://lore.kernel.org/lkml/20180223210901.23480-1-rasmus.villemoes@prevas.dk/
> >
> > Rasmus Villemoes (2):
> > dt/bindings: Add bindings for Layerscape external irqs
> > irqchip: add support for Layerscape external interrupt lines
> >
> > .../interrupt-controller/fsl,ls-extirq.txt | 49 +++++
> > drivers/irqchip/Kconfig | 4 +
> > drivers/irqchip/Makefile | 1 +
> > drivers/irqchip/irq-ls-extirq.c | 197
> > ++++++++++++++++++
> > 4 files changed, 251 insertions(+)
> > create mode 100644
> >
> > Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt
> > create mode 100644 drivers/irqchip/irq-ls-extirq.c
>
> Applied to irqchip-next.
>
> Thanks,
>
> M.
> --
> Jazz is not dead. It just smells funny...
A bit late, but for what it's worth,
Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Background: https://www.spinics.net/lists/netdev/msg611505.html
Thanks,
-Vladimir
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v7 0/2] Add support for Layerscape external interrupt lines
2019-11-11 10:24 ` [PATCH v7 0/2] " Marc Zyngier
2019-11-11 10:31 ` Vladimir Oltean
@ 2019-11-12 10:18 ` Rasmus Villemoes
2019-11-12 10:58 ` Marc Zyngier
1 sibling, 1 reply; 10+ messages in thread
From: Rasmus Villemoes @ 2019-11-12 10:18 UTC (permalink / raw)
To: Marc Zyngier
Cc: Thomas Gleixner, Jason Cooper, Rob Herring, Mark Rutland,
linux-kernel, devicetree, Kurt Kanzenbach, Vladimir Oltean
On 11/11/2019 11.24, Marc Zyngier wrote:
> On 2019-11-07 13:30, Rasmus Villemoes wrote:
>> Rasmus Villemoes (2):
>> dt/bindings: Add bindings for Layerscape external irqs
>> irqchip: add support for Layerscape external interrupt lines
>>
>> .../interrupt-controller/fsl,ls-extirq.txt | 49 +++++
>> drivers/irqchip/Kconfig | 4 +
>> drivers/irqchip/Makefile | 1 +
>> drivers/irqchip/irq-ls-extirq.c | 197 ++++++++++++++++++
>> 4 files changed, 251 insertions(+)
>> create mode 100644
>>
>> Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt
>> create mode 100644 drivers/irqchip/irq-ls-extirq.c
>
> Applied to irqchip-next.
Thanks! Can I assume that branch doesn't get rebased so 87cd38dfd9e6 is
a stable SHA1? I want to send a patch adding the node to ls1021a.dtsi,
and I hope not to have to wait another release cycle.
Rasmus
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v7 0/2] Add support for Layerscape external interrupt lines
2019-11-12 10:18 ` Rasmus Villemoes
@ 2019-11-12 10:58 ` Marc Zyngier
2019-11-12 11:44 ` Rasmus Villemoes
0 siblings, 1 reply; 10+ messages in thread
From: Marc Zyngier @ 2019-11-12 10:58 UTC (permalink / raw)
To: Rasmus Villemoes
Cc: Thomas Gleixner, Jason Cooper, Rob Herring, Mark Rutland,
linux-kernel, devicetree, Kurt Kanzenbach, Vladimir Oltean
On 2019-11-12 11:27, Rasmus Villemoes wrote:
> On 11/11/2019 11.24, Marc Zyngier wrote:
>> On 2019-11-07 13:30, Rasmus Villemoes wrote:
>
>>> Rasmus Villemoes (2):
>>> dt/bindings: Add bindings for Layerscape external irqs
>>> irqchip: add support for Layerscape external interrupt lines
>>>
>>> .../interrupt-controller/fsl,ls-extirq.txt | 49 +++++
>>> drivers/irqchip/Kconfig | 4 +
>>> drivers/irqchip/Makefile | 1 +
>>> drivers/irqchip/irq-ls-extirq.c | 197
>>> ++++++++++++++++++
>>> 4 files changed, 251 insertions(+)
>>> create mode 100644
>>>
>>>
>>> Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt
>>> create mode 100644 drivers/irqchip/irq-ls-extirq.c
>>
>> Applied to irqchip-next.
>
> Thanks! Can I assume that branch doesn't get rebased so 87cd38dfd9e6
> is
> a stable SHA1? I want to send a patch adding the node to
> ls1021a.dtsi,
> and I hope not to have to wait another release cycle.
I usually try to avoid rebasing it, unless something really bad shows
up.
Now, just adding a node to a DT shouldn't break anything, right? You
should be able to do that change and get things working magically once
this code hits mainline.
Or am I missing something?
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v7 0/2] Add support for Layerscape external interrupt lines
2019-11-12 10:58 ` Marc Zyngier
@ 2019-11-12 11:44 ` Rasmus Villemoes
0 siblings, 0 replies; 10+ messages in thread
From: Rasmus Villemoes @ 2019-11-12 11:44 UTC (permalink / raw)
To: Marc Zyngier
Cc: Thomas Gleixner, Jason Cooper, Rob Herring, Mark Rutland,
linux-kernel, devicetree, Kurt Kanzenbach, Vladimir Oltean
On 12/11/2019 11.58, Marc Zyngier wrote:
> On 2019-11-12 11:27, Rasmus Villemoes wrote:
>> On 11/11/2019 11.24, Marc Zyngier wrote:
>>> Applied to irqchip-next.
>>
>> Thanks! Can I assume that branch doesn't get rebased so 87cd38dfd9e6 is
>> a stable SHA1? I want to send a patch adding the node to ls1021a.dtsi,
>> and I hope not to have to wait another release cycle.
>
> I usually try to avoid rebasing it, unless something really bad shows up.
>
> Now, just adding a node to a DT shouldn't break anything, right? You
> should be able to do that change and get things working magically once
> this code hits mainline.
Well, yes, but I wanted to refer to the binding documentation in the
form of a reference to that SHA1. But I suppose I can just do that in
the cover letter or below ---.
Thanks,
Rasmus
^ permalink raw reply [flat|nested] 10+ messages in thread
* [tip: irq/core] dt/bindings: Add bindings for Layerscape external irqs
2019-11-07 12:21 ` [PATCH v7 1/2] dt/bindings: Add bindings for Layerscape external irqs Rasmus Villemoes
@ 2019-11-20 13:21 ` tip-bot2 for Rasmus Villemoes
0 siblings, 0 replies; 10+ messages in thread
From: tip-bot2 for Rasmus Villemoes @ 2019-11-20 13:21 UTC (permalink / raw)
To: linux-tip-commits
Cc: Rasmus Villemoes, Marc Zyngier, Ingo Molnar, Borislav Petkov,
linux-kernel
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 87cd38dfd9e67ffa7c3d3d1a54a2482ed23f1307
Gitweb: https://git.kernel.org/tip/87cd38dfd9e67ffa7c3d3d1a54a2482ed23f1307
Author: Rasmus Villemoes <linux@rasmusvillemoes.dk>
AuthorDate: Thu, 07 Nov 2019 13:21:14 +01:00
Committer: Marc Zyngier <maz@kernel.org>
CommitterDate: Sun, 10 Nov 2019 18:47:48
dt/bindings: Add bindings for Layerscape external irqs
This adds Device Tree binding documentation for the external interrupt
lines with configurable polarity present on some Layerscape SOCs.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20191107122115.6244-2-linux@rasmusvillemoes.dk
---
Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt | 49 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt
diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt
new file mode 100644
index 0000000..f0ad780
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt
@@ -0,0 +1,49 @@
+* Freescale Layerscape external IRQs
+
+Some Layerscape SOCs (LS1021A, LS1043A, LS1046A) support inverting
+the polarity of certain external interrupt lines.
+
+The device node must be a child of the node representing the
+Supplemental Configuration Unit (SCFG).
+
+Required properties:
+- compatible: should be "fsl,<soc-name>-extirq", e.g. "fsl,ls1021a-extirq".
+- #interrupt-cells: Must be 2. The first element is the index of the
+ external interrupt line. The second element is the trigger type.
+- #address-cells: Must be 0.
+- interrupt-controller: Identifies the node as an interrupt controller
+- reg: Specifies the Interrupt Polarity Control Register (INTPCR) in
+ the SCFG.
+- interrupt-map: Specifies the mapping from external interrupts to GIC
+ interrupts.
+- interrupt-map-mask: Must be <0xffffffff 0>.
+
+Example:
+ scfg: scfg@1570000 {
+ compatible = "fsl,ls1021a-scfg", "syscon";
+ reg = <0x0 0x1570000 0x0 0x10000>;
+ big-endian;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1570000 0x10000>;
+
+ extirq: interrupt-controller@1ac {
+ compatible = "fsl,ls1021a-extirq";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x1ac 4>;
+ interrupt-map =
+ <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0xffffffff 0x0>;
+ };
+ };
+
+
+ interrupts-extended = <&gic GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <&extirq 1 IRQ_TYPE_LEVEL_LOW>;
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [tip: irq/core] irqchip: Add support for Layerscape external interrupt lines
2019-11-07 12:21 ` [PATCH v7 2/2] irqchip: add support for Layerscape external interrupt lines Rasmus Villemoes
@ 2019-11-20 13:21 ` tip-bot2 for Rasmus Villemoes
0 siblings, 0 replies; 10+ messages in thread
From: tip-bot2 for Rasmus Villemoes @ 2019-11-20 13:21 UTC (permalink / raw)
To: linux-tip-commits
Cc: Rasmus Villemoes, Marc Zyngier, Ingo Molnar, Borislav Petkov,
linux-kernel
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 0dcd9f872769547f336741880bc7e721149c8d0a
Gitweb: https://git.kernel.org/tip/0dcd9f872769547f336741880bc7e721149c8d0a
Author: Rasmus Villemoes <linux@rasmusvillemoes.dk>
AuthorDate: Thu, 07 Nov 2019 13:21:15 +01:00
Committer: Marc Zyngier <maz@kernel.org>
CommitterDate: Sun, 10 Nov 2019 18:47:49
irqchip: Add support for Layerscape external interrupt lines
The LS1021A allows inverting the polarity of six interrupt lines
IRQ[0:5] via the scfg_intpcr register, effectively allowing
IRQ_TYPE_LEVEL_LOW and IRQ_TYPE_EDGE_FALLING for those. We just need to
check the type, set the relevant bit in INTPCR accordingly, and fixup
the type argument before calling the GIC's irq_set_type.
In fact, the power-on-reset value of the INTPCR register on the LS1021A
is so that all six lines have their polarity inverted. Hence any
hardware connected to those lines is unusable without this: If the line
is indeed active low, the generic GIC code will reject an irq spec with
IRQ_TYPE_LEVEL_LOW, while if the line is active high, we must obviously
disable the polarity inversion (writing 0 to the relevant bit) before
unmasking the interrupt.
Some other Layerscape SOCs (LS1043A, LS1046A) have a similar feature,
just with a different number of external interrupt lines (and a
different POR value for the INTPCR register). This driver should be
prepared for supporting those by properly filling out the device tree
node. I have the reference manuals for all three boards, but I've only
tested the driver on an LS1021A.
Unfortunately, the Kconfig symbol ARCH_LAYERSCAPE only exists on
arm64, so do as is done for irq-ls-scfg-msi.c: introduce a new symbol
which is set when either ARCH_LAYERSCAPE or SOC_LS1021A is set.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20191107122115.6244-3-linux@rasmusvillemoes.dk
---
drivers/irqchip/Kconfig | 4 +-
drivers/irqchip/Makefile | 1 +-
drivers/irqchip/irq-ls-extirq.c | 197 +++++++++++++++++++++++++++++++-
3 files changed, 202 insertions(+)
create mode 100644 drivers/irqchip/irq-ls-extirq.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index ccbb897..bbb3234 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -370,6 +370,10 @@ config MVEBU_PIC
config MVEBU_SEI
bool
+config LS_EXTIRQ
+ def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
+ select MFD_SYSCON
+
config LS_SCFG_MSI
def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
depends on PCI && PCI_MSI
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index cc7c439..e806dda 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -84,6 +84,7 @@ obj-$(CONFIG_MVEBU_ICU) += irq-mvebu-icu.o
obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o
obj-$(CONFIG_MVEBU_PIC) += irq-mvebu-pic.o
obj-$(CONFIG_MVEBU_SEI) += irq-mvebu-sei.o
+obj-$(CONFIG_LS_EXTIRQ) += irq-ls-extirq.o
obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o
obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o
obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o
diff --git a/drivers/irqchip/irq-ls-extirq.c b/drivers/irqchip/irq-ls-extirq.c
new file mode 100644
index 0000000..4d1179f
--- /dev/null
+++ b/drivers/irqchip/irq-ls-extirq.c
@@ -0,0 +1,197 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#define pr_fmt(fmt) "irq-ls-extirq: " fmt
+
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqdomain.h>
+#include <linux/of.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#define MAXIRQ 12
+#define LS1021A_SCFGREVCR 0x200
+
+struct ls_extirq_data {
+ struct regmap *syscon;
+ u32 intpcr;
+ bool bit_reverse;
+ u32 nirq;
+ struct irq_fwspec map[MAXIRQ];
+};
+
+static int
+ls_extirq_set_type(struct irq_data *data, unsigned int type)
+{
+ struct ls_extirq_data *priv = data->chip_data;
+ irq_hw_number_t hwirq = data->hwirq;
+ u32 value, mask;
+
+ if (priv->bit_reverse)
+ mask = 1U << (31 - hwirq);
+ else
+ mask = 1U << hwirq;
+
+ switch (type) {
+ case IRQ_TYPE_LEVEL_LOW:
+ type = IRQ_TYPE_LEVEL_HIGH;
+ value = mask;
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ type = IRQ_TYPE_EDGE_RISING;
+ value = mask;
+ break;
+ case IRQ_TYPE_LEVEL_HIGH:
+ case IRQ_TYPE_EDGE_RISING:
+ value = 0;
+ break;
+ default:
+ return -EINVAL;
+ }
+ regmap_update_bits(priv->syscon, priv->intpcr, mask, value);
+
+ return irq_chip_set_type_parent(data, type);
+}
+
+static struct irq_chip ls_extirq_chip = {
+ .name = "ls-extirq",
+ .irq_mask = irq_chip_mask_parent,
+ .irq_unmask = irq_chip_unmask_parent,
+ .irq_eoi = irq_chip_eoi_parent,
+ .irq_set_type = ls_extirq_set_type,
+ .irq_retrigger = irq_chip_retrigger_hierarchy,
+ .irq_set_affinity = irq_chip_set_affinity_parent,
+ .flags = IRQCHIP_SET_TYPE_MASKED,
+};
+
+static int
+ls_extirq_domain_alloc(struct irq_domain *domain, unsigned int virq,
+ unsigned int nr_irqs, void *arg)
+{
+ struct ls_extirq_data *priv = domain->host_data;
+ struct irq_fwspec *fwspec = arg;
+ irq_hw_number_t hwirq;
+
+ if (fwspec->param_count != 2)
+ return -EINVAL;
+
+ hwirq = fwspec->param[0];
+ if (hwirq >= priv->nirq)
+ return -EINVAL;
+
+ irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &ls_extirq_chip,
+ priv);
+
+ return irq_domain_alloc_irqs_parent(domain, virq, 1, &priv->map[hwirq]);
+}
+
+static const struct irq_domain_ops extirq_domain_ops = {
+ .xlate = irq_domain_xlate_twocell,
+ .alloc = ls_extirq_domain_alloc,
+ .free = irq_domain_free_irqs_common,
+};
+
+static int
+ls_extirq_parse_map(struct ls_extirq_data *priv, struct device_node *node)
+{
+ const __be32 *map;
+ u32 mapsize;
+ int ret;
+
+ map = of_get_property(node, "interrupt-map", &mapsize);
+ if (!map)
+ return -ENOENT;
+ if (mapsize % sizeof(*map))
+ return -EINVAL;
+ mapsize /= sizeof(*map);
+
+ while (mapsize) {
+ struct device_node *ipar;
+ u32 hwirq, intsize, j;
+
+ if (mapsize < 3)
+ return -EINVAL;
+ hwirq = be32_to_cpup(map);
+ if (hwirq >= MAXIRQ)
+ return -EINVAL;
+ priv->nirq = max(priv->nirq, hwirq + 1);
+
+ ipar = of_find_node_by_phandle(be32_to_cpup(map + 2));
+ map += 3;
+ mapsize -= 3;
+ if (!ipar)
+ return -EINVAL;
+ priv->map[hwirq].fwnode = &ipar->fwnode;
+ ret = of_property_read_u32(ipar, "#interrupt-cells", &intsize);
+ if (ret)
+ return ret;
+
+ if (intsize > mapsize)
+ return -EINVAL;
+
+ priv->map[hwirq].param_count = intsize;
+ for (j = 0; j < intsize; ++j)
+ priv->map[hwirq].param[j] = be32_to_cpup(map++);
+ mapsize -= intsize;
+ }
+ return 0;
+}
+
+static int __init
+ls_extirq_of_init(struct device_node *node, struct device_node *parent)
+{
+
+ struct irq_domain *domain, *parent_domain;
+ struct ls_extirq_data *priv;
+ int ret;
+
+ parent_domain = irq_find_host(parent);
+ if (!parent_domain) {
+ pr_err("Cannot find parent domain\n");
+ return -ENODEV;
+ }
+
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->syscon = syscon_node_to_regmap(node->parent);
+ if (IS_ERR(priv->syscon)) {
+ ret = PTR_ERR(priv->syscon);
+ pr_err("Failed to lookup parent regmap\n");
+ goto out;
+ }
+ ret = of_property_read_u32(node, "reg", &priv->intpcr);
+ if (ret) {
+ pr_err("Missing INTPCR offset value\n");
+ goto out;
+ }
+
+ ret = ls_extirq_parse_map(priv, node);
+ if (ret)
+ goto out;
+
+ if (of_device_is_compatible(node, "fsl,ls1021a-extirq")) {
+ u32 revcr;
+
+ ret = regmap_read(priv->syscon, LS1021A_SCFGREVCR, &revcr);
+ if (ret)
+ goto out;
+ priv->bit_reverse = (revcr != 0);
+ }
+
+ domain = irq_domain_add_hierarchy(parent_domain, 0, priv->nirq, node,
+ &extirq_domain_ops, priv);
+ if (!domain)
+ ret = -ENOMEM;
+
+out:
+ if (ret)
+ kfree(priv);
+ return ret;
+}
+
+IRQCHIP_DECLARE(ls1021a_extirq, "fsl,ls1021a-extirq", ls_extirq_of_init);
^ permalink raw reply related [flat|nested] 10+ messages in thread
end of thread, other threads:[~2019-11-20 13:22 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-11-07 12:21 [PATCH v7 0/2] Add support for Layerscape external interrupt lines Rasmus Villemoes
2019-11-07 12:21 ` [PATCH v7 1/2] dt/bindings: Add bindings for Layerscape external irqs Rasmus Villemoes
2019-11-20 13:21 ` [tip: irq/core] " tip-bot2 for Rasmus Villemoes
2019-11-07 12:21 ` [PATCH v7 2/2] irqchip: add support for Layerscape external interrupt lines Rasmus Villemoes
2019-11-20 13:21 ` [tip: irq/core] irqchip: Add " tip-bot2 for Rasmus Villemoes
2019-11-11 10:24 ` [PATCH v7 0/2] " Marc Zyngier
2019-11-11 10:31 ` Vladimir Oltean
2019-11-12 10:18 ` Rasmus Villemoes
2019-11-12 10:58 ` Marc Zyngier
2019-11-12 11:44 ` Rasmus Villemoes
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