[PATCH 0/8] nvmem: sfp: binding updates and additions

[PATCH 0/8] nvmem: sfp: binding updates and additions

[Sean Anderson]

This adds several properties to the Layerscape Security Fuse Processor
(SFP) necessary for writing. Although the Linux driver does not use
these bindings, I plan to use them in U-Boot [1]. It also adds a new
compatibles for Trust Architecture (TA) 2.1 devices. In addition, it
also adds an SFP binding for all TA 2.1 and 3.0 devices.

[1] https://lore.kernel.org/u-boot/7c8e206a-cd40-2a77-6282-7f4bead2b13a@seco.com/T/#m591f8425b6f096ab3d54e6f7bd258e41cfa4c43b


Sean Anderson (8):
  dt-bindings: nvmem: sfp: Fix typo
  dt-bindings: nvmem: sfp: Add clock properties
  dt-bindings: nvmem: sfp: Add TA_PROG_SFP supply
  dt-bindings: nvmem: sfp: Add compatible binding for TA 2.1 SFPs
  arm64: dts: ls1028a: Update SFP binding to include clock
  ARM: dts: layerscape: Add SFP binding for TA 2.1 devices
  ARM: dts: Add SFP binding for TA 3.0 devices
  nvmem: sfp: Add support for TA 2.1 devices

 .../bindings/nvmem/fsl,layerscape-sfp.yaml    | 30 +++++++++++++++++--
 arch/arm/boot/dts/ls1021a.dtsi                |  7 +++++
 .../arm64/boot/dts/freescale/fsl-ls1012a.dtsi |  8 +++++
 .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi |  5 +++-
 .../arm64/boot/dts/freescale/fsl-ls1043a.dtsi |  8 +++++
 .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi |  8 +++++
 .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi |  8 +++++
 .../arm64/boot/dts/freescale/fsl-ls208xa.dtsi |  8 +++++
 .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi |  8 +++++
 drivers/nvmem/layerscape-sfp.c                |  1 +
 10 files changed, 87 insertions(+), 4 deletions(-)

-- 
2.35.1.1320.gc452695387.dirty

[PATCH 1/8] dt-bindings: nvmem: sfp: Fix typo

[Sean Anderson]

There is a small gramattical error in the description. Fix it.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---

 Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
index 80914b93638e..b7798e903191 100644
--- a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
+++ b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
@@ -10,7 +10,7 @@ maintainers:
   - Michael Walle <michael@walle.cc>
 
 description: |
-  SFP is the security fuse processor which among other things provide a
+  SFP is the security fuse processor which among other things provides a
   unique identifier per part.
 
 allOf:
-- 
2.35.1.1320.gc452695387.dirty

[PATCH 2/8] dt-bindings: nvmem: sfp: Add clock properties

[Sean Anderson]

To program fuses, it is necessary to set the fuse programming time. This
is determined based on the value of the platform clock. Add a clock
property.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---

 .../bindings/nvmem/fsl,layerscape-sfp.yaml         | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
index b7798e903191..54086f50157d 100644
--- a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
+++ b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
@@ -24,15 +24,29 @@ properties:
   reg:
     maxItems: 1
 
+  clocks:
+    maxItems: 1
+    description:
+      The SFP clock. Typically, this is the platform clock divided by 4.
+
+  clock-names:
+    const: sfp
+
 required:
   - compatible
   - reg
+  - clock-names
+  - clocks
 
 unevaluatedProperties: false
 
 examples:
   - |
+    #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
     efuse@1e80000 {
         compatible = "fsl,ls1028a-sfp";
         reg = <0x1e80000 0x8000>;
+        clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+                            QORIQ_CLK_PLL_DIV(4)>;
+        clock-names = "sfp";
     };
-- 
2.35.1.1320.gc452695387.dirty

[PATCH 3/8] dt-bindings: nvmem: sfp: Add TA_PROG_SFP supply

[Sean Anderson]

The TA_PROG_SFP supply must be enabled to program the fuses, and
disabled to read the fuses (such as at power-on-reset). On many boards,
this supply is controlled by a jumper. The user must manually insert or
remove it at the appropriate time in the programming process. However,
on other boards this supply is controlled by and FPGA or a GPIO. In
these cases, the driver can automatically enabled and disable it as
necessary.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---

 .../devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml        | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
index 54086f50157d..e7d1232fcd41 100644
--- a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
+++ b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
@@ -32,6 +32,11 @@ properties:
   clock-names:
     const: sfp
 
+  ta-prog-sfp-supply:
+    description:
+      The TA_PROG_SFP supply. It will be enabled for programming and disabled
+      for reading.
+
 required:
   - compatible
   - reg
-- 
2.35.1.1320.gc452695387.dirty

[PATCH 4/8] dt-bindings: nvmem: sfp: Add compatible binding for TA 2.1 SFPs

[Sean Anderson]

Trust Architecture (TA) 2.1 devices include the LS1012A, LS1021A,
LS1043A, and LS1046A. The SFP device on TA 2.1 devices is very similar
to the SFP on TA 3.0 devices. The primary difference is a few fields in
the control register. Add a compatible string.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---

 .../devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml    | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
index e7d1232fcd41..aa277f1eee7e 100644
--- a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
+++ b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
@@ -18,8 +18,13 @@ allOf:
 
 properties:
   compatible:
-    enum:
-      - fsl,ls1028a-sfp
+    oneOf:
+      - description: Trust architecture 2.1 SFP
+        items:
+          - const: fsl,ls1021a-sfp
+      - description: Trust architecture 3.0 SFP
+        items:
+          - const: fsl,ls1028a-sfp
 
   reg:
     maxItems: 1
-- 
2.35.1.1320.gc452695387.dirty

[PATCH 5/8] arm64: dts: ls1028a: Update SFP binding to include clock

[Sean Anderson]

The clocks property is now mandatory. Add it.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---

 arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 088271d49139..59b289b52a28 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -224,9 +224,12 @@ rst: syscon@1e60000 {
 			little-endian;
 		};
 
-		efuse@1e80000 {
+		sfp: efuse@1e80000 {
 			compatible = "fsl,ls1028a-sfp";
 			reg = <0x0 0x1e80000 0x0 0x10000>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(4)>;
+			clock-names = "sfp";
 			#address-cells = <1>;
 			#size-cells = <1>;
 
-- 
2.35.1.1320.gc452695387.dirty

[PATCH 6/8] ARM: dts: layerscape: Add SFP binding for TA 2.1 devices

[Sean Anderson]

This adds an appropriate SFP binding for Trust Architecture 2.1 devices.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---

 arch/arm/boot/dts/ls1021a.dtsi                 | 7 +++++++
 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 8 ++++++++
 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 8 ++++++++
 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 8 ++++++++
 4 files changed, 31 insertions(+)

diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 2e69d6eab4d1..c1e94a317cba 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -129,6 +129,13 @@ ifc: ifc@1530000 {
 			status = "disabled";
 		};
 
+		sfp: efuse@1e80000 {
+			compatible = "fsl,ls1021a-sfp";
+			reg = <0x0 0x1e80000 0x0 0x10000>;
+			clocks = <&clockgen 4 3>;
+			clock-names = "sfp";
+		};
+
 		dcfg: dcfg@1ee0000 {
 			compatible = "fsl,ls1021a-dcfg", "syscon";
 			reg = <0x0 0x1ee0000 0x0 0x1000>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
index 50a72cda4727..47ce525e0a72 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -271,6 +271,14 @@ rtic_d: rtic-d@60 {
 			};
 		};
 
+		sfp: efuse@1e80000 {
+			compatible = "fsl,ls1021a-sfp";
+			reg = <0x0 0x1e80000 0x0 0x10000>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(4)>;
+			clock-names = "sfp";
+		};
+
 		sec_mon: sec_mon@1e90000 {
 			compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
 				     "fsl,sec-v4.0-mon";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 35d1939e690b..b0ab0b19de7e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -383,6 +383,14 @@ sec_jr3: jr@40000 {
 			};
 		};
 
+		sfp: efuse@1e80000 {
+			compatible = "fsl,ls1021a-sfp";
+			reg = <0x0 0x1e80000 0x0 0x10000>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(4)>;
+			clock-names = "sfp";
+		};
+
 		dcfg: dcfg@1ee0000 {
 			compatible = "fsl,ls1043a-dcfg", "syscon";
 			reg = <0x0 0x1ee0000 0x0 0x10000>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 4e7bd04d9798..c30056afc02a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -413,6 +413,14 @@ bportals: bman-portals@508000000 {
 			ranges = <0x0 0x5 0x08000000 0x8000000>;
 		};
 
+		sfp: efuse@1e80000 {
+			compatible = "fsl,ls1021a-sfp";
+			reg = <0x0 0x1e80000 0x0 0x10000>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(4)>;
+			clock-names = "sfp";
+		};
+
 		dcfg: dcfg@1ee0000 {
 			compatible = "fsl,ls1046a-dcfg", "syscon";
 			reg = <0x0 0x1ee0000 0x0 0x1000>;
-- 
2.35.1.1320.gc452695387.dirty

[PATCH 7/8] ARM: dts: Add SFP binding for TA 3.0 devices

[Sean Anderson]

This adds an SFP binding for Trust Architecture 3.0 devices.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---

 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 8 ++++++++
 arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 8 ++++++++
 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 8 ++++++++
 3 files changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index 18e529118476..1a58e8671047 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -269,6 +269,14 @@ extirq: interrupt-controller@14 {
 			};
 		};
 
+		sfp: efuse@1e80000 {
+			compatible = "fsl,ls1028a-sfp";
+			reg = <0x0 0x1e80000 0x0 0x10000>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(4)>;
+			clock-names = "sfp";
+		};
+
 		tmu: tmu@1f80000 {
 			compatible = "fsl,qoriq-tmu";
 			reg = <0x0 0x1f80000 0x0 0x10000>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index 1282b61da8a5..5705ec554bf9 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -278,6 +278,14 @@ dcfg: dcfg@1e00000 {
 			little-endian;
 		};
 
+		sfp: efuse@1e80000 {
+			compatible = "fsl,ls1028a-sfp";
+			reg = <0x0 0x1e80000 0x0 0x10000>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(4)>;
+			clock-names = "sfp";
+		};
+
 		isc: syscon@1f70000 {
 			compatible = "fsl,ls2080a-isc", "syscon";
 			reg = <0x0 0x1f70000 0x0 0x10000>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index c5daa15b020d..53dd8c7dc048 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -671,6 +671,14 @@ dcfg: syscon@1e00000 {
 			little-endian;
 		};
 
+		sfp: efuse@1e80000 {
+			compatible = "fsl,ls1028a-sfp";
+			reg = <0x0 0x1e80000 0x0 0x10000>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(4)>;
+			clock-names = "sfp";
+		};
+
 		isc: syscon@1f70000 {
 			compatible = "fsl,lx2160a-isc", "syscon";
 			reg = <0x0 0x1f70000 0x0 0x10000>;
-- 
2.35.1.1320.gc452695387.dirty

[PATCH 8/8] nvmem: sfp: Add support for TA 2.1 devices

[Sean Anderson]

This adds support for Trust Architecture (TA) 2.1 devices to the SFP driver.
There are few differences between TA 2.1 and TA 3.0, especially for
read-only support, so just re-use the existing data.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---

 drivers/nvmem/layerscape-sfp.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/nvmem/layerscape-sfp.c b/drivers/nvmem/layerscape-sfp.c
index e591c1511e33..6336be5d8726 100644
--- a/drivers/nvmem/layerscape-sfp.c
+++ b/drivers/nvmem/layerscape-sfp.c
@@ -70,6 +70,7 @@ static const struct layerscape_sfp_data ls1028a_data = {
 };
 
 static const struct of_device_id layerscape_sfp_dt_ids[] = {
+	{ .compatible = "fsl,ls1021a-sfp", .data = &ls1028a_data },
 	{ .compatible = "fsl,ls1028a-sfp", .data = &ls1028a_data },
 	{},
 };
-- 
2.35.1.1320.gc452695387.dirty

Re: [PATCH 1/8] dt-bindings: nvmem: sfp: Fix typo

[Michael Walle]

Am 2022-04-21 19:56, schrieb Sean Anderson:
> There is a small gramattical error in the description. Fix it.
> 
> Signed-off-by: Sean Anderson <sean.anderson@seco.com>

Reviewed-by: Michael Walle <michael@walle.cc>

Re: [PATCH 2/8] dt-bindings: nvmem: sfp: Add clock properties

[Michael Walle]

Am 2022-04-21 19:56, schrieb Sean Anderson:
> To program fuses, it is necessary to set the fuse programming time. 
> This
> is determined based on the value of the platform clock. Add a clock
> property.

For some context: Sean was adding the SFP support in u-boot and
I referred him to this binding. I didn't need the clock to just
read the data. But Sean is right, we need the clock for the
programming. I was unaware of that. The binding is still yet to
be released with v5.18, thus I think it is still possible to make
the clock mandatory.

> Signed-off-by: Sean Anderson <sean.anderson@seco.com>

Fixes: 6f9817cdcc82 ("dt-bindings: nvmem: add fsl,layerscape-sfp 
binding")

-michael

> ---
> 
>  .../bindings/nvmem/fsl,layerscape-sfp.yaml         | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git
> a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
> b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
> index b7798e903191..54086f50157d 100644
> --- a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
> +++ b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
> @@ -24,15 +24,29 @@ properties:
>    reg:
>      maxItems: 1
> 
> +  clocks:
> +    maxItems: 1
> +    description:
> +      The SFP clock. Typically, this is the platform clock divided by 
> 4.
> +
> +  clock-names:
> +    const: sfp
> +
>  required:
>    - compatible
>    - reg
> +  - clock-names
> +  - clocks
> 
>  unevaluatedProperties: false
> 
>  examples:
>    - |
> +    #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
>      efuse@1e80000 {
>          compatible = "fsl,ls1028a-sfp";
>          reg = <0x1e80000 0x8000>;
> +        clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> +                            QORIQ_CLK_PLL_DIV(4)>;
> +        clock-names = "sfp";
>      };

Re: [PATCH 4/8] dt-bindings: nvmem: sfp: Add compatible binding for TA 2.1 SFPs

[Michael Walle]

Am 2022-04-21 19:56, schrieb Sean Anderson:
> Trust Architecture (TA) 2.1 devices include the LS1012A, LS1021A,
> LS1043A, and LS1046A. The SFP device on TA 2.1 devices is very similar
> to the SFP on TA 3.0 devices. The primary difference is a few fields in
> the control register. Add a compatible string.
> 
> Signed-off-by: Sean Anderson <sean.anderson@seco.com>
> ---
> 
>  .../devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml    | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git
> a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
> b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
> index e7d1232fcd41..aa277f1eee7e 100644
> --- a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
> +++ b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
> @@ -18,8 +18,13 @@ allOf:
> 
>  properties:
>    compatible:
> -    enum:
> -      - fsl,ls1028a-sfp
> +    oneOf:
> +      - description: Trust architecture 2.1 SFP
> +        items:
> +          - const: fsl,ls1021a-sfp
> +      - description: Trust architecture 3.0 SFP
> +        items:
> +          - const: fsl,ls1028a-sfp

I'm unsure about this one. Esp. if you reuse the fsl,ls1028a-sfp
compatible on other SoCs, there were some endianess issues with
other IP blocks on the ls1028a. So it might be that on the LS1028A
the IP has to accessed in little endian order and for other devices
in big endian. I think we should add one compatible per SoC unless
we know better.

-michael

Re: [PATCH 5/8] arm64: dts: ls1028a: Update SFP binding to include clock

[Michael Walle]

Am 2022-04-21 19:56, schrieb Sean Anderson:
> The clocks property is now mandatory. Add it.
> 
> Signed-off-by: Sean Anderson <sean.anderson@seco.com>

Reviewed-by: Michael Walle <michael@walle.cc>

> ---
> 
>  arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> index 088271d49139..59b289b52a28 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> @@ -224,9 +224,12 @@ rst: syscon@1e60000 {
>  			little-endian;
>  		};
> 
> -		efuse@1e80000 {
> +		sfp: efuse@1e80000 {
>  			compatible = "fsl,ls1028a-sfp";
>  			reg = <0x0 0x1e80000 0x0 0x10000>;
> +			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> +					    QORIQ_CLK_PLL_DIV(4)>;
> +			clock-names = "sfp";
>  			#address-cells = <1>;
>  			#size-cells = <1>;

Re: [PATCH 4/8] dt-bindings: nvmem: sfp: Add compatible binding for TA 2.1 SFPs

[Sean Anderson]

On 4/21/22 2:18 PM, Michael Walle wrote:
> Am 2022-04-21 19:56, schrieb Sean Anderson:
>> Trust Architecture (TA) 2.1 devices include the LS1012A, LS1021A,
>> LS1043A, and LS1046A. The SFP device on TA 2.1 devices is very similar
>> to the SFP on TA 3.0 devices. The primary difference is a few fields in
>> the control register. Add a compatible string.
>>
>> Signed-off-by: Sean Anderson <sean.anderson@seco.com>
>> ---
>>
>>  .../devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml    | 9 +++++++--
>>  1 file changed, 7 insertions(+), 2 deletions(-)
>>
>> diff --git
>> a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
>> b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
>> index e7d1232fcd41..aa277f1eee7e 100644
>> --- a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
>> +++ b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
>> @@ -18,8 +18,13 @@ allOf:
>>
>>  properties:
>>    compatible:
>> -    enum:
>> -      - fsl,ls1028a-sfp
>> +    oneOf:
>> +      - description: Trust architecture 2.1 SFP
>> +        items:
>> +          - const: fsl,ls1021a-sfp
>> +      - description: Trust architecture 3.0 SFP
>> +        items:
>> +          - const: fsl,ls1028a-sfp
> 
> I'm unsure about this one. Esp. if you reuse the fsl,ls1028a-sfp
> compatible on other SoCs, there were some endianess issues with
> other IP blocks on the ls1028a. So it might be that on the LS1028A
> the IP has to accessed in little endian order and for other devices
> in big endian. I think we should add one compatible per SoC unless
> we know better.

It looks like I overlooked this. As you pointed out, there is indeed an
endianness difference between TA 2.1 and 3.0 platforms (see e.g. [1]).
Patch 8/8 will need to be updated. I think the easiest way to support
this may be to convert the driver to regmap and set the endiannes in the
config based on the compatible. We could also use the little-endian/
big-endian properties.

--Sean

[1] https://docs.nxp.com/bundle/GUID-487B2E69-BB19-42CB-AC38-7EF18C0FE3AE/page/GUID-EFF8FF41-C8C0-4A3B-AF95-E801D585B7C6.html

Re: [PATCH 1/8] dt-bindings: nvmem: sfp: Fix typo

[Andrew Lunn]

On Thu, Apr 21, 2022 at 01:56:50PM -0400, Sean Anderson wrote:
> There is a small gramattical error in the description. Fix it.

s/gramattical/grammatical :-)

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

Re: [PATCH 3/8] dt-bindings: nvmem: sfp: Add TA_PROG_SFP supply

[Andrew Lunn]

On Thu, Apr 21, 2022 at 01:56:52PM -0400, Sean Anderson wrote:
> The TA_PROG_SFP supply must be enabled to program the fuses, and
> disabled to read the fuses (such as at power-on-reset). On many boards,
> this supply is controlled by a jumper. The user must manually insert or
> remove it at the appropriate time in the programming process. However,
> on other boards this supply is controlled by and FPGA or a GPIO. In
> these cases, the driver can automatically enabled and disable it as
> necessary.
> 
> Signed-off-by: Sean Anderson <sean.anderson@seco.com>
> ---
> 
>  .../devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml        | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
> index 54086f50157d..e7d1232fcd41 100644
> --- a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
> +++ b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
> @@ -32,6 +32,11 @@ properties:
>    clock-names:
>      const: sfp
>  
> +  ta-prog-sfp-supply:
> +    description:
> +      The TA_PROG_SFP supply. It will be enabled for programming and disabled
> +      for reading.
> +

Doesn't there need to be some indication what this is? Is it a GPIO,
or maybe a regulator?

   Andrew

Re: [PATCH 3/8] dt-bindings: nvmem: sfp: Add TA_PROG_SFP supply

[Sean Anderson]

Hi Andrew,

On 4/21/22 5:59 PM, Andrew Lunn wrote:
> On Thu, Apr 21, 2022 at 01:56:52PM -0400, Sean Anderson wrote:
>> The TA_PROG_SFP supply must be enabled to program the fuses, and
>> disabled to read the fuses (such as at power-on-reset). On many boards,
>> this supply is controlled by a jumper. The user must manually insert or
>> remove it at the appropriate time in the programming process. However,
>> on other boards this supply is controlled by and FPGA or a GPIO. In
>> these cases, the driver can automatically enabled and disable it as
>> necessary.
>> 
>> Signed-off-by: Sean Anderson <sean.anderson@seco.com>
>> ---
>> 
>>  .../devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml        | 5 +++++
>>  1 file changed, 5 insertions(+)
>> 
>> diff --git a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
>> index 54086f50157d..e7d1232fcd41 100644
>> --- a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
>> +++ b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
>> @@ -32,6 +32,11 @@ properties:
>>    clock-names:
>>      const: sfp
>>  
>> +  ta-prog-sfp-supply:
>> +    description:
>> +      The TA_PROG_SFP supply. It will be enabled for programming and disabled
>> +      for reading.
>> +
> 
> Doesn't there need to be some indication what this is? Is it a GPIO,
> or maybe a regulator?

There is a pin on these processors named "TA_PROG_SFP". The supply here should
be for whatever regulator supplies that pin. So it could be a fixed-regulator
or perhaps a sub-node of the board's FPGA (no such node exists yet, but it
certainly could). There's a pattern property under
Documentation/devicetree/bindings/regulator/regulator.yaml for these sorts
of nodes.

--Sean

Re: [PATCH 3/8] dt-bindings: nvmem: sfp: Add TA_PROG_SFP supply

[Andrew Lunn]

On Thu, Apr 21, 2022 at 06:06:39PM -0400, Sean Anderson wrote:
> Hi Andrew,
> 
> On 4/21/22 5:59 PM, Andrew Lunn wrote:
> > On Thu, Apr 21, 2022 at 01:56:52PM -0400, Sean Anderson wrote:
> >> The TA_PROG_SFP supply must be enabled to program the fuses, and
> >> disabled to read the fuses (such as at power-on-reset). On many boards,
> >> this supply is controlled by a jumper. The user must manually insert or
> >> remove it at the appropriate time in the programming process. However,
> >> on other boards this supply is controlled by and FPGA or a GPIO. In
> >> these cases, the driver can automatically enabled and disable it as
> >> necessary.
> >> 
> >> Signed-off-by: Sean Anderson <sean.anderson@seco.com>
> >> ---
> >> 
> >>  .../devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml        | 5 +++++
> >>  1 file changed, 5 insertions(+)
> >> 
> >> diff --git a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
> >> index 54086f50157d..e7d1232fcd41 100644
> >> --- a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
> >> +++ b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
> >> @@ -32,6 +32,11 @@ properties:
> >>    clock-names:
> >>      const: sfp
> >>  
> >> +  ta-prog-sfp-supply:
> >> +    description:
> >> +      The TA_PROG_SFP supply. It will be enabled for programming and disabled
> >> +      for reading.
> >> +
> > 
> > Doesn't there need to be some indication what this is? Is it a GPIO,
> > or maybe a regulator?
> 
> There is a pin on these processors named "TA_PROG_SFP". The supply here should
> be for whatever regulator supplies that pin. So it could be a fixed-regulator
> or perhaps a sub-node of the board's FPGA (no such node exists yet, but it
> certainly could). There's a pattern property under
> Documentation/devicetree/bindings/regulator/regulator.yaml for these sorts
> of nodes.

Ah, so -supply means regulator. I would spell it out for dumb people
like my:

  ta-prog-sfp-supply:
    description:
      The regulator supplying TA_PROG_SFP. It will be enabled for programming and disabled
      for reading.

      Andrew

Re: [PATCH 2/8] dt-bindings: nvmem: sfp: Add clock properties

[Rob Herring]

On Thu, 21 Apr 2022 13:56:51 -0400, Sean Anderson wrote:
> To program fuses, it is necessary to set the fuse programming time. This
> is determined based on the value of the platform clock. Add a clock
> property.
> 
> Signed-off-by: Sean Anderson <sean.anderson@seco.com>
> ---
> 
>  .../bindings/nvmem/fsl,layerscape-sfp.yaml         | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 

Running 'make dtbs_check' with the schema in this patch gives the
following warnings. Consider if they are expected or the schema is
incorrect. These may not be new warnings.

Note that it is not yet a requirement to have 0 warnings for dtbs_check.
This will change in the future.

Full log is available here: https://patchwork.ozlabs.org/patch/


efuse@1e80000: 'clock-names' is a required property
	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var2.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dtb

efuse@1e80000: 'clocks' is a required property
	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var2.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dtb

Re: [PATCH 2/8] dt-bindings: nvmem: sfp: Add clock properties

[Sean Anderson]

On 4/22/22 9:36 AM, Rob Herring wrote:
> On Thu, 21 Apr 2022 13:56:51 -0400, Sean Anderson wrote:
>> To program fuses, it is necessary to set the fuse programming time. This
>> is determined based on the value of the platform clock. Add a clock
>> property.
>> 
>> Signed-off-by: Sean Anderson <sean.anderson@seco.com>
>> ---
>> 
>>  .../bindings/nvmem/fsl,layerscape-sfp.yaml         | 14 ++++++++++++++
>>  1 file changed, 14 insertions(+)
>> 
> 
> Running 'make dtbs_check' with the schema in this patch gives the
> following warnings. Consider if they are expected or the schema is
> incorrect. These may not be new warnings.
> 
> Note that it is not yet a requirement to have 0 warnings for dtbs_check.
> This will change in the future.
> 
> Full log is available here: https://patchwork.ozlabs.org/patch/
> 
> 
> efuse@1e80000: 'clock-names' is a required property
> 	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dtb
> 	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dtb
> 	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dtb
> 	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var2.dtb
> 	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dtb
> 	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dtb
> 	arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dtb
> 	arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dtb
> 
> efuse@1e80000: 'clocks' is a required property
> 	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dtb
> 	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dtb
> 	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dtb
> 	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var2.dtb
> 	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dtb
> 	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dtb
> 	arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dtb
> 	arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dtb
> 

This is fixed in 4/8, but I have ordered dt bindings changes first as
required by Documentation/devicetree/bindings/submitting-patches.html

--Sean

Re: [PATCH 2/8] dt-bindings: nvmem: sfp: Add clock properties

[Rob Herring]

On Thu, Apr 21, 2022 at 08:12:34PM +0200, Michael Walle wrote:
> Am 2022-04-21 19:56, schrieb Sean Anderson:
> > To program fuses, it is necessary to set the fuse programming time. This
> > is determined based on the value of the platform clock. Add a clock
> > property.
> 
> For some context: Sean was adding the SFP support in u-boot and
> I referred him to this binding. I didn't need the clock to just
> read the data. But Sean is right, we need the clock for the
> programming. I was unaware of that. The binding is still yet to
> be released with v5.18, thus I think it is still possible to make
> the clock mandatory.

Please add this detail to the commit message. Otherwise, it looks like 
an ABI break to make a new property required.

> 
> > Signed-off-by: Sean Anderson <sean.anderson@seco.com>
> 
> Fixes: 6f9817cdcc82 ("dt-bindings: nvmem: add fsl,layerscape-sfp binding")
> 
> -michael
> 
> > ---
> > 
> >  .../bindings/nvmem/fsl,layerscape-sfp.yaml         | 14 ++++++++++++++
> >  1 file changed, 14 insertions(+)
> > 
> > diff --git
> > a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
> > b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
> > index b7798e903191..54086f50157d 100644
> > --- a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
> > +++ b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
> > @@ -24,15 +24,29 @@ properties:
> >    reg:
> >      maxItems: 1
> > 
> > +  clocks:
> > +    maxItems: 1
> > +    description:
> > +      The SFP clock. Typically, this is the platform clock divided by
> > 4.
> > +
> > +  clock-names:
> > +    const: sfp
> > +
> >  required:
> >    - compatible
> >    - reg
> > +  - clock-names
> > +  - clocks
> > 
> >  unevaluatedProperties: false
> > 
> >  examples:
> >    - |
> > +    #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
> >      efuse@1e80000 {
> >          compatible = "fsl,ls1028a-sfp";
> >          reg = <0x1e80000 0x8000>;
> > +        clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> > +                            QORIQ_CLK_PLL_DIV(4)>;
> > +        clock-names = "sfp";
> >      };