[PATCH 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40

[PATCH 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40

[Icenowy Zheng]

From: Chen-Yu Tsai <wens@csie.org>

The Allwinner R40 SoC is marketed as the successor to the A20 SoC.
The R40 is a smaller chip than the A20, but features the same set
of programmable pins, with a couple extra pins and some new pin
functions. The chip features 4 Cortex-A7 cores and a Mali-400 MP2
GPU. It retains most if not all features from the A20, while adding
some new features, such as MIPI DSI output, or updating various
hardware blocks, such as DE 2.0.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 arch/arm/boot/dts/sun8i-r40.dtsi | 396 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 396 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun8i-r40.dtsi

diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
new file mode 100644
index 000000000000..5b48801bdd01
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -0,0 +1,396 @@
+/*
+ * Copyright 2017 Chen-Yu Tsai <wens@csie.org>
+ * Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/sun8i-r40-ccu.h>
+#include <dt-bindings/reset/sun8i-r40-ccu.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	interrupt-parent = <&gic>;
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		osc24M: osc24M {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <24000000>;
+			clock-output-names = "osc24M";
+		};
+
+		osc32k: osc32k {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			clock-output-names = "osc32k";
+		};
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <0>;
+		};
+
+		cpu@1 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <1>;
+		};
+
+		cpu@2 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <2>;
+		};
+
+		cpu@3 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <3>;
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		nmi_intc: interrupt-controller@1c00030 {
+			compatible = "allwinner,sun7i-a20-sc-nmi";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			reg = <0x01c00030 0x0c>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		mmc0: mmc@1c0f000 {
+			compatible = "allwinner,sun50i-a64-mmc";
+			reg = <0x01c0f000 0x1000>;
+			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
+			clock-names = "ahb", "mmc";
+			resets = <&ccu RST_BUS_MMC0>;
+			reset-names = "ahb";
+			pinctrl-0 = <&mmc0_pins>;
+			pinctrl-names = "default";
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			max-frequency = <150000000>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		mmc1: mmc@1c10000 {
+			compatible = "allwinner,sun50i-a64-mmc";
+			reg = <0x01c10000 0x1000>;
+			clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
+			clock-names = "ahb", "mmc";
+			resets = <&ccu RST_BUS_MMC1>;
+			reset-names = "ahb";
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+			max-frequency = <150000000>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		mmc2: mmc@1c11000 {
+			compatible = "allwinner,sun50i-a64-emmc";
+			reg = <0x01c11000 0x1000>;
+			clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
+			clock-names = "ahb", "mmc";
+			resets = <&ccu RST_BUS_MMC2>;
+			reset-names = "ahb";
+			pinctrl-0 = <&mmc2_pins>;
+			pinctrl-names = "default";
+			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+			max-frequency = <200000000>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		mmc3: mmc@1c12000 {
+			compatible = "allwinner,sun50i-a64-mmc";
+			reg = <0x01c12000 0x1000>;
+			clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>;
+			clock-names = "ahb", "mmc";
+			resets = <&ccu RST_BUS_MMC3>;
+			reset-names = "ahb";
+			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+			max-frequency = <150000000>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		ccu: clock@1c20000 {
+			compatible = "allwinner,sun8i-r40-ccu";
+			reg = <0x01c20000 0x400>;
+			clocks = <&osc24M>, <&osc32k>;
+			clock-names = "hosc", "losc";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		pio: pinctrl@1c20800 {
+			compatible = "allwinner,sun8i-r40-pinctrl";
+			reg = <0x01c20800 0x400>;
+			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
+			clock-names = "apb", "hosc", "losc";
+			gpio-controller;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			#gpio-cells = <3>;
+
+			i2c0_pins: i2c0-pins {
+				pins = "PB0", "PB1";
+				function = "i2c0";
+			};
+
+			mmc0_pins: mmc0-pins {
+				pins = "PF0", "PF1", "PF2",
+				       "PF3", "PF4", "PF5";
+				function = "mmc0";
+				drive-strength = <30>;
+				bias-pull-up;
+			};
+
+			mmc1_pg_pins: mmc1-pg-pins {
+				pins = "PG0", "PG1", "PG2",
+				       "PG3", "PG4", "PG5";
+				function = "mmc1";
+				drive-strength = <30>;
+				bias-pull-up;
+			};
+
+			mmc2_pins: mmc2-pins {
+				pins = "PC5", "PC6", "PC7", "PC8", "PC9",
+				       "PC10", "PC11", "PC12", "PC13", "PC14",
+				       "PC15", "PC24";
+				function = "mmc2";
+				drive-strength = <30>;
+				bias-pull-up;
+			};
+
+			uart0_pb_pins: uart0-pb-pins {
+				pins = "PB22", "PB23";
+				function = "uart0";
+			};
+		};
+
+		uart0: serial@1c28000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c28000 0x400>;
+			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&ccu CLK_BUS_UART0>;
+			resets = <&ccu RST_BUS_UART0>;
+			status = "disabled";
+		};
+
+		uart1: serial@1c28400 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c28400 0x400>;
+			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&ccu CLK_BUS_UART1>;
+			resets = <&ccu RST_BUS_UART1>;
+			status = "disabled";
+		};
+
+		uart2: serial@1c28800 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c28800 0x400>;
+			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&ccu CLK_BUS_UART2>;
+			resets = <&ccu RST_BUS_UART2>;
+			status = "disabled";
+		};
+
+		uart3: serial@1c28c00 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c28c00 0x400>;
+			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&ccu CLK_BUS_UART3>;
+			resets = <&ccu RST_BUS_UART3>;
+			status = "disabled";
+		};
+
+		uart4: serial@1c29000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c29000 0x400>;
+			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&ccu CLK_BUS_UART4>;
+			resets = <&ccu RST_BUS_UART4>;
+			status = "disabled";
+		};
+
+		uart5: serial@1c29400 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c29400 0x400>;
+			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&ccu CLK_BUS_UART5>;
+			resets = <&ccu RST_BUS_UART5>;
+			status = "disabled";
+		};
+
+		uart6: serial@1c29800 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c29800 0x400>;
+			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&ccu CLK_BUS_UART6>;
+			resets = <&ccu RST_BUS_UART6>;
+			status = "disabled";
+		};
+
+		uart7: serial@1c29c00 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c29c00 0x400>;
+			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&ccu CLK_BUS_UART7>;
+			resets = <&ccu RST_BUS_UART7>;
+			status = "disabled";
+		};
+
+		i2c0: i2c@1c2ac00 {
+			compatible = "allwinner,sun6i-a31-i2c";
+			reg = <0x01c2ac00 0x400>;
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2C0>;
+			resets = <&ccu RST_BUS_I2C0>;
+			pinctrl-0 = <&i2c0_pins>;
+			pinctrl-names = "default";
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c1: i2c@1c2b000 {
+			compatible = "allwinner,sun6i-a31-i2c";
+			reg = <0x01c2b000 0x400>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2C1>;
+			resets = <&ccu RST_BUS_I2C1>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c2: i2c@1c2b400 {
+			compatible = "allwinner,sun6i-a31-i2c";
+			reg = <0x01c2b400 0x400>;
+			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2C2>;
+			resets = <&ccu RST_BUS_I2C2>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c3: i2c@1c2b800 {
+			compatible = "allwinner,sun6i-a31-i2c";
+			reg = <0x01c2b800 0x400>;
+			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2C3>;
+			resets = <&ccu RST_BUS_I2C3>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c4: i2c@1c2c000 {
+			compatible = "allwinner,sun6i-a31-i2c";
+			reg = <0x01c2c000 0x400>;
+			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2C4>;
+			resets = <&ccu RST_BUS_I2C4>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		gic: interrupt-controller@1c81000 {
+			compatible = "arm,gic-400";
+			reg = <0x01c81000 0x1000>,
+			      <0x01c82000 0x1000>,
+			      <0x01c84000 0x2000>,
+			      <0x01c86000 0x2000>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+};
-- 
2.13.5

[PATCH 2/3] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra

[Icenowy Zheng]

From: Chen-Yu Tsai <wens@csie.org>

The Banana Pi M2 Ultra is an SBC based on the Allwinner R40 SoC. The
form factor and position of various connectors, leds and buttons is
similar to the Banana Pi M1+, Banana Pi M3, and is exactly the same
as the latest Banana Pi M64.

It features:

  - X-Powers AXP221s PMIC connected to i2c0
  - 2 GB DDR3 DRAM
  - 8 GB eMMC
  - micro SD card slot
  - DC power jack
  - HDMI output
  - MIPI DSI connector
  - 2x USB 2.0 hosts
  - 1x USB 2.0 OTG
  - gigabit ethernet with Realtek RTL8211E transceiver
  - WiFi/Bluetooth with AP6212 chip, with external antenna connector
  - SATA and power connectors for native SATA support
  - camera sensor connector
  - consumer IR receiver
  - audio out headphone jack
  - onboard microphone
  - red, green, and blue LEDs
  - debug UART pins
  - Li-Po battery connector
  - Raspberry Pi B+ compatible GPIO header
  - power, reset, and boot control buttons

This patch adds a dts file that enables UART, MMC and PMIC support.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 arch/arm/boot/dts/Makefile                        |   1 +
 arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 181 ++++++++++++++++++++++
 2 files changed, 182 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 570e107bf702..e0b1ed3e2e24 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -927,6 +927,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
 	sun8i-h3-orangepi-plus2e.dtb \
 	sun8i-r16-bananapi-m2m.dtb \
 	sun8i-r16-parrot.dtb \
+	sun8i-r40-bananapi-m2-ultra.dtb \
 	sun8i-v3s-licheepi-zero.dtb \
 	sun8i-v3s-licheepi-zero-dock.dtb
 dtb-$(CONFIG_MACH_SUN9I) += \
diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
new file mode 100644
index 000000000000..daf55556036f
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
@@ -0,0 +1,181 @@
+/*
+ * Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-r40.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+/ {
+	model = "Banana Pi BPI-M2-Ultra";
+	compatible = "sinovoip,bpi-m2-ultra", "allwinner,sun8i-r40";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+	leds {
+		compatible = "gpio-leds";
+
+		pwr-led {
+			label = "bananapi:red:pwr";
+			gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		user-led-green {
+			label = "bananapi:green:user";
+			gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>;
+		};
+
+		user-led-blue {
+			label = "bananapi:blue:user";
+			gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	wifi_pwrseq: wifi_pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */
+	};
+};
+
+&i2c0 {
+	status = "okay";
+
+	axp22x: pmic@34 {
+		compatible = "x-powers,axp221";
+		reg = <0x34>;
+		interrupt-parent = <&nmi_intc>;
+		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
+#include "axp22x.dtsi"
+
+&reg_aldo3 {
+	regulator-always-on;
+	regulator-min-microvolt = <2700000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "avcc";
+};
+
+&reg_dcdc1 {
+	regulator-always-on;
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "vcc-3v0";
+};
+
+&reg_dcdc2 {
+	regulator-always-on;
+	regulator-min-microvolt = <1000000>;
+	regulator-max-microvolt = <1300000>;
+	regulator-name = "vdd-cpu";
+};
+
+&reg_dcdc3 {
+	regulator-always-on;
+	regulator-min-microvolt = <1000000>;
+	regulator-max-microvolt = <1300000>;
+	regulator-name = "vdd-sys";
+};
+
+&reg_dcdc5 {
+	regulator-always-on;
+	regulator-min-microvolt = <1500000>;
+	regulator-max-microvolt = <1500000>;
+	regulator-name = "vcc-dram";
+};
+
+&reg_dldo1 {
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-wifi-io";
+};
+
+&reg_dldo2 {
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-wifi";
+};
+
+&reg_vcc5v0 {
+	gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */
+	enable-active-high;
+};
+
+&mmc0 {
+	vmmc-supply = <&reg_dcdc1>;
+	bus-width = <4>;
+	cd-gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; /* PH13 */
+	cd-inverted;
+	status = "okay";
+};
+
+&mmc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pg_pins>;
+	vmmc-supply = <&reg_dldo2>;
+	vqmmc-supply = <&reg_dldo1>;
+	mmc-pwrseq = <&wifi_pwrseq>;
+	bus-width = <4>;
+	non-removable;
+	status = "okay";
+};
+
+&mmc2 {
+	vmmc-supply = <&reg_dcdc1>;
+	vqmmc-supply = <&reg_dcdc1>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pb_pins>;
+	status = "okay";
+};
-- 
2.13.5

[PATCH 3/3] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Berry

[Icenowy Zheng]

The Banana Pi M2 Ultra is an SBC based on the Allwinner V40 SoC (same as
the R40 SoC). The form factor is similar to the Raspberry Pi series.

It features:

- X-Powers AXP221s PMIC connected to i2c0
- 1GiB DDR3 DRAM
- microSD slot
- MicroUSB Type-B port for power and connected to usb0
- HDMI output
- MIPI DSI connector
- 4 USB Type-A ports (connected to the usb1 controller via a hub)
- gigabit ethernet with Realtek RTL8211E transceiver
- WiFi/Bluetooth with AP6212 module, with external antenna connector
- SATA and power connectors for native SATA support
- camera sensor connector
- audio out headphone jack
- red and green LEDs
- debug UART pins
- Raspberry Pi B+ compatible GPIO header
- power and reset buttons

This patch adds a dts file that enables UART, MMC and PMIC support.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 arch/arm/boot/dts/Makefile                        |   3 +-
 arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 168 ++++++++++++++++++++++
 2 files changed, 170 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index e0b1ed3e2e24..c22cd6b914b4 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -929,7 +929,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \
 	sun8i-r16-parrot.dtb \
 	sun8i-r40-bananapi-m2-ultra.dtb \
 	sun8i-v3s-licheepi-zero.dtb \
-	sun8i-v3s-licheepi-zero-dock.dtb
+	sun8i-v3s-licheepi-zero-dock.dtb \
+	sun8i-v40-bananapi-m2-berry.dtb
 dtb-$(CONFIG_MACH_SUN9I) += \
 	sun9i-a80-optimus.dtb \
 	sun9i-a80-cubieboard4.dtb
diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
new file mode 100644
index 000000000000..04d8bbb8ea51
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
@@ -0,0 +1,168 @@
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-r40.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+/ {
+	model = "Banana Pi M2 Berry";
+	compatible = "sinovoip,bpi-m2-berry", "allwinner,sun8i-r40";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		pwr-led {
+			label = "bananapi:red:pwr";
+			gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		user-led {
+			label = "bananapi:green:user";
+			gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	wifi_pwrseq: wifi_pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */
+	};
+};
+
+&i2c0 {
+	status = "okay";
+
+	axp22x: pmic@68 {
+		compatible = "x-powers,axp221";
+		reg = <0x34>;
+		interrupt-parent = <&nmi_intc>;
+		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
+#include "axp22x.dtsi"
+
+&reg_aldo3 {
+	regulator-always-on;
+	regulator-min-microvolt = <2700000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "avcc";
+};
+
+&reg_dcdc1 {
+	regulator-always-on;
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "vcc-3v0";
+};
+
+&reg_dcdc2 {
+	regulator-always-on;
+	regulator-min-microvolt = <1000000>;
+	regulator-max-microvolt = <1300000>;
+	regulator-name = "vdd-cpu";
+};
+
+&reg_dcdc3 {
+	regulator-always-on;
+	regulator-min-microvolt = <1000000>;
+	regulator-max-microvolt = <1300000>;
+	regulator-name = "vdd-sys";
+};
+
+&reg_dcdc5 {
+	regulator-always-on;
+	regulator-min-microvolt = <1500000>;
+	regulator-max-microvolt = <1500000>;
+	regulator-name = "vcc-dram";
+};
+
+&reg_dldo1 {
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-wifi-io";
+};
+
+&reg_dldo2 {
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-wifi";
+};
+
+&reg_vcc5v0 {
+	gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */
+	enable-active-high;
+};
+
+&mmc0 {
+	vmmc-supply = <&reg_dcdc1>;
+	bus-width = <4>;
+	cd-gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; /* PH13 */
+	cd-inverted;
+	status = "okay";
+};
+
+&mmc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pg_pins>;
+	vmmc-supply = <&reg_dldo2>;
+	vqmmc-supply = <&reg_dldo1>;
+	mmc-pwrseq = <&wifi_pwrseq>;
+	bus-width = <4>;
+	non-removable;
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pb_pins>;
+	status = "okay";
+};
-- 
2.13.5

Re: [PATCH 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 13963 bytes --]

Hi,

On Tue, Aug 22, 2017 at 02:17:40PM +0800, Icenowy Zheng wrote:
> From: Chen-Yu Tsai <wens@csie.org>
> 
> The Allwinner R40 SoC is marketed as the successor to the A20 SoC.
> The R40 is a smaller chip than the A20, but features the same set
> of programmable pins, with a couple extra pins and some new pin
> functions. The chip features 4 Cortex-A7 cores and a Mali-400 MP2
> GPU. It retains most if not all features from the A20, while adding
> some new features, such as MIPI DSI output, or updating various
> hardware blocks, such as DE 2.0.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

I'm not sure why you have two series to achieve one thing here. And
the fact that you don't have a cover letter doesn't make it any
clearer.

Please make series based on what you're trying to do and not split it
arbitrarily. And document what you're doing in a cover letter.

> ---
>  arch/arm/boot/dts/sun8i-r40.dtsi | 396 +++++++++++++++++++++++++++++++++++++++
>  1 file changed, 396 insertions(+)
>  create mode 100644 arch/arm/boot/dts/sun8i-r40.dtsi
> 
> diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
> new file mode 100644
> index 000000000000..5b48801bdd01
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
> @@ -0,0 +1,396 @@
> +/*
> + * Copyright 2017 Chen-Yu Tsai <wens@csie.org>
> + * Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This file is free software; you can redistribute it and/or
> + *     modify it under the terms of the GNU General Public License as
> + *     published by the Free Software Foundation; either version 2 of the
> + *     License, or (at your option) any later version.
> + *
> + *     This file is distributed in the hope that it will be useful,
> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *     GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + *     obtaining a copy of this software and associated documentation
> + *     files (the "Software"), to deal in the Software without
> + *     restriction, including without limitation the rights to use,
> + *     copy, modify, merge, publish, distribute, sublicense, and/or
> + *     sell copies of the Software, and to permit persons to whom the
> + *     Software is furnished to do so, subject to the following
> + *     conditions:
> + *
> + *     The above copyright notice and this permission notice shall be
> + *     included in all copies or substantial portions of the Software.
> + *
> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + *     OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/sun8i-r40-ccu.h>
> +#include <dt-bindings/reset/sun8i-r40-ccu.h>
> +
> +/ {
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +	interrupt-parent = <&gic>;
> +
> +	clocks {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		osc24M: osc24M {
> +			#clock-cells = <0>;
> +			compatible = "fixed-clock";
> +			clock-frequency = <24000000>;
> +			clock-output-names = "osc24M";
> +		};
> +
> +		osc32k: osc32k {
> +			#clock-cells = <0>;
> +			compatible = "fixed-clock";
> +			clock-frequency = <32768>;
> +			clock-output-names = "osc32k";
> +		};
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu@0 {
> +			compatible = "arm,cortex-a7";
> +			device_type = "cpu";
> +			reg = <0>;
> +		};
> +
> +		cpu@1 {
> +			compatible = "arm,cortex-a7";
> +			device_type = "cpu";
> +			reg = <1>;
> +		};
> +
> +		cpu@2 {
> +			compatible = "arm,cortex-a7";
> +			device_type = "cpu";
> +			reg = <2>;
> +		};
> +
> +		cpu@3 {
> +			compatible = "arm,cortex-a7";
> +			device_type = "cpu";
> +			reg = <3>;
> +		};
> +	};
> +
> +	soc {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		nmi_intc: interrupt-controller@1c00030 {
> +			compatible = "allwinner,sun7i-a20-sc-nmi";
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			reg = <0x01c00030 0x0c>;
> +			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> +		};

You should use the new compatible here.

> +		mmc0: mmc@1c0f000 {
> +			compatible = "allwinner,sun50i-a64-mmc";

Please add a soc specific compatible for all the blocks.

> +			reg = <0x01c0f000 0x1000>;
> +			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
> +			clock-names = "ahb", "mmc";
> +			resets = <&ccu RST_BUS_MMC0>;
> +			reset-names = "ahb";
> +			pinctrl-0 = <&mmc0_pins>;
> +			pinctrl-names = "default";
> +			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> +			max-frequency = <150000000>;

have you tested that frequency?

> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		mmc1: mmc@1c10000 {
> +			compatible = "allwinner,sun50i-a64-mmc";
> +			reg = <0x01c10000 0x1000>;
> +			clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
> +			clock-names = "ahb", "mmc";
> +			resets = <&ccu RST_BUS_MMC1>;
> +			reset-names = "ahb";
> +			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> +			max-frequency = <150000000>;

Ditto.

> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		mmc2: mmc@1c11000 {
> +			compatible = "allwinner,sun50i-a64-emmc";
> +			reg = <0x01c11000 0x1000>;
> +			clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
> +			clock-names = "ahb", "mmc";
> +			resets = <&ccu RST_BUS_MMC2>;
> +			reset-names = "ahb";
> +			pinctrl-0 = <&mmc2_pins>;
> +			pinctrl-names = "default";
> +			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> +			max-frequency = <200000000>;

Ditto.

> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		mmc3: mmc@1c12000 {
> +			compatible = "allwinner,sun50i-a64-mmc";
> +			reg = <0x01c12000 0x1000>;
> +			clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>;
> +			clock-names = "ahb", "mmc";
> +			resets = <&ccu RST_BUS_MMC3>;
> +			reset-names = "ahb";
> +			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> +			max-frequency = <150000000>;

Ditto.

> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		ccu: clock@1c20000 {
> +			compatible = "allwinner,sun8i-r40-ccu";
> +			reg = <0x01c20000 0x400>;
> +			clocks = <&osc24M>, <&osc32k>;
> +			clock-names = "hosc", "losc";
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +		};
> +
> +		pio: pinctrl@1c20800 {
> +			compatible = "allwinner,sun8i-r40-pinctrl";
> +			reg = <0x01c20800 0x400>;
> +			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
> +			clock-names = "apb", "hosc", "losc";
> +			gpio-controller;
> +			interrupt-controller;
> +			#interrupt-cells = <3>;
> +			#gpio-cells = <3>;
> +
> +			i2c0_pins: i2c0-pins {
> +				pins = "PB0", "PB1";
> +				function = "i2c0";
> +			};
> +
> +			mmc0_pins: mmc0-pins {
> +				pins = "PF0", "PF1", "PF2",
> +				       "PF3", "PF4", "PF5";
> +				function = "mmc0";
> +				drive-strength = <30>;
> +				bias-pull-up;
> +			};
> +
> +			mmc1_pg_pins: mmc1-pg-pins {
> +				pins = "PG0", "PG1", "PG2",
> +				       "PG3", "PG4", "PG5";
> +				function = "mmc1";
> +				drive-strength = <30>;
> +				bias-pull-up;
> +			};
> +
> +			mmc2_pins: mmc2-pins {
> +				pins = "PC5", "PC6", "PC7", "PC8", "PC9",
> +				       "PC10", "PC11", "PC12", "PC13", "PC14",
> +				       "PC15", "PC24";
> +				function = "mmc2";
> +				drive-strength = <30>;
> +				bias-pull-up;
> +			};
> +
> +			uart0_pb_pins: uart0-pb-pins {
> +				pins = "PB22", "PB23";
> +				function = "uart0";
> +			};
> +		};
> +
> +		uart0: serial@1c28000 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x01c28000 0x400>;
> +			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clocks = <&ccu CLK_BUS_UART0>;
> +			resets = <&ccu RST_BUS_UART0>;
> +			status = "disabled";
> +		};
> +
> +		uart1: serial@1c28400 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x01c28400 0x400>;
> +			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clocks = <&ccu CLK_BUS_UART1>;
> +			resets = <&ccu RST_BUS_UART1>;
> +			status = "disabled";
> +		};
> +
> +		uart2: serial@1c28800 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x01c28800 0x400>;
> +			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clocks = <&ccu CLK_BUS_UART2>;
> +			resets = <&ccu RST_BUS_UART2>;
> +			status = "disabled";
> +		};
> +
> +		uart3: serial@1c28c00 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x01c28c00 0x400>;
> +			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clocks = <&ccu CLK_BUS_UART3>;
> +			resets = <&ccu RST_BUS_UART3>;
> +			status = "disabled";
> +		};
> +
> +		uart4: serial@1c29000 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x01c29000 0x400>;
> +			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clocks = <&ccu CLK_BUS_UART4>;
> +			resets = <&ccu RST_BUS_UART4>;
> +			status = "disabled";
> +		};
> +
> +		uart5: serial@1c29400 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x01c29400 0x400>;
> +			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clocks = <&ccu CLK_BUS_UART5>;
> +			resets = <&ccu RST_BUS_UART5>;
> +			status = "disabled";
> +		};
> +
> +		uart6: serial@1c29800 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x01c29800 0x400>;
> +			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clocks = <&ccu CLK_BUS_UART6>;
> +			resets = <&ccu RST_BUS_UART6>;
> +			status = "disabled";
> +		};
> +
> +		uart7: serial@1c29c00 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x01c29c00 0x400>;
> +			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clocks = <&ccu CLK_BUS_UART7>;
> +			resets = <&ccu RST_BUS_UART7>;
> +			status = "disabled";
> +		};
> +
> +		i2c0: i2c@1c2ac00 {
> +			compatible = "allwinner,sun6i-a31-i2c";
> +			reg = <0x01c2ac00 0x400>;
> +			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_I2C0>;
> +			resets = <&ccu RST_BUS_I2C0>;
> +			pinctrl-0 = <&i2c0_pins>;
> +			pinctrl-names = "default";
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c1: i2c@1c2b000 {
> +			compatible = "allwinner,sun6i-a31-i2c";
> +			reg = <0x01c2b000 0x400>;
> +			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_I2C1>;
> +			resets = <&ccu RST_BUS_I2C1>;
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c2: i2c@1c2b400 {
> +			compatible = "allwinner,sun6i-a31-i2c";
> +			reg = <0x01c2b400 0x400>;
> +			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_I2C2>;
> +			resets = <&ccu RST_BUS_I2C2>;
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c3: i2c@1c2b800 {
> +			compatible = "allwinner,sun6i-a31-i2c";
> +			reg = <0x01c2b800 0x400>;
> +			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_I2C3>;
> +			resets = <&ccu RST_BUS_I2C3>;
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c4: i2c@1c2c000 {
> +			compatible = "allwinner,sun6i-a31-i2c";
> +			reg = <0x01c2c000 0x400>;
> +			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_I2C4>;
> +			resets = <&ccu RST_BUS_I2C4>;
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		gic: interrupt-controller@1c81000 {
> +			compatible = "arm,gic-400";
> +			reg = <0x01c81000 0x1000>,
> +			      <0x01c82000 0x1000>,
> +			      <0x01c84000 0x2000>,
> +			      <0x01c86000 0x2000>;
> +			interrupt-controller;
> +			#interrupt-cells = <3>;
> +			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> +		};
> +	};
> +
> +	timer {
> +		compatible = "arm,armv7-timer";
> +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;

Those masks are wrong.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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Re: [PATCH 2/3] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra

[Maxime Ripard]

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Hi,

On Tue, Aug 22, 2017 at 02:17:41PM +0800, Icenowy Zheng wrote:
> From: Chen-Yu Tsai <wens@csie.org>
> 
> The Banana Pi M2 Ultra is an SBC based on the Allwinner R40 SoC. The
> form factor and position of various connectors, leds and buttons is
> similar to the Banana Pi M1+, Banana Pi M3, and is exactly the same
> as the latest Banana Pi M64.
> 
> It features:
> 
>   - X-Powers AXP221s PMIC connected to i2c0
>   - 2 GB DDR3 DRAM
>   - 8 GB eMMC
>   - micro SD card slot
>   - DC power jack
>   - HDMI output
>   - MIPI DSI connector
>   - 2x USB 2.0 hosts
>   - 1x USB 2.0 OTG
>   - gigabit ethernet with Realtek RTL8211E transceiver
>   - WiFi/Bluetooth with AP6212 chip, with external antenna connector
>   - SATA and power connectors for native SATA support
>   - camera sensor connector
>   - consumer IR receiver
>   - audio out headphone jack
>   - onboard microphone
>   - red, green, and blue LEDs
>   - debug UART pins
>   - Li-Po battery connector
>   - Raspberry Pi B+ compatible GPIO header
>   - power, reset, and boot control buttons
> 
> This patch adds a dts file that enables UART, MMC and PMIC support.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
>  arch/arm/boot/dts/Makefile                        |   1 +
>  arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 181 ++++++++++++++++++++++
>  2 files changed, 182 insertions(+)
>  create mode 100644 arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 570e107bf702..e0b1ed3e2e24 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -927,6 +927,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
>  	sun8i-h3-orangepi-plus2e.dtb \
>  	sun8i-r16-bananapi-m2m.dtb \
>  	sun8i-r16-parrot.dtb \
> +	sun8i-r40-bananapi-m2-ultra.dtb \
>  	sun8i-v3s-licheepi-zero.dtb \
>  	sun8i-v3s-licheepi-zero-dock.dtb
>  dtb-$(CONFIG_MACH_SUN9I) += \
> diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
> new file mode 100644
> index 000000000000..daf55556036f
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
> @@ -0,0 +1,181 @@
> +/*
> + * Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
> + * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This file is free software; you can redistribute it and/or
> + *     modify it under the terms of the GNU General Public License as
> + *     published by the Free Software Foundation; either version 2 of the
> + *     License, or (at your option) any later version.
> + *
> + *     This file is distributed in the hope that it will be useful,
> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *     GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + *     obtaining a copy of this software and associated documentation
> + *     files (the "Software"), to deal in the Software without
> + *     restriction, including without limitation the rights to use,
> + *     copy, modify, merge, publish, distribute, sublicense, and/or
> + *     sell copies of the Software, and to permit persons to whom the
> + *     Software is furnished to do so, subject to the following
> + *     conditions:
> + *
> + *     The above copyright notice and this permission notice shall be
> + *     included in all copies or substantial portions of the Software.
> + *
> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + *     OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +#include "sun8i-r40.dtsi"
> +#include "sunxi-common-regulators.dtsi"
> +
> +/ {
> +	model = "Banana Pi BPI-M2-Ultra";
> +	compatible = "sinovoip,bpi-m2-ultra", "allwinner,sun8i-r40";
> +
> +	aliases {
> +		serial0 = &uart0;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};

Missing newline

> +	leds {
> +		compatible = "gpio-leds";
> +
> +		pwr-led {
> +			label = "bananapi:red:pwr";
> +			gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
> +			default-state = "on";
> +		};
> +
> +		user-led-green {
> +			label = "bananapi:green:user";
> +			gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>;
> +		};
> +
> +		user-led-blue {
> +			label = "bananapi:blue:user";
> +			gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>;
> +		};
> +	};
> +
> +	wifi_pwrseq: wifi_pwrseq {
> +		compatible = "mmc-pwrseq-simple";
> +		reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */
> +	};
> +};
> +
> +&i2c0 {
> +	status = "okay";
> +
> +	axp22x: pmic@34 {
> +		compatible = "x-powers,axp221";
> +		reg = <0x34>;
> +		interrupt-parent = <&nmi_intc>;
> +		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
> +	};
> +};
> +
> +#include "axp22x.dtsi"
> +
> +&reg_aldo3 {
> +	regulator-always-on;
> +	regulator-min-microvolt = <2700000>;
> +	regulator-max-microvolt = <3300000>;
> +	regulator-name = "avcc";
> +};
> +
> +&reg_dcdc1 {
> +	regulator-always-on;
> +	regulator-min-microvolt = <3000000>;
> +	regulator-max-microvolt = <3000000>;
> +	regulator-name = "vcc-3v0";
> +};
> +
> +&reg_dcdc2 {
> +	regulator-always-on;
> +	regulator-min-microvolt = <1000000>;
> +	regulator-max-microvolt = <1300000>;
> +	regulator-name = "vdd-cpu";
> +};
> +
> +&reg_dcdc3 {
> +	regulator-always-on;
> +	regulator-min-microvolt = <1000000>;
> +	regulator-max-microvolt = <1300000>;
> +	regulator-name = "vdd-sys";
> +};
> +
> +&reg_dcdc5 {
> +	regulator-always-on;
> +	regulator-min-microvolt = <1500000>;
> +	regulator-max-microvolt = <1500000>;
> +	regulator-name = "vcc-dram";
> +};
> +
> +&reg_dldo1 {
> +	regulator-min-microvolt = <1800000>;
> +	regulator-max-microvolt = <3300000>;
> +	regulator-name = "vcc-wifi-io";
> +};
> +
> +&reg_dldo2 {
> +	regulator-min-microvolt = <3300000>;
> +	regulator-max-microvolt = <3300000>;
> +	regulator-name = "vcc-wifi";
> +};
> +
> +&reg_vcc5v0 {
> +	gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */
> +	enable-active-high;
> +};

That regulator is unused, and the GPIO is marked to be unused on the schematics.

> +&mmc0 {
> +	vmmc-supply = <&reg_dcdc1>;
> +	bus-width = <4>;
> +	cd-gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; /* PH13 */
> +	cd-inverted;
> +	status = "okay";
> +};
> +
> +&mmc1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&mmc1_pg_pins>;
> +	vmmc-supply = <&reg_dldo2>;
> +	vqmmc-supply = <&reg_dldo1>;
> +	mmc-pwrseq = <&wifi_pwrseq>;
> +	bus-width = <4>;
> +	non-removable;
> +	status = "okay";
> +};
> +
> +&mmc2 {
> +	vmmc-supply = <&reg_dcdc1>;
> +	vqmmc-supply = <&reg_dcdc1>;

You don't need vqmmc here.

Maxime

-- 
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Embedded Linux and Kernel engineering
http://free-electrons.com

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Re: [PATCH 3/3] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Berry

[Maxime Ripard]

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On Tue, Aug 22, 2017 at 02:17:42PM +0800, Icenowy Zheng wrote:
> +&reg_vcc5v0 {
> +	gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */
> +	enable-active-high;
> +};

Same thing here, you're not using that regulator anywhere. You don't
even use any of the regulators in sunxi-common-regulators.

Maxime

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Embedded Linux and Kernel engineering
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Re: [PATCH 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40

[Icenowy Zheng]

于 2017年8月23日 GMT+08:00 上午4:05:21, Maxime Ripard <maxime.ripard@free-electrons.com> 写到:
>Hi,
>
>On Tue, Aug 22, 2017 at 02:17:40PM +0800, Icenowy Zheng wrote:
>> From: Chen-Yu Tsai <wens@csie.org>
>> 
>> The Allwinner R40 SoC is marketed as the successor to the A20 SoC.
>> The R40 is a smaller chip than the A20, but features the same set
>> of programmable pins, with a couple extra pins and some new pin
>> functions. The chip features 4 Cortex-A7 cores and a Mali-400 MP2
>> GPU. It retains most if not all features from the A20, while adding
>> some new features, such as MIPI DSI output, or updating various
>> hardware blocks, such as DE 2.0.
>> 
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>
>I'm not sure why you have two series to achieve one thing here. And
>the fact that you don't have a cover letter doesn't make it any
>clearer.
>
>Please make series based on what you're trying to do and not split it
>arbitrarily. And document what you're doing in a cover letter.
>
>> ---
>>  arch/arm/boot/dts/sun8i-r40.dtsi | 396
>+++++++++++++++++++++++++++++++++++++++
>>  1 file changed, 396 insertions(+)
>>  create mode 100644 arch/arm/boot/dts/sun8i-r40.dtsi
>> 
>> diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi
>b/arch/arm/boot/dts/sun8i-r40.dtsi
>> new file mode 100644
>> index 000000000000..5b48801bdd01
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
>> @@ -0,0 +1,396 @@
>> +/*
>> + * Copyright 2017 Chen-Yu Tsai <wens@csie.org>
>> + * Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this
>dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + *  a) This file is free software; you can redistribute it and/or
>> + *     modify it under the terms of the GNU General Public License
>as
>> + *     published by the Free Software Foundation; either version 2
>of the
>> + *     License, or (at your option) any later version.
>> + *
>> + *     This file is distributed in the hope that it will be useful,
>> + *     but WITHOUT ANY WARRANTY; without even the implied warranty
>of
>> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + *     GNU General Public License for more details.
>> + *
>> + * Or, alternatively,
>> + *
>> + *  b) Permission is hereby granted, free of charge, to any person
>> + *     obtaining a copy of this software and associated
>documentation
>> + *     files (the "Software"), to deal in the Software without
>> + *     restriction, including without limitation the rights to use,
>> + *     copy, modify, merge, publish, distribute, sublicense, and/or
>> + *     sell copies of the Software, and to permit persons to whom
>the
>> + *     Software is furnished to do so, subject to the following
>> + *     conditions:
>> + *
>> + *     The above copyright notice and this permission notice shall
>be
>> + *     included in all copies or substantial portions of the
>Software.
>> + *
>> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
>KIND,
>> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
>WARRANTIES
>> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + *     OTHER DEALINGS IN THE SOFTWARE.
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/clock/sun8i-r40-ccu.h>
>> +#include <dt-bindings/reset/sun8i-r40-ccu.h>
>> +
>> +/ {
>> +	#address-cells = <1>;
>> +	#size-cells = <1>;
>> +	interrupt-parent = <&gic>;
>> +
>> +	clocks {
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +		ranges;
>> +
>> +		osc24M: osc24M {
>> +			#clock-cells = <0>;
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <24000000>;
>> +			clock-output-names = "osc24M";
>> +		};
>> +
>> +		osc32k: osc32k {
>> +			#clock-cells = <0>;
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <32768>;
>> +			clock-output-names = "osc32k";
>> +		};
>> +	};
>> +
>> +	cpus {
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +
>> +		cpu@0 {
>> +			compatible = "arm,cortex-a7";
>> +			device_type = "cpu";
>> +			reg = <0>;
>> +		};
>> +
>> +		cpu@1 {
>> +			compatible = "arm,cortex-a7";
>> +			device_type = "cpu";
>> +			reg = <1>;
>> +		};
>> +
>> +		cpu@2 {
>> +			compatible = "arm,cortex-a7";
>> +			device_type = "cpu";
>> +			reg = <2>;
>> +		};
>> +
>> +		cpu@3 {
>> +			compatible = "arm,cortex-a7";
>> +			device_type = "cpu";
>> +			reg = <3>;
>> +		};
>> +	};
>> +
>> +	soc {
>> +		compatible = "simple-bus";
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +		ranges;
>> +
>> +		nmi_intc: interrupt-controller@1c00030 {
>> +			compatible = "allwinner,sun7i-a20-sc-nmi";
>> +			interrupt-controller;
>> +			#interrupt-cells = <2>;
>> +			reg = <0x01c00030 0x0c>;
>> +			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
>> +		};
>
>You should use the new compatible here.

It's not the R_INTC, but the same NMI with A20.

R40 has even no R_ peripherals.

>
>> +		mmc0: mmc@1c0f000 {
>> +			compatible = "allwinner,sun50i-a64-mmc";
>
>Please add a soc specific compatible for all the blocks.
>
>> +			reg = <0x01c0f000 0x1000>;
>> +			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
>> +			clock-names = "ahb", "mmc";
>> +			resets = <&ccu RST_BUS_MMC0>;
>> +			reset-names = "ahb";
>> +			pinctrl-0 = <&mmc0_pins>;
>> +			pinctrl-names = "default";
>> +			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
>> +			max-frequency = <150000000>;
>
>have you tested that frequency?

No.

Should I decrease it?

>
>> +			status = "disabled";
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +		};
>> +
>> +		mmc1: mmc@1c10000 {
>> +			compatible = "allwinner,sun50i-a64-mmc";
>> +			reg = <0x01c10000 0x1000>;
>> +			clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
>> +			clock-names = "ahb", "mmc";
>> +			resets = <&ccu RST_BUS_MMC1>;
>> +			reset-names = "ahb";
>> +			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
>> +			max-frequency = <150000000>;
>
>Ditto.
>
>> +			status = "disabled";
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +		};
>> +
>> +		mmc2: mmc@1c11000 {
>> +			compatible = "allwinner,sun50i-a64-emmc";
>> +			reg = <0x01c11000 0x1000>;
>> +			clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
>> +			clock-names = "ahb", "mmc";
>> +			resets = <&ccu RST_BUS_MMC2>;
>> +			reset-names = "ahb";
>> +			pinctrl-0 = <&mmc2_pins>;
>> +			pinctrl-names = "default";
>> +			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
>> +			max-frequency = <200000000>;
>
>Ditto.
>
>> +			status = "disabled";
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +		};
>> +
>> +		mmc3: mmc@1c12000 {
>> +			compatible = "allwinner,sun50i-a64-mmc";
>> +			reg = <0x01c12000 0x1000>;
>> +			clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>;
>> +			clock-names = "ahb", "mmc";
>> +			resets = <&ccu RST_BUS_MMC3>;
>> +			reset-names = "ahb";
>> +			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
>> +			max-frequency = <150000000>;
>
>Ditto.
>
>> +			status = "disabled";
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +		};
>> +
>> +		ccu: clock@1c20000 {
>> +			compatible = "allwinner,sun8i-r40-ccu";
>> +			reg = <0x01c20000 0x400>;
>> +			clocks = <&osc24M>, <&osc32k>;
>> +			clock-names = "hosc", "losc";
>> +			#clock-cells = <1>;
>> +			#reset-cells = <1>;
>> +		};
>> +
>> +		pio: pinctrl@1c20800 {
>> +			compatible = "allwinner,sun8i-r40-pinctrl";
>> +			reg = <0x01c20800 0x400>;
>> +			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
>> +			clock-names = "apb", "hosc", "losc";
>> +			gpio-controller;
>> +			interrupt-controller;
>> +			#interrupt-cells = <3>;
>> +			#gpio-cells = <3>;
>> +
>> +			i2c0_pins: i2c0-pins {
>> +				pins = "PB0", "PB1";
>> +				function = "i2c0";
>> +			};
>> +
>> +			mmc0_pins: mmc0-pins {
>> +				pins = "PF0", "PF1", "PF2",
>> +				       "PF3", "PF4", "PF5";
>> +				function = "mmc0";
>> +				drive-strength = <30>;
>> +				bias-pull-up;
>> +			};
>> +
>> +			mmc1_pg_pins: mmc1-pg-pins {
>> +				pins = "PG0", "PG1", "PG2",
>> +				       "PG3", "PG4", "PG5";
>> +				function = "mmc1";
>> +				drive-strength = <30>;
>> +				bias-pull-up;
>> +			};
>> +
>> +			mmc2_pins: mmc2-pins {
>> +				pins = "PC5", "PC6", "PC7", "PC8", "PC9",
>> +				       "PC10", "PC11", "PC12", "PC13", "PC14",
>> +				       "PC15", "PC24";
>> +				function = "mmc2";
>> +				drive-strength = <30>;
>> +				bias-pull-up;
>> +			};
>> +
>> +			uart0_pb_pins: uart0-pb-pins {
>> +				pins = "PB22", "PB23";
>> +				function = "uart0";
>> +			};
>> +		};
>> +
>> +		uart0: serial@1c28000 {
>> +			compatible = "snps,dw-apb-uart";
>> +			reg = <0x01c28000 0x400>;
>> +			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
>> +			reg-shift = <2>;
>> +			reg-io-width = <4>;
>> +			clocks = <&ccu CLK_BUS_UART0>;
>> +			resets = <&ccu RST_BUS_UART0>;
>> +			status = "disabled";
>> +		};
>> +
>> +		uart1: serial@1c28400 {
>> +			compatible = "snps,dw-apb-uart";
>> +			reg = <0x01c28400 0x400>;
>> +			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
>> +			reg-shift = <2>;
>> +			reg-io-width = <4>;
>> +			clocks = <&ccu CLK_BUS_UART1>;
>> +			resets = <&ccu RST_BUS_UART1>;
>> +			status = "disabled";
>> +		};
>> +
>> +		uart2: serial@1c28800 {
>> +			compatible = "snps,dw-apb-uart";
>> +			reg = <0x01c28800 0x400>;
>> +			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
>> +			reg-shift = <2>;
>> +			reg-io-width = <4>;
>> +			clocks = <&ccu CLK_BUS_UART2>;
>> +			resets = <&ccu RST_BUS_UART2>;
>> +			status = "disabled";
>> +		};
>> +
>> +		uart3: serial@1c28c00 {
>> +			compatible = "snps,dw-apb-uart";
>> +			reg = <0x01c28c00 0x400>;
>> +			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
>> +			reg-shift = <2>;
>> +			reg-io-width = <4>;
>> +			clocks = <&ccu CLK_BUS_UART3>;
>> +			resets = <&ccu RST_BUS_UART3>;
>> +			status = "disabled";
>> +		};
>> +
>> +		uart4: serial@1c29000 {
>> +			compatible = "snps,dw-apb-uart";
>> +			reg = <0x01c29000 0x400>;
>> +			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
>> +			reg-shift = <2>;
>> +			reg-io-width = <4>;
>> +			clocks = <&ccu CLK_BUS_UART4>;
>> +			resets = <&ccu RST_BUS_UART4>;
>> +			status = "disabled";
>> +		};
>> +
>> +		uart5: serial@1c29400 {
>> +			compatible = "snps,dw-apb-uart";
>> +			reg = <0x01c29400 0x400>;
>> +			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>> +			reg-shift = <2>;
>> +			reg-io-width = <4>;
>> +			clocks = <&ccu CLK_BUS_UART5>;
>> +			resets = <&ccu RST_BUS_UART5>;
>> +			status = "disabled";
>> +		};
>> +
>> +		uart6: serial@1c29800 {
>> +			compatible = "snps,dw-apb-uart";
>> +			reg = <0x01c29800 0x400>;
>> +			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>> +			reg-shift = <2>;
>> +			reg-io-width = <4>;
>> +			clocks = <&ccu CLK_BUS_UART6>;
>> +			resets = <&ccu RST_BUS_UART6>;
>> +			status = "disabled";
>> +		};
>> +
>> +		uart7: serial@1c29c00 {
>> +			compatible = "snps,dw-apb-uart";
>> +			reg = <0x01c29c00 0x400>;
>> +			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
>> +			reg-shift = <2>;
>> +			reg-io-width = <4>;
>> +			clocks = <&ccu CLK_BUS_UART7>;
>> +			resets = <&ccu RST_BUS_UART7>;
>> +			status = "disabled";
>> +		};
>> +
>> +		i2c0: i2c@1c2ac00 {
>> +			compatible = "allwinner,sun6i-a31-i2c";
>> +			reg = <0x01c2ac00 0x400>;
>> +			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&ccu CLK_BUS_I2C0>;
>> +			resets = <&ccu RST_BUS_I2C0>;
>> +			pinctrl-0 = <&i2c0_pins>;
>> +			pinctrl-names = "default";
>> +			status = "disabled";
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +		};
>> +
>> +		i2c1: i2c@1c2b000 {
>> +			compatible = "allwinner,sun6i-a31-i2c";
>> +			reg = <0x01c2b000 0x400>;
>> +			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&ccu CLK_BUS_I2C1>;
>> +			resets = <&ccu RST_BUS_I2C1>;
>> +			status = "disabled";
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +		};
>> +
>> +		i2c2: i2c@1c2b400 {
>> +			compatible = "allwinner,sun6i-a31-i2c";
>> +			reg = <0x01c2b400 0x400>;
>> +			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&ccu CLK_BUS_I2C2>;
>> +			resets = <&ccu RST_BUS_I2C2>;
>> +			status = "disabled";
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +		};
>> +
>> +		i2c3: i2c@1c2b800 {
>> +			compatible = "allwinner,sun6i-a31-i2c";
>> +			reg = <0x01c2b800 0x400>;
>> +			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&ccu CLK_BUS_I2C3>;
>> +			resets = <&ccu RST_BUS_I2C3>;
>> +			status = "disabled";
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +		};
>> +
>> +		i2c4: i2c@1c2c000 {
>> +			compatible = "allwinner,sun6i-a31-i2c";
>> +			reg = <0x01c2c000 0x400>;
>> +			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&ccu CLK_BUS_I2C4>;
>> +			resets = <&ccu RST_BUS_I2C4>;
>> +			status = "disabled";
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +		};
>> +
>> +		gic: interrupt-controller@1c81000 {
>> +			compatible = "arm,gic-400";
>> +			reg = <0x01c81000 0x1000>,
>> +			      <0x01c82000 0x1000>,
>> +			      <0x01c84000 0x2000>,
>> +			      <0x01c86000 0x2000>;
>> +			interrupt-controller;
>> +			#interrupt-cells = <3>;
>> +			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
>IRQ_TYPE_LEVEL_HIGH)>;
>> +		};
>> +	};
>> +
>> +	timer {
>> +		compatible = "arm,armv7-timer";
>> +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
>IRQ_TYPE_LEVEL_LOW)>,
>> +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> +			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>
>Those masks are wrong.
>
>Maxime

Re: [PATCH 2/3] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra

[Icenowy Zheng]

于 2017年8月23日 GMT+08:00 上午4:10:43, Maxime Ripard <maxime.ripard@free-electrons.com> 写到:
>Hi,
>
>On Tue, Aug 22, 2017 at 02:17:41PM +0800, Icenowy Zheng wrote:
>> From: Chen-Yu Tsai <wens@csie.org>
>> 
>> The Banana Pi M2 Ultra is an SBC based on the Allwinner R40 SoC. The
>> form factor and position of various connectors, leds and buttons is
>> similar to the Banana Pi M1+, Banana Pi M3, and is exactly the same
>> as the latest Banana Pi M64.
>> 
>> It features:
>> 
>>   - X-Powers AXP221s PMIC connected to i2c0
>>   - 2 GB DDR3 DRAM
>>   - 8 GB eMMC
>>   - micro SD card slot
>>   - DC power jack
>>   - HDMI output
>>   - MIPI DSI connector
>>   - 2x USB 2.0 hosts
>>   - 1x USB 2.0 OTG
>>   - gigabit ethernet with Realtek RTL8211E transceiver
>>   - WiFi/Bluetooth with AP6212 chip, with external antenna connector
>>   - SATA and power connectors for native SATA support
>>   - camera sensor connector
>>   - consumer IR receiver
>>   - audio out headphone jack
>>   - onboard microphone
>>   - red, green, and blue LEDs
>>   - debug UART pins
>>   - Li-Po battery connector
>>   - Raspberry Pi B+ compatible GPIO header
>>   - power, reset, and boot control buttons
>> 
>> This patch adds a dts file that enables UART, MMC and PMIC support.
>> 
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>> ---
>>  arch/arm/boot/dts/Makefile                        |   1 +
>>  arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 181
>++++++++++++++++++++++
>>  2 files changed, 182 insertions(+)
>>  create mode 100644 arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
>> 
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index 570e107bf702..e0b1ed3e2e24 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -927,6 +927,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
>>  	sun8i-h3-orangepi-plus2e.dtb \
>>  	sun8i-r16-bananapi-m2m.dtb \
>>  	sun8i-r16-parrot.dtb \
>> +	sun8i-r40-bananapi-m2-ultra.dtb \
>>  	sun8i-v3s-licheepi-zero.dtb \
>>  	sun8i-v3s-licheepi-zero-dock.dtb
>>  dtb-$(CONFIG_MACH_SUN9I) += \
>> diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
>b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
>> new file mode 100644
>> index 000000000000..daf55556036f
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
>> @@ -0,0 +1,181 @@
>> +/*
>> + * Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
>> + * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this
>dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + *  a) This file is free software; you can redistribute it and/or
>> + *     modify it under the terms of the GNU General Public License
>as
>> + *     published by the Free Software Foundation; either version 2
>of the
>> + *     License, or (at your option) any later version.
>> + *
>> + *     This file is distributed in the hope that it will be useful,
>> + *     but WITHOUT ANY WARRANTY; without even the implied warranty
>of
>> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + *     GNU General Public License for more details.
>> + *
>> + * Or, alternatively,
>> + *
>> + *  b) Permission is hereby granted, free of charge, to any person
>> + *     obtaining a copy of this software and associated
>documentation
>> + *     files (the "Software"), to deal in the Software without
>> + *     restriction, including without limitation the rights to use,
>> + *     copy, modify, merge, publish, distribute, sublicense, and/or
>> + *     sell copies of the Software, and to permit persons to whom
>the
>> + *     Software is furnished to do so, subject to the following
>> + *     conditions:
>> + *
>> + *     The above copyright notice and this permission notice shall
>be
>> + *     included in all copies or substantial portions of the
>Software.
>> + *
>> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
>KIND,
>> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
>WARRANTIES
>> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + *     OTHER DEALINGS IN THE SOFTWARE.
>> + */
>> +
>> +/dts-v1/;
>> +#include "sun8i-r40.dtsi"
>> +#include "sunxi-common-regulators.dtsi"
>> +
>> +/ {
>> +	model = "Banana Pi BPI-M2-Ultra";
>> +	compatible = "sinovoip,bpi-m2-ultra", "allwinner,sun8i-r40";
>> +
>> +	aliases {
>> +		serial0 = &uart0;
>> +	};
>> +
>> +	chosen {
>> +		stdout-path = "serial0:115200n8";
>> +	};
>
>Missing newline
>
>> +	leds {
>> +		compatible = "gpio-leds";
>> +
>> +		pwr-led {
>> +			label = "bananapi:red:pwr";
>> +			gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
>> +			default-state = "on";
>> +		};
>> +
>> +		user-led-green {
>> +			label = "bananapi:green:user";
>> +			gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>;
>> +		};
>> +
>> +		user-led-blue {
>> +			label = "bananapi:blue:user";
>> +			gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>;
>> +		};
>> +	};
>> +
>> +	wifi_pwrseq: wifi_pwrseq {
>> +		compatible = "mmc-pwrseq-simple";
>> +		reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */
>> +	};
>> +};
>> +
>> +&i2c0 {
>> +	status = "okay";
>> +
>> +	axp22x: pmic@34 {
>> +		compatible = "x-powers,axp221";
>> +		reg = <0x34>;
>> +		interrupt-parent = <&nmi_intc>;
>> +		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
>> +	};
>> +};
>> +
>> +#include "axp22x.dtsi"
>> +
>> +&reg_aldo3 {
>> +	regulator-always-on;
>> +	regulator-min-microvolt = <2700000>;
>> +	regulator-max-microvolt = <3300000>;
>> +	regulator-name = "avcc";
>> +};
>> +
>> +&reg_dcdc1 {
>> +	regulator-always-on;
>> +	regulator-min-microvolt = <3000000>;
>> +	regulator-max-microvolt = <3000000>;
>> +	regulator-name = "vcc-3v0";
>> +};
>> +
>> +&reg_dcdc2 {
>> +	regulator-always-on;
>> +	regulator-min-microvolt = <1000000>;
>> +	regulator-max-microvolt = <1300000>;
>> +	regulator-name = "vdd-cpu";
>> +};
>> +
>> +&reg_dcdc3 {
>> +	regulator-always-on;
>> +	regulator-min-microvolt = <1000000>;
>> +	regulator-max-microvolt = <1300000>;
>> +	regulator-name = "vdd-sys";
>> +};
>> +
>> +&reg_dcdc5 {
>> +	regulator-always-on;
>> +	regulator-min-microvolt = <1500000>;
>> +	regulator-max-microvolt = <1500000>;
>> +	regulator-name = "vcc-dram";
>> +};
>> +
>> +&reg_dldo1 {
>> +	regulator-min-microvolt = <1800000>;
>> +	regulator-max-microvolt = <3300000>;
>> +	regulator-name = "vcc-wifi-io";
>> +};
>> +
>> +&reg_dldo2 {
>> +	regulator-min-microvolt = <3300000>;
>> +	regulator-max-microvolt = <3300000>;
>> +	regulator-name = "vcc-wifi";
>> +};
>> +
>> +&reg_vcc5v0 {
>> +	gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */
>> +	enable-active-high;
>> +};
>
>That regulator is unused, and the GPIO is marked to be unused on the
>schematics.

It's a change in newer revision board.

I got this infomation directly from BPi people, not from schematics.

>
>> +&mmc0 {
>> +	vmmc-supply = <&reg_dcdc1>;
>> +	bus-width = <4>;
>> +	cd-gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; /* PH13 */
>> +	cd-inverted;
>> +	status = "okay";
>> +};
>> +
>> +&mmc1 {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&mmc1_pg_pins>;
>> +	vmmc-supply = <&reg_dldo2>;
>> +	vqmmc-supply = <&reg_dldo1>;
>> +	mmc-pwrseq = <&wifi_pwrseq>;
>> +	bus-width = <4>;
>> +	non-removable;
>> +	status = "okay";
>> +};
>> +
>> +&mmc2 {
>> +	vmmc-supply = <&reg_dcdc1>;
>> +	vqmmc-supply = <&reg_dcdc1>;
>
>You don't need vqmmc here.
>
>Maxime

Re: [PATCH 3/3] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Berry

[Icenowy Zheng]

于 2017年8月23日 GMT+08:00 上午4:12:15, Maxime Ripard <maxime.ripard@free-electrons.com> 写到:
>On Tue, Aug 22, 2017 at 02:17:42PM +0800, Icenowy Zheng wrote:
>> +&reg_vcc5v0 {
>> +	gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */
>> +	enable-active-high;
>> +};
>
>Same thing here, you're not using that regulator anywhere. You don't
>even use any of the regulators in sunxi-common-regulators.

Maybe I should drop the regulator now, and re-introduce it when adding USB/SATA?

>
>Maxime

Re: [PATCH 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40

[icenowy]

在 2017-08-23 04:05，Maxime Ripard 写道：
> Hi,
> 
> On Tue, Aug 22, 2017 at 02:17:40PM +0800, Icenowy Zheng wrote:
>> From: Chen-Yu Tsai <wens@csie.org>
>> 
>> The Allwinner R40 SoC is marketed as the successor to the A20 SoC.
>> The R40 is a smaller chip than the A20, but features the same set
>> of programmable pins, with a couple extra pins and some new pin
>> functions. The chip features 4 Cortex-A7 cores and a Mali-400 MP2
>> GPU. It retains most if not all features from the A20, while adding
>> some new features, such as MIPI DSI output, or updating various
>> hardware blocks, such as DE 2.0.
>> 
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> 
> I'm not sure why you have two series to achieve one thing here. And
> the fact that you don't have a cover letter doesn't make it any
> clearer.
> 
> Please make series based on what you're trying to do and not split it
> arbitrarily. And document what you're doing in a cover letter.
> 
>> ---
>>  arch/arm/boot/dts/sun8i-r40.dtsi | 396 
>> +++++++++++++++++++++++++++++++++++++++
>>  1 file changed, 396 insertions(+)
>>  create mode 100644 arch/arm/boot/dts/sun8i-r40.dtsi
>> 
>> diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi 
>> b/arch/arm/boot/dts/sun8i-r40.dtsi
>> new file mode 100644
>> index 000000000000..5b48801bdd01
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
>> @@ -0,0 +1,396 @@
>> +/*
>> + * Copyright 2017 Chen-Yu Tsai <wens@csie.org>
>> + * Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + *  a) This file is free software; you can redistribute it and/or
>> + *     modify it under the terms of the GNU General Public License as
>> + *     published by the Free Software Foundation; either version 2 of 
>> the
>> + *     License, or (at your option) any later version.
>> + *
>> + *     This file is distributed in the hope that it will be useful,
>> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + *     GNU General Public License for more details.
>> + *
>> + * Or, alternatively,
>> + *
>> + *  b) Permission is hereby granted, free of charge, to any person
>> + *     obtaining a copy of this software and associated documentation
>> + *     files (the "Software"), to deal in the Software without
>> + *     restriction, including without limitation the rights to use,
>> + *     copy, modify, merge, publish, distribute, sublicense, and/or
>> + *     sell copies of the Software, and to permit persons to whom the
>> + *     Software is furnished to do so, subject to the following
>> + *     conditions:
>> + *
>> + *     The above copyright notice and this permission notice shall be
>> + *     included in all copies or substantial portions of the 
>> Software.
>> + *
>> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY 
>> KIND,
>> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE 
>> WARRANTIES
>> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + *     OTHER DEALINGS IN THE SOFTWARE.
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/clock/sun8i-r40-ccu.h>
>> +#include <dt-bindings/reset/sun8i-r40-ccu.h>
>> +
>> +/ {
>> +	#address-cells = <1>;
>> +	#size-cells = <1>;
>> +	interrupt-parent = <&gic>;
>> +
>> +	clocks {
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +		ranges;
>> +
>> +		osc24M: osc24M {
>> +			#clock-cells = <0>;
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <24000000>;
>> +			clock-output-names = "osc24M";
>> +		};
>> +
>> +		osc32k: osc32k {
>> +			#clock-cells = <0>;
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <32768>;
>> +			clock-output-names = "osc32k";
>> +		};
>> +	};
>> +
>> +	cpus {
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +
>> +		cpu@0 {
>> +			compatible = "arm,cortex-a7";
>> +			device_type = "cpu";
>> +			reg = <0>;
>> +		};
>> +
>> +		cpu@1 {
>> +			compatible = "arm,cortex-a7";
>> +			device_type = "cpu";
>> +			reg = <1>;
>> +		};
>> +
>> +		cpu@2 {
>> +			compatible = "arm,cortex-a7";
>> +			device_type = "cpu";
>> +			reg = <2>;
>> +		};
>> +
>> +		cpu@3 {
>> +			compatible = "arm,cortex-a7";
>> +			device_type = "cpu";
>> +			reg = <3>;
>> +		};
>> +	};
>> +
>> +	soc {
>> +		compatible = "simple-bus";
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +		ranges;
>> +
>> +		nmi_intc: interrupt-controller@1c00030 {
>> +			compatible = "allwinner,sun7i-a20-sc-nmi";
>> +			interrupt-controller;
>> +			#interrupt-cells = <2>;
>> +			reg = <0x01c00030 0x0c>;
>> +			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
>> +		};
> 
> You should use the new compatible here.
> 
>> +		mmc0: mmc@1c0f000 {
>> +			compatible = "allwinner,sun50i-a64-mmc";
> 
> Please add a soc specific compatible for all the blocks.
> 
>> +			reg = <0x01c0f000 0x1000>;
>> +			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
>> +			clock-names = "ahb", "mmc";
>> +			resets = <&ccu RST_BUS_MMC0>;
>> +			reset-names = "ahb";
>> +			pinctrl-0 = <&mmc0_pins>;
>> +			pinctrl-names = "default";
>> +			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
>> +			max-frequency = <150000000>;
> 
> have you tested that frequency?

I think the frequency should be kept here, although my cards cannot
reach this frequency.

The numbers are same as the corresponding controllers in A64.

Maybe I should add a comment saying it's educated guess?

> 
>> +			status = "disabled";
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +		};
>> +
>> +		mmc1: mmc@1c10000 {
>> +			compatible = "allwinner,sun50i-a64-mmc";
>> +			reg = <0x01c10000 0x1000>;
>> +			clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
>> +			clock-names = "ahb", "mmc";
>> +			resets = <&ccu RST_BUS_MMC1>;
>> +			reset-names = "ahb";
>> +			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
>> +			max-frequency = <150000000>;
> 
> Ditto.
> 
>> +			status = "disabled";
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +		};
>> +
>> +		mmc2: mmc@1c11000 {
>> +			compatible = "allwinner,sun50i-a64-emmc";
>> +			reg = <0x01c11000 0x1000>;
>> +			clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
>> +			clock-names = "ahb", "mmc";
>> +			resets = <&ccu RST_BUS_MMC2>;
>> +			reset-names = "ahb";
>> +			pinctrl-0 = <&mmc2_pins>;
>> +			pinctrl-names = "default";
>> +			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
>> +			max-frequency = <200000000>;
> 
> Ditto.
> 
>> +			status = "disabled";
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +		};
>> +
>> +		mmc3: mmc@1c12000 {
>> +			compatible = "allwinner,sun50i-a64-mmc";
>> +			reg = <0x01c12000 0x1000>;
>> +			clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>;
>> +			clock-names = "ahb", "mmc";
>> +			resets = <&ccu RST_BUS_MMC3>;
>> +			reset-names = "ahb";
>> +			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
>> +			max-frequency = <150000000>;
> 
> Ditto.
> 
>> +			status = "disabled";
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +		};
>> +
>> +		ccu: clock@1c20000 {
>> +			compatible = "allwinner,sun8i-r40-ccu";
>> +			reg = <0x01c20000 0x400>;
>> +			clocks = <&osc24M>, <&osc32k>;
>> +			clock-names = "hosc", "losc";
>> +			#clock-cells = <1>;
>> +			#reset-cells = <1>;
>> +		};
>> +
>> +		pio: pinctrl@1c20800 {
>> +			compatible = "allwinner,sun8i-r40-pinctrl";
>> +			reg = <0x01c20800 0x400>;
>> +			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
>> +			clock-names = "apb", "hosc", "losc";
>> +			gpio-controller;
>> +			interrupt-controller;
>> +			#interrupt-cells = <3>;
>> +			#gpio-cells = <3>;
>> +
>> +			i2c0_pins: i2c0-pins {
>> +				pins = "PB0", "PB1";
>> +				function = "i2c0";
>> +			};
>> +
>> +			mmc0_pins: mmc0-pins {
>> +				pins = "PF0", "PF1", "PF2",
>> +				       "PF3", "PF4", "PF5";
>> +				function = "mmc0";
>> +				drive-strength = <30>;
>> +				bias-pull-up;
>> +			};
>> +
>> +			mmc1_pg_pins: mmc1-pg-pins {
>> +				pins = "PG0", "PG1", "PG2",
>> +				       "PG3", "PG4", "PG5";
>> +				function = "mmc1";
>> +				drive-strength = <30>;
>> +				bias-pull-up;
>> +			};
>> +
>> +			mmc2_pins: mmc2-pins {
>> +				pins = "PC5", "PC6", "PC7", "PC8", "PC9",
>> +				       "PC10", "PC11", "PC12", "PC13", "PC14",
>> +				       "PC15", "PC24";
>> +				function = "mmc2";
>> +				drive-strength = <30>;
>> +				bias-pull-up;
>> +			};
>> +
>> +			uart0_pb_pins: uart0-pb-pins {
>> +				pins = "PB22", "PB23";
>> +				function = "uart0";
>> +			};
>> +		};
>> +
>> +		uart0: serial@1c28000 {
>> +			compatible = "snps,dw-apb-uart";
>> +			reg = <0x01c28000 0x400>;
>> +			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
>> +			reg-shift = <2>;
>> +			reg-io-width = <4>;
>> +			clocks = <&ccu CLK_BUS_UART0>;
>> +			resets = <&ccu RST_BUS_UART0>;
>> +			status = "disabled";
>> +		};
>> +
>> +		uart1: serial@1c28400 {
>> +			compatible = "snps,dw-apb-uart";
>> +			reg = <0x01c28400 0x400>;
>> +			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
>> +			reg-shift = <2>;
>> +			reg-io-width = <4>;
>> +			clocks = <&ccu CLK_BUS_UART1>;
>> +			resets = <&ccu RST_BUS_UART1>;
>> +			status = "disabled";
>> +		};
>> +
>> +		uart2: serial@1c28800 {
>> +			compatible = "snps,dw-apb-uart";
>> +			reg = <0x01c28800 0x400>;
>> +			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
>> +			reg-shift = <2>;
>> +			reg-io-width = <4>;
>> +			clocks = <&ccu CLK_BUS_UART2>;
>> +			resets = <&ccu RST_BUS_UART2>;
>> +			status = "disabled";
>> +		};
>> +
>> +		uart3: serial@1c28c00 {
>> +			compatible = "snps,dw-apb-uart";
>> +			reg = <0x01c28c00 0x400>;
>> +			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
>> +			reg-shift = <2>;
>> +			reg-io-width = <4>;
>> +			clocks = <&ccu CLK_BUS_UART3>;
>> +			resets = <&ccu RST_BUS_UART3>;
>> +			status = "disabled";
>> +		};
>> +
>> +		uart4: serial@1c29000 {
>> +			compatible = "snps,dw-apb-uart";
>> +			reg = <0x01c29000 0x400>;
>> +			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
>> +			reg-shift = <2>;
>> +			reg-io-width = <4>;
>> +			clocks = <&ccu CLK_BUS_UART4>;
>> +			resets = <&ccu RST_BUS_UART4>;
>> +			status = "disabled";
>> +		};
>> +
>> +		uart5: serial@1c29400 {
>> +			compatible = "snps,dw-apb-uart";
>> +			reg = <0x01c29400 0x400>;
>> +			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>> +			reg-shift = <2>;
>> +			reg-io-width = <4>;
>> +			clocks = <&ccu CLK_BUS_UART5>;
>> +			resets = <&ccu RST_BUS_UART5>;
>> +			status = "disabled";
>> +		};
>> +
>> +		uart6: serial@1c29800 {
>> +			compatible = "snps,dw-apb-uart";
>> +			reg = <0x01c29800 0x400>;
>> +			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>> +			reg-shift = <2>;
>> +			reg-io-width = <4>;
>> +			clocks = <&ccu CLK_BUS_UART6>;
>> +			resets = <&ccu RST_BUS_UART6>;
>> +			status = "disabled";
>> +		};
>> +
>> +		uart7: serial@1c29c00 {
>> +			compatible = "snps,dw-apb-uart";
>> +			reg = <0x01c29c00 0x400>;
>> +			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
>> +			reg-shift = <2>;
>> +			reg-io-width = <4>;
>> +			clocks = <&ccu CLK_BUS_UART7>;
>> +			resets = <&ccu RST_BUS_UART7>;
>> +			status = "disabled";
>> +		};
>> +
>> +		i2c0: i2c@1c2ac00 {
>> +			compatible = "allwinner,sun6i-a31-i2c";
>> +			reg = <0x01c2ac00 0x400>;
>> +			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&ccu CLK_BUS_I2C0>;
>> +			resets = <&ccu RST_BUS_I2C0>;
>> +			pinctrl-0 = <&i2c0_pins>;
>> +			pinctrl-names = "default";
>> +			status = "disabled";
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +		};
>> +
>> +		i2c1: i2c@1c2b000 {
>> +			compatible = "allwinner,sun6i-a31-i2c";
>> +			reg = <0x01c2b000 0x400>;
>> +			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&ccu CLK_BUS_I2C1>;
>> +			resets = <&ccu RST_BUS_I2C1>;
>> +			status = "disabled";
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +		};
>> +
>> +		i2c2: i2c@1c2b400 {
>> +			compatible = "allwinner,sun6i-a31-i2c";
>> +			reg = <0x01c2b400 0x400>;
>> +			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&ccu CLK_BUS_I2C2>;
>> +			resets = <&ccu RST_BUS_I2C2>;
>> +			status = "disabled";
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +		};
>> +
>> +		i2c3: i2c@1c2b800 {
>> +			compatible = "allwinner,sun6i-a31-i2c";
>> +			reg = <0x01c2b800 0x400>;
>> +			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&ccu CLK_BUS_I2C3>;
>> +			resets = <&ccu RST_BUS_I2C3>;
>> +			status = "disabled";
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +		};
>> +
>> +		i2c4: i2c@1c2c000 {
>> +			compatible = "allwinner,sun6i-a31-i2c";
>> +			reg = <0x01c2c000 0x400>;
>> +			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&ccu CLK_BUS_I2C4>;
>> +			resets = <&ccu RST_BUS_I2C4>;
>> +			status = "disabled";
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +		};
>> +
>> +		gic: interrupt-controller@1c81000 {
>> +			compatible = "arm,gic-400";
>> +			reg = <0x01c81000 0x1000>,
>> +			      <0x01c82000 0x1000>,
>> +			      <0x01c84000 0x2000>,
>> +			      <0x01c86000 0x2000>;
>> +			interrupt-controller;
>> +			#interrupt-cells = <3>;
>> +			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 
>> IRQ_TYPE_LEVEL_HIGH)>;
>> +		};
>> +	};
>> +
>> +	timer {
>> +		compatible = "arm,armv7-timer";
>> +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 
>> IRQ_TYPE_LEVEL_LOW)>,
>> +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> +			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> 
> Those masks are wrong.

I compared it with other sun8i SoCs' device tree.

Where's wrong?

> 
> Maxime

Re: [PATCH 3/3] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Berry

[Maxime Ripard]

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On Wed, Aug 23, 2017 at 01:46:50PM +0800, Icenowy Zheng wrote:
> 
> 
> 于 2017年8月23日 GMT+08:00 上午4:12:15, Maxime Ripard <maxime.ripard@free-electrons.com> 写到:
> >On Tue, Aug 22, 2017 at 02:17:42PM +0800, Icenowy Zheng wrote:
> >> +&reg_vcc5v0 {
> >> +	gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */
> >> +	enable-active-high;
> >> +};
> >
> >Same thing here, you're not using that regulator anywhere. You don't
> >even use any of the regulators in sunxi-common-regulators.
> 
> Maybe I should drop the regulator now, and re-introduce it when adding USB/SATA?

If that's what it's used for, then yes, please.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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Re: [PATCH 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40

[Maxime Ripard]

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On Wed, Aug 23, 2017 at 07:56:29PM +0800, icenowy@aosc.io wrote:
> > > +			reg = <0x01c0f000 0x1000>;
> > > +			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
> > > +			clock-names = "ahb", "mmc";
> > > +			resets = <&ccu RST_BUS_MMC0>;
> > > +			reset-names = "ahb";
> > > +			pinctrl-0 = <&mmc0_pins>;
> > > +			pinctrl-names = "default";
> > > +			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> > > +			max-frequency = <150000000>;
> > 
> > have you tested that frequency?
> 
> I think the frequency should be kept here, although my cards cannot
> reach this frequency.
> 
> The numbers are same as the corresponding controllers in A64.
> 
> Maybe I should add a comment saying it's educated guess?

I'd rather have it tested by someone, and then add the proper
frequencies. It took quite a while to figure out how these modes were
supposed to be working on the A64, so it's not obvious that they're
just going to work.

> > > +		gic: interrupt-controller@1c81000 {
> > > +			compatible = "arm,gic-400";
> > > +			reg = <0x01c81000 0x1000>,
> > > +			      <0x01c82000 0x1000>,
> > > +			      <0x01c84000 0x2000>,
> > > +			      <0x01c86000 0x2000>;
> > > +			interrupt-controller;
> > > +			#interrupt-cells = <3>;
> > > +			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
> > > IRQ_TYPE_LEVEL_HIGH)>;
> > > +		};
> > > +	};
> > > +
> > > +	timer {
> > > +		compatible = "arm,armv7-timer";
> > > +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
> > > IRQ_TYPE_LEVEL_LOW)>,
> > > +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> > > +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> > > +			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> > 
> > Those masks are wrong.
> 
> I compared it with other sun8i SoCs' device tree.
> 
> Where's wrong?

It's supposed to be a mask of the CPUs in your system. Since you just
have one of them, it shouldn't be 4.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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Re: [PATCH 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40

[icenowy]

在 2017-08-23 22:35，Maxime Ripard 写道：
> On Wed, Aug 23, 2017 at 07:56:29PM +0800, icenowy@aosc.io wrote:
>> > > +			reg = <0x01c0f000 0x1000>;
>> > > +			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
>> > > +			clock-names = "ahb", "mmc";
>> > > +			resets = <&ccu RST_BUS_MMC0>;
>> > > +			reset-names = "ahb";
>> > > +			pinctrl-0 = <&mmc0_pins>;
>> > > +			pinctrl-names = "default";
>> > > +			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
>> > > +			max-frequency = <150000000>;
>> >
>> > have you tested that frequency?
>> 
>> I think the frequency should be kept here, although my cards cannot
>> reach this frequency.
>> 
>> The numbers are same as the corresponding controllers in A64.
>> 
>> Maybe I should add a comment saying it's educated guess?
> 
> I'd rather have it tested by someone, and then add the proper
> frequencies. It took quite a while to figure out how these modes were
> supposed to be working on the A64, so it's not obvious that they're
> just going to work.

Should I add my results here?

MMC0: 25MHz
MMC1: 50MHz
MMC2: 52MHz
MMC3: not wired :-(

I think it's conservative enough and works well ;-)

> 
>> > > +		gic: interrupt-controller@1c81000 {
>> > > +			compatible = "arm,gic-400";
>> > > +			reg = <0x01c81000 0x1000>,
>> > > +			      <0x01c82000 0x1000>,
>> > > +			      <0x01c84000 0x2000>,
>> > > +			      <0x01c86000 0x2000>;
>> > > +			interrupt-controller;
>> > > +			#interrupt-cells = <3>;
>> > > +			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
>> > > IRQ_TYPE_LEVEL_HIGH)>;
>> > > +		};
>> > > +	};
>> > > +
>> > > +	timer {
>> > > +		compatible = "arm,armv7-timer";
>> > > +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
>> > > IRQ_TYPE_LEVEL_LOW)>,
>> > > +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> > > +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> > > +			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>> >
>> > Those masks are wrong.
>> 
>> I compared it with other sun8i SoCs' device tree.
>> 
>> Where's wrong?
> 
> It's supposed to be a mask of the CPUs in your system. Since you just
> have one of them, it shouldn't be 4.

R40 has 4 cores...

Or I didn't understand this?

> 
> Maxime

Re: [PATCH 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40

[Maxime Ripard]

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On Wed, Aug 23, 2017 at 11:13:04PM +0800, icenowy@aosc.io wrote:
> 在 2017-08-23 22:35，Maxime Ripard 写道：
> > On Wed, Aug 23, 2017 at 07:56:29PM +0800, icenowy@aosc.io wrote:
> > > > > +			reg = <0x01c0f000 0x1000>;
> > > > > +			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
> > > > > +			clock-names = "ahb", "mmc";
> > > > > +			resets = <&ccu RST_BUS_MMC0>;
> > > > > +			reset-names = "ahb";
> > > > > +			pinctrl-0 = <&mmc0_pins>;
> > > > > +			pinctrl-names = "default";
> > > > > +			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> > > > > +			max-frequency = <150000000>;
> > > >
> > > > have you tested that frequency?
> > > 
> > > I think the frequency should be kept here, although my cards cannot
> > > reach this frequency.
> > > 
> > > The numbers are same as the corresponding controllers in A64.
> > > 
> > > Maybe I should add a comment saying it's educated guess?
> > 
> > I'd rather have it tested by someone, and then add the proper
> > frequencies. It took quite a while to figure out how these modes were
> > supposed to be working on the A64, so it's not obvious that they're
> > just going to work.
> 
> Should I add my results here?
> 
> MMC0: 25MHz
> MMC1: 50MHz
> MMC2: 52MHz
> MMC3: not wired :-(
> 
> I think it's conservative enough and works well ;-)

And that's my point. You didn't test HS200, SDR50 or SDR104 for
example. So you have no idea whether the frequencies from 50MHz to
150MHz are actually working or not.

> 
> > 
> > > > > +		gic: interrupt-controller@1c81000 {
> > > > > +			compatible = "arm,gic-400";
> > > > > +			reg = <0x01c81000 0x1000>,
> > > > > +			      <0x01c82000 0x1000>,
> > > > > +			      <0x01c84000 0x2000>,
> > > > > +			      <0x01c86000 0x2000>;
> > > > > +			interrupt-controller;
> > > > > +			#interrupt-cells = <3>;
> > > > > +			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
> > > > > IRQ_TYPE_LEVEL_HIGH)>;
> > > > > +		};
> > > > > +	};
> > > > > +
> > > > > +	timer {
> > > > > +		compatible = "arm,armv7-timer";
> > > > > +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
> > > > > IRQ_TYPE_LEVEL_LOW)>,
> > > > > +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> > > > > +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> > > > > +			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> > > >
> > > > Those masks are wrong.
> > > 
> > > I compared it with other sun8i SoCs' device tree.
> > > 
> > > Where's wrong?
> > 
> > It's supposed to be a mask of the CPUs in your system. Since you just
> > have one of them, it shouldn't be 4.
> 
> R40 has 4 cores...
> 
> Or I didn't understand this?

Gah, sorry, I mistook this for the V3s for some reason...

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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Re: [linux-sunxi] Re: [PATCH 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40

[icenowy]

在 2017-08-24 14:07，Maxime Ripard 写道：
> On Wed, Aug 23, 2017 at 11:13:04PM +0800, icenowy@aosc.io wrote:
>> 在 2017-08-23 22:35，Maxime Ripard 写道：
>> > On Wed, Aug 23, 2017 at 07:56:29PM +0800, icenowy@aosc.io wrote:
>> > > > > +			reg = <0x01c0f000 0x1000>;
>> > > > > +			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
>> > > > > +			clock-names = "ahb", "mmc";
>> > > > > +			resets = <&ccu RST_BUS_MMC0>;
>> > > > > +			reset-names = "ahb";
>> > > > > +			pinctrl-0 = <&mmc0_pins>;
>> > > > > +			pinctrl-names = "default";
>> > > > > +			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
>> > > > > +			max-frequency = <150000000>;
>> > > >
>> > > > have you tested that frequency?
>> > >
>> > > I think the frequency should be kept here, although my cards cannot
>> > > reach this frequency.
>> > >
>> > > The numbers are same as the corresponding controllers in A64.
>> > >
>> > > Maybe I should add a comment saying it's educated guess?
>> >
>> > I'd rather have it tested by someone, and then add the proper
>> > frequencies. It took quite a while to figure out how these modes were
>> > supposed to be working on the A64, so it's not obvious that they're
>> > just going to work.
>> 
>> Should I add my results here?
>> 
>> MMC0: 25MHz
>> MMC1: 50MHz
>> MMC2: 52MHz
>> MMC3: not wired :-(
>> 
>> I think it's conservative enough and works well ;-)
> 
> And that's my point. You didn't test HS200, SDR50 or SDR104 for
> example. So you have no idea whether the frequencies from 50MHz to
> 150MHz are actually working or not.

OK.

I will leave a TODO here, although I cannot measure the frequencies
with Banana Pis -- it will requires custom boards.

> 
>> 
>> >
>> > > > > +		gic: interrupt-controller@1c81000 {
>> > > > > +			compatible = "arm,gic-400";
>> > > > > +			reg = <0x01c81000 0x1000>,
>> > > > > +			      <0x01c82000 0x1000>,
>> > > > > +			      <0x01c84000 0x2000>,
>> > > > > +			      <0x01c86000 0x2000>;
>> > > > > +			interrupt-controller;
>> > > > > +			#interrupt-cells = <3>;
>> > > > > +			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
>> > > > > IRQ_TYPE_LEVEL_HIGH)>;
>> > > > > +		};
>> > > > > +	};
>> > > > > +
>> > > > > +	timer {
>> > > > > +		compatible = "arm,armv7-timer";
>> > > > > +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
>> > > > > IRQ_TYPE_LEVEL_LOW)>,
>> > > > > +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> > > > > +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> > > > > +			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>> > > >
>> > > > Those masks are wrong.
>> > >
>> > > I compared it with other sun8i SoCs' device tree.
>> > >
>> > > Where's wrong?
>> >
>> > It's supposed to be a mask of the CPUs in your system. Since you just
>> > have one of them, it shouldn't be 4.
>> 
>> R40 has 4 cores...
>> 
>> Or I didn't understand this?
> 
> Gah, sorry, I mistook this for the V3s for some reason...

Thanks.

I think I should send a fix for V3s.

> 
> Maxime
> 
> --
> Maxime Ripard, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com