* [PATCH 00/11] Add support for the Mobileye EyeQ5 SoC
@ 2023-10-04 16:10 Gregory CLEMENT
2023-10-04 16:10 ` [PATCH 01/11] MIPS: compressed: Use correct instruction for 64 bit code Gregory CLEMENT
` (10 more replies)
0 siblings, 11 replies; 53+ messages in thread
From: Gregory CLEMENT @ 2023-10-04 16:10 UTC (permalink / raw)
To: Paul Burton, Thomas Bogendoerfer, linux-mips, Rob Herring,
Krzysztof Kozlowski, devicetree, linux-kernel
Cc: Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni, Gregory CLEMENT
Hello,
The EyeQ5 SoC from Mobileye is based on the MIPS I6500 architecture
and features multiple controllers such as the classic UART, I2C, SPI,
as well as CAN-FD, PCIe, Octal/Quad SPI Flash interface, Gigabit
Ethernet, MIPI CSI-2, and eMMC 5.1. It also includes a Hardware
Security Module, Functional Safety Hardware, and MJPEG encoder.
One peculiarity of this SoC is that the physical address of the DDDR
exceeds 32 bits. Given that the architecture is 64 bits, this is not
an issue, but it requires some changes in how the mips64 is currently
managed during boot.
With the second patch, we enable the use of xphys instead of the
legacy kesg0 and kseg1. However, the vector reset remains 32 bits. So
the third patch allows the use of aliasing to map the vector address
using a 32-bit pointer.
While working on it, we found that there was an issue in the way the
assembly code managed kernel uncompression. While most of the head.S
file uses macros to employ the correct instruction depending on
whether it's in 32 or 64 bits, one was missing. Fixing it is the
purpose of the first patch.
Then the following 4 patches document the bindings that will be used
for the device tree of the SoC submitted by patch 7.
In addition to the SoC support, patch 8 adds support for the
evaluation board.
Finally, patch 10 adds support to build the kernel image for the EyeQ5
SoC and board, not only the Kconfig and Makefile infrastructure but
also an ITS file and a default configuration. To build and test the
kernel, we need to run the following commands:
make 64r6el_defconfig BOARDS=eyeq5
make vmlinuz.itb
And then from U-Boot
bootm ${vmlinuz.itb_addr}#conf-1
Gregory
Gregory CLEMENT (9):
MIPS: compressed: Use correct instruction for 64 bit code
dt-bindings: Add vendor prefix for Mobileye Vision Technologies Ltd.
dt-bindings: mips: cpu: Add I-Class I6500 Multiprocessor Core
dt-bindings: mips: Add bindings for Mobileye SoCs
dt-bindings: mfd: syscon: Document EyeQ5 OLB
MIPS: mobileye: Add EyeQ5 dtsi
MIPS: mobileye: Add EPM5 device tree
MIPS: generic: Add support for Mobileye EyeQ5
MAINTAINERS: Add entry for Mobileye MIPS SoCs
Vladimir Kondratiev (2):
MIPS: use virtual addresses from xkphys for MIPS64
MIPS: support RAM beyond 32-bit
.../devicetree/bindings/mfd/syscon.yaml | 1 +
.../devicetree/bindings/mips/cpus.yaml | 1 +
.../devicetree/bindings/mips/mobileye.yaml | 36 ++
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
MAINTAINERS | 12 +
arch/mips/Kconfig | 15 +
arch/mips/Makefile | 4 +
arch/mips/boot/compressed/head.S | 4 +-
arch/mips/boot/dts/Makefile | 1 +
arch/mips/boot/dts/mobileye/Makefile | 6 +
arch/mips/boot/dts/mobileye/eyeq5-epm5.dts | 24 ++
.../boot/dts/mobileye/eyeq5-fixed-clocks.dtsi | 315 ++++++++++++++++++
arch/mips/boot/dts/mobileye/eyeq5.dtsi | 138 ++++++++
arch/mips/configs/generic/board-eyeq5.config | 42 +++
arch/mips/generic/Kconfig | 14 +
arch/mips/generic/Platform | 7 +
arch/mips/generic/board-epm5.its.S | 24 ++
arch/mips/include/asm/addrspace.h | 12 +-
arch/mips/include/asm/mips-cm.h | 1 +
arch/mips/include/asm/page.h | 10 +
arch/mips/include/asm/vga.h | 4 +
arch/mips/kernel/cps-vec.S | 8 +
arch/mips/kernel/genex.S | 14 +
arch/mips/kernel/smp-cps.c | 47 ++-
arch/mips/kernel/traps.c | 32 +-
arch/mips/lib/uncached.c | 10 +
arch/mips/mm/init.c | 4 +-
include/dt-bindings/soc/mobileye,eyeq5.h | 77 +++++
28 files changed, 847 insertions(+), 18 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mips/mobileye.yaml
create mode 100644 arch/mips/boot/dts/mobileye/Makefile
create mode 100644 arch/mips/boot/dts/mobileye/eyeq5-epm5.dts
create mode 100644 arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi
create mode 100644 arch/mips/boot/dts/mobileye/eyeq5.dtsi
create mode 100644 arch/mips/configs/generic/board-eyeq5.config
create mode 100644 arch/mips/generic/board-epm5.its.S
create mode 100644 include/dt-bindings/soc/mobileye,eyeq5.h
--
2.40.1
^ permalink raw reply [flat|nested] 53+ messages in thread
* [PATCH 01/11] MIPS: compressed: Use correct instruction for 64 bit code
2023-10-04 16:10 [PATCH 00/11] Add support for the Mobileye EyeQ5 SoC Gregory CLEMENT
@ 2023-10-04 16:10 ` Gregory CLEMENT
2023-10-05 6:40 ` Philippe Mathieu-Daudé
2023-10-24 1:49 ` Florian Fainelli
2023-10-04 16:10 ` [PATCH 02/11] MIPS: use virtual addresses from xkphys for MIPS64 Gregory CLEMENT
` (9 subsequent siblings)
10 siblings, 2 replies; 53+ messages in thread
From: Gregory CLEMENT @ 2023-10-04 16:10 UTC (permalink / raw)
To: Paul Burton, Thomas Bogendoerfer, linux-mips, Rob Herring,
Krzysztof Kozlowski, devicetree, linux-kernel
Cc: Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni, Gregory CLEMENT
The code clearing BSS already use macro or use correct instruction
depending id the CPU is 32 bits or 64 bits. However, a few
instructions remained 32 bits only.
By using the accurate MACRO, it is now possible to deal with memory
address beyond 32 bits. As a side effect, when using 64bits processor,
it also divides the loop number needed to clear the BSS by 2.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
arch/mips/boot/compressed/head.S | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/mips/boot/compressed/head.S b/arch/mips/boot/compressed/head.S
index 5795d0af1e1b..d237a834b85e 100644
--- a/arch/mips/boot/compressed/head.S
+++ b/arch/mips/boot/compressed/head.S
@@ -25,8 +25,8 @@
/* Clear BSS */
PTR_LA a0, _edata
PTR_LA a2, _end
-1: sw zero, 0(a0)
- addiu a0, a0, 4
+1: PTR_S zero, 0(a0)
+ PTR_ADDIU a0, a0, PTRSIZE
bne a2, a0, 1b
PTR_LA a0, (.heap) /* heap address */
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH 02/11] MIPS: use virtual addresses from xkphys for MIPS64
2023-10-04 16:10 [PATCH 00/11] Add support for the Mobileye EyeQ5 SoC Gregory CLEMENT
2023-10-04 16:10 ` [PATCH 01/11] MIPS: compressed: Use correct instruction for 64 bit code Gregory CLEMENT
@ 2023-10-04 16:10 ` Gregory CLEMENT
2023-10-12 15:34 ` Thomas Bogendoerfer
` (2 more replies)
2023-10-04 16:10 ` [PATCH 03/11] MIPS: support RAM beyond 32-bit Gregory CLEMENT
` (8 subsequent siblings)
10 siblings, 3 replies; 53+ messages in thread
From: Gregory CLEMENT @ 2023-10-04 16:10 UTC (permalink / raw)
To: Paul Burton, Thomas Bogendoerfer, linux-mips, Rob Herring,
Krzysztof Kozlowski, devicetree, linux-kernel
Cc: Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni, Gregory CLEMENT
From: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
Now 64-bit MIPS uses 32-bit compatible segments KSEG0 and KSEG1
to trivially map first 1/2 GByte of physical memory. This memory
used to run kernel. This mean, one should have memory installed
in this area in order for Linux to work.
Kconfig CONFIG_USE_XKPHYS introduced; it adds support for kernel
to use virtual addresses from the XKPHYS segment for both cached
and uncached access. XKPHYS allows to access 2^48 bytes of
memory, thus allowing kernel to work with any memory
configuration.
MIPS CPU sets KX bit in the CP0 status register at reset
if RESET_BASE_MODE (BIT 1) set in the GCR_CL_RESET_BASE.
Reset vector should fit into 32-bit. If reset vector put outside of
KSEG1, BIT(1) should be set in this value.
IRQ handler for CPU updated to generate 64-bit address for jump
Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
arch/mips/Kconfig | 15 +++++++++++++
arch/mips/Makefile | 4 ++++
arch/mips/generic/Platform | 5 +++++
arch/mips/include/asm/addrspace.h | 12 ++++++++--
arch/mips/include/asm/mips-cm.h | 1 +
arch/mips/include/asm/page.h | 10 +++++++++
arch/mips/include/asm/vga.h | 4 ++++
arch/mips/kernel/cps-vec.S | 8 +++++++
arch/mips/kernel/genex.S | 14 ++++++++++++
arch/mips/kernel/smp-cps.c | 37 +++++++++++++++++++++++--------
arch/mips/kernel/traps.c | 32 +++++++++++++++++++++++---
arch/mips/lib/uncached.c | 10 +++++++++
arch/mips/mm/init.c | 4 ++--
13 files changed, 140 insertions(+), 16 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index bc8421859006..92832bbcca5d 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2026,6 +2026,21 @@ config 64BIT
endchoice
+config USE_XKPHYS
+ bool "use virtual address from XKPHYS"
+ depends on 64BIT
+ default n
+ help
+ By default, MIPS uses 32-bit compatible segments KSEG0 and KSEG1
+ to trivially map first 1/2 GByte of physical memory. This mean,
+ one should have memory installed in this area in order for Linux to
+ work. With this option selected, kernel uses virtual addresses from
+ the XKPHYS segment for both cached and uncached access. XKPHYS allows
+ to access 2^48 bytes of memory, thus allowing to work with any memory
+ configuration.
+
+ Say N if not sure
+
config MIPS_VA_BITS_48
bool "48 bits virtual memory"
depends on 64BIT
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index f49807e1f19b..544ee8427cab 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -303,6 +303,10 @@ ifdef CONFIG_64BIT
endif
endif
+ ifdef CONFIG_USE_XKPHYS
+ KBUILD_SYM32 = n
+ endif
+
ifeq ($(KBUILD_SYM32), y)
cflags-$(KBUILD_SYM32) += -msym32 -DKBUILD_64BIT_SYM32
else
diff --git a/arch/mips/generic/Platform b/arch/mips/generic/Platform
index 0c03623f3897..2be9947814ad 100644
--- a/arch/mips/generic/Platform
+++ b/arch/mips/generic/Platform
@@ -12,7 +12,12 @@
cflags-$(CONFIG_MACH_INGENIC_SOC) += -I$(srctree)/arch/mips/include/asm/mach-ingenic
cflags-$(CONFIG_MIPS_GENERIC) += -I$(srctree)/arch/mips/include/asm/mach-generic
+ifndef (CONFIG_USE_XKPHYS)
load-$(CONFIG_MIPS_GENERIC) += 0xffffffff80100000
+else
+load-$(CONFIG_MIPS_GENERIC) += 0xa800000080100000
+endif
+
all-$(CONFIG_MIPS_GENERIC) += vmlinux.gz.itb
its-y := vmlinux.its.S
diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h
index 59a48c60a065..8dc500d8e66d 100644
--- a/arch/mips/include/asm/addrspace.h
+++ b/arch/mips/include/asm/addrspace.h
@@ -65,10 +65,15 @@
#define XKSSEG _CONST64_(0x4000000000000000)
#define XKPHYS _CONST64_(0x8000000000000000)
#define XKSEG _CONST64_(0xc000000000000000)
+#if !defined(CONFIG_USE_XKPHYS)
#define CKSEG0 _CONST64_(0xffffffff80000000)
#define CKSEG1 _CONST64_(0xffffffffa0000000)
#define CKSSEG _CONST64_(0xffffffffc0000000)
#define CKSEG3 _CONST64_(0xffffffffe0000000)
+#else
+#define CKSEG0 XKPHYS_CM_CACHED
+#define CKSEG1 XKPHYS_CM_UNCACHED
+#endif /* !defined(CONFIG_USE_XKPHYS) */
#define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0)
#define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1)
@@ -126,8 +131,11 @@
#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p))
#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p))
#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK)
-#define PHYS_TO_XKPHYS(cm, a) (XKPHYS | (_ACAST64_(cm) << 59) | (a))
-
+#define XKPHYS_CM(cm) (XKPHYS | (_ACAST64_(cm) << 59))
+#define PHYS_TO_XKPHYS(cm, a) (XKPHYS_CM(cm) | (a))
+#define XKPHYS_CM_CACHED (XKPHYS_CM(K_CALG_COH_SHAREABLE))
+#define XKPHYS_CM_UNCACHED (XKPHYS_CM(K_CALG_UNCACHED))
+#define IS_XKPHYS(a) (((a) >> 62) == 2)
/*
* The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting
* the region, 3 bits for the CCA mode. This leaves 59 bits of which the
diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h
index 23c67c0871b1..15d8d69de455 100644
--- a/arch/mips/include/asm/mips-cm.h
+++ b/arch/mips/include/asm/mips-cm.h
@@ -311,6 +311,7 @@ GCR_CX_ACCESSOR_RW(32, 0x018, other)
/* GCR_Cx_RESET_BASE - Configure where powered up cores will fetch from */
GCR_CX_ACCESSOR_RW(32, 0x020, reset_base)
#define CM_GCR_Cx_RESET_BASE_BEVEXCBASE GENMASK(31, 12)
+#define CM_GCR_Cx_RESET_BASE_MODE BIT(1)
/* GCR_Cx_ID - Identify the current core */
GCR_CX_ACCESSOR_RO(32, 0x028, id)
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index 5978a8dfb917..53b8306da571 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -176,7 +176,11 @@ static inline unsigned long ___pa(unsigned long x)
* the compatibility segements ckseg0 or ckseg1, or it may
* be in xkphys.
*/
+#if defined(CONFIG_USE_XKPHYS)
+ return XPHYSADDR(x);
+#else
return x < CKSEG0 ? XPHYSADDR(x) : CPHYSADDR(x);
+#endif
}
if (!IS_ENABLED(CONFIG_EVA)) {
@@ -196,7 +200,11 @@ static inline unsigned long ___pa(unsigned long x)
return x - PAGE_OFFSET + PHYS_OFFSET;
}
#define __pa(x) ___pa((unsigned long)(x))
+#if IS_ENABLED(CONFIG_64BIT) && IS_ENABLED(CONFIG_USE_XKPHYS)
+#define __va(x) ((void *)PHYS_TO_XKSEG_CACHED(x))
+#else
#define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET))
+#endif
#include <asm/io.h>
/*
@@ -239,6 +247,8 @@ static inline unsigned long kaslr_offset(void)
return __kaslr_offset;
}
+#define UNCAC_ADDR(addr) (UNCAC_BASE + __pa(addr))
+
#include <asm-generic/memory_model.h>
#include <asm-generic/getorder.h>
diff --git a/arch/mips/include/asm/vga.h b/arch/mips/include/asm/vga.h
index 0136e0366698..e338e57d0784 100644
--- a/arch/mips/include/asm/vga.h
+++ b/arch/mips/include/asm/vga.h
@@ -16,7 +16,11 @@
* access the videoram directly without any black magic.
*/
+#if defined(CONFIG_USE_XKPHYS)
+#define VGA_MAP_MEM(x, s) UNCAC_ADDR(0x10000000L + (unsigned long)(x))
+#else
#define VGA_MAP_MEM(x, s) CKSEG1ADDR(0x10000000L + (unsigned long)(x))
+#endif
#define vga_readb(x) (*(x))
#define vga_writeb(x, y) (*(y) = (x))
diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
index 64ecfdac6580..541f31a43a7f 100644
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -554,7 +554,11 @@ LEAF(mips_cps_cache_init)
mul t1, t1, t0
mul t1, t1, t2
+#if defined(CONFIG_USE_XKPHYS)
+ PTR_LI a0, XKPHYS_CM_CACHED
+#else
li a0, CKSEG0
+#endif
PTR_ADD a1, a0, t1
1: cache Index_Store_Tag_I, 0(a0)
PTR_ADD a0, a0, t0
@@ -581,7 +585,11 @@ icache_done:
mul t1, t1, t0
mul t1, t1, t2
+#if defined(CONFIG_USE_XKPHYS)
+ PTR_LI a0, XKPHYS_CM_CACHED
+#else
li a0, CKSEG0
+#endif
PTR_ADDU a1, a0, t1
PTR_SUBU a1, a1, t0
1: cache Index_Store_Tag_D, 0(a0)
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index b6de8e88c1bd..a002058e1838 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -272,11 +272,25 @@ NESTED(except_vec_vi, 0, sp)
.set push
.set noreorder
PTR_LA v1, except_vec_vi_handler
+#if defined(CONFIG_USE_XKPHYS)
+FEXPORT(except_vec_vi_63_48)
+ lui v0, 0 /* Patched - bits 63:48 */
+FEXPORT(except_vec_vi_47_32)
+ ori v0, 0 /* Patched - bits 47:32 */
+ dsll v0, v0, 0x10
+FEXPORT(except_vec_vi_31_16)
+ ori v0, 0 /* Patched - bits 31:16 */
+ dsll v0, v0, 0x10
+ jr v1
+FEXPORT(except_vec_vi_15_0)
+ ori v0, 0 /* Patched - bits 15:0 */
+#else /* defined(CONFIG_USE_XKPHYS) */
FEXPORT(except_vec_vi_lui)
lui v0, 0 /* Patched */
jr v1
FEXPORT(except_vec_vi_ori)
ori v0, 0 /* Patched */
+#endif /* defined(CONFIG_USE_XKPHYS) */
.set pop
END(except_vec_vi)
EXPORT(except_vec_vi_end)
diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
index dd55d59b88db..47e76722a306 100644
--- a/arch/mips/kernel/smp-cps.c
+++ b/arch/mips/kernel/smp-cps.c
@@ -34,10 +34,33 @@ static unsigned __init core_vpe_count(unsigned int cluster, unsigned core)
return min(smp_max_threads, mips_cps_numvps(cluster, core));
}
+/**
+ * plat_core_entry - query reset vector for NMI/reset
+ *
+ * Returns low 32 bits of the reset vector
+ *
+ * This is used to fill 2 registers:
+ * - BEV Base (GCR_BEV_BASE) Offset: 0x0680
+ * - VP Local Reset Exception Base (GCR_CL_RESET_BASE,GCR_CO_RESET_BASE)
+ * Offset: 0x0020 (0x2020 relative to GCR_BASE_ADDR)
+ *
+ * In both registers, BIT(1) should be set in case it uses address in XKPHYS
+ * (as opposed to KSEG1). This bit defined as CM_GCR_Cx_RESET_BASE_MODE,
+ * using it unconditionally because for GCR_BEV_BASE its value is the same
+ */
+static u32 plat_core_entry(void)
+{
+#if defined(CONFIG_USE_XKPHYS)
+ return (UNCAC_ADDR(mips_cps_core_entry) & 0xffffffff)
+ | CM_GCR_Cx_RESET_BASE_MODE;
+#else
+ return CKSEG1ADDR((unsigned long)mips_cps_core_entry);
+#endif
+}
+
static void __init cps_smp_setup(void)
{
unsigned int nclusters, ncores, nvpes, core_vpes;
- unsigned long core_entry;
int cl, c, v;
/* Detect & record VPE topology */
@@ -94,10 +117,8 @@ static void __init cps_smp_setup(void)
/* Make core 0 coherent with everything */
write_gcr_cl_coherence(0xff);
- if (mips_cm_revision() >= CM_REV_CM3) {
- core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry);
- write_gcr_bev_base(core_entry);
- }
+ if (mips_cm_revision() >= CM_REV_CM3)
+ write_gcr_bev_base(plat_core_entry());
#ifdef CONFIG_MIPS_MT_FPAFF
/* If we have an FPU, enroll ourselves in the FPU-full mask */
@@ -213,7 +234,7 @@ static void boot_core(unsigned int core, unsigned int vpe_id)
mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
/* Set its reset vector */
- write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry));
+ write_gcr_co_reset_base(plat_core_entry());
/* Ensure its coherency is disabled */
write_gcr_co_coherence(0);
@@ -290,7 +311,6 @@ static int cps_boot_secondary(int cpu, struct task_struct *idle)
unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id];
- unsigned long core_entry;
unsigned int remote;
int err;
@@ -314,8 +334,7 @@ static int cps_boot_secondary(int cpu, struct task_struct *idle)
if (cpu_has_vp) {
mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
- core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry);
- write_gcr_co_reset_base(core_entry);
+ write_gcr_co_reset_base(plat_core_entry());
mips_cm_unlock_other();
}
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 246c6a6b0261..875594843626 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -2091,11 +2091,20 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
* If no shadow set is selected then use the default handler
* that does normal register saving and standard interrupt exit
*/
- extern const u8 except_vec_vi[], except_vec_vi_lui[];
- extern const u8 except_vec_vi_ori[], except_vec_vi_end[];
+ extern const u8 except_vec_vi[], except_vec_vi_end[];
extern const u8 rollback_except_vec_vi[];
const u8 *vec_start = using_rollback_handler() ?
rollback_except_vec_vi : except_vec_vi;
+ const int handler_len = except_vec_vi_end - vec_start;
+#if defined(CONFIG_USE_XKPHYS)
+ extern const u8 except_vec_vi_63_48[], except_vec_vi_47_32[];
+ extern const u8 except_vec_vi_31_16[], except_vec_vi_15_0[];
+ const int offset_63_48 = except_vec_vi_63_48 - vec_start;
+ const int offset_47_32 = except_vec_vi_47_32 - vec_start;
+ const int offset_31_16 = except_vec_vi_31_16 - vec_start;
+ const int offset_15_0 = except_vec_vi_15_0 - vec_start;
+#else /* defined(CONFIG_USE_XKPHYS) */
+ extern const u8 except_vec_vi_lui[], except_vec_vi_ori[];
#if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
const int lui_offset = except_vec_vi_lui - vec_start + 2;
const int ori_offset = except_vec_vi_ori - vec_start + 2;
@@ -2103,7 +2112,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
const int lui_offset = except_vec_vi_lui - vec_start;
const int ori_offset = except_vec_vi_ori - vec_start;
#endif
- const int handler_len = except_vec_vi_end - vec_start;
+#endif /* defined(CONFIG_USE_XKPHYS) */
if (handler_len > VECTORSPACING) {
/*
@@ -2119,10 +2128,21 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
#else
handler_len);
#endif
+#if defined(CONFIG_USE_XKPHYS)
+ h = (u16 *)(b + offset_63_48);
+ *h = (handler >> 48) & 0xffff;
+ h = (u16 *)(b + offset_47_32);
+ *h = (handler >> 32) & 0xffff;
+ h = (u16 *)(b + offset_31_16);
+ *h = (handler >> 16) & 0xffff;
+ h = (u16 *)(b + offset_15_0);
+ *h = (handler >> 0) & 0xffff;
+#else /* defined(CONFIG_USE_XKPHYS) */
h = (u16 *)(b + lui_offset);
*h = (handler >> 16) & 0xffff;
h = (u16 *)(b + ori_offset);
*h = (handler & 0xffff);
+#endif /* defined(CONFIG_USE_XKPHYS) */
local_flush_icache_range((unsigned long)b,
(unsigned long)(b+handler_len));
}
@@ -2332,7 +2352,11 @@ static const char panic_null_cerr[] =
void set_uncached_handler(unsigned long offset, void *addr,
unsigned long size)
{
+#if IS_ENABLED(CONFIG_64BIT) && IS_ENABLED(CONFIG_USE_XKPHYS)
+ unsigned long uncached_ebase = UNCAC_ADDR(ebase);
+#else
unsigned long uncached_ebase = CKSEG1ADDR(ebase);
+#endif
if (!addr)
panic(panic_null_cerr);
@@ -2384,9 +2408,11 @@ void __init trap_init(void)
* EVA is special though as it allows segments to be rearranged
* and to become uncached during cache error handling.
*/
+#if !defined(CONFIG_USE_XKPHYS)
if (!IS_ENABLED(CONFIG_EVA) && !WARN_ON(ebase_pa >= 0x20000000))
ebase = CKSEG0ADDR(ebase_pa);
else
+#endif
ebase = (unsigned long)phys_to_virt(ebase_pa);
}
diff --git a/arch/mips/lib/uncached.c b/arch/mips/lib/uncached.c
index f80a67c092b6..8a78348a2dd7 100644
--- a/arch/mips/lib/uncached.c
+++ b/arch/mips/lib/uncached.c
@@ -44,6 +44,10 @@ unsigned long run_uncached(void *func)
__asm__("move %0, $sp" : "=r" (sp));
+#if defined(CONFIG_USE_XKPHYS)
+ if (IS_XKPHYS(sp))
+ usp = UNCAC_ADDR(sp);
+#else /* defined(CONFIG_USE_XKPHYS) */
if (sp >= (long)CKSEG0 && sp < (long)CKSEG2)
usp = CKSEG1ADDR(sp);
#ifdef CONFIG_64BIT
@@ -52,10 +56,15 @@ unsigned long run_uncached(void *func)
usp = PHYS_TO_XKPHYS(K_CALG_UNCACHED,
XKPHYS_TO_PHYS((long long)sp));
#endif
+#endif /* defined(CONFIG_USE_XKPHYS) */
else {
BUG();
usp = sp;
}
+#if defined(CONFIG_USE_XKPHYS)
+ if (IS_XKPHYS(lfunc))
+ ufunc = UNCAC_ADDR(lfunc);
+#else /* defined(CONFIG_USE_XKPHYS) */
if (lfunc >= (long)CKSEG0 && lfunc < (long)CKSEG2)
ufunc = CKSEG1ADDR(lfunc);
#ifdef CONFIG_64BIT
@@ -64,6 +73,7 @@ unsigned long run_uncached(void *func)
ufunc = PHYS_TO_XKPHYS(K_CALG_UNCACHED,
XKPHYS_TO_PHYS((long long)lfunc));
#endif
+#endif /* defined(CONFIG_USE_XKPHYS) */
else {
BUG();
ufunc = lfunc;
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 5dcb525a8995..eb57283ec4e0 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -427,7 +427,7 @@ void __init paging_init(void)
free_area_init(max_zone_pfns);
}
-#ifdef CONFIG_64BIT
+#if defined(CONFIG_64BIT) && !defined(CONFIG_USE_XKPHYS)
static struct kcore_list kcore_kseg0;
#endif
@@ -470,7 +470,7 @@ void __init mem_init(void)
setup_zero_pages(); /* Setup zeroed pages. */
mem_init_free_highmem();
-#ifdef CONFIG_64BIT
+#if defined(CONFIG_64BIT) && !defined(CONFIG_USE_XKPHYS)
if ((unsigned long) &_text > (unsigned long) CKSEG0)
/* The -4 is a hack so that user tools don't have to handle
the overflow. */
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH 03/11] MIPS: support RAM beyond 32-bit
2023-10-04 16:10 [PATCH 00/11] Add support for the Mobileye EyeQ5 SoC Gregory CLEMENT
2023-10-04 16:10 ` [PATCH 01/11] MIPS: compressed: Use correct instruction for 64 bit code Gregory CLEMENT
2023-10-04 16:10 ` [PATCH 02/11] MIPS: use virtual addresses from xkphys for MIPS64 Gregory CLEMENT
@ 2023-10-04 16:10 ` Gregory CLEMENT
2023-10-06 11:21 ` Arnd Bergmann
2023-10-07 20:14 ` Jiaxun Yang
2023-10-04 16:10 ` [PATCH 04/11] dt-bindings: Add vendor prefix for Mobileye Vision Technologies Ltd Gregory CLEMENT
` (7 subsequent siblings)
10 siblings, 2 replies; 53+ messages in thread
From: Gregory CLEMENT @ 2023-10-04 16:10 UTC (permalink / raw)
To: Paul Burton, Thomas Bogendoerfer, linux-mips, Rob Herring,
Krzysztof Kozlowski, devicetree, linux-kernel
Cc: Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni, Gregory CLEMENT
From: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
Support platforms where RAM is mapped beyond 32-bit.
The kernel parameter ddr32_alias allows to setup the alias to point
outside the first 4 GB of memory.
Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
arch/mips/kernel/smp-cps.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
index 47e76722a306..fcfb19487612 100644
--- a/arch/mips/kernel/smp-cps.c
+++ b/arch/mips/kernel/smp-cps.c
@@ -34,6 +34,16 @@ static unsigned __init core_vpe_count(unsigned int cluster, unsigned core)
return min(smp_max_threads, mips_cps_numvps(cluster, core));
}
+static int ddr32_alias;
+
+static int __init ddr32_alias_setup(char *str)
+{
+ get_option(&str, &ddr32_alias);
+
+ return 0;
+}
+early_param("ddr32_alias", ddr32_alias_setup);
+
/**
* plat_core_entry - query reset vector for NMI/reset
*
@@ -52,7 +62,7 @@ static u32 plat_core_entry(void)
{
#if defined(CONFIG_USE_XKPHYS)
return (UNCAC_ADDR(mips_cps_core_entry) & 0xffffffff)
- | CM_GCR_Cx_RESET_BASE_MODE;
+ | ddr32_alias | CM_GCR_Cx_RESET_BASE_MODE;
#else
return CKSEG1ADDR((unsigned long)mips_cps_core_entry);
#endif
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH 04/11] dt-bindings: Add vendor prefix for Mobileye Vision Technologies Ltd.
2023-10-04 16:10 [PATCH 00/11] Add support for the Mobileye EyeQ5 SoC Gregory CLEMENT
` (2 preceding siblings ...)
2023-10-04 16:10 ` [PATCH 03/11] MIPS: support RAM beyond 32-bit Gregory CLEMENT
@ 2023-10-04 16:10 ` Gregory CLEMENT
2023-10-05 6:34 ` Philippe Mathieu-Daudé
2023-10-06 16:32 ` Rob Herring
2023-10-04 16:10 ` [PATCH 05/11] dt-bindings: mips: cpu: Add I-Class I6500 Multiprocessor Core Gregory CLEMENT
` (6 subsequent siblings)
10 siblings, 2 replies; 53+ messages in thread
From: Gregory CLEMENT @ 2023-10-04 16:10 UTC (permalink / raw)
To: Paul Burton, Thomas Bogendoerfer, linux-mips, Rob Herring,
Krzysztof Kozlowski, devicetree, linux-kernel
Cc: Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni, Gregory CLEMENT
Mobileye Vision Technologies Ltd. is a company developing autonomous
driving technologies and advanced driver-assistance systems (ADAS)
including cameras, computer chips and software.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 573578db9509..510c6c03f6d5 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -877,6 +877,8 @@ patternProperties:
description: Miyoo
"^mntre,.*":
description: MNT Research GmbH
+ "^mobileye,.*":
+ description: Mobileye Vision Technologies Ltd.
"^modtronix,.*":
description: Modtronix Engineering
"^moortec,.*":
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH 05/11] dt-bindings: mips: cpu: Add I-Class I6500 Multiprocessor Core
2023-10-04 16:10 [PATCH 00/11] Add support for the Mobileye EyeQ5 SoC Gregory CLEMENT
` (3 preceding siblings ...)
2023-10-04 16:10 ` [PATCH 04/11] dt-bindings: Add vendor prefix for Mobileye Vision Technologies Ltd Gregory CLEMENT
@ 2023-10-04 16:10 ` Gregory CLEMENT
2023-10-05 6:31 ` Philippe Mathieu-Daudé
` (2 more replies)
2023-10-04 16:10 ` [PATCH 06/11] dt-bindings: mips: Add bindings for Mobileye SoCs Gregory CLEMENT
` (5 subsequent siblings)
10 siblings, 3 replies; 53+ messages in thread
From: Gregory CLEMENT @ 2023-10-04 16:10 UTC (permalink / raw)
To: Paul Burton, Thomas Bogendoerfer, linux-mips, Rob Herring,
Krzysztof Kozlowski, devicetree, linux-kernel
Cc: Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni, Gregory CLEMENT
The MIPS Warrior I-class I6500 was announced by Imagination
Technologies in 2016 and is used in the Mobileye SoC EyeQ5.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
Documentation/devicetree/bindings/mips/cpus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mips/cpus.yaml b/Documentation/devicetree/bindings/mips/cpus.yaml
index cf382dea3922..87fd2842ba68 100644
--- a/Documentation/devicetree/bindings/mips/cpus.yaml
+++ b/Documentation/devicetree/bindings/mips/cpus.yaml
@@ -39,6 +39,7 @@ properties:
- mti,mips24KEc
- mti,mips14KEc
- mti,mips14Kc
+ - mti,i6500
reg:
maxItems: 1
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH 06/11] dt-bindings: mips: Add bindings for Mobileye SoCs
2023-10-04 16:10 [PATCH 00/11] Add support for the Mobileye EyeQ5 SoC Gregory CLEMENT
` (4 preceding siblings ...)
2023-10-04 16:10 ` [PATCH 05/11] dt-bindings: mips: cpu: Add I-Class I6500 Multiprocessor Core Gregory CLEMENT
@ 2023-10-04 16:10 ` Gregory CLEMENT
2023-10-04 16:47 ` Rob Herring
2023-10-04 16:10 ` [PATCH 07/11] dt-bindings: mfd: syscon: Document EyeQ5 OLB Gregory CLEMENT
` (4 subsequent siblings)
10 siblings, 1 reply; 53+ messages in thread
From: Gregory CLEMENT @ 2023-10-04 16:10 UTC (permalink / raw)
To: Paul Burton, Thomas Bogendoerfer, linux-mips, Rob Herring,
Krzysztof Kozlowski, devicetree, linux-kernel
Cc: Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni, Gregory CLEMENT
Add the yaml bindings for Mobileye SoCs. Currently only EyeQ5 is
supported
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
.../devicetree/bindings/mips/mobileye.yaml | 36 +++++++++
include/dt-bindings/soc/mobileye,eyeq5.h | 77 +++++++++++++++++++
2 files changed, 113 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mips/mobileye.yaml
create mode 100644 include/dt-bindings/soc/mobileye,eyeq5.h
diff --git a/Documentation/devicetree/bindings/mips/mobileye.yaml b/Documentation/devicetree/bindings/mips/mobileye.yaml
new file mode 100644
index 000000000000..f47767bc2c8f
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/mobileye.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
+# Copyright 2023 Mobileye Vision Technologies Ltd.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mips/mobileye.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mobileye SoC series
+
+maintainers:
+ - Vladimir Kondratiev <vladimir.kondratiev@intel.com>
+ - Gregory CLEMENT <gregory.clement@bootlin.com>
+ - Théo Lebrun <theo.lebrun@bootlin.com>
+
+description: |
+ Boards with a Mobileye SoC shall have the following properties.
+
+properties:
+ $nodename:
+ const: '/'
+
+ compatible:
+ oneOf:
+ - description: Boards with Mobileye EyeQ5 SoC
+ items:
+ - enum:
+ - mobileye,eyeq5-epm5
+ - const: mobileye,eyeq5
+
+ - description: Boards with Mobileye EyeQ6 SoC
+ items:
+ - const: mobileye,eyeq6
+
+additionalProperties: true
+
+...
diff --git a/include/dt-bindings/soc/mobileye,eyeq5.h b/include/dt-bindings/soc/mobileye,eyeq5.h
new file mode 100644
index 000000000000..7d8cb97b45bf
--- /dev/null
+++ b/include/dt-bindings/soc/mobileye,eyeq5.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2023 Mobileye Vision Technologies Ltd.
+ */
+#ifndef _DT_BINDINGS_SOC_MOBILEYE_EYEQ5_H
+#define _DT_BINDINGS_SOC_MOBILEYE_EYEQ5_H
+
+/* EQ5 interrupts */
+#define NUM_INT_I2C_A 1
+#define NUM_INT_I2C_B 2
+#define NUM_INT_I2C_C 3
+#define NUM_INT_I2C_D 4
+#define NUM_INT_I2C_E 5
+
+#define NUM_INT_UART 6 /* same for all UARTs - A, B, C */
+#define NUM_INT_PCIE0_INT0 7
+#define NUM_INT_PCIE0_INT1 8
+
+#define NUM_INT_CAN 9 /* same for all CANs A, B, C */
+
+#define NUM_INT_EMMC 10
+/* empty 11 */
+#define NUM_INT_SPIA_B 12
+#define NUM_INT_SPIC_D 13
+
+#define NUM_INT_GPIO 14
+
+#define NUM_INT_TIMER_0 15
+#define NUM_INT_TIMER_1 16
+#define NUM_INT_TIMER_2 17
+#define NUM_INT_TIMER_3 18
+#define NUM_INT_TIMER_4_ETIMER0_1 19
+#define NUM_INT_OQSPI 20
+#define NUM_INT_DDR_CTRL 21
+#define NUM_INT_NOC 22
+
+#define NUM_INT_GEM0 23
+#define NUM_INT_GEM1 24
+
+#define NUM_INT_VDI_0_VC0 25
+#define NUM_INT_VDI_0_VC1 26
+#define NUM_INT_VDI_0_VC2 27
+#define NUM_INT_VDI_0_VC3 28
+#define NUM_INT_VDI_0_ERR 29
+#define NUM_INT_VDI_1_VC0 30
+#define NUM_INT_VDI_1_VC1 31
+#define NUM_INT_VDI_1_VC2 32
+#define NUM_INT_VDI_1_VC3 33
+#define NUM_INT_VDI_1_ERR 34
+
+#define NUM_INT_MPC0 35
+#define NUM_INT_MPC1 36
+#define NUM_INT_MPC2 37
+#define NUM_INT_MPC3 38
+#define NUM_INT_MPC4 39
+#define NUM_INT_VMP0 40
+#define NUM_INT_VMP1 41
+#define NUM_INT_VMP2 42
+#define NUM_INT_VMP3 43
+#define NUM_INT_PMA0 44
+#define NUM_INT_PMA1 45
+#define NUM_INT_PMAC0 46
+#define NUM_INT_PMAC1 47
+
+#define NUM_INT_PCIE1_INT0 48
+#define NUM_INT_PCIE1_INT1 49
+
+#define NUM_INT_HSM_C3 50
+
+#define NUM_INT_MJPEG 51
+
+#define NUM_INT_FCMU_OLB 52
+#define NUM_INT_FCMU_NMI 53
+#define NUM_INT_WDDOG_TIMER 54
+#define NUM_INT_WDDOG_TIMER_1 55
+
+#endif /* _DT_BINDINGS_SOC_MOBILEYE_EYEQ5_H */
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH 07/11] dt-bindings: mfd: syscon: Document EyeQ5 OLB
2023-10-04 16:10 [PATCH 00/11] Add support for the Mobileye EyeQ5 SoC Gregory CLEMENT
` (5 preceding siblings ...)
2023-10-04 16:10 ` [PATCH 06/11] dt-bindings: mips: Add bindings for Mobileye SoCs Gregory CLEMENT
@ 2023-10-04 16:10 ` Gregory CLEMENT
2023-10-06 16:54 ` Rob Herring
2023-10-04 16:10 ` [PATCH 08/11] MIPS: mobileye: Add EyeQ5 dtsi Gregory CLEMENT
` (3 subsequent siblings)
10 siblings, 1 reply; 53+ messages in thread
From: Gregory CLEMENT @ 2023-10-04 16:10 UTC (permalink / raw)
To: Paul Burton, Thomas Bogendoerfer, linux-mips, Rob Herring,
Krzysztof Kozlowski, devicetree, linux-kernel
Cc: Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni, Gregory CLEMENT
Document Mobileye EyeQ5 compatibles for OLB registers that are
misceallanous SoC related registers.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
index 8103154bbb52..70bc6e8d15ba 100644
--- a/Documentation/devicetree/bindings/mfd/syscon.yaml
+++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
@@ -53,6 +53,7 @@ properties:
- mediatek,mt8135-pctl-a-syscfg
- mediatek,mt8135-pctl-b-syscfg
- mediatek,mt8365-syscfg
+ - mobileye,eyeq5-olb
- microchip,lan966x-cpu-syscon
- microchip,sparx5-cpu-syscon
- mstar,msc313-pmsleep
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH 08/11] MIPS: mobileye: Add EyeQ5 dtsi
2023-10-04 16:10 [PATCH 00/11] Add support for the Mobileye EyeQ5 SoC Gregory CLEMENT
` (6 preceding siblings ...)
2023-10-04 16:10 ` [PATCH 07/11] dt-bindings: mfd: syscon: Document EyeQ5 OLB Gregory CLEMENT
@ 2023-10-04 16:10 ` Gregory CLEMENT
2023-10-04 16:41 ` Rob Herring
2023-10-04 16:10 ` [PATCH 09/11] MIPS: mobileye: Add EPM5 device tree Gregory CLEMENT
` (2 subsequent siblings)
10 siblings, 1 reply; 53+ messages in thread
From: Gregory CLEMENT @ 2023-10-04 16:10 UTC (permalink / raw)
To: Paul Burton, Thomas Bogendoerfer, linux-mips, Rob Herring,
Krzysztof Kozlowski, devicetree, linux-kernel
Cc: Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni, Gregory CLEMENT
Add a device tree include file for the Mobileye EyeQ5 SoC.
Based on the work of Slava Samsonov <stanislav.samsonov@intel.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
arch/mips/boot/dts/Makefile | 1 +
arch/mips/boot/dts/mobileye/Makefile | 4 +
.../boot/dts/mobileye/eyeq5-fixed-clocks.dtsi | 315 ++++++++++++++++++
arch/mips/boot/dts/mobileye/eyeq5.dtsi | 138 ++++++++
4 files changed, 458 insertions(+)
create mode 100644 arch/mips/boot/dts/mobileye/Makefile
create mode 100644 arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi
create mode 100644 arch/mips/boot/dts/mobileye/eyeq5.dtsi
diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
index 928f38a79dff..edb8e8dee758 100644
--- a/arch/mips/boot/dts/Makefile
+++ b/arch/mips/boot/dts/Makefile
@@ -8,6 +8,7 @@ subdir-$(CONFIG_LANTIQ) += lantiq
subdir-$(CONFIG_MACH_LOONGSON64) += loongson
subdir-$(CONFIG_SOC_VCOREIII) += mscc
subdir-$(CONFIG_MIPS_MALTA) += mti
+subdir-$(CONFIG_SOC_EYEQ5) += mobileye
subdir-$(CONFIG_LEGACY_BOARD_SEAD3) += mti
subdir-$(CONFIG_FIT_IMAGE_FDT_NI169445) += ni
subdir-$(CONFIG_MACH_PIC32) += pic32
diff --git a/arch/mips/boot/dts/mobileye/Makefile b/arch/mips/boot/dts/mobileye/Makefile
new file mode 100644
index 000000000000..99c4124fd4c0
--- /dev/null
+++ b/arch/mips/boot/dts/mobileye/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+# Copyright 2023 Mobileye Vision Technologies Ltd.
+
+obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
diff --git a/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi b/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi
new file mode 100644
index 000000000000..a0066465ac8b
--- /dev/null
+++ b/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi
@@ -0,0 +1,315 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright 2023 Mobileye Vision Technologies Ltd.
+ */
+
+/ {
+ /* Fixed clock */
+ pll_cpu: pll_cpu {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1500000000>;
+ };
+
+ pll_vdi: pll_vdi {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1280000000>;
+ };
+
+ pll_per: pll_per {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2000000000>;
+ };
+
+ pll_ddr0: pll_ddr0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1857210000>;
+ };
+
+ pll_ddr1: pll_ddr1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1857210000>;
+ };
+
+/* PLL_CPU derivatives */
+ occ_cpu: occ_cpu {
+ compatible = "fixed-factor-clock";
+ clocks = <&pll_cpu>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clock-output-names = "occ_cpu";
+ };
+ si_css0_ref_clk: si_css0_ref_clk { /* gate ClkRstGen_si_css0_ref */
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_cpu>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clock-output-names = "si_css0_ref_clk";
+ };
+ cpc_clk: cpc_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&si_css0_ref_clk>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clock-output-names = "cpc_clk";
+ };
+ core0_clk: core0_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&si_css0_ref_clk>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clock-output-names = "core0_clk";
+ };
+ core1_clk: core1_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&si_css0_ref_clk>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clock-output-names = "core1_clk";
+ };
+ core2_clk: core2_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&si_css0_ref_clk>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clock-output-names = "core2_clk";
+ };
+ core3_clk: core3_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&si_css0_ref_clk>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clock-output-names = "core3_clk";
+ };
+ cm_clk: cm_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&si_css0_ref_clk>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clock-output-names = "cm_clk";
+ };
+ mem_clk: mem_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&si_css0_ref_clk>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clock-output-names = "mem_clk";
+ };
+ occ_isram: occ_isram {
+ compatible = "fixed-factor-clock";
+ clocks = <&pll_cpu>;
+ #clock-cells = <0>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ clock-output-names = "occ_isram";
+ };
+ isram_clk: isram_clk { /* gate ClkRstGen_isram */
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_isram>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clock-output-names = "isram_clk";
+ };
+ occ_dbu: occ_dbu {
+ compatible = "fixed-factor-clock";
+ clocks = <&pll_cpu>;
+ #clock-cells = <0>;
+ clock-div = <10>;
+ clock-mult = <1>;
+ clock-output-names = "occ_dbu";
+ };
+ si_dbu_tp_pclk: si_dbu_tp_pclk { /* gate ClkRstGen_dbu */
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_dbu>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clock-output-names = "si_dbu_tp_pclk";
+ };
+/* PLL_VDI derivatives */
+ occ_vdi: occ_vdi {
+ compatible = "fixed-factor-clock";
+ clocks = <&pll_vdi>;
+ #clock-cells = <0>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ clock-output-names = "occ_vdi";
+ };
+ vdi_clk: vdi_clk { /* gate ClkRstGen_vdi */
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_vdi>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clock-output-names = "vdi_clk";
+ };
+ occ_can_ser: occ_can_ser {
+ compatible = "fixed-factor-clock";
+ clocks = <&pll_vdi>;
+ #clock-cells = <0>;
+ clock-div = <16>;
+ clock-mult = <1>;
+ clock-output-names = "occ_can_ser";
+ };
+ can_ser_clk: can_ser_clk { /* gate ClkRstGen_can_ser */
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_can_ser>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clock-output-names = "can_ser_clk";
+ };
+ i2c_ser_clk: i2c_ser_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&pll_vdi>;
+ #clock-cells = <0>;
+ clock-div = <20>;
+ clock-mult = <1>;
+ clock-output-names = "i2c_ser_clk";
+ };
+/* PLL_PER derivatives */
+ occ_periph: occ_periph {
+ compatible = "fixed-factor-clock";
+ clocks = <&pll_per>;
+ #clock-cells = <0>;
+ clock-div = <16>;
+ clock-mult = <1>;
+ clock-output-names = "occ_periph";
+ };
+ periph_clk: periph_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_periph>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clock-output-names = "periph_clk";
+ };
+ can_clk: can_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_periph>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clock-output-names = "can_clk";
+ };
+ spi_clk: spi_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_periph>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clock-output-names = "spi_clk";
+ };
+ uart_clk: uart_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_periph>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clock-output-names = "uart_clk";
+ };
+ i2c_clk: i2c_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_periph>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clock-output-names = "i2c_clk";
+ };
+ timer_clk: timer_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_periph>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clock-output-names = "timer_clk";
+ };
+ gpio_clk: gpio_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_periph>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clock-output-names = "gpio_clk";
+ };
+ emmc_sys_clk: emmc_sys_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&pll_per>;
+ #clock-cells = <0>;
+ clock-div = <10>;
+ clock-mult = <1>;
+ clock-output-names = "emmc_sys_clk";
+ };
+ ccf_ctrl_clk: ccf_ctrl_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&pll_per>;
+ #clock-cells = <0>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ clock-output-names = "ccf_ctrl_clk";
+ };
+ occ_mjpeg_core: occ_mjpeg_core {
+ compatible = "fixed-factor-clock";
+ clocks = <&pll_per>;
+ #clock-cells = <0>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ clock-output-names = "occ_mjpeg_core";
+ };
+ hsm_clk: hsm_clk { /* gate ClkRstGen_hsm */
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_mjpeg_core>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clock-output-names = "hsm_clk";
+ };
+ mjpeg_core_clk: mjpeg_core_clk { /* gate ClkRstGen_mjpeg_gen */
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_mjpeg_core>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clock-output-names = "mjpeg_core_clk";
+ };
+ fcmu_a_clk: fcmu_a_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&pll_per>;
+ #clock-cells = <0>;
+ clock-div = <20>;
+ clock-mult = <1>;
+ clock-output-names = "fcmu_a_clk";
+ };
+ occ_pci_sys: occ_pci_sys {
+ compatible = "fixed-factor-clock";
+ clocks = <&pll_per>;
+ #clock-cells = <0>;
+ clock-div = <8>;
+ clock-mult = <1>;
+ clock-output-names = "occ_pci_sys";
+ };
+ pclk: pclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <250000000>; /* 250MHz */
+ };
+ tsu_clk: tsu_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>; /* 125MHz */
+ };
+};
diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi
new file mode 100644
index 000000000000..0504c2fb3ad5
--- /dev/null
+++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi
@@ -0,0 +1,138 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2023 Mobileye Vision Technologies Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/mips-gic.h>
+#include <dt-bindings/soc/mobileye,eyeq5.h>
+
+/memreserve/ 0x40000000 0xc0000000; /* DDR32 */
+/memreserve/ 0x08000000 0x08000000; /* DDR_LOW */
+
+#include "eyeq5-fixed-clocks.dtsi"
+
+/* almost all GIC IRQs has the same characteristics. provide short form */
+#define GIC_IRQ(x) GIC_SHARED (x) IRQ_TYPE_LEVEL_HIGH
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "mti,i6500";
+ reg = <0>;
+ clocks = <&core0_clk>;
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+/* These reserved memory regions are also defined in bootmanager
+ * for configuring inbound translation for BARS, don't change
+ * these without syncing with bootmanager
+ */
+ shmem0_reserved: shmem@804000000 {
+ reg = <0x8 0x04000000 0x0 0x1000000>;
+ };
+ shmem1_reserved: shmem@805000000 {
+ reg = <0x8 0x05000000 0x0 0x1000000>;
+ };
+ pci0_msi_reserved: pci0_msi@806000000 {
+ reg = <0x8 0x06000000 0x0 0x100000>;
+ };
+ pci1_msi_reserved: pci1_msi@806100000 {
+ reg = <0x8 0x06100000 0x0 0x100000>;
+ };
+
+ mini_coredump0_reserved: mini_coredump0@806200000 {
+ reg = <0x8 0x06200000 0x0 0x100000>;
+ };
+ mhm_reserved_0: the_mhm_reserved_0@0 {
+ reg = <0x8 0x00000000 0x0 0x0000800>;
+ };
+ };
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ };
+
+ cpu_intc: interrupt-controller {
+ compatible = "mti,cpu-interrupt-controller";
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+
+ gic: interrupt-controller@140000 {
+ compatible = "mti,gic";
+ reg = <0x0 0x140000 0x0 0x20000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ /*
+ * Declare the interrupt-parent even though the mti,gic
+ * binding doesn't require it, such that the kernel can
+ * figure out that cpu_intc is the root interrupt
+ * controller & should be probed first.
+ */
+ interrupt-parent = <&cpu_intc>;
+
+ timer {
+ compatible = "mti,gic-timer";
+ interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
+ clocks = <&core0_clk>;
+ };
+ };
+
+ soc: soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ compatible = "simple-bus";
+
+ uart0: serial@800000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0 0x800000 0x0 0x1000>;
+ reg-io-width = <4>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_IRQ(NUM_INT_UART)>;
+ clocks = <&uart_clk>, <&occ_periph>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+
+ uart1: serial@900000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0 0x900000 0x0 0x1000>;
+ reg-io-width = <4>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_IRQ(NUM_INT_UART)>;
+ clocks = <&uart_clk>, <&occ_periph>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+
+ uart2: serial@a00000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0 0xa00000 0x0 0x1000>;
+ reg-io-width = <4>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_IRQ(NUM_INT_UART)>;
+ clocks = <&uart_clk>, <&occ_periph>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+
+ olb: olb@e00000 {
+ compatible = "mobileye,eyeq5-olb", "syscon", "simple-mfd";
+ reg = <0 0xe00000 0x0 0x400>;
+ reg-io-width = <4>;
+ };
+
+ };
+};
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH 09/11] MIPS: mobileye: Add EPM5 device tree
2023-10-04 16:10 [PATCH 00/11] Add support for the Mobileye EyeQ5 SoC Gregory CLEMENT
` (7 preceding siblings ...)
2023-10-04 16:10 ` [PATCH 08/11] MIPS: mobileye: Add EyeQ5 dtsi Gregory CLEMENT
@ 2023-10-04 16:10 ` Gregory CLEMENT
2023-10-06 11:18 ` Arnd Bergmann
2023-10-04 16:10 ` [PATCH 10/11] MIPS: generic: Add support for Mobileye EyeQ5 Gregory CLEMENT
2023-10-04 16:10 ` [PATCH 11/11] MAINTAINERS: Add entry for Mobileye MIPS SoCs Gregory CLEMENT
10 siblings, 1 reply; 53+ messages in thread
From: Gregory CLEMENT @ 2023-10-04 16:10 UTC (permalink / raw)
To: Paul Burton, Thomas Bogendoerfer, linux-mips, Rob Herring,
Krzysztof Kozlowski, devicetree, linux-kernel
Cc: Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni, Gregory CLEMENT
Add a device tree for the Mobileye EPM5 evaluation board.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
arch/mips/boot/dts/mobileye/Makefile | 2 ++
arch/mips/boot/dts/mobileye/eyeq5-epm5.dts | 24 ++++++++++++++++++++++
2 files changed, 26 insertions(+)
create mode 100644 arch/mips/boot/dts/mobileye/eyeq5-epm5.dts
diff --git a/arch/mips/boot/dts/mobileye/Makefile b/arch/mips/boot/dts/mobileye/Makefile
index 99c4124fd4c0..539b2e1f4e07 100644
--- a/arch/mips/boot/dts/mobileye/Makefile
+++ b/arch/mips/boot/dts/mobileye/Makefile
@@ -1,4 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
# Copyright 2023 Mobileye Vision Technologies Ltd.
+dtb-$(CONFIG_SOC_EYEQ5) += eyeq5-epm5.dtb
+
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
diff --git a/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts b/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts
new file mode 100644
index 000000000000..ca03115a2858
--- /dev/null
+++ b/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright 2023 Mobileye Vision Technologies Ltd.
+ */
+
+/dts-v1/;
+
+#include "eyeq5.dtsi"
+
+/ {
+ compatible = "mobileye,eyeq5-epm5", "mobileye,eyeq5";
+ model = "Mobile EyeQ5 MP5 Evaluation board";
+
+ chosen {
+ bootargs = "cca=5 earlycon console=ttyAMA2 ddr32_alias=0x40000000";
+ stdout-path = "serial2:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x8 0x00000000 0x0 0x80000000>;
+ };
+};
+
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH 10/11] MIPS: generic: Add support for Mobileye EyeQ5
2023-10-04 16:10 [PATCH 00/11] Add support for the Mobileye EyeQ5 SoC Gregory CLEMENT
` (8 preceding siblings ...)
2023-10-04 16:10 ` [PATCH 09/11] MIPS: mobileye: Add EPM5 device tree Gregory CLEMENT
@ 2023-10-04 16:10 ` Gregory CLEMENT
2023-10-05 0:08 ` kernel test robot
2023-10-04 16:10 ` [PATCH 11/11] MAINTAINERS: Add entry for Mobileye MIPS SoCs Gregory CLEMENT
10 siblings, 1 reply; 53+ messages in thread
From: Gregory CLEMENT @ 2023-10-04 16:10 UTC (permalink / raw)
To: Paul Burton, Thomas Bogendoerfer, linux-mips, Rob Herring,
Krzysztof Kozlowski, devicetree, linux-kernel
Cc: Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni, Gregory CLEMENT
Introduce support for the MIPS based Mobileye EyeQ5 SoCs.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
arch/mips/configs/generic/board-eyeq5.config | 42 ++++++++++++++++++++
arch/mips/generic/Kconfig | 14 +++++++
arch/mips/generic/Platform | 2 +
arch/mips/generic/board-epm5.its.S | 24 +++++++++++
4 files changed, 82 insertions(+)
create mode 100644 arch/mips/configs/generic/board-eyeq5.config
create mode 100644 arch/mips/generic/board-epm5.its.S
diff --git a/arch/mips/configs/generic/board-eyeq5.config b/arch/mips/configs/generic/board-eyeq5.config
new file mode 100644
index 000000000000..946428318e15
--- /dev/null
+++ b/arch/mips/configs/generic/board-eyeq5.config
@@ -0,0 +1,42 @@
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_TASKSTATS=y
+CONFIG_FIT_IMAGE_FDT_EPM5=y
+CONFIG_BOARD_EYEQ5=y
+CONFIG_USE_XKPHYS=y
+CONFIG_ZBOOT_LOAD_ADDRESS=0xA800000080480000
+CONFIG_CPU_HAS_MSA=y
+CONFIG_NET_KEY=y
+CONFIG_CAN=y
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_DEBUG=y
+CONFIG_PCI_ENDPOINT=y
+CONFIG_CONNECTOR=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_RAM=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_BLOCK2MTD=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_NETDEVICES=y
+CONFIG_MACVLAN=y
+CONFIG_IPVLAN=y
+CONFIG_MACB=y
+CONFIG_MARVELL_PHY=y
+CONFIG_MICREL_PHY=y
+CONFIG_CAN_M_CAN=y
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_PINCTRL=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_CADENCE=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_FANOTIFY=y
+CONFIG_ROMFS_FS=y
+CONFIG_ROMFS_BACKED_BY_BOTH=y
+CONFIG_PAGE_SIZE_16KB=y
\ No newline at end of file
diff --git a/arch/mips/generic/Kconfig b/arch/mips/generic/Kconfig
index 7dc5b3821cc6..9eb876a819c0 100644
--- a/arch/mips/generic/Kconfig
+++ b/arch/mips/generic/Kconfig
@@ -48,6 +48,12 @@ config SOC_VCOREIII
config MSCC_OCELOT
bool
+config SOC_EYEQ5
+ select WEAK_ORDERING
+ select WEAK_REORDERING_BEYOND_LLSC
+ select ARM_AMBA
+ bool
+
comment "FIT/UHI Boards"
config FIT_IMAGE_FDT_BOSTON
@@ -124,4 +130,12 @@ config VIRT_BOARD_RANCHU
Android emulator. Android emulator is based on Qemu, and contains
the support for the same set of virtual devices.
+config FIT_IMAGE_FDT_EPM5
+ bool "Include FDT for Mobileye EyeQ5 development platforms"
+ select SOC_EYEQ5
+ default n
+ help
+ Enable this to include the FDT for the EyeQ5 development platforms
+ from Mobileye in the FIT kernel image.
+ This requires u-boot on the platform.
endif
diff --git a/arch/mips/generic/Platform b/arch/mips/generic/Platform
index 2be9947814ad..447c42e1f676 100644
--- a/arch/mips/generic/Platform
+++ b/arch/mips/generic/Platform
@@ -29,3 +29,5 @@ its-$(CONFIG_FIT_IMAGE_FDT_JAGUAR2) += board-jaguar2.its.S
its-$(CONFIG_FIT_IMAGE_FDT_SERVAL) += board-serval.its.S
its-$(CONFIG_FIT_IMAGE_FDT_XILFPGA) += board-xilfpga.its.S
its-$(CONFIG_FIT_IMAGE_FDT_MARDUK) += board-marduk.its.S
+its-$(CONFIG_FIT_IMAGE_FDT_EPM5) += board-epm5.its.S
+
diff --git a/arch/mips/generic/board-epm5.its.S b/arch/mips/generic/board-epm5.its.S
new file mode 100644
index 000000000000..08e8c4f183d6
--- /dev/null
+++ b/arch/mips/generic/board-epm5.its.S
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/ {
+ images {
+ fdt-mobileye-epm5 {
+ description = "Mobileeye MP5 Device Tree";
+ data = /incbin/("boot/dts/mobileye/eyeq5-epm5.dtb");
+ type = "flat_dt";
+ arch = "mips";
+ compression = "none";
+ hash {
+ algo = "sha1";
+ };
+ };
+ };
+
+ configurations {
+ default = "conf-1";
+ conf-1 {
+ description = "Mobileye EPM5 Linux kernel";
+ kernel = "kernel";
+ fdt = "fdt-mobileye-epm5";
+ };
+ };
+};
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH 11/11] MAINTAINERS: Add entry for Mobileye MIPS SoCs
2023-10-04 16:10 [PATCH 00/11] Add support for the Mobileye EyeQ5 SoC Gregory CLEMENT
` (9 preceding siblings ...)
2023-10-04 16:10 ` [PATCH 10/11] MIPS: generic: Add support for Mobileye EyeQ5 Gregory CLEMENT
@ 2023-10-04 16:10 ` Gregory CLEMENT
2023-10-06 11:11 ` Arnd Bergmann
10 siblings, 1 reply; 53+ messages in thread
From: Gregory CLEMENT @ 2023-10-04 16:10 UTC (permalink / raw)
To: Paul Burton, Thomas Bogendoerfer, linux-mips, Rob Herring,
Krzysztof Kozlowski, devicetree, linux-kernel
Cc: Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni, Gregory CLEMENT
Add Vlad, Théo and myself as co-maintainers for the Mobileye MIPS
SoCs.
Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
MAINTAINERS | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 90f13281d297..6aedeab5f07c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14423,6 +14423,18 @@ W: http://palosaari.fi/linux/
Q: http://patchwork.linuxtv.org/project/linux-media/list/
F: drivers/media/dvb-frontends/mn88473*
+MOBILEYE MIPS SOCS
+M: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
+M: Gregory CLEMENT <gregory.clement@bootlin.com>
+M: Théo Lebrun <theo.lebrun@bootlin.com>
+L: linux-mips@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/mips/mobileye.yaml
+F: arch/mips/boot/dts/mobileye/
+F: arch/mips/configs/generic/board-eyeq5.config
+F: arch/mips/generic/board-epm5.its.S
+F: include/dt-bindings/soc/mobileye,eyeq5.h
+
MODULE SUPPORT
M: Luis Chamberlain <mcgrof@kernel.org>
L: linux-modules@vger.kernel.org
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* Re: [PATCH 08/11] MIPS: mobileye: Add EyeQ5 dtsi
2023-10-04 16:10 ` [PATCH 08/11] MIPS: mobileye: Add EyeQ5 dtsi Gregory CLEMENT
@ 2023-10-04 16:41 ` Rob Herring
2023-10-05 15:17 ` Gregory CLEMENT
0 siblings, 1 reply; 53+ messages in thread
From: Rob Herring @ 2023-10-04 16:41 UTC (permalink / raw)
To: Gregory CLEMENT
Cc: Paul Burton, Thomas Bogendoerfer, linux-mips,
Krzysztof Kozlowski, devicetree, linux-kernel,
Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni
On Wed, Oct 4, 2023 at 11:11 AM Gregory CLEMENT
<gregory.clement@bootlin.com> wrote:
>
> Add a device tree include file for the Mobileye EyeQ5 SoC.
>
> Based on the work of Slava Samsonov <stanislav.samsonov@intel.com>
>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
> arch/mips/boot/dts/Makefile | 1 +
> arch/mips/boot/dts/mobileye/Makefile | 4 +
> .../boot/dts/mobileye/eyeq5-fixed-clocks.dtsi | 315 ++++++++++++++++++
> arch/mips/boot/dts/mobileye/eyeq5.dtsi | 138 ++++++++
> 4 files changed, 458 insertions(+)
> create mode 100644 arch/mips/boot/dts/mobileye/Makefile
> create mode 100644 arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi
> create mode 100644 arch/mips/boot/dts/mobileye/eyeq5.dtsi
>
> diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
> index 928f38a79dff..edb8e8dee758 100644
> --- a/arch/mips/boot/dts/Makefile
> +++ b/arch/mips/boot/dts/Makefile
> @@ -8,6 +8,7 @@ subdir-$(CONFIG_LANTIQ) += lantiq
> subdir-$(CONFIG_MACH_LOONGSON64) += loongson
> subdir-$(CONFIG_SOC_VCOREIII) += mscc
> subdir-$(CONFIG_MIPS_MALTA) += mti
> +subdir-$(CONFIG_SOC_EYEQ5) += mobileye
> subdir-$(CONFIG_LEGACY_BOARD_SEAD3) += mti
> subdir-$(CONFIG_FIT_IMAGE_FDT_NI169445) += ni
> subdir-$(CONFIG_MACH_PIC32) += pic32
> diff --git a/arch/mips/boot/dts/mobileye/Makefile b/arch/mips/boot/dts/mobileye/Makefile
> new file mode 100644
> index 000000000000..99c4124fd4c0
> --- /dev/null
> +++ b/arch/mips/boot/dts/mobileye/Makefile
> @@ -0,0 +1,4 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +# Copyright 2023 Mobileye Vision Technologies Ltd.
> +
> +obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
You didn't add anything to 'dtb-y'. Did you test this?
Also, CONFIG_BUILTIN_DTB is supposed to be for legacy bootloaders
which don't understand DT. For a new SoC, fix the bootloader.
> diff --git a/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi b/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi
> new file mode 100644
> index 000000000000..a0066465ac8b
> --- /dev/null
> +++ b/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi
> @@ -0,0 +1,315 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Copyright 2023 Mobileye Vision Technologies Ltd.
> + */
I assume these aren't all really fixed, but just 'I don't have a clock
driver yet'. That creates an ABI issue when you add the clock
driver(s). Just FYI.
> +
> +/ {
> + /* Fixed clock */
> + pll_cpu: pll_cpu {
Don't use _ in node names.
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <1500000000>;
> + };
> +
> + pll_vdi: pll_vdi {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <1280000000>;
> + };
> +
> + pll_per: pll_per {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <2000000000>;
> + };
> +
> + pll_ddr0: pll_ddr0 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <1857210000>;
> + };
> +
> + pll_ddr1: pll_ddr1 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <1857210000>;
> + };
> +
> +/* PLL_CPU derivatives */
> + occ_cpu: occ_cpu {
> + compatible = "fixed-factor-clock";
> + clocks = <&pll_cpu>;
> + #clock-cells = <0>;
> + clock-div = <1>;
> + clock-mult = <1>;
> + clock-output-names = "occ_cpu";
Isn't the default name the node name? Drop these unless you really
have a need and they aren't redundant.
> + };
> + si_css0_ref_clk: si_css0_ref_clk { /* gate ClkRstGen_si_css0_ref */
> + compatible = "fixed-factor-clock";
> + clocks = <&occ_cpu>;
> + #clock-cells = <0>;
> + clock-div = <1>;
> + clock-mult = <1>;
> + clock-output-names = "si_css0_ref_clk";
> + };
> + cpc_clk: cpc_clk {
> + compatible = "fixed-factor-clock";
> + clocks = <&si_css0_ref_clk>;
> + #clock-cells = <0>;
> + clock-div = <1>;
> + clock-mult = <1>;
> + clock-output-names = "cpc_clk";
> + };
> + core0_clk: core0_clk {
> + compatible = "fixed-factor-clock";
> + clocks = <&si_css0_ref_clk>;
> + #clock-cells = <0>;
> + clock-div = <1>;
> + clock-mult = <1>;
> + clock-output-names = "core0_clk";
> + };
> + core1_clk: core1_clk {
> + compatible = "fixed-factor-clock";
> + clocks = <&si_css0_ref_clk>;
> + #clock-cells = <0>;
> + clock-div = <1>;
> + clock-mult = <1>;
> + clock-output-names = "core1_clk";
> + };
> + core2_clk: core2_clk {
> + compatible = "fixed-factor-clock";
> + clocks = <&si_css0_ref_clk>;
> + #clock-cells = <0>;
> + clock-div = <1>;
> + clock-mult = <1>;
> + clock-output-names = "core2_clk";
> + };
> + core3_clk: core3_clk {
> + compatible = "fixed-factor-clock";
> + clocks = <&si_css0_ref_clk>;
> + #clock-cells = <0>;
> + clock-div = <1>;
> + clock-mult = <1>;
> + clock-output-names = "core3_clk";
> + };
> + cm_clk: cm_clk {
> + compatible = "fixed-factor-clock";
> + clocks = <&si_css0_ref_clk>;
> + #clock-cells = <0>;
> + clock-div = <1>;
> + clock-mult = <1>;
> + clock-output-names = "cm_clk";
> + };
> + mem_clk: mem_clk {
> + compatible = "fixed-factor-clock";
> + clocks = <&si_css0_ref_clk>;
> + #clock-cells = <0>;
> + clock-div = <1>;
> + clock-mult = <1>;
> + clock-output-names = "mem_clk";
> + };
> + occ_isram: occ_isram {
> + compatible = "fixed-factor-clock";
> + clocks = <&pll_cpu>;
> + #clock-cells = <0>;
> + clock-div = <2>;
> + clock-mult = <1>;
> + clock-output-names = "occ_isram";
> + };
> + isram_clk: isram_clk { /* gate ClkRstGen_isram */
> + compatible = "fixed-factor-clock";
> + clocks = <&occ_isram>;
> + #clock-cells = <0>;
> + clock-div = <1>;
> + clock-mult = <1>;
> + clock-output-names = "isram_clk";
> + };
> + occ_dbu: occ_dbu {
> + compatible = "fixed-factor-clock";
> + clocks = <&pll_cpu>;
> + #clock-cells = <0>;
> + clock-div = <10>;
> + clock-mult = <1>;
> + clock-output-names = "occ_dbu";
> + };
> + si_dbu_tp_pclk: si_dbu_tp_pclk { /* gate ClkRstGen_dbu */
> + compatible = "fixed-factor-clock";
> + clocks = <&occ_dbu>;
> + #clock-cells = <0>;
> + clock-div = <1>;
> + clock-mult = <1>;
> + clock-output-names = "si_dbu_tp_pclk";
> + };
> +/* PLL_VDI derivatives */
> + occ_vdi: occ_vdi {
> + compatible = "fixed-factor-clock";
> + clocks = <&pll_vdi>;
> + #clock-cells = <0>;
> + clock-div = <2>;
> + clock-mult = <1>;
> + clock-output-names = "occ_vdi";
> + };
> + vdi_clk: vdi_clk { /* gate ClkRstGen_vdi */
> + compatible = "fixed-factor-clock";
> + clocks = <&occ_vdi>;
> + #clock-cells = <0>;
> + clock-div = <1>;
> + clock-mult = <1>;
> + clock-output-names = "vdi_clk";
> + };
> + occ_can_ser: occ_can_ser {
> + compatible = "fixed-factor-clock";
> + clocks = <&pll_vdi>;
> + #clock-cells = <0>;
> + clock-div = <16>;
> + clock-mult = <1>;
> + clock-output-names = "occ_can_ser";
> + };
> + can_ser_clk: can_ser_clk { /* gate ClkRstGen_can_ser */
> + compatible = "fixed-factor-clock";
> + clocks = <&occ_can_ser>;
> + #clock-cells = <0>;
> + clock-div = <1>;
> + clock-mult = <1>;
> + clock-output-names = "can_ser_clk";
> + };
> + i2c_ser_clk: i2c_ser_clk {
> + compatible = "fixed-factor-clock";
> + clocks = <&pll_vdi>;
> + #clock-cells = <0>;
> + clock-div = <20>;
> + clock-mult = <1>;
> + clock-output-names = "i2c_ser_clk";
> + };
> +/* PLL_PER derivatives */
> + occ_periph: occ_periph {
> + compatible = "fixed-factor-clock";
> + clocks = <&pll_per>;
> + #clock-cells = <0>;
> + clock-div = <16>;
> + clock-mult = <1>;
> + clock-output-names = "occ_periph";
> + };
> + periph_clk: periph_clk {
> + compatible = "fixed-factor-clock";
> + clocks = <&occ_periph>;
> + #clock-cells = <0>;
> + clock-div = <1>;
> + clock-mult = <1>;
> + clock-output-names = "periph_clk";
> + };
> + can_clk: can_clk {
> + compatible = "fixed-factor-clock";
> + clocks = <&occ_periph>;
> + #clock-cells = <0>;
> + clock-div = <1>;
> + clock-mult = <1>;
> + clock-output-names = "can_clk";
> + };
> + spi_clk: spi_clk {
> + compatible = "fixed-factor-clock";
> + clocks = <&occ_periph>;
> + #clock-cells = <0>;
> + clock-div = <1>;
> + clock-mult = <1>;
> + clock-output-names = "spi_clk";
> + };
> + uart_clk: uart_clk {
> + compatible = "fixed-factor-clock";
> + clocks = <&occ_periph>;
> + #clock-cells = <0>;
> + clock-div = <1>;
> + clock-mult = <1>;
> + clock-output-names = "uart_clk";
> + };
> + i2c_clk: i2c_clk {
> + compatible = "fixed-factor-clock";
> + clocks = <&occ_periph>;
> + #clock-cells = <0>;
> + clock-div = <1>;
> + clock-mult = <1>;
> + clock-output-names = "i2c_clk";
> + };
> + timer_clk: timer_clk {
> + compatible = "fixed-factor-clock";
> + clocks = <&occ_periph>;
> + #clock-cells = <0>;
> + clock-div = <1>;
> + clock-mult = <1>;
> + clock-output-names = "timer_clk";
> + };
> + gpio_clk: gpio_clk {
> + compatible = "fixed-factor-clock";
> + clocks = <&occ_periph>;
> + #clock-cells = <0>;
> + clock-div = <1>;
> + clock-mult = <1>;
> + clock-output-names = "gpio_clk";
> + };
> + emmc_sys_clk: emmc_sys_clk {
> + compatible = "fixed-factor-clock";
> + clocks = <&pll_per>;
> + #clock-cells = <0>;
> + clock-div = <10>;
> + clock-mult = <1>;
> + clock-output-names = "emmc_sys_clk";
> + };
> + ccf_ctrl_clk: ccf_ctrl_clk {
> + compatible = "fixed-factor-clock";
> + clocks = <&pll_per>;
> + #clock-cells = <0>;
> + clock-div = <4>;
> + clock-mult = <1>;
> + clock-output-names = "ccf_ctrl_clk";
> + };
> + occ_mjpeg_core: occ_mjpeg_core {
> + compatible = "fixed-factor-clock";
> + clocks = <&pll_per>;
> + #clock-cells = <0>;
> + clock-div = <2>;
> + clock-mult = <1>;
> + clock-output-names = "occ_mjpeg_core";
> + };
> + hsm_clk: hsm_clk { /* gate ClkRstGen_hsm */
> + compatible = "fixed-factor-clock";
> + clocks = <&occ_mjpeg_core>;
> + #clock-cells = <0>;
> + clock-div = <1>;
> + clock-mult = <1>;
> + clock-output-names = "hsm_clk";
> + };
> + mjpeg_core_clk: mjpeg_core_clk { /* gate ClkRstGen_mjpeg_gen */
> + compatible = "fixed-factor-clock";
> + clocks = <&occ_mjpeg_core>;
> + #clock-cells = <0>;
> + clock-div = <1>;
> + clock-mult = <1>;
> + clock-output-names = "mjpeg_core_clk";
> + };
> + fcmu_a_clk: fcmu_a_clk {
> + compatible = "fixed-factor-clock";
> + clocks = <&pll_per>;
> + #clock-cells = <0>;
> + clock-div = <20>;
> + clock-mult = <1>;
> + clock-output-names = "fcmu_a_clk";
> + };
> + occ_pci_sys: occ_pci_sys {
> + compatible = "fixed-factor-clock";
> + clocks = <&pll_per>;
> + #clock-cells = <0>;
> + clock-div = <8>;
> + clock-mult = <1>;
> + clock-output-names = "occ_pci_sys";
> + };
> + pclk: pclk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <250000000>; /* 250MHz */
> + };
> + tsu_clk: tsu_clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <125000000>; /* 125MHz */
> + };
> +};
> diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi
> new file mode 100644
> index 000000000000..0504c2fb3ad5
> --- /dev/null
> +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi
> @@ -0,0 +1,138 @@
> +// SPDX-License-Identifier: GPL-2.0
Doesn't match eyeq5-fixed-clocks.dtsi
> +/*
> + * Copyright 2023 Mobileye Vision Technologies Ltd.
> + */
> +
> +#include <dt-bindings/interrupt-controller/mips-gic.h>
> +#include <dt-bindings/soc/mobileye,eyeq5.h>
> +
> +/memreserve/ 0x40000000 0xc0000000; /* DDR32 */
> +/memreserve/ 0x08000000 0x08000000; /* DDR_LOW */
> +
> +#include "eyeq5-fixed-clocks.dtsi"
> +
> +/* almost all GIC IRQs has the same characteristics. provide short form */
Maybe so, but I prefer not having 2 levels of lookup to figure out values.
> +#define GIC_IRQ(x) GIC_SHARED (x) IRQ_TYPE_LEVEL_HIGH
> +
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cpu@0 {
> + device_type = "cpu";
> + compatible = "mti,i6500";
> + reg = <0>;
> + clocks = <&core0_clk>;
> + };
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> +/* These reserved memory regions are also defined in bootmanager
> + * for configuring inbound translation for BARS, don't change
> + * these without syncing with bootmanager
> + */
Indent with the rest of the node.
> + shmem0_reserved: shmem@804000000 {
> + reg = <0x8 0x04000000 0x0 0x1000000>;
> + };
> + shmem1_reserved: shmem@805000000 {
> + reg = <0x8 0x05000000 0x0 0x1000000>;
> + };
> + pci0_msi_reserved: pci0_msi@806000000 {
> + reg = <0x8 0x06000000 0x0 0x100000>;
> + };
> + pci1_msi_reserved: pci1_msi@806100000 {
> + reg = <0x8 0x06100000 0x0 0x100000>;
> + };
> +
> + mini_coredump0_reserved: mini_coredump0@806200000 {
> + reg = <0x8 0x06200000 0x0 0x100000>;
> + };
> + mhm_reserved_0: the_mhm_reserved_0@0 {
> + reg = <0x8 0x00000000 0x0 0x0000800>;
> + };
> + };
> +
> + aliases {
> + serial0 = &uart0;
> + serial1 = &uart1;
> + serial2 = &uart2;
> + };
> +
> + cpu_intc: interrupt-controller {
> + compatible = "mti,cpu-interrupt-controller";
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + };
> +
> + gic: interrupt-controller@140000 {
> + compatible = "mti,gic";
> + reg = <0x0 0x140000 0x0 0x20000>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> +
> + /*
> + * Declare the interrupt-parent even though the mti,gic
> + * binding doesn't require it, such that the kernel can
> + * figure out that cpu_intc is the root interrupt
> + * controller & should be probed first.
> + */
> + interrupt-parent = <&cpu_intc>;
> +
> + timer {
> + compatible = "mti,gic-timer";
> + interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
> + clocks = <&core0_clk>;
> + };
> + };
> +
> + soc: soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + compatible = "simple-bus";
> +
> + uart0: serial@800000 {
> + compatible = "arm,pl011", "arm,primecell";
> + reg = <0 0x800000 0x0 0x1000>;
> + reg-io-width = <4>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_IRQ(NUM_INT_UART)>;
> + clocks = <&uart_clk>, <&occ_periph>;
> + clock-names = "uartclk", "apb_pclk";
> + };
> +
> + uart1: serial@900000 {
> + compatible = "arm,pl011", "arm,primecell";
> + reg = <0 0x900000 0x0 0x1000>;
> + reg-io-width = <4>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_IRQ(NUM_INT_UART)>;
> + clocks = <&uart_clk>, <&occ_periph>;
> + clock-names = "uartclk", "apb_pclk";
> + };
> +
> + uart2: serial@a00000 {
> + compatible = "arm,pl011", "arm,primecell";
> + reg = <0 0xa00000 0x0 0x1000>;
> + reg-io-width = <4>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_IRQ(NUM_INT_UART)>;
> + clocks = <&uart_clk>, <&occ_periph>;
> + clock-names = "uartclk", "apb_pclk";
> + };
> +
> + olb: olb@e00000 {
> + compatible = "mobileye,eyeq5-olb", "syscon", "simple-mfd";
> + reg = <0 0xe00000 0x0 0x400>;
> + reg-io-width = <4>;
> + };
> +
> + };
> +};
> --
> 2.40.1
>
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 06/11] dt-bindings: mips: Add bindings for Mobileye SoCs
2023-10-04 16:10 ` [PATCH 06/11] dt-bindings: mips: Add bindings for Mobileye SoCs Gregory CLEMENT
@ 2023-10-04 16:47 ` Rob Herring
2023-10-05 14:55 ` Gregory CLEMENT
0 siblings, 1 reply; 53+ messages in thread
From: Rob Herring @ 2023-10-04 16:47 UTC (permalink / raw)
To: Gregory CLEMENT
Cc: Paul Burton, Thomas Bogendoerfer, linux-mips,
Krzysztof Kozlowski, devicetree, linux-kernel,
Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni
On Wed, Oct 4, 2023 at 11:11 AM Gregory CLEMENT
<gregory.clement@bootlin.com> wrote:
>
> Add the yaml bindings for Mobileye SoCs. Currently only EyeQ5 is
> supported
>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
> .../devicetree/bindings/mips/mobileye.yaml | 36 +++++++++
> include/dt-bindings/soc/mobileye,eyeq5.h | 77 +++++++++++++++++++
> 2 files changed, 113 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mips/mobileye.yaml
> create mode 100644 include/dt-bindings/soc/mobileye,eyeq5.h
>
> diff --git a/Documentation/devicetree/bindings/mips/mobileye.yaml b/Documentation/devicetree/bindings/mips/mobileye.yaml
> new file mode 100644
> index 000000000000..f47767bc2c8f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mips/mobileye.yaml
> @@ -0,0 +1,36 @@
> +# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
Use what checkpatch tells you.
> +# Copyright 2023 Mobileye Vision Technologies Ltd.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mips/mobileye.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mobileye SoC series
> +
> +maintainers:
> + - Vladimir Kondratiev <vladimir.kondratiev@intel.com>
> + - Gregory CLEMENT <gregory.clement@bootlin.com>
> + - Théo Lebrun <theo.lebrun@bootlin.com>
> +
> +description: |
Don't need '|'.
> + Boards with a Mobileye SoC shall have the following properties.
> +
> +properties:
> + $nodename:
> + const: '/'
> +
> + compatible:
> + oneOf:
> + - description: Boards with Mobileye EyeQ5 SoC
> + items:
> + - enum:
> + - mobileye,eyeq5-epm5
> + - const: mobileye,eyeq5
> +
> + - description: Boards with Mobileye EyeQ6 SoC
> + items:
> + - const: mobileye,eyeq6
Not valid to have only SoC compatible. Add this when you have a user.
> +
> +additionalProperties: true
> +
> +...
> diff --git a/include/dt-bindings/soc/mobileye,eyeq5.h b/include/dt-bindings/soc/mobileye,eyeq5.h
> new file mode 100644
> index 000000000000..7d8cb97b45bf
> --- /dev/null
> +++ b/include/dt-bindings/soc/mobileye,eyeq5.h
> @@ -0,0 +1,77 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright 2023 Mobileye Vision Technologies Ltd.
> + */
> +#ifndef _DT_BINDINGS_SOC_MOBILEYE_EYEQ5_H
> +#define _DT_BINDINGS_SOC_MOBILEYE_EYEQ5_H
> +
> +/* EQ5 interrupts */
> +#define NUM_INT_I2C_A 1
> +#define NUM_INT_I2C_B 2
> +#define NUM_INT_I2C_C 3
> +#define NUM_INT_I2C_D 4
> +#define NUM_INT_I2C_E 5
These are interrupt numbers? Note that we never do headers for
interrupt numbers, so drop this.
Rob
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 10/11] MIPS: generic: Add support for Mobileye EyeQ5
2023-10-04 16:10 ` [PATCH 10/11] MIPS: generic: Add support for Mobileye EyeQ5 Gregory CLEMENT
@ 2023-10-05 0:08 ` kernel test robot
2023-10-06 14:47 ` Arnd Bergmann
0 siblings, 1 reply; 53+ messages in thread
From: kernel test robot @ 2023-10-05 0:08 UTC (permalink / raw)
To: Gregory CLEMENT, Paul Burton, Thomas Bogendoerfer, linux-mips,
Rob Herring, Krzysztof Kozlowski, devicetree, linux-kernel
Cc: oe-kbuild-all, Vladimir Kondratiev, Tawfik Bayouk,
Alexandre Belloni, Théo Lebrun, Thomas Petazzoni,
Gregory CLEMENT
Hi Gregory,
kernel test robot noticed the following build errors:
[auto build test ERROR on robh/for-next]
[also build test ERROR on lee-mfd/for-mfd-next linus/master v6.6-rc4 next-20231004]
[cannot apply to lee-mfd/for-mfd-fixes]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Gregory-CLEMENT/MIPS-compressed-Use-correct-instruction-for-64-bit-code/20231005-001314
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link: https://lore.kernel.org/r/20231004161038.2818327-11-gregory.clement%40bootlin.com
patch subject: [PATCH 10/11] MIPS: generic: Add support for Mobileye EyeQ5
config: mips-allmodconfig (https://download.01.org/0day-ci/archive/20231005/202310050726.GDpZbMDO-lkp@intel.com/config)
compiler: mips-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231005/202310050726.GDpZbMDO-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202310050726.GDpZbMDO-lkp@intel.com/
All error/warnings (new ones prefixed by >>):
drivers/tty/serial/amba-pl011.c: In function 'pl011_sgbuf_init':
>> drivers/tty/serial/amba-pl011.c:380:30: error: implicit declaration of function 'phys_to_page'; did you mean 'pfn_to_page'? [-Werror=implicit-function-declaration]
380 | sg_set_page(&sg->sg, phys_to_page(dma_addr),
| ^~~~~~~~~~~~
| pfn_to_page
>> drivers/tty/serial/amba-pl011.c:380:30: warning: passing argument 2 of 'sg_set_page' makes pointer from integer without a cast [-Wint-conversion]
380 | sg_set_page(&sg->sg, phys_to_page(dma_addr),
| ^~~~~~~~~~~~~~~~~~~~~~
| |
| int
In file included from include/linux/kfifo.h:42,
from include/linux/tty_port.h:5,
from include/linux/tty.h:12,
from drivers/tty/serial/amba-pl011.c:26:
include/linux/scatterlist.h:136:69: note: expected 'struct page *' but argument is of type 'int'
136 | static inline void sg_set_page(struct scatterlist *sg, struct page *page,
| ~~~~~~~~~~~~~^~~~
cc1: some warnings being treated as errors
vim +380 drivers/tty/serial/amba-pl011.c
68b65f7305e54b drivers/serial/amba-pl011.c Russell King 2010-12-22 368
ead76f329f777c drivers/tty/serial/amba-pl011.c Linus Walleij 2011-02-24 369 static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
ead76f329f777c drivers/tty/serial/amba-pl011.c Linus Walleij 2011-02-24 370 enum dma_data_direction dir)
ead76f329f777c drivers/tty/serial/amba-pl011.c Linus Walleij 2011-02-24 371 {
cb06ff102e2d79 drivers/tty/serial/amba-pl011.c Chanho Min 2013-03-27 372 dma_addr_t dma_addr;
cb06ff102e2d79 drivers/tty/serial/amba-pl011.c Chanho Min 2013-03-27 373
cb06ff102e2d79 drivers/tty/serial/amba-pl011.c Chanho Min 2013-03-27 374 sg->buf = dma_alloc_coherent(chan->device->dev,
cb06ff102e2d79 drivers/tty/serial/amba-pl011.c Chanho Min 2013-03-27 375 PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL);
ead76f329f777c drivers/tty/serial/amba-pl011.c Linus Walleij 2011-02-24 376 if (!sg->buf)
ead76f329f777c drivers/tty/serial/amba-pl011.c Linus Walleij 2011-02-24 377 return -ENOMEM;
ead76f329f777c drivers/tty/serial/amba-pl011.c Linus Walleij 2011-02-24 378
cb06ff102e2d79 drivers/tty/serial/amba-pl011.c Chanho Min 2013-03-27 379 sg_init_table(&sg->sg, 1);
cb06ff102e2d79 drivers/tty/serial/amba-pl011.c Chanho Min 2013-03-27 @380 sg_set_page(&sg->sg, phys_to_page(dma_addr),
cb06ff102e2d79 drivers/tty/serial/amba-pl011.c Chanho Min 2013-03-27 381 PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr));
cb06ff102e2d79 drivers/tty/serial/amba-pl011.c Chanho Min 2013-03-27 382 sg_dma_address(&sg->sg) = dma_addr;
c64be9231e0893 drivers/tty/serial/amba-pl011.c Andrew Jackson 2014-11-07 383 sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE;
ead76f329f777c drivers/tty/serial/amba-pl011.c Linus Walleij 2011-02-24 384
ead76f329f777c drivers/tty/serial/amba-pl011.c Linus Walleij 2011-02-24 385 return 0;
ead76f329f777c drivers/tty/serial/amba-pl011.c Linus Walleij 2011-02-24 386 }
ead76f329f777c drivers/tty/serial/amba-pl011.c Linus Walleij 2011-02-24 387
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 05/11] dt-bindings: mips: cpu: Add I-Class I6500 Multiprocessor Core
2023-10-04 16:10 ` [PATCH 05/11] dt-bindings: mips: cpu: Add I-Class I6500 Multiprocessor Core Gregory CLEMENT
@ 2023-10-05 6:31 ` Philippe Mathieu-Daudé
2023-10-05 14:39 ` Serge Semin
2023-10-05 14:47 ` Sergio Paracuellos
2 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-05 6:31 UTC (permalink / raw)
To: Gregory CLEMENT, Paul Burton, Thomas Bogendoerfer, linux-mips,
Rob Herring, Krzysztof Kozlowski, devicetree, linux-kernel
Cc: Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni
On 4/10/23 18:10, Gregory CLEMENT wrote:
> The MIPS Warrior I-class I6500 was announced by Imagination
> Technologies in 2016 and is used in the Mobileye SoC EyeQ5.
>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
> Documentation/devicetree/bindings/mips/cpus.yaml | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 04/11] dt-bindings: Add vendor prefix for Mobileye Vision Technologies Ltd.
2023-10-04 16:10 ` [PATCH 04/11] dt-bindings: Add vendor prefix for Mobileye Vision Technologies Ltd Gregory CLEMENT
@ 2023-10-05 6:34 ` Philippe Mathieu-Daudé
2023-10-06 16:32 ` Rob Herring
1 sibling, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-05 6:34 UTC (permalink / raw)
To: Gregory CLEMENT, Paul Burton, Thomas Bogendoerfer, linux-mips,
Rob Herring, Krzysztof Kozlowski, devicetree, linux-kernel
Cc: Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni
On 4/10/23 18:10, Gregory CLEMENT wrote:
> Mobileye Vision Technologies Ltd. is a company developing autonomous
> driving technologies and advanced driver-assistance systems (ADAS)
> including cameras, computer chips and software.
>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
> Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
> 1 file changed, 2 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 01/11] MIPS: compressed: Use correct instruction for 64 bit code
2023-10-04 16:10 ` [PATCH 01/11] MIPS: compressed: Use correct instruction for 64 bit code Gregory CLEMENT
@ 2023-10-05 6:40 ` Philippe Mathieu-Daudé
2023-10-24 1:49 ` Florian Fainelli
1 sibling, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-05 6:40 UTC (permalink / raw)
To: Gregory CLEMENT, Paul Burton, Thomas Bogendoerfer, linux-mips,
Rob Herring, Krzysztof Kozlowski, devicetree, linux-kernel
Cc: Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni
On 4/10/23 18:10, Gregory CLEMENT wrote:
> The code clearing BSS already use macro or use correct instruction
> depending id the CPU is 32 bits or 64 bits. However, a few
> instructions remained 32 bits only.
>
> By using the accurate MACRO, it is now possible to deal with memory
> address beyond 32 bits. As a side effect, when using 64bits processor,
> it also divides the loop number needed to clear the BSS by 2.
>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
> arch/mips/boot/compressed/head.S | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 05/11] dt-bindings: mips: cpu: Add I-Class I6500 Multiprocessor Core
2023-10-04 16:10 ` [PATCH 05/11] dt-bindings: mips: cpu: Add I-Class I6500 Multiprocessor Core Gregory CLEMENT
2023-10-05 6:31 ` Philippe Mathieu-Daudé
@ 2023-10-05 14:39 ` Serge Semin
2023-10-05 14:51 ` Gregory CLEMENT
2023-10-05 14:47 ` Sergio Paracuellos
2 siblings, 1 reply; 53+ messages in thread
From: Serge Semin @ 2023-10-05 14:39 UTC (permalink / raw)
To: Gregory CLEMENT
Cc: Philippe Mathieu-Daudé,
Paul Burton, Thomas Bogendoerfer, linux-mips, Rob Herring,
Krzysztof Kozlowski, devicetree, linux-kernel,
Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni
On Wed, Oct 04, 2023 at 06:10:32PM +0200, Gregory CLEMENT wrote:
> The MIPS Warrior I-class I6500 was announced by Imagination
> Technologies in 2016 and is used in the Mobileye SoC EyeQ5.
>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
> Documentation/devicetree/bindings/mips/cpus.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/mips/cpus.yaml b/Documentation/devicetree/bindings/mips/cpus.yaml
> index cf382dea3922..87fd2842ba68 100644
> --- a/Documentation/devicetree/bindings/mips/cpus.yaml
> +++ b/Documentation/devicetree/bindings/mips/cpus.yaml
> @@ -39,6 +39,7 @@ properties:
> - mti,mips24KEc
> - mti,mips14KEc
> - mti,mips14Kc
> + - mti,i6500
Since the CPU core vendor is Imagination Technologies thus it would
be more appropriate to have the "img," prefix. Wouldn't it?
-Serge(y)
>
> reg:
> maxItems: 1
> --
> 2.40.1
>
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 05/11] dt-bindings: mips: cpu: Add I-Class I6500 Multiprocessor Core
2023-10-04 16:10 ` [PATCH 05/11] dt-bindings: mips: cpu: Add I-Class I6500 Multiprocessor Core Gregory CLEMENT
2023-10-05 6:31 ` Philippe Mathieu-Daudé
2023-10-05 14:39 ` Serge Semin
@ 2023-10-05 14:47 ` Sergio Paracuellos
2 siblings, 0 replies; 53+ messages in thread
From: Sergio Paracuellos @ 2023-10-05 14:47 UTC (permalink / raw)
To: Gregory CLEMENT
Cc: Paul Burton, Thomas Bogendoerfer, linux-mips, Rob Herring,
Krzysztof Kozlowski, devicetree, linux-kernel,
Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni
On Wed, Oct 4, 2023 at 6:15 PM Gregory CLEMENT
<gregory.clement@bootlin.com> wrote:
>
> The MIPS Warrior I-class I6500 was announced by Imagination
> Technologies in 2016 and is used in the Mobileye SoC EyeQ5.
>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
> Documentation/devicetree/bindings/mips/cpus.yaml | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 05/11] dt-bindings: mips: cpu: Add I-Class I6500 Multiprocessor Core
2023-10-05 14:39 ` Serge Semin
@ 2023-10-05 14:51 ` Gregory CLEMENT
2023-10-05 15:23 ` Serge Semin
2023-10-06 10:48 ` Arnd Bergmann
0 siblings, 2 replies; 53+ messages in thread
From: Gregory CLEMENT @ 2023-10-05 14:51 UTC (permalink / raw)
To: Serge Semin
Cc: Philippe Mathieu-Daudé,
Paul Burton, Thomas Bogendoerfer, linux-mips, Rob Herring,
Krzysztof Kozlowski, devicetree, linux-kernel,
Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni
Hello Serge(y),
> On Wed, Oct 04, 2023 at 06:10:32PM +0200, Gregory CLEMENT wrote:
>> The MIPS Warrior I-class I6500 was announced by Imagination
>> Technologies in 2016 and is used in the Mobileye SoC EyeQ5.
>>
>> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
>> ---
>> Documentation/devicetree/bindings/mips/cpus.yaml | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/Documentation/devicetree/bindings/mips/cpus.yaml b/Documentation/devicetree/bindings/mips/cpus.yaml
>> index cf382dea3922..87fd2842ba68 100644
>> --- a/Documentation/devicetree/bindings/mips/cpus.yaml
>> +++ b/Documentation/devicetree/bindings/mips/cpus.yaml
>> @@ -39,6 +39,7 @@ properties:
>> - mti,mips24KEc
>> - mti,mips14KEc
>> - mti,mips14Kc
>
>> + - mti,i6500
>
> Since the CPU core vendor is Imagination Technologies thus it would
> be more appropriate to have the "img," prefix. Wouldn't it?
According to Documentation/devicetree/bindings/vendor-prefixes.yaml
"^mti,.*":
description: Imagination Technologies Ltd. (formerly MIPS
Technologies Inc.)
So I think it's OK.
Gregory
>
> -Serge(y)
>
>>
>> reg:
>> maxItems: 1
>> --
>> 2.40.1
>>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 06/11] dt-bindings: mips: Add bindings for Mobileye SoCs
2023-10-04 16:47 ` Rob Herring
@ 2023-10-05 14:55 ` Gregory CLEMENT
2023-10-06 16:50 ` Rob Herring
0 siblings, 1 reply; 53+ messages in thread
From: Gregory CLEMENT @ 2023-10-05 14:55 UTC (permalink / raw)
To: Rob Herring
Cc: Paul Burton, Thomas Bogendoerfer, linux-mips,
Krzysztof Kozlowski, devicetree, linux-kernel,
Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni
Hello Rob,
> On Wed, Oct 4, 2023 at 11:11 AM Gregory CLEMENT
> <gregory.clement@bootlin.com> wrote:
>>
>> Add the yaml bindings for Mobileye SoCs. Currently only EyeQ5 is
>> supported
>>
>> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
>> ---
>> .../devicetree/bindings/mips/mobileye.yaml | 36 +++++++++
>> include/dt-bindings/soc/mobileye,eyeq5.h | 77 +++++++++++++++++++
>> 2 files changed, 113 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/mips/mobileye.yaml
>> create mode 100644 include/dt-bindings/soc/mobileye,eyeq5.h
>>
>> diff --git a/Documentation/devicetree/bindings/mips/mobileye.yaml b/Documentation/devicetree/bindings/mips/mobileye.yaml
>> new file mode 100644
>> index 000000000000..f47767bc2c8f
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mips/mobileye.yaml
>> @@ -0,0 +1,36 @@
>> +# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
>
> Use what checkpatch tells you.
From my point of view GPL-2.0-or-later is compatible with GPL-2.0-only,
but OK I will do this.
>
>> +# Copyright 2023 Mobileye Vision Technologies Ltd.
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/mips/mobileye.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Mobileye SoC series
>> +
>> +maintainers:
>> + - Vladimir Kondratiev <vladimir.kondratiev@intel.com>
>> + - Gregory CLEMENT <gregory.clement@bootlin.com>
>> + - Théo Lebrun <theo.lebrun@bootlin.com>
>> +
>> +description: |
>
> Don't need '|'.
OK
>
>> + Boards with a Mobileye SoC shall have the following properties.
>> +
>> +properties:
>> + $nodename:
>> + const: '/'
>> +
>> + compatible:
>> + oneOf:
>> + - description: Boards with Mobileye EyeQ5 SoC
>> + items:
>> + - enum:
>> + - mobileye,eyeq5-epm5
>> + - const: mobileye,eyeq5
>> +
>> + - description: Boards with Mobileye EyeQ6 SoC
>> + items:
>> + - const: mobileye,eyeq6
>
> Not valid to have only SoC compatible. Add this when you have a user.
OK
>
>> +
>> +additionalProperties: true
>> +
>> +...
>> diff --git a/include/dt-bindings/soc/mobileye,eyeq5.h b/include/dt-bindings/soc/mobileye,eyeq5.h
>> new file mode 100644
>> index 000000000000..7d8cb97b45bf
>> --- /dev/null
>> +++ b/include/dt-bindings/soc/mobileye,eyeq5.h
>> @@ -0,0 +1,77 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/*
>> + * Copyright 2023 Mobileye Vision Technologies Ltd.
>> + */
>> +#ifndef _DT_BINDINGS_SOC_MOBILEYE_EYEQ5_H
>> +#define _DT_BINDINGS_SOC_MOBILEYE_EYEQ5_H
>> +
>> +/* EQ5 interrupts */
>> +#define NUM_INT_I2C_A 1
>> +#define NUM_INT_I2C_B 2
>> +#define NUM_INT_I2C_C 3
>> +#define NUM_INT_I2C_D 4
>> +#define NUM_INT_I2C_E 5
>
> These are interrupt numbers? Note that we never do headers for
> interrupt numbers, so drop this.
OK
Thanks for the review the changesrequested will be part of the next
version.
Gregory
>
> Rob
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 08/11] MIPS: mobileye: Add EyeQ5 dtsi
2023-10-04 16:41 ` Rob Herring
@ 2023-10-05 15:17 ` Gregory CLEMENT
0 siblings, 0 replies; 53+ messages in thread
From: Gregory CLEMENT @ 2023-10-05 15:17 UTC (permalink / raw)
To: Rob Herring
Cc: Paul Burton, Thomas Bogendoerfer, linux-mips,
Krzysztof Kozlowski, devicetree, linux-kernel,
Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni
Hello Rob,
> On Wed, Oct 4, 2023 at 11:11 AM Gregory CLEMENT
> <gregory.clement@bootlin.com> wrote:
>>
>> Add a device tree include file for the Mobileye EyeQ5 SoC.
>>
>> Based on the work of Slava Samsonov <stanislav.samsonov@intel.com>
>>
>> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
>> ---
>> arch/mips/boot/dts/Makefile | 1 +
>> arch/mips/boot/dts/mobileye/Makefile | 4 +
>> .../boot/dts/mobileye/eyeq5-fixed-clocks.dtsi | 315 ++++++++++++++++++
>> arch/mips/boot/dts/mobileye/eyeq5.dtsi | 138 ++++++++
>> 4 files changed, 458 insertions(+)
>> create mode 100644 arch/mips/boot/dts/mobileye/Makefile
>> create mode 100644 arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi
>> create mode 100644 arch/mips/boot/dts/mobileye/eyeq5.dtsi
>>
>> diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
>> index 928f38a79dff..edb8e8dee758 100644
>> --- a/arch/mips/boot/dts/Makefile
>> +++ b/arch/mips/boot/dts/Makefile
>> @@ -8,6 +8,7 @@ subdir-$(CONFIG_LANTIQ) += lantiq
>> subdir-$(CONFIG_MACH_LOONGSON64) += loongson
>> subdir-$(CONFIG_SOC_VCOREIII) += mscc
>> subdir-$(CONFIG_MIPS_MALTA) += mti
>> +subdir-$(CONFIG_SOC_EYEQ5) += mobileye
>> subdir-$(CONFIG_LEGACY_BOARD_SEAD3) += mti
>> subdir-$(CONFIG_FIT_IMAGE_FDT_NI169445) += ni
>> subdir-$(CONFIG_MACH_PIC32) += pic32
>> diff --git a/arch/mips/boot/dts/mobileye/Makefile b/arch/mips/boot/dts/mobileye/Makefile
>> new file mode 100644
>> index 000000000000..99c4124fd4c0
>> --- /dev/null
>> +++ b/arch/mips/boot/dts/mobileye/Makefile
>> @@ -0,0 +1,4 @@
>> +# SPDX-License-Identifier: GPL-2.0-only
>> +# Copyright 2023 Mobileye Vision Technologies Ltd.
>> +
>> +obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
>
> You didn't add anything to 'dtb-y'. Did you test this?
Initially yes, and finally we switch on the FIT image generation, so we
don't use it anymore
>
> Also, CONFIG_BUILTIN_DTB is supposed to be for legacy bootloaders
> which don't understand DT. For a new SoC, fix the bootloader.
I can remove it
>
>> diff --git a/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi b/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi
>> new file mode 100644
>> index 000000000000..a0066465ac8b
>> --- /dev/null
>> +++ b/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi
>> @@ -0,0 +1,315 @@
>> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +/*
>> + * Copyright 2023 Mobileye Vision Technologies Ltd.
>> + */
>
> I assume these aren't all really fixed, but just 'I don't have a clock
> driver yet'. That creates an ABI issue when you add the clock
> driver(s). Just FYI.
Indeed they aren't all fixed. The plan is to replace the relevant ones by a
real clock driver when ready.
In this case some part of the dts file will be modified. But is it a
real issue ?
Booting with a new kernel with an old dtb will still continue to work in
the same way. it's only new tdb with old kernel that won't work, but we
are not supposed to support this case.
>
>> +
>> +/ {
>> + /* Fixed clock */
>> + pll_cpu: pll_cpu {
>
> Don't use _ in node names.
OK
[...]
>> +/* PLL_CPU derivatives */
>> + occ_cpu: occ_cpu {
>> + compatible = "fixed-factor-clock";
>> + clocks = <&pll_cpu>;
>> + #clock-cells = <0>;
>> + clock-div = <1>;
>> + clock-mult = <1>;
>> + clock-output-names = "occ_cpu";
>
> Isn't the default name the node name? Drop these unless you really
> have a need and they aren't redundant.
indeed it's not used, I remove them too.
[...]
>> --- /dev/null
>> +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi
>> @@ -0,0 +1,138 @@
>> +// SPDX-License-Identifier: GPL-2.0
>
> Doesn't match eyeq5-fixed-clocks.dtsi
OK
>
>> +/*
>> + * Copyright 2023 Mobileye Vision Technologies Ltd.
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/mips-gic.h>
>> +#include <dt-bindings/soc/mobileye,eyeq5.h>
>> +
>> +/memreserve/ 0x40000000 0xc0000000; /* DDR32 */
>> +/memreserve/ 0x08000000 0x08000000; /* DDR_LOW */
>> +
>> +#include "eyeq5-fixed-clocks.dtsi"
>> +
>> +/* almost all GIC IRQs has the same characteristics. provide short form */
>
> Maybe so, but I prefer not having 2 levels of lookup to figure out values.
>
>> +#define GIC_IRQ(x) GIC_SHARED (x) IRQ_TYPE_LEVEL_HIGH
OK I remove it.
>> +
>> +/ {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + cpu@0 {
>> + device_type = "cpu";
>> + compatible = "mti,i6500";
>> + reg = <0>;
>> + clocks = <&core0_clk>;
>> + };
>> + };
>> +
>> + reserved-memory {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> +/* These reserved memory regions are also defined in bootmanager
>> + * for configuring inbound translation for BARS, don't change
>> + * these without syncing with bootmanager
>> + */
>
> Indent with the rest of the node.
OK
Thanks,
Gregory
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 05/11] dt-bindings: mips: cpu: Add I-Class I6500 Multiprocessor Core
2023-10-05 14:51 ` Gregory CLEMENT
@ 2023-10-05 15:23 ` Serge Semin
2023-10-06 10:48 ` Arnd Bergmann
1 sibling, 0 replies; 53+ messages in thread
From: Serge Semin @ 2023-10-05 15:23 UTC (permalink / raw)
To: Gregory CLEMENT, Rob Herring, Rob Herring
Cc: Philippe Mathieu-Daudé,
Paul Burton, Thomas Bogendoerfer, linux-mips,
Krzysztof Kozlowski, devicetree, linux-kernel,
Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni
On Thu, Oct 05, 2023 at 04:51:50PM +0200, Gregory CLEMENT wrote:
> Hello Serge(y),
>
> > On Wed, Oct 04, 2023 at 06:10:32PM +0200, Gregory CLEMENT wrote:
> >> The MIPS Warrior I-class I6500 was announced by Imagination
> >> Technologies in 2016 and is used in the Mobileye SoC EyeQ5.
> >>
> >> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> >> ---
> >> Documentation/devicetree/bindings/mips/cpus.yaml | 1 +
> >> 1 file changed, 1 insertion(+)
> >>
> >> diff --git a/Documentation/devicetree/bindings/mips/cpus.yaml b/Documentation/devicetree/bindings/mips/cpus.yaml
> >> index cf382dea3922..87fd2842ba68 100644
> >> --- a/Documentation/devicetree/bindings/mips/cpus.yaml
> >> +++ b/Documentation/devicetree/bindings/mips/cpus.yaml
> >> @@ -39,6 +39,7 @@ properties:
> >> - mti,mips24KEc
> >> - mti,mips14KEc
> >> - mti,mips14Kc
> >
> >> + - mti,i6500
> >
> > Since the CPU core vendor is Imagination Technologies thus it would
> > be more appropriate to have the "img," prefix. Wouldn't it?
>
> According to Documentation/devicetree/bindings/vendor-prefixes.yaml
>
> "^mti,.*":
> description: Imagination Technologies Ltd. (formerly MIPS
> Technologies Inc.)
Yes, "mti" is also marked as Imagination Technologies Ltd, but I
doubt we should use "mti" prefix for something what has been developed
after Image Tech acquired MIPS Tech. What is the point in having the
"img," prefix then?
Rob, your opinion?
-Serge(y)
>
> So I think it's OK.
>
> Gregory
>
> >
> > -Serge(y)
> >
> >>
> >> reg:
> >> maxItems: 1
> >> --
> >> 2.40.1
> >>
>
> --
> Gregory Clement, Bootlin
> Embedded Linux and Kernel engineering
> http://bootlin.com
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 05/11] dt-bindings: mips: cpu: Add I-Class I6500 Multiprocessor Core
2023-10-05 14:51 ` Gregory CLEMENT
2023-10-05 15:23 ` Serge Semin
@ 2023-10-06 10:48 ` Arnd Bergmann
2023-10-06 16:40 ` Rob Herring
1 sibling, 1 reply; 53+ messages in thread
From: Arnd Bergmann @ 2023-10-06 10:48 UTC (permalink / raw)
To: Gregory Clement, Serge Semin
Cc: Phil Mathieu-Daudé,
Paul Burton, Thomas Bogendoerfer, linux-mips, Rob Herring,
Krzysztof Kozlowski, devicetree, linux-kernel,
Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni
On Thu, Oct 5, 2023, at 16:51, Gregory CLEMENT wrote:
>> On Wed, Oct 04, 2023 at 06:10:32PM +0200, Gregory CLEMENT wrote:
>>> The MIPS Warrior I-class I6500 was announced by Imagination
>>> Technologies in 2016 and is used in the Mobileye SoC EyeQ5.
>>>
>>> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
>>> ---
>>> Documentation/devicetree/bindings/mips/cpus.yaml | 1 +
>>> 1 file changed, 1 insertion(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/mips/cpus.yaml b/Documentation/devicetree/bindings/mips/cpus.yaml
>>> index cf382dea3922..87fd2842ba68 100644
>>> --- a/Documentation/devicetree/bindings/mips/cpus.yaml
>>> +++ b/Documentation/devicetree/bindings/mips/cpus.yaml
>>> @@ -39,6 +39,7 @@ properties:
>>> - mti,mips24KEc
>>> - mti,mips14KEc
>>> - mti,mips14Kc
>>
>>> + - mti,i6500
>>
>> Since the CPU core vendor is Imagination Technologies thus it would
>> be more appropriate to have the "img," prefix. Wouldn't it?
>
> According to Documentation/devicetree/bindings/vendor-prefixes.yaml
>
> "^mti,.*":
> description: Imagination Technologies Ltd. (formerly MIPS
> Technologies Inc.)
>
> So I think it's OK.
I don't see any good solution, they changed their name and
ownership too many times. I would actually revert back the
description here to "MIPS Technologies Inc" instead of trying
to keep track of what they currently call themselves.
Since we already have both the 'mips,' and 'mti,' vendow
names for the 14Kc, 14KEc and 24KEc parts, maybe we can
just go back to 'mips,' for all cores past the mti era
rather than trying to date and geolocate each of the
classic cores as one of 'mti', 'img', 'wavecomp', 'tallwood',
'mips' 'cipunited' etc.
Arnd
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 11/11] MAINTAINERS: Add entry for Mobileye MIPS SoCs
2023-10-04 16:10 ` [PATCH 11/11] MAINTAINERS: Add entry for Mobileye MIPS SoCs Gregory CLEMENT
@ 2023-10-06 11:11 ` Arnd Bergmann
2023-10-09 15:06 ` Gregory CLEMENT
0 siblings, 1 reply; 53+ messages in thread
From: Arnd Bergmann @ 2023-10-06 11:11 UTC (permalink / raw)
To: Gregory Clement, Paul Burton, Thomas Bogendoerfer, linux-mips,
Rob Herring, Krzysztof Kozlowski, devicetree, linux-kernel
Cc: Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni
On Wed, Oct 4, 2023, at 18:10, Gregory CLEMENT wrote:
> Add Vlad, Théo and myself as co-maintainers for the Mobileye MIPS
> SoCs.
>
> Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
> ---
> MAINTAINERS | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 90f13281d297..6aedeab5f07c 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -14423,6 +14423,18 @@ W: http://palosaari.fi/linux/
> Q: http://patchwork.linuxtv.org/project/linux-media/list/
> F: drivers/media/dvb-frontends/mn88473*
>
> +MOBILEYE MIPS SOCS
> +M: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
> +M: Gregory CLEMENT <gregory.clement@bootlin.com>
> +M: Théo Lebrun <theo.lebrun@bootlin.com>
Is Vladimir's @intel.com address going to stay valid in the
future? I would have assumed that after the spin-out, all
remaining developers working on eyeq would go back to a
mobileye address.
Arnd
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 09/11] MIPS: mobileye: Add EPM5 device tree
2023-10-04 16:10 ` [PATCH 09/11] MIPS: mobileye: Add EPM5 device tree Gregory CLEMENT
@ 2023-10-06 11:18 ` Arnd Bergmann
2023-10-09 14:51 ` Gregory CLEMENT
0 siblings, 1 reply; 53+ messages in thread
From: Arnd Bergmann @ 2023-10-06 11:18 UTC (permalink / raw)
To: Gregory Clement, Paul Burton, Thomas Bogendoerfer, linux-mips,
Rob Herring, Krzysztof Kozlowski, devicetree, linux-kernel
Cc: Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni
On Wed, Oct 4, 2023, at 18:10, Gregory CLEMENT wrote:
> +
> + chosen {
> + bootargs = "cca=5 earlycon console=ttyAMA2 ddr32_alias=0x40000000";
> + stdout-path = "serial2:115200n8";
> + };
> +
The bootargs should not be needed here, at least most of them:
- no need to set both console= and the stdout-path if you have
earlycon support
- ddr32_alias=0x40000000 sounds like something that should be
part of the dtb elsewhere and not require a command line argument.
I assume this is needed to even build?
- For cca=, it looks like this is intended to be autodetected from
the c0_config register. Does that not work for you for some reason?
Arnd
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 03/11] MIPS: support RAM beyond 32-bit
2023-10-04 16:10 ` [PATCH 03/11] MIPS: support RAM beyond 32-bit Gregory CLEMENT
@ 2023-10-06 11:21 ` Arnd Bergmann
2023-10-07 20:14 ` Jiaxun Yang
1 sibling, 0 replies; 53+ messages in thread
From: Arnd Bergmann @ 2023-10-06 11:21 UTC (permalink / raw)
To: Gregory Clement, Paul Burton, Thomas Bogendoerfer, linux-mips,
Rob Herring, Krzysztof Kozlowski, devicetree, linux-kernel
Cc: Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni
On Wed, Oct 4, 2023, at 18:10, Gregory CLEMENT wrote:
> From: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
>
> Support platforms where RAM is mapped beyond 32-bit.
>
> The kernel parameter ddr32_alias allows to setup the alias to point
> outside the first 4 GB of memory.
>
> Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
This needs a better explanation, and probably a rewrite.
Having to pass the memory address on the command line does
not sound like an appropriate way to boot the kernel, so
I think either this needs to be detected from the running kernel
itself, or passed through DT.
Arnd
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 10/11] MIPS: generic: Add support for Mobileye EyeQ5
2023-10-05 0:08 ` kernel test robot
@ 2023-10-06 14:47 ` Arnd Bergmann
2023-10-09 14:58 ` Gregory CLEMENT
0 siblings, 1 reply; 53+ messages in thread
From: Arnd Bergmann @ 2023-10-06 14:47 UTC (permalink / raw)
To: kernel test robot, Gregory Clement, Paul Burton,
Thomas Bogendoerfer, linux-mips, Rob Herring,
Krzysztof Kozlowski, devicetree, linux-kernel
Cc: oe-kbuild-all, Vladimir Kondratiev, Tawfik Bayouk,
Alexandre Belloni, Théo Lebrun, Thomas Petazzoni,
Chanho Min, Greg Kroah-Hartman, Russell King
On Thu, Oct 5, 2023, at 02:08, kernel test robot wrote:
> Hi Gregory,
>
> kernel test robot noticed the following build errors:
>
> [auto build test ERROR on robh/for-next]
> [also build test ERROR on lee-mfd/for-mfd-next linus/master v6.6-rc4
> next-20231004]
> [cannot apply to lee-mfd/for-mfd-fixes]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch#_base_tree_information]
> If you fix the issue in a separate patch/commit (i.e. not just a new
> version of
> the same patch/commit), kindly add following tags
> | Reported-by: kernel test robot <lkp@intel.com>
> | Closes:
> https://lore.kernel.org/oe-kbuild-all/202310050726.GDpZbMDO-lkp@intel.com/
>
> All error/warnings (new ones prefixed by >>):
>
> drivers/tty/serial/amba-pl011.c: In function 'pl011_sgbuf_init':
>>> drivers/tty/serial/amba-pl011.c:380:30: error: implicit declaration of function 'phys_to_page'; did you mean 'pfn_to_page'? [-Werror=implicit-function-declaration]
> 380 | sg_set_page(&sg->sg, phys_to_page(dma_addr),
> | ^~~~~~~~~~~~
> | pfn_to_page
I discussed this with Gregory on IRC, and prototyped a
possible fix. The issue was caused by the use of coherent memory
for the buffer and passing that into a scatterlist structure.
Since there is no guarantee that the memory returned by
dma_alloc_coherent() is associated with a 'struct page', using
the architecture specific phys_to_page() is wrong, but using
virt_to_page() would be as well.
An easy workaround is to stop using sg lists altogether and
just use the *_single() functions instead. This also simplifies
the code a bit since the scatterlists in this driver always have
only one entry anyway.
Fixes: cb06ff102e2d7 ("ARM: PL011: Add support for Rx DMA buffer polling.")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index 0667e045ccb31..a3d92a91ff17d 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -219,8 +219,9 @@ static struct vendor_data vendor_st = {
/* Deals with DMA transactions */
struct pl011_sgbuf {
- struct scatterlist sg;
- char *buf;
+ dma_addr_t dma;
+ size_t len;
+ char *buf;
};
struct pl011_dmarx_data {
@@ -241,7 +242,8 @@ struct pl011_dmarx_data {
struct pl011_dmatx_data {
struct dma_chan *chan;
- struct scatterlist sg;
+ dma_addr_t dma;
+ size_t len;
char *buf;
bool queued;
};
@@ -369,18 +371,11 @@ static int pl011_fifo_to_tty(struct uart_amba_port *uap)
static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
enum dma_data_direction dir)
{
- dma_addr_t dma_addr;
-
- sg->buf = dma_alloc_coherent(chan->device->dev,
- PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL);
+ sg->buf = dma_alloc_coherent(chan->device->dev, PL011_DMA_BUFFER_SIZE,
+ &sg->dma, GFP_KERNEL);
if (!sg->buf)
return -ENOMEM;
-
- sg_init_table(&sg->sg, 1);
- sg_set_page(&sg->sg, phys_to_page(dma_addr),
- PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr));
- sg_dma_address(&sg->sg) = dma_addr;
- sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE;
+ sg->len = PL011_DMA_BUFFER_SIZE;
return 0;
}
@@ -390,8 +385,7 @@ static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
{
if (sg->buf) {
dma_free_coherent(chan->device->dev,
- PL011_DMA_BUFFER_SIZE, sg->buf,
- sg_dma_address(&sg->sg));
+ PL011_DMA_BUFFER_SIZE, sg->buf, sg->dma);
}
}
@@ -552,8 +546,8 @@ static void pl011_dma_tx_callback(void *data)
uart_port_lock_irqsave(&uap->port, &flags);
if (uap->dmatx.queued)
- dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
- DMA_TO_DEVICE);
+ dma_unmap_single(dmatx->chan->device->dev, dmatx->dma,
+ dmatx->len, DMA_TO_DEVICE);
dmacr = uap->dmacr;
uap->dmacr = dmacr & ~UART011_TXDMAE;
@@ -639,18 +633,19 @@ static int pl011_dma_tx_refill(struct uart_amba_port *uap)
memcpy(&dmatx->buf[first], &xmit->buf[0], second);
}
- dmatx->sg.length = count;
-
- if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
+ dmatx->len = count;
+ dmatx->dma = dma_map_single(dma_dev->dev, dmatx->buf, count,
+ DMA_TO_DEVICE);
+ if (dmatx->dma == DMA_MAPPING_ERROR) {
uap->dmatx.queued = false;
dev_dbg(uap->port.dev, "unable to map TX DMA\n");
return -EBUSY;
}
- desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV,
+ desc = dmaengine_prep_slave_single(chan, dmatx->dma, dmatx->len, DMA_MEM_TO_DEV,
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
if (!desc) {
- dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
+ dma_unmap_single(dma_dev->dev, dmatx->dma, dmatx->len, DMA_TO_DEVICE);
uap->dmatx.queued = false;
/*
* If DMA cannot be used right now, we complete this
@@ -813,8 +808,8 @@ __acquires(&uap->port.lock)
dmaengine_terminate_async(uap->dmatx.chan);
if (uap->dmatx.queued) {
- dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
- DMA_TO_DEVICE);
+ dma_unmap_single(uap->dmatx.chan->device->dev, uap->dmatx.dma,
+ uap->dmatx.len, DMA_TO_DEVICE);
uap->dmatx.queued = false;
uap->dmacr &= ~UART011_TXDMAE;
pl011_write(uap->dmacr, uap, REG_DMACR);
@@ -836,7 +831,7 @@ static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
/* Start the RX DMA job */
sgbuf = uap->dmarx.use_buf_b ?
&uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
- desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1,
+ desc = dmaengine_prep_slave_single(rxchan, sgbuf->dma, sgbuf->len,
DMA_DEV_TO_MEM,
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
/*
@@ -886,7 +881,7 @@ static void pl011_dma_rx_chars(struct uart_amba_port *uap,
if (uap->dmarx.poll_rate) {
/* The data can be taken by polling */
- dmataken = sgbuf->sg.length - dmarx->last_residue;
+ dmataken = sgbuf->len - dmarx->last_residue;
/* Recalculate the pending size */
if (pending >= dmataken)
pending -= dmataken;
@@ -911,7 +906,7 @@ static void pl011_dma_rx_chars(struct uart_amba_port *uap,
/* Reset the last_residue for Rx DMA poll */
if (uap->dmarx.poll_rate)
- dmarx->last_residue = sgbuf->sg.length;
+ dmarx->last_residue = sgbuf->len;
/*
* Only continue with trying to read the FIFO if all DMA chars have
@@ -969,7 +964,7 @@ static void pl011_dma_rx_irq(struct uart_amba_port *uap)
pl011_write(uap->dmacr, uap, REG_DMACR);
uap->dmarx.running = false;
- pending = sgbuf->sg.length - state.residue;
+ pending = sgbuf->len - state.residue;
BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
/* Then we terminate the transfer - we now know our residue */
dmaengine_terminate_all(rxchan);
@@ -1015,7 +1010,7 @@ static void pl011_dma_rx_callback(void *data)
* the DMA irq handler. So we check the residue here.
*/
rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
- pending = sgbuf->sg.length - state.residue;
+ pending = sgbuf->len - state.residue;
BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
/* Then we terminate the transfer - we now know our residue */
dmaengine_terminate_all(rxchan);
@@ -1074,7 +1069,7 @@ static void pl011_dma_rx_poll(struct timer_list *t)
sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
if (likely(state.residue < dmarx->last_residue)) {
- dmataken = sgbuf->sg.length - dmarx->last_residue;
+ dmataken = sgbuf->len - dmarx->last_residue;
size = dmarx->last_residue - state.residue;
dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
size);
@@ -1123,7 +1118,7 @@ static void pl011_dma_startup(struct uart_amba_port *uap)
return;
}
- sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
+ uap->dmatx.len = PL011_DMA_BUFFER_SIZE;
/* The DMA buffer is now the FIFO the TTY subsystem can use */
uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
@@ -1200,8 +1195,9 @@ static void pl011_dma_shutdown(struct uart_amba_port *uap)
/* In theory, this should already be done by pl011_dma_flush_buffer */
dmaengine_terminate_all(uap->dmatx.chan);
if (uap->dmatx.queued) {
- dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
- DMA_TO_DEVICE);
+ dma_unmap_single(uap->dmatx.chan->device->dev,
+ uap->dmatx.dma, uap->dmatx.len,
+ DMA_TO_DEVICE);
uap->dmatx.queued = false;
}
^ permalink raw reply related [flat|nested] 53+ messages in thread
* Re: [PATCH 04/11] dt-bindings: Add vendor prefix for Mobileye Vision Technologies Ltd.
2023-10-04 16:10 ` [PATCH 04/11] dt-bindings: Add vendor prefix for Mobileye Vision Technologies Ltd Gregory CLEMENT
2023-10-05 6:34 ` Philippe Mathieu-Daudé
@ 2023-10-06 16:32 ` Rob Herring
1 sibling, 0 replies; 53+ messages in thread
From: Rob Herring @ 2023-10-06 16:32 UTC (permalink / raw)
To: Gregory CLEMENT
Cc: Thomas Petazzoni, Rob Herring, Thomas Bogendoerfer,
Vladimir Kondratiev, Krzysztof Kozlowski, devicetree,
linux-kernel, Tawfik Bayouk, Paul Burton, Alexandre Belloni,
linux-mips, Théo Lebrun
On Wed, 04 Oct 2023 18:10:31 +0200, Gregory CLEMENT wrote:
> Mobileye Vision Technologies Ltd. is a company developing autonomous
> driving technologies and advanced driver-assistance systems (ADAS)
> including cameras, computer chips and software.
>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
> Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 05/11] dt-bindings: mips: cpu: Add I-Class I6500 Multiprocessor Core
2023-10-06 10:48 ` Arnd Bergmann
@ 2023-10-06 16:40 ` Rob Herring
2023-10-09 15:32 ` Gregory CLEMENT
0 siblings, 1 reply; 53+ messages in thread
From: Rob Herring @ 2023-10-06 16:40 UTC (permalink / raw)
To: Arnd Bergmann, Gregory Clement
Cc: Serge Semin, Phil Mathieu-Daudé,
Paul Burton, Thomas Bogendoerfer, linux-mips,
Krzysztof Kozlowski, devicetree, linux-kernel,
Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni
On Fri, Oct 06, 2023 at 12:48:03PM +0200, Arnd Bergmann wrote:
> On Thu, Oct 5, 2023, at 16:51, Gregory CLEMENT wrote:
> >> On Wed, Oct 04, 2023 at 06:10:32PM +0200, Gregory CLEMENT wrote:
> >>> The MIPS Warrior I-class I6500 was announced by Imagination
> >>> Technologies in 2016 and is used in the Mobileye SoC EyeQ5.
> >>>
> >>> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> >>> ---
> >>> Documentation/devicetree/bindings/mips/cpus.yaml | 1 +
> >>> 1 file changed, 1 insertion(+)
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/mips/cpus.yaml b/Documentation/devicetree/bindings/mips/cpus.yaml
> >>> index cf382dea3922..87fd2842ba68 100644
> >>> --- a/Documentation/devicetree/bindings/mips/cpus.yaml
> >>> +++ b/Documentation/devicetree/bindings/mips/cpus.yaml
> >>> @@ -39,6 +39,7 @@ properties:
> >>> - mti,mips24KEc
> >>> - mti,mips14KEc
> >>> - mti,mips14Kc
> >>
> >>> + - mti,i6500
> >>
> >> Since the CPU core vendor is Imagination Technologies thus it would
> >> be more appropriate to have the "img," prefix. Wouldn't it?
> >
> > According to Documentation/devicetree/bindings/vendor-prefixes.yaml
> >
> > "^mti,.*":
> > description: Imagination Technologies Ltd. (formerly MIPS
> > Technologies Inc.)
> >
> > So I think it's OK.
>
> I don't see any good solution, they changed their name and
> ownership too many times. I would actually revert back the
> description here to "MIPS Technologies Inc" instead of trying
> to keep track of what they currently call themselves.
>
> Since we already have both the 'mips,' and 'mti,' vendow
> names for the 14Kc, 14KEc and 24KEc parts, maybe we can
> just go back to 'mips,' for all cores past the mti era
> rather than trying to date and geolocate each of the
> classic cores as one of 'mti', 'img', 'wavecomp', 'tallwood',
> 'mips' 'cipunited' etc.
I would reserve 'mips' for anything common. Much like 'riscv' is only
for things based on RiscV specs/standards.
I would use 'img' here if we know this was designed/implemented by
Imagination.
Rob
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 06/11] dt-bindings: mips: Add bindings for Mobileye SoCs
2023-10-05 14:55 ` Gregory CLEMENT
@ 2023-10-06 16:50 ` Rob Herring
0 siblings, 0 replies; 53+ messages in thread
From: Rob Herring @ 2023-10-06 16:50 UTC (permalink / raw)
To: Gregory CLEMENT
Cc: Paul Burton, Thomas Bogendoerfer, linux-mips,
Krzysztof Kozlowski, devicetree, linux-kernel,
Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni
On Thu, Oct 05, 2023 at 04:55:08PM +0200, Gregory CLEMENT wrote:
> Hello Rob,
>
> > On Wed, Oct 4, 2023 at 11:11 AM Gregory CLEMENT
> > <gregory.clement@bootlin.com> wrote:
> >>
> >> Add the yaml bindings for Mobileye SoCs. Currently only EyeQ5 is
> >> supported
> >>
> >> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> >> ---
> >> .../devicetree/bindings/mips/mobileye.yaml | 36 +++++++++
> >> include/dt-bindings/soc/mobileye,eyeq5.h | 77 +++++++++++++++++++
> >> 2 files changed, 113 insertions(+)
> >> create mode 100644 Documentation/devicetree/bindings/mips/mobileye.yaml
> >> create mode 100644 include/dt-bindings/soc/mobileye,eyeq5.h
> >>
> >> diff --git a/Documentation/devicetree/bindings/mips/mobileye.yaml b/Documentation/devicetree/bindings/mips/mobileye.yaml
> >> new file mode 100644
> >> index 000000000000..f47767bc2c8f
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/mips/mobileye.yaml
> >> @@ -0,0 +1,36 @@
> >> +# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
> >
> > Use what checkpatch tells you.
>
> >From my point of view GPL-2.0-or-later is compatible with GPL-2.0-only,
> but OK I will do this.
GPL-2.0-only is compatible with GPL3, so why does that matter? And MIT
is compatible with BSD-2-Clause, but we don't include that.
Are we okay with GPLv4, v5, ...?
What I really care about is having a free-for-all and having a
proliferation of different licenses and combinations of licenses under
bindings. If everyone paid attention, then I wouldn't care. But they
don't and just copy code around. We already have a license mess with DT
headers and .dts files. Besides the copying problem, it is not hard to
find GPL only license included in dual or BSD/MIT only licensed .dts
files. Seems like an issue to me.
Rob
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 07/11] dt-bindings: mfd: syscon: Document EyeQ5 OLB
2023-10-04 16:10 ` [PATCH 07/11] dt-bindings: mfd: syscon: Document EyeQ5 OLB Gregory CLEMENT
@ 2023-10-06 16:54 ` Rob Herring
2023-10-09 15:49 ` Gregory CLEMENT
0 siblings, 1 reply; 53+ messages in thread
From: Rob Herring @ 2023-10-06 16:54 UTC (permalink / raw)
To: Gregory CLEMENT
Cc: Paul Burton, Thomas Bogendoerfer, linux-mips,
Krzysztof Kozlowski, devicetree, linux-kernel,
Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni
On Wed, Oct 04, 2023 at 06:10:34PM +0200, Gregory CLEMENT wrote:
> Document Mobileye EyeQ5 compatibles for OLB registers that are
> misceallanous SoC related registers.
typo.
Please state what OLB is and what kind of things are in this block. IOW,
convince me this is not just a skeleton placeholder until you add a
bunch of providers in a real binding.
>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
> Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
> index 8103154bbb52..70bc6e8d15ba 100644
> --- a/Documentation/devicetree/bindings/mfd/syscon.yaml
> +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
> @@ -53,6 +53,7 @@ properties:
> - mediatek,mt8135-pctl-a-syscfg
> - mediatek,mt8135-pctl-b-syscfg
> - mediatek,mt8365-syscfg
> + - mobileye,eyeq5-olb
> - microchip,lan966x-cpu-syscon
> - microchip,sparx5-cpu-syscon
> - mstar,msc313-pmsleep
> --
> 2.40.1
>
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 03/11] MIPS: support RAM beyond 32-bit
2023-10-04 16:10 ` [PATCH 03/11] MIPS: support RAM beyond 32-bit Gregory CLEMENT
2023-10-06 11:21 ` Arnd Bergmann
@ 2023-10-07 20:14 ` Jiaxun Yang
2023-10-09 15:59 ` Gregory CLEMENT
1 sibling, 1 reply; 53+ messages in thread
From: Jiaxun Yang @ 2023-10-07 20:14 UTC (permalink / raw)
To: Gregory CLEMENT, paulburton, Thomas Bogendoerfer, linux-mips,
Rob Herring, Krzysztof Kozlowski, devicetree, linux-kernel
Cc: Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni
在2023年10月4日十月 下午5:10，Gregory CLEMENT写道：
> From: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
>
> Support platforms where RAM is mapped beyond 32-bit.
>
> The kernel parameter ddr32_alias allows to setup the alias to point
> outside the first 4 GB of memory.
Are you trying to fix the problem that if kernel text is loaded in
XKPHYS there is no way to to set EBASE to that region?
The common practice for other 64bit MIPS system is to load kernel
in KSEG0 and add low 4G mirror with rest of the high memory to buddy
system. By doing this Kernel still have access to all memory beyond
32 bit, the only draw back is Kernel's text and data can't be relocted
beyond 32-bit.
Loading kernel into KSEG0 (i.e. with KBUILD_SYM32) have significant benefit
on performance, so I think you shouldn't try to load kernel into XKPHYS
without a good reason, but it might be helpful to add a BUG_ON at
CPS driver to handle such situation.
Btw: Is your target hardware publicly available? Folks at CIP United
are looking for EyeQ5 boards for a while, they are supporting MIPS R6
support at various projects.
Thanks
Jiaxun
>
> Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
> arch/mips/kernel/smp-cps.c | 12 +++++++++++-
> 1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
> index 47e76722a306..fcfb19487612 100644
> --- a/arch/mips/kernel/smp-cps.c
> +++ b/arch/mips/kernel/smp-cps.c
> @@ -34,6 +34,16 @@ static unsigned __init core_vpe_count(unsigned int
> cluster, unsigned core)
> return min(smp_max_threads, mips_cps_numvps(cluster, core));
> }
>
> +static int ddr32_alias;
> +
> +static int __init ddr32_alias_setup(char *str)
> +{
> + get_option(&str, &ddr32_alias);
> +
> + return 0;
> +}
> +early_param("ddr32_alias", ddr32_alias_setup);
> +
> /**
> * plat_core_entry - query reset vector for NMI/reset
> *
> @@ -52,7 +62,7 @@ static u32 plat_core_entry(void)
> {
> #if defined(CONFIG_USE_XKPHYS)
> return (UNCAC_ADDR(mips_cps_core_entry) & 0xffffffff)
> - | CM_GCR_Cx_RESET_BASE_MODE;
> + | ddr32_alias | CM_GCR_Cx_RESET_BASE_MODE;
> #else
> return CKSEG1ADDR((unsigned long)mips_cps_core_entry);
> #endif
> --
> 2.40.1
--
- Jiaxun
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 09/11] MIPS: mobileye: Add EPM5 device tree
2023-10-06 11:18 ` Arnd Bergmann
@ 2023-10-09 14:51 ` Gregory CLEMENT
0 siblings, 0 replies; 53+ messages in thread
From: Gregory CLEMENT @ 2023-10-09 14:51 UTC (permalink / raw)
To: Arnd Bergmann, Paul Burton, Thomas Bogendoerfer, linux-mips,
Rob Herring, Krzysztof Kozlowski, devicetree, linux-kernel
Cc: Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni
"Arnd Bergmann" <arnd@arndb.de> writes:
> On Wed, Oct 4, 2023, at 18:10, Gregory CLEMENT wrote:
>> +
>> + chosen {
>> + bootargs = "cca=5 earlycon console=ttyAMA2 ddr32_alias=0x40000000";
>> + stdout-path = "serial2:115200n8";
>> + };
>> +
>
> The bootargs should not be needed here, at least most of them:
>
> - no need to set both console= and the stdout-path if you have
> earlycon support
OK I keep stdout-path.
>
> - ddr32_alias=0x40000000 sounds like something that should be
> part of the dtb elsewhere and not require a command line argument.
> I assume this is needed to even build?
I will answer on the other email but in short I agree.
>
> - For cca=, it looks like this is intended to be autodetected from
> the c0_config register. Does that not work for you for some reason?
Indeed I checked and it it nost needed anymore, it is already set in
cps_smp_setup. I remove it.
Thanks,
Gregory
>
> Arnd
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 10/11] MIPS: generic: Add support for Mobileye EyeQ5
2023-10-06 14:47 ` Arnd Bergmann
@ 2023-10-09 14:58 ` Gregory CLEMENT
0 siblings, 0 replies; 53+ messages in thread
From: Gregory CLEMENT @ 2023-10-09 14:58 UTC (permalink / raw)
To: Arnd Bergmann, kernel test robot, Paul Burton,
Thomas Bogendoerfer, linux-mips, Rob Herring,
Krzysztof Kozlowski, devicetree, linux-kernel, Linus Walleij
Cc: oe-kbuild-all, Vladimir Kondratiev, Tawfik Bayouk,
Alexandre Belloni, Théo Lebrun, Thomas Petazzoni,
Chanho Min, Greg Kroah-Hartman, Russell King
Hello,
> On Thu, Oct 5, 2023, at 02:08, kernel test robot wrote:
>> Hi Gregory,
>>
>> kernel test robot noticed the following build errors:
>>
>> [auto build test ERROR on robh/for-next]
>> [also build test ERROR on lee-mfd/for-mfd-next linus/master v6.6-rc4
>> next-20231004]
>> [cannot apply to lee-mfd/for-mfd-fixes]
>> [If your patch is applied to the wrong git tree, kindly drop us a note.
>> And when submitting patch, we suggest to use '--base' as documented in
>> https://git-scm.com/docs/git-format-patch#_base_tree_information]
>
>
>> If you fix the issue in a separate patch/commit (i.e. not just a new
>> version of
>> the same patch/commit), kindly add following tags
>> | Reported-by: kernel test robot <lkp@intel.com>
>> | Closes:
>> https://lore.kernel.org/oe-kbuild-all/202310050726.GDpZbMDO-lkp@intel.com/
>>
>> All error/warnings (new ones prefixed by >>):
>>
>> drivers/tty/serial/amba-pl011.c: In function 'pl011_sgbuf_init':
>>>> drivers/tty/serial/amba-pl011.c:380:30: error: implicit declaration of function 'phys_to_page'; did you mean 'pfn_to_page'? [-Werror=implicit-function-declaration]
>> 380 | sg_set_page(&sg->sg, phys_to_page(dma_addr),
>> | ^~~~~~~~~~~~
>> | pfn_to_page
>
> I discussed this with Gregory on IRC, and prototyped a
> possible fix. The issue was caused by the use of coherent memory
> for the buffer and passing that into a scatterlist structure.
>
> Since there is no guarantee that the memory returned by
> dma_alloc_coherent() is associated with a 'struct page', using
> the architecture specific phys_to_page() is wrong, but using
> virt_to_page() would be as well.
>
> An easy workaround is to stop using sg lists altogether and
> just use the *_single() functions instead. This also simplifies
> the code a bit since the scatterlists in this driver always have
> only one entry anyway.
>
> Fixes: cb06ff102e2d7 ("ARM: PL011: Add support for Rx DMA buffer polling.")
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
I tested the following patch and it didn't introduce any regression and
when using the same defconfig than the bot there is no more any error.
So we can add,
Tested-by: Gregory CLEMENT <gregory.clement@bootlin.com>
However, we don't use DMA on our platform for UART so the tests are
limited.
Linus; I know that you have a couple of boards that used the same UART
controller. By any chance do you have some of them with DMA support that
you could test ?
Gregory
PS: we are going to send series of clean-up and improvement for the
pl011, but there are not mandatory for using the EyeQ5 platform. We
hope being able to send them soon.
>
> diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
> index 0667e045ccb31..a3d92a91ff17d 100644
> --- a/drivers/tty/serial/amba-pl011.c
> +++ b/drivers/tty/serial/amba-pl011.c
> @@ -219,8 +219,9 @@ static struct vendor_data vendor_st = {
> /* Deals with DMA transactions */
>
> struct pl011_sgbuf {
> - struct scatterlist sg;
> - char *buf;
> + dma_addr_t dma;
> + size_t len;
> + char *buf;
> };
>
> struct pl011_dmarx_data {
> @@ -241,7 +242,8 @@ struct pl011_dmarx_data {
>
> struct pl011_dmatx_data {
> struct dma_chan *chan;
> - struct scatterlist sg;
> + dma_addr_t dma;
> + size_t len;
> char *buf;
> bool queued;
> };
> @@ -369,18 +371,11 @@ static int pl011_fifo_to_tty(struct uart_amba_port *uap)
> static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
> enum dma_data_direction dir)
> {
> - dma_addr_t dma_addr;
> -
> - sg->buf = dma_alloc_coherent(chan->device->dev,
> - PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL);
> + sg->buf = dma_alloc_coherent(chan->device->dev, PL011_DMA_BUFFER_SIZE,
> + &sg->dma, GFP_KERNEL);
> if (!sg->buf)
> return -ENOMEM;
> -
> - sg_init_table(&sg->sg, 1);
> - sg_set_page(&sg->sg, phys_to_page(dma_addr),
> - PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr));
> - sg_dma_address(&sg->sg) = dma_addr;
> - sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE;
> + sg->len = PL011_DMA_BUFFER_SIZE;
>
> return 0;
> }
> @@ -390,8 +385,7 @@ static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
> {
> if (sg->buf) {
> dma_free_coherent(chan->device->dev,
> - PL011_DMA_BUFFER_SIZE, sg->buf,
> - sg_dma_address(&sg->sg));
> + PL011_DMA_BUFFER_SIZE, sg->buf, sg->dma);
> }
> }
>
> @@ -552,8 +546,8 @@ static void pl011_dma_tx_callback(void *data)
>
> uart_port_lock_irqsave(&uap->port, &flags);
> if (uap->dmatx.queued)
> - dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
> - DMA_TO_DEVICE);
> + dma_unmap_single(dmatx->chan->device->dev, dmatx->dma,
> + dmatx->len, DMA_TO_DEVICE);
>
> dmacr = uap->dmacr;
> uap->dmacr = dmacr & ~UART011_TXDMAE;
> @@ -639,18 +633,19 @@ static int pl011_dma_tx_refill(struct uart_amba_port *uap)
> memcpy(&dmatx->buf[first], &xmit->buf[0], second);
> }
>
> - dmatx->sg.length = count;
> -
> - if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
> + dmatx->len = count;
> + dmatx->dma = dma_map_single(dma_dev->dev, dmatx->buf, count,
> + DMA_TO_DEVICE);
> + if (dmatx->dma == DMA_MAPPING_ERROR) {
> uap->dmatx.queued = false;
> dev_dbg(uap->port.dev, "unable to map TX DMA\n");
> return -EBUSY;
> }
>
> - desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV,
> + desc = dmaengine_prep_slave_single(chan, dmatx->dma, dmatx->len, DMA_MEM_TO_DEV,
> DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
> if (!desc) {
> - dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
> + dma_unmap_single(dma_dev->dev, dmatx->dma, dmatx->len, DMA_TO_DEVICE);
> uap->dmatx.queued = false;
> /*
> * If DMA cannot be used right now, we complete this
> @@ -813,8 +808,8 @@ __acquires(&uap->port.lock)
> dmaengine_terminate_async(uap->dmatx.chan);
>
> if (uap->dmatx.queued) {
> - dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
> - DMA_TO_DEVICE);
> + dma_unmap_single(uap->dmatx.chan->device->dev, uap->dmatx.dma,
> + uap->dmatx.len, DMA_TO_DEVICE);
> uap->dmatx.queued = false;
> uap->dmacr &= ~UART011_TXDMAE;
> pl011_write(uap->dmacr, uap, REG_DMACR);
> @@ -836,7 +831,7 @@ static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
> /* Start the RX DMA job */
> sgbuf = uap->dmarx.use_buf_b ?
> &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
> - desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1,
> + desc = dmaengine_prep_slave_single(rxchan, sgbuf->dma, sgbuf->len,
> DMA_DEV_TO_MEM,
> DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
> /*
> @@ -886,7 +881,7 @@ static void pl011_dma_rx_chars(struct uart_amba_port *uap,
>
> if (uap->dmarx.poll_rate) {
> /* The data can be taken by polling */
> - dmataken = sgbuf->sg.length - dmarx->last_residue;
> + dmataken = sgbuf->len - dmarx->last_residue;
> /* Recalculate the pending size */
> if (pending >= dmataken)
> pending -= dmataken;
> @@ -911,7 +906,7 @@ static void pl011_dma_rx_chars(struct uart_amba_port *uap,
>
> /* Reset the last_residue for Rx DMA poll */
> if (uap->dmarx.poll_rate)
> - dmarx->last_residue = sgbuf->sg.length;
> + dmarx->last_residue = sgbuf->len;
>
> /*
> * Only continue with trying to read the FIFO if all DMA chars have
> @@ -969,7 +964,7 @@ static void pl011_dma_rx_irq(struct uart_amba_port *uap)
> pl011_write(uap->dmacr, uap, REG_DMACR);
> uap->dmarx.running = false;
>
> - pending = sgbuf->sg.length - state.residue;
> + pending = sgbuf->len - state.residue;
> BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
> /* Then we terminate the transfer - we now know our residue */
> dmaengine_terminate_all(rxchan);
> @@ -1015,7 +1010,7 @@ static void pl011_dma_rx_callback(void *data)
> * the DMA irq handler. So we check the residue here.
> */
> rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
> - pending = sgbuf->sg.length - state.residue;
> + pending = sgbuf->len - state.residue;
> BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
> /* Then we terminate the transfer - we now know our residue */
> dmaengine_terminate_all(rxchan);
> @@ -1074,7 +1069,7 @@ static void pl011_dma_rx_poll(struct timer_list *t)
> sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
> rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
> if (likely(state.residue < dmarx->last_residue)) {
> - dmataken = sgbuf->sg.length - dmarx->last_residue;
> + dmataken = sgbuf->len - dmarx->last_residue;
> size = dmarx->last_residue - state.residue;
> dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
> size);
> @@ -1123,7 +1118,7 @@ static void pl011_dma_startup(struct uart_amba_port *uap)
> return;
> }
>
> - sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
> + uap->dmatx.len = PL011_DMA_BUFFER_SIZE;
>
> /* The DMA buffer is now the FIFO the TTY subsystem can use */
> uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
> @@ -1200,8 +1195,9 @@ static void pl011_dma_shutdown(struct uart_amba_port *uap)
> /* In theory, this should already be done by pl011_dma_flush_buffer */
> dmaengine_terminate_all(uap->dmatx.chan);
> if (uap->dmatx.queued) {
> - dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
> - DMA_TO_DEVICE);
> + dma_unmap_single(uap->dmatx.chan->device->dev,
> + uap->dmatx.dma, uap->dmatx.len,
> + DMA_TO_DEVICE);
> uap->dmatx.queued = false;
> }
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 11/11] MAINTAINERS: Add entry for Mobileye MIPS SoCs
2023-10-06 11:11 ` Arnd Bergmann
@ 2023-10-09 15:06 ` Gregory CLEMENT
0 siblings, 0 replies; 53+ messages in thread
From: Gregory CLEMENT @ 2023-10-09 15:06 UTC (permalink / raw)
To: Arnd Bergmann, Paul Burton, Thomas Bogendoerfer, linux-mips,
Rob Herring, Krzysztof Kozlowski, devicetree, linux-kernel
Cc: Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni
"Arnd Bergmann" <arnd@arndb.de> writes:
> On Wed, Oct 4, 2023, at 18:10, Gregory CLEMENT wrote:
>> Add Vlad, Théo and myself as co-maintainers for the Mobileye MIPS
>> SoCs.
>>
>> Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
>> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
>> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
>> ---
>> MAINTAINERS | 12 ++++++++++++
>> 1 file changed, 12 insertions(+)
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 90f13281d297..6aedeab5f07c 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -14423,6 +14423,18 @@ W: http://palosaari.fi/linux/
>> Q: http://patchwork.linuxtv.org/project/linux-media/list/
>> F: drivers/media/dvb-frontends/mn88473*
>>
>> +MOBILEYE MIPS SOCS
>> +M: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
>> +M: Gregory CLEMENT <gregory.clement@bootlin.com>
>> +M: Théo Lebrun <theo.lebrun@bootlin.com>
>
> Is Vladimir's @intel.com address going to stay valid in the
> future? I would have assumed that after the spin-out, all
> remaining developers working on eyeq would go back to a
> mobileye address.
Until recently it was an intel address but now the mobileye one is
available, I will update it.
Thanks,
Gregory
>
> Arnd
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 05/11] dt-bindings: mips: cpu: Add I-Class I6500 Multiprocessor Core
2023-10-06 16:40 ` Rob Herring
@ 2023-10-09 15:32 ` Gregory CLEMENT
2023-10-09 18:48 ` Arnd Bergmann
2023-10-10 10:13 ` Serge Semin
0 siblings, 2 replies; 53+ messages in thread
From: Gregory CLEMENT @ 2023-10-09 15:32 UTC (permalink / raw)
To: Rob Herring, Arnd Bergmann
Cc: Serge Semin, Phil Mathieu-Daudé,
Paul Burton, Thomas Bogendoerfer, linux-mips,
Krzysztof Kozlowski, devicetree, linux-kernel,
Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni
Rob Herring <robh@kernel.org> writes:
> On Fri, Oct 06, 2023 at 12:48:03PM +0200, Arnd Bergmann wrote:
>> On Thu, Oct 5, 2023, at 16:51, Gregory CLEMENT wrote:
>> >> On Wed, Oct 04, 2023 at 06:10:32PM +0200, Gregory CLEMENT wrote:
>> >>> The MIPS Warrior I-class I6500 was announced by Imagination
>> >>> Technologies in 2016 and is used in the Mobileye SoC EyeQ5.
>> >>>
>> >>> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
>> >>> ---
>> >>> Documentation/devicetree/bindings/mips/cpus.yaml | 1 +
>> >>> 1 file changed, 1 insertion(+)
>> >>>
>> >>> diff --git a/Documentation/devicetree/bindings/mips/cpus.yaml b/Documentation/devicetree/bindings/mips/cpus.yaml
>> >>> index cf382dea3922..87fd2842ba68 100644
>> >>> --- a/Documentation/devicetree/bindings/mips/cpus.yaml
>> >>> +++ b/Documentation/devicetree/bindings/mips/cpus.yaml
>> >>> @@ -39,6 +39,7 @@ properties:
>> >>> - mti,mips24KEc
>> >>> - mti,mips14KEc
>> >>> - mti,mips14Kc
>> >>
>> >>> + - mti,i6500
>> >>
>> >> Since the CPU core vendor is Imagination Technologies thus it would
>> >> be more appropriate to have the "img," prefix. Wouldn't it?
>> >
>> > According to Documentation/devicetree/bindings/vendor-prefixes.yaml
>> >
>> > "^mti,.*":
>> > description: Imagination Technologies Ltd. (formerly MIPS
>> > Technologies Inc.)
>> >
>> > So I think it's OK.
>>
>> I don't see any good solution, they changed their name and
>> ownership too many times. I would actually revert back the
>> description here to "MIPS Technologies Inc" instead of trying
>> to keep track of what they currently call themselves.
>>
>> Since we already have both the 'mips,' and 'mti,' vendow
>> names for the 14Kc, 14KEc and 24KEc parts, maybe we can
>> just go back to 'mips,' for all cores past the mti era
>> rather than trying to date and geolocate each of the
>> classic cores as one of 'mti', 'img', 'wavecomp', 'tallwood',
>> 'mips' 'cipunited' etc.
>
> I would reserve 'mips' for anything common. Much like 'riscv' is only
> for things based on RiscV specs/standards.
>
> I would use 'img' here if we know this was designed/implemented by
> Imagination.
If there is no objection I will use 'img' then.
Gregory
>
> Rob
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 07/11] dt-bindings: mfd: syscon: Document EyeQ5 OLB
2023-10-06 16:54 ` Rob Herring
@ 2023-10-09 15:49 ` Gregory CLEMENT
0 siblings, 0 replies; 53+ messages in thread
From: Gregory CLEMENT @ 2023-10-09 15:49 UTC (permalink / raw)
To: Rob Herring
Cc: Paul Burton, Thomas Bogendoerfer, linux-mips,
Krzysztof Kozlowski, devicetree, linux-kernel,
Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni
Rob Herring <robh@kernel.org> writes:
> On Wed, Oct 04, 2023 at 06:10:34PM +0200, Gregory CLEMENT wrote:
>> Document Mobileye EyeQ5 compatibles for OLB registers that are
>> misceallanous SoC related registers.
>
> typo.
>
> Please state what OLB is and what kind of things are in this block. IOW,
> convince me this is not just a skeleton placeholder until you add a
> bunch of providers in a real binding.
I understand your concern. First OLB stands for Other Logic Block which
does not say much about it!
It is used to expose SoC specific configuration such as for example
reset, clock or pinctrl. We have a few series nearly ready to be send to
add support for them, each of them will use this block. So declaring
this block since the beginning avoid to have dependencies between these
series and they will only depend of this current initial series.
Is it OK for you ?
Besides fixing the typo I can add the following explanation to the
commit log: "It is used to expose SoC specific configuration such as for
example reset, clock or pinctrl"
Gregory
>
>>
>> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
>> ---
>> Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
>> index 8103154bbb52..70bc6e8d15ba 100644
>> --- a/Documentation/devicetree/bindings/mfd/syscon.yaml
>> +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
>> @@ -53,6 +53,7 @@ properties:
>> - mediatek,mt8135-pctl-a-syscfg
>> - mediatek,mt8135-pctl-b-syscfg
>> - mediatek,mt8365-syscfg
>> + - mobileye,eyeq5-olb
>> - microchip,lan966x-cpu-syscon
>> - microchip,sparx5-cpu-syscon
>> - mstar,msc313-pmsleep
>> --
>> 2.40.1
>>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 03/11] MIPS: support RAM beyond 32-bit
2023-10-07 20:14 ` Jiaxun Yang
@ 2023-10-09 15:59 ` Gregory CLEMENT
2023-10-10 8:55 ` Jiaxun Yang
0 siblings, 1 reply; 53+ messages in thread
From: Gregory CLEMENT @ 2023-10-09 15:59 UTC (permalink / raw)
To: Jiaxun Yang, paulburton, Thomas Bogendoerfer, linux-mips,
Rob Herring, Krzysztof Kozlowski, devicetree, linux-kernel
Cc: Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni
Hello Jiaxun,
> 在2023年10月4日十月 下午5:10，Gregory CLEMENT写道：
>> From: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
>>
>> Support platforms where RAM is mapped beyond 32-bit.
>>
>> The kernel parameter ddr32_alias allows to setup the alias to point
>> outside the first 4 GB of memory.
>
> Are you trying to fix the problem that if kernel text is loaded in
> XKPHYS there is no way to to set EBASE to that region?
Yes that exactly we try to fix.
>
> The common practice for other 64bit MIPS system is to load kernel
> in KSEG0 and add low 4G mirror with rest of the high memory to buddy
> system. By doing this Kernel still have access to all memory beyond
> 32 bit, the only draw back is Kernel's text and data can't be relocted
> beyond 32-bit.
>
> Loading kernel into KSEG0 (i.e. with KBUILD_SYM32) have significant benefit
> on performance, so I think you shouldn't try to load kernel into XKPHYS
> without a good reason, but it might be helpful to add a BUG_ON at
> CPS driver to handle such situation.
I guess that being in KSEG0 allows to use shorter pointer. But in our
case the RAM is physically connected beyond 32bits, so it is not
accessible in KSEG0.
>
> Btw: Is your target hardware publicly available? Folks at CIP United
> are looking for EyeQ5 boards for a while, they are supporting MIPS R6
> support at various projects.
We use evaluation boards and I don't know if they are publicly
available.
Gregory
>
> Thanks
> Jiaxun
>
>>
>> Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
>> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
>> ---
>> arch/mips/kernel/smp-cps.c | 12 +++++++++++-
>> 1 file changed, 11 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
>> index 47e76722a306..fcfb19487612 100644
>> --- a/arch/mips/kernel/smp-cps.c
>> +++ b/arch/mips/kernel/smp-cps.c
>> @@ -34,6 +34,16 @@ static unsigned __init core_vpe_count(unsigned int
>> cluster, unsigned core)
>> return min(smp_max_threads, mips_cps_numvps(cluster, core));
>> }
>>
>> +static int ddr32_alias;
>> +
>> +static int __init ddr32_alias_setup(char *str)
>> +{
>> + get_option(&str, &ddr32_alias);
>> +
>> + return 0;
>> +}
>> +early_param("ddr32_alias", ddr32_alias_setup);
>> +
>> /**
>> * plat_core_entry - query reset vector for NMI/reset
>> *
>> @@ -52,7 +62,7 @@ static u32 plat_core_entry(void)
>> {
>> #if defined(CONFIG_USE_XKPHYS)
>> return (UNCAC_ADDR(mips_cps_core_entry) & 0xffffffff)
>> - | CM_GCR_Cx_RESET_BASE_MODE;
>> + | ddr32_alias | CM_GCR_Cx_RESET_BASE_MODE;
>> #else
>> return CKSEG1ADDR((unsigned long)mips_cps_core_entry);
>> #endif
>> --
>> 2.40.1
>
> --
> - Jiaxun
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 05/11] dt-bindings: mips: cpu: Add I-Class I6500 Multiprocessor Core
2023-10-09 15:32 ` Gregory CLEMENT
@ 2023-10-09 18:48 ` Arnd Bergmann
2023-10-10 10:13 ` Serge Semin
1 sibling, 0 replies; 53+ messages in thread
From: Arnd Bergmann @ 2023-10-09 18:48 UTC (permalink / raw)
To: Gregory Clement, Rob Herring
Cc: Serge Semin, Phil Mathieu-Daudé,
Paul Burton, Thomas Bogendoerfer, linux-mips,
Krzysztof Kozlowski, devicetree, linux-kernel,
Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni
On Mon, Oct 9, 2023, at 17:32, Gregory CLEMENT wrote:
> Rob Herring <robh@kernel.org> writes:
>> On Fri, Oct 06, 2023 at 12:48:03PM +0200, Arnd Bergmann wrote:
>>> On Thu, Oct 5, 2023, at 16:51, Gregory CLEMENT wrote:
>>>
>>> I don't see any good solution, they changed their name and
>>> ownership too many times. I would actually revert back the
>>> description here to "MIPS Technologies Inc" instead of trying
>>> to keep track of what they currently call themselves.
>>>
>>> Since we already have both the 'mips,' and 'mti,' vendow
>>> names for the 14Kc, 14KEc and 24KEc parts, maybe we can
>>> just go back to 'mips,' for all cores past the mti era
>>> rather than trying to date and geolocate each of the
>>> classic cores as one of 'mti', 'img', 'wavecomp', 'tallwood',
>>> 'mips' 'cipunited' etc.
>>
>> I would reserve 'mips' for anything common. Much like 'riscv' is only
>> for things based on RiscV specs/standards.
>>
>> I would use 'img' here if we know this was designed/implemented by
>> Imagination.
>
> If there is no objection I will use 'img' then.
Ok, let's do that then. With this modification:
Acked-by: Arnd Bergmann <arnd@arndb.de>
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 03/11] MIPS: support RAM beyond 32-bit
2023-10-09 15:59 ` Gregory CLEMENT
@ 2023-10-10 8:55 ` Jiaxun Yang
2023-10-11 14:46 ` Gregory CLEMENT
0 siblings, 1 reply; 53+ messages in thread
From: Jiaxun Yang @ 2023-10-10 8:55 UTC (permalink / raw)
To: Gregory CLEMENT, paulburton, Thomas Bogendoerfer, linux-mips,
Rob Herring, Krzysztof Kozlowski, devicetree, linux-kernel
Cc: Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni
在2023年10月9日十月 下午4:59，Gregory CLEMENT写道：
> Hello Jiaxun,
>
>> 在2023年10月4日十月 下午5:10，Gregory CLEMENT写道：
>>> From: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
>>>
>>> Support platforms where RAM is mapped beyond 32-bit.
>>>
>>> The kernel parameter ddr32_alias allows to setup the alias to point
>>> outside the first 4 GB of memory.
>>
>> Are you trying to fix the problem that if kernel text is loaded in
>> XKPHYS there is no way to to set EBASE to that region?
>
> Yes that exactly we try to fix.
>
>>
>> The common practice for other 64bit MIPS system is to load kernel
>> in KSEG0 and add low 4G mirror with rest of the high memory to buddy
>> system. By doing this Kernel still have access to all memory beyond
>> 32 bit, the only draw back is Kernel's text and data can't be relocted
>> beyond 32-bit.
>>
>> Loading kernel into KSEG0 (i.e. with KBUILD_SYM32) have significant benefit
>> on performance, so I think you shouldn't try to load kernel into XKPHYS
>> without a good reason, but it might be helpful to add a BUG_ON at
>> CPS driver to handle such situation.
>
> I guess that being in KSEG0 allows to use shorter pointer. But in our
> case the RAM is physically connected beyond 32bits, so it is not
> accessible in KSEG0.
For most system there should be a mirror of part of DDR which is accessible
at KSEG0 and kernel runs from here. As per my interpretion of your code EyeQ5
is also doing this? If not could you please briefly describe the memory map?
For Kernel in KSEG0 the pointer is still 64bit but we can use fewer inst
to load ABS pointer into register, see [1].
>>
>> Btw: Is your target hardware publicly available? Folks at CIP United
>> are looking for EyeQ5 boards for a while, they are supporting MIPS R6
>> support at various projects.
>
> We use evaluation boards and I don't know if they are publicly
> available.
>
> Gregory
>
[1]: https://elinux.org/images/1/1f/New-tricks-mips-linux.pdf
Thanks
- Jiaxun
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 05/11] dt-bindings: mips: cpu: Add I-Class I6500 Multiprocessor Core
2023-10-09 15:32 ` Gregory CLEMENT
2023-10-09 18:48 ` Arnd Bergmann
@ 2023-10-10 10:13 ` Serge Semin
1 sibling, 0 replies; 53+ messages in thread
From: Serge Semin @ 2023-10-10 10:13 UTC (permalink / raw)
To: Gregory CLEMENT
Cc: Rob Herring, Arnd Bergmann, Phil Mathieu-Daudé,
Paul Burton, Thomas Bogendoerfer, linux-mips,
Krzysztof Kozlowski, devicetree, linux-kernel,
Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni
On Mon, Oct 09, 2023 at 05:32:57PM +0200, Gregory CLEMENT wrote:
> Rob Herring <robh@kernel.org> writes:
>
> > On Fri, Oct 06, 2023 at 12:48:03PM +0200, Arnd Bergmann wrote:
> >> On Thu, Oct 5, 2023, at 16:51, Gregory CLEMENT wrote:
> >> >> On Wed, Oct 04, 2023 at 06:10:32PM +0200, Gregory CLEMENT wrote:
> >> >>> The MIPS Warrior I-class I6500 was announced by Imagination
> >> >>> Technologies in 2016 and is used in the Mobileye SoC EyeQ5.
> >> >>>
> >> >>> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> >> >>> ---
> >> >>> Documentation/devicetree/bindings/mips/cpus.yaml | 1 +
> >> >>> 1 file changed, 1 insertion(+)
> >> >>>
> >> >>> diff --git a/Documentation/devicetree/bindings/mips/cpus.yaml b/Documentation/devicetree/bindings/mips/cpus.yaml
> >> >>> index cf382dea3922..87fd2842ba68 100644
> >> >>> --- a/Documentation/devicetree/bindings/mips/cpus.yaml
> >> >>> +++ b/Documentation/devicetree/bindings/mips/cpus.yaml
> >> >>> @@ -39,6 +39,7 @@ properties:
> >> >>> - mti,mips24KEc
> >> >>> - mti,mips14KEc
> >> >>> - mti,mips14Kc
> >> >>
> >> >>> + - mti,i6500
> >> >>
> >> >> Since the CPU core vendor is Imagination Technologies thus it would
> >> >> be more appropriate to have the "img," prefix. Wouldn't it?
> >> >
> >> > According to Documentation/devicetree/bindings/vendor-prefixes.yaml
> >> >
> >> > "^mti,.*":
> >> > description: Imagination Technologies Ltd. (formerly MIPS
> >> > Technologies Inc.)
> >> >
> >> > So I think it's OK.
> >>
> >> I don't see any good solution, they changed their name and
> >> ownership too many times. I would actually revert back the
> >> description here to "MIPS Technologies Inc" instead of trying
> >> to keep track of what they currently call themselves.
> >>
> >> Since we already have both the 'mips,' and 'mti,' vendow
> >> names for the 14Kc, 14KEc and 24KEc parts, maybe we can
> >> just go back to 'mips,' for all cores past the mti era
> >> rather than trying to date and geolocate each of the
> >> classic cores as one of 'mti', 'img', 'wavecomp', 'tallwood',
> >> 'mips' 'cipunited' etc.
> >
> > I would reserve 'mips' for anything common. Much like 'riscv' is only
> > for things based on RiscV specs/standards.
> >
> > I would use 'img' here if we know this was designed/implemented by
> > Imagination.
>
> If there is no objection I will use 'img' then.
Sounds good. Thanks. Feel free to add then:
Acked-by: Serge Semin <fancer.lancer@gmail.com>
-Serge(y)
>
> Gregory
>
> >
> > Rob
>
> --
> Gregory Clement, Bootlin
> Embedded Linux and Kernel engineering
> http://bootlin.com
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 03/11] MIPS: support RAM beyond 32-bit
2023-10-10 8:55 ` Jiaxun Yang
@ 2023-10-11 14:46 ` Gregory CLEMENT
2023-10-12 20:40 ` Jiaxun Yang
0 siblings, 1 reply; 53+ messages in thread
From: Gregory CLEMENT @ 2023-10-11 14:46 UTC (permalink / raw)
To: Jiaxun Yang, paulburton, Thomas Bogendoerfer, linux-mips,
Rob Herring, Krzysztof Kozlowski, devicetree, linux-kernel
Cc: Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni
Hello Jiaxun,
> 在2023年10月9日十月 下午4:59，Gregory CLEMENT写道：
>> Hello Jiaxun,
>>
>>> 在2023年10月4日十月 下午5:10，Gregory CLEMENT写道：
>>>> From: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
>>>>
>>>> Support platforms where RAM is mapped beyond 32-bit.
>>>>
>>>> The kernel parameter ddr32_alias allows to setup the alias to point
>>>> outside the first 4 GB of memory.
>>>
>>> Are you trying to fix the problem that if kernel text is loaded in
>>> XKPHYS there is no way to to set EBASE to that region?
>>
>> Yes that exactly we try to fix.
>>
>>>
>>> The common practice for other 64bit MIPS system is to load kernel
>>> in KSEG0 and add low 4G mirror with rest of the high memory to buddy
>>> system. By doing this Kernel still have access to all memory beyond
>>> 32 bit, the only draw back is Kernel's text and data can't be relocted
>>> beyond 32-bit.
>>>
>>> Loading kernel into KSEG0 (i.e. with KBUILD_SYM32) have significant benefit
>>> on performance, so I think you shouldn't try to load kernel into XKPHYS
>>> without a good reason, but it might be helpful to add a BUG_ON at
>>> CPS driver to handle such situation.
>>
>> I guess that being in KSEG0 allows to use shorter pointer. But in our
>> case the RAM is physically connected beyond 32bits, so it is not
>> accessible in KSEG0.
>
> For most system there should be a mirror of part of DDR which is accessible
> at KSEG0 and kernel runs from here. As per my interpretion of your code EyeQ5
> is also doing this? If not could you please briefly describe the memory map?
>
> For Kernel in KSEG0 the pointer is still 64bit but we can use fewer inst
> to load ABS pointer into register, see [1].
>
There is a kind of mirror but its physical address start at 0x8000000
so beyond the first 512MBytes that are used for KSEG0.
In short the 32bits mapping is the following:
- the controllers registers of the SoC are located until 0x8000000,
- then from 0x8000000 to 0x10000000 there is the alias to low addresses
of the DDR
- then the SPIflash is mapped to from 0x10000000 to 0x20000000
- after the PCIe Memory 32-bit addr space is from 0x20000000 to
0x40000000
Gregory
> [1]: https://elinux.org/images/1/1f/New-tricks-mips-linux.pdf
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 02/11] MIPS: use virtual addresses from xkphys for MIPS64
2023-10-04 16:10 ` [PATCH 02/11] MIPS: use virtual addresses from xkphys for MIPS64 Gregory CLEMENT
@ 2023-10-12 15:34 ` Thomas Bogendoerfer
2023-10-22 11:52 ` Jiaxun Yang
2023-10-22 11:39 ` Jiaxun Yang
2023-10-22 16:42 ` Jiaxun Yang
2 siblings, 1 reply; 53+ messages in thread
From: Thomas Bogendoerfer @ 2023-10-12 15:34 UTC (permalink / raw)
To: Gregory CLEMENT
Cc: Paul Burton, linux-mips, Rob Herring, Krzysztof Kozlowski,
devicetree, linux-kernel, Vladimir Kondratiev, Tawfik Bayouk,
Alexandre Belloni, Théo Lebrun, Thomas Petazzoni
On Wed, Oct 04, 2023 at 06:10:29PM +0200, Gregory CLEMENT wrote:
> From: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
>
> Now 64-bit MIPS uses 32-bit compatible segments KSEG0 and KSEG1
> to trivially map first 1/2 GByte of physical memory. This memory
> used to run kernel. This mean, one should have memory installed
> in this area in order for Linux to work.
>
> Kconfig CONFIG_USE_XKPHYS introduced; it adds support for kernel
> to use virtual addresses from the XKPHYS segment for both cached
> and uncached access. XKPHYS allows to access 2^48 bytes of
> memory, thus allowing kernel to work with any memory
> configuration.
IMHO it doesn't make sense to introduce an option for a generic
kernel, which then renders the generic kernel useless on all
platforms other then yours.
Please don't use generic, but setup a new platform for it. Hopefully
we can get rid all of the weirdness in this patch.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 03/11] MIPS: support RAM beyond 32-bit
2023-10-11 14:46 ` Gregory CLEMENT
@ 2023-10-12 20:40 ` Jiaxun Yang
2023-10-24 9:05 ` Maciej W. Rozycki
0 siblings, 1 reply; 53+ messages in thread
From: Jiaxun Yang @ 2023-10-12 20:40 UTC (permalink / raw)
To: Gregory CLEMENT, paulburton, Thomas Bogendoerfer, linux-mips,
Rob Herring, Krzysztof Kozlowski, devicetree, linux-kernel
Cc: Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni
在2023年10月11日十月 下午3:46，Gregory CLEMENT写道：
> Hello Jiaxun,
>
[...]
>
> There is a kind of mirror but its physical address start at 0x8000000
> so beyond the first 512MBytes that are used for KSEG0.
Really, KSEG0 range is 0x00000000 to 0x20000000, and 0x08000000 to 0x10000000
is definitely within that range.
But I'd agree that 0x08000000 to 0x10000000 (32MB) seems too small for kernel
text and data. So yeah, it makes sense to load kernel into XKPHYS.
My sugesstion is, kernel does not have to be aware of the mirror deisgn.
Say that you have DDR fully mapped at 0x100000000, you can split memory
space into two trunks: 0x08000000 to 0x10000000 and 0x102000000 to end
of the dram. Since memblock always allocate from first continuous range
in system, we can guarantee that ebase is allocated with in the first
trunk.
Thanks
>
> In short the 32bits mapping is the following:
>
> - the controllers registers of the SoC are located until 0x8000000,
> - then from 0x8000000 to 0x10000000 there is the alias to low addresses
> of the DDR
> - then the SPIflash is mapped to from 0x10000000 to 0x20000000
> - after the PCIe Memory 32-bit addr space is from 0x20000000 to
> 0x40000000
>
> Gregory
>
>> [1]: https://elinux.org/images/1/1f/New-tricks-mips-linux.pdf
>
> --
> Gregory Clement, Bootlin
> Embedded Linux and Kernel engineering
> http://bootlin.com
--
- Jiaxun
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 02/11] MIPS: use virtual addresses from xkphys for MIPS64
2023-10-04 16:10 ` [PATCH 02/11] MIPS: use virtual addresses from xkphys for MIPS64 Gregory CLEMENT
2023-10-12 15:34 ` Thomas Bogendoerfer
@ 2023-10-22 11:39 ` Jiaxun Yang
2023-10-23 15:45 ` Gregory CLEMENT
2023-10-22 16:42 ` Jiaxun Yang
2 siblings, 1 reply; 53+ messages in thread
From: Jiaxun Yang @ 2023-10-22 11:39 UTC (permalink / raw)
To: Gregory CLEMENT, paulburton, Thomas Bogendoerfer, linux-mips,
Rob Herring, Krzysztof Kozlowski, devicetree, linux-kernel
Cc: Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni
在2023年10月4日十月 下午5:10，Gregory CLEMENT写道：
> From: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
>
> Now 64-bit MIPS uses 32-bit compatible segments KSEG0 and KSEG1
> to trivially map first 1/2 GByte of physical memory. This memory
> used to run kernel. This mean, one should have memory installed
> in this area in order for Linux to work.
>
> Kconfig CONFIG_USE_XKPHYS introduced; it adds support for kernel
> to use virtual addresses from the XKPHYS segment for both cached
> and uncached access. XKPHYS allows to access 2^48 bytes of
> memory, thus allowing kernel to work with any memory
> configuration.
>
> MIPS CPU sets KX bit in the CP0 status register at reset
> if RESET_BASE_MODE (BIT 1) set in the GCR_CL_RESET_BASE.
>
> Reset vector should fit into 32-bit. If reset vector put outside of
> KSEG1, BIT(1) should be set in this value.
>
> IRQ handler for CPU updated to generate 64-bit address for jump
Please use existing KBUILD_SYM32 symbol.
Thanks
- Jiaxun
>
> Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
> arch/mips/Kconfig | 15 +++++++++++++
> arch/mips/Makefile | 4 ++++
> arch/mips/generic/Platform | 5 +++++
> arch/mips/include/asm/addrspace.h | 12 ++++++++--
> arch/mips/include/asm/mips-cm.h | 1 +
> arch/mips/include/asm/page.h | 10 +++++++++
> arch/mips/include/asm/vga.h | 4 ++++
> arch/mips/kernel/cps-vec.S | 8 +++++++
> arch/mips/kernel/genex.S | 14 ++++++++++++
> arch/mips/kernel/smp-cps.c | 37 +++++++++++++++++++++++--------
> arch/mips/kernel/traps.c | 32 +++++++++++++++++++++++---
> arch/mips/lib/uncached.c | 10 +++++++++
> arch/mips/mm/init.c | 4 ++--
> 13 files changed, 140 insertions(+), 16 deletions(-)
>
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index bc8421859006..92832bbcca5d 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -2026,6 +2026,21 @@ config 64BIT
>
> endchoice
>
> +config USE_XKPHYS
> + bool "use virtual address from XKPHYS"
> + depends on 64BIT
> + default n
> + help
> + By default, MIPS uses 32-bit compatible segments KSEG0 and KSEG1
> + to trivially map first 1/2 GByte of physical memory. This mean,
> + one should have memory installed in this area in order for Linux to
> + work. With this option selected, kernel uses virtual addresses from
> + the XKPHYS segment for both cached and uncached access. XKPHYS allows
> + to access 2^48 bytes of memory, thus allowing to work with any memory
> + configuration.
> +
> + Say N if not sure
> +
> config MIPS_VA_BITS_48
> bool "48 bits virtual memory"
> depends on 64BIT
> diff --git a/arch/mips/Makefile b/arch/mips/Makefile
> index f49807e1f19b..544ee8427cab 100644
> --- a/arch/mips/Makefile
> +++ b/arch/mips/Makefile
> @@ -303,6 +303,10 @@ ifdef CONFIG_64BIT
> endif
> endif
>
> + ifdef CONFIG_USE_XKPHYS
> + KBUILD_SYM32 = n
> + endif
> +
> ifeq ($(KBUILD_SYM32), y)
> cflags-$(KBUILD_SYM32) += -msym32 -DKBUILD_64BIT_SYM32
> else
> diff --git a/arch/mips/generic/Platform b/arch/mips/generic/Platform
> index 0c03623f3897..2be9947814ad 100644
> --- a/arch/mips/generic/Platform
> +++ b/arch/mips/generic/Platform
> @@ -12,7 +12,12 @@
> cflags-$(CONFIG_MACH_INGENIC_SOC) +=
> -I$(srctree)/arch/mips/include/asm/mach-ingenic
> cflags-$(CONFIG_MIPS_GENERIC) +=
> -I$(srctree)/arch/mips/include/asm/mach-generic
>
> +ifndef (CONFIG_USE_XKPHYS)
> load-$(CONFIG_MIPS_GENERIC) += 0xffffffff80100000
> +else
> +load-$(CONFIG_MIPS_GENERIC) += 0xa800000080100000
> +endif
> +
> all-$(CONFIG_MIPS_GENERIC) += vmlinux.gz.itb
>
> its-y := vmlinux.its.S
> diff --git a/arch/mips/include/asm/addrspace.h
> b/arch/mips/include/asm/addrspace.h
> index 59a48c60a065..8dc500d8e66d 100644
> --- a/arch/mips/include/asm/addrspace.h
> +++ b/arch/mips/include/asm/addrspace.h
> @@ -65,10 +65,15 @@
> #define XKSSEG _CONST64_(0x4000000000000000)
> #define XKPHYS _CONST64_(0x8000000000000000)
> #define XKSEG _CONST64_(0xc000000000000000)
> +#if !defined(CONFIG_USE_XKPHYS)
> #define CKSEG0 _CONST64_(0xffffffff80000000)
> #define CKSEG1 _CONST64_(0xffffffffa0000000)
> #define CKSSEG _CONST64_(0xffffffffc0000000)
> #define CKSEG3 _CONST64_(0xffffffffe0000000)
> +#else
> +#define CKSEG0 XKPHYS_CM_CACHED
> +#define CKSEG1 XKPHYS_CM_UNCACHED
> +#endif /* !defined(CONFIG_USE_XKPHYS) */
>
> #define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0)
> #define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1)
> @@ -126,8 +131,11 @@
> #define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p))
> #define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p))
> #define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK)
> -#define PHYS_TO_XKPHYS(cm, a) (XKPHYS | (_ACAST64_(cm) << 59) | (a))
> -
> +#define XKPHYS_CM(cm) (XKPHYS | (_ACAST64_(cm) << 59))
> +#define PHYS_TO_XKPHYS(cm, a) (XKPHYS_CM(cm) | (a))
> +#define XKPHYS_CM_CACHED (XKPHYS_CM(K_CALG_COH_SHAREABLE))
> +#define XKPHYS_CM_UNCACHED (XKPHYS_CM(K_CALG_UNCACHED))
> +#define IS_XKPHYS(a) (((a) >> 62) == 2)
> /*
> * The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting
> * the region, 3 bits for the CCA mode. This leaves 59 bits of which the
> diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h
> index 23c67c0871b1..15d8d69de455 100644
> --- a/arch/mips/include/asm/mips-cm.h
> +++ b/arch/mips/include/asm/mips-cm.h
> @@ -311,6 +311,7 @@ GCR_CX_ACCESSOR_RW(32, 0x018, other)
> /* GCR_Cx_RESET_BASE - Configure where powered up cores will fetch from */
> GCR_CX_ACCESSOR_RW(32, 0x020, reset_base)
> #define CM_GCR_Cx_RESET_BASE_BEVEXCBASE GENMASK(31, 12)
> +#define CM_GCR_Cx_RESET_BASE_MODE BIT(1)
>
> /* GCR_Cx_ID - Identify the current core */
> GCR_CX_ACCESSOR_RO(32, 0x028, id)
> diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
> index 5978a8dfb917..53b8306da571 100644
> --- a/arch/mips/include/asm/page.h
> +++ b/arch/mips/include/asm/page.h
> @@ -176,7 +176,11 @@ static inline unsigned long ___pa(unsigned long x)
> * the compatibility segements ckseg0 or ckseg1, or it may
> * be in xkphys.
> */
> +#if defined(CONFIG_USE_XKPHYS)
> + return XPHYSADDR(x);
> +#else
> return x < CKSEG0 ? XPHYSADDR(x) : CPHYSADDR(x);
> +#endif
> }
>
> if (!IS_ENABLED(CONFIG_EVA)) {
> @@ -196,7 +200,11 @@ static inline unsigned long ___pa(unsigned long x)
> return x - PAGE_OFFSET + PHYS_OFFSET;
> }
> #define __pa(x) ___pa((unsigned long)(x))
> +#if IS_ENABLED(CONFIG_64BIT) && IS_ENABLED(CONFIG_USE_XKPHYS)
> +#define __va(x) ((void *)PHYS_TO_XKSEG_CACHED(x))
> +#else
> #define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET))
> +#endif
> #include <asm/io.h>
>
> /*
> @@ -239,6 +247,8 @@ static inline unsigned long kaslr_offset(void)
> return __kaslr_offset;
> }
>
> +#define UNCAC_ADDR(addr) (UNCAC_BASE + __pa(addr))
> +
> #include <asm-generic/memory_model.h>
> #include <asm-generic/getorder.h>
>
> diff --git a/arch/mips/include/asm/vga.h b/arch/mips/include/asm/vga.h
> index 0136e0366698..e338e57d0784 100644
> --- a/arch/mips/include/asm/vga.h
> +++ b/arch/mips/include/asm/vga.h
> @@ -16,7 +16,11 @@
> * access the videoram directly without any black magic.
> */
>
> +#if defined(CONFIG_USE_XKPHYS)
> +#define VGA_MAP_MEM(x, s) UNCAC_ADDR(0x10000000L + (unsigned long)(x))
> +#else
> #define VGA_MAP_MEM(x, s) CKSEG1ADDR(0x10000000L + (unsigned long)(x))
> +#endif
>
> #define vga_readb(x) (*(x))
> #define vga_writeb(x, y) (*(y) = (x))
> diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
> index 64ecfdac6580..541f31a43a7f 100644
> --- a/arch/mips/kernel/cps-vec.S
> +++ b/arch/mips/kernel/cps-vec.S
> @@ -554,7 +554,11 @@ LEAF(mips_cps_cache_init)
> mul t1, t1, t0
> mul t1, t1, t2
>
> +#if defined(CONFIG_USE_XKPHYS)
> + PTR_LI a0, XKPHYS_CM_CACHED
> +#else
> li a0, CKSEG0
> +#endif
> PTR_ADD a1, a0, t1
> 1: cache Index_Store_Tag_I, 0(a0)
> PTR_ADD a0, a0, t0
> @@ -581,7 +585,11 @@ icache_done:
> mul t1, t1, t0
> mul t1, t1, t2
>
> +#if defined(CONFIG_USE_XKPHYS)
> + PTR_LI a0, XKPHYS_CM_CACHED
> +#else
> li a0, CKSEG0
> +#endif
> PTR_ADDU a1, a0, t1
> PTR_SUBU a1, a1, t0
> 1: cache Index_Store_Tag_D, 0(a0)
> diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
> index b6de8e88c1bd..a002058e1838 100644
> --- a/arch/mips/kernel/genex.S
> +++ b/arch/mips/kernel/genex.S
> @@ -272,11 +272,25 @@ NESTED(except_vec_vi, 0, sp)
> .set push
> .set noreorder
> PTR_LA v1, except_vec_vi_handler
> +#if defined(CONFIG_USE_XKPHYS)
> +FEXPORT(except_vec_vi_63_48)
> + lui v0, 0 /* Patched - bits 63:48 */
> +FEXPORT(except_vec_vi_47_32)
> + ori v0, 0 /* Patched - bits 47:32 */
> + dsll v0, v0, 0x10
> +FEXPORT(except_vec_vi_31_16)
> + ori v0, 0 /* Patched - bits 31:16 */
> + dsll v0, v0, 0x10
> + jr v1
> +FEXPORT(except_vec_vi_15_0)
> + ori v0, 0 /* Patched - bits 15:0 */
> +#else /* defined(CONFIG_USE_XKPHYS) */
> FEXPORT(except_vec_vi_lui)
> lui v0, 0 /* Patched */
> jr v1
> FEXPORT(except_vec_vi_ori)
> ori v0, 0 /* Patched */
> +#endif /* defined(CONFIG_USE_XKPHYS) */
> .set pop
> END(except_vec_vi)
> EXPORT(except_vec_vi_end)
> diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
> index dd55d59b88db..47e76722a306 100644
> --- a/arch/mips/kernel/smp-cps.c
> +++ b/arch/mips/kernel/smp-cps.c
> @@ -34,10 +34,33 @@ static unsigned __init core_vpe_count(unsigned int
> cluster, unsigned core)
> return min(smp_max_threads, mips_cps_numvps(cluster, core));
> }
>
> +/**
> + * plat_core_entry - query reset vector for NMI/reset
> + *
> + * Returns low 32 bits of the reset vector
> + *
> + * This is used to fill 2 registers:
> + * - BEV Base (GCR_BEV_BASE) Offset: 0x0680
> + * - VP Local Reset Exception Base (GCR_CL_RESET_BASE,GCR_CO_RESET_BASE)
> + * Offset: 0x0020 (0x2020 relative to GCR_BASE_ADDR)
> + *
> + * In both registers, BIT(1) should be set in case it uses address in XKPHYS
> + * (as opposed to KSEG1). This bit defined as CM_GCR_Cx_RESET_BASE_MODE,
> + * using it unconditionally because for GCR_BEV_BASE its value is the same
> + */
> +static u32 plat_core_entry(void)
> +{
> +#if defined(CONFIG_USE_XKPHYS)
> + return (UNCAC_ADDR(mips_cps_core_entry) & 0xffffffff)
> + | CM_GCR_Cx_RESET_BASE_MODE;
> +#else
> + return CKSEG1ADDR((unsigned long)mips_cps_core_entry);
> +#endif
> +}
> +
> static void __init cps_smp_setup(void)
> {
> unsigned int nclusters, ncores, nvpes, core_vpes;
> - unsigned long core_entry;
> int cl, c, v;
>
> /* Detect & record VPE topology */
> @@ -94,10 +117,8 @@ static void __init cps_smp_setup(void)
> /* Make core 0 coherent with everything */
> write_gcr_cl_coherence(0xff);
>
> - if (mips_cm_revision() >= CM_REV_CM3) {
> - core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry);
> - write_gcr_bev_base(core_entry);
> - }
> + if (mips_cm_revision() >= CM_REV_CM3)
> + write_gcr_bev_base(plat_core_entry());
>
> #ifdef CONFIG_MIPS_MT_FPAFF
> /* If we have an FPU, enroll ourselves in the FPU-full mask */
> @@ -213,7 +234,7 @@ static void boot_core(unsigned int core, unsigned
> int vpe_id)
> mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
>
> /* Set its reset vector */
> - write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry));
> + write_gcr_co_reset_base(plat_core_entry());
>
> /* Ensure its coherency is disabled */
> write_gcr_co_coherence(0);
> @@ -290,7 +311,6 @@ static int cps_boot_secondary(int cpu, struct
> task_struct *idle)
> unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
> struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
> struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id];
> - unsigned long core_entry;
> unsigned int remote;
> int err;
>
> @@ -314,8 +334,7 @@ static int cps_boot_secondary(int cpu, struct
> task_struct *idle)
>
> if (cpu_has_vp) {
> mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
> - core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry);
> - write_gcr_co_reset_base(core_entry);
> + write_gcr_co_reset_base(plat_core_entry());
> mips_cm_unlock_other();
> }
>
> diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
> index 246c6a6b0261..875594843626 100644
> --- a/arch/mips/kernel/traps.c
> +++ b/arch/mips/kernel/traps.c
> @@ -2091,11 +2091,20 @@ static void *set_vi_srs_handler(int n,
> vi_handler_t addr, int srs)
> * If no shadow set is selected then use the default handler
> * that does normal register saving and standard interrupt exit
> */
> - extern const u8 except_vec_vi[], except_vec_vi_lui[];
> - extern const u8 except_vec_vi_ori[], except_vec_vi_end[];
> + extern const u8 except_vec_vi[], except_vec_vi_end[];
> extern const u8 rollback_except_vec_vi[];
> const u8 *vec_start = using_rollback_handler() ?
> rollback_except_vec_vi : except_vec_vi;
> + const int handler_len = except_vec_vi_end - vec_start;
> +#if defined(CONFIG_USE_XKPHYS)
> + extern const u8 except_vec_vi_63_48[], except_vec_vi_47_32[];
> + extern const u8 except_vec_vi_31_16[], except_vec_vi_15_0[];
> + const int offset_63_48 = except_vec_vi_63_48 - vec_start;
> + const int offset_47_32 = except_vec_vi_47_32 - vec_start;
> + const int offset_31_16 = except_vec_vi_31_16 - vec_start;
> + const int offset_15_0 = except_vec_vi_15_0 - vec_start;
> +#else /* defined(CONFIG_USE_XKPHYS) */
> + extern const u8 except_vec_vi_lui[], except_vec_vi_ori[];
> #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
> const int lui_offset = except_vec_vi_lui - vec_start + 2;
> const int ori_offset = except_vec_vi_ori - vec_start + 2;
> @@ -2103,7 +2112,7 @@ static void *set_vi_srs_handler(int n,
> vi_handler_t addr, int srs)
> const int lui_offset = except_vec_vi_lui - vec_start;
> const int ori_offset = except_vec_vi_ori - vec_start;
> #endif
> - const int handler_len = except_vec_vi_end - vec_start;
> +#endif /* defined(CONFIG_USE_XKPHYS) */
>
> if (handler_len > VECTORSPACING) {
> /*
> @@ -2119,10 +2128,21 @@ static void *set_vi_srs_handler(int n,
> vi_handler_t addr, int srs)
> #else
> handler_len);
> #endif
> +#if defined(CONFIG_USE_XKPHYS)
> + h = (u16 *)(b + offset_63_48);
> + *h = (handler >> 48) & 0xffff;
> + h = (u16 *)(b + offset_47_32);
> + *h = (handler >> 32) & 0xffff;
> + h = (u16 *)(b + offset_31_16);
> + *h = (handler >> 16) & 0xffff;
> + h = (u16 *)(b + offset_15_0);
> + *h = (handler >> 0) & 0xffff;
> +#else /* defined(CONFIG_USE_XKPHYS) */
> h = (u16 *)(b + lui_offset);
> *h = (handler >> 16) & 0xffff;
> h = (u16 *)(b + ori_offset);
> *h = (handler & 0xffff);
> +#endif /* defined(CONFIG_USE_XKPHYS) */
> local_flush_icache_range((unsigned long)b,
> (unsigned long)(b+handler_len));
> }
> @@ -2332,7 +2352,11 @@ static const char panic_null_cerr[] =
> void set_uncached_handler(unsigned long offset, void *addr,
> unsigned long size)
> {
> +#if IS_ENABLED(CONFIG_64BIT) && IS_ENABLED(CONFIG_USE_XKPHYS)
> + unsigned long uncached_ebase = UNCAC_ADDR(ebase);
> +#else
> unsigned long uncached_ebase = CKSEG1ADDR(ebase);
> +#endif
>
> if (!addr)
> panic(panic_null_cerr);
> @@ -2384,9 +2408,11 @@ void __init trap_init(void)
> * EVA is special though as it allows segments to be rearranged
> * and to become uncached during cache error handling.
> */
> +#if !defined(CONFIG_USE_XKPHYS)
> if (!IS_ENABLED(CONFIG_EVA) && !WARN_ON(ebase_pa >= 0x20000000))
> ebase = CKSEG0ADDR(ebase_pa);
> else
> +#endif
> ebase = (unsigned long)phys_to_virt(ebase_pa);
> }
>
> diff --git a/arch/mips/lib/uncached.c b/arch/mips/lib/uncached.c
> index f80a67c092b6..8a78348a2dd7 100644
> --- a/arch/mips/lib/uncached.c
> +++ b/arch/mips/lib/uncached.c
> @@ -44,6 +44,10 @@ unsigned long run_uncached(void *func)
>
> __asm__("move %0, $sp" : "=r" (sp));
>
> +#if defined(CONFIG_USE_XKPHYS)
> + if (IS_XKPHYS(sp))
> + usp = UNCAC_ADDR(sp);
> +#else /* defined(CONFIG_USE_XKPHYS) */
> if (sp >= (long)CKSEG0 && sp < (long)CKSEG2)
> usp = CKSEG1ADDR(sp);
> #ifdef CONFIG_64BIT
> @@ -52,10 +56,15 @@ unsigned long run_uncached(void *func)
> usp = PHYS_TO_XKPHYS(K_CALG_UNCACHED,
> XKPHYS_TO_PHYS((long long)sp));
> #endif
> +#endif /* defined(CONFIG_USE_XKPHYS) */
> else {
> BUG();
> usp = sp;
> }
> +#if defined(CONFIG_USE_XKPHYS)
> + if (IS_XKPHYS(lfunc))
> + ufunc = UNCAC_ADDR(lfunc);
> +#else /* defined(CONFIG_USE_XKPHYS) */
> if (lfunc >= (long)CKSEG0 && lfunc < (long)CKSEG2)
> ufunc = CKSEG1ADDR(lfunc);
> #ifdef CONFIG_64BIT
> @@ -64,6 +73,7 @@ unsigned long run_uncached(void *func)
> ufunc = PHYS_TO_XKPHYS(K_CALG_UNCACHED,
> XKPHYS_TO_PHYS((long long)lfunc));
> #endif
> +#endif /* defined(CONFIG_USE_XKPHYS) */
> else {
> BUG();
> ufunc = lfunc;
> diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
> index 5dcb525a8995..eb57283ec4e0 100644
> --- a/arch/mips/mm/init.c
> +++ b/arch/mips/mm/init.c
> @@ -427,7 +427,7 @@ void __init paging_init(void)
> free_area_init(max_zone_pfns);
> }
>
> -#ifdef CONFIG_64BIT
> +#if defined(CONFIG_64BIT) && !defined(CONFIG_USE_XKPHYS)
> static struct kcore_list kcore_kseg0;
> #endif
>
> @@ -470,7 +470,7 @@ void __init mem_init(void)
> setup_zero_pages(); /* Setup zeroed pages. */
> mem_init_free_highmem();
>
> -#ifdef CONFIG_64BIT
> +#if defined(CONFIG_64BIT) && !defined(CONFIG_USE_XKPHYS)
> if ((unsigned long) &_text > (unsigned long) CKSEG0)
> /* The -4 is a hack so that user tools don't have to handle
> the overflow. */
> --
> 2.40.1
--
- Jiaxun
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 02/11] MIPS: use virtual addresses from xkphys for MIPS64
2023-10-12 15:34 ` Thomas Bogendoerfer
@ 2023-10-22 11:52 ` Jiaxun Yang
0 siblings, 0 replies; 53+ messages in thread
From: Jiaxun Yang @ 2023-10-22 11:52 UTC (permalink / raw)
To: Thomas Bogendoerfer, Gregory CLEMENT
Cc: paulburton, linux-mips, Rob Herring, Krzysztof Kozlowski,
devicetree, linux-kernel, Vladimir Kondratiev, Tawfik Bayouk,
Alexandre Belloni, Théo Lebrun, Thomas Petazzoni
在2023年10月12日十月 下午4:34，Thomas Bogendoerfer写道：
> On Wed, Oct 04, 2023 at 06:10:29PM +0200, Gregory CLEMENT wrote:
>> From: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
>>
>> Now 64-bit MIPS uses 32-bit compatible segments KSEG0 and KSEG1
>> to trivially map first 1/2 GByte of physical memory. This memory
>> used to run kernel. This mean, one should have memory installed
>> in this area in order for Linux to work.
>>
>> Kconfig CONFIG_USE_XKPHYS introduced; it adds support for kernel
>> to use virtual addresses from the XKPHYS segment for both cached
>> and uncached access. XKPHYS allows to access 2^48 bytes of
>> memory, thus allowing kernel to work with any memory
>> configuration.
>
> IMHO it doesn't make sense to introduce an option for a generic
> kernel, which then renders the generic kernel useless on all
> platforms other then yours.
Actually it won't. Many 64bit platforms do support load kernel to
XKPHYS, including boston and Loongson64, so it's still a generic
function.
IMO this patch won't break support for any generic platform.
>
> Please don't use generic, but setup a new platform for it. Hopefully
> we can get rid all of the weirdness in this patch.
Perhaps better to introduce a Kconfig option to allow manipulation of
kernel load address.
Thanks
- Jiaxun
>
> Thomas.
>
> --
> Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
> good idea. [ RFC1925, 2.3 ]
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 02/11] MIPS: use virtual addresses from xkphys for MIPS64
2023-10-04 16:10 ` [PATCH 02/11] MIPS: use virtual addresses from xkphys for MIPS64 Gregory CLEMENT
2023-10-12 15:34 ` Thomas Bogendoerfer
2023-10-22 11:39 ` Jiaxun Yang
@ 2023-10-22 16:42 ` Jiaxun Yang
2023-10-24 16:08 ` Gregory CLEMENT
2 siblings, 1 reply; 53+ messages in thread
From: Jiaxun Yang @ 2023-10-22 16:42 UTC (permalink / raw)
To: Gregory CLEMENT, paulburton, Thomas Bogendoerfer, linux-mips,
Rob Herring, Krzysztof Kozlowski, devicetree, linux-kernel
Cc: Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni
在2023年10月4日十月 下午5:10，Gregory CLEMENT写道：
> From: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
>
> Now 64-bit MIPS uses 32-bit compatible segments KSEG0 and KSEG1
> to trivially map first 1/2 GByte of physical memory. This memory
> used to run kernel. This mean, one should have memory installed
> in this area in order for Linux to work.
>
> Kconfig CONFIG_USE_XKPHYS introduced; it adds support for kernel
> to use virtual addresses from the XKPHYS segment for both cached
> and uncached access. XKPHYS allows to access 2^48 bytes of
> memory, thus allowing kernel to work with any memory
> configuration.
>
> MIPS CPU sets KX bit in the CP0 status register at reset
> if RESET_BASE_MODE (BIT 1) set in the GCR_CL_RESET_BASE.
>
> Reset vector should fit into 32-bit. If reset vector put outside of
> KSEG1, BIT(1) should be set in this value.
>
> IRQ handler for CPU updated to generate 64-bit address for jump
So I just spend some time to review and test this patch on QEMU,
comments below:
>
> Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
> arch/mips/Kconfig | 15 +++++++++++++
> arch/mips/Makefile | 4 ++++
> arch/mips/generic/Platform | 5 +++++
> arch/mips/include/asm/addrspace.h | 12 ++++++++--
> arch/mips/include/asm/mips-cm.h | 1 +
> arch/mips/include/asm/page.h | 10 +++++++++
> arch/mips/include/asm/vga.h | 4 ++++
> arch/mips/kernel/cps-vec.S | 8 +++++++
> arch/mips/kernel/genex.S | 14 ++++++++++++
> arch/mips/kernel/smp-cps.c | 37 +++++++++++++++++++++++--------
> arch/mips/kernel/traps.c | 32 +++++++++++++++++++++++---
> arch/mips/lib/uncached.c | 10 +++++++++
> arch/mips/mm/init.c | 4 ++--
> 13 files changed, 140 insertions(+), 16 deletions(-)
>
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index bc8421859006..92832bbcca5d 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -2026,6 +2026,21 @@ config 64BIT
>
> endchoice
>
> +config USE_XKPHYS
> + bool "use virtual address from XKPHYS"
> + depends on 64BIT
> + default n
> + help
> + By default, MIPS uses 32-bit compatible segments KSEG0 and KSEG1
> + to trivially map first 1/2 GByte of physical memory. This mean,
> + one should have memory installed in this area in order for Linux to
> + work. With this option selected, kernel uses virtual addresses from
> + the XKPHYS segment for both cached and uncached access. XKPHYS allows
> + to access 2^48 bytes of memory, thus allowing to work with any memory
> + configuration.
> +
> + Say N if not sure
> +
> config MIPS_VA_BITS_48
> bool "48 bits virtual memory"
> depends on 64BIT
> diff --git a/arch/mips/Makefile b/arch/mips/Makefile
> index f49807e1f19b..544ee8427cab 100644
> --- a/arch/mips/Makefile
> +++ b/arch/mips/Makefile
> @@ -303,6 +303,10 @@ ifdef CONFIG_64BIT
> endif
> endif
>
> + ifdef CONFIG_USE_XKPHYS
> + KBUILD_SYM32 = n
> + endif
> +
> ifeq ($(KBUILD_SYM32), y)
> cflags-$(KBUILD_SYM32) += -msym32 -DKBUILD_64BIT_SYM32
> else
> diff --git a/arch/mips/generic/Platform b/arch/mips/generic/Platform
> index 0c03623f3897..2be9947814ad 100644
> --- a/arch/mips/generic/Platform
> +++ b/arch/mips/generic/Platform
> @@ -12,7 +12,12 @@
> cflags-$(CONFIG_MACH_INGENIC_SOC) +=
> -I$(srctree)/arch/mips/include/asm/mach-ingenic
> cflags-$(CONFIG_MIPS_GENERIC) +=
> -I$(srctree)/arch/mips/include/asm/mach-generic
>
> +ifndef (CONFIG_USE_XKPHYS)
> load-$(CONFIG_MIPS_GENERIC) += 0xffffffff80100000
> +else
> +load-$(CONFIG_MIPS_GENERIC) += 0xa800000080100000
> +endif
Better to make load address configurable.
> +
> all-$(CONFIG_MIPS_GENERIC) += vmlinux.gz.itb
>
> its-y := vmlinux.its.S
> diff --git a/arch/mips/include/asm/addrspace.h
> b/arch/mips/include/asm/addrspace.h
> index 59a48c60a065..8dc500d8e66d 100644
> --- a/arch/mips/include/asm/addrspace.h
> +++ b/arch/mips/include/asm/addrspace.h
> @@ -65,10 +65,15 @@
> #define XKSSEG _CONST64_(0x4000000000000000)
> #define XKPHYS _CONST64_(0x8000000000000000)
> #define XKSEG _CONST64_(0xc000000000000000)
> +#if !defined(CONFIG_USE_XKPHYS)
> #define CKSEG0 _CONST64_(0xffffffff80000000)
> #define CKSEG1 _CONST64_(0xffffffffa0000000)
> #define CKSSEG _CONST64_(0xffffffffc0000000)
> #define CKSEG3 _CONST64_(0xffffffffe0000000)
> +#else
> +#define CKSEG0 XKPHYS_CM_CACHED
> +#define CKSEG1 XKPHYS_CM_UNCACHED
> +#endif /* !defined(CONFIG_USE_XKPHYS) */
>
> #define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0)
> #define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1)
> @@ -126,8 +131,11 @@
> #define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p))
> #define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p))
> #define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK)
> -#define PHYS_TO_XKPHYS(cm, a) (XKPHYS | (_ACAST64_(cm) << 59) | (a))
> -
> +#define XKPHYS_CM(cm) (XKPHYS | (_ACAST64_(cm) << 59))
> +#define PHYS_TO_XKPHYS(cm, a) (XKPHYS_CM(cm) | (a))
> +#define XKPHYS_CM_CACHED (XKPHYS_CM(K_CALG_COH_SHAREABLE))
> +#define XKPHYS_CM_UNCACHED (XKPHYS_CM(K_CALG_UNCACHED))
> +#define IS_XKPHYS(a) (((a) >> 62) == 2)
> /*
> * The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting
> * the region, 3 bits for the CCA mode. This leaves 59 bits of which the
> diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h
> index 23c67c0871b1..15d8d69de455 100644
> --- a/arch/mips/include/asm/mips-cm.h
> +++ b/arch/mips/include/asm/mips-cm.h
> @@ -311,6 +311,7 @@ GCR_CX_ACCESSOR_RW(32, 0x018, other)
> /* GCR_Cx_RESET_BASE - Configure where powered up cores will fetch from */
> GCR_CX_ACCESSOR_RW(32, 0x020, reset_base)
> #define CM_GCR_Cx_RESET_BASE_BEVEXCBASE GENMASK(31, 12)
> +#define CM_GCR_Cx_RESET_BASE_MODE BIT(1)
>
> /* GCR_Cx_ID - Identify the current core */
> GCR_CX_ACCESSOR_RO(32, 0x028, id)
> diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
> index 5978a8dfb917..53b8306da571 100644
> --- a/arch/mips/include/asm/page.h
> +++ b/arch/mips/include/asm/page.h
> @@ -176,7 +176,11 @@ static inline unsigned long ___pa(unsigned long x)
> * the compatibility segements ckseg0 or ckseg1, or it may
> * be in xkphys.
> */
> +#if defined(CONFIG_USE_XKPHYS)
> + return XPHYSADDR(x);
> +#else
> return x < CKSEG0 ? XPHYSADDR(x) : CPHYSADDR(x);
> +#endif
Dangerous, there might be some code passing KSEG0/1 address to __pa, so
we should not disregard it.
> }
>
> if (!IS_ENABLED(CONFIG_EVA)) {
> @@ -196,7 +200,11 @@ static inline unsigned long ___pa(unsigned long x)
> return x - PAGE_OFFSET + PHYS_OFFSET;
> }
> #define __pa(x) ___pa((unsigned long)(x))
> +#if IS_ENABLED(CONFIG_64BIT) && IS_ENABLED(CONFIG_USE_XKPHYS)
> +#define __va(x) ((void *)PHYS_TO_XKSEG_CACHED(x))
> +#else
> #define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET))
> +#endif
PAGE_OFFSET resolves to CAC_BASE anyway, so unnecessary.
> #include <asm/io.h>
>
> /*
> @@ -239,6 +247,8 @@ static inline unsigned long kaslr_offset(void)
> return __kaslr_offset;
> }
>
> +#define UNCAC_ADDR(addr) (UNCAC_BASE + __pa(addr))
> +
> #include <asm-generic/memory_model.h>
> #include <asm-generic/getorder.h>
>
> diff --git a/arch/mips/include/asm/vga.h b/arch/mips/include/asm/vga.h
> index 0136e0366698..e338e57d0784 100644
> --- a/arch/mips/include/asm/vga.h
> +++ b/arch/mips/include/asm/vga.h
> @@ -16,7 +16,11 @@
> * access the videoram directly without any black magic.
> */
>
> +#if defined(CONFIG_USE_XKPHYS)
> +#define VGA_MAP_MEM(x, s) UNCAC_ADDR(0x10000000L + (unsigned long)(x))
> +#else
> #define VGA_MAP_MEM(x, s) CKSEG1ADDR(0x10000000L + (unsigned long)(x))
> +#endif
VGA_MAP_MEM intends to work on some really legacy systems, it won't break
your platform, so better leave it as is.
>
> #define vga_readb(x) (*(x))
> #define vga_writeb(x, y) (*(y) = (x))
> diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
> index 64ecfdac6580..541f31a43a7f 100644
> --- a/arch/mips/kernel/cps-vec.S
> +++ b/arch/mips/kernel/cps-vec.S
> @@ -554,7 +554,11 @@ LEAF(mips_cps_cache_init)
> mul t1, t1, t0
> mul t1, t1, t2
>
> +#if defined(CONFIG_USE_XKPHYS)
> + PTR_LI a0, XKPHYS_CM_CACHED
> +#else
> li a0, CKSEG0
> +#endif
Unnecessary, KSEG0 address here are just for matching cache ways,
so there is no difference to use KSEG0 or XKPHYS.
If you are using XKPHYS here you must extarct CCA from bootinfo
or CP0 as it may varies on different systems.
> PTR_ADD a1, a0, t1
> 1: cache Index_Store_Tag_I, 0(a0)
> PTR_ADD a0, a0, t0
> @@ -581,7 +585,11 @@ icache_done:
> mul t1, t1, t0
> mul t1, t1, t2
>
> +#if defined(CONFIG_USE_XKPHYS)
> + PTR_LI a0, XKPHYS_CM_CACHED
> +#else
Ditto.
> li a0, CKSEG0
> +#endif
> PTR_ADDU a1, a0, t1
> PTR_SUBU a1, a1, t0
> 1: cache Index_Store_Tag_D, 0(a0)
> diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
> index b6de8e88c1bd..a002058e1838 100644
> --- a/arch/mips/kernel/genex.S
> +++ b/arch/mips/kernel/genex.S
> @@ -272,11 +272,25 @@ NESTED(except_vec_vi, 0, sp)
> .set push
> .set noreorder
> PTR_LA v1, except_vec_vi_handler
> +#if defined(CONFIG_USE_XKPHYS)
> +FEXPORT(except_vec_vi_63_48)
> + lui v0, 0 /* Patched - bits 63:48 */
> +FEXPORT(except_vec_vi_47_32)
> + ori v0, 0 /* Patched - bits 47:32 */
> + dsll v0, v0, 0x10
> +FEXPORT(except_vec_vi_31_16)
> + ori v0, 0 /* Patched - bits 31:16 */
> + dsll v0, v0, 0x10
> + jr v1
> +FEXPORT(except_vec_vi_15_0)
> + ori v0, 0 /* Patched - bits 15:0 */
> +#else /* defined(CONFIG_USE_XKPHYS) */
> FEXPORT(except_vec_vi_lui)
> lui v0, 0 /* Patched */
> jr v1
> FEXPORT(except_vec_vi_ori)
> ori v0, 0 /* Patched */
> +#endif /* defined(CONFIG_USE_XKPHYS) */
> .set pop
> END(except_vec_vi)
> EXPORT(except_vec_vi_end)
> diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
> index dd55d59b88db..47e76722a306 100644
> --- a/arch/mips/kernel/smp-cps.c
> +++ b/arch/mips/kernel/smp-cps.c
> @@ -34,10 +34,33 @@ static unsigned __init core_vpe_count(unsigned int
> cluster, unsigned core)
> return min(smp_max_threads, mips_cps_numvps(cluster, core));
> }
>
> +/**
> + * plat_core_entry - query reset vector for NMI/reset
> + *
> + * Returns low 32 bits of the reset vector
> + *
> + * This is used to fill 2 registers:
> + * - BEV Base (GCR_BEV_BASE) Offset: 0x0680
> + * - VP Local Reset Exception Base (GCR_CL_RESET_BASE,GCR_CO_RESET_BASE)
> + * Offset: 0x0020 (0x2020 relative to GCR_BASE_ADDR)
> + *
> + * In both registers, BIT(1) should be set in case it uses address in XKPHYS
> + * (as opposed to KSEG1). This bit defined as CM_GCR_Cx_RESET_BASE_MODE,
> + * using it unconditionally because for GCR_BEV_BASE its value is the same
> + */
> +static u32 plat_core_entry(void)
> +{
> +#if defined(CONFIG_USE_XKPHYS)
> + return (UNCAC_ADDR(mips_cps_core_entry) & 0xffffffff)
> + | CM_GCR_Cx_RESET_BASE_MODE;
> +#else
> + return CKSEG1ADDR((unsigned long)mips_cps_core_entry);
> +#endif
This is a CM3 feature, so perhaps we should handle it in a general
way.
> +}
> +
> static void __init cps_smp_setup(void)
> {
> unsigned int nclusters, ncores, nvpes, core_vpes;
> - unsigned long core_entry;
> int cl, c, v;
>
> /* Detect & record VPE topology */
> @@ -94,10 +117,8 @@ static void __init cps_smp_setup(void)
> /* Make core 0 coherent with everything */
> write_gcr_cl_coherence(0xff);
>
> - if (mips_cm_revision() >= CM_REV_CM3) {
> - core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry);
> - write_gcr_bev_base(core_entry);
> - }
> + if (mips_cm_revision() >= CM_REV_CM3)
> + write_gcr_bev_base(plat_core_entry());
>
> #ifdef CONFIG_MIPS_MT_FPAFF
> /* If we have an FPU, enroll ourselves in the FPU-full mask */
> @@ -213,7 +234,7 @@ static void boot_core(unsigned int core, unsigned
> int vpe_id)
> mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
>
> /* Set its reset vector */
> - write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry));
> + write_gcr_co_reset_base(plat_core_entry());
>
> /* Ensure its coherency is disabled */
> write_gcr_co_coherence(0);
> @@ -290,7 +311,6 @@ static int cps_boot_secondary(int cpu, struct
> task_struct *idle)
> unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
> struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
> struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id];
> - unsigned long core_entry;
> unsigned int remote;
> int err;
>
> @@ -314,8 +334,7 @@ static int cps_boot_secondary(int cpu, struct
> task_struct *idle)
>
> if (cpu_has_vp) {
> mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
> - core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry);
> - write_gcr_co_reset_base(core_entry);
> + write_gcr_co_reset_base(plat_core_entry());
> mips_cm_unlock_other();
> }
>
> diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
> index 246c6a6b0261..875594843626 100644
> --- a/arch/mips/kernel/traps.c
> +++ b/arch/mips/kernel/traps.c
> @@ -2091,11 +2091,20 @@ static void *set_vi_srs_handler(int n,
> vi_handler_t addr, int srs)
> * If no shadow set is selected then use the default handler
> * that does normal register saving and standard interrupt exit
> */
> - extern const u8 except_vec_vi[], except_vec_vi_lui[];
> - extern const u8 except_vec_vi_ori[], except_vec_vi_end[];
> + extern const u8 except_vec_vi[], except_vec_vi_end[];
> extern const u8 rollback_except_vec_vi[];
> const u8 *vec_start = using_rollback_handler() ?
> rollback_except_vec_vi : except_vec_vi;
> + const int handler_len = except_vec_vi_end - vec_start;
> +#if defined(CONFIG_USE_XKPHYS)
> + extern const u8 except_vec_vi_63_48[], except_vec_vi_47_32[];
> + extern const u8 except_vec_vi_31_16[], except_vec_vi_15_0[];
> + const int offset_63_48 = except_vec_vi_63_48 - vec_start;
> + const int offset_47_32 = except_vec_vi_47_32 - vec_start;
> + const int offset_31_16 = except_vec_vi_31_16 - vec_start;
> + const int offset_15_0 = except_vec_vi_15_0 - vec_start;
> +#else /* defined(CONFIG_USE_XKPHYS) */
> + extern const u8 except_vec_vi_lui[], except_vec_vi_ori[];
> #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
> const int lui_offset = except_vec_vi_lui - vec_start + 2;
> const int ori_offset = except_vec_vi_ori - vec_start + 2;
> @@ -2103,7 +2112,7 @@ static void *set_vi_srs_handler(int n,
> vi_handler_t addr, int srs)
> const int lui_offset = except_vec_vi_lui - vec_start;
> const int ori_offset = except_vec_vi_ori - vec_start;
> #endif
> - const int handler_len = except_vec_vi_end - vec_start;
> +#endif /* defined(CONFIG_USE_XKPHYS) */
>
> if (handler_len > VECTORSPACING) {
> /*
> @@ -2119,10 +2128,21 @@ static void *set_vi_srs_handler(int n,
> vi_handler_t addr, int srs)
> #else
> handler_len);
> #endif
> +#if defined(CONFIG_USE_XKPHYS)
> + h = (u16 *)(b + offset_63_48);
> + *h = (handler >> 48) & 0xffff;
> + h = (u16 *)(b + offset_47_32);
> + *h = (handler >> 32) & 0xffff;
> + h = (u16 *)(b + offset_31_16);
> + *h = (handler >> 16) & 0xffff;
> + h = (u16 *)(b + offset_15_0);
> + *h = (handler >> 0) & 0xffff;
> +#else /* defined(CONFIG_USE_XKPHYS) */
> h = (u16 *)(b + lui_offset);
> *h = (handler >> 16) & 0xffff;
> h = (u16 *)(b + ori_offset);
> *h = (handler & 0xffff);
> +#endif /* defined(CONFIG_USE_XKPHYS) */
> local_flush_icache_range((unsigned long)b,
> (unsigned long)(b+handler_len));
> }
> @@ -2332,7 +2352,11 @@ static const char panic_null_cerr[] =
> void set_uncached_handler(unsigned long offset, void *addr,
> unsigned long size)
> {
> +#if IS_ENABLED(CONFIG_64BIT) && IS_ENABLED(CONFIG_USE_XKPHYS)
> + unsigned long uncached_ebase = UNCAC_ADDR(ebase);
> +#else
> unsigned long uncached_ebase = CKSEG1ADDR(ebase);
> +#endif
>
> if (!addr)
> panic(panic_null_cerr);
> @@ -2384,9 +2408,11 @@ void __init trap_init(void)
> * EVA is special though as it allows segments to be rearranged
> * and to become uncached during cache error handling.
> */
> +#if !defined(CONFIG_USE_XKPHYS)
> if (!IS_ENABLED(CONFIG_EVA) && !WARN_ON(ebase_pa >= 0x20000000))
> ebase = CKSEG0ADDR(ebase_pa);
> else
> +#endif
> ebase = (unsigned long)phys_to_virt(ebase_pa);
> }
>
> diff --git a/arch/mips/lib/uncached.c b/arch/mips/lib/uncached.c
> index f80a67c092b6..8a78348a2dd7 100644
> --- a/arch/mips/lib/uncached.c
> +++ b/arch/mips/lib/uncached.c
> @@ -44,6 +44,10 @@ unsigned long run_uncached(void *func)
>
> __asm__("move %0, $sp" : "=r" (sp));
>
> +#if defined(CONFIG_USE_XKPHYS)
> + if (IS_XKPHYS(sp))
> + usp = UNCAC_ADDR(sp);
Unnecessary, the else if later is actually handling XKPHYS sp.
> +#else /* defined(CONFIG_USE_XKPHYS) */
> if (sp >= (long)CKSEG0 && sp < (long)CKSEG2)
> usp = CKSEG1ADDR(sp);
> #ifdef CONFIG_64BIT
> @@ -52,10 +56,15 @@ unsigned long run_uncached(void *func)
> usp = PHYS_TO_XKPHYS(K_CALG_UNCACHED,
> XKPHYS_TO_PHYS((long long)sp));
> #endif
> +#endif /* defined(CONFIG_USE_XKPHYS) */
> else {
> BUG();
> usp = sp;
> }
> +#if defined(CONFIG_USE_XKPHYS)
> + if (IS_XKPHYS(lfunc))
> + ufunc = UNCAC_ADDR(lfunc);
ditto.
> +#else /* defined(CONFIG_USE_XKPHYS) */
> if (lfunc >= (long)CKSEG0 && lfunc < (long)CKSEG2)
> ufunc = CKSEG1ADDR(lfunc);
> #ifdef CONFIG_64BIT
> @@ -64,6 +73,7 @@ unsigned long run_uncached(void *func)
> ufunc = PHYS_TO_XKPHYS(K_CALG_UNCACHED,
> XKPHYS_TO_PHYS((long long)lfunc));
> #endif
> +#endif /* defined(CONFIG_USE_XKPHYS) */
> else {
> BUG();
> ufunc = lfunc;
> diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
> index 5dcb525a8995..eb57283ec4e0 100644
> --- a/arch/mips/mm/init.c
> +++ b/arch/mips/mm/init.c
> @@ -427,7 +427,7 @@ void __init paging_init(void)
> free_area_init(max_zone_pfns);
> }
>
> -#ifdef CONFIG_64BIT
> +#if defined(CONFIG_64BIT) && !defined(CONFIG_USE_XKPHYS)
> static struct kcore_list kcore_kseg0;
> #endif
>
> @@ -470,7 +470,7 @@ void __init mem_init(void)
> setup_zero_pages(); /* Setup zeroed pages. */
> mem_init_free_highmem();
>
> -#ifdef CONFIG_64BIT
> +#if defined(CONFIG_64BIT) && !defined(CONFIG_USE_XKPHYS)
> if ((unsigned long) &_text > (unsigned long) CKSEG0)
> /* The -4 is a hack so that user tools don't have to handle
> the overflow. */
> --
> 2.40.1
Thanks.
--
- Jiaxun
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 02/11] MIPS: use virtual addresses from xkphys for MIPS64
2023-10-22 11:39 ` Jiaxun Yang
@ 2023-10-23 15:45 ` Gregory CLEMENT
0 siblings, 0 replies; 53+ messages in thread
From: Gregory CLEMENT @ 2023-10-23 15:45 UTC (permalink / raw)
To: Jiaxun Yang, paulburton, Thomas Bogendoerfer, linux-mips,
Rob Herring, Krzysztof Kozlowski, devicetree, linux-kernel
Cc: Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni
Hello Jiaxun,
> 在2023年10月4日十月 下午5:10，Gregory CLEMENT写道：
>> From: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
>>
>> Now 64-bit MIPS uses 32-bit compatible segments KSEG0 and KSEG1
>> to trivially map first 1/2 GByte of physical memory. This memory
>> used to run kernel. This mean, one should have memory installed
>> in this area in order for Linux to work.
>>
>> Kconfig CONFIG_USE_XKPHYS introduced; it adds support for kernel
>> to use virtual addresses from the XKPHYS segment for both cached
>> and uncached access. XKPHYS allows to access 2^48 bytes of
>> memory, thus allowing kernel to work with any memory
>> configuration.
>>
>> MIPS CPU sets KX bit in the CP0 status register at reset
>> if RESET_BASE_MODE (BIT 1) set in the GCR_CL_RESET_BASE.
>>
>> Reset vector should fit into 32-bit. If reset vector put outside of
>> KSEG1, BIT(1) should be set in this value.
>>
>> IRQ handler for CPU updated to generate 64-bit address for jump
>
> Please use existing KBUILD_SYM32 symbol.
Could you add more detail ?
Where do you think KBUILD_SYM32 symbol should be used ?
Gregory
>
> Thanks
> - Jiaxun
>
>>
>> Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
>> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
>> ---
>> arch/mips/Kconfig | 15 +++++++++++++
>> arch/mips/Makefile | 4 ++++
>> arch/mips/generic/Platform | 5 +++++
>> arch/mips/include/asm/addrspace.h | 12 ++++++++--
>> arch/mips/include/asm/mips-cm.h | 1 +
>> arch/mips/include/asm/page.h | 10 +++++++++
>> arch/mips/include/asm/vga.h | 4 ++++
>> arch/mips/kernel/cps-vec.S | 8 +++++++
>> arch/mips/kernel/genex.S | 14 ++++++++++++
>> arch/mips/kernel/smp-cps.c | 37 +++++++++++++++++++++++--------
>> arch/mips/kernel/traps.c | 32 +++++++++++++++++++++++---
>> arch/mips/lib/uncached.c | 10 +++++++++
>> arch/mips/mm/init.c | 4 ++--
>> 13 files changed, 140 insertions(+), 16 deletions(-)
>>
>> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
>> index bc8421859006..92832bbcca5d 100644
>> --- a/arch/mips/Kconfig
>> +++ b/arch/mips/Kconfig
>> @@ -2026,6 +2026,21 @@ config 64BIT
>>
>> endchoice
>>
>> +config USE_XKPHYS
>> + bool "use virtual address from XKPHYS"
>> + depends on 64BIT
>> + default n
>> + help
>> + By default, MIPS uses 32-bit compatible segments KSEG0 and KSEG1
>> + to trivially map first 1/2 GByte of physical memory. This mean,
>> + one should have memory installed in this area in order for Linux to
>> + work. With this option selected, kernel uses virtual addresses from
>> + the XKPHYS segment for both cached and uncached access. XKPHYS allows
>> + to access 2^48 bytes of memory, thus allowing to work with any memory
>> + configuration.
>> +
>> + Say N if not sure
>> +
>> config MIPS_VA_BITS_48
>> bool "48 bits virtual memory"
>> depends on 64BIT
>> diff --git a/arch/mips/Makefile b/arch/mips/Makefile
>> index f49807e1f19b..544ee8427cab 100644
>> --- a/arch/mips/Makefile
>> +++ b/arch/mips/Makefile
>> @@ -303,6 +303,10 @@ ifdef CONFIG_64BIT
>> endif
>> endif
>>
>> + ifdef CONFIG_USE_XKPHYS
>> + KBUILD_SYM32 = n
>> + endif
>> +
>> ifeq ($(KBUILD_SYM32), y)
>> cflags-$(KBUILD_SYM32) += -msym32 -DKBUILD_64BIT_SYM32
>> else
>> diff --git a/arch/mips/generic/Platform b/arch/mips/generic/Platform
>> index 0c03623f3897..2be9947814ad 100644
>> --- a/arch/mips/generic/Platform
>> +++ b/arch/mips/generic/Platform
>> @@ -12,7 +12,12 @@
>> cflags-$(CONFIG_MACH_INGENIC_SOC) +=
>> -I$(srctree)/arch/mips/include/asm/mach-ingenic
>> cflags-$(CONFIG_MIPS_GENERIC) +=
>> -I$(srctree)/arch/mips/include/asm/mach-generic
>>
>> +ifndef (CONFIG_USE_XKPHYS)
>> load-$(CONFIG_MIPS_GENERIC) += 0xffffffff80100000
>> +else
>> +load-$(CONFIG_MIPS_GENERIC) += 0xa800000080100000
>> +endif
>> +
>> all-$(CONFIG_MIPS_GENERIC) += vmlinux.gz.itb
>>
>> its-y := vmlinux.its.S
>> diff --git a/arch/mips/include/asm/addrspace.h
>> b/arch/mips/include/asm/addrspace.h
>> index 59a48c60a065..8dc500d8e66d 100644
>> --- a/arch/mips/include/asm/addrspace.h
>> +++ b/arch/mips/include/asm/addrspace.h
>> @@ -65,10 +65,15 @@
>> #define XKSSEG _CONST64_(0x4000000000000000)
>> #define XKPHYS _CONST64_(0x8000000000000000)
>> #define XKSEG _CONST64_(0xc000000000000000)
>> +#if !defined(CONFIG_USE_XKPHYS)
>> #define CKSEG0 _CONST64_(0xffffffff80000000)
>> #define CKSEG1 _CONST64_(0xffffffffa0000000)
>> #define CKSSEG _CONST64_(0xffffffffc0000000)
>> #define CKSEG3 _CONST64_(0xffffffffe0000000)
>> +#else
>> +#define CKSEG0 XKPHYS_CM_CACHED
>> +#define CKSEG1 XKPHYS_CM_UNCACHED
>> +#endif /* !defined(CONFIG_USE_XKPHYS) */
>>
>> #define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0)
>> #define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1)
>> @@ -126,8 +131,11 @@
>> #define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p))
>> #define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p))
>> #define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK)
>> -#define PHYS_TO_XKPHYS(cm, a) (XKPHYS | (_ACAST64_(cm) << 59) | (a))
>> -
>> +#define XKPHYS_CM(cm) (XKPHYS | (_ACAST64_(cm) << 59))
>> +#define PHYS_TO_XKPHYS(cm, a) (XKPHYS_CM(cm) | (a))
>> +#define XKPHYS_CM_CACHED (XKPHYS_CM(K_CALG_COH_SHAREABLE))
>> +#define XKPHYS_CM_UNCACHED (XKPHYS_CM(K_CALG_UNCACHED))
>> +#define IS_XKPHYS(a) (((a) >> 62) == 2)
>> /*
>> * The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting
>> * the region, 3 bits for the CCA mode. This leaves 59 bits of which the
>> diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h
>> index 23c67c0871b1..15d8d69de455 100644
>> --- a/arch/mips/include/asm/mips-cm.h
>> +++ b/arch/mips/include/asm/mips-cm.h
>> @@ -311,6 +311,7 @@ GCR_CX_ACCESSOR_RW(32, 0x018, other)
>> /* GCR_Cx_RESET_BASE - Configure where powered up cores will fetch from */
>> GCR_CX_ACCESSOR_RW(32, 0x020, reset_base)
>> #define CM_GCR_Cx_RESET_BASE_BEVEXCBASE GENMASK(31, 12)
>> +#define CM_GCR_Cx_RESET_BASE_MODE BIT(1)
>>
>> /* GCR_Cx_ID - Identify the current core */
>> GCR_CX_ACCESSOR_RO(32, 0x028, id)
>> diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
>> index 5978a8dfb917..53b8306da571 100644
>> --- a/arch/mips/include/asm/page.h
>> +++ b/arch/mips/include/asm/page.h
>> @@ -176,7 +176,11 @@ static inline unsigned long ___pa(unsigned long x)
>> * the compatibility segements ckseg0 or ckseg1, or it may
>> * be in xkphys.
>> */
>> +#if defined(CONFIG_USE_XKPHYS)
>> + return XPHYSADDR(x);
>> +#else
>> return x < CKSEG0 ? XPHYSADDR(x) : CPHYSADDR(x);
>> +#endif
>> }
>>
>> if (!IS_ENABLED(CONFIG_EVA)) {
>> @@ -196,7 +200,11 @@ static inline unsigned long ___pa(unsigned long x)
>> return x - PAGE_OFFSET + PHYS_OFFSET;
>> }
>> #define __pa(x) ___pa((unsigned long)(x))
>> +#if IS_ENABLED(CONFIG_64BIT) && IS_ENABLED(CONFIG_USE_XKPHYS)
>> +#define __va(x) ((void *)PHYS_TO_XKSEG_CACHED(x))
>> +#else
>> #define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET))
>> +#endif
>> #include <asm/io.h>
>>
>> /*
>> @@ -239,6 +247,8 @@ static inline unsigned long kaslr_offset(void)
>> return __kaslr_offset;
>> }
>>
>> +#define UNCAC_ADDR(addr) (UNCAC_BASE + __pa(addr))
>> +
>> #include <asm-generic/memory_model.h>
>> #include <asm-generic/getorder.h>
>>
>> diff --git a/arch/mips/include/asm/vga.h b/arch/mips/include/asm/vga.h
>> index 0136e0366698..e338e57d0784 100644
>> --- a/arch/mips/include/asm/vga.h
>> +++ b/arch/mips/include/asm/vga.h
>> @@ -16,7 +16,11 @@
>> * access the videoram directly without any black magic.
>> */
>>
>> +#if defined(CONFIG_USE_XKPHYS)
>> +#define VGA_MAP_MEM(x, s) UNCAC_ADDR(0x10000000L + (unsigned long)(x))
>> +#else
>> #define VGA_MAP_MEM(x, s) CKSEG1ADDR(0x10000000L + (unsigned long)(x))
>> +#endif
>>
>> #define vga_readb(x) (*(x))
>> #define vga_writeb(x, y) (*(y) = (x))
>> diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
>> index 64ecfdac6580..541f31a43a7f 100644
>> --- a/arch/mips/kernel/cps-vec.S
>> +++ b/arch/mips/kernel/cps-vec.S
>> @@ -554,7 +554,11 @@ LEAF(mips_cps_cache_init)
>> mul t1, t1, t0
>> mul t1, t1, t2
>>
>> +#if defined(CONFIG_USE_XKPHYS)
>> + PTR_LI a0, XKPHYS_CM_CACHED
>> +#else
>> li a0, CKSEG0
>> +#endif
>> PTR_ADD a1, a0, t1
>> 1: cache Index_Store_Tag_I, 0(a0)
>> PTR_ADD a0, a0, t0
>> @@ -581,7 +585,11 @@ icache_done:
>> mul t1, t1, t0
>> mul t1, t1, t2
>>
>> +#if defined(CONFIG_USE_XKPHYS)
>> + PTR_LI a0, XKPHYS_CM_CACHED
>> +#else
>> li a0, CKSEG0
>> +#endif
>> PTR_ADDU a1, a0, t1
>> PTR_SUBU a1, a1, t0
>> 1: cache Index_Store_Tag_D, 0(a0)
>> diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
>> index b6de8e88c1bd..a002058e1838 100644
>> --- a/arch/mips/kernel/genex.S
>> +++ b/arch/mips/kernel/genex.S
>> @@ -272,11 +272,25 @@ NESTED(except_vec_vi, 0, sp)
>> .set push
>> .set noreorder
>> PTR_LA v1, except_vec_vi_handler
>> +#if defined(CONFIG_USE_XKPHYS)
>> +FEXPORT(except_vec_vi_63_48)
>> + lui v0, 0 /* Patched - bits 63:48 */
>> +FEXPORT(except_vec_vi_47_32)
>> + ori v0, 0 /* Patched - bits 47:32 */
>> + dsll v0, v0, 0x10
>> +FEXPORT(except_vec_vi_31_16)
>> + ori v0, 0 /* Patched - bits 31:16 */
>> + dsll v0, v0, 0x10
>> + jr v1
>> +FEXPORT(except_vec_vi_15_0)
>> + ori v0, 0 /* Patched - bits 15:0 */
>> +#else /* defined(CONFIG_USE_XKPHYS) */
>> FEXPORT(except_vec_vi_lui)
>> lui v0, 0 /* Patched */
>> jr v1
>> FEXPORT(except_vec_vi_ori)
>> ori v0, 0 /* Patched */
>> +#endif /* defined(CONFIG_USE_XKPHYS) */
>> .set pop
>> END(except_vec_vi)
>> EXPORT(except_vec_vi_end)
>> diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
>> index dd55d59b88db..47e76722a306 100644
>> --- a/arch/mips/kernel/smp-cps.c
>> +++ b/arch/mips/kernel/smp-cps.c
>> @@ -34,10 +34,33 @@ static unsigned __init core_vpe_count(unsigned int
>> cluster, unsigned core)
>> return min(smp_max_threads, mips_cps_numvps(cluster, core));
>> }
>>
>> +/**
>> + * plat_core_entry - query reset vector for NMI/reset
>> + *
>> + * Returns low 32 bits of the reset vector
>> + *
>> + * This is used to fill 2 registers:
>> + * - BEV Base (GCR_BEV_BASE) Offset: 0x0680
>> + * - VP Local Reset Exception Base (GCR_CL_RESET_BASE,GCR_CO_RESET_BASE)
>> + * Offset: 0x0020 (0x2020 relative to GCR_BASE_ADDR)
>> + *
>> + * In both registers, BIT(1) should be set in case it uses address in XKPHYS
>> + * (as opposed to KSEG1). This bit defined as CM_GCR_Cx_RESET_BASE_MODE,
>> + * using it unconditionally because for GCR_BEV_BASE its value is the same
>> + */
>> +static u32 plat_core_entry(void)
>> +{
>> +#if defined(CONFIG_USE_XKPHYS)
>> + return (UNCAC_ADDR(mips_cps_core_entry) & 0xffffffff)
>> + | CM_GCR_Cx_RESET_BASE_MODE;
>> +#else
>> + return CKSEG1ADDR((unsigned long)mips_cps_core_entry);
>> +#endif
>> +}
>> +
>> static void __init cps_smp_setup(void)
>> {
>> unsigned int nclusters, ncores, nvpes, core_vpes;
>> - unsigned long core_entry;
>> int cl, c, v;
>>
>> /* Detect & record VPE topology */
>> @@ -94,10 +117,8 @@ static void __init cps_smp_setup(void)
>> /* Make core 0 coherent with everything */
>> write_gcr_cl_coherence(0xff);
>>
>> - if (mips_cm_revision() >= CM_REV_CM3) {
>> - core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry);
>> - write_gcr_bev_base(core_entry);
>> - }
>> + if (mips_cm_revision() >= CM_REV_CM3)
>> + write_gcr_bev_base(plat_core_entry());
>>
>> #ifdef CONFIG_MIPS_MT_FPAFF
>> /* If we have an FPU, enroll ourselves in the FPU-full mask */
>> @@ -213,7 +234,7 @@ static void boot_core(unsigned int core, unsigned
>> int vpe_id)
>> mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
>>
>> /* Set its reset vector */
>> - write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry));
>> + write_gcr_co_reset_base(plat_core_entry());
>>
>> /* Ensure its coherency is disabled */
>> write_gcr_co_coherence(0);
>> @@ -290,7 +311,6 @@ static int cps_boot_secondary(int cpu, struct
>> task_struct *idle)
>> unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
>> struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
>> struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id];
>> - unsigned long core_entry;
>> unsigned int remote;
>> int err;
>>
>> @@ -314,8 +334,7 @@ static int cps_boot_secondary(int cpu, struct
>> task_struct *idle)
>>
>> if (cpu_has_vp) {
>> mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
>> - core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry);
>> - write_gcr_co_reset_base(core_entry);
>> + write_gcr_co_reset_base(plat_core_entry());
>> mips_cm_unlock_other();
>> }
>>
>> diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
>> index 246c6a6b0261..875594843626 100644
>> --- a/arch/mips/kernel/traps.c
>> +++ b/arch/mips/kernel/traps.c
>> @@ -2091,11 +2091,20 @@ static void *set_vi_srs_handler(int n,
>> vi_handler_t addr, int srs)
>> * If no shadow set is selected then use the default handler
>> * that does normal register saving and standard interrupt exit
>> */
>> - extern const u8 except_vec_vi[], except_vec_vi_lui[];
>> - extern const u8 except_vec_vi_ori[], except_vec_vi_end[];
>> + extern const u8 except_vec_vi[], except_vec_vi_end[];
>> extern const u8 rollback_except_vec_vi[];
>> const u8 *vec_start = using_rollback_handler() ?
>> rollback_except_vec_vi : except_vec_vi;
>> + const int handler_len = except_vec_vi_end - vec_start;
>> +#if defined(CONFIG_USE_XKPHYS)
>> + extern const u8 except_vec_vi_63_48[], except_vec_vi_47_32[];
>> + extern const u8 except_vec_vi_31_16[], except_vec_vi_15_0[];
>> + const int offset_63_48 = except_vec_vi_63_48 - vec_start;
>> + const int offset_47_32 = except_vec_vi_47_32 - vec_start;
>> + const int offset_31_16 = except_vec_vi_31_16 - vec_start;
>> + const int offset_15_0 = except_vec_vi_15_0 - vec_start;
>> +#else /* defined(CONFIG_USE_XKPHYS) */
>> + extern const u8 except_vec_vi_lui[], except_vec_vi_ori[];
>> #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
>> const int lui_offset = except_vec_vi_lui - vec_start + 2;
>> const int ori_offset = except_vec_vi_ori - vec_start + 2;
>> @@ -2103,7 +2112,7 @@ static void *set_vi_srs_handler(int n,
>> vi_handler_t addr, int srs)
>> const int lui_offset = except_vec_vi_lui - vec_start;
>> const int ori_offset = except_vec_vi_ori - vec_start;
>> #endif
>> - const int handler_len = except_vec_vi_end - vec_start;
>> +#endif /* defined(CONFIG_USE_XKPHYS) */
>>
>> if (handler_len > VECTORSPACING) {
>> /*
>> @@ -2119,10 +2128,21 @@ static void *set_vi_srs_handler(int n,
>> vi_handler_t addr, int srs)
>> #else
>> handler_len);
>> #endif
>> +#if defined(CONFIG_USE_XKPHYS)
>> + h = (u16 *)(b + offset_63_48);
>> + *h = (handler >> 48) & 0xffff;
>> + h = (u16 *)(b + offset_47_32);
>> + *h = (handler >> 32) & 0xffff;
>> + h = (u16 *)(b + offset_31_16);
>> + *h = (handler >> 16) & 0xffff;
>> + h = (u16 *)(b + offset_15_0);
>> + *h = (handler >> 0) & 0xffff;
>> +#else /* defined(CONFIG_USE_XKPHYS) */
>> h = (u16 *)(b + lui_offset);
>> *h = (handler >> 16) & 0xffff;
>> h = (u16 *)(b + ori_offset);
>> *h = (handler & 0xffff);
>> +#endif /* defined(CONFIG_USE_XKPHYS) */
>> local_flush_icache_range((unsigned long)b,
>> (unsigned long)(b+handler_len));
>> }
>> @@ -2332,7 +2352,11 @@ static const char panic_null_cerr[] =
>> void set_uncached_handler(unsigned long offset, void *addr,
>> unsigned long size)
>> {
>> +#if IS_ENABLED(CONFIG_64BIT) && IS_ENABLED(CONFIG_USE_XKPHYS)
>> + unsigned long uncached_ebase = UNCAC_ADDR(ebase);
>> +#else
>> unsigned long uncached_ebase = CKSEG1ADDR(ebase);
>> +#endif
>>
>> if (!addr)
>> panic(panic_null_cerr);
>> @@ -2384,9 +2408,11 @@ void __init trap_init(void)
>> * EVA is special though as it allows segments to be rearranged
>> * and to become uncached during cache error handling.
>> */
>> +#if !defined(CONFIG_USE_XKPHYS)
>> if (!IS_ENABLED(CONFIG_EVA) && !WARN_ON(ebase_pa >= 0x20000000))
>> ebase = CKSEG0ADDR(ebase_pa);
>> else
>> +#endif
>> ebase = (unsigned long)phys_to_virt(ebase_pa);
>> }
>>
>> diff --git a/arch/mips/lib/uncached.c b/arch/mips/lib/uncached.c
>> index f80a67c092b6..8a78348a2dd7 100644
>> --- a/arch/mips/lib/uncached.c
>> +++ b/arch/mips/lib/uncached.c
>> @@ -44,6 +44,10 @@ unsigned long run_uncached(void *func)
>>
>> __asm__("move %0, $sp" : "=r" (sp));
>>
>> +#if defined(CONFIG_USE_XKPHYS)
>> + if (IS_XKPHYS(sp))
>> + usp = UNCAC_ADDR(sp);
>> +#else /* defined(CONFIG_USE_XKPHYS) */
>> if (sp >= (long)CKSEG0 && sp < (long)CKSEG2)
>> usp = CKSEG1ADDR(sp);
>> #ifdef CONFIG_64BIT
>> @@ -52,10 +56,15 @@ unsigned long run_uncached(void *func)
>> usp = PHYS_TO_XKPHYS(K_CALG_UNCACHED,
>> XKPHYS_TO_PHYS((long long)sp));
>> #endif
>> +#endif /* defined(CONFIG_USE_XKPHYS) */
>> else {
>> BUG();
>> usp = sp;
>> }
>> +#if defined(CONFIG_USE_XKPHYS)
>> + if (IS_XKPHYS(lfunc))
>> + ufunc = UNCAC_ADDR(lfunc);
>> +#else /* defined(CONFIG_USE_XKPHYS) */
>> if (lfunc >= (long)CKSEG0 && lfunc < (long)CKSEG2)
>> ufunc = CKSEG1ADDR(lfunc);
>> #ifdef CONFIG_64BIT
>> @@ -64,6 +73,7 @@ unsigned long run_uncached(void *func)
>> ufunc = PHYS_TO_XKPHYS(K_CALG_UNCACHED,
>> XKPHYS_TO_PHYS((long long)lfunc));
>> #endif
>> +#endif /* defined(CONFIG_USE_XKPHYS) */
>> else {
>> BUG();
>> ufunc = lfunc;
>> diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
>> index 5dcb525a8995..eb57283ec4e0 100644
>> --- a/arch/mips/mm/init.c
>> +++ b/arch/mips/mm/init.c
>> @@ -427,7 +427,7 @@ void __init paging_init(void)
>> free_area_init(max_zone_pfns);
>> }
>>
>> -#ifdef CONFIG_64BIT
>> +#if defined(CONFIG_64BIT) && !defined(CONFIG_USE_XKPHYS)
>> static struct kcore_list kcore_kseg0;
>> #endif
>>
>> @@ -470,7 +470,7 @@ void __init mem_init(void)
>> setup_zero_pages(); /* Setup zeroed pages. */
>> mem_init_free_highmem();
>>
>> -#ifdef CONFIG_64BIT
>> +#if defined(CONFIG_64BIT) && !defined(CONFIG_USE_XKPHYS)
>> if ((unsigned long) &_text > (unsigned long) CKSEG0)
>> /* The -4 is a hack so that user tools don't have to handle
>> the overflow. */
>> --
>> 2.40.1
>
> --
> - Jiaxun
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 01/11] MIPS: compressed: Use correct instruction for 64 bit code
2023-10-04 16:10 ` [PATCH 01/11] MIPS: compressed: Use correct instruction for 64 bit code Gregory CLEMENT
2023-10-05 6:40 ` Philippe Mathieu-Daudé
@ 2023-10-24 1:49 ` Florian Fainelli
1 sibling, 0 replies; 53+ messages in thread
From: Florian Fainelli @ 2023-10-24 1:49 UTC (permalink / raw)
To: Gregory CLEMENT, Paul Burton, Thomas Bogendoerfer, linux-mips,
Rob Herring, Krzysztof Kozlowski, devicetree, linux-kernel
Cc: Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni
On 10/4/2023 9:10 AM, Gregory CLEMENT wrote:
> The code clearing BSS already use macro or use correct instruction
> depending id the CPU is 32 bits or 64 bits.
s/id/if/
> However, a few
> instructions remained 32 bits only.
>
> By using the accurate MACRO, it is now possible to deal with memory
> address beyond 32 bits. As a side effect, when using 64bits processor,
> it also divides the loop number needed to clear the BSS by 2.
>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
> ---
> arch/mips/boot/compressed/head.S | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/mips/boot/compressed/head.S b/arch/mips/boot/compressed/head.S
> index 5795d0af1e1b..d237a834b85e 100644
> --- a/arch/mips/boot/compressed/head.S
> +++ b/arch/mips/boot/compressed/head.S
> @@ -25,8 +25,8 @@
> /* Clear BSS */
> PTR_LA a0, _edata
> PTR_LA a2, _end
> -1: sw zero, 0(a0)
> - addiu a0, a0, 4
> +1: PTR_S zero, 0(a0)
> + PTR_ADDIU a0, a0, PTRSIZE
> bne a2, a0, 1b
>
> PTR_LA a0, (.heap) /* heap address */
--
Florian
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 03/11] MIPS: support RAM beyond 32-bit
2023-10-12 20:40 ` Jiaxun Yang
@ 2023-10-24 9:05 ` Maciej W. Rozycki
0 siblings, 0 replies; 53+ messages in thread
From: Maciej W. Rozycki @ 2023-10-24 9:05 UTC (permalink / raw)
To: Jiaxun Yang
Cc: Gregory CLEMENT, paulburton, Thomas Bogendoerfer, linux-mips,
Rob Herring, Krzysztof Kozlowski, devicetree, linux-kernel,
Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni
On Thu, 12 Oct 2023, Jiaxun Yang wrote:
> > There is a kind of mirror but its physical address start at 0x8000000
> > so beyond the first 512MBytes that are used for KSEG0.
>
> Really, KSEG0 range is 0x00000000 to 0x20000000, and 0x08000000 to 0x10000000
> is definitely within that range.
>
> But I'd agree that 0x08000000 to 0x10000000 (32MB) seems too small for kernel
> text and data. So yeah, it makes sense to load kernel into XKPHYS.
Hmm, my calculation indicates the range shown spans 128MiB, which I think
is usually suitably large to hold kernel static text and data even for the
richest configurations. Regardless, loading into XKPHYS isn't wrong, with
some platforms we've been doing it for decades now.
Maciej
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 02/11] MIPS: use virtual addresses from xkphys for MIPS64
2023-10-22 16:42 ` Jiaxun Yang
@ 2023-10-24 16:08 ` Gregory CLEMENT
0 siblings, 0 replies; 53+ messages in thread
From: Gregory CLEMENT @ 2023-10-24 16:08 UTC (permalink / raw)
To: Jiaxun Yang, paulburton, Thomas Bogendoerfer, linux-mips,
Rob Herring, Krzysztof Kozlowski, devicetree, linux-kernel
Cc: Vladimir Kondratiev, Tawfik Bayouk, Alexandre Belloni,
Théo Lebrun, Thomas Petazzoni
"Jiaxun Yang" <jiaxun.yang@flygoat.com> writes:
> 在2023年10月4日十月 下午5:10，Gregory CLEMENT写道：
>> From: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
>>
>> Now 64-bit MIPS uses 32-bit compatible segments KSEG0 and KSEG1
>> to trivially map first 1/2 GByte of physical memory. This memory
>> used to run kernel. This mean, one should have memory installed
>> in this area in order for Linux to work.
>>
>> Kconfig CONFIG_USE_XKPHYS introduced; it adds support for kernel
>> to use virtual addresses from the XKPHYS segment for both cached
>> and uncached access. XKPHYS allows to access 2^48 bytes of
>> memory, thus allowing kernel to work with any memory
>> configuration.
>>
>> MIPS CPU sets KX bit in the CP0 status register at reset
>> if RESET_BASE_MODE (BIT 1) set in the GCR_CL_RESET_BASE.
>>
>> Reset vector should fit into 32-bit. If reset vector put outside of
>> KSEG1, BIT(1) should be set in this value.
>>
>> IRQ handler for CPU updated to generate 64-bit address for jump
>
> So I just spend some time to review and test this patch on QEMU,
> comments below:
Thanks for your time.
>
>>
>> Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
>> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
>> ---
>> arch/mips/Kconfig | 15 +++++++++++++
>> arch/mips/Makefile | 4 ++++
>> arch/mips/generic/Platform | 5 +++++
>> arch/mips/include/asm/addrspace.h | 12 ++++++++--
>> arch/mips/include/asm/mips-cm.h | 1 +
>> arch/mips/include/asm/page.h | 10 +++++++++
>> arch/mips/include/asm/vga.h | 4 ++++
>> arch/mips/kernel/cps-vec.S | 8 +++++++
>> arch/mips/kernel/genex.S | 14 ++++++++++++
>> arch/mips/kernel/smp-cps.c | 37 +++++++++++++++++++++++--------
>> arch/mips/kernel/traps.c | 32 +++++++++++++++++++++++---
>> arch/mips/lib/uncached.c | 10 +++++++++
>> arch/mips/mm/init.c | 4 ++--
>> 13 files changed, 140 insertions(+), 16 deletions(-)
>>
>> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
>> index bc8421859006..92832bbcca5d 100644
>> --- a/arch/mips/Kconfig
>> +++ b/arch/mips/Kconfig
>> @@ -2026,6 +2026,21 @@ config 64BIT
>>
>> endchoice
>>
>> +config USE_XKPHYS
>> + bool "use virtual address from XKPHYS"
>> + depends on 64BIT
>> + default n
>> + help
>> + By default, MIPS uses 32-bit compatible segments KSEG0 and KSEG1
>> + to trivially map first 1/2 GByte of physical memory. This mean,
>> + one should have memory installed in this area in order for Linux to
>> + work. With this option selected, kernel uses virtual addresses from
>> + the XKPHYS segment for both cached and uncached access. XKPHYS allows
>> + to access 2^48 bytes of memory, thus allowing to work with any memory
>> + configuration.
>> +
>> + Say N if not sure
>> +
>> config MIPS_VA_BITS_48
>> bool "48 bits virtual memory"
>> depends on 64BIT
>> diff --git a/arch/mips/Makefile b/arch/mips/Makefile
>> index f49807e1f19b..544ee8427cab 100644
>> --- a/arch/mips/Makefile
>> +++ b/arch/mips/Makefile
>> @@ -303,6 +303,10 @@ ifdef CONFIG_64BIT
>> endif
>> endif
>>
>> + ifdef CONFIG_USE_XKPHYS
>> + KBUILD_SYM32 = n
>> + endif
>> +
>> ifeq ($(KBUILD_SYM32), y)
>> cflags-$(KBUILD_SYM32) += -msym32 -DKBUILD_64BIT_SYM32
>> else
>> diff --git a/arch/mips/generic/Platform b/arch/mips/generic/Platform
>> index 0c03623f3897..2be9947814ad 100644
>> --- a/arch/mips/generic/Platform
>> +++ b/arch/mips/generic/Platform
>> @@ -12,7 +12,12 @@
>> cflags-$(CONFIG_MACH_INGENIC_SOC) +=
>> -I$(srctree)/arch/mips/include/asm/mach-ingenic
>> cflags-$(CONFIG_MIPS_GENERIC) +=
>> -I$(srctree)/arch/mips/include/asm/mach-generic
>>
>> +ifndef (CONFIG_USE_XKPHYS)
>> load-$(CONFIG_MIPS_GENERIC) += 0xffffffff80100000
>> +else
>> +load-$(CONFIG_MIPS_GENERIC) += 0xa800000080100000
>> +endif
>
> Better to make load address configurable.
OK I prepared a patch for it.
>
>> +
>> all-$(CONFIG_MIPS_GENERIC) += vmlinux.gz.itb
>>
>> its-y := vmlinux.its.S
>> diff --git a/arch/mips/include/asm/addrspace.h
>> b/arch/mips/include/asm/addrspace.h
>> index 59a48c60a065..8dc500d8e66d 100644
>> --- a/arch/mips/include/asm/addrspace.h
>> +++ b/arch/mips/include/asm/addrspace.h
>> @@ -65,10 +65,15 @@
>> #define XKSSEG _CONST64_(0x4000000000000000)
>> #define XKPHYS _CONST64_(0x8000000000000000)
>> #define XKSEG _CONST64_(0xc000000000000000)
>> +#if !defined(CONFIG_USE_XKPHYS)
>> #define CKSEG0 _CONST64_(0xffffffff80000000)
>> #define CKSEG1 _CONST64_(0xffffffffa0000000)
>> #define CKSSEG _CONST64_(0xffffffffc0000000)
>> #define CKSEG3 _CONST64_(0xffffffffe0000000)
>> +#else
>> +#define CKSEG0 XKPHYS_CM_CACHED
>> +#define CKSEG1 XKPHYS_CM_UNCACHED
>> +#endif /* !defined(CONFIG_USE_XKPHYS) */
>>
>> #define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0)
>> #define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1)
>> @@ -126,8 +131,11 @@
>> #define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p))
>> #define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p))
>> #define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK)
>> -#define PHYS_TO_XKPHYS(cm, a) (XKPHYS | (_ACAST64_(cm) << 59) | (a))
>> -
>> +#define XKPHYS_CM(cm) (XKPHYS | (_ACAST64_(cm) << 59))
>> +#define PHYS_TO_XKPHYS(cm, a) (XKPHYS_CM(cm) | (a))
>> +#define XKPHYS_CM_CACHED (XKPHYS_CM(K_CALG_COH_SHAREABLE))
>> +#define XKPHYS_CM_UNCACHED (XKPHYS_CM(K_CALG_UNCACHED))
>> +#define IS_XKPHYS(a) (((a) >> 62) == 2)
>> /*
>> * The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting
>> * the region, 3 bits for the CCA mode. This leaves 59 bits of which the
>> diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h
>> index 23c67c0871b1..15d8d69de455 100644
>> --- a/arch/mips/include/asm/mips-cm.h
>> +++ b/arch/mips/include/asm/mips-cm.h
>> @@ -311,6 +311,7 @@ GCR_CX_ACCESSOR_RW(32, 0x018, other)
>> /* GCR_Cx_RESET_BASE - Configure where powered up cores will fetch from */
>> GCR_CX_ACCESSOR_RW(32, 0x020, reset_base)
>> #define CM_GCR_Cx_RESET_BASE_BEVEXCBASE GENMASK(31, 12)
>> +#define CM_GCR_Cx_RESET_BASE_MODE BIT(1)
>>
>> /* GCR_Cx_ID - Identify the current core */
>> GCR_CX_ACCESSOR_RO(32, 0x028, id)
>> diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
>> index 5978a8dfb917..53b8306da571 100644
>> --- a/arch/mips/include/asm/page.h
>> +++ b/arch/mips/include/asm/page.h
>> @@ -176,7 +176,11 @@ static inline unsigned long ___pa(unsigned long x)
>> * the compatibility segements ckseg0 or ckseg1, or it may
>> * be in xkphys.
>> */
>> +#if defined(CONFIG_USE_XKPHYS)
>> + return XPHYSADDR(x);
>> +#else
>> return x < CKSEG0 ? XPHYSADDR(x) : CPHYSADDR(x);
>> +#endif
>
> Dangerous, there might be some code passing KSEG0/1 address to __pa, so
> we should not disregard it.
I don't see any code doing it, but to be safe I will remove it.
>
>> }
>>
>> if (!IS_ENABLED(CONFIG_EVA)) {
>> @@ -196,7 +200,11 @@ static inline unsigned long ___pa(unsigned long x)
>> return x - PAGE_OFFSET + PHYS_OFFSET;
>> }
>> #define __pa(x) ___pa((unsigned long)(x))
>> +#if IS_ENABLED(CONFIG_64BIT) && IS_ENABLED(CONFIG_USE_XKPHYS)
>> +#define __va(x) ((void *)PHYS_TO_XKSEG_CACHED(x))
>> +#else
>> #define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET))
>> +#endif
>
> PAGE_OFFSET resolves to CAC_BASE anyway, so unnecessary.
OK, there was a lot of indirection but in the end it almost the same
indeed.
Gregory
>
>> #include <asm/io.h>
>>
>> /*
>> @@ -239,6 +247,8 @@ static inline unsigned long kaslr_offset(void)
>> return __kaslr_offset;
>> }
>>
>> +#define UNCAC_ADDR(addr) (UNCAC_BASE + __pa(addr))
>> +
>> #include <asm-generic/memory_model.h>
>> #include <asm-generic/getorder.h>
>>
>> diff --git a/arch/mips/include/asm/vga.h b/arch/mips/include/asm/vga.h
>> index 0136e0366698..e338e57d0784 100644
>> --- a/arch/mips/include/asm/vga.h
>> +++ b/arch/mips/include/asm/vga.h
>> @@ -16,7 +16,11 @@
>> * access the videoram directly without any black magic.
>> */
>>
>> +#if defined(CONFIG_USE_XKPHYS)
>> +#define VGA_MAP_MEM(x, s) UNCAC_ADDR(0x10000000L + (unsigned long)(x))
>> +#else
>> #define VGA_MAP_MEM(x, s) CKSEG1ADDR(0x10000000L + (unsigned long)(x))
>> +#endif
>
> VGA_MAP_MEM intends to work on some really legacy systems, it won't break
> your platform, so better leave it as is.
OK maybe I will still put a comment here.
>
>>
>> #define vga_readb(x) (*(x))
>> #define vga_writeb(x, y) (*(y) = (x))
>> diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
>> index 64ecfdac6580..541f31a43a7f 100644
>> --- a/arch/mips/kernel/cps-vec.S
>> +++ b/arch/mips/kernel/cps-vec.S
>> @@ -554,7 +554,11 @@ LEAF(mips_cps_cache_init)
>> mul t1, t1, t0
>> mul t1, t1, t2
>>
>> +#if defined(CONFIG_USE_XKPHYS)
>> + PTR_LI a0, XKPHYS_CM_CACHED
>> +#else
>> li a0, CKSEG0
>> +#endif
>
> Unnecessary, KSEG0 address here are just for matching cache ways,
> so there is no difference to use KSEG0 or XKPHYS.
>
> If you are using XKPHYS here you must extarct CCA from bootinfo
> or CP0 as it may varies on different systems.
>
>> PTR_ADD a1, a0, t1
>> 1: cache Index_Store_Tag_I, 0(a0)
>> PTR_ADD a0, a0, t0
>> @@ -581,7 +585,11 @@ icache_done:
>> mul t1, t1, t0
>> mul t1, t1, t2
>>
>> +#if defined(CONFIG_USE_XKPHYS)
>> + PTR_LI a0, XKPHYS_CM_CACHED
>> +#else
>
> Ditto.
>
>> li a0, CKSEG0
>> +#endif
>> PTR_ADDU a1, a0, t1
>> PTR_SUBU a1, a1, t0
>> 1: cache Index_Store_Tag_D, 0(a0)
>> diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
>> index b6de8e88c1bd..a002058e1838 100644
>> --- a/arch/mips/kernel/genex.S
>> +++ b/arch/mips/kernel/genex.S
>> @@ -272,11 +272,25 @@ NESTED(except_vec_vi, 0, sp)
>> .set push
>> .set noreorder
>> PTR_LA v1, except_vec_vi_handler
>> +#if defined(CONFIG_USE_XKPHYS)
>> +FEXPORT(except_vec_vi_63_48)
>> + lui v0, 0 /* Patched - bits 63:48 */
>> +FEXPORT(except_vec_vi_47_32)
>> + ori v0, 0 /* Patched - bits 47:32 */
>> + dsll v0, v0, 0x10
>> +FEXPORT(except_vec_vi_31_16)
>> + ori v0, 0 /* Patched - bits 31:16 */
>> + dsll v0, v0, 0x10
>> + jr v1
>> +FEXPORT(except_vec_vi_15_0)
>> + ori v0, 0 /* Patched - bits 15:0 */
>> +#else /* defined(CONFIG_USE_XKPHYS) */
>> FEXPORT(except_vec_vi_lui)
>> lui v0, 0 /* Patched */
>> jr v1
>> FEXPORT(except_vec_vi_ori)
>> ori v0, 0 /* Patched */
>> +#endif /* defined(CONFIG_USE_XKPHYS) */
>> .set pop
>> END(except_vec_vi)
>> EXPORT(except_vec_vi_end)
>> diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
>> index dd55d59b88db..47e76722a306 100644
>> --- a/arch/mips/kernel/smp-cps.c
>> +++ b/arch/mips/kernel/smp-cps.c
>> @@ -34,10 +34,33 @@ static unsigned __init core_vpe_count(unsigned int
>> cluster, unsigned core)
>> return min(smp_max_threads, mips_cps_numvps(cluster, core));
>> }
>>
>> +/**
>> + * plat_core_entry - query reset vector for NMI/reset
>> + *
>> + * Returns low 32 bits of the reset vector
>> + *
>> + * This is used to fill 2 registers:
>> + * - BEV Base (GCR_BEV_BASE) Offset: 0x0680
>> + * - VP Local Reset Exception Base (GCR_CL_RESET_BASE,GCR_CO_RESET_BASE)
>> + * Offset: 0x0020 (0x2020 relative to GCR_BASE_ADDR)
>> + *
>> + * In both registers, BIT(1) should be set in case it uses address in XKPHYS
>> + * (as opposed to KSEG1). This bit defined as CM_GCR_Cx_RESET_BASE_MODE,
>> + * using it unconditionally because for GCR_BEV_BASE its value is the same
>> + */
>> +static u32 plat_core_entry(void)
>> +{
>> +#if defined(CONFIG_USE_XKPHYS)
>> + return (UNCAC_ADDR(mips_cps_core_entry) & 0xffffffff)
>> + | CM_GCR_Cx_RESET_BASE_MODE;
>> +#else
>> + return CKSEG1ADDR((unsigned long)mips_cps_core_entry);
>> +#endif
>
> This is a CM3 feature, so perhaps we should handle it in a general
> way.
>
>> +}
>> +
>> static void __init cps_smp_setup(void)
>> {
>> unsigned int nclusters, ncores, nvpes, core_vpes;
>> - unsigned long core_entry;
>> int cl, c, v;
>>
>> /* Detect & record VPE topology */
>> @@ -94,10 +117,8 @@ static void __init cps_smp_setup(void)
>> /* Make core 0 coherent with everything */
>> write_gcr_cl_coherence(0xff);
>>
>> - if (mips_cm_revision() >= CM_REV_CM3) {
>> - core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry);
>> - write_gcr_bev_base(core_entry);
>> - }
>> + if (mips_cm_revision() >= CM_REV_CM3)
>> + write_gcr_bev_base(plat_core_entry());
>>
>> #ifdef CONFIG_MIPS_MT_FPAFF
>> /* If we have an FPU, enroll ourselves in the FPU-full mask */
>> @@ -213,7 +234,7 @@ static void boot_core(unsigned int core, unsigned
>> int vpe_id)
>> mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
>>
>> /* Set its reset vector */
>> - write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry));
>> + write_gcr_co_reset_base(plat_core_entry());
>>
>> /* Ensure its coherency is disabled */
>> write_gcr_co_coherence(0);
>> @@ -290,7 +311,6 @@ static int cps_boot_secondary(int cpu, struct
>> task_struct *idle)
>> unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
>> struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
>> struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id];
>> - unsigned long core_entry;
>> unsigned int remote;
>> int err;
>>
>> @@ -314,8 +334,7 @@ static int cps_boot_secondary(int cpu, struct
>> task_struct *idle)
>>
>> if (cpu_has_vp) {
>> mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
>> - core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry);
>> - write_gcr_co_reset_base(core_entry);
>> + write_gcr_co_reset_base(plat_core_entry());
>> mips_cm_unlock_other();
>> }
>>
>> diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
>> index 246c6a6b0261..875594843626 100644
>> --- a/arch/mips/kernel/traps.c
>> +++ b/arch/mips/kernel/traps.c
>> @@ -2091,11 +2091,20 @@ static void *set_vi_srs_handler(int n,
>> vi_handler_t addr, int srs)
>> * If no shadow set is selected then use the default handler
>> * that does normal register saving and standard interrupt exit
>> */
>> - extern const u8 except_vec_vi[], except_vec_vi_lui[];
>> - extern const u8 except_vec_vi_ori[], except_vec_vi_end[];
>> + extern const u8 except_vec_vi[], except_vec_vi_end[];
>> extern const u8 rollback_except_vec_vi[];
>> const u8 *vec_start = using_rollback_handler() ?
>> rollback_except_vec_vi : except_vec_vi;
>> + const int handler_len = except_vec_vi_end - vec_start;
>> +#if defined(CONFIG_USE_XKPHYS)
>> + extern const u8 except_vec_vi_63_48[], except_vec_vi_47_32[];
>> + extern const u8 except_vec_vi_31_16[], except_vec_vi_15_0[];
>> + const int offset_63_48 = except_vec_vi_63_48 - vec_start;
>> + const int offset_47_32 = except_vec_vi_47_32 - vec_start;
>> + const int offset_31_16 = except_vec_vi_31_16 - vec_start;
>> + const int offset_15_0 = except_vec_vi_15_0 - vec_start;
>> +#else /* defined(CONFIG_USE_XKPHYS) */
>> + extern const u8 except_vec_vi_lui[], except_vec_vi_ori[];
>> #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
>> const int lui_offset = except_vec_vi_lui - vec_start + 2;
>> const int ori_offset = except_vec_vi_ori - vec_start + 2;
>> @@ -2103,7 +2112,7 @@ static void *set_vi_srs_handler(int n,
>> vi_handler_t addr, int srs)
>> const int lui_offset = except_vec_vi_lui - vec_start;
>> const int ori_offset = except_vec_vi_ori - vec_start;
>> #endif
>> - const int handler_len = except_vec_vi_end - vec_start;
>> +#endif /* defined(CONFIG_USE_XKPHYS) */
>>
>> if (handler_len > VECTORSPACING) {
>> /*
>> @@ -2119,10 +2128,21 @@ static void *set_vi_srs_handler(int n,
>> vi_handler_t addr, int srs)
>> #else
>> handler_len);
>> #endif
>> +#if defined(CONFIG_USE_XKPHYS)
>> + h = (u16 *)(b + offset_63_48);
>> + *h = (handler >> 48) & 0xffff;
>> + h = (u16 *)(b + offset_47_32);
>> + *h = (handler >> 32) & 0xffff;
>> + h = (u16 *)(b + offset_31_16);
>> + *h = (handler >> 16) & 0xffff;
>> + h = (u16 *)(b + offset_15_0);
>> + *h = (handler >> 0) & 0xffff;
>> +#else /* defined(CONFIG_USE_XKPHYS) */
>> h = (u16 *)(b + lui_offset);
>> *h = (handler >> 16) & 0xffff;
>> h = (u16 *)(b + ori_offset);
>> *h = (handler & 0xffff);
>> +#endif /* defined(CONFIG_USE_XKPHYS) */
>> local_flush_icache_range((unsigned long)b,
>> (unsigned long)(b+handler_len));
>> }
>> @@ -2332,7 +2352,11 @@ static const char panic_null_cerr[] =
>> void set_uncached_handler(unsigned long offset, void *addr,
>> unsigned long size)
>> {
>> +#if IS_ENABLED(CONFIG_64BIT) && IS_ENABLED(CONFIG_USE_XKPHYS)
>> + unsigned long uncached_ebase = UNCAC_ADDR(ebase);
>> +#else
>> unsigned long uncached_ebase = CKSEG1ADDR(ebase);
>> +#endif
>>
>> if (!addr)
>> panic(panic_null_cerr);
>> @@ -2384,9 +2408,11 @@ void __init trap_init(void)
>> * EVA is special though as it allows segments to be rearranged
>> * and to become uncached during cache error handling.
>> */
>> +#if !defined(CONFIG_USE_XKPHYS)
>> if (!IS_ENABLED(CONFIG_EVA) && !WARN_ON(ebase_pa >= 0x20000000))
>> ebase = CKSEG0ADDR(ebase_pa);
>> else
>> +#endif
>> ebase = (unsigned long)phys_to_virt(ebase_pa);
>> }
>>
>> diff --git a/arch/mips/lib/uncached.c b/arch/mips/lib/uncached.c
>> index f80a67c092b6..8a78348a2dd7 100644
>> --- a/arch/mips/lib/uncached.c
>> +++ b/arch/mips/lib/uncached.c
>> @@ -44,6 +44,10 @@ unsigned long run_uncached(void *func)
>>
>> __asm__("move %0, $sp" : "=r" (sp));
>>
>> +#if defined(CONFIG_USE_XKPHYS)
>> + if (IS_XKPHYS(sp))
>> + usp = UNCAC_ADDR(sp);
>
> Unnecessary, the else if later is actually handling XKPHYS sp.
>
>> +#else /* defined(CONFIG_USE_XKPHYS) */
>> if (sp >= (long)CKSEG0 && sp < (long)CKSEG2)
>> usp = CKSEG1ADDR(sp);
>> #ifdef CONFIG_64BIT
>> @@ -52,10 +56,15 @@ unsigned long run_uncached(void *func)
>> usp = PHYS_TO_XKPHYS(K_CALG_UNCACHED,
>> XKPHYS_TO_PHYS((long long)sp));
>> #endif
>> +#endif /* defined(CONFIG_USE_XKPHYS) */
>> else {
>> BUG();
>> usp = sp;
>> }
>> +#if defined(CONFIG_USE_XKPHYS)
>> + if (IS_XKPHYS(lfunc))
>> + ufunc = UNCAC_ADDR(lfunc);
>
> ditto.
>
>> +#else /* defined(CONFIG_USE_XKPHYS) */
>> if (lfunc >= (long)CKSEG0 && lfunc < (long)CKSEG2)
>> ufunc = CKSEG1ADDR(lfunc);
>> #ifdef CONFIG_64BIT
>> @@ -64,6 +73,7 @@ unsigned long run_uncached(void *func)
>> ufunc = PHYS_TO_XKPHYS(K_CALG_UNCACHED,
>> XKPHYS_TO_PHYS((long long)lfunc));
>> #endif
>> +#endif /* defined(CONFIG_USE_XKPHYS) */
>> else {
>> BUG();
>> ufunc = lfunc;
>> diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
>> index 5dcb525a8995..eb57283ec4e0 100644
>> --- a/arch/mips/mm/init.c
>> +++ b/arch/mips/mm/init.c
>> @@ -427,7 +427,7 @@ void __init paging_init(void)
>> free_area_init(max_zone_pfns);
>> }
>>
>> -#ifdef CONFIG_64BIT
>> +#if defined(CONFIG_64BIT) && !defined(CONFIG_USE_XKPHYS)
>> static struct kcore_list kcore_kseg0;
>> #endif
>>
>> @@ -470,7 +470,7 @@ void __init mem_init(void)
>> setup_zero_pages(); /* Setup zeroed pages. */
>> mem_init_free_highmem();
>>
>> -#ifdef CONFIG_64BIT
>> +#if defined(CONFIG_64BIT) && !defined(CONFIG_USE_XKPHYS)
>> if ((unsigned long) &_text > (unsigned long) CKSEG0)
>> /* The -4 is a hack so that user tools don't have to handle
>> the overflow. */
>> --
>> 2.40.1
>
> Thanks.
>
> --
> - Jiaxun
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
^ permalink raw reply [flat|nested] 53+ messages in thread
end of thread, other threads:[~2023-10-24 16:08 UTC | newest]
Thread overview: 53+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-10-04 16:10 [PATCH 00/11] Add support for the Mobileye EyeQ5 SoC Gregory CLEMENT
2023-10-04 16:10 ` [PATCH 01/11] MIPS: compressed: Use correct instruction for 64 bit code Gregory CLEMENT
2023-10-05 6:40 ` Philippe Mathieu-Daudé
2023-10-24 1:49 ` Florian Fainelli
2023-10-04 16:10 ` [PATCH 02/11] MIPS: use virtual addresses from xkphys for MIPS64 Gregory CLEMENT
2023-10-12 15:34 ` Thomas Bogendoerfer
2023-10-22 11:52 ` Jiaxun Yang
2023-10-22 11:39 ` Jiaxun Yang
2023-10-23 15:45 ` Gregory CLEMENT
2023-10-22 16:42 ` Jiaxun Yang
2023-10-24 16:08 ` Gregory CLEMENT
2023-10-04 16:10 ` [PATCH 03/11] MIPS: support RAM beyond 32-bit Gregory CLEMENT
2023-10-06 11:21 ` Arnd Bergmann
2023-10-07 20:14 ` Jiaxun Yang
2023-10-09 15:59 ` Gregory CLEMENT
2023-10-10 8:55 ` Jiaxun Yang
2023-10-11 14:46 ` Gregory CLEMENT
2023-10-12 20:40 ` Jiaxun Yang
2023-10-24 9:05 ` Maciej W. Rozycki
2023-10-04 16:10 ` [PATCH 04/11] dt-bindings: Add vendor prefix for Mobileye Vision Technologies Ltd Gregory CLEMENT
2023-10-05 6:34 ` Philippe Mathieu-Daudé
2023-10-06 16:32 ` Rob Herring
2023-10-04 16:10 ` [PATCH 05/11] dt-bindings: mips: cpu: Add I-Class I6500 Multiprocessor Core Gregory CLEMENT
2023-10-05 6:31 ` Philippe Mathieu-Daudé
2023-10-05 14:39 ` Serge Semin
2023-10-05 14:51 ` Gregory CLEMENT
2023-10-05 15:23 ` Serge Semin
2023-10-06 10:48 ` Arnd Bergmann
2023-10-06 16:40 ` Rob Herring
2023-10-09 15:32 ` Gregory CLEMENT
2023-10-09 18:48 ` Arnd Bergmann
2023-10-10 10:13 ` Serge Semin
2023-10-05 14:47 ` Sergio Paracuellos
2023-10-04 16:10 ` [PATCH 06/11] dt-bindings: mips: Add bindings for Mobileye SoCs Gregory CLEMENT
2023-10-04 16:47 ` Rob Herring
2023-10-05 14:55 ` Gregory CLEMENT
2023-10-06 16:50 ` Rob Herring
2023-10-04 16:10 ` [PATCH 07/11] dt-bindings: mfd: syscon: Document EyeQ5 OLB Gregory CLEMENT
2023-10-06 16:54 ` Rob Herring
2023-10-09 15:49 ` Gregory CLEMENT
2023-10-04 16:10 ` [PATCH 08/11] MIPS: mobileye: Add EyeQ5 dtsi Gregory CLEMENT
2023-10-04 16:41 ` Rob Herring
2023-10-05 15:17 ` Gregory CLEMENT
2023-10-04 16:10 ` [PATCH 09/11] MIPS: mobileye: Add EPM5 device tree Gregory CLEMENT
2023-10-06 11:18 ` Arnd Bergmann
2023-10-09 14:51 ` Gregory CLEMENT
2023-10-04 16:10 ` [PATCH 10/11] MIPS: generic: Add support for Mobileye EyeQ5 Gregory CLEMENT
2023-10-05 0:08 ` kernel test robot
2023-10-06 14:47 ` Arnd Bergmann
2023-10-09 14:58 ` Gregory CLEMENT
2023-10-04 16:10 ` [PATCH 11/11] MAINTAINERS: Add entry for Mobileye MIPS SoCs Gregory CLEMENT
2023-10-06 11:11 ` Arnd Bergmann
2023-10-09 15:06 ` Gregory CLEMENT
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