* [PATCH v5 1/2] arm64: tegra: add ACONNECT, ADMA and AGIC nodes
@ 2019-06-13 10:41 Sameer Pujar
2019-06-13 10:41 ` [PATCH v5 2/2] arm64: tegra: enable ACONNECT, ADMA and AGIC Sameer Pujar
2019-06-13 14:09 ` [PATCH v5 1/2] arm64: tegra: add ACONNECT, ADMA and AGIC nodes Jon Hunter
0 siblings, 2 replies; 5+ messages in thread
From: Sameer Pujar @ 2019-06-13 10:41 UTC (permalink / raw)
To: thierry.reding, jonathanh, robh+dt, mark.rutland
Cc: mkumard, devicetree, linux-tegra, linux-kernel, Sameer Pujar
Add DT nodes for following devices on Tegra186 and Tegra194
* ACONNECT
* ADMA
* AGIC
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
---
changes from previous revision
* fixed size value for ranges property in aconnect
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 67 ++++++++++++++++++++++++++++++++
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 67 ++++++++++++++++++++++++++++++++
2 files changed, 134 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 426ac0b..5e9fe7e 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -1295,4 +1295,71 @@
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-parent = <&gic>;
};
+
+ aconnect {
+ compatible = "nvidia,tegra210-aconnect";
+ clocks = <&bpmp TEGRA186_CLK_APE>,
+ <&bpmp TEGRA186_CLK_APB2APE>;
+ clock-names = "ape", "apb2ape";
+ power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x02900000 0x0 0x02900000 0x200000>;
+ status = "disabled";
+
+ dma-controller@2930000 {
+ compatible = "nvidia,tegra186-adma";
+ reg = <0x02930000 0x50000>;
+ interrupt-parent = <&agic>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ clocks = <&bpmp TEGRA186_CLK_AHUB>;
+ clock-names = "d_audio";
+ status = "disabled";
+ };
+
+ agic: interrupt-controller@2a41000 {
+ compatible = "nvidia,tegra210-agic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x02a41000 0x1000>,
+ <0x02a42000 0x2000>;
+ interrupts = <GIC_SPI 145
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&bpmp TEGRA186_CLK_APE>;
+ clock-names = "clk";
+ status = "disabled";
+ };
+ };
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index c77ca21..a60ed5f 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -1054,4 +1054,71 @@
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-parent = <&gic>;
};
+
+ aconnect {
+ compatible = "nvidia,tegra210-aconnect";
+ clocks = <&bpmp TEGRA194_CLK_APE>,
+ <&bpmp TEGRA194_CLK_APB2APE>;
+ clock-names = "ape", "apb2ape";
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x02900000 0x0 0x02900000 0x200000>;
+ status = "disabled";
+
+ dma-controller@2930000 {
+ compatible = "nvidia,tegra186-adma";
+ reg = <0x02930000 0x50000>;
+ interrupt-parent = <&agic>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ clocks = <&bpmp TEGRA194_CLK_AHUB>;
+ clock-names = "d_audio";
+ status = "disabled";
+ };
+
+ agic: interrupt-controller@2a41000 {
+ compatible = "nvidia,tegra210-agic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x02a41000 0x1000>,
+ <0x02a42000 0x2000>;
+ interrupts = <GIC_SPI 145
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&bpmp TEGRA194_CLK_APE>;
+ clock-names = "clk";
+ status = "disabled";
+ };
+ };
};
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v5 2/2] arm64: tegra: enable ACONNECT, ADMA and AGIC
2019-06-13 10:41 [PATCH v5 1/2] arm64: tegra: add ACONNECT, ADMA and AGIC nodes Sameer Pujar
@ 2019-06-13 10:41 ` Sameer Pujar
2019-06-13 14:09 ` [PATCH v5 1/2] arm64: tegra: add ACONNECT, ADMA and AGIC nodes Jon Hunter
1 sibling, 0 replies; 5+ messages in thread
From: Sameer Pujar @ 2019-06-13 10:41 UTC (permalink / raw)
To: thierry.reding, jonathanh, robh+dt, mark.rutland
Cc: mkumard, devicetree, linux-tegra, linux-kernel, Sameer Pujar
Enable ACONNECT, ADMA and AGIC devices for following platforms
* Jetson TX2
* Jetson Xavier
Verified driver probe path and devices get registered fine.
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
---
changes from previous revision - None
arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 12 ++++++++++++
arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 12 ++++++++++++
2 files changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
index 5102de1..d055913 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
@@ -298,4 +298,16 @@
vin-supply = <&vdd_5v0_sys>;
};
};
+
+ aconnect {
+ status = "okay";
+
+ dma-controller@2930000 {
+ status = "okay";
+ };
+
+ interrupt-controller@2a41000 {
+ status = "okay";
+ };
+ };
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
index 6e6df65..c4a57959 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
@@ -167,4 +167,16 @@
};
};
};
+
+ aconnect {
+ status = "okay";
+
+ dma-controller@2930000 {
+ status = "okay";
+ };
+
+ interrupt-controller@2a41000 {
+ status = "okay";
+ };
+ };
};
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v5 1/2] arm64: tegra: add ACONNECT, ADMA and AGIC nodes
2019-06-13 10:41 [PATCH v5 1/2] arm64: tegra: add ACONNECT, ADMA and AGIC nodes Sameer Pujar
2019-06-13 10:41 ` [PATCH v5 2/2] arm64: tegra: enable ACONNECT, ADMA and AGIC Sameer Pujar
@ 2019-06-13 14:09 ` Jon Hunter
2019-06-13 14:43 ` Sameer Pujar
1 sibling, 1 reply; 5+ messages in thread
From: Jon Hunter @ 2019-06-13 14:09 UTC (permalink / raw)
To: Sameer Pujar, thierry.reding, robh+dt, mark.rutland
Cc: mkumard, devicetree, linux-tegra, linux-kernel
On 13/06/2019 11:41, Sameer Pujar wrote:
> Add DT nodes for following devices on Tegra186 and Tegra194
> * ACONNECT
> * ADMA
> * AGIC
>
> Signed-off-by: Sameer Pujar <spujar@nvidia.com>
> ---
> changes from previous revision
> * fixed size value for ranges property in aconnect
>
> arch/arm64/boot/dts/nvidia/tegra186.dtsi | 67 ++++++++++++++++++++++++++++++++
> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 67 ++++++++++++++++++++++++++++++++
> 2 files changed, 134 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> index 426ac0b..5e9fe7e 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> @@ -1295,4 +1295,71 @@
> (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> interrupt-parent = <&gic>;
> };
> +
> + aconnect {
> + compatible = "nvidia,tegra210-aconnect";
> + clocks = <&bpmp TEGRA186_CLK_APE>,
> + <&bpmp TEGRA186_CLK_APB2APE>;
> + clock-names = "ape", "apb2ape";
> + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x02900000 0x0 0x02900000 0x200000>;
> + status = "disabled";
> +
> + dma-controller@2930000 {
> + compatible = "nvidia,tegra186-adma";
> + reg = <0x02930000 0x50000>;
Sorry but I have been double checking these register addresses and I
wonder if this should be a length of 0x10000. The 0x50000 includes all
the ranges where the registers are paged, so I don't think that this is
correct including these.
> + interrupt-parent = <&agic>;
> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
> + #dma-cells = <1>;
> + clocks = <&bpmp TEGRA186_CLK_AHUB>;
> + clock-names = "d_audio";
> + status = "disabled";
> + };
> +
> + agic: interrupt-controller@2a41000 {
I think that this should be 2a40000 but otherwise looks correct.
Sorry but you are too quick for me to keep up!
Cheers
Jon
--
nvpublic
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v5 1/2] arm64: tegra: add ACONNECT, ADMA and AGIC nodes
2019-06-13 14:09 ` [PATCH v5 1/2] arm64: tegra: add ACONNECT, ADMA and AGIC nodes Jon Hunter
@ 2019-06-13 14:43 ` Sameer Pujar
2019-06-13 15:01 ` Jon Hunter
0 siblings, 1 reply; 5+ messages in thread
From: Sameer Pujar @ 2019-06-13 14:43 UTC (permalink / raw)
To: Jon Hunter, thierry.reding, robh+dt, mark.rutland
Cc: mkumard, devicetree, linux-tegra, linux-kernel
On 6/13/2019 7:39 PM, Jon Hunter wrote:
> On 13/06/2019 11:41, Sameer Pujar wrote:
>> Add DT nodes for following devices on Tegra186 and Tegra194
>> * ACONNECT
>> * ADMA
>> * AGIC
>>
>> Signed-off-by: Sameer Pujar <spujar@nvidia.com>
>> ---
>> changes from previous revision
>> * fixed size value for ranges property in aconnect
>>
>> arch/arm64/boot/dts/nvidia/tegra186.dtsi | 67 ++++++++++++++++++++++++++++++++
>> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 67 ++++++++++++++++++++++++++++++++
>> 2 files changed, 134 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
>> index 426ac0b..5e9fe7e 100644
>> --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
>> +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
>> @@ -1295,4 +1295,71 @@
>> (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>> interrupt-parent = <&gic>;
>> };
>> +
>> + aconnect {
>> + compatible = "nvidia,tegra210-aconnect";
>> + clocks = <&bpmp TEGRA186_CLK_APE>,
>> + <&bpmp TEGRA186_CLK_APB2APE>;
>> + clock-names = "ape", "apb2ape";
>> + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0x02900000 0x0 0x02900000 0x200000>;
>> + status = "disabled";
>> +
>> + dma-controller@2930000 {
>> + compatible = "nvidia,tegra186-adma";
>> + reg = <0x02930000 0x50000>;
> Sorry but I have been double checking these register addresses and I
> wonder if this should be a length of 0x10000. The 0x50000 includes all
> the ranges where the registers are paged, so I don't think that this is
> correct including these.
Is it because we don't have virtualization support yet?
and isn't the range 0x10000 covers only global register space, don't we
want to include page1 ADMA channel registers. In that case it would be
0x20000.
>
>> + interrupt-parent = <&agic>;
>> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
>> + #dma-cells = <1>;
>> + clocks = <&bpmp TEGRA186_CLK_AHUB>;
>> + clock-names = "d_audio";
>> + status = "disabled";
>> + };
>> +
>> + agic: interrupt-controller@2a41000 {
> I think that this should be 2a40000 but otherwise looks correct.
done.
> Sorry but you are too quick for me to keep up!
>
> Cheers
> Jon
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v5 1/2] arm64: tegra: add ACONNECT, ADMA and AGIC nodes
2019-06-13 14:43 ` Sameer Pujar
@ 2019-06-13 15:01 ` Jon Hunter
0 siblings, 0 replies; 5+ messages in thread
From: Jon Hunter @ 2019-06-13 15:01 UTC (permalink / raw)
To: Sameer Pujar, thierry.reding, robh+dt, mark.rutland
Cc: mkumard, devicetree, linux-tegra, linux-kernel
On 13/06/2019 15:43, Sameer Pujar wrote:
>
> On 6/13/2019 7:39 PM, Jon Hunter wrote:
>> On 13/06/2019 11:41, Sameer Pujar wrote:
>>> Add DT nodes for following devices on Tegra186 and Tegra194
>>> * ACONNECT
>>> * ADMA
>>> * AGIC
>>>
>>> Signed-off-by: Sameer Pujar <spujar@nvidia.com>
>>> ---
>>> changes from previous revision
>>> * fixed size value for ranges property in aconnect
>>>
>>> arch/arm64/boot/dts/nvidia/tegra186.dtsi | 67
>>> ++++++++++++++++++++++++++++++++
>>> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 67
>>> ++++++++++++++++++++++++++++++++
>>> 2 files changed, 134 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
>>> b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
>>> index 426ac0b..5e9fe7e 100644
>>> --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
>>> +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
>>> @@ -1295,4 +1295,71 @@
>>> (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>>> interrupt-parent = <&gic>;
>>> };
>>> +
>>> + aconnect {
>>> + compatible = "nvidia,tegra210-aconnect";
>>> + clocks = <&bpmp TEGRA186_CLK_APE>,
>>> + <&bpmp TEGRA186_CLK_APB2APE>;
>>> + clock-names = "ape", "apb2ape";
>>> + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> + ranges = <0x02900000 0x0 0x02900000 0x200000>;
>>> + status = "disabled";
>>> +
>>> + dma-controller@2930000 {
>>> + compatible = "nvidia,tegra186-adma";
>>> + reg = <0x02930000 0x50000>;
>> Sorry but I have been double checking these register addresses and I
>> wonder if this should be a length of 0x10000. The 0x50000 includes all
>> the ranges where the registers are paged, so I don't think that this is
>> correct including these.
> Is it because we don't have virtualization support yet?
Yes those are for virtulisation, but I don't believe we need them here.
> and isn't the range 0x10000 covers only global register space, don't we
> want to include page1 ADMA channel registers. In that case it would be
> 0x20000.
Yes, 0x20000 is correct indeed
Cheers
Jon
--
nvpublic
^ permalink raw reply [flat|nested] 5+ messages in thread
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2019-06-13 10:41 [PATCH v5 1/2] arm64: tegra: add ACONNECT, ADMA and AGIC nodes Sameer Pujar
2019-06-13 10:41 ` [PATCH v5 2/2] arm64: tegra: enable ACONNECT, ADMA and AGIC Sameer Pujar
2019-06-13 14:09 ` [PATCH v5 1/2] arm64: tegra: add ACONNECT, ADMA and AGIC nodes Jon Hunter
2019-06-13 14:43 ` Sameer Pujar
2019-06-13 15:01 ` Jon Hunter
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