* [PATCH v2] PCI: xilinx-nwl: Fix Multi MSI data programming
@ 2019-03-11 11:45 Bharat Kumar Gogada
2019-04-01 17:00 ` Bharat Kumar Gogada
2019-04-02 16:23 ` Ard Biesheuvel
0 siblings, 2 replies; 6+ messages in thread
From: Bharat Kumar Gogada @ 2019-03-11 11:45 UTC (permalink / raw)
To: lorenzo.pieralisi, bhelgaas
Cc: linux-pci, linux-arm-kernel, linux-kernel, Bharat Kumar Gogada
The current Multi MSI data programming fails if multiple end points
requesting MSI and multi MSI are connected with switch, i.e the current
multi MSI data being given is not considering the number of vectors
being requested in case of multi MSI.
Due to this if multiple end points are connected and requesting MSI
and multi MSI combination, the multi MSI data is ending up using
wrong MSI data, which might be used by different device.
Fix Multi MSI data programming with required alignment by
using number of vectors being requested.
Fixes: ab597d35ef11 ("PCI: xilinx-nwl: Add support for Xilinx NWL PCIe
Host Controller")
Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
---
V2:
- Added more description of fix
---
drivers/pci/controller/pcie-xilinx-nwl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c
index 81538d7..36669c5 100644
--- a/drivers/pci/controller/pcie-xilinx-nwl.c
+++ b/drivers/pci/controller/pcie-xilinx-nwl.c
@@ -484,7 +484,7 @@ static int nwl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
mutex_lock(&msi->lock);
bit = bitmap_find_next_zero_area(msi->bitmap, INT_PCI_MSI_NR, 0,
- nr_irqs, 0);
+ nr_irqs, nr_irqs - 1);
if (bit >= INT_PCI_MSI_NR) {
mutex_unlock(&msi->lock);
return -ENOSPC;
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* RE: [PATCH v2] PCI: xilinx-nwl: Fix Multi MSI data programming
2019-03-11 11:45 [PATCH v2] PCI: xilinx-nwl: Fix Multi MSI data programming Bharat Kumar Gogada
@ 2019-04-01 17:00 ` Bharat Kumar Gogada
2019-04-02 16:08 ` Lorenzo Pieralisi
2019-04-02 16:23 ` Ard Biesheuvel
1 sibling, 1 reply; 6+ messages in thread
From: Bharat Kumar Gogada @ 2019-04-01 17:00 UTC (permalink / raw)
To: Bharat Kumar Gogada, lorenzo.pieralisi, bhelgaas
Cc: linux-pci, linux-arm-kernel, linux-kernel
Hi All,
Please let me know if anyone has any inputs on this.
Regards,
Bharat
>
> The current Multi MSI data programming fails if multiple end points
> requesting MSI and multi MSI are connected with switch, i.e the current
> multi MSI data being given is not considering the number of vectors being
> requested in case of multi MSI.
> Due to this if multiple end points are connected and requesting MSI and
> multi MSI combination, the multi MSI data is ending up using wrong MSI
> data, which might be used by different device.
>
> Fix Multi MSI data programming with required alignment by using number
> of vectors being requested.
>
> Fixes: ab597d35ef11 ("PCI: xilinx-nwl: Add support for Xilinx NWL PCIe Host
> Controller")
> Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
> ---
> V2:
> - Added more description of fix
> ---
> drivers/pci/controller/pcie-xilinx-nwl.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c
> b/drivers/pci/controller/pcie-xilinx-nwl.c
> index 81538d7..36669c5 100644
> --- a/drivers/pci/controller/pcie-xilinx-nwl.c
> +++ b/drivers/pci/controller/pcie-xilinx-nwl.c
> @@ -484,7 +484,7 @@ static int nwl_irq_domain_alloc(struct irq_domain
> *domain, unsigned int virq,
>
> mutex_lock(&msi->lock);
> bit = bitmap_find_next_zero_area(msi->bitmap, INT_PCI_MSI_NR, 0,
> - nr_irqs, 0);
> + nr_irqs, nr_irqs - 1);
> if (bit >= INT_PCI_MSI_NR) {
> mutex_unlock(&msi->lock);
> return -ENOSPC;
> --
> 2.7.4
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2] PCI: xilinx-nwl: Fix Multi MSI data programming
2019-04-01 17:00 ` Bharat Kumar Gogada
@ 2019-04-02 16:08 ` Lorenzo Pieralisi
2019-04-04 11:48 ` Bharat Kumar Gogada
0 siblings, 1 reply; 6+ messages in thread
From: Lorenzo Pieralisi @ 2019-04-02 16:08 UTC (permalink / raw)
To: Bharat Kumar Gogada; +Cc: bhelgaas, linux-pci, linux-arm-kernel, linux-kernel
On Mon, Apr 01, 2019 at 05:00:40PM +0000, Bharat Kumar Gogada wrote:
> Hi All,
>
> Please let me know if anyone has any inputs on this.
>
> Regards,
> Bharat
> >
> > The current Multi MSI data programming fails if multiple end points
> > requesting MSI and multi MSI are connected with switch, i.e the current
> > multi MSI data being given is not considering the number of vectors being
> > requested in case of multi MSI.
> > Due to this if multiple end points are connected and requesting MSI and
> > multi MSI combination, the multi MSI data is ending up using wrong MSI
> > data, which might be used by different device.
> >
> > Fix Multi MSI data programming with required alignment by using number
> > of vectors being requested.
I still do not understand what you mean I am sorry. An example is worth
two thousand words, I would start with that as it stands this commit
log does not provide any information on what you are actually fixing.
Lorenzo
> > Fixes: ab597d35ef11 ("PCI: xilinx-nwl: Add support for Xilinx NWL PCIe Host
> > Controller")
> > Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
> > ---
> > V2:
> > - Added more description of fix
> > ---
> > drivers/pci/controller/pcie-xilinx-nwl.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c
> > b/drivers/pci/controller/pcie-xilinx-nwl.c
> > index 81538d7..36669c5 100644
> > --- a/drivers/pci/controller/pcie-xilinx-nwl.c
> > +++ b/drivers/pci/controller/pcie-xilinx-nwl.c
> > @@ -484,7 +484,7 @@ static int nwl_irq_domain_alloc(struct irq_domain
> > *domain, unsigned int virq,
> >
> > mutex_lock(&msi->lock);
> > bit = bitmap_find_next_zero_area(msi->bitmap, INT_PCI_MSI_NR, 0,
> > - nr_irqs, 0);
> > + nr_irqs, nr_irqs - 1);
> > if (bit >= INT_PCI_MSI_NR) {
> > mutex_unlock(&msi->lock);
> > return -ENOSPC;
> > --
> > 2.7.4
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2] PCI: xilinx-nwl: Fix Multi MSI data programming
2019-03-11 11:45 [PATCH v2] PCI: xilinx-nwl: Fix Multi MSI data programming Bharat Kumar Gogada
2019-04-01 17:00 ` Bharat Kumar Gogada
@ 2019-04-02 16:23 ` Ard Biesheuvel
2019-04-04 11:51 ` Bharat Kumar Gogada
1 sibling, 1 reply; 6+ messages in thread
From: Ard Biesheuvel @ 2019-04-02 16:23 UTC (permalink / raw)
To: Bharat Kumar Gogada
Cc: Lorenzo Pieralisi, Bjorn Helgaas, linux-pci,
Linux Kernel Mailing List, linux-arm-kernel
On Mon, 11 Mar 2019 at 12:46, Bharat Kumar Gogada
<bharat.kumar.gogada@xilinx.com> wrote:
>
> The current Multi MSI data programming fails if multiple end points
> requesting MSI and multi MSI are connected with switch, i.e the current
> multi MSI data being given is not considering the number of vectors
> being requested in case of multi MSI.
> Due to this if multiple end points are connected and requesting MSI
> and multi MSI combination, the multi MSI data is ending up using
> wrong MSI data, which might be used by different device.
>
> Fix Multi MSI data programming with required alignment by
> using number of vectors being requested.
>
> Fixes: ab597d35ef11 ("PCI: xilinx-nwl: Add support for Xilinx NWL PCIe
> Host Controller")
> Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
> ---
> V2:
> - Added more description of fix
> ---
> drivers/pci/controller/pcie-xilinx-nwl.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c
> index 81538d7..36669c5 100644
> --- a/drivers/pci/controller/pcie-xilinx-nwl.c
> +++ b/drivers/pci/controller/pcie-xilinx-nwl.c
> @@ -484,7 +484,7 @@ static int nwl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
>
> mutex_lock(&msi->lock);
> bit = bitmap_find_next_zero_area(msi->bitmap, INT_PCI_MSI_NR, 0,
> - nr_irqs, 0);
> + nr_irqs, nr_irqs - 1);
Are you sure nr_irqs is guaranteed to be a power of 2?
> if (bit >= INT_PCI_MSI_NR) {
> mutex_unlock(&msi->lock);
> return -ENOSPC;
> --
> 2.7.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH v2] PCI: xilinx-nwl: Fix Multi MSI data programming
2019-04-02 16:08 ` Lorenzo Pieralisi
@ 2019-04-04 11:48 ` Bharat Kumar Gogada
0 siblings, 0 replies; 6+ messages in thread
From: Bharat Kumar Gogada @ 2019-04-04 11:48 UTC (permalink / raw)
To: lorenzo.pieralisi; +Cc: bhelgaas, linux-pci, linux-arm-kernel, linux-kernel
> On Mon, Apr 01, 2019 at 05:00:40PM +0000, Bharat Kumar Gogada wrote:
> > Hi All,
> >
> > Please let me know if anyone has any inputs on this.
> >
> > Regards,
> > Bharat
> > >
> > > The current Multi MSI data programming fails if multiple end points
> > > requesting MSI and multi MSI are connected with switch, i.e the
> > > current multi MSI data being given is not considering the number of
> > > vectors being requested in case of multi MSI.
> > > Due to this if multiple end points are connected and requesting MSI
> > > and multi MSI combination, the multi MSI data is ending up using
> > > wrong MSI data, which might be used by different device.
> > >
> > > Fix Multi MSI data programming with required alignment by using
> > > number of vectors being requested.
>
> I still do not understand what you mean I am sorry. An example is worth
> two thousand words, I would start with that as it stands this commit log
> does not provide any information on what you are actually fixing.
>
Hi Lorenzo, Thanks for your time.
Yes, will add an example to describe the problem.
Regards,
Bharat
> > > Fixes: ab597d35ef11 ("PCI: xilinx-nwl: Add support for Xilinx NWL
> > > PCIe Host
> > > Controller")
> > > Signed-off-by: Bharat Kumar Gogada
> <bharat.kumar.gogada@xilinx.com>
> > > ---
> > > V2:
> > > - Added more description of fix
> > > ---
> > > drivers/pci/controller/pcie-xilinx-nwl.c | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c
> > > b/drivers/pci/controller/pcie-xilinx-nwl.c
> > > index 81538d7..36669c5 100644
> > > --- a/drivers/pci/controller/pcie-xilinx-nwl.c
> > > +++ b/drivers/pci/controller/pcie-xilinx-nwl.c
> > > @@ -484,7 +484,7 @@ static int nwl_irq_domain_alloc(struct
> > > irq_domain *domain, unsigned int virq,
> > >
> > > mutex_lock(&msi->lock);
> > > bit = bitmap_find_next_zero_area(msi->bitmap, INT_PCI_MSI_NR, 0,
> > > - nr_irqs, 0);
> > > + nr_irqs, nr_irqs - 1);
> > > if (bit >= INT_PCI_MSI_NR) {
> > > mutex_unlock(&msi->lock);
> > > return -ENOSPC;
> > > --
> > > 2.7.4
> >
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH v2] PCI: xilinx-nwl: Fix Multi MSI data programming
2019-04-02 16:23 ` Ard Biesheuvel
@ 2019-04-04 11:51 ` Bharat Kumar Gogada
0 siblings, 0 replies; 6+ messages in thread
From: Bharat Kumar Gogada @ 2019-04-04 11:51 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: lorenzo.pieralisi, Bjorn Helgaas, linux-pci,
Linux Kernel Mailing List, linux-arm-kernel
> Subject: Re: [PATCH v2] PCI: xilinx-nwl: Fix Multi MSI data programming
>
> On Mon, 11 Mar 2019 at 12:46, Bharat Kumar Gogada
> <bharat.kumar.gogada@xilinx.com> wrote:
> >
> > The current Multi MSI data programming fails if multiple end points
> > requesting MSI and multi MSI are connected with switch, i.e the
> > current multi MSI data being given is not considering the number of
> > vectors being requested in case of multi MSI.
> > Due to this if multiple end points are connected and requesting MSI
> > and multi MSI combination, the multi MSI data is ending up using wrong
> > MSI data, which might be used by different device.
> >
> > Fix Multi MSI data programming with required alignment by using number
> > of vectors being requested.
> >
> > Fixes: ab597d35ef11 ("PCI: xilinx-nwl: Add support for Xilinx NWL PCIe
> > Host Controller")
> > Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
> > ---
> > V2:
> > - Added more description of fix
> > ---
> > drivers/pci/controller/pcie-xilinx-nwl.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c
> > b/drivers/pci/controller/pcie-xilinx-nwl.c
> > index 81538d7..36669c5 100644
> > --- a/drivers/pci/controller/pcie-xilinx-nwl.c
> > +++ b/drivers/pci/controller/pcie-xilinx-nwl.c
> > @@ -484,7 +484,7 @@ static int nwl_irq_domain_alloc(struct irq_domain
> > *domain, unsigned int virq,
> >
> > mutex_lock(&msi->lock);
> > bit = bitmap_find_next_zero_area(msi->bitmap, INT_PCI_MSI_NR, 0,
> > - nr_irqs, 0);
> > + nr_irqs, nr_irqs - 1);
>
> Are you sure nr_irqs is guaranteed to be a power of 2?
Hi Ard, Thanks for your time.
After checking other source codes its not guaranteed, will add extra check and resend patch.
Regards,
Bharat
>
> > if (bit >= INT_PCI_MSI_NR) {
> > mutex_unlock(&msi->lock);
> > return -ENOSPC;
> > --
> > 2.7.4
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2019-04-04 11:51 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-03-11 11:45 [PATCH v2] PCI: xilinx-nwl: Fix Multi MSI data programming Bharat Kumar Gogada
2019-04-01 17:00 ` Bharat Kumar Gogada
2019-04-02 16:08 ` Lorenzo Pieralisi
2019-04-04 11:48 ` Bharat Kumar Gogada
2019-04-02 16:23 ` Ard Biesheuvel
2019-04-04 11:51 ` Bharat Kumar Gogada
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).