[PATCH v1 1/1] mmc: sdhci-acpi: Add support for NVIDIA BlueField-3 SoC

[PATCH v1 1/1] mmc: sdhci-acpi: Add support for NVIDIA BlueField-3 SoC

[Liming Sun]

This commit adds ACPI support for the BlueField-3 SoC which uses
the DWC_mshc eMMC controller. The boundary check logic in static
function dwcmshc_adma_write_desc() comes from sdhci-of-dwcmshc.c.

Signed-off-by: Liming Sun <limings@nvidia.com>
Reviewed-by: Khalil Blaiech <kblaiech@nvidia.com>
---
 drivers/mmc/host/sdhci-acpi.c | 64 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 64 insertions(+)

diff --git a/drivers/mmc/host/sdhci-acpi.c b/drivers/mmc/host/sdhci-acpi.c
index 54205e3..6448e94e 100644
--- a/drivers/mmc/host/sdhci-acpi.c
+++ b/drivers/mmc/host/sdhci-acpi.c
@@ -716,6 +716,68 @@ static int sdhci_acpi_emmc_amd_probe_slot(struct platform_device *pdev,
 	.priv_size	= sizeof(struct amd_sdhci_host),
 };
 
+/* Check DMA address/length boundary. */
+static inline bool dwcmshc_adma_boundary_ok(dma_addr_t addr, int len)
+{
+	return (addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1));
+}
+
+/*
+ * If DMA addr spans 128MB boundary, we split the DMA transfer into two
+ * so that each DMA transfer doesn't exceed the boundary.
+ */
+static void dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc,
+				    dma_addr_t addr, int len, unsigned int cmd)
+{
+	int tmplen, offset;
+
+	if (likely(!len || dwcmshc_adma_boundary_ok(addr, len))) {
+		sdhci_adma_write_desc(host, desc, addr, len, cmd);
+		return;
+	}
+
+	offset = addr & (SZ_128M - 1);
+	tmplen = SZ_128M - offset;
+	sdhci_adma_write_desc(host, desc, addr, tmplen, cmd);
+
+	addr += tmplen;
+	len -= tmplen;
+	sdhci_adma_write_desc(host, desc, addr, len, cmd);
+}
+
+static int sdhci_acpi_emmc_nvda_bf_probe_slot(struct platform_device *pdev,
+					      struct acpi_device *adev)
+{
+	struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
+	struct sdhci_host *host = c->host;
+	u32 extra;
+
+	/* Extra adma table cnt for cross 128M boundary handling. */
+	extra = DIV_ROUND_UP_ULL(dma_get_required_mask(&pdev->dev), SZ_128M);
+	extra = min(extra, (u32)SDHCI_MAX_SEGS);
+	host->adma_table_cnt += extra;
+
+	return 0;
+}
+
+static const struct sdhci_ops sdhci_acpi_ops_nvda_bf = {
+	.set_clock		= sdhci_set_clock,
+	.set_bus_width		= sdhci_set_bus_width,
+	.set_uhs_signaling	= sdhci_set_uhs_signaling,
+	.reset			= sdhci_reset,
+	.adma_write_desc	= dwcmshc_adma_write_desc,
+};
+
+static const struct sdhci_acpi_chip sdhci_acpi_chip_nvda_bf = {
+	.ops = &sdhci_acpi_ops_nvda_bf,
+};
+
+static const struct sdhci_acpi_slot sdhci_acpi_slot_nvda_bf_emmc = {
+	.chip		= &sdhci_acpi_chip_nvda_bf,
+	.caps		= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
+	.probe_slot	= sdhci_acpi_emmc_nvda_bf_probe_slot,
+};
+
 struct sdhci_acpi_uid_slot {
 	const char *hid;
 	const char *uid;
@@ -740,6 +802,7 @@ struct sdhci_acpi_uid_slot {
 	{ "QCOM8051", NULL, &sdhci_acpi_slot_qcom_sd_3v },
 	{ "QCOM8052", NULL, &sdhci_acpi_slot_qcom_sd },
 	{ "AMDI0040", NULL, &sdhci_acpi_slot_amd_emmc },
+	{ "MLNXBF30", NULL, &sdhci_acpi_slot_nvda_bf_emmc },
 	{ },
 };
 
@@ -757,6 +820,7 @@ struct sdhci_acpi_uid_slot {
 	{ "QCOM8051" },
 	{ "QCOM8052" },
 	{ "AMDI0040" },
+	{ "MLNXBF30" },
 	{ },
 };
 MODULE_DEVICE_TABLE(acpi, sdhci_acpi_ids);
-- 
1.8.3.1

Re: [PATCH v1 1/1] mmc: sdhci-acpi: Add support for NVIDIA BlueField-3 SoC

[Adrian Hunter]

On 12/03/21 3:48 pm, Liming Sun wrote:
> This commit adds ACPI support for the BlueField-3 SoC which uses
> the DWC_mshc eMMC controller. The boundary check logic in static
> function dwcmshc_adma_write_desc() comes from sdhci-of-dwcmshc.c.

Did you consider adding ACPI support to sdhci-of-dwcmshc.c ?
Other drivers have taken that approach, see sdhci-xenon.c or sdhci-iproc.c

> 
> Signed-off-by: Liming Sun <limings@nvidia.com>
> Reviewed-by: Khalil Blaiech <kblaiech@nvidia.com>
> ---
>  drivers/mmc/host/sdhci-acpi.c | 64 +++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 64 insertions(+)
> 
> diff --git a/drivers/mmc/host/sdhci-acpi.c b/drivers/mmc/host/sdhci-acpi.c
> index 54205e3..6448e94e 100644
> --- a/drivers/mmc/host/sdhci-acpi.c
> +++ b/drivers/mmc/host/sdhci-acpi.c
> @@ -716,6 +716,68 @@ static int sdhci_acpi_emmc_amd_probe_slot(struct platform_device *pdev,
>  	.priv_size	= sizeof(struct amd_sdhci_host),
>  };
>  
> +/* Check DMA address/length boundary. */
> +static inline bool dwcmshc_adma_boundary_ok(dma_addr_t addr, int len)
> +{
> +	return (addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1));
> +}
> +
> +/*
> + * If DMA addr spans 128MB boundary, we split the DMA transfer into two
> + * so that each DMA transfer doesn't exceed the boundary.
> + */
> +static void dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc,
> +				    dma_addr_t addr, int len, unsigned int cmd)
> +{
> +	int tmplen, offset;
> +
> +	if (likely(!len || dwcmshc_adma_boundary_ok(addr, len))) {
> +		sdhci_adma_write_desc(host, desc, addr, len, cmd);
> +		return;
> +	}
> +
> +	offset = addr & (SZ_128M - 1);
> +	tmplen = SZ_128M - offset;
> +	sdhci_adma_write_desc(host, desc, addr, tmplen, cmd);
> +
> +	addr += tmplen;
> +	len -= tmplen;
> +	sdhci_adma_write_desc(host, desc, addr, len, cmd);
> +}
> +
> +static int sdhci_acpi_emmc_nvda_bf_probe_slot(struct platform_device *pdev,
> +					      struct acpi_device *adev)
> +{
> +	struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
> +	struct sdhci_host *host = c->host;
> +	u32 extra;
> +
> +	/* Extra adma table cnt for cross 128M boundary handling. */
> +	extra = DIV_ROUND_UP_ULL(dma_get_required_mask(&pdev->dev), SZ_128M);
> +	extra = min(extra, (u32)SDHCI_MAX_SEGS);
> +	host->adma_table_cnt += extra;
> +
> +	return 0;
> +}
> +
> +static const struct sdhci_ops sdhci_acpi_ops_nvda_bf = {
> +	.set_clock		= sdhci_set_clock,
> +	.set_bus_width		= sdhci_set_bus_width,
> +	.set_uhs_signaling	= sdhci_set_uhs_signaling,
> +	.reset			= sdhci_reset,
> +	.adma_write_desc	= dwcmshc_adma_write_desc,
> +};
> +
> +static const struct sdhci_acpi_chip sdhci_acpi_chip_nvda_bf = {
> +	.ops = &sdhci_acpi_ops_nvda_bf,
> +};
> +
> +static const struct sdhci_acpi_slot sdhci_acpi_slot_nvda_bf_emmc = {
> +	.chip		= &sdhci_acpi_chip_nvda_bf,
> +	.caps		= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
> +	.probe_slot	= sdhci_acpi_emmc_nvda_bf_probe_slot,
> +};
> +
>  struct sdhci_acpi_uid_slot {
>  	const char *hid;
>  	const char *uid;
> @@ -740,6 +802,7 @@ struct sdhci_acpi_uid_slot {
>  	{ "QCOM8051", NULL, &sdhci_acpi_slot_qcom_sd_3v },
>  	{ "QCOM8052", NULL, &sdhci_acpi_slot_qcom_sd },
>  	{ "AMDI0040", NULL, &sdhci_acpi_slot_amd_emmc },
> +	{ "MLNXBF30", NULL, &sdhci_acpi_slot_nvda_bf_emmc },
>  	{ },
>  };
>  
> @@ -757,6 +820,7 @@ struct sdhci_acpi_uid_slot {
>  	{ "QCOM8051" },
>  	{ "QCOM8052" },
>  	{ "AMDI0040" },
> +	{ "MLNXBF30" },
>  	{ },
>  };
>  MODULE_DEVICE_TABLE(acpi, sdhci_acpi_ids);
> 

RE: [PATCH v1 1/1] mmc: sdhci-acpi: Add support for NVIDIA BlueField-3 SoC

[Liming Sun]

Thanks Adrian. Yes, I did consider adding this ACPI support into sdhci-of-dwcmshc.c, but not sure which one is the preferred way.
Is this (sdhci-of-dwcmshc.c) what you recommend? I'll post the revised changes in patch v2.

> -----Original Message-----
> From: Adrian Hunter <adrian.hunter@intel.com>
> Sent: Monday, March 15, 2021 4:34 AM
> To: Liming Sun <limings@nvidia.com>; Ulf Hansson <ulf.hansson@linaro.org>;
> Khalil Blaiech <kblaiech@nvidia.com>
> Cc: linux-mmc@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v1 1/1] mmc: sdhci-acpi: Add support for NVIDIA
> BlueField-3 SoC
> 
> On 12/03/21 3:48 pm, Liming Sun wrote:
> > This commit adds ACPI support for the BlueField-3 SoC which uses
> > the DWC_mshc eMMC controller. The boundary check logic in static
> > function dwcmshc_adma_write_desc() comes from sdhci-of-dwcmshc.c.
> 
> Did you consider adding ACPI support to sdhci-of-dwcmshc.c ?
> Other drivers have taken that approach, see sdhci-xenon.c or sdhci-iproc.c
> 
> >
> > Signed-off-by: Liming Sun <limings@nvidia.com>
> > Reviewed-by: Khalil Blaiech <kblaiech@nvidia.com>
> > ---
> >  drivers/mmc/host/sdhci-acpi.c | 64
> +++++++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 64 insertions(+)
> >
> > diff --git a/drivers/mmc/host/sdhci-acpi.c b/drivers/mmc/host/sdhci-acpi.c
> > index 54205e3..6448e94e 100644
> > --- a/drivers/mmc/host/sdhci-acpi.c
> > +++ b/drivers/mmc/host/sdhci-acpi.c
> > @@ -716,6 +716,68 @@ static int sdhci_acpi_emmc_amd_probe_slot(struct
> platform_device *pdev,
> >  	.priv_size	= sizeof(struct amd_sdhci_host),
> >  };
> >
> > +/* Check DMA address/length boundary. */
> > +static inline bool dwcmshc_adma_boundary_ok(dma_addr_t addr, int len)
> > +{
> > +	return (addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1));
> > +}
> > +
> > +/*
> > + * If DMA addr spans 128MB boundary, we split the DMA transfer into two
> > + * so that each DMA transfer doesn't exceed the boundary.
> > + */
> > +static void dwcmshc_adma_write_desc(struct sdhci_host *host, void
> **desc,
> > +				    dma_addr_t addr, int len, unsigned int cmd)
> > +{
> > +	int tmplen, offset;
> > +
> > +	if (likely(!len || dwcmshc_adma_boundary_ok(addr, len))) {
> > +		sdhci_adma_write_desc(host, desc, addr, len, cmd);
> > +		return;
> > +	}
> > +
> > +	offset = addr & (SZ_128M - 1);
> > +	tmplen = SZ_128M - offset;
> > +	sdhci_adma_write_desc(host, desc, addr, tmplen, cmd);
> > +
> > +	addr += tmplen;
> > +	len -= tmplen;
> > +	sdhci_adma_write_desc(host, desc, addr, len, cmd);
> > +}
> > +
> > +static int sdhci_acpi_emmc_nvda_bf_probe_slot(struct platform_device
> *pdev,
> > +					      struct acpi_device *adev)
> > +{
> > +	struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
> > +	struct sdhci_host *host = c->host;
> > +	u32 extra;
> > +
> > +	/* Extra adma table cnt for cross 128M boundary handling. */
> > +	extra = DIV_ROUND_UP_ULL(dma_get_required_mask(&pdev->dev),
> SZ_128M);
> > +	extra = min(extra, (u32)SDHCI_MAX_SEGS);
> > +	host->adma_table_cnt += extra;
> > +
> > +	return 0;
> > +}
> > +
> > +static const struct sdhci_ops sdhci_acpi_ops_nvda_bf = {
> > +	.set_clock		= sdhci_set_clock,
> > +	.set_bus_width		= sdhci_set_bus_width,
> > +	.set_uhs_signaling	= sdhci_set_uhs_signaling,
> > +	.reset			= sdhci_reset,
> > +	.adma_write_desc	= dwcmshc_adma_write_desc,
> > +};
> > +
> > +static const struct sdhci_acpi_chip sdhci_acpi_chip_nvda_bf = {
> > +	.ops = &sdhci_acpi_ops_nvda_bf,
> > +};
> > +
> > +static const struct sdhci_acpi_slot sdhci_acpi_slot_nvda_bf_emmc = {
> > +	.chip		= &sdhci_acpi_chip_nvda_bf,
> > +	.caps		= MMC_CAP_8_BIT_DATA |
> MMC_CAP_NONREMOVABLE,
> > +	.probe_slot	= sdhci_acpi_emmc_nvda_bf_probe_slot,
> > +};
> > +
> >  struct sdhci_acpi_uid_slot {
> >  	const char *hid;
> >  	const char *uid;
> > @@ -740,6 +802,7 @@ struct sdhci_acpi_uid_slot {
> >  	{ "QCOM8051", NULL, &sdhci_acpi_slot_qcom_sd_3v },
> >  	{ "QCOM8052", NULL, &sdhci_acpi_slot_qcom_sd },
> >  	{ "AMDI0040", NULL, &sdhci_acpi_slot_amd_emmc },
> > +	{ "MLNXBF30", NULL, &sdhci_acpi_slot_nvda_bf_emmc },
> >  	{ },
> >  };
> >
> > @@ -757,6 +820,7 @@ struct sdhci_acpi_uid_slot {
> >  	{ "QCOM8051" },
> >  	{ "QCOM8052" },
> >  	{ "AMDI0040" },
> > +	{ "MLNXBF30" },
> >  	{ },
> >  };
> >  MODULE_DEVICE_TABLE(acpi, sdhci_acpi_ids);
> >

Re: [PATCH v1 1/1] mmc: sdhci-acpi: Add support for NVIDIA BlueField-3 SoC

[Adrian Hunter]

On 15/03/21 7:00 pm, Liming Sun wrote:
> Thanks Adrian. Yes, I did consider adding this ACPI support into sdhci-of-dwcmshc.c, but not sure which one is the preferred way.
> Is this (sdhci-of-dwcmshc.c) what you recommend? I'll post the revised changes in patch v2.

Yes, that is generally preferred I think.

> 
>> -----Original Message-----
>> From: Adrian Hunter <adrian.hunter@intel.com>
>> Sent: Monday, March 15, 2021 4:34 AM
>> To: Liming Sun <limings@nvidia.com>; Ulf Hansson <ulf.hansson@linaro.org>;
>> Khalil Blaiech <kblaiech@nvidia.com>
>> Cc: linux-mmc@vger.kernel.org; linux-kernel@vger.kernel.org
>> Subject: Re: [PATCH v1 1/1] mmc: sdhci-acpi: Add support for NVIDIA
>> BlueField-3 SoC
>>
>> On 12/03/21 3:48 pm, Liming Sun wrote:
>>> This commit adds ACPI support for the BlueField-3 SoC which uses
>>> the DWC_mshc eMMC controller. The boundary check logic in static
>>> function dwcmshc_adma_write_desc() comes from sdhci-of-dwcmshc.c.
>>
>> Did you consider adding ACPI support to sdhci-of-dwcmshc.c ?
>> Other drivers have taken that approach, see sdhci-xenon.c or sdhci-iproc.c
>>
>>>
>>> Signed-off-by: Liming Sun <limings@nvidia.com>
>>> Reviewed-by: Khalil Blaiech <kblaiech@nvidia.com>
>>> ---
>>>  drivers/mmc/host/sdhci-acpi.c | 64
>> +++++++++++++++++++++++++++++++++++++++++++
>>>  1 file changed, 64 insertions(+)
>>>
>>> diff --git a/drivers/mmc/host/sdhci-acpi.c b/drivers/mmc/host/sdhci-acpi.c
>>> index 54205e3..6448e94e 100644
>>> --- a/drivers/mmc/host/sdhci-acpi.c
>>> +++ b/drivers/mmc/host/sdhci-acpi.c
>>> @@ -716,6 +716,68 @@ static int sdhci_acpi_emmc_amd_probe_slot(struct
>> platform_device *pdev,
>>>  	.priv_size	= sizeof(struct amd_sdhci_host),
>>>  };
>>>
>>> +/* Check DMA address/length boundary. */
>>> +static inline bool dwcmshc_adma_boundary_ok(dma_addr_t addr, int len)
>>> +{
>>> +	return (addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1));
>>> +}
>>> +
>>> +/*
>>> + * If DMA addr spans 128MB boundary, we split the DMA transfer into two
>>> + * so that each DMA transfer doesn't exceed the boundary.
>>> + */
>>> +static void dwcmshc_adma_write_desc(struct sdhci_host *host, void
>> **desc,
>>> +				    dma_addr_t addr, int len, unsigned int cmd)
>>> +{
>>> +	int tmplen, offset;
>>> +
>>> +	if (likely(!len || dwcmshc_adma_boundary_ok(addr, len))) {
>>> +		sdhci_adma_write_desc(host, desc, addr, len, cmd);
>>> +		return;
>>> +	}
>>> +
>>> +	offset = addr & (SZ_128M - 1);
>>> +	tmplen = SZ_128M - offset;
>>> +	sdhci_adma_write_desc(host, desc, addr, tmplen, cmd);
>>> +
>>> +	addr += tmplen;
>>> +	len -= tmplen;
>>> +	sdhci_adma_write_desc(host, desc, addr, len, cmd);
>>> +}
>>> +
>>> +static int sdhci_acpi_emmc_nvda_bf_probe_slot(struct platform_device
>> *pdev,
>>> +					      struct acpi_device *adev)
>>> +{
>>> +	struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
>>> +	struct sdhci_host *host = c->host;
>>> +	u32 extra;
>>> +
>>> +	/* Extra adma table cnt for cross 128M boundary handling. */
>>> +	extra = DIV_ROUND_UP_ULL(dma_get_required_mask(&pdev->dev),
>> SZ_128M);
>>> +	extra = min(extra, (u32)SDHCI_MAX_SEGS);
>>> +	host->adma_table_cnt += extra;
>>> +
>>> +	return 0;
>>> +}
>>> +
>>> +static const struct sdhci_ops sdhci_acpi_ops_nvda_bf = {
>>> +	.set_clock		= sdhci_set_clock,
>>> +	.set_bus_width		= sdhci_set_bus_width,
>>> +	.set_uhs_signaling	= sdhci_set_uhs_signaling,
>>> +	.reset			= sdhci_reset,
>>> +	.adma_write_desc	= dwcmshc_adma_write_desc,
>>> +};
>>> +
>>> +static const struct sdhci_acpi_chip sdhci_acpi_chip_nvda_bf = {
>>> +	.ops = &sdhci_acpi_ops_nvda_bf,
>>> +};
>>> +
>>> +static const struct sdhci_acpi_slot sdhci_acpi_slot_nvda_bf_emmc = {
>>> +	.chip		= &sdhci_acpi_chip_nvda_bf,
>>> +	.caps		= MMC_CAP_8_BIT_DATA |
>> MMC_CAP_NONREMOVABLE,
>>> +	.probe_slot	= sdhci_acpi_emmc_nvda_bf_probe_slot,
>>> +};
>>> +
>>>  struct sdhci_acpi_uid_slot {
>>>  	const char *hid;
>>>  	const char *uid;
>>> @@ -740,6 +802,7 @@ struct sdhci_acpi_uid_slot {
>>>  	{ "QCOM8051", NULL, &sdhci_acpi_slot_qcom_sd_3v },
>>>  	{ "QCOM8052", NULL, &sdhci_acpi_slot_qcom_sd },
>>>  	{ "AMDI0040", NULL, &sdhci_acpi_slot_amd_emmc },
>>> +	{ "MLNXBF30", NULL, &sdhci_acpi_slot_nvda_bf_emmc },
>>>  	{ },
>>>  };
>>>
>>> @@ -757,6 +820,7 @@ struct sdhci_acpi_uid_slot {
>>>  	{ "QCOM8051" },
>>>  	{ "QCOM8052" },
>>>  	{ "AMDI0040" },
>>> +	{ "MLNXBF30" },
>>>  	{ },
>>>  };
>>>  MODULE_DEVICE_TABLE(acpi, sdhci_acpi_ids);
>>>
> 

[PATCH v2] mmc: sdhci-of-dwcmshc: add ACPI support for BlueField-3 SoC

[Liming Sun]

This commit adds ACPI support in the sdhci-of-dwcmshc driver for
BlueField-3 SoC. It has changes to only use the clock hierarchy
for Deviec Tree since the clk is not supported by ACPI. Instead,
ACPI can define 'clock-frequency' which is parsed by existing
sdhci_get_property(). This clock value will be returned in function
dwcmshc_get_max_clock().

Signed-off-by: Liming Sun <limings@nvidia.com>
Reviewed-by: Khalil Blaiech <kblaiech@nvidia.com>
---
v1->v2:
   Changes for comments from Adrian Hunter <adrian.hunter@intel.com>:
   - Make changes in sdhci-of-dwcmshc instead.
v1: Initial version which was done in sdhci-acpi.c
---
 drivers/mmc/host/sdhci-of-dwcmshc.c | 50 ++++++++++++++++++++++++++-----------
 1 file changed, 36 insertions(+), 14 deletions(-)

diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c
index 59d8d96..bf5037a 100644
--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
@@ -7,6 +7,7 @@
  * Author: Jisheng Zhang <jszhang@kernel.org>
  */
 
+#include <linux/acpi.h>
 #include <linux/clk.h>
 #include <linux/dma-mapping.h>
 #include <linux/kernel.h>
@@ -51,6 +52,16 @@ static void dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc,
 	sdhci_adma_write_desc(host, desc, addr, len, cmd);
 }
 
+static unsigned int dwcmshc_get_max_clock(struct sdhci_host *host)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+
+	if (pltfm_host->clk)
+		return sdhci_pltfm_clk_get_max_clock(host);
+	else
+		return pltfm_host->clock;
+}
+
 static void dwcmshc_check_auto_cmd23(struct mmc_host *mmc,
 				     struct mmc_request *mrq)
 {
@@ -104,7 +115,7 @@ static void dwcmshc_set_uhs_signaling(struct sdhci_host *host,
 	.set_clock		= sdhci_set_clock,
 	.set_bus_width		= sdhci_set_bus_width,
 	.set_uhs_signaling	= dwcmshc_set_uhs_signaling,
-	.get_max_clock		= sdhci_pltfm_clk_get_max_clock,
+	.get_max_clock		= dwcmshc_get_max_clock,
 	.reset			= sdhci_reset,
 	.adma_write_desc	= dwcmshc_adma_write_desc,
 };
@@ -117,6 +128,7 @@ static void dwcmshc_set_uhs_signaling(struct sdhci_host *host,
 
 static int dwcmshc_probe(struct platform_device *pdev)
 {
+	struct device *dev = &pdev->dev;
 	struct sdhci_pltfm_host *pltfm_host;
 	struct sdhci_host *host;
 	struct dwcmshc_priv *priv;
@@ -131,7 +143,7 @@ static int dwcmshc_probe(struct platform_device *pdev)
 	/*
 	 * extra adma table cnt for cross 128M boundary handling.
 	 */
-	extra = DIV_ROUND_UP_ULL(dma_get_required_mask(&pdev->dev), SZ_128M);
+	extra = DIV_ROUND_UP_ULL(dma_get_required_mask(dev), SZ_128M);
 	if (extra > SDHCI_MAX_SEGS)
 		extra = SDHCI_MAX_SEGS;
 	host->adma_table_cnt += extra;
@@ -139,19 +151,21 @@ static int dwcmshc_probe(struct platform_device *pdev)
 	pltfm_host = sdhci_priv(host);
 	priv = sdhci_pltfm_priv(pltfm_host);
 
-	pltfm_host->clk = devm_clk_get(&pdev->dev, "core");
-	if (IS_ERR(pltfm_host->clk)) {
-		err = PTR_ERR(pltfm_host->clk);
-		dev_err(&pdev->dev, "failed to get core clk: %d\n", err);
-		goto free_pltfm;
+	if (dev->of_node) {
+		pltfm_host->clk = devm_clk_get(dev, "core");
+		if (IS_ERR(pltfm_host->clk)) {
+			err = PTR_ERR(pltfm_host->clk);
+			dev_err(dev, "failed to get core clk: %d\n", err);
+			goto free_pltfm;
+		}
+		err = clk_prepare_enable(pltfm_host->clk);
+		if (err)
+			goto free_pltfm;
+
+		priv->bus_clk = devm_clk_get(dev, "bus");
+		if (!IS_ERR(priv->bus_clk))
+			clk_prepare_enable(priv->bus_clk);
 	}
-	err = clk_prepare_enable(pltfm_host->clk);
-	if (err)
-		goto free_pltfm;
-
-	priv->bus_clk = devm_clk_get(&pdev->dev, "bus");
-	if (!IS_ERR(priv->bus_clk))
-		clk_prepare_enable(priv->bus_clk);
 
 	err = mmc_of_parse(host->mmc);
 	if (err)
@@ -239,11 +253,19 @@ static int dwcmshc_resume(struct device *dev)
 };
 MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids);
 
+#ifdef CONFIG_ACPI
+static const struct acpi_device_id sdhci_dwcmshc_acpi_ids[] = {
+	{ .id = "MLNXBF30" },
+	{}
+};
+#endif
+
 static struct platform_driver sdhci_dwcmshc_driver = {
 	.driver	= {
 		.name	= "sdhci-dwcmshc",
 		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
 		.of_match_table = sdhci_dwcmshc_dt_ids,
+		.acpi_match_table = ACPI_PTR(sdhci_dwcmshc_acpi_ids),
 		.pm = &dwcmshc_pmops,
 	},
 	.probe	= dwcmshc_probe,
-- 
1.8.3.1

RE: [PATCH v1 1/1] mmc: sdhci-acpi: Add support for NVIDIA BlueField-3 SoC

[Liming Sun]

> -----Original Message-----
> From: Adrian Hunter <adrian.hunter@intel.com>
> Sent: Monday, March 15, 2021 3:20 PM
> To: Liming Sun <limings@nvidia.com>; Khalil Blaiech <kblaiech@nvidia.com>;
> Ulf Hansson <ulf.hansson@linaro.org>
> Cc: linux-mmc@vger.kernel.org; Linux Kernel Mailing List <linux-
> kernel@vger.kernel.org>
> Subject: Re: [PATCH v1 1/1] mmc: sdhci-acpi: Add support for NVIDIA
> BlueField-3 SoC
> 
> On 15/03/21 7:00 pm, Liming Sun wrote:
> > Thanks Adrian. Yes, I did consider adding this ACPI support into sdhci-of-
> dwcmshc.c, but not sure which one is the preferred way.
> > Is this (sdhci-of-dwcmshc.c) what you recommend? I'll post the revised
> changes in patch v2.
> 
> Yes, that is generally preferred I think.

Thanks Adrian. Posted "[PATCH v2] mmc: sdhci-of-dwcmshc: add ACPI support for BlueField-3 SoC" for this change.

Re: [PATCH v2] mmc: sdhci-of-dwcmshc: add ACPI support for BlueField-3 SoC

[Ulf Hansson]

On Wed, 17 Mar 2021 at 00:20, Liming Sun <limings@nvidia.com> wrote:
>
> This commit adds ACPI support in the sdhci-of-dwcmshc driver for
> BlueField-3 SoC. It has changes to only use the clock hierarchy
> for Deviec Tree since the clk is not supported by ACPI. Instead,
> ACPI can define 'clock-frequency' which is parsed by existing
> sdhci_get_property(). This clock value will be returned in function
> dwcmshc_get_max_clock().
>
> Signed-off-by: Liming Sun <limings@nvidia.com>
> Reviewed-by: Khalil Blaiech <kblaiech@nvidia.com>

Liming, can you please rebase and repost a new version. It seems like
Shawn Lin's patch that added rockchip platform support causes the
conflict.

Kind regards
Uffe


> ---
> v1->v2:
>    Changes for comments from Adrian Hunter <adrian.hunter@intel.com>:
>    - Make changes in sdhci-of-dwcmshc instead.
> v1: Initial version which was done in sdhci-acpi.c
> ---
>  drivers/mmc/host/sdhci-of-dwcmshc.c | 50 ++++++++++++++++++++++++++-----------
>  1 file changed, 36 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c
> index 59d8d96..bf5037a 100644
> --- a/drivers/mmc/host/sdhci-of-dwcmshc.c
> +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
> @@ -7,6 +7,7 @@
>   * Author: Jisheng Zhang <jszhang@kernel.org>
>   */
>
> +#include <linux/acpi.h>
>  #include <linux/clk.h>
>  #include <linux/dma-mapping.h>
>  #include <linux/kernel.h>
> @@ -51,6 +52,16 @@ static void dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc,
>         sdhci_adma_write_desc(host, desc, addr, len, cmd);
>  }
>
> +static unsigned int dwcmshc_get_max_clock(struct sdhci_host *host)
> +{
> +       struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +
> +       if (pltfm_host->clk)
> +               return sdhci_pltfm_clk_get_max_clock(host);
> +       else
> +               return pltfm_host->clock;
> +}
> +
>  static void dwcmshc_check_auto_cmd23(struct mmc_host *mmc,
>                                      struct mmc_request *mrq)
>  {
> @@ -104,7 +115,7 @@ static void dwcmshc_set_uhs_signaling(struct sdhci_host *host,
>         .set_clock              = sdhci_set_clock,
>         .set_bus_width          = sdhci_set_bus_width,
>         .set_uhs_signaling      = dwcmshc_set_uhs_signaling,
> -       .get_max_clock          = sdhci_pltfm_clk_get_max_clock,
> +       .get_max_clock          = dwcmshc_get_max_clock,
>         .reset                  = sdhci_reset,
>         .adma_write_desc        = dwcmshc_adma_write_desc,
>  };
> @@ -117,6 +128,7 @@ static void dwcmshc_set_uhs_signaling(struct sdhci_host *host,
>
>  static int dwcmshc_probe(struct platform_device *pdev)
>  {
> +       struct device *dev = &pdev->dev;
>         struct sdhci_pltfm_host *pltfm_host;
>         struct sdhci_host *host;
>         struct dwcmshc_priv *priv;
> @@ -131,7 +143,7 @@ static int dwcmshc_probe(struct platform_device *pdev)
>         /*
>          * extra adma table cnt for cross 128M boundary handling.
>          */
> -       extra = DIV_ROUND_UP_ULL(dma_get_required_mask(&pdev->dev), SZ_128M);
> +       extra = DIV_ROUND_UP_ULL(dma_get_required_mask(dev), SZ_128M);
>         if (extra > SDHCI_MAX_SEGS)
>                 extra = SDHCI_MAX_SEGS;
>         host->adma_table_cnt += extra;
> @@ -139,19 +151,21 @@ static int dwcmshc_probe(struct platform_device *pdev)
>         pltfm_host = sdhci_priv(host);
>         priv = sdhci_pltfm_priv(pltfm_host);
>
> -       pltfm_host->clk = devm_clk_get(&pdev->dev, "core");
> -       if (IS_ERR(pltfm_host->clk)) {
> -               err = PTR_ERR(pltfm_host->clk);
> -               dev_err(&pdev->dev, "failed to get core clk: %d\n", err);
> -               goto free_pltfm;
> +       if (dev->of_node) {
> +               pltfm_host->clk = devm_clk_get(dev, "core");
> +               if (IS_ERR(pltfm_host->clk)) {
> +                       err = PTR_ERR(pltfm_host->clk);
> +                       dev_err(dev, "failed to get core clk: %d\n", err);
> +                       goto free_pltfm;
> +               }
> +               err = clk_prepare_enable(pltfm_host->clk);
> +               if (err)
> +                       goto free_pltfm;
> +
> +               priv->bus_clk = devm_clk_get(dev, "bus");
> +               if (!IS_ERR(priv->bus_clk))
> +                       clk_prepare_enable(priv->bus_clk);
>         }
> -       err = clk_prepare_enable(pltfm_host->clk);
> -       if (err)
> -               goto free_pltfm;
> -
> -       priv->bus_clk = devm_clk_get(&pdev->dev, "bus");
> -       if (!IS_ERR(priv->bus_clk))
> -               clk_prepare_enable(priv->bus_clk);
>
>         err = mmc_of_parse(host->mmc);
>         if (err)
> @@ -239,11 +253,19 @@ static int dwcmshc_resume(struct device *dev)
>  };
>  MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids);
>
> +#ifdef CONFIG_ACPI
> +static const struct acpi_device_id sdhci_dwcmshc_acpi_ids[] = {
> +       { .id = "MLNXBF30" },
> +       {}
> +};
> +#endif
> +
>  static struct platform_driver sdhci_dwcmshc_driver = {
>         .driver = {
>                 .name   = "sdhci-dwcmshc",
>                 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
>                 .of_match_table = sdhci_dwcmshc_dt_ids,
> +               .acpi_match_table = ACPI_PTR(sdhci_dwcmshc_acpi_ids),
>                 .pm = &dwcmshc_pmops,
>         },
>         .probe  = dwcmshc_probe,
> --
> 1.8.3.1
>

RE: [PATCH v2] mmc: sdhci-of-dwcmshc: add ACPI support for BlueField-3 SoC

[Liming Sun]

Uffe,

Can I confirm whether you meant the 'master' branch or some other branch?
I did a rebase of master and didn't see Shawn Lin's changes in the sdhci-of-dwcmshc.c

Thanks,
Liming

> -----Original Message-----
> From: Ulf Hansson <ulf.hansson@linaro.org>
> Sent: Friday, March 19, 2021 10:12 AM
> To: Liming Sun <limings@nvidia.com>
> Cc: Adrian Hunter <adrian.hunter@intel.com>; Khalil Blaiech
> <kblaiech@nvidia.com>; linux-mmc <linux-mmc@vger.kernel.org>; Linux
> Kernel Mailing List <linux-kernel@vger.kernel.org>
> Subject: Re: [PATCH v2] mmc: sdhci-of-dwcmshc: add ACPI support for
> BlueField-3 SoC
> 
> On Wed, 17 Mar 2021 at 00:20, Liming Sun <limings@nvidia.com> wrote:
> >
> > This commit adds ACPI support in the sdhci-of-dwcmshc driver for
> > BlueField-3 SoC. It has changes to only use the clock hierarchy
> > for Deviec Tree since the clk is not supported by ACPI. Instead,
> > ACPI can define 'clock-frequency' which is parsed by existing
> > sdhci_get_property(). This clock value will be returned in function
> > dwcmshc_get_max_clock().
> >
> > Signed-off-by: Liming Sun <limings@nvidia.com>
> > Reviewed-by: Khalil Blaiech <kblaiech@nvidia.com>
> 
> Liming, can you please rebase and repost a new version. It seems like
> Shawn Lin's patch that added rockchip platform support causes the
> conflict.
> 
> Kind regards
> Uffe
> 
> 
> > ---
> > v1->v2:
> >    Changes for comments from Adrian Hunter <adrian.hunter@intel.com>:
> >    - Make changes in sdhci-of-dwcmshc instead.
> > v1: Initial version which was done in sdhci-acpi.c
> > ---
> >  drivers/mmc/host/sdhci-of-dwcmshc.c | 50
> ++++++++++++++++++++++++++-----------
> >  1 file changed, 36 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c
> b/drivers/mmc/host/sdhci-of-dwcmshc.c
> > index 59d8d96..bf5037a 100644
> > --- a/drivers/mmc/host/sdhci-of-dwcmshc.c
> > +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
> > @@ -7,6 +7,7 @@
> >   * Author: Jisheng Zhang <jszhang@kernel.org>
> >   */
> >
> > +#include <linux/acpi.h>
> >  #include <linux/clk.h>
> >  #include <linux/dma-mapping.h>
> >  #include <linux/kernel.h>
> > @@ -51,6 +52,16 @@ static void dwcmshc_adma_write_desc(struct
> sdhci_host *host, void **desc,
> >         sdhci_adma_write_desc(host, desc, addr, len, cmd);
> >  }
> >
> > +static unsigned int dwcmshc_get_max_clock(struct sdhci_host *host)
> > +{
> > +       struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> > +
> > +       if (pltfm_host->clk)
> > +               return sdhci_pltfm_clk_get_max_clock(host);
> > +       else
> > +               return pltfm_host->clock;
> > +}
> > +
> >  static void dwcmshc_check_auto_cmd23(struct mmc_host *mmc,
> >                                      struct mmc_request *mrq)
> >  {
> > @@ -104,7 +115,7 @@ static void dwcmshc_set_uhs_signaling(struct
> sdhci_host *host,
> >         .set_clock              = sdhci_set_clock,
> >         .set_bus_width          = sdhci_set_bus_width,
> >         .set_uhs_signaling      = dwcmshc_set_uhs_signaling,
> > -       .get_max_clock          = sdhci_pltfm_clk_get_max_clock,
> > +       .get_max_clock          = dwcmshc_get_max_clock,
> >         .reset                  = sdhci_reset,
> >         .adma_write_desc        = dwcmshc_adma_write_desc,
> >  };
> > @@ -117,6 +128,7 @@ static void dwcmshc_set_uhs_signaling(struct
> sdhci_host *host,
> >
> >  static int dwcmshc_probe(struct platform_device *pdev)
> >  {
> > +       struct device *dev = &pdev->dev;
> >         struct sdhci_pltfm_host *pltfm_host;
> >         struct sdhci_host *host;
> >         struct dwcmshc_priv *priv;
> > @@ -131,7 +143,7 @@ static int dwcmshc_probe(struct platform_device
> *pdev)
> >         /*
> >          * extra adma table cnt for cross 128M boundary handling.
> >          */
> > -       extra = DIV_ROUND_UP_ULL(dma_get_required_mask(&pdev->dev),
> SZ_128M);
> > +       extra = DIV_ROUND_UP_ULL(dma_get_required_mask(dev), SZ_128M);
> >         if (extra > SDHCI_MAX_SEGS)
> >                 extra = SDHCI_MAX_SEGS;
> >         host->adma_table_cnt += extra;
> > @@ -139,19 +151,21 @@ static int dwcmshc_probe(struct platform_device
> *pdev)
> >         pltfm_host = sdhci_priv(host);
> >         priv = sdhci_pltfm_priv(pltfm_host);
> >
> > -       pltfm_host->clk = devm_clk_get(&pdev->dev, "core");
> > -       if (IS_ERR(pltfm_host->clk)) {
> > -               err = PTR_ERR(pltfm_host->clk);
> > -               dev_err(&pdev->dev, "failed to get core clk: %d\n", err);
> > -               goto free_pltfm;
> > +       if (dev->of_node) {
> > +               pltfm_host->clk = devm_clk_get(dev, "core");
> > +               if (IS_ERR(pltfm_host->clk)) {
> > +                       err = PTR_ERR(pltfm_host->clk);
> > +                       dev_err(dev, "failed to get core clk: %d\n", err);
> > +                       goto free_pltfm;
> > +               }
> > +               err = clk_prepare_enable(pltfm_host->clk);
> > +               if (err)
> > +                       goto free_pltfm;
> > +
> > +               priv->bus_clk = devm_clk_get(dev, "bus");
> > +               if (!IS_ERR(priv->bus_clk))
> > +                       clk_prepare_enable(priv->bus_clk);
> >         }
> > -       err = clk_prepare_enable(pltfm_host->clk);
> > -       if (err)
> > -               goto free_pltfm;
> > -
> > -       priv->bus_clk = devm_clk_get(&pdev->dev, "bus");
> > -       if (!IS_ERR(priv->bus_clk))
> > -               clk_prepare_enable(priv->bus_clk);
> >
> >         err = mmc_of_parse(host->mmc);
> >         if (err)
> > @@ -239,11 +253,19 @@ static int dwcmshc_resume(struct device *dev)
> >  };
> >  MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids);
> >
> > +#ifdef CONFIG_ACPI
> > +static const struct acpi_device_id sdhci_dwcmshc_acpi_ids[] = {
> > +       { .id = "MLNXBF30" },
> > +       {}
> > +};
> > +#endif
> > +
> >  static struct platform_driver sdhci_dwcmshc_driver = {
> >         .driver = {
> >                 .name   = "sdhci-dwcmshc",
> >                 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
> >                 .of_match_table = sdhci_dwcmshc_dt_ids,
> > +               .acpi_match_table = ACPI_PTR(sdhci_dwcmshc_acpi_ids),
> >                 .pm = &dwcmshc_pmops,
> >         },
> >         .probe  = dwcmshc_probe,
> > --
> > 1.8.3.1
> >

Re: [PATCH v2] mmc: sdhci-of-dwcmshc: add ACPI support for BlueField-3 SoC

[Ulf Hansson]

On Fri, 19 Mar 2021 at 21:23, Liming Sun <limings@nvidia.com> wrote:
>
> Uffe,
>
> Can I confirm whether you meant the 'master' branch or some other branch?
> I did a rebase of master and didn't see Shawn Lin's changes in the sdhci-of-dwcmshc.c

git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc.git next

[...]

Kind regards
Uffe

[PATCH v3] mmc: sdhci-of-dwcmshc: add ACPI support for BlueField-3 SoC

[Liming Sun]

This commit adds ACPI support in the sdhci-of-dwcmshc driver for
BlueField-3 SoC. It has changes to only use the clock hierarchy
for Deviec Tree since the clk is not supported by ACPI. Instead,
ACPI can define 'clock-frequency' which is parsed by existing
sdhci_get_property(). This clock value will be returned in function
dwcmshc_get_max_clock().

Signed-off-by: Liming Sun <limings@nvidia.com>
Reviewed-by: Khalil Blaiech <kblaiech@nvidia.com>
---
v2->v3:
   Rebase to mmc next.
v1->v2:
   Changes for comments from Adrian Hunter <adrian.hunter@intel.com>:
   - Make changes in sdhci-of-dwcmshc instead.
v1: Initial version which was done in sdhci-acpi.c
---
 drivers/mmc/host/sdhci-of-dwcmshc.c | 50 ++++++++++++++++++++++++++-----------
 1 file changed, 36 insertions(+), 14 deletions(-)

diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c
index 0687368..1113a56 100644
--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
@@ -7,6 +7,7 @@
  * Author: Jisheng Zhang <jszhang@kernel.org>
  */
 
+#include <linux/acpi.h>
 #include <linux/clk.h>
 #include <linux/dma-mapping.h>
 #include <linux/iopoll.h>
@@ -94,6 +95,16 @@ static void dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc,
 	sdhci_adma_write_desc(host, desc, addr, len, cmd);
 }
 
+static unsigned int dwcmshc_get_max_clock(struct sdhci_host *host)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+
+	if (pltfm_host->clk)
+		return sdhci_pltfm_clk_get_max_clock(host);
+	else
+		return pltfm_host->clock;
+}
+
 static void dwcmshc_check_auto_cmd23(struct mmc_host *mmc,
 				     struct mmc_request *mrq)
 {
@@ -248,7 +259,7 @@ static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock
 	.set_clock		= sdhci_set_clock,
 	.set_bus_width		= sdhci_set_bus_width,
 	.set_uhs_signaling	= dwcmshc_set_uhs_signaling,
-	.get_max_clock		= sdhci_pltfm_clk_get_max_clock,
+	.get_max_clock		= dwcmshc_get_max_clock,
 	.reset			= sdhci_reset,
 	.adma_write_desc	= dwcmshc_adma_write_desc,
 };
@@ -323,8 +334,16 @@ static int dwcmshc_rk3568_init(struct sdhci_host *host, struct dwcmshc_priv *dwc
 };
 MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids);
 
+#ifdef CONFIG_ACPI
+static const struct acpi_device_id sdhci_dwcmshc_acpi_ids[] = {
+	{ .id = "MLNXBF30" },
+	{}
+};
+#endif
+
 static int dwcmshc_probe(struct platform_device *pdev)
 {
+	struct device *dev = &pdev->dev;
 	struct sdhci_pltfm_host *pltfm_host;
 	struct sdhci_host *host;
 	struct dwcmshc_priv *priv;
@@ -347,7 +366,7 @@ static int dwcmshc_probe(struct platform_device *pdev)
 	/*
 	 * extra adma table cnt for cross 128M boundary handling.
 	 */
-	extra = DIV_ROUND_UP_ULL(dma_get_required_mask(&pdev->dev), SZ_128M);
+	extra = DIV_ROUND_UP_ULL(dma_get_required_mask(dev), SZ_128M);
 	if (extra > SDHCI_MAX_SEGS)
 		extra = SDHCI_MAX_SEGS;
 	host->adma_table_cnt += extra;
@@ -355,19 +374,21 @@ static int dwcmshc_probe(struct platform_device *pdev)
 	pltfm_host = sdhci_priv(host);
 	priv = sdhci_pltfm_priv(pltfm_host);
 
-	pltfm_host->clk = devm_clk_get(&pdev->dev, "core");
-	if (IS_ERR(pltfm_host->clk)) {
-		err = PTR_ERR(pltfm_host->clk);
-		dev_err(&pdev->dev, "failed to get core clk: %d\n", err);
-		goto free_pltfm;
-	}
-	err = clk_prepare_enable(pltfm_host->clk);
-	if (err)
-		goto free_pltfm;
+	if (dev->of_node) {
+		pltfm_host->clk = devm_clk_get(dev, "core");
+		if (IS_ERR(pltfm_host->clk)) {
+			err = PTR_ERR(pltfm_host->clk);
+			dev_err(dev, "failed to get core clk: %d\n", err);
+			goto free_pltfm;
+		}
+		err = clk_prepare_enable(pltfm_host->clk);
+		if (err)
+			goto free_pltfm;
 
-	priv->bus_clk = devm_clk_get(&pdev->dev, "bus");
-	if (!IS_ERR(priv->bus_clk))
-		clk_prepare_enable(priv->bus_clk);
+		priv->bus_clk = devm_clk_get(dev, "bus");
+		if (!IS_ERR(priv->bus_clk))
+			clk_prepare_enable(priv->bus_clk);
+	}
 
 	err = mmc_of_parse(host->mmc);
 	if (err)
@@ -489,6 +510,7 @@ static int dwcmshc_resume(struct device *dev)
 		.name	= "sdhci-dwcmshc",
 		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
 		.of_match_table = sdhci_dwcmshc_dt_ids,
+		.acpi_match_table = ACPI_PTR(sdhci_dwcmshc_acpi_ids),
 		.pm = &dwcmshc_pmops,
 	},
 	.probe	= dwcmshc_probe,
-- 
1.8.3.1

RE: [PATCH v2] mmc: sdhci-of-dwcmshc: add ACPI support for BlueField-3 SoC

[Liming Sun]

> -----Original Message-----
> From: Ulf Hansson <ulf.hansson@linaro.org>
> Sent: Monday, March 22, 2021 5:51 AM
> To: Liming Sun <limings@nvidia.com>
> Cc: Adrian Hunter <adrian.hunter@intel.com>; Khalil Blaiech
> <kblaiech@nvidia.com>; linux-mmc <linux-mmc@vger.kernel.org>; Linux
> Kernel Mailing List <linux-kernel@vger.kernel.org>
> Subject: Re: [PATCH v2] mmc: sdhci-of-dwcmshc: add ACPI support for
> BlueField-3 SoC
> 
> On Fri, 19 Mar 2021 at 21:23, Liming Sun <limings@nvidia.com> wrote:
> >
> > Uffe,
> >
> > Can I confirm whether you meant the 'master' branch or some other
> branch?
> > I did a rebase of master and didn't see Shawn Lin's changes in the sdhci-of-
> dwcmshc.c
> 
> git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc.git next

Thanks! Rebased and posted v3.

> 
> [...]
> 
> Kind regards
> Uffe

Re: [PATCH v3] mmc: sdhci-of-dwcmshc: add ACPI support for BlueField-3 SoC

[Ulf Hansson]

On Mon, 22 Mar 2021 at 23:47, Liming Sun <limings@nvidia.com> wrote:
>
> This commit adds ACPI support in the sdhci-of-dwcmshc driver for
> BlueField-3 SoC. It has changes to only use the clock hierarchy
> for Deviec Tree since the clk is not supported by ACPI. Instead,
> ACPI can define 'clock-frequency' which is parsed by existing
> sdhci_get_property(). This clock value will be returned in function
> dwcmshc_get_max_clock().
>
> Signed-off-by: Liming Sun <limings@nvidia.com>
> Reviewed-by: Khalil Blaiech <kblaiech@nvidia.com>

Applied for next, thanks!

Kind regards
Uffe


> ---
> v2->v3:
>    Rebase to mmc next.
> v1->v2:
>    Changes for comments from Adrian Hunter <adrian.hunter@intel.com>:
>    - Make changes in sdhci-of-dwcmshc instead.
> v1: Initial version which was done in sdhci-acpi.c
> ---
>  drivers/mmc/host/sdhci-of-dwcmshc.c | 50 ++++++++++++++++++++++++++-----------
>  1 file changed, 36 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c
> index 0687368..1113a56 100644
> --- a/drivers/mmc/host/sdhci-of-dwcmshc.c
> +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
> @@ -7,6 +7,7 @@
>   * Author: Jisheng Zhang <jszhang@kernel.org>
>   */
>
> +#include <linux/acpi.h>
>  #include <linux/clk.h>
>  #include <linux/dma-mapping.h>
>  #include <linux/iopoll.h>
> @@ -94,6 +95,16 @@ static void dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc,
>         sdhci_adma_write_desc(host, desc, addr, len, cmd);
>  }
>
> +static unsigned int dwcmshc_get_max_clock(struct sdhci_host *host)
> +{
> +       struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +
> +       if (pltfm_host->clk)
> +               return sdhci_pltfm_clk_get_max_clock(host);
> +       else
> +               return pltfm_host->clock;
> +}
> +
>  static void dwcmshc_check_auto_cmd23(struct mmc_host *mmc,
>                                      struct mmc_request *mrq)
>  {
> @@ -248,7 +259,7 @@ static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock
>         .set_clock              = sdhci_set_clock,
>         .set_bus_width          = sdhci_set_bus_width,
>         .set_uhs_signaling      = dwcmshc_set_uhs_signaling,
> -       .get_max_clock          = sdhci_pltfm_clk_get_max_clock,
> +       .get_max_clock          = dwcmshc_get_max_clock,
>         .reset                  = sdhci_reset,
>         .adma_write_desc        = dwcmshc_adma_write_desc,
>  };
> @@ -323,8 +334,16 @@ static int dwcmshc_rk3568_init(struct sdhci_host *host, struct dwcmshc_priv *dwc
>  };
>  MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids);
>
> +#ifdef CONFIG_ACPI
> +static const struct acpi_device_id sdhci_dwcmshc_acpi_ids[] = {
> +       { .id = "MLNXBF30" },
> +       {}
> +};
> +#endif
> +
>  static int dwcmshc_probe(struct platform_device *pdev)
>  {
> +       struct device *dev = &pdev->dev;
>         struct sdhci_pltfm_host *pltfm_host;
>         struct sdhci_host *host;
>         struct dwcmshc_priv *priv;
> @@ -347,7 +366,7 @@ static int dwcmshc_probe(struct platform_device *pdev)
>         /*
>          * extra adma table cnt for cross 128M boundary handling.
>          */
> -       extra = DIV_ROUND_UP_ULL(dma_get_required_mask(&pdev->dev), SZ_128M);
> +       extra = DIV_ROUND_UP_ULL(dma_get_required_mask(dev), SZ_128M);
>         if (extra > SDHCI_MAX_SEGS)
>                 extra = SDHCI_MAX_SEGS;
>         host->adma_table_cnt += extra;
> @@ -355,19 +374,21 @@ static int dwcmshc_probe(struct platform_device *pdev)
>         pltfm_host = sdhci_priv(host);
>         priv = sdhci_pltfm_priv(pltfm_host);
>
> -       pltfm_host->clk = devm_clk_get(&pdev->dev, "core");
> -       if (IS_ERR(pltfm_host->clk)) {
> -               err = PTR_ERR(pltfm_host->clk);
> -               dev_err(&pdev->dev, "failed to get core clk: %d\n", err);
> -               goto free_pltfm;
> -       }
> -       err = clk_prepare_enable(pltfm_host->clk);
> -       if (err)
> -               goto free_pltfm;
> +       if (dev->of_node) {
> +               pltfm_host->clk = devm_clk_get(dev, "core");
> +               if (IS_ERR(pltfm_host->clk)) {
> +                       err = PTR_ERR(pltfm_host->clk);
> +                       dev_err(dev, "failed to get core clk: %d\n", err);
> +                       goto free_pltfm;
> +               }
> +               err = clk_prepare_enable(pltfm_host->clk);
> +               if (err)
> +                       goto free_pltfm;
>
> -       priv->bus_clk = devm_clk_get(&pdev->dev, "bus");
> -       if (!IS_ERR(priv->bus_clk))
> -               clk_prepare_enable(priv->bus_clk);
> +               priv->bus_clk = devm_clk_get(dev, "bus");
> +               if (!IS_ERR(priv->bus_clk))
> +                       clk_prepare_enable(priv->bus_clk);
> +       }
>
>         err = mmc_of_parse(host->mmc);
>         if (err)
> @@ -489,6 +510,7 @@ static int dwcmshc_resume(struct device *dev)
>                 .name   = "sdhci-dwcmshc",
>                 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
>                 .of_match_table = sdhci_dwcmshc_dt_ids,
> +               .acpi_match_table = ACPI_PTR(sdhci_dwcmshc_acpi_ids),
>                 .pm = &dwcmshc_pmops,
>         },
>         .probe  = dwcmshc_probe,
> --
> 1.8.3.1
>