* [PATCH 0/4] Add new Renesas RZ/V2H SoC
@ 2024-02-19 16:09 Prabhakar
2024-02-19 16:09 ` [PATCH 1/4] dt-bindings: soc: renesas: Document Renesas RZ/V2H{P} SoC variants Prabhakar
` (3 more replies)
0 siblings, 4 replies; 17+ messages in thread
From: Prabhakar @ 2024-02-19 16:09 UTC (permalink / raw)
To: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Catalin Marinas, Will Deacon
Cc: linux-arm-kernel, linux-renesas-soc, devicetree, linux-kernel,
Prabhakar, Fabrizio Castro, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi,
This patch series adds initial support for RZ/V2H{P} (R9A09G057) SoC
identification.
The RZ/V2H{P} SoC is equipped with a Quad 64-bit Arm Cortex-A55 core
(up to 1.8 GHz), dual 32-bit Arm Cortex R8 core (up to 800 MHz) and a
32-bit Arm Cortex M33 core (up to 200 MHz). It supports the below
IP blocks/Features:
- Boot
* Selectable boot CPU from Cortex-M33 or Cortex-A55
- Accelerated engines
* AI accelerator (dynamically reconfigurable processor for AI (DRP-AI))
* Dynamic re-configurable processor (DRP)
* 3D graphics engine (GE3D MALI-G31) (optional)
* Image signal processing (ISP MALI-C55) (optional)
* Image scaling unit (ISU)
* Video codec unit (VCU)
- On-chip SRAM and external memory interfaces
* On-chip share SRAM (6-Mbyte with ECC)
* 2-channel memory controller for LPDDR4-3200 or LPDDR4X-3200 with a
32-bit bus width
* xSPI interface
* SDHI (eMMC/SD - 3ch)
- Timers
* 32-bit general purpose timers (16 ch)
* 32-bit CMTW (8 ch)
* 32-bit GTM (8 ch)
* RTC
* WDT (4 ch)
- Communication/storage /network interface
* Ethernet (2 ch: 10/100/1000 BASE)
* USB2.0 (1 ch: Host/Function, 1 ch: Host only)
* USB3.2 Gen2 (2 ch: Host only)
* PCIe Gen3 (1/2/4 lanes)
* MIPI CSI2 (4 ch: 1/2/4 lanes)
* MIPI DSI (1ch: 1/2/4 lanes)
* CAN/CANFD (6 ch)
* SCI (10 ch: UART/SPI/I2C)
* SCIF (1 ch)
* SPI (3 ch)
* I2C (9 ch)
* I3C (1 ch)
- Audio
* Asynchronous sampling rate converter unit (SCU) (up to 192 kHz)
* DMAC for Audio (ADMAC) is available to transfer audio formats
of I2S with SCU.
* Flexible audio clock generator (ADG) for audio functions.
* I2S (TDM) input/output interfaces (half-duplex 10 ch.; full-duplex
5 ch.)
* SPDIF input/output interfaces (3 ch.)
* Pulse density modulation (PDM) input interfaces (6 ch.)
- Analogue/Digital converter and sensors
* 2.5 Msps 12-bit ADC (8 ch)
* Internal temperature sensors (2 ch)
- Security
* Hardware cryptographic engine (optional)
Logs:
~ # uname -ra
Linux rz/v2h 6.8.0-rc5+ #167 SMP PREEMPT Mon Feb 19 10:42:01 GMT 2024 aarch64 GNU/Linux
~ #
~ # for i in machine family soc_id revision; do echo -n "$i: ";cat /sys/devices/
soc0/$i; done
machine: Renesas EVK based on r9a09g057h44
family: RZ/V2H
soc_id: r9a09g057
revision: 0
~ # cat /proc/cpuinfo
processor : 0
BogoMIPS : 48.00
Features : fp asimd evtstrm crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
CPU implementer : 0x41
CPU architecture: 8
CPU variant : 0x2
CPU part : 0xd05
CPU revision : 0
processor : 1
BogoMIPS : 48.00
Features : fp asimd evtstrm crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
CPU implementer : 0x41
CPU architecture: 8
CPU variant : 0x2
CPU part : 0xd05
CPU revision : 0
processor : 2
BogoMIPS : 48.00
Features : fp asimd evtstrm crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
CPU implementer : 0x41
CPU architecture: 8
CPU variant : 0x2
CPU part : 0xd05
CPU revision : 0
processor : 3
BogoMIPS : 48.00
Features : fp asimd evtstrm crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
CPU implementer : 0x41
CPU architecture: 8
CPU variant : 0x2
CPU part : 0xd05
CPU revision : 0
~ # cat /proc/meminfo
MemTotal: 16240544 kB
MemFree: 16201748 kB
MemAvailable: 16073696 kB
Buffers: 0 kB
Cached: 2040 kB
SwapCached: 0 kB
Active: 0 kB
Inactive: 68 kB
Active(anon): 0 kB
Inactive(anon): 68 kB
Active(file): 0 kB
Inactive(file): 0 kB
Unevictable: 2040 kB
Mlocked: 0 kB
SwapTotal: 0 kB
SwapFree: 0 kB
Dirty: 0 kB
Writeback: 0 kB
AnonPages: 84 kB
Mapped: 1456 kB
Shmem: 0 kB
KReclaimable: 2924 kB
Slab: 8720 kB
SReclaimable: 2924 kB
SUnreclaim: 5796 kB
KernelStack: 1056 kB
PageTables: 40 kB
SecPageTables: 0 kB
NFS_Unstable: 0 kB
Bounce: 0 kB
WritebackTmp: 0 kB
CommitLimit: 8120272 kB
Committed_AS: 648 kB
VmallocTotal: 133141626880 kB
VmallocUsed: 1264 kB
VmallocChunk: 0 kB
Percpu: 352 kB
HardwareCorrupted: 0 kB
AnonHugePages: 0 kB
ShmemHugePages: 0 kB
ShmemPmdMapped: 0 kB
FileHugePages: 0 kB
FilePmdMapped: 0 kB
CmaTotal: 32768 kB
CmaFree: 26624 kB
HugePages_Total: 0
HugePages_Free: 0
HugePages_Rsvd: 0
HugePages_Surp: 0
Hugepagesize: 2048 kB
Hugetlb: 0 kB
~ # cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3
11: 3426 66 291 243 GICv3 27 Level arch_timer
13: 0 0 0 0 GICv3 561 Level 11c01400.serial:rx err
14: 15 0 0 0 GICv3 564 Level 11c01400.serial:rx full
15: 1259 0 0 0 GICv3 565 Level 11c01400.serial:tx empty
16: 0 0 0 0 GICv3 562 Level 11c01400.serial:break
17: 82 0 0 0 GICv3 566 Level 11c01400.serial:rx ready
18: 0 0 0 0 GICv3 563 Level 11c01400.serial:tx end
IPI0: 5 20 8 23 Rescheduling interrupts
IPI1: 530 204 91 155 Function call interrupts
IPI2: 0 0 0 0 CPU stop interrupts
IPI3: 0 0 0 0 CPU stop (for crash dump) interrupts
IPI4: 0 0 0 0 Timer broadcast interrupts
IPI5: 0 0 0 0 IRQ work interrupts
Err: 0
~ #
Cheers,
Prabhakar
Lad Prabhakar (4):
dt-bindings: soc: renesas: Document Renesas RZ/V2H{P} SoC variants
dt-bindings: arm: renesas: Document Renesas RZ/V2H{P} System
Controller
soc: renesas: Add identification support for RZ/V2H SoC
arm64: defconfig: Enable R9A09G057 SoC
.../soc/renesas/renesas,r9a09g057-sys.yaml | 59 +++++++++++++++++++
.../bindings/soc/renesas/renesas.yaml | 8 +++
arch/arm64/configs/defconfig | 1 +
drivers/soc/renesas/Kconfig | 5 ++
drivers/soc/renesas/renesas-soc.c | 20 ++++++-
5 files changed, 92 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 1/4] dt-bindings: soc: renesas: Document Renesas RZ/V2H{P} SoC variants
2024-02-19 16:09 [PATCH 0/4] Add new Renesas RZ/V2H SoC Prabhakar
@ 2024-02-19 16:09 ` Prabhakar
2024-02-20 9:50 ` Krzysztof Kozlowski
2024-02-26 13:41 ` Geert Uytterhoeven
2024-02-19 16:09 ` [PATCH 2/4] dt-bindings: arm: renesas: Document Renesas RZ/V2H{P} System Controller Prabhakar
` (2 subsequent siblings)
3 siblings, 2 replies; 17+ messages in thread
From: Prabhakar @ 2024-02-19 16:09 UTC (permalink / raw)
To: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Catalin Marinas, Will Deacon
Cc: linux-arm-kernel, linux-renesas-soc, devicetree, linux-kernel,
Prabhakar, Fabrizio Castro, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Document Renesas RZ/V2H{P} (R9A09G057) SoC variants.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
---
.../devicetree/bindings/soc/renesas/renesas.yaml | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
index c1ce4da2dc32..109fbc8d48db 100644
--- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
+++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
@@ -513,6 +513,14 @@ properties:
- renesas,rzv2mevk2 # RZ/V2M Eval Board v2.0
- const: renesas,r9a09g011
+ - description: RZ/V2H{P} (R9A09G057)
+ items:
+ - enum:
+ - renesas,r9a09g057h41 # RZ/V2H
+ - renesas,r9a09g057h42 # RZ/V2H with Mali-G31 support
+ - renesas,r9a09g057h44 # RZ/V2HP with Mali-G31 + Mali-C55 support
+ - const: renesas,r9a09g057
+
additionalProperties: true
...
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 2/4] dt-bindings: arm: renesas: Document Renesas RZ/V2H{P} System Controller
2024-02-19 16:09 [PATCH 0/4] Add new Renesas RZ/V2H SoC Prabhakar
2024-02-19 16:09 ` [PATCH 1/4] dt-bindings: soc: renesas: Document Renesas RZ/V2H{P} SoC variants Prabhakar
@ 2024-02-19 16:09 ` Prabhakar
2024-02-20 9:51 ` Krzysztof Kozlowski
2024-02-26 13:41 ` Geert Uytterhoeven
2024-02-19 16:09 ` [PATCH 3/4] soc: renesas: Add identification support for RZ/V2H SoC Prabhakar
2024-02-19 16:09 ` [PATCH 4/4] arm64: defconfig: Enable R9A09G057 SoC Prabhakar
3 siblings, 2 replies; 17+ messages in thread
From: Prabhakar @ 2024-02-19 16:09 UTC (permalink / raw)
To: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Catalin Marinas, Will Deacon
Cc: linux-arm-kernel, linux-renesas-soc, devicetree, linux-kernel,
Prabhakar, Fabrizio Castro, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Add DT binding documentation for System Controller (SYS) found on
RZ/V2H{P} ("R9A09G057") SoC's.
SYS block contains the SYS_LSI_DEVID register which can be used to
retrieve SoC version information.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
---
Note, the reset index in example node will be update once the CPG
support is upstreamed.
---
.../soc/renesas/renesas,r9a09g057-sys.yaml | 59 +++++++++++++++++++
1 file changed, 59 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml
diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml
new file mode 100644
index 000000000000..ba30d7734ee8
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/renesas/renesas,r9a09g057-sys.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/V2H{P} System Controller (SYS)
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+
+description:
+ The RZ/V2H{P} SYS (System Controller) controls the overall
+ configuration of the LSI and supports the following functions,
+ - Trust zone control
+ - Extend access by specific masters to address beyond 4GB space
+ - GBETH configuration
+ - Control of settings and states of SRAM/PCIe/CM33/CA55/CR8/xSPI/ADC/TSU
+ - LSI version
+ - WDT stop control
+ - General registers
+
+properties:
+ compatible:
+ const: renesas,r9a09g057-sys
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Clock from external oscillator
+
+ resets:
+ items:
+ - description: SYS_0_PRESETN reset signal
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+ extal_clk: extal-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+
+ sys: system-controller@10430000 {
+ compatible = "renesas,r9a09g057-sys";
+ reg = <0x10430000 0x10000>;
+ clocks = <&extal_clk>;
+ resets = <&cpg 1>;
+ };
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 3/4] soc: renesas: Add identification support for RZ/V2H SoC
2024-02-19 16:09 [PATCH 0/4] Add new Renesas RZ/V2H SoC Prabhakar
2024-02-19 16:09 ` [PATCH 1/4] dt-bindings: soc: renesas: Document Renesas RZ/V2H{P} SoC variants Prabhakar
2024-02-19 16:09 ` [PATCH 2/4] dt-bindings: arm: renesas: Document Renesas RZ/V2H{P} System Controller Prabhakar
@ 2024-02-19 16:09 ` Prabhakar
2024-02-26 13:42 ` Geert Uytterhoeven
2024-02-19 16:09 ` [PATCH 4/4] arm64: defconfig: Enable R9A09G057 SoC Prabhakar
3 siblings, 1 reply; 17+ messages in thread
From: Prabhakar @ 2024-02-19 16:09 UTC (permalink / raw)
To: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Catalin Marinas, Will Deacon
Cc: linux-arm-kernel, linux-renesas-soc, devicetree, linux-kernel,
Prabhakar, Fabrizio Castro, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Add support to identify the RZ/V2H (R9A09G057) SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
---
drivers/soc/renesas/Kconfig | 5 +++++
drivers/soc/renesas/renesas-soc.c | 20 +++++++++++++++++++-
2 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 5deca747fb77..78d656d7699f 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -344,6 +344,11 @@ config ARCH_R9A09G011
help
This enables support for the Renesas RZ/V2M SoC.
+config ARCH_R9A09G057
+ bool "ARM64 Platform support for RZ/V2H{P}"
+ help
+ This enables support for the Renesas RZ/V2H{P} SoC variants.
+
endif # ARM64
if RISCV
diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c
index 8f9b8d3736dc..499d120f9978 100644
--- a/drivers/soc/renesas/renesas-soc.c
+++ b/drivers/soc/renesas/renesas-soc.c
@@ -75,6 +75,10 @@ static const struct renesas_family fam_rzg3s __initconst __maybe_unused = {
.name = "RZ/G3S",
};
+static const struct renesas_family fam_rzv2h __initconst __maybe_unused = {
+ .name = "RZ/V2H",
+};
+
static const struct renesas_family fam_rzv2l __initconst __maybe_unused = {
.name = "RZ/V2L",
};
@@ -177,6 +181,11 @@ static const struct renesas_soc soc_rz_g3s __initconst __maybe_unused = {
.id = 0x85e0447,
};
+static const struct renesas_soc soc_rz_v2h __initconst __maybe_unused = {
+ .family = &fam_rzv2h,
+ .id = 0x847A447,
+};
+
static const struct renesas_soc soc_rz_v2l __initconst __maybe_unused = {
.family = &fam_rzv2l,
.id = 0x8447447,
@@ -407,6 +416,9 @@ static const struct of_device_id renesas_socs[] __initconst __maybe_unused = {
#ifdef CONFIG_ARCH_R9A09G011
{ .compatible = "renesas,r9a09g011", .data = &soc_rz_v2m },
#endif
+#ifdef CONFIG_ARCH_R9A09G057
+ { .compatible = "renesas,r9a09g057", .data = &soc_rz_v2h },
+#endif
#ifdef CONFIG_ARCH_SH73A0
{ .compatible = "renesas,sh73a0", .data = &soc_shmobile_ag5 },
#endif
@@ -432,6 +444,11 @@ static const struct renesas_id id_rzg2l __initconst = {
.mask = 0xfffffff,
};
+static const struct renesas_id id_rzv2h __initconst = {
+ .offset = 0x304,
+ .mask = 0xfffffff,
+};
+
static const struct renesas_id id_rzv2m __initconst = {
.offset = 0x104,
.mask = 0xff,
@@ -449,6 +466,7 @@ static const struct of_device_id renesas_ids[] __initconst = {
{ .compatible = "renesas,r9a07g054-sysc", .data = &id_rzg2l },
{ .compatible = "renesas,r9a08g045-sysc", .data = &id_rzg2l },
{ .compatible = "renesas,r9a09g011-sys", .data = &id_rzv2m },
+ { .compatible = "renesas,r9a09g057-sys", .data = &id_rzv2h },
{ .compatible = "renesas,prr", .data = &id_prr },
{ /* sentinel */ }
};
@@ -513,7 +531,7 @@ static int __init renesas_soc_init(void)
eslo = product & 0xf;
soc_dev_attr->revision = kasprintf(GFP_KERNEL, "ES%u.%u",
eshi, eslo);
- } else if (id == &id_rzg2l) {
+ } else if (id == &id_rzg2l || id == &id_rzv2h) {
eshi = ((product >> 28) & 0x0f);
soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%u",
eshi);
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 4/4] arm64: defconfig: Enable R9A09G057 SoC
2024-02-19 16:09 [PATCH 0/4] Add new Renesas RZ/V2H SoC Prabhakar
` (2 preceding siblings ...)
2024-02-19 16:09 ` [PATCH 3/4] soc: renesas: Add identification support for RZ/V2H SoC Prabhakar
@ 2024-02-19 16:09 ` Prabhakar
2024-02-26 13:43 ` Geert Uytterhoeven
3 siblings, 1 reply; 17+ messages in thread
From: Prabhakar @ 2024-02-19 16:09 UTC (permalink / raw)
To: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Catalin Marinas, Will Deacon
Cc: linux-arm-kernel, linux-renesas-soc, devicetree, linux-kernel,
Prabhakar, Fabrizio Castro, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Enable support for the Renesas RZ/V2H (R9A09G057) SoC in the ARM64
defconfig.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index f9cc5bff157c..5d51ab7d14a3 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1387,6 +1387,7 @@ CONFIG_ARCH_R9A07G044=y
CONFIG_ARCH_R9A07G054=y
CONFIG_ARCH_R9A08G045=y
CONFIG_ARCH_R9A09G011=y
+CONFIG_ARCH_R9A09G057=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_ARCH_TEGRA_132_SOC=y
CONFIG_ARCH_TEGRA_210_SOC=y
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH 1/4] dt-bindings: soc: renesas: Document Renesas RZ/V2H{P} SoC variants
2024-02-19 16:09 ` [PATCH 1/4] dt-bindings: soc: renesas: Document Renesas RZ/V2H{P} SoC variants Prabhakar
@ 2024-02-20 9:50 ` Krzysztof Kozlowski
2024-02-26 13:41 ` Geert Uytterhoeven
1 sibling, 0 replies; 17+ messages in thread
From: Krzysztof Kozlowski @ 2024-02-20 9:50 UTC (permalink / raw)
To: Prabhakar, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Catalin Marinas, Will Deacon
Cc: linux-arm-kernel, linux-renesas-soc, devicetree, linux-kernel,
Fabrizio Castro, Lad Prabhakar
On 19/02/2024 17:09, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Document Renesas RZ/V2H{P} (R9A09G057) SoC variants.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> ---
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 2/4] dt-bindings: arm: renesas: Document Renesas RZ/V2H{P} System Controller
2024-02-19 16:09 ` [PATCH 2/4] dt-bindings: arm: renesas: Document Renesas RZ/V2H{P} System Controller Prabhakar
@ 2024-02-20 9:51 ` Krzysztof Kozlowski
2024-02-22 12:44 ` Lad, Prabhakar
2024-02-26 13:41 ` Geert Uytterhoeven
1 sibling, 1 reply; 17+ messages in thread
From: Krzysztof Kozlowski @ 2024-02-20 9:51 UTC (permalink / raw)
To: Prabhakar, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Catalin Marinas, Will Deacon
Cc: linux-arm-kernel, linux-renesas-soc, devicetree, linux-kernel,
Fabrizio Castro, Lad Prabhakar
On 19/02/2024 17:09, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add DT binding documentation for System Controller (SYS) found on
> RZ/V2H{P} ("R9A09G057") SoC's.
>
> SYS block contains the SYS_LSI_DEVID register which can be used to
> retrieve SoC version information.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + extal_clk: extal-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <24000000>;
> + };
Drop the node, not relevant.
> +
> + sys: system-controller@10430000 {
> + compatible = "renesas,r9a09g057-sys";
> + reg = <0x10430000 0x10000>;
> + clocks = <&extal_clk>;
> + resets = <&cpg 1>;
> + };
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 2/4] dt-bindings: arm: renesas: Document Renesas RZ/V2H{P} System Controller
2024-02-20 9:51 ` Krzysztof Kozlowski
@ 2024-02-22 12:44 ` Lad, Prabhakar
0 siblings, 0 replies; 17+ messages in thread
From: Lad, Prabhakar @ 2024-02-22 12:44 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Catalin Marinas, Will Deacon, linux-arm-kernel,
linux-renesas-soc, devicetree, linux-kernel, Fabrizio Castro,
Lad Prabhakar
Hi Krzysztof,
Thank you for the review.
On Tue, Feb 20, 2024 at 9:51 AM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 19/02/2024 17:09, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add DT binding documentation for System Controller (SYS) found on
> > RZ/V2H{P} ("R9A09G057") SoC's.
> >
> > SYS block contains the SYS_LSI_DEVID register which can be used to
> > retrieve SoC version information.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
>
>
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + extal_clk: extal-clk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <24000000>;
> > + };
>
> Drop the node, not relevant.
>
OK, I'll drop the clock node in the next version.
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/4] dt-bindings: soc: renesas: Document Renesas RZ/V2H{P} SoC variants
2024-02-19 16:09 ` [PATCH 1/4] dt-bindings: soc: renesas: Document Renesas RZ/V2H{P} SoC variants Prabhakar
2024-02-20 9:50 ` Krzysztof Kozlowski
@ 2024-02-26 13:41 ` Geert Uytterhoeven
2024-02-26 13:55 ` Lad, Prabhakar
1 sibling, 1 reply; 17+ messages in thread
From: Geert Uytterhoeven @ 2024-02-26 13:41 UTC (permalink / raw)
To: Prabhakar
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Catalin Marinas, Will Deacon, linux-arm-kernel,
linux-renesas-soc, devicetree, linux-kernel, Fabrizio Castro,
Lad Prabhakar
Hi Prabhakar,
Thanks for your patch!
On Mon, Feb 19, 2024 at 5:10 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Document Renesas RZ/V2H{P} (R9A09G057) SoC variants.
I think "RZ/V2H(P)" would be better, as curly braces are usually used
to group multiple values (e.g. "RZ/G2{L,LC}").
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> ---
> .../devicetree/bindings/soc/renesas/renesas.yaml | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> index c1ce4da2dc32..109fbc8d48db 100644
> --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> @@ -513,6 +513,14 @@ properties:
> - renesas,rzv2mevk2 # RZ/V2M Eval Board v2.0
> - const: renesas,r9a09g011
>
> + - description: RZ/V2H{P} (R9A09G057)
RZ/V2H(P)
> + items:
> + - enum:
> + - renesas,r9a09g057h41 # RZ/V2H
> + - renesas,r9a09g057h42 # RZ/V2H with Mali-G31 support
> + - renesas,r9a09g057h44 # RZ/V2HP with Mali-G31 + Mali-C55 support
> + - const: renesas,r9a09g057
> +
> additionalProperties: true
The rest LGTM, so
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 2/4] dt-bindings: arm: renesas: Document Renesas RZ/V2H{P} System Controller
2024-02-19 16:09 ` [PATCH 2/4] dt-bindings: arm: renesas: Document Renesas RZ/V2H{P} System Controller Prabhakar
2024-02-20 9:51 ` Krzysztof Kozlowski
@ 2024-02-26 13:41 ` Geert Uytterhoeven
2024-02-26 14:00 ` Lad, Prabhakar
1 sibling, 1 reply; 17+ messages in thread
From: Geert Uytterhoeven @ 2024-02-26 13:41 UTC (permalink / raw)
To: Prabhakar
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Catalin Marinas, Will Deacon, linux-arm-kernel,
linux-renesas-soc, devicetree, linux-kernel, Fabrizio Castro,
Lad Prabhakar
Hi Prabhakar,
Thanks for your patch!
On Mon, Feb 19, 2024 at 5:10 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add DT binding documentation for System Controller (SYS) found on
> RZ/V2H{P} ("R9A09G057") SoC's.
RZ/V2H(P)
>
> SYS block contains the SYS_LSI_DEVID register which can be used to
> retrieve SoC version information.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml
> @@ -0,0 +1,59 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/renesas/renesas,r9a09g057-sys.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/V2H{P} System Controller (SYS)
> +
> +maintainers:
> + - Geert Uytterhoeven <geert+renesas@glider.be>
> +
> +description:
> + The RZ/V2H{P} SYS (System Controller) controls the overall
RZ/V2H(P)
> + configuration of the LSI and supports the following functions,
> + - Trust zone control
> + - Extend access by specific masters to address beyond 4GB space
> + - GBETH configuration
> + - Control of settings and states of SRAM/PCIe/CM33/CA55/CR8/xSPI/ADC/TSU
> + - LSI version
> + - WDT stop control
> + - General registers
> +
> +properties:
> + compatible:
> + const: renesas,r9a09g057-sys
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: Clock from external oscillator
Isn't this SYS_0_PCLK inside the CPG?
> +
> + resets:
> + items:
> + - description: SYS_0_PRESETN reset signal
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - resets
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + extal_clk: extal-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <24000000>;
> + };
> +
> + sys: system-controller@10430000 {
> + compatible = "renesas,r9a09g057-sys";
> + reg = <0x10430000 0x10000>;
> + clocks = <&extal_clk>;
clocks = <&cpg 1>;
(I guess it will be 1 ;-)
> + resets = <&cpg 1>;
> + };
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 3/4] soc: renesas: Add identification support for RZ/V2H SoC
2024-02-19 16:09 ` [PATCH 3/4] soc: renesas: Add identification support for RZ/V2H SoC Prabhakar
@ 2024-02-26 13:42 ` Geert Uytterhoeven
2024-02-26 14:01 ` Lad, Prabhakar
0 siblings, 1 reply; 17+ messages in thread
From: Geert Uytterhoeven @ 2024-02-26 13:42 UTC (permalink / raw)
To: Prabhakar
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Catalin Marinas, Will Deacon, linux-arm-kernel,
linux-renesas-soc, devicetree, linux-kernel, Fabrizio Castro,
Lad Prabhakar
Hi Prabhakar,
On Mon, Feb 19, 2024 at 5:10 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Add support to identify the RZ/V2H (R9A09G057) SoC.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Thanks for your patch!
> --- a/drivers/soc/renesas/Kconfig
> +++ b/drivers/soc/renesas/Kconfig
> @@ -344,6 +344,11 @@ config ARCH_R9A09G011
> help
> This enables support for the Renesas RZ/V2M SoC.
>
> +config ARCH_R9A09G057
> + bool "ARM64 Platform support for RZ/V2H{P}"
> + help
> + This enables support for the Renesas RZ/V2H{P} SoC variants.
"RZ/V2H(P)" (everywhere).
> +
> endif # ARM64
> --- a/drivers/soc/renesas/renesas-soc.c
> +++ b/drivers/soc/renesas/renesas-soc.c
> @@ -177,6 +181,11 @@ static const struct renesas_soc soc_rz_g3s __initconst __maybe_unused = {
> .id = 0x85e0447,
> };
>
> +static const struct renesas_soc soc_rz_v2h __initconst __maybe_unused = {
> + .family = &fam_rzv2h,
> + .id = 0x847A447,
Lower case hex please.
> +};
The rest LGTM.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 4/4] arm64: defconfig: Enable R9A09G057 SoC
2024-02-19 16:09 ` [PATCH 4/4] arm64: defconfig: Enable R9A09G057 SoC Prabhakar
@ 2024-02-26 13:43 ` Geert Uytterhoeven
0 siblings, 0 replies; 17+ messages in thread
From: Geert Uytterhoeven @ 2024-02-26 13:43 UTC (permalink / raw)
To: Prabhakar
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Catalin Marinas, Will Deacon, linux-arm-kernel,
linux-renesas-soc, devicetree, linux-kernel, Fabrizio Castro,
Lad Prabhakar
On Mon, Feb 19, 2024 at 5:10 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Enable support for the Renesas RZ/V2H (R9A09G057) SoC in the ARM64
> defconfig.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/4] dt-bindings: soc: renesas: Document Renesas RZ/V2H{P} SoC variants
2024-02-26 13:41 ` Geert Uytterhoeven
@ 2024-02-26 13:55 ` Lad, Prabhakar
0 siblings, 0 replies; 17+ messages in thread
From: Lad, Prabhakar @ 2024-02-26 13:55 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Catalin Marinas, Will Deacon, linux-arm-kernel,
linux-renesas-soc, devicetree, linux-kernel, Fabrizio Castro,
Lad Prabhakar
Hi Geert,
Thank you for the review.
On Mon, Feb 26, 2024 at 1:41 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> Thanks for your patch!
>
> On Mon, Feb 19, 2024 at 5:10 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Document Renesas RZ/V2H{P} (R9A09G057) SoC variants.
>
> I think "RZ/V2H(P)" would be better, as curly braces are usually used
> to group multiple values (e.g. "RZ/G2{L,LC}").
>
Agreed, I will use "RZ/V2H(P)" (here and in rest of the other patches)
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> > ---
> > .../devicetree/bindings/soc/renesas/renesas.yaml | 8 ++++++++
> > 1 file changed, 8 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> > index c1ce4da2dc32..109fbc8d48db 100644
> > --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> > +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> > @@ -513,6 +513,14 @@ properties:
> > - renesas,rzv2mevk2 # RZ/V2M Eval Board v2.0
> > - const: renesas,r9a09g011
> >
> > + - description: RZ/V2H{P} (R9A09G057)
>
> RZ/V2H(P)
>
OK.
Cheers,
Prabhakar
> > + items:
> > + - enum:
> > + - renesas,r9a09g057h41 # RZ/V2H
> > + - renesas,r9a09g057h42 # RZ/V2H with Mali-G31 support
> > + - renesas,r9a09g057h44 # RZ/V2HP with Mali-G31 + Mali-C55 support
> > + - const: renesas,r9a09g057
> > +
> > additionalProperties: true
>
> The rest LGTM, so
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> Gr{oetje,eeting}s,
>
> Geert
>
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 2/4] dt-bindings: arm: renesas: Document Renesas RZ/V2H{P} System Controller
2024-02-26 13:41 ` Geert Uytterhoeven
@ 2024-02-26 14:00 ` Lad, Prabhakar
2024-02-26 15:14 ` Geert Uytterhoeven
0 siblings, 1 reply; 17+ messages in thread
From: Lad, Prabhakar @ 2024-02-26 14:00 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Catalin Marinas, Will Deacon, linux-arm-kernel,
linux-renesas-soc, devicetree, linux-kernel, Fabrizio Castro,
Lad Prabhakar
Hi Geert,
Thank you for the review.
On Mon, Feb 26, 2024 at 1:41 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> Thanks for your patch!
>
> On Mon, Feb 19, 2024 at 5:10 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add DT binding documentation for System Controller (SYS) found on
> > RZ/V2H{P} ("R9A09G057") SoC's.
>
> RZ/V2H(P)
>
> >
> > SYS block contains the SYS_LSI_DEVID register which can be used to
> > retrieve SoC version information.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
>
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml
> > @@ -0,0 +1,59 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/soc/renesas/renesas,r9a09g057-sys.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Renesas RZ/V2H{P} System Controller (SYS)
> > +
> > +maintainers:
> > + - Geert Uytterhoeven <geert+renesas@glider.be>
> > +
> > +description:
> > + The RZ/V2H{P} SYS (System Controller) controls the overall
>
> RZ/V2H(P)
>
OK.
> > + configuration of the LSI and supports the following functions,
> > + - Trust zone control
> > + - Extend access by specific masters to address beyond 4GB space
> > + - GBETH configuration
> > + - Control of settings and states of SRAM/PCIe/CM33/CA55/CR8/xSPI/ADC/TSU
> > + - LSI version
> > + - WDT stop control
> > + - General registers
> > +
> > +properties:
> > + compatible:
> > + const: renesas,r9a09g057-sys
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + clocks:
> > + items:
> > + - description: Clock from external oscillator
>
> Isn't this SYS_0_PCLK inside the CPG?
>
As per the block diagram (figure 4.4-3), if we follow the clock source
for SYS it traces back to 24MHz Oscillator. Let me know how you want
me to describe this please.
> > +
> > + resets:
> > + items:
> > + - description: SYS_0_PRESETN reset signal
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - clocks
> > + - resets
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + extal_clk: extal-clk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <24000000>;
> > + };
> > +
> > + sys: system-controller@10430000 {
> > + compatible = "renesas,r9a09g057-sys";
> > + reg = <0x10430000 0x10000>;
> > + clocks = <&extal_clk>;
>
> clocks = <&cpg 1>;
>
> (I guess it will be 1 ;-)
>
Yep indeed ;)
Cheers,
Prabhakar
> > + resets = <&cpg 1>;
> > + };
>
> Gr{oetje,eeting}s,
>
> Geert
>
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 3/4] soc: renesas: Add identification support for RZ/V2H SoC
2024-02-26 13:42 ` Geert Uytterhoeven
@ 2024-02-26 14:01 ` Lad, Prabhakar
0 siblings, 0 replies; 17+ messages in thread
From: Lad, Prabhakar @ 2024-02-26 14:01 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Catalin Marinas, Will Deacon, linux-arm-kernel,
linux-renesas-soc, devicetree, linux-kernel, Fabrizio Castro,
Lad Prabhakar
Hi Geert,
Thank you for the review.
On Mon, Feb 26, 2024 at 1:43 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Mon, Feb 19, 2024 at 5:10 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Add support to identify the RZ/V2H (R9A09G057) SoC.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
>
> Thanks for your patch!
>
> > --- a/drivers/soc/renesas/Kconfig
> > +++ b/drivers/soc/renesas/Kconfig
> > @@ -344,6 +344,11 @@ config ARCH_R9A09G011
> > help
> > This enables support for the Renesas RZ/V2M SoC.
> >
> > +config ARCH_R9A09G057
> > + bool "ARM64 Platform support for RZ/V2H{P}"
> > + help
> > + This enables support for the Renesas RZ/V2H{P} SoC variants.
>
> "RZ/V2H(P)" (everywhere).
>
OK.
> > +
> > endif # ARM64
>
> > --- a/drivers/soc/renesas/renesas-soc.c
> > +++ b/drivers/soc/renesas/renesas-soc.c
>
> > @@ -177,6 +181,11 @@ static const struct renesas_soc soc_rz_g3s __initconst __maybe_unused = {
> > .id = 0x85e0447,
> > };
> >
> > +static const struct renesas_soc soc_rz_v2h __initconst __maybe_unused = {
> > + .family = &fam_rzv2h,
> > + .id = 0x847A447,
>
> Lower case hex please.
>
sure, I will update this in v2.
Cheers,
Prabhakar
> > +};
>
> The rest LGTM.
>
> Gr{oetje,eeting}s,
>
> Geert
>
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 2/4] dt-bindings: arm: renesas: Document Renesas RZ/V2H{P} System Controller
2024-02-26 14:00 ` Lad, Prabhakar
@ 2024-02-26 15:14 ` Geert Uytterhoeven
2024-02-26 16:00 ` Lad, Prabhakar
0 siblings, 1 reply; 17+ messages in thread
From: Geert Uytterhoeven @ 2024-02-26 15:14 UTC (permalink / raw)
To: Lad, Prabhakar
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Catalin Marinas, Will Deacon, linux-arm-kernel,
linux-renesas-soc, devicetree, linux-kernel, Fabrizio Castro,
Lad Prabhakar
Hi Prabhakar,
On Mon, Feb 26, 2024 at 3:01 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Mon, Feb 26, 2024 at 1:41 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Mon, Feb 19, 2024 at 5:10 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml
> > > + clocks:
> > > + items:
> > > + - description: Clock from external oscillator
> >
> > Isn't this SYS_0_PCLK inside the CPG?
> >
> As per the block diagram (figure 4.4-3), if we follow the clock source
> for SYS it traces back to 24MHz Oscillator. Let me know how you want
> me to describe this please.
Yes, that is the diagram I was looking at.
MAIN OSC 24 MHz -> MAINCLK -> SYS_0_PCLK.
MAIN OSC 24 MHz is a clock input to the CPG.
MAINCLK is a CPG internal core clock.
SYS_0_PCLK is a CPG clock output, serving as the SYS module clock.
I think the standard "maxItems: 1" would be fine, and no description
is needed.
> > > +
> > > + resets:
> > > + items:
> > > + - description: SYS_0_PRESETN reset signal
Same here.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 2/4] dt-bindings: arm: renesas: Document Renesas RZ/V2H{P} System Controller
2024-02-26 15:14 ` Geert Uytterhoeven
@ 2024-02-26 16:00 ` Lad, Prabhakar
0 siblings, 0 replies; 17+ messages in thread
From: Lad, Prabhakar @ 2024-02-26 16:00 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Catalin Marinas, Will Deacon, linux-arm-kernel,
linux-renesas-soc, devicetree, linux-kernel, Fabrizio Castro,
Lad Prabhakar
Hi Geert,
On Mon, Feb 26, 2024 at 3:15 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Mon, Feb 26, 2024 at 3:01 PM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> > On Mon, Feb 26, 2024 at 1:41 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > On Mon, Feb 19, 2024 at 5:10 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml
> > > > + clocks:
> > > > + items:
> > > > + - description: Clock from external oscillator
> > >
> > > Isn't this SYS_0_PCLK inside the CPG?
> > >
> > As per the block diagram (figure 4.4-3), if we follow the clock source
> > for SYS it traces back to 24MHz Oscillator. Let me know how you want
> > me to describe this please.
>
> Yes, that is the diagram I was looking at.
> MAIN OSC 24 MHz -> MAINCLK -> SYS_0_PCLK.
>
> MAIN OSC 24 MHz is a clock input to the CPG.
> MAINCLK is a CPG internal core clock.
> SYS_0_PCLK is a CPG clock output, serving as the SYS module clock.
>
Agreed.
> I think the standard "maxItems: 1" would be fine, and no description
> is needed.
>
OK, makes sense.
> > > > +
> > > > + resets:
> > > > + items:
> > > > + - description: SYS_0_PRESETN reset signal
>
> Same here.
>
Ok.
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2024-02-26 16:01 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-02-19 16:09 [PATCH 0/4] Add new Renesas RZ/V2H SoC Prabhakar
2024-02-19 16:09 ` [PATCH 1/4] dt-bindings: soc: renesas: Document Renesas RZ/V2H{P} SoC variants Prabhakar
2024-02-20 9:50 ` Krzysztof Kozlowski
2024-02-26 13:41 ` Geert Uytterhoeven
2024-02-26 13:55 ` Lad, Prabhakar
2024-02-19 16:09 ` [PATCH 2/4] dt-bindings: arm: renesas: Document Renesas RZ/V2H{P} System Controller Prabhakar
2024-02-20 9:51 ` Krzysztof Kozlowski
2024-02-22 12:44 ` Lad, Prabhakar
2024-02-26 13:41 ` Geert Uytterhoeven
2024-02-26 14:00 ` Lad, Prabhakar
2024-02-26 15:14 ` Geert Uytterhoeven
2024-02-26 16:00 ` Lad, Prabhakar
2024-02-19 16:09 ` [PATCH 3/4] soc: renesas: Add identification support for RZ/V2H SoC Prabhakar
2024-02-26 13:42 ` Geert Uytterhoeven
2024-02-26 14:01 ` Lad, Prabhakar
2024-02-19 16:09 ` [PATCH 4/4] arm64: defconfig: Enable R9A09G057 SoC Prabhakar
2024-02-26 13:43 ` Geert Uytterhoeven
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