From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
To: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Rob Herring <robh+dt@kernel.org>,
Fabrizio Castro <fabrizio.castro.jz@renesas.com>,
Wolfgang Grandegger <wg@grandegger.com>,
Marc Kleine-Budde <mkl@pengutronix.de>,
"David S. Miller" <davem@davemloft.net>,
Jakub Kicinski <kuba@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
linux-can@vger.kernel.org, netdev <netdev@vger.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>,
linux-clk <linux-clk@vger.kernel.org>,
LKML <linux-kernel@vger.kernel.org>,
Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH v2 2/5] can: rcar_canfd: Add support for RZ/G2L family
Date: Tue, 20 Jul 2021 15:57:40 +0100 [thread overview]
Message-ID: <CA+V-a8vgQ1-tUOw2o3E39reZmnLGFVN_HEvZeH-x5cj01x-Pzg@mail.gmail.com> (raw)
In-Reply-To: <c8ec5fe0c8eb86898416edb7c68dcf0eeeaccf54.camel@pengutronix.de>
Hi Philipp,
Thank you for the review.
On Tue, Jul 20, 2021 at 11:23 AM Philipp Zabel <p.zabel@pengutronix.de> wrote:
>
> On Mon, 2021-07-19 at 15:38 +0100, Lad Prabhakar wrote:
> > CANFD block on RZ/G2L SoC is almost identical to one found on
> > R-Car Gen3 SoC's. On RZ/G2L SoC interrupt sources for each channel
> > are split into different sources and the IP doesn't divide (1/2)
> > CANFD clock within the IP.
> >
> > This patch adds compatible string for RZ/G2L family and registers
> > the irq handlers required for CANFD operation. IRQ numbers are now
> > fetched based on names instead of indices. For backward compatibility
> > on non RZ/G2L SoC's we fallback reading based on indices.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > drivers/net/can/rcar/rcar_canfd.c | 178 ++++++++++++++++++++++++------
> > 1 file changed, 147 insertions(+), 31 deletions(-)
> >
> > diff --git a/drivers/net/can/rcar/rcar_canfd.c b/drivers/net/can/rcar/rcar_canfd.c
> > index 311e6ca3bdc4..d4affc002fb3 100644
> > --- a/drivers/net/can/rcar/rcar_canfd.c
> > +++ b/drivers/net/can/rcar/rcar_canfd.c
> > @@ -37,9 +37,15 @@
> [...]
> > + if (gpriv->chip_id == RENESAS_RZG2L) {
> > + gpriv->rstc1 = devm_reset_control_get_exclusive_by_index(&pdev->dev, 0);
> > + if (IS_ERR(gpriv->rstc1)) {
> > + dev_err(&pdev->dev, "failed to get reset index 0\n");
>
> Please consider requesting the reset controls by name instead of by
> index. See also my reply to the binding patch.
>
Will do.
> > + return PTR_ERR(gpriv->rstc1);
> > + }
> > +
> > + err = reset_control_reset(gpriv->rstc1);
> > + if (err)
> > + return err;
>
> I suggest to wait until after all resource requests have succeeded
> before triggering the resets, i.e. first get all reset controls and
> clocks, etc., and only then trigger resets, enable clocks, and so on.
>
> That way there will be no spurious resets in case of probe deferrals.
>
Agreed, will update the code.
Cheers,
Prabhakar
> regards
> Philipp
next prev parent reply other threads:[~2021-07-20 15:12 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-19 14:38 [PATCH v2 0/5] Renesas RZ/G2L CANFD support Lad Prabhakar
2021-07-19 14:38 ` [PATCH v2 1/5] dt-bindings: net: can: renesas,rcar-canfd: Document RZ/G2L SoC Lad Prabhakar
2021-07-20 10:20 ` Geert Uytterhoeven
2021-07-20 14:37 ` Lad, Prabhakar
2021-07-20 10:22 ` Philipp Zabel
2021-07-20 14:31 ` Lad, Prabhakar
2021-07-20 15:11 ` Geert Uytterhoeven
2021-07-20 15:56 ` Lad, Prabhakar
2021-07-20 16:33 ` Philipp Zabel
2021-07-20 16:33 ` Philipp Zabel
2021-07-19 14:38 ` [PATCH v2 2/5] can: rcar_canfd: Add support for RZ/G2L family Lad Prabhakar
2021-07-20 10:23 ` Philipp Zabel
2021-07-20 14:57 ` Lad, Prabhakar [this message]
2021-07-20 10:30 ` Geert Uytterhoeven
2021-07-20 15:15 ` Lad, Prabhakar
2021-07-19 14:38 ` [PATCH v2 3/5] dt-bindings: clk: r9a07g044-cpg: Add entry for P0_DIV2 core clock Lad Prabhakar
2021-07-20 10:39 ` Geert Uytterhoeven
2021-07-19 14:38 ` [PATCH v2 4/5] clk: renesas: r9a07g044-cpg: Add entry for fixed clock P0_DIV2 Lad Prabhakar
2021-07-20 10:39 ` Geert Uytterhoeven
2021-07-19 14:38 ` [PATCH v2 5/5] arm64: dts: renesas: r9a07g044: Add CANFD node Lad Prabhakar
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